1 /** 2 ****************************************************************************** 3 * @file ism330dhcx_reg.h 4 * @author Sensor Solutions Software Team 5 * @brief This file contains all the functions prototypes for the 6 * ism330dhcx_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef ISM330DHCX_REGS_H 23 #define ISM330DHCX_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup ISM330DHCX 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 /* #define DRV_BYTE_ORDER DRV_BIG_ENDIAN */ 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup ISM330DHCX Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ 172 #define ISM330DHCX_I2C_ADD_L 0xD5U 173 #define ISM330DHCX_I2C_ADD_H 0xD7U 174 175 /** Device Identification (Who am I) **/ 176 #define ISM330DHCX_ID 0x6BU 177 178 /** 179 * @} 180 * 181 */ 182 183 #define ISM330DHCX_FUNC_CFG_ACCESS 0x01U 184 typedef struct 185 { 186 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 187 uint8_t not_used_01 : 6; 188 uint8_t reg_access : 2; /* shub_reg_access + func_cfg_access */ 189 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 190 uint8_t reg_access : 2; /* shub_reg_access + func_cfg_access */ 191 uint8_t not_used_01 : 6; 192 #endif /* DRV_BYTE_ORDER */ 193 } ism330dhcx_func_cfg_access_t; 194 195 #define ISM330DHCX_PIN_CTRL 0x02U 196 typedef struct 197 { 198 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 199 uint8_t not_used_01 : 6; 200 uint8_t sdo_pu_en : 1; 201 uint8_t ois_pu_dis : 1; 202 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 203 uint8_t ois_pu_dis : 1; 204 uint8_t sdo_pu_en : 1; 205 uint8_t not_used_01 : 6; 206 #endif /* DRV_BYTE_ORDER */ 207 } ism330dhcx_pin_ctrl_t; 208 209 #define ISM330DHCX_FIFO_CTRL1 0x07U 210 typedef struct 211 { 212 uint8_t wtm : 8; 213 } ism330dhcx_fifo_ctrl1_t; 214 215 #define ISM330DHCX_FIFO_CTRL2 0x08U 216 typedef struct 217 { 218 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 219 uint8_t wtm : 1; 220 uint8_t uncoptr_rate : 2; 221 uint8_t not_used_01 : 1; 222 uint8_t odrchg_en : 1; 223 uint8_t not_used_02 : 1; 224 uint8_t fifo_compr_rt_en : 1; 225 uint8_t stop_on_wtm : 1; 226 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 227 uint8_t stop_on_wtm : 1; 228 uint8_t fifo_compr_rt_en : 1; 229 uint8_t not_used_02 : 1; 230 uint8_t odrchg_en : 1; 231 uint8_t not_used_01 : 1; 232 uint8_t uncoptr_rate : 2; 233 uint8_t wtm : 1; 234 #endif /* DRV_BYTE_ORDER */ 235 } ism330dhcx_fifo_ctrl2_t; 236 237 #define ISM330DHCX_FIFO_CTRL3 0x09U 238 typedef struct 239 { 240 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 241 uint8_t bdr_xl : 4; 242 uint8_t bdr_gy : 4; 243 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 244 uint8_t bdr_gy : 4; 245 uint8_t bdr_xl : 4; 246 #endif /* DRV_BYTE_ORDER */ 247 } ism330dhcx_fifo_ctrl3_t; 248 249 #define ISM330DHCX_FIFO_CTRL4 0x0AU 250 typedef struct 251 { 252 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 253 uint8_t fifo_mode : 3; 254 uint8_t not_used_01 : 1; 255 uint8_t odr_t_batch : 2; 256 uint8_t odr_ts_batch : 2; 257 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 258 uint8_t odr_ts_batch : 2; 259 uint8_t odr_t_batch : 2; 260 uint8_t not_used_01 : 1; 261 uint8_t fifo_mode : 3; 262 #endif /* DRV_BYTE_ORDER */ 263 } ism330dhcx_fifo_ctrl4_t; 264 265 #define ISM330DHCX_COUNTER_BDR_REG1 0x0BU 266 typedef struct 267 { 268 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 269 uint8_t cnt_bdr_th : 3; 270 uint8_t not_used_01 : 2; 271 uint8_t trig_counter_bdr : 1; 272 uint8_t rst_counter_bdr : 1; 273 uint8_t dataready_pulsed : 1; 274 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 275 uint8_t dataready_pulsed : 1; 276 uint8_t rst_counter_bdr : 1; 277 uint8_t trig_counter_bdr : 1; 278 uint8_t not_used_01 : 2; 279 uint8_t cnt_bdr_th : 3; 280 #endif /* DRV_BYTE_ORDER */ 281 } ism330dhcx_counter_bdr_reg1_t; 282 283 #define ISM330DHCX_COUNTER_BDR_REG2 0x0CU 284 typedef struct 285 { 286 uint8_t cnt_bdr_th : 8; 287 } ism330dhcx_counter_bdr_reg2_t; 288 289 #define ISM330DHCX_INT1_CTRL 0x0DU 290 typedef struct 291 { 292 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 293 uint8_t int1_drdy_xl : 1; 294 uint8_t int1_drdy_g : 1; 295 uint8_t int1_boot : 1; 296 uint8_t int1_fifo_th : 1; 297 uint8_t int1_fifo_ovr : 1; 298 uint8_t int1_fifo_full : 1; 299 uint8_t int1_cnt_bdr : 1; 300 uint8_t den_drdy_flag : 1; 301 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 302 uint8_t den_drdy_flag : 1; 303 uint8_t int1_cnt_bdr : 1; 304 uint8_t int1_fifo_full : 1; 305 uint8_t int1_fifo_ovr : 1; 306 uint8_t int1_fifo_th : 1; 307 uint8_t int1_boot : 1; 308 uint8_t int1_drdy_g : 1; 309 uint8_t int1_drdy_xl : 1; 310 #endif /* DRV_BYTE_ORDER */ 311 } ism330dhcx_int1_ctrl_t; 312 313 #define ISM330DHCX_INT2_CTRL 0x0EU 314 typedef struct 315 { 316 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 317 uint8_t int2_drdy_xl : 1; 318 uint8_t int2_drdy_g : 1; 319 uint8_t int2_drdy_temp : 1; 320 uint8_t int2_fifo_th : 1; 321 uint8_t int2_fifo_ovr : 1; 322 uint8_t int2_fifo_full : 1; 323 uint8_t int2_cnt_bdr : 1; 324 uint8_t not_used_01 : 1; 325 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 326 uint8_t not_used_01 : 1; 327 uint8_t int2_cnt_bdr : 1; 328 uint8_t int2_fifo_full : 1; 329 uint8_t int2_fifo_ovr : 1; 330 uint8_t int2_fifo_th : 1; 331 uint8_t int2_drdy_temp : 1; 332 uint8_t int2_drdy_g : 1; 333 uint8_t int2_drdy_xl : 1; 334 #endif /* DRV_BYTE_ORDER */ 335 } ism330dhcx_int2_ctrl_t; 336 337 #define ISM330DHCX_WHO_AM_I 0x0FU 338 #define ISM330DHCX_CTRL1_XL 0x10U 339 typedef struct 340 { 341 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 342 uint8_t not_used_01 : 1; 343 uint8_t lpf2_xl_en : 1; 344 uint8_t fs_xl : 2; 345 uint8_t odr_xl : 4; 346 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 347 uint8_t odr_xl : 4; 348 uint8_t fs_xl : 2; 349 uint8_t lpf2_xl_en : 1; 350 uint8_t not_used_01 : 1; 351 #endif /* DRV_BYTE_ORDER */ 352 } ism330dhcx_ctrl1_xl_t; 353 354 #define ISM330DHCX_CTRL2_G 0x11U 355 typedef struct 356 { 357 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 358 uint8_t fs_g : 4; /* fs_4000 + fs_125 + fs_g */ 359 uint8_t odr_g : 4; 360 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 361 uint8_t odr_g : 4; 362 uint8_t fs_g : 4; /* fs_4000 + fs_125 + fs_g */ 363 #endif /* DRV_BYTE_ORDER */ 364 } ism330dhcx_ctrl2_g_t; 365 366 #define ISM330DHCX_CTRL3_C 0x12U 367 typedef struct 368 { 369 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 370 uint8_t sw_reset : 1; 371 uint8_t not_used_01 : 1; 372 uint8_t if_inc : 1; 373 uint8_t sim : 1; 374 uint8_t pp_od : 1; 375 uint8_t h_lactive : 1; 376 uint8_t bdu : 1; 377 uint8_t boot : 1; 378 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 379 uint8_t boot : 1; 380 uint8_t bdu : 1; 381 uint8_t h_lactive : 1; 382 uint8_t pp_od : 1; 383 uint8_t sim : 1; 384 uint8_t if_inc : 1; 385 uint8_t not_used_01 : 1; 386 uint8_t sw_reset : 1; 387 #endif /* DRV_BYTE_ORDER */ 388 } ism330dhcx_ctrl3_c_t; 389 390 #define ISM330DHCX_CTRL4_C 0x13U 391 typedef struct 392 { 393 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 394 uint8_t not_used_01 : 1; 395 uint8_t lpf1_sel_g : 1; 396 uint8_t i2c_disable : 1; 397 uint8_t drdy_mask : 1; 398 uint8_t not_used_02 : 1; 399 uint8_t int2_on_int1 : 1; 400 uint8_t sleep_g : 1; 401 uint8_t not_used_03 : 1; 402 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 403 uint8_t not_used_03 : 1; 404 uint8_t sleep_g : 1; 405 uint8_t int2_on_int1 : 1; 406 uint8_t not_used_02 : 1; 407 uint8_t drdy_mask : 1; 408 uint8_t i2c_disable : 1; 409 uint8_t lpf1_sel_g : 1; 410 uint8_t not_used_01 : 1; 411 #endif /* DRV_BYTE_ORDER */ 412 } ism330dhcx_ctrl4_c_t; 413 414 #define ISM330DHCX_CTRL5_C 0x14U 415 typedef struct 416 { 417 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 418 uint8_t st_xl : 2; 419 uint8_t st_g : 2; 420 uint8_t not_used_01 : 1; 421 uint8_t rounding : 2; 422 uint8_t not_used_02 : 1; 423 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 424 uint8_t not_used_02 : 1; 425 uint8_t rounding : 2; 426 uint8_t not_used_01 : 1; 427 uint8_t st_g : 2; 428 uint8_t st_xl : 2; 429 #endif /* DRV_BYTE_ORDER */ 430 } ism330dhcx_ctrl5_c_t; 431 432 #define ISM330DHCX_CTRL6_C 0x15U 433 typedef struct 434 { 435 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 436 uint8_t ftype : 3; 437 uint8_t usr_off_w : 1; 438 uint8_t xl_hm_mode : 1; 439 uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */ 440 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 441 uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */ 442 uint8_t xl_hm_mode : 1; 443 uint8_t usr_off_w : 1; 444 uint8_t ftype : 3; 445 #endif /* DRV_BYTE_ORDER */ 446 } ism330dhcx_ctrl6_c_t; 447 448 #define ISM330DHCX_CTRL7_G 0x16U 449 typedef struct 450 { 451 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 452 uint8_t ois_on : 1; 453 uint8_t usr_off_on_out : 1; 454 uint8_t ois_on_en : 1; 455 uint8_t not_used_01 : 1; 456 uint8_t hpm_g : 2; 457 uint8_t hp_en_g : 1; 458 uint8_t g_hm_mode : 1; 459 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 460 uint8_t g_hm_mode : 1; 461 uint8_t hp_en_g : 1; 462 uint8_t hpm_g : 2; 463 uint8_t not_used_01 : 1; 464 uint8_t ois_on_en : 1; 465 uint8_t usr_off_on_out : 1; 466 uint8_t ois_on : 1; 467 #endif /* DRV_BYTE_ORDER */ 468 } ism330dhcx_ctrl7_g_t; 469 470 #define ISM330DHCX_CTRL8_XL 0x17U 471 typedef struct 472 { 473 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 474 uint8_t low_pass_on_6d : 1; 475 uint8_t not_used_01 : 1; 476 uint8_t hp_slope_xl_en : 1; 477 uint8_t fastsettl_mode_xl : 1; 478 uint8_t hp_ref_mode_xl : 1; 479 uint8_t hpcf_xl : 3; 480 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 481 uint8_t hpcf_xl : 3; 482 uint8_t hp_ref_mode_xl : 1; 483 uint8_t fastsettl_mode_xl : 1; 484 uint8_t hp_slope_xl_en : 1; 485 uint8_t not_used_01 : 1; 486 uint8_t low_pass_on_6d : 1; 487 #endif /* DRV_BYTE_ORDER */ 488 } ism330dhcx_ctrl8_xl_t; 489 490 #define ISM330DHCX_CTRL9_XL 0x18U 491 typedef struct 492 { 493 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 494 uint8_t not_used_01 : 1; 495 uint8_t device_conf : 1; 496 uint8_t den_lh : 1; 497 uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */ 498 uint8_t den_z : 1; 499 uint8_t den_y : 1; 500 uint8_t den_x : 1; 501 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 502 uint8_t den_x : 1; 503 uint8_t den_y : 1; 504 uint8_t den_z : 1; 505 uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */ 506 uint8_t den_lh : 1; 507 uint8_t device_conf : 1; 508 uint8_t not_used_01 : 1; 509 #endif /* DRV_BYTE_ORDER */ 510 } ism330dhcx_ctrl9_xl_t; 511 512 #define ISM330DHCX_CTRL10_C 0x19U 513 typedef struct 514 { 515 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 516 uint8_t not_used_01 : 5; 517 uint8_t timestamp_en : 1; 518 uint8_t not_used_02 : 2; 519 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 520 uint8_t not_used_02 : 2; 521 uint8_t timestamp_en : 1; 522 uint8_t not_used_01 : 5; 523 #endif /* DRV_BYTE_ORDER */ 524 } ism330dhcx_ctrl10_c_t; 525 526 #define ISM330DHCX_ALL_INT_SRC 0x1AU 527 typedef struct 528 { 529 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 530 uint8_t ff_ia : 1; 531 uint8_t wu_ia : 1; 532 uint8_t single_tap : 1; 533 uint8_t double_tap : 1; 534 uint8_t d6d_ia : 1; 535 uint8_t sleep_change_ia : 1; 536 uint8_t not_used_01 : 1; 537 uint8_t timestamp_endcount : 1; 538 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 539 uint8_t timestamp_endcount : 1; 540 uint8_t not_used_01 : 1; 541 uint8_t sleep_change_ia : 1; 542 uint8_t d6d_ia : 1; 543 uint8_t double_tap : 1; 544 uint8_t single_tap : 1; 545 uint8_t wu_ia : 1; 546 uint8_t ff_ia : 1; 547 #endif /* DRV_BYTE_ORDER */ 548 } ism330dhcx_all_int_src_t; 549 550 #define ISM330DHCX_WAKE_UP_SRC 0x1BU 551 typedef struct 552 { 553 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 554 uint8_t z_wu : 1; 555 uint8_t y_wu : 1; 556 uint8_t x_wu : 1; 557 uint8_t wu_ia : 1; 558 uint8_t sleep_state : 1; 559 uint8_t ff_ia : 1; 560 uint8_t sleep_change_ia : 1; 561 uint8_t not_used_01 : 1; 562 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 563 uint8_t not_used_01 : 1; 564 uint8_t sleep_change_ia : 1; 565 uint8_t ff_ia : 1; 566 uint8_t sleep_state : 1; 567 uint8_t wu_ia : 1; 568 uint8_t x_wu : 1; 569 uint8_t y_wu : 1; 570 uint8_t z_wu : 1; 571 #endif /* DRV_BYTE_ORDER */ 572 } ism330dhcx_wake_up_src_t; 573 574 #define ISM330DHCX_TAP_SRC 0x1CU 575 typedef struct 576 { 577 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 578 uint8_t z_tap : 1; 579 uint8_t y_tap : 1; 580 uint8_t x_tap : 1; 581 uint8_t tap_sign : 1; 582 uint8_t double_tap : 1; 583 uint8_t single_tap : 1; 584 uint8_t tap_ia : 1; 585 uint8_t not_used_01 : 1; 586 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 587 uint8_t not_used_01 : 1; 588 uint8_t tap_ia : 1; 589 uint8_t single_tap : 1; 590 uint8_t double_tap : 1; 591 uint8_t tap_sign : 1; 592 uint8_t x_tap : 1; 593 uint8_t y_tap : 1; 594 uint8_t z_tap : 1; 595 #endif /* DRV_BYTE_ORDER */ 596 } ism330dhcx_tap_src_t; 597 598 #define ISM330DHCX_D6D_SRC 0x1DU 599 typedef struct 600 { 601 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 602 uint8_t xl : 1; 603 uint8_t xh : 1; 604 uint8_t yl : 1; 605 uint8_t yh : 1; 606 uint8_t zl : 1; 607 uint8_t zh : 1; 608 uint8_t d6d_ia : 1; 609 uint8_t den_drdy : 1; 610 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 611 uint8_t den_drdy : 1; 612 uint8_t d6d_ia : 1; 613 uint8_t zh : 1; 614 uint8_t zl : 1; 615 uint8_t yh : 1; 616 uint8_t yl : 1; 617 uint8_t xh : 1; 618 uint8_t xl : 1; 619 #endif /* DRV_BYTE_ORDER */ 620 } ism330dhcx_d6d_src_t; 621 622 #define ISM330DHCX_STATUS_REG 0x1EU 623 typedef struct 624 { 625 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 626 uint8_t xlda : 1; 627 uint8_t gda : 1; 628 uint8_t tda : 1; 629 uint8_t not_used_01 : 5; 630 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 631 uint8_t not_used_01 : 5; 632 uint8_t tda : 1; 633 uint8_t gda : 1; 634 uint8_t xlda : 1; 635 #endif /* DRV_BYTE_ORDER */ 636 } ism330dhcx_status_reg_t; 637 638 #define ISM330DHCX_STATUS_SPIAUX 0x1EU 639 typedef struct 640 { 641 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 642 uint8_t xlda : 1; 643 uint8_t gda : 1; 644 uint8_t gyro_settling : 1; 645 uint8_t not_used_01 : 5; 646 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 647 uint8_t not_used_01 : 5; 648 uint8_t gyro_settling : 1; 649 uint8_t gda : 1; 650 uint8_t xlda : 1; 651 #endif /* DRV_BYTE_ORDER */ 652 } ism330dhcx_status_spiaux_t; 653 654 #define ISM330DHCX_OUT_TEMP_L 0x20U 655 #define ISM330DHCX_OUT_TEMP_H 0x21U 656 #define ISM330DHCX_OUTX_L_G 0x22U 657 #define ISM330DHCX_OUTX_H_G 0x23U 658 #define ISM330DHCX_OUTY_L_G 0x24U 659 #define ISM330DHCX_OUTY_H_G 0x25U 660 #define ISM330DHCX_OUTZ_L_G 0x26U 661 #define ISM330DHCX_OUTZ_H_G 0x27U 662 #define ISM330DHCX_OUTX_L_A 0x28U 663 #define ISM330DHCX_OUTX_H_A 0x29U 664 #define ISM330DHCX_OUTY_L_A 0x2AU 665 #define ISM330DHCX_OUTY_H_A 0x2BU 666 #define ISM330DHCX_OUTZ_L_A 0x2CU 667 #define ISM330DHCX_OUTZ_H_A 0x2DU 668 669 #define ISM330DHCX_EMB_FUNC_STATUS_MAINPAGE 0x35U 670 typedef struct 671 { 672 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 673 uint8_t not_used_01 : 3; 674 uint8_t is_step_det : 1; 675 uint8_t is_tilt : 1; 676 uint8_t is_sigmot : 1; 677 uint8_t not_used_02 : 1; 678 uint8_t is_fsm_lc : 1; 679 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 680 uint8_t is_fsm_lc : 1; 681 uint8_t not_used_02 : 1; 682 uint8_t is_sigmot : 1; 683 uint8_t is_tilt : 1; 684 uint8_t is_step_det : 1; 685 uint8_t not_used_01 : 3; 686 #endif /* DRV_BYTE_ORDER */ 687 } ism330dhcx_emb_func_status_mainpage_t; 688 689 #define ISM330DHCX_FSM_STATUS_A_MAINPAGE 0x36U 690 typedef struct 691 { 692 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 693 uint8_t is_fsm1 : 1; 694 uint8_t is_fsm2 : 1; 695 uint8_t is_fsm3 : 1; 696 uint8_t is_fsm4 : 1; 697 uint8_t is_fsm5 : 1; 698 uint8_t is_fsm6 : 1; 699 uint8_t is_fsm7 : 1; 700 uint8_t is_fsm8 : 1; 701 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 702 uint8_t is_fsm8 : 1; 703 uint8_t is_fsm7 : 1; 704 uint8_t is_fsm6 : 1; 705 uint8_t is_fsm5 : 1; 706 uint8_t is_fsm4 : 1; 707 uint8_t is_fsm3 : 1; 708 uint8_t is_fsm2 : 1; 709 uint8_t is_fsm1 : 1; 710 #endif /* DRV_BYTE_ORDER */ 711 } ism330dhcx_fsm_status_a_mainpage_t; 712 713 #define ISM330DHCX_FSM_STATUS_B_MAINPAGE 0x37U 714 typedef struct 715 { 716 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 717 uint8_t is_fsm9 : 1; 718 uint8_t is_fsm10 : 1; 719 uint8_t is_fsm11 : 1; 720 uint8_t is_fsm12 : 1; 721 uint8_t is_fsm13 : 1; 722 uint8_t is_fsm14 : 1; 723 uint8_t is_fsm15 : 1; 724 uint8_t is_fsm16 : 1; 725 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 726 uint8_t is_fsm16 : 1; 727 uint8_t is_fsm15 : 1; 728 uint8_t is_fsm14 : 1; 729 uint8_t is_fsm13 : 1; 730 uint8_t is_fsm12 : 1; 731 uint8_t is_fsm11 : 1; 732 uint8_t is_fsm10 : 1; 733 uint8_t is_fsm9 : 1; 734 #endif /* DRV_BYTE_ORDER */ 735 } ism330dhcx_fsm_status_b_mainpage_t; 736 737 #define ISM330DHCX_MLC_STATUS_MAINPAGE 0x38U 738 typedef struct 739 { 740 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 741 uint8_t is_mlc1 : 1; 742 uint8_t is_mlc2 : 1; 743 uint8_t is_mlc3 : 1; 744 uint8_t is_mlc4 : 1; 745 uint8_t is_mlc5 : 1; 746 uint8_t is_mlc6 : 1; 747 uint8_t is_mlc7 : 1; 748 uint8_t is_mlc8 : 1; 749 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 750 uint8_t is_mlc8 : 1; 751 uint8_t is_mlc7 : 1; 752 uint8_t is_mlc6 : 1; 753 uint8_t is_mlc5 : 1; 754 uint8_t is_mlc4 : 1; 755 uint8_t is_mlc3 : 1; 756 uint8_t is_mlc2 : 1; 757 uint8_t is_mlc1 : 1; 758 #endif /* DRV_BYTE_ORDER */ 759 } ism330dhcx_mlc_status_mainpage_t; 760 761 #define ISM330DHCX_STATUS_MASTER_MAINPAGE 0x39U 762 typedef struct 763 { 764 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 765 uint8_t sens_hub_endop : 1; 766 uint8_t not_used_01 : 2; 767 uint8_t slave0_nack : 1; 768 uint8_t slave1_nack : 1; 769 uint8_t slave2_nack : 1; 770 uint8_t slave3_nack : 1; 771 uint8_t wr_once_done : 1; 772 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 773 uint8_t wr_once_done : 1; 774 uint8_t slave3_nack : 1; 775 uint8_t slave2_nack : 1; 776 uint8_t slave1_nack : 1; 777 uint8_t slave0_nack : 1; 778 uint8_t not_used_01 : 2; 779 uint8_t sens_hub_endop : 1; 780 #endif /* DRV_BYTE_ORDER */ 781 } ism330dhcx_status_master_mainpage_t; 782 783 #define ISM330DHCX_FIFO_STATUS1 0x3AU 784 typedef struct 785 { 786 uint8_t diff_fifo : 8; 787 } ism330dhcx_fifo_status1_t; 788 789 #define ISM330DHCX_FIFO_STATUS2 0x3BU 790 typedef struct 791 { 792 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 793 uint8_t diff_fifo : 2; 794 uint8_t not_used_01 : 1; 795 uint8_t over_run_latched : 1; 796 uint8_t counter_bdr_ia : 1; 797 uint8_t fifo_full_ia : 1; 798 uint8_t fifo_ovr_ia : 1; 799 uint8_t fifo_wtm_ia : 1; 800 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 801 uint8_t fifo_wtm_ia : 1; 802 uint8_t fifo_ovr_ia : 1; 803 uint8_t fifo_full_ia : 1; 804 uint8_t counter_bdr_ia : 1; 805 uint8_t over_run_latched : 1; 806 uint8_t not_used_01 : 1; 807 uint8_t diff_fifo : 2; 808 #endif /* DRV_BYTE_ORDER */ 809 } ism330dhcx_fifo_status2_t; 810 811 #define ISM330DHCX_TIMESTAMP0 0x40U 812 #define ISM330DHCX_TIMESTAMP1 0x41U 813 #define ISM330DHCX_TIMESTAMP2 0x42U 814 #define ISM330DHCX_TIMESTAMP3 0x43U 815 #define ISM330DHCX_TAP_CFG0 0x56U 816 typedef struct 817 { 818 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 819 uint8_t lir : 1; 820 uint8_t tap_z_en : 1; 821 uint8_t tap_y_en : 1; 822 uint8_t tap_x_en : 1; 823 uint8_t slope_fds : 1; 824 uint8_t sleep_status_on_int : 1; 825 uint8_t int_clr_on_read : 1; 826 uint8_t not_used_01 : 1; 827 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 828 uint8_t not_used_01 : 1; 829 uint8_t int_clr_on_read : 1; 830 uint8_t sleep_status_on_int : 1; 831 uint8_t slope_fds : 1; 832 uint8_t tap_x_en : 1; 833 uint8_t tap_y_en : 1; 834 uint8_t tap_z_en : 1; 835 uint8_t lir : 1; 836 #endif /* DRV_BYTE_ORDER */ 837 } ism330dhcx_tap_cfg0_t; 838 839 #define ISM330DHCX_TAP_CFG1 0x57U 840 typedef struct 841 { 842 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 843 uint8_t tap_ths_x : 5; 844 uint8_t tap_priority : 3; 845 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 846 uint8_t tap_priority : 3; 847 uint8_t tap_ths_x : 5; 848 #endif /* DRV_BYTE_ORDER */ 849 } ism330dhcx_tap_cfg1_t; 850 851 #define ISM330DHCX_TAP_CFG2 0x58U 852 typedef struct 853 { 854 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 855 uint8_t tap_ths_y : 5; 856 uint8_t inact_en : 2; 857 uint8_t interrupts_enable : 1; 858 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 859 uint8_t interrupts_enable : 1; 860 uint8_t inact_en : 2; 861 uint8_t tap_ths_y : 5; 862 #endif /* DRV_BYTE_ORDER */ 863 } ism330dhcx_tap_cfg2_t; 864 865 #define ISM330DHCX_TAP_THS_6D 0x59U 866 typedef struct 867 { 868 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 869 uint8_t tap_ths_z : 5; 870 uint8_t sixd_ths : 2; 871 uint8_t d4d_en : 1; 872 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 873 uint8_t d4d_en : 1; 874 uint8_t sixd_ths : 2; 875 uint8_t tap_ths_z : 5; 876 #endif /* DRV_BYTE_ORDER */ 877 } ism330dhcx_tap_ths_6d_t; 878 879 #define ISM330DHCX_INT_DUR2 0x5AU 880 typedef struct 881 { 882 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 883 uint8_t shock : 2; 884 uint8_t quiet : 2; 885 uint8_t dur : 4; 886 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 887 uint8_t dur : 4; 888 uint8_t quiet : 2; 889 uint8_t shock : 2; 890 #endif /* DRV_BYTE_ORDER */ 891 } ism330dhcx_int_dur2_t; 892 893 #define ISM330DHCX_WAKE_UP_THS 0x5BU 894 typedef struct 895 { 896 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 897 uint8_t wk_ths : 6; 898 uint8_t usr_off_on_wu : 1; 899 uint8_t single_double_tap : 1; 900 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 901 uint8_t single_double_tap : 1; 902 uint8_t usr_off_on_wu : 1; 903 uint8_t wk_ths : 6; 904 #endif /* DRV_BYTE_ORDER */ 905 } ism330dhcx_wake_up_ths_t; 906 907 #define ISM330DHCX_WAKE_UP_DUR 0x5CU 908 typedef struct 909 { 910 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 911 uint8_t sleep_dur : 4; 912 uint8_t wake_ths_w : 1; 913 uint8_t wake_dur : 2; 914 uint8_t ff_dur : 1; 915 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 916 uint8_t ff_dur : 1; 917 uint8_t wake_dur : 2; 918 uint8_t wake_ths_w : 1; 919 uint8_t sleep_dur : 4; 920 #endif /* DRV_BYTE_ORDER */ 921 } ism330dhcx_wake_up_dur_t; 922 923 #define ISM330DHCX_FREE_FALL 0x5DU 924 typedef struct 925 { 926 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 927 uint8_t ff_ths : 3; 928 uint8_t ff_dur : 5; 929 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 930 uint8_t ff_dur : 5; 931 uint8_t ff_ths : 3; 932 #endif /* DRV_BYTE_ORDER */ 933 } ism330dhcx_free_fall_t; 934 935 #define ISM330DHCX_MD1_CFG 0x5EU 936 typedef struct 937 { 938 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 939 uint8_t int1_shub : 1; 940 uint8_t int1_emb_func : 1; 941 uint8_t int1_6d : 1; 942 uint8_t int1_double_tap : 1; 943 uint8_t int1_ff : 1; 944 uint8_t int1_wu : 1; 945 uint8_t int1_single_tap : 1; 946 uint8_t int1_sleep_change : 1; 947 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 948 uint8_t int1_sleep_change : 1; 949 uint8_t int1_single_tap : 1; 950 uint8_t int1_wu : 1; 951 uint8_t int1_ff : 1; 952 uint8_t int1_double_tap : 1; 953 uint8_t int1_6d : 1; 954 uint8_t int1_emb_func : 1; 955 uint8_t int1_shub : 1; 956 #endif /* DRV_BYTE_ORDER */ 957 } ism330dhcx_md1_cfg_t; 958 959 #define ISM330DHCX_MD2_CFG 0x5FU 960 typedef struct 961 { 962 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 963 uint8_t int2_timestamp : 1; 964 uint8_t int2_emb_func : 1; 965 uint8_t int2_6d : 1; 966 uint8_t int2_double_tap : 1; 967 uint8_t int2_ff : 1; 968 uint8_t int2_wu : 1; 969 uint8_t int2_single_tap : 1; 970 uint8_t int2_sleep_change : 1; 971 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 972 uint8_t int2_sleep_change : 1; 973 uint8_t int2_single_tap : 1; 974 uint8_t int2_wu : 1; 975 uint8_t int2_ff : 1; 976 uint8_t int2_double_tap : 1; 977 uint8_t int2_6d : 1; 978 uint8_t int2_emb_func : 1; 979 uint8_t int2_timestamp : 1; 980 #endif /* DRV_BYTE_ORDER */ 981 } ism330dhcx_md2_cfg_t; 982 983 #define ISM330DHCX_INTERNAL_FREQ_FINE 0x63U 984 typedef struct 985 { 986 uint8_t freq_fine : 8; 987 } ism330dhcx_internal_freq_fine_t; 988 989 #define ISM330DHCX_INT_OIS 0x6FU 990 typedef struct 991 { 992 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 993 uint8_t st_xl_ois : 2; 994 uint8_t not_used_01 : 3; 995 uint8_t den_lh_ois : 1; 996 uint8_t lvl2_ois : 1; 997 uint8_t int2_drdy_ois : 1; 998 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 999 uint8_t int2_drdy_ois : 1; 1000 uint8_t lvl2_ois : 1; 1001 uint8_t den_lh_ois : 1; 1002 uint8_t not_used_01 : 3; 1003 uint8_t st_xl_ois : 2; 1004 #endif /* DRV_BYTE_ORDER */ 1005 } ism330dhcx_int_ois_t; 1006 1007 #define ISM330DHCX_CTRL1_OIS 0x70U 1008 typedef struct 1009 { 1010 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1011 uint8_t ois_en_spi2 : 1; 1012 uint8_t fs_125_ois : 1; 1013 uint8_t fs_g_ois : 2; 1014 uint8_t mode4_en : 1; 1015 uint8_t sim_ois : 1; 1016 uint8_t lvl1_ois : 1; 1017 uint8_t not_used_01 : 1; 1018 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1019 uint8_t not_used_01 : 1; 1020 uint8_t lvl1_ois : 1; 1021 uint8_t sim_ois : 1; 1022 uint8_t mode4_en : 1; 1023 uint8_t fs_g_ois : 2; 1024 uint8_t fs_125_ois : 1; 1025 uint8_t ois_en_spi2 : 1; 1026 #endif /* DRV_BYTE_ORDER */ 1027 } ism330dhcx_ctrl1_ois_t; 1028 1029 #define ISM330DHCX_CTRL2_OIS 0x71U 1030 typedef struct 1031 { 1032 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1033 uint8_t hp_en_ois : 1; 1034 uint8_t ftype_ois : 2; 1035 uint8_t not_used_01 : 1; 1036 uint8_t hpm_ois : 2; 1037 uint8_t not_used_02 : 2; 1038 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1039 uint8_t not_used_02 : 2; 1040 uint8_t hpm_ois : 2; 1041 uint8_t not_used_01 : 1; 1042 uint8_t ftype_ois : 2; 1043 uint8_t hp_en_ois : 1; 1044 #endif /* DRV_BYTE_ORDER */ 1045 } ism330dhcx_ctrl2_ois_t; 1046 1047 #define ISM330DHCX_CTRL3_OIS 0x72U 1048 typedef struct 1049 { 1050 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1051 uint8_t st_ois_clampdis : 1; 1052 uint8_t st_ois : 2; 1053 uint8_t filter_xl_conf_ois : 3; 1054 uint8_t fs_xl_ois : 2; 1055 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1056 uint8_t fs_xl_ois : 2; 1057 uint8_t filter_xl_conf_ois : 3; 1058 uint8_t st_ois : 2; 1059 uint8_t st_ois_clampdis : 1; 1060 #endif /* DRV_BYTE_ORDER */ 1061 } ism330dhcx_ctrl3_ois_t; 1062 1063 #define ISM330DHCX_X_OFS_USR 0x73U 1064 #define ISM330DHCX_Y_OFS_USR 0x74U 1065 #define ISM330DHCX_Z_OFS_USR 0x75U 1066 #define ISM330DHCX_FIFO_DATA_OUT_TAG 0x78U 1067 typedef struct 1068 { 1069 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1070 uint8_t tag_parity : 1; 1071 uint8_t tag_cnt : 2; 1072 uint8_t tag_sensor : 5; 1073 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1074 uint8_t tag_sensor : 5; 1075 uint8_t tag_cnt : 2; 1076 uint8_t tag_parity : 1; 1077 #endif /* DRV_BYTE_ORDER */ 1078 } ism330dhcx_fifo_data_out_tag_t; 1079 1080 #define ISM330DHCX_FIFO_DATA_OUT_X_L 0x79U 1081 #define ISM330DHCX_FIFO_DATA_OUT_X_H 0x7AU 1082 #define ISM330DHCX_FIFO_DATA_OUT_Y_L 0x7BU 1083 #define ISM330DHCX_FIFO_DATA_OUT_Y_H 0x7CU 1084 #define ISM330DHCX_FIFO_DATA_OUT_Z_L 0x7DU 1085 #define ISM330DHCX_FIFO_DATA_OUT_Z_H 0x7EU 1086 #define ISM330DHCX_PAGE_SEL 0x02U 1087 typedef struct 1088 { 1089 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1090 uint8_t not_used_01 : 4; 1091 uint8_t page_sel : 4; 1092 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1093 uint8_t page_sel : 4; 1094 uint8_t not_used_01 : 4; 1095 #endif /* DRV_BYTE_ORDER */ 1096 } ism330dhcx_page_sel_t; 1097 1098 #define ISM330DHCX_EMB_FUNC_EN_A 0x04U 1099 typedef struct 1100 { 1101 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1102 uint8_t not_used_01 : 3; 1103 uint8_t pedo_en : 1; 1104 uint8_t tilt_en : 1; 1105 uint8_t sign_motion_en : 1; 1106 uint8_t not_used_02 : 2; 1107 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1108 uint8_t not_used_02 : 2; 1109 uint8_t sign_motion_en : 1; 1110 uint8_t tilt_en : 1; 1111 uint8_t pedo_en : 1; 1112 uint8_t not_used_01 : 3; 1113 #endif /* DRV_BYTE_ORDER */ 1114 } ism330dhcx_emb_func_en_a_t; 1115 1116 #define ISM330DHCX_EMB_FUNC_EN_B 0x05U 1117 typedef struct 1118 { 1119 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1120 uint8_t fsm_en : 1; 1121 uint8_t not_used_01 : 2; 1122 uint8_t fifo_compr_en : 1; 1123 uint8_t mlc_en : 1; 1124 uint8_t not_used_02 : 3; 1125 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1126 uint8_t not_used_02 : 3; 1127 uint8_t mlc_en : 1; 1128 uint8_t fifo_compr_en : 1; 1129 uint8_t not_used_01 : 2; 1130 uint8_t fsm_en : 1; 1131 #endif /* DRV_BYTE_ORDER */ 1132 } ism330dhcx_emb_func_en_b_t; 1133 1134 #define ISM330DHCX_PAGE_ADDRESS 0x08U 1135 typedef struct 1136 { 1137 uint8_t page_addr : 8; 1138 } ism330dhcx_page_address_t; 1139 1140 #define ISM330DHCX_PAGE_VALUE 0x09U 1141 typedef struct 1142 { 1143 uint8_t page_value : 8; 1144 } ism330dhcx_page_value_t; 1145 1146 #define ISM330DHCX_EMB_FUNC_INT1 0x0AU 1147 typedef struct 1148 { 1149 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1150 uint8_t not_used_01 : 3; 1151 uint8_t int1_step_detector : 1; 1152 uint8_t int1_tilt : 1; 1153 uint8_t int1_sig_mot : 1; 1154 uint8_t not_used_02 : 1; 1155 uint8_t int1_fsm_lc : 1; 1156 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1157 uint8_t int1_fsm_lc : 1; 1158 uint8_t not_used_02 : 1; 1159 uint8_t int1_sig_mot : 1; 1160 uint8_t int1_tilt : 1; 1161 uint8_t int1_step_detector : 1; 1162 uint8_t not_used_01 : 3; 1163 #endif /* DRV_BYTE_ORDER */ 1164 } ism330dhcx_emb_func_int1_t; 1165 1166 #define ISM330DHCX_FSM_INT1_A 0x0BU 1167 typedef struct 1168 { 1169 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1170 uint8_t int1_fsm1 : 1; 1171 uint8_t int1_fsm2 : 1; 1172 uint8_t int1_fsm3 : 1; 1173 uint8_t int1_fsm4 : 1; 1174 uint8_t int1_fsm5 : 1; 1175 uint8_t int1_fsm6 : 1; 1176 uint8_t int1_fsm7 : 1; 1177 uint8_t int1_fsm8 : 1; 1178 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1179 uint8_t int1_fsm8 : 1; 1180 uint8_t int1_fsm7 : 1; 1181 uint8_t int1_fsm6 : 1; 1182 uint8_t int1_fsm5 : 1; 1183 uint8_t int1_fsm4 : 1; 1184 uint8_t int1_fsm3 : 1; 1185 uint8_t int1_fsm2 : 1; 1186 uint8_t int1_fsm1 : 1; 1187 #endif /* DRV_BYTE_ORDER */ 1188 } ism330dhcx_fsm_int1_a_t; 1189 1190 #define ISM330DHCX_FSM_INT1_B 0x0CU 1191 typedef struct 1192 { 1193 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1194 uint8_t int1_fsm9 : 1; 1195 uint8_t int1_fsm10 : 1; 1196 uint8_t int1_fsm11 : 1; 1197 uint8_t int1_fsm12 : 1; 1198 uint8_t int1_fsm13 : 1; 1199 uint8_t int1_fsm14 : 1; 1200 uint8_t int1_fsm15 : 1; 1201 uint8_t int1_fsm16 : 1; 1202 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1203 uint8_t int1_fsm16 : 1; 1204 uint8_t int1_fsm15 : 1; 1205 uint8_t int1_fsm14 : 1; 1206 uint8_t int1_fsm13 : 1; 1207 uint8_t int1_fsm12 : 1; 1208 uint8_t int1_fsm11 : 1; 1209 uint8_t int1_fsm10 : 1; 1210 uint8_t int1_fsm9 : 1; 1211 #endif /* DRV_BYTE_ORDER */ 1212 } ism330dhcx_fsm_int1_b_t; 1213 1214 #define ISM330DHCX_MLC_INT1 0x0DU 1215 typedef struct 1216 { 1217 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1218 uint8_t int1_mlc1 : 1; 1219 uint8_t int1_mlc2 : 1; 1220 uint8_t int1_mlc3 : 1; 1221 uint8_t int1_mlc4 : 1; 1222 uint8_t int1_mlc5 : 1; 1223 uint8_t int1_mlc6 : 1; 1224 uint8_t int1_mlc7 : 1; 1225 uint8_t int1_mlc8 : 1; 1226 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1227 uint8_t int1_mlc8 : 1; 1228 uint8_t int1_mlc7 : 1; 1229 uint8_t int1_mlc6 : 1; 1230 uint8_t int1_mlc5 : 1; 1231 uint8_t int1_mlc4 : 1; 1232 uint8_t int1_mlc3 : 1; 1233 uint8_t int1_mlc2 : 1; 1234 uint8_t int1_mlc1 : 1; 1235 #endif /* DRV_BYTE_ORDER */ 1236 } ism330dhcx_mlc_int1_t; 1237 1238 #define ISM330DHCX_EMB_FUNC_INT2 0x0EU 1239 typedef struct 1240 { 1241 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1242 uint8_t not_used_01 : 3; 1243 uint8_t int2_step_detector : 1; 1244 uint8_t int2_tilt : 1; 1245 uint8_t int2_sig_mot : 1; 1246 uint8_t not_used_02 : 1; 1247 uint8_t int2_fsm_lc : 1; 1248 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1249 uint8_t int2_fsm_lc : 1; 1250 uint8_t not_used_02 : 1; 1251 uint8_t int2_sig_mot : 1; 1252 uint8_t int2_tilt : 1; 1253 uint8_t int2_step_detector : 1; 1254 uint8_t not_used_01 : 3; 1255 #endif /* DRV_BYTE_ORDER */ 1256 } ism330dhcx_emb_func_int2_t; 1257 1258 #define ISM330DHCX_FSM_INT2_A 0x0FU 1259 typedef struct 1260 { 1261 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1262 uint8_t int2_fsm1 : 1; 1263 uint8_t int2_fsm2 : 1; 1264 uint8_t int2_fsm3 : 1; 1265 uint8_t int2_fsm4 : 1; 1266 uint8_t int2_fsm5 : 1; 1267 uint8_t int2_fsm6 : 1; 1268 uint8_t int2_fsm7 : 1; 1269 uint8_t int2_fsm8 : 1; 1270 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1271 uint8_t int2_fsm8 : 1; 1272 uint8_t int2_fsm7 : 1; 1273 uint8_t int2_fsm6 : 1; 1274 uint8_t int2_fsm5 : 1; 1275 uint8_t int2_fsm4 : 1; 1276 uint8_t int2_fsm3 : 1; 1277 uint8_t int2_fsm2 : 1; 1278 uint8_t int2_fsm1 : 1; 1279 #endif /* DRV_BYTE_ORDER */ 1280 } ism330dhcx_fsm_int2_a_t; 1281 1282 #define ISM330DHCX_FSM_INT2_B 0x10U 1283 typedef struct 1284 { 1285 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1286 uint8_t int2_fsm9 : 1; 1287 uint8_t int2_fsm10 : 1; 1288 uint8_t int2_fsm11 : 1; 1289 uint8_t int2_fsm12 : 1; 1290 uint8_t int2_fsm13 : 1; 1291 uint8_t int2_fsm14 : 1; 1292 uint8_t int2_fsm15 : 1; 1293 uint8_t int2_fsm16 : 1; 1294 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1295 uint8_t int2_fsm16 : 1; 1296 uint8_t int2_fsm15 : 1; 1297 uint8_t int2_fsm14 : 1; 1298 uint8_t int2_fsm13 : 1; 1299 uint8_t int2_fsm12 : 1; 1300 uint8_t int2_fsm11 : 1; 1301 uint8_t int2_fsm10 : 1; 1302 uint8_t int2_fsm9 : 1; 1303 #endif /* DRV_BYTE_ORDER */ 1304 } ism330dhcx_fsm_int2_b_t; 1305 1306 #define ISM330DHCX_MLC_INT2 0x11U 1307 typedef struct 1308 { 1309 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1310 uint8_t int2_mlc1 : 1; 1311 uint8_t int2_mlc2 : 1; 1312 uint8_t int2_mlc3 : 1; 1313 uint8_t int2_mlc4 : 1; 1314 uint8_t int2_mlc5 : 1; 1315 uint8_t int2_mlc6 : 1; 1316 uint8_t int2_mlc7 : 1; 1317 uint8_t int2_mlc8 : 1; 1318 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1319 uint8_t int2_mlc8 : 1; 1320 uint8_t int2_mlc7 : 1; 1321 uint8_t int2_mlc6 : 1; 1322 uint8_t int2_mlc5 : 1; 1323 uint8_t int2_mlc4 : 1; 1324 uint8_t int2_mlc3 : 1; 1325 uint8_t int2_mlc2 : 1; 1326 uint8_t int2_mlc1 : 1; 1327 #endif /* DRV_BYTE_ORDER */ 1328 } ism330dhcx_mlc_int2_t; 1329 1330 #define ISM330DHCX_EMB_FUNC_STATUS 0x12U 1331 typedef struct 1332 { 1333 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1334 uint8_t not_used_01 : 3; 1335 uint8_t is_step_det : 1; 1336 uint8_t is_tilt : 1; 1337 uint8_t is_sigmot : 1; 1338 uint8_t not_used_02 : 1; 1339 uint8_t is_fsm_lc : 1; 1340 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1341 uint8_t is_fsm_lc : 1; 1342 uint8_t not_used_02 : 1; 1343 uint8_t is_sigmot : 1; 1344 uint8_t is_tilt : 1; 1345 uint8_t is_step_det : 1; 1346 uint8_t not_used_01 : 3; 1347 #endif /* DRV_BYTE_ORDER */ 1348 } ism330dhcx_emb_func_status_t; 1349 1350 #define ISM330DHCX_FSM_STATUS_A 0x13U 1351 typedef struct 1352 { 1353 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1354 uint8_t is_fsm1 : 1; 1355 uint8_t is_fsm2 : 1; 1356 uint8_t is_fsm3 : 1; 1357 uint8_t is_fsm4 : 1; 1358 uint8_t is_fsm5 : 1; 1359 uint8_t is_fsm6 : 1; 1360 uint8_t is_fsm7 : 1; 1361 uint8_t is_fsm8 : 1; 1362 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1363 uint8_t is_fsm8 : 1; 1364 uint8_t is_fsm7 : 1; 1365 uint8_t is_fsm6 : 1; 1366 uint8_t is_fsm5 : 1; 1367 uint8_t is_fsm4 : 1; 1368 uint8_t is_fsm3 : 1; 1369 uint8_t is_fsm2 : 1; 1370 uint8_t is_fsm1 : 1; 1371 #endif /* DRV_BYTE_ORDER */ 1372 } ism330dhcx_fsm_status_a_t; 1373 1374 #define ISM330DHCX_FSM_STATUS_B 0x14U 1375 typedef struct 1376 { 1377 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1378 uint8_t is_fsm9 : 1; 1379 uint8_t is_fsm10 : 1; 1380 uint8_t is_fsm11 : 1; 1381 uint8_t is_fsm12 : 1; 1382 uint8_t is_fsm13 : 1; 1383 uint8_t is_fsm14 : 1; 1384 uint8_t is_fsm15 : 1; 1385 uint8_t is_fsm16 : 1; 1386 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1387 uint8_t is_fsm16 : 1; 1388 uint8_t is_fsm15 : 1; 1389 uint8_t is_fsm14 : 1; 1390 uint8_t is_fsm13 : 1; 1391 uint8_t is_fsm12 : 1; 1392 uint8_t is_fsm11 : 1; 1393 uint8_t is_fsm10 : 1; 1394 uint8_t is_fsm9 : 1; 1395 #endif /* DRV_BYTE_ORDER */ 1396 } ism330dhcx_fsm_status_b_t; 1397 1398 #define ISM330DHCX_MLC_STATUS 0x15U 1399 typedef struct 1400 { 1401 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1402 uint8_t is_mlc1 : 1; 1403 uint8_t is_mlc2 : 1; 1404 uint8_t is_mlc3 : 1; 1405 uint8_t is_mlc4 : 1; 1406 uint8_t is_mlc5 : 1; 1407 uint8_t is_mlc6 : 1; 1408 uint8_t is_mlc7 : 1; 1409 uint8_t is_mlc8 : 1; 1410 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1411 uint8_t is_mlc8 : 1; 1412 uint8_t is_mlc7 : 1; 1413 uint8_t is_mlc6 : 1; 1414 uint8_t is_mlc5 : 1; 1415 uint8_t is_mlc4 : 1; 1416 uint8_t is_mlc3 : 1; 1417 uint8_t is_mlc2 : 1; 1418 uint8_t is_mlc1 : 1; 1419 #endif /* DRV_BYTE_ORDER */ 1420 } ism330dhcx_mlc_status_t; 1421 1422 #define ISM330DHCX_PAGE_RW 0x17U 1423 typedef struct 1424 { 1425 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1426 uint8_t not_used_01 : 5; 1427 uint8_t page_rw : 2; /* page_write + page_read */ 1428 uint8_t emb_func_lir : 1; 1429 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1430 uint8_t emb_func_lir : 1; 1431 uint8_t page_rw : 2; /* page_write + page_read */ 1432 uint8_t not_used_01 : 5; 1433 #endif /* DRV_BYTE_ORDER */ 1434 } ism330dhcx_page_rw_t; 1435 1436 #define ISM330DHCX_EMB_FUNC_FIFO_CFG 0x44U 1437 typedef struct 1438 { 1439 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1440 uint8_t not_used_01 : 6; 1441 uint8_t pedo_fifo_en : 1; 1442 uint8_t not_used_02 : 1; 1443 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1444 uint8_t not_used_02 : 1; 1445 uint8_t pedo_fifo_en : 1; 1446 uint8_t not_used_01 : 6; 1447 #endif /* DRV_BYTE_ORDER */ 1448 } ism330dhcx_emb_func_fifo_cfg_t; 1449 1450 #define ISM330DHCX_FSM_ENABLE_A 0x46U 1451 typedef struct 1452 { 1453 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1454 uint8_t fsm1_en : 1; 1455 uint8_t fsm2_en : 1; 1456 uint8_t fsm3_en : 1; 1457 uint8_t fsm4_en : 1; 1458 uint8_t fsm5_en : 1; 1459 uint8_t fsm6_en : 1; 1460 uint8_t fsm7_en : 1; 1461 uint8_t fsm8_en : 1; 1462 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1463 uint8_t fsm8_en : 1; 1464 uint8_t fsm7_en : 1; 1465 uint8_t fsm6_en : 1; 1466 uint8_t fsm5_en : 1; 1467 uint8_t fsm4_en : 1; 1468 uint8_t fsm3_en : 1; 1469 uint8_t fsm2_en : 1; 1470 uint8_t fsm1_en : 1; 1471 #endif /* DRV_BYTE_ORDER */ 1472 } ism330dhcx_fsm_enable_a_t; 1473 1474 #define ISM330DHCX_FSM_ENABLE_B 0x47U 1475 typedef struct 1476 { 1477 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1478 uint8_t fsm9_en : 1; 1479 uint8_t fsm10_en : 1; 1480 uint8_t fsm11_en : 1; 1481 uint8_t fsm12_en : 1; 1482 uint8_t fsm13_en : 1; 1483 uint8_t fsm14_en : 1; 1484 uint8_t fsm15_en : 1; 1485 uint8_t fsm16_en : 1; 1486 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1487 uint8_t fsm16_en : 1; 1488 uint8_t fsm15_en : 1; 1489 uint8_t fsm14_en : 1; 1490 uint8_t fsm13_en : 1; 1491 uint8_t fsm12_en : 1; 1492 uint8_t fsm11_en : 1; 1493 uint8_t fsm10_en : 1; 1494 uint8_t fsm9_en : 1; 1495 #endif /* DRV_BYTE_ORDER */ 1496 } ism330dhcx_fsm_enable_b_t; 1497 1498 #define ISM330DHCX_FSM_LONG_COUNTER_L 0x48U 1499 #define ISM330DHCX_FSM_LONG_COUNTER_H 0x49U 1500 #define ISM330DHCX_FSM_LONG_COUNTER_CLEAR 0x4AU 1501 typedef struct 1502 { 1503 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1504 uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */ 1505 uint8_t not_used_01 : 6; 1506 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1507 uint8_t not_used_01 : 6; 1508 uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */ 1509 #endif /* DRV_BYTE_ORDER */ 1510 } ism330dhcx_fsm_long_counter_clear_t; 1511 1512 #define ISM330DHCX_FSM_OUTS1 0x4CU 1513 typedef struct 1514 { 1515 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1516 uint8_t n_v : 1; 1517 uint8_t p_v : 1; 1518 uint8_t n_z : 1; 1519 uint8_t p_z : 1; 1520 uint8_t n_y : 1; 1521 uint8_t p_y : 1; 1522 uint8_t n_x : 1; 1523 uint8_t p_x : 1; 1524 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1525 uint8_t p_x : 1; 1526 uint8_t n_x : 1; 1527 uint8_t p_y : 1; 1528 uint8_t n_y : 1; 1529 uint8_t p_z : 1; 1530 uint8_t n_z : 1; 1531 uint8_t p_v : 1; 1532 uint8_t n_v : 1; 1533 #endif /* DRV_BYTE_ORDER */ 1534 } ism330dhcx_fsm_outs1_t; 1535 1536 #define ISM330DHCX_FSM_OUTS2 0x4DU 1537 typedef struct 1538 { 1539 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1540 uint8_t n_v : 1; 1541 uint8_t p_v : 1; 1542 uint8_t n_z : 1; 1543 uint8_t p_z : 1; 1544 uint8_t n_y : 1; 1545 uint8_t p_y : 1; 1546 uint8_t n_x : 1; 1547 uint8_t p_x : 1; 1548 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1549 uint8_t p_x : 1; 1550 uint8_t n_x : 1; 1551 uint8_t p_y : 1; 1552 uint8_t n_y : 1; 1553 uint8_t p_z : 1; 1554 uint8_t n_z : 1; 1555 uint8_t p_v : 1; 1556 uint8_t n_v : 1; 1557 #endif /* DRV_BYTE_ORDER */ 1558 } ism330dhcx_fsm_outs2_t; 1559 1560 #define ISM330DHCX_FSM_OUTS3 0x4EU 1561 typedef struct 1562 { 1563 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1564 uint8_t n_v : 1; 1565 uint8_t p_v : 1; 1566 uint8_t n_z : 1; 1567 uint8_t p_z : 1; 1568 uint8_t n_y : 1; 1569 uint8_t p_y : 1; 1570 uint8_t n_x : 1; 1571 uint8_t p_x : 1; 1572 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1573 uint8_t p_x : 1; 1574 uint8_t n_x : 1; 1575 uint8_t p_y : 1; 1576 uint8_t n_y : 1; 1577 uint8_t p_z : 1; 1578 uint8_t n_z : 1; 1579 uint8_t p_v : 1; 1580 uint8_t n_v : 1; 1581 #endif /* DRV_BYTE_ORDER */ 1582 } ism330dhcx_fsm_outs3_t; 1583 1584 #define ISM330DHCX_FSM_OUTS4 0x4FU 1585 typedef struct 1586 { 1587 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1588 uint8_t n_v : 1; 1589 uint8_t p_v : 1; 1590 uint8_t n_z : 1; 1591 uint8_t p_z : 1; 1592 uint8_t n_y : 1; 1593 uint8_t p_y : 1; 1594 uint8_t n_x : 1; 1595 uint8_t p_x : 1; 1596 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1597 uint8_t p_x : 1; 1598 uint8_t n_x : 1; 1599 uint8_t p_y : 1; 1600 uint8_t n_y : 1; 1601 uint8_t p_z : 1; 1602 uint8_t n_z : 1; 1603 uint8_t p_v : 1; 1604 uint8_t n_v : 1; 1605 #endif /* DRV_BYTE_ORDER */ 1606 } ism330dhcx_fsm_outs4_t; 1607 1608 #define ISM330DHCX_FSM_OUTS5 0x50U 1609 typedef struct 1610 { 1611 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1612 uint8_t n_v : 1; 1613 uint8_t p_v : 1; 1614 uint8_t n_z : 1; 1615 uint8_t p_z : 1; 1616 uint8_t n_y : 1; 1617 uint8_t p_y : 1; 1618 uint8_t n_x : 1; 1619 uint8_t p_x : 1; 1620 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1621 uint8_t p_x : 1; 1622 uint8_t n_x : 1; 1623 uint8_t p_y : 1; 1624 uint8_t n_y : 1; 1625 uint8_t p_z : 1; 1626 uint8_t n_z : 1; 1627 uint8_t p_v : 1; 1628 uint8_t n_v : 1; 1629 #endif /* DRV_BYTE_ORDER */ 1630 } ism330dhcx_fsm_outs5_t; 1631 1632 #define ISM330DHCX_FSM_OUTS6 0x51U 1633 typedef struct 1634 { 1635 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1636 uint8_t n_v : 1; 1637 uint8_t p_v : 1; 1638 uint8_t n_z : 1; 1639 uint8_t p_z : 1; 1640 uint8_t n_y : 1; 1641 uint8_t p_y : 1; 1642 uint8_t n_x : 1; 1643 uint8_t p_x : 1; 1644 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1645 uint8_t p_x : 1; 1646 uint8_t n_x : 1; 1647 uint8_t p_y : 1; 1648 uint8_t n_y : 1; 1649 uint8_t p_z : 1; 1650 uint8_t n_z : 1; 1651 uint8_t p_v : 1; 1652 uint8_t n_v : 1; 1653 #endif /* DRV_BYTE_ORDER */ 1654 } ism330dhcx_fsm_outs6_t; 1655 1656 #define ISM330DHCX_FSM_OUTS7 0x52U 1657 typedef struct 1658 { 1659 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1660 uint8_t n_v : 1; 1661 uint8_t p_v : 1; 1662 uint8_t n_z : 1; 1663 uint8_t p_z : 1; 1664 uint8_t n_y : 1; 1665 uint8_t p_y : 1; 1666 uint8_t n_x : 1; 1667 uint8_t p_x : 1; 1668 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1669 uint8_t p_x : 1; 1670 uint8_t n_x : 1; 1671 uint8_t p_y : 1; 1672 uint8_t n_y : 1; 1673 uint8_t p_z : 1; 1674 uint8_t n_z : 1; 1675 uint8_t p_v : 1; 1676 uint8_t n_v : 1; 1677 #endif /* DRV_BYTE_ORDER */ 1678 } ism330dhcx_fsm_outs7_t; 1679 1680 #define ISM330DHCX_FSM_OUTS8 0x53U 1681 typedef struct 1682 { 1683 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1684 uint8_t n_v : 1; 1685 uint8_t p_v : 1; 1686 uint8_t n_z : 1; 1687 uint8_t p_z : 1; 1688 uint8_t n_y : 1; 1689 uint8_t p_y : 1; 1690 uint8_t n_x : 1; 1691 uint8_t p_x : 1; 1692 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1693 uint8_t p_x : 1; 1694 uint8_t n_x : 1; 1695 uint8_t p_y : 1; 1696 uint8_t n_y : 1; 1697 uint8_t p_z : 1; 1698 uint8_t n_z : 1; 1699 uint8_t p_v : 1; 1700 uint8_t n_v : 1; 1701 #endif /* DRV_BYTE_ORDER */ 1702 } ism330dhcx_fsm_outs8_t; 1703 1704 #define ISM330DHCX_FSM_OUTS9 0x54U 1705 typedef struct 1706 { 1707 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1708 uint8_t n_v : 1; 1709 uint8_t p_v : 1; 1710 uint8_t n_z : 1; 1711 uint8_t p_z : 1; 1712 uint8_t n_y : 1; 1713 uint8_t p_y : 1; 1714 uint8_t n_x : 1; 1715 uint8_t p_x : 1; 1716 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1717 uint8_t p_x : 1; 1718 uint8_t n_x : 1; 1719 uint8_t p_y : 1; 1720 uint8_t n_y : 1; 1721 uint8_t p_z : 1; 1722 uint8_t n_z : 1; 1723 uint8_t p_v : 1; 1724 uint8_t n_v : 1; 1725 #endif /* DRV_BYTE_ORDER */ 1726 } ism330dhcx_fsm_outs9_t; 1727 1728 #define ISM330DHCX_FSM_OUTS10 0x55U 1729 typedef struct 1730 { 1731 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1732 uint8_t n_v : 1; 1733 uint8_t p_v : 1; 1734 uint8_t n_z : 1; 1735 uint8_t p_z : 1; 1736 uint8_t n_y : 1; 1737 uint8_t p_y : 1; 1738 uint8_t n_x : 1; 1739 uint8_t p_x : 1; 1740 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1741 uint8_t p_x : 1; 1742 uint8_t n_x : 1; 1743 uint8_t p_y : 1; 1744 uint8_t n_y : 1; 1745 uint8_t p_z : 1; 1746 uint8_t n_z : 1; 1747 uint8_t p_v : 1; 1748 uint8_t n_v : 1; 1749 #endif /* DRV_BYTE_ORDER */ 1750 } ism330dhcx_fsm_outs10_t; 1751 1752 #define ISM330DHCX_FSM_OUTS11 0x56U 1753 typedef struct 1754 { 1755 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1756 uint8_t n_v : 1; 1757 uint8_t p_v : 1; 1758 uint8_t n_z : 1; 1759 uint8_t p_z : 1; 1760 uint8_t n_y : 1; 1761 uint8_t p_y : 1; 1762 uint8_t n_x : 1; 1763 uint8_t p_x : 1; 1764 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1765 uint8_t p_x : 1; 1766 uint8_t n_x : 1; 1767 uint8_t p_y : 1; 1768 uint8_t n_y : 1; 1769 uint8_t p_z : 1; 1770 uint8_t n_z : 1; 1771 uint8_t p_v : 1; 1772 uint8_t n_v : 1; 1773 #endif /* DRV_BYTE_ORDER */ 1774 } ism330dhcx_fsm_outs11_t; 1775 1776 #define ISM330DHCX_FSM_OUTS12 0x57U 1777 typedef struct 1778 { 1779 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1780 uint8_t n_v : 1; 1781 uint8_t p_v : 1; 1782 uint8_t n_z : 1; 1783 uint8_t p_z : 1; 1784 uint8_t n_y : 1; 1785 uint8_t p_y : 1; 1786 uint8_t n_x : 1; 1787 uint8_t p_x : 1; 1788 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1789 uint8_t p_x : 1; 1790 uint8_t n_x : 1; 1791 uint8_t p_y : 1; 1792 uint8_t n_y : 1; 1793 uint8_t p_z : 1; 1794 uint8_t n_z : 1; 1795 uint8_t p_v : 1; 1796 uint8_t n_v : 1; 1797 #endif /* DRV_BYTE_ORDER */ 1798 } ism330dhcx_fsm_outs12_t; 1799 1800 #define ISM330DHCX_FSM_OUTS13 0x58U 1801 typedef struct 1802 { 1803 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1804 uint8_t n_v : 1; 1805 uint8_t p_v : 1; 1806 uint8_t n_z : 1; 1807 uint8_t p_z : 1; 1808 uint8_t n_y : 1; 1809 uint8_t p_y : 1; 1810 uint8_t n_x : 1; 1811 uint8_t p_x : 1; 1812 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1813 uint8_t p_x : 1; 1814 uint8_t n_x : 1; 1815 uint8_t p_y : 1; 1816 uint8_t n_y : 1; 1817 uint8_t p_z : 1; 1818 uint8_t n_z : 1; 1819 uint8_t p_v : 1; 1820 uint8_t n_v : 1; 1821 #endif /* DRV_BYTE_ORDER */ 1822 } ism330dhcx_fsm_outs13_t; 1823 1824 #define ISM330DHCX_FSM_OUTS14 0x59U 1825 typedef struct 1826 { 1827 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1828 uint8_t n_v : 1; 1829 uint8_t p_v : 1; 1830 uint8_t n_z : 1; 1831 uint8_t p_z : 1; 1832 uint8_t n_y : 1; 1833 uint8_t p_y : 1; 1834 uint8_t n_x : 1; 1835 uint8_t p_x : 1; 1836 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1837 uint8_t p_x : 1; 1838 uint8_t n_x : 1; 1839 uint8_t p_y : 1; 1840 uint8_t n_y : 1; 1841 uint8_t p_z : 1; 1842 uint8_t n_z : 1; 1843 uint8_t p_v : 1; 1844 uint8_t n_v : 1; 1845 #endif /* DRV_BYTE_ORDER */ 1846 } ism330dhcx_fsm_outs14_t; 1847 1848 #define ISM330DHCX_FSM_OUTS15 0x5AU 1849 typedef struct 1850 { 1851 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1852 uint8_t n_v : 1; 1853 uint8_t p_v : 1; 1854 uint8_t n_z : 1; 1855 uint8_t p_z : 1; 1856 uint8_t n_y : 1; 1857 uint8_t p_y : 1; 1858 uint8_t n_x : 1; 1859 uint8_t p_x : 1; 1860 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1861 uint8_t p_x : 1; 1862 uint8_t n_x : 1; 1863 uint8_t p_y : 1; 1864 uint8_t n_y : 1; 1865 uint8_t p_z : 1; 1866 uint8_t n_z : 1; 1867 uint8_t p_v : 1; 1868 uint8_t n_v : 1; 1869 #endif /* DRV_BYTE_ORDER */ 1870 } ism330dhcx_fsm_outs15_t; 1871 1872 #define ISM330DHCX_FSM_OUTS16 0x5BU 1873 typedef struct 1874 { 1875 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1876 uint8_t n_v : 1; 1877 uint8_t p_v : 1; 1878 uint8_t n_z : 1; 1879 uint8_t p_z : 1; 1880 uint8_t n_y : 1; 1881 uint8_t p_y : 1; 1882 uint8_t n_x : 1; 1883 uint8_t p_x : 1; 1884 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1885 uint8_t p_x : 1; 1886 uint8_t n_x : 1; 1887 uint8_t p_y : 1; 1888 uint8_t n_y : 1; 1889 uint8_t p_z : 1; 1890 uint8_t n_z : 1; 1891 uint8_t p_v : 1; 1892 uint8_t n_v : 1; 1893 #endif /* DRV_BYTE_ORDER */ 1894 } ism330dhcx_fsm_outs16_t; 1895 1896 #define ISM330DHCX_EMB_FUNC_ODR_CFG_B 0x5FU 1897 typedef struct 1898 { 1899 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1900 uint8_t not_used_01 : 3; 1901 uint8_t fsm_odr : 2; 1902 uint8_t not_used_02 : 3; 1903 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1904 uint8_t not_used_02 : 3; 1905 uint8_t fsm_odr : 2; 1906 uint8_t not_used_01 : 3; 1907 #endif /* DRV_BYTE_ORDER */ 1908 } ism330dhcx_emb_func_odr_cfg_b_t; 1909 1910 #define ISM330DHCX_EMB_FUNC_ODR_CFG_C 0x60U 1911 typedef struct 1912 { 1913 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1914 uint8_t not_used_01 : 4; 1915 uint8_t mlc_odr : 2; 1916 uint8_t not_used_02 : 2; 1917 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1918 uint8_t not_used_02 : 2; 1919 uint8_t mlc_odr : 2; 1920 uint8_t not_used_01 : 4; 1921 #endif /* DRV_BYTE_ORDER */ 1922 } ism330dhcx_emb_func_odr_cfg_c_t; 1923 1924 #define ISM330DHCX_STEP_COUNTER_L 0x62U 1925 #define ISM330DHCX_STEP_COUNTER_H 0x63U 1926 #define ISM330DHCX_EMB_FUNC_SRC 0x64U 1927 typedef struct 1928 { 1929 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1930 uint8_t not_used_01 : 2; 1931 uint8_t stepcounter_bit_set : 1; 1932 uint8_t step_overflow : 1; 1933 uint8_t step_count_delta_ia : 1; 1934 uint8_t step_detected : 1; 1935 uint8_t not_used_02 : 1; 1936 uint8_t pedo_rst_step : 1; 1937 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1938 uint8_t pedo_rst_step : 1; 1939 uint8_t not_used_02 : 1; 1940 uint8_t step_detected : 1; 1941 uint8_t step_count_delta_ia : 1; 1942 uint8_t step_overflow : 1; 1943 uint8_t stepcounter_bit_set : 1; 1944 uint8_t not_used_01 : 2; 1945 #endif /* DRV_BYTE_ORDER */ 1946 } ism330dhcx_emb_func_src_t; 1947 1948 #define ISM330DHCX_EMB_FUNC_INIT_A 0x66U 1949 typedef struct 1950 { 1951 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1952 uint8_t not_used_01 : 3; 1953 uint8_t step_det_init : 1; 1954 uint8_t tilt_init : 1; 1955 uint8_t sig_mot_init : 1; 1956 uint8_t not_used_02 : 2; 1957 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1958 uint8_t not_used_02 : 2; 1959 uint8_t sig_mot_init : 1; 1960 uint8_t tilt_init : 1; 1961 uint8_t step_det_init : 1; 1962 uint8_t not_used_01 : 3; 1963 #endif /* DRV_BYTE_ORDER */ 1964 } ism330dhcx_emb_func_init_a_t; 1965 1966 #define ISM330DHCX_EMB_FUNC_INIT_B 0x67U 1967 typedef struct 1968 { 1969 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1970 uint8_t fsm_init : 1; 1971 uint8_t not_used_01 : 2; 1972 uint8_t fifo_compr_init : 1; 1973 uint8_t mlc_init : 1; 1974 uint8_t not_used_02 : 3; 1975 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1976 uint8_t not_used_02 : 3; 1977 uint8_t mlc_init : 1; 1978 uint8_t fifo_compr_init : 1; 1979 uint8_t not_used_01 : 2; 1980 uint8_t fsm_init : 1; 1981 #endif /* DRV_BYTE_ORDER */ 1982 } ism330dhcx_emb_func_init_b_t; 1983 1984 #define ISM330DHCX_MLC0_SRC 0x70U 1985 #define ISM330DHCX_MLC1_SRC 0x71U 1986 #define ISM330DHCX_MLC2_SRC 0x72U 1987 #define ISM330DHCX_MLC3_SRC 0x73U 1988 #define ISM330DHCX_MLC4_SRC 0x74U 1989 #define ISM330DHCX_MLC5_SRC 0x75U 1990 #define ISM330DHCX_MLC6_SRC 0x76U 1991 #define ISM330DHCX_MLC7_SRC 0x77U 1992 1993 /** @defgroup bitfields page 0 and 1 1994 * @{ 1995 * 1996 */ 1997 #define ISM330DHCX_MAG_SENSITIVITY_L 0xBAU 1998 #define ISM330DHCX_MAG_SENSITIVITY_H 0xBBU 1999 #define ISM330DHCX_MAG_OFFX_L 0xC0U 2000 #define ISM330DHCX_MAG_OFFX_H 0xC1U 2001 #define ISM330DHCX_MAG_OFFY_L 0xC2U 2002 #define ISM330DHCX_MAG_OFFY_H 0xC3U 2003 #define ISM330DHCX_MAG_OFFZ_L 0xC4U 2004 #define ISM330DHCX_MAG_OFFZ_H 0xC5U 2005 #define ISM330DHCX_MAG_SI_XX_L 0xC6U 2006 #define ISM330DHCX_MAG_SI_XX_H 0xC7U 2007 #define ISM330DHCX_MAG_SI_XY_L 0xC8U 2008 #define ISM330DHCX_MAG_SI_XY_H 0xC9U 2009 #define ISM330DHCX_MAG_SI_XZ_L 0xCAU 2010 #define ISM330DHCX_MAG_SI_XZ_H 0xCBU 2011 #define ISM330DHCX_MAG_SI_YY_L 0xCCU 2012 #define ISM330DHCX_MAG_SI_YY_H 0xCDU 2013 #define ISM330DHCX_MAG_SI_YZ_L 0xCEU 2014 #define ISM330DHCX_MAG_SI_YZ_H 0xCFU 2015 #define ISM330DHCX_MAG_SI_ZZ_L 0xD0U 2016 #define ISM330DHCX_MAG_SI_ZZ_H 0xD1U 2017 #define ISM330DHCX_MAG_CFG_A 0xD4U 2018 typedef struct 2019 { 2020 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2021 uint8_t mag_z_axis : 3; 2022 uint8_t not_used_01 : 1; 2023 uint8_t mag_y_axis : 3; 2024 uint8_t not_used_02 : 1; 2025 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2026 uint8_t not_used_02 : 1; 2027 uint8_t mag_y_axis : 3; 2028 uint8_t not_used_01 : 1; 2029 uint8_t mag_z_axis : 3; 2030 #endif /* DRV_BYTE_ORDER */ 2031 } ism330dhcx_mag_cfg_a_t; 2032 2033 #define ISM330DHCX_MAG_CFG_B 0xD5U 2034 typedef struct 2035 { 2036 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2037 uint8_t mag_x_axis : 3; 2038 uint8_t not_used_01 : 5; 2039 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2040 uint8_t not_used_01 : 5; 2041 uint8_t mag_x_axis : 3; 2042 #endif /* DRV_BYTE_ORDER */ 2043 } ism330dhcx_mag_cfg_b_t; 2044 2045 #define ISM330DHCX_FSM_LC_TIMEOUT_L 0x17AU 2046 #define ISM330DHCX_FSM_LC_TIMEOUT_H 0x17BU 2047 #define ISM330DHCX_FSM_PROGRAMS 0x17CU 2048 #define ISM330DHCX_FSM_START_ADD_L 0x17EU 2049 #define ISM330DHCX_FSM_START_ADD_H 0x17FU 2050 #define ISM330DHCX_PEDO_CMD_REG 0x183U 2051 typedef struct 2052 { 2053 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2054 uint8_t not_used_01 : 3; 2055 uint8_t carry_count_en : 1; 2056 uint8_t not_used_02 : 4; 2057 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2058 uint8_t not_used_02 : 4; 2059 uint8_t carry_count_en : 1; 2060 uint8_t not_used_01 : 3; 2061 #endif /* DRV_BYTE_ORDER */ 2062 } ism330dhcx_pedo_cmd_reg_t; 2063 2064 #define ISM330DHCX_PEDO_DEB_STEPS_CONF 0x184U 2065 #define ISM330DHCX_PEDO_SC_DELTAT_L 0x1D0U 2066 #define ISM330DHCX_PEDO_SC_DELTAT_H 0x1D1U 2067 #define ISM330DHCX_MLC_MAG_SENSITIVITY_L 0x1E8U 2068 #define ISM330DHCX_MLC_MAG_SENSITIVITY_H 0x1E9U 2069 2070 /** 2071 * @} 2072 * 2073 */ 2074 2075 /** @defgroup bitfields page sensor_hub 2076 * @{ 2077 * 2078 */ 2079 2080 #define ISM330DHCX_SENSOR_HUB_1 0x02U 2081 typedef struct 2082 { 2083 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2084 uint8_t bit0 : 1; 2085 uint8_t bit1 : 1; 2086 uint8_t bit2 : 1; 2087 uint8_t bit3 : 1; 2088 uint8_t bit4 : 1; 2089 uint8_t bit5 : 1; 2090 uint8_t bit6 : 1; 2091 uint8_t bit7 : 1; 2092 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2093 uint8_t bit7 : 1; 2094 uint8_t bit6 : 1; 2095 uint8_t bit5 : 1; 2096 uint8_t bit4 : 1; 2097 uint8_t bit3 : 1; 2098 uint8_t bit2 : 1; 2099 uint8_t bit1 : 1; 2100 uint8_t bit0 : 1; 2101 #endif /* DRV_BYTE_ORDER */ 2102 } ism330dhcx_sensor_hub_1_t; 2103 2104 #define ISM330DHCX_SENSOR_HUB_2 0x03U 2105 typedef struct 2106 { 2107 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2108 uint8_t bit0 : 1; 2109 uint8_t bit1 : 1; 2110 uint8_t bit2 : 1; 2111 uint8_t bit3 : 1; 2112 uint8_t bit4 : 1; 2113 uint8_t bit5 : 1; 2114 uint8_t bit6 : 1; 2115 uint8_t bit7 : 1; 2116 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2117 uint8_t bit7 : 1; 2118 uint8_t bit6 : 1; 2119 uint8_t bit5 : 1; 2120 uint8_t bit4 : 1; 2121 uint8_t bit3 : 1; 2122 uint8_t bit2 : 1; 2123 uint8_t bit1 : 1; 2124 uint8_t bit0 : 1; 2125 #endif /* DRV_BYTE_ORDER */ 2126 } ism330dhcx_sensor_hub_2_t; 2127 2128 #define ISM330DHCX_SENSOR_HUB_3 0x04U 2129 typedef struct 2130 { 2131 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2132 uint8_t bit0 : 1; 2133 uint8_t bit1 : 1; 2134 uint8_t bit2 : 1; 2135 uint8_t bit3 : 1; 2136 uint8_t bit4 : 1; 2137 uint8_t bit5 : 1; 2138 uint8_t bit6 : 1; 2139 uint8_t bit7 : 1; 2140 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2141 uint8_t bit7 : 1; 2142 uint8_t bit6 : 1; 2143 uint8_t bit5 : 1; 2144 uint8_t bit4 : 1; 2145 uint8_t bit3 : 1; 2146 uint8_t bit2 : 1; 2147 uint8_t bit1 : 1; 2148 uint8_t bit0 : 1; 2149 #endif /* DRV_BYTE_ORDER */ 2150 } ism330dhcx_sensor_hub_3_t; 2151 2152 #define ISM330DHCX_SENSOR_HUB_4 0x05U 2153 typedef struct 2154 { 2155 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2156 uint8_t bit0 : 1; 2157 uint8_t bit1 : 1; 2158 uint8_t bit2 : 1; 2159 uint8_t bit3 : 1; 2160 uint8_t bit4 : 1; 2161 uint8_t bit5 : 1; 2162 uint8_t bit6 : 1; 2163 uint8_t bit7 : 1; 2164 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2165 uint8_t bit7 : 1; 2166 uint8_t bit6 : 1; 2167 uint8_t bit5 : 1; 2168 uint8_t bit4 : 1; 2169 uint8_t bit3 : 1; 2170 uint8_t bit2 : 1; 2171 uint8_t bit1 : 1; 2172 uint8_t bit0 : 1; 2173 #endif /* DRV_BYTE_ORDER */ 2174 } ism330dhcx_sensor_hub_4_t; 2175 2176 #define ISM330DHCX_SENSOR_HUB_5 0x06U 2177 typedef struct 2178 { 2179 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2180 uint8_t bit0 : 1; 2181 uint8_t bit1 : 1; 2182 uint8_t bit2 : 1; 2183 uint8_t bit3 : 1; 2184 uint8_t bit4 : 1; 2185 uint8_t bit5 : 1; 2186 uint8_t bit6 : 1; 2187 uint8_t bit7 : 1; 2188 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2189 uint8_t bit7 : 1; 2190 uint8_t bit6 : 1; 2191 uint8_t bit5 : 1; 2192 uint8_t bit4 : 1; 2193 uint8_t bit3 : 1; 2194 uint8_t bit2 : 1; 2195 uint8_t bit1 : 1; 2196 uint8_t bit0 : 1; 2197 #endif /* DRV_BYTE_ORDER */ 2198 } ism330dhcx_sensor_hub_5_t; 2199 2200 #define ISM330DHCX_SENSOR_HUB_6 0x07U 2201 typedef struct 2202 { 2203 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2204 uint8_t bit0 : 1; 2205 uint8_t bit1 : 1; 2206 uint8_t bit2 : 1; 2207 uint8_t bit3 : 1; 2208 uint8_t bit4 : 1; 2209 uint8_t bit5 : 1; 2210 uint8_t bit6 : 1; 2211 uint8_t bit7 : 1; 2212 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2213 uint8_t bit7 : 1; 2214 uint8_t bit6 : 1; 2215 uint8_t bit5 : 1; 2216 uint8_t bit4 : 1; 2217 uint8_t bit3 : 1; 2218 uint8_t bit2 : 1; 2219 uint8_t bit1 : 1; 2220 uint8_t bit0 : 1; 2221 #endif /* DRV_BYTE_ORDER */ 2222 } ism330dhcx_sensor_hub_6_t; 2223 2224 #define ISM330DHCX_SENSOR_HUB_7 0x08U 2225 typedef struct 2226 { 2227 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2228 uint8_t bit0 : 1; 2229 uint8_t bit1 : 1; 2230 uint8_t bit2 : 1; 2231 uint8_t bit3 : 1; 2232 uint8_t bit4 : 1; 2233 uint8_t bit5 : 1; 2234 uint8_t bit6 : 1; 2235 uint8_t bit7 : 1; 2236 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2237 uint8_t bit7 : 1; 2238 uint8_t bit6 : 1; 2239 uint8_t bit5 : 1; 2240 uint8_t bit4 : 1; 2241 uint8_t bit3 : 1; 2242 uint8_t bit2 : 1; 2243 uint8_t bit1 : 1; 2244 uint8_t bit0 : 1; 2245 #endif /* DRV_BYTE_ORDER */ 2246 } ism330dhcx_sensor_hub_7_t; 2247 2248 #define ISM330DHCX_SENSOR_HUB_8 0x09U 2249 typedef struct 2250 { 2251 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2252 uint8_t bit0 : 1; 2253 uint8_t bit1 : 1; 2254 uint8_t bit2 : 1; 2255 uint8_t bit3 : 1; 2256 uint8_t bit4 : 1; 2257 uint8_t bit5 : 1; 2258 uint8_t bit6 : 1; 2259 uint8_t bit7 : 1; 2260 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2261 uint8_t bit7 : 1; 2262 uint8_t bit6 : 1; 2263 uint8_t bit5 : 1; 2264 uint8_t bit4 : 1; 2265 uint8_t bit3 : 1; 2266 uint8_t bit2 : 1; 2267 uint8_t bit1 : 1; 2268 uint8_t bit0 : 1; 2269 #endif /* DRV_BYTE_ORDER */ 2270 } ism330dhcx_sensor_hub_8_t; 2271 2272 #define ISM330DHCX_SENSOR_HUB_9 0x0AU 2273 typedef struct 2274 { 2275 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2276 uint8_t bit0 : 1; 2277 uint8_t bit1 : 1; 2278 uint8_t bit2 : 1; 2279 uint8_t bit3 : 1; 2280 uint8_t bit4 : 1; 2281 uint8_t bit5 : 1; 2282 uint8_t bit6 : 1; 2283 uint8_t bit7 : 1; 2284 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2285 uint8_t bit7 : 1; 2286 uint8_t bit6 : 1; 2287 uint8_t bit5 : 1; 2288 uint8_t bit4 : 1; 2289 uint8_t bit3 : 1; 2290 uint8_t bit2 : 1; 2291 uint8_t bit1 : 1; 2292 uint8_t bit0 : 1; 2293 #endif /* DRV_BYTE_ORDER */ 2294 } ism330dhcx_sensor_hub_9_t; 2295 2296 #define ISM330DHCX_SENSOR_HUB_10 0x0BU 2297 typedef struct 2298 { 2299 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2300 uint8_t bit0 : 1; 2301 uint8_t bit1 : 1; 2302 uint8_t bit2 : 1; 2303 uint8_t bit3 : 1; 2304 uint8_t bit4 : 1; 2305 uint8_t bit5 : 1; 2306 uint8_t bit6 : 1; 2307 uint8_t bit7 : 1; 2308 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2309 uint8_t bit7 : 1; 2310 uint8_t bit6 : 1; 2311 uint8_t bit5 : 1; 2312 uint8_t bit4 : 1; 2313 uint8_t bit3 : 1; 2314 uint8_t bit2 : 1; 2315 uint8_t bit1 : 1; 2316 uint8_t bit0 : 1; 2317 #endif /* DRV_BYTE_ORDER */ 2318 } ism330dhcx_sensor_hub_10_t; 2319 2320 #define ISM330DHCX_SENSOR_HUB_11 0x0CU 2321 typedef struct 2322 { 2323 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2324 uint8_t bit0 : 1; 2325 uint8_t bit1 : 1; 2326 uint8_t bit2 : 1; 2327 uint8_t bit3 : 1; 2328 uint8_t bit4 : 1; 2329 uint8_t bit5 : 1; 2330 uint8_t bit6 : 1; 2331 uint8_t bit7 : 1; 2332 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2333 uint8_t bit7 : 1; 2334 uint8_t bit6 : 1; 2335 uint8_t bit5 : 1; 2336 uint8_t bit4 : 1; 2337 uint8_t bit3 : 1; 2338 uint8_t bit2 : 1; 2339 uint8_t bit1 : 1; 2340 uint8_t bit0 : 1; 2341 #endif /* DRV_BYTE_ORDER */ 2342 } ism330dhcx_sensor_hub_11_t; 2343 2344 #define ISM330DHCX_SENSOR_HUB_12 0x0DU 2345 typedef struct 2346 { 2347 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2348 uint8_t bit0 : 1; 2349 uint8_t bit1 : 1; 2350 uint8_t bit2 : 1; 2351 uint8_t bit3 : 1; 2352 uint8_t bit4 : 1; 2353 uint8_t bit5 : 1; 2354 uint8_t bit6 : 1; 2355 uint8_t bit7 : 1; 2356 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2357 uint8_t bit7 : 1; 2358 uint8_t bit6 : 1; 2359 uint8_t bit5 : 1; 2360 uint8_t bit4 : 1; 2361 uint8_t bit3 : 1; 2362 uint8_t bit2 : 1; 2363 uint8_t bit1 : 1; 2364 uint8_t bit0 : 1; 2365 #endif /* DRV_BYTE_ORDER */ 2366 } ism330dhcx_sensor_hub_12_t; 2367 2368 #define ISM330DHCX_SENSOR_HUB_13 0x0EU 2369 typedef struct 2370 { 2371 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2372 uint8_t bit0 : 1; 2373 uint8_t bit1 : 1; 2374 uint8_t bit2 : 1; 2375 uint8_t bit3 : 1; 2376 uint8_t bit4 : 1; 2377 uint8_t bit5 : 1; 2378 uint8_t bit6 : 1; 2379 uint8_t bit7 : 1; 2380 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2381 uint8_t bit7 : 1; 2382 uint8_t bit6 : 1; 2383 uint8_t bit5 : 1; 2384 uint8_t bit4 : 1; 2385 uint8_t bit3 : 1; 2386 uint8_t bit2 : 1; 2387 uint8_t bit1 : 1; 2388 uint8_t bit0 : 1; 2389 #endif /* DRV_BYTE_ORDER */ 2390 } ism330dhcx_sensor_hub_13_t; 2391 2392 #define ISM330DHCX_SENSOR_HUB_14 0x0FU 2393 typedef struct 2394 { 2395 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2396 uint8_t bit0 : 1; 2397 uint8_t bit1 : 1; 2398 uint8_t bit2 : 1; 2399 uint8_t bit3 : 1; 2400 uint8_t bit4 : 1; 2401 uint8_t bit5 : 1; 2402 uint8_t bit6 : 1; 2403 uint8_t bit7 : 1; 2404 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2405 uint8_t bit7 : 1; 2406 uint8_t bit6 : 1; 2407 uint8_t bit5 : 1; 2408 uint8_t bit4 : 1; 2409 uint8_t bit3 : 1; 2410 uint8_t bit2 : 1; 2411 uint8_t bit1 : 1; 2412 uint8_t bit0 : 1; 2413 #endif /* DRV_BYTE_ORDER */ 2414 } ism330dhcx_sensor_hub_14_t; 2415 2416 #define ISM330DHCX_SENSOR_HUB_15 0x10U 2417 typedef struct 2418 { 2419 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2420 uint8_t bit0 : 1; 2421 uint8_t bit1 : 1; 2422 uint8_t bit2 : 1; 2423 uint8_t bit3 : 1; 2424 uint8_t bit4 : 1; 2425 uint8_t bit5 : 1; 2426 uint8_t bit6 : 1; 2427 uint8_t bit7 : 1; 2428 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2429 uint8_t bit7 : 1; 2430 uint8_t bit6 : 1; 2431 uint8_t bit5 : 1; 2432 uint8_t bit4 : 1; 2433 uint8_t bit3 : 1; 2434 uint8_t bit2 : 1; 2435 uint8_t bit1 : 1; 2436 uint8_t bit0 : 1; 2437 #endif /* DRV_BYTE_ORDER */ 2438 } ism330dhcx_sensor_hub_15_t; 2439 2440 #define ISM330DHCX_SENSOR_HUB_16 0x11U 2441 typedef struct 2442 { 2443 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2444 uint8_t bit0 : 1; 2445 uint8_t bit1 : 1; 2446 uint8_t bit2 : 1; 2447 uint8_t bit3 : 1; 2448 uint8_t bit4 : 1; 2449 uint8_t bit5 : 1; 2450 uint8_t bit6 : 1; 2451 uint8_t bit7 : 1; 2452 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2453 uint8_t bit7 : 1; 2454 uint8_t bit6 : 1; 2455 uint8_t bit5 : 1; 2456 uint8_t bit4 : 1; 2457 uint8_t bit3 : 1; 2458 uint8_t bit2 : 1; 2459 uint8_t bit1 : 1; 2460 uint8_t bit0 : 1; 2461 #endif /* DRV_BYTE_ORDER */ 2462 } ism330dhcx_sensor_hub_16_t; 2463 2464 #define ISM330DHCX_SENSOR_HUB_17 0x12U 2465 typedef struct 2466 { 2467 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2468 uint8_t bit0 : 1; 2469 uint8_t bit1 : 1; 2470 uint8_t bit2 : 1; 2471 uint8_t bit3 : 1; 2472 uint8_t bit4 : 1; 2473 uint8_t bit5 : 1; 2474 uint8_t bit6 : 1; 2475 uint8_t bit7 : 1; 2476 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2477 uint8_t bit7 : 1; 2478 uint8_t bit6 : 1; 2479 uint8_t bit5 : 1; 2480 uint8_t bit4 : 1; 2481 uint8_t bit3 : 1; 2482 uint8_t bit2 : 1; 2483 uint8_t bit1 : 1; 2484 uint8_t bit0 : 1; 2485 #endif /* DRV_BYTE_ORDER */ 2486 } ism330dhcx_sensor_hub_17_t; 2487 2488 #define ISM330DHCX_SENSOR_HUB_18 0x13U 2489 typedef struct 2490 { 2491 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2492 uint8_t bit0 : 1; 2493 uint8_t bit1 : 1; 2494 uint8_t bit2 : 1; 2495 uint8_t bit3 : 1; 2496 uint8_t bit4 : 1; 2497 uint8_t bit5 : 1; 2498 uint8_t bit6 : 1; 2499 uint8_t bit7 : 1; 2500 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2501 uint8_t bit7 : 1; 2502 uint8_t bit6 : 1; 2503 uint8_t bit5 : 1; 2504 uint8_t bit4 : 1; 2505 uint8_t bit3 : 1; 2506 uint8_t bit2 : 1; 2507 uint8_t bit1 : 1; 2508 uint8_t bit0 : 1; 2509 #endif /* DRV_BYTE_ORDER */ 2510 } ism330dhcx_sensor_hub_18_t; 2511 2512 #define ISM330DHCX_MASTER_CONFIG 0x14U 2513 typedef struct 2514 { 2515 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2516 uint8_t aux_sens_on : 2; 2517 uint8_t master_on : 1; 2518 uint8_t shub_pu_en : 1; 2519 uint8_t pass_through_mode : 1; 2520 uint8_t start_config : 1; 2521 uint8_t write_once : 1; 2522 uint8_t rst_master_regs : 1; 2523 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2524 uint8_t rst_master_regs : 1; 2525 uint8_t write_once : 1; 2526 uint8_t start_config : 1; 2527 uint8_t pass_through_mode : 1; 2528 uint8_t shub_pu_en : 1; 2529 uint8_t master_on : 1; 2530 uint8_t aux_sens_on : 2; 2531 #endif /* DRV_BYTE_ORDER */ 2532 } ism330dhcx_master_config_t; 2533 2534 #define ISM330DHCX_SLV0_ADD 0x15U 2535 typedef struct 2536 { 2537 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2538 uint8_t rw_0 : 1; 2539 uint8_t slave0 : 7; 2540 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2541 uint8_t slave0 : 7; 2542 uint8_t rw_0 : 1; 2543 #endif /* DRV_BYTE_ORDER */ 2544 } ism330dhcx_slv0_add_t; 2545 2546 #define ISM330DHCX_SLV0_SUBADD 0x16U 2547 typedef struct 2548 { 2549 uint8_t slave0_reg : 8; 2550 } ism330dhcx_slv0_subadd_t; 2551 2552 #define ISM330DHCX_SLV0_CONFIG 0x17U 2553 typedef struct 2554 { 2555 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2556 uint8_t slave0_numop : 3; 2557 uint8_t batch_ext_sens_0_en : 1; 2558 uint8_t not_used_01 : 2; 2559 uint8_t shub_odr : 2; 2560 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2561 uint8_t shub_odr : 2; 2562 uint8_t not_used_01 : 2; 2563 uint8_t batch_ext_sens_0_en : 1; 2564 uint8_t slave0_numop : 3; 2565 #endif /* DRV_BYTE_ORDER */ 2566 } ism330dhcx_slv0_config_t; 2567 2568 #define ISM330DHCX_SLV1_ADD 0x18U 2569 typedef struct 2570 { 2571 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2572 uint8_t r_1 : 1; 2573 uint8_t slave1_add : 7; 2574 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2575 uint8_t slave1_add : 7; 2576 uint8_t r_1 : 1; 2577 #endif /* DRV_BYTE_ORDER */ 2578 } ism330dhcx_slv1_add_t; 2579 2580 #define ISM330DHCX_SLV1_SUBADD 0x19U 2581 typedef struct 2582 { 2583 uint8_t slave1_reg : 8; 2584 } ism330dhcx_slv1_subadd_t; 2585 2586 #define ISM330DHCX_SLV1_CONFIG 0x1AU 2587 typedef struct 2588 { 2589 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2590 uint8_t slave1_numop : 3; 2591 uint8_t batch_ext_sens_1_en : 1; 2592 uint8_t not_used_01 : 4; 2593 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2594 uint8_t not_used_01 : 4; 2595 uint8_t batch_ext_sens_1_en : 1; 2596 uint8_t slave1_numop : 3; 2597 #endif /* DRV_BYTE_ORDER */ 2598 } ism330dhcx_slv1_config_t; 2599 2600 #define ISM330DHCX_SLV2_ADD 0x1BU 2601 typedef struct 2602 { 2603 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2604 uint8_t r_2 : 1; 2605 uint8_t slave2_add : 7; 2606 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2607 uint8_t slave2_add : 7; 2608 uint8_t r_2 : 1; 2609 #endif /* DRV_BYTE_ORDER */ 2610 } ism330dhcx_slv2_add_t; 2611 2612 #define ISM330DHCX_SLV2_SUBADD 0x1CU 2613 typedef struct 2614 { 2615 uint8_t slave2_reg : 8; 2616 } ism330dhcx_slv2_subadd_t; 2617 2618 #define ISM330DHCX_SLV2_CONFIG 0x1DU 2619 typedef struct 2620 { 2621 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2622 uint8_t slave2_numop : 3; 2623 uint8_t batch_ext_sens_2_en : 1; 2624 uint8_t not_used_01 : 4; 2625 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2626 uint8_t not_used_01 : 4; 2627 uint8_t batch_ext_sens_2_en : 1; 2628 uint8_t slave2_numop : 3; 2629 #endif /* DRV_BYTE_ORDER */ 2630 } ism330dhcx_slv2_config_t; 2631 2632 #define ISM330DHCX_SLV3_ADD 0x1EU 2633 typedef struct 2634 { 2635 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2636 uint8_t r_3 : 1; 2637 uint8_t slave3_add : 7; 2638 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2639 uint8_t slave3_add : 7; 2640 uint8_t r_3 : 1; 2641 #endif /* DRV_BYTE_ORDER */ 2642 } ism330dhcx_slv3_add_t; 2643 2644 #define ISM330DHCX_SLV3_SUBADD 0x1FU 2645 typedef struct 2646 { 2647 uint8_t slave3_reg : 8; 2648 } ism330dhcx_slv3_subadd_t; 2649 2650 #define ISM330DHCX_SLV3_CONFIG 0x20U 2651 typedef struct 2652 { 2653 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2654 uint8_t slave3_numop : 3; 2655 uint8_t batch_ext_sens_3_en : 1; 2656 uint8_t not_used_01 : 4; 2657 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2658 uint8_t not_used_01 : 4; 2659 uint8_t batch_ext_sens_3_en : 1; 2660 uint8_t slave3_numop : 3; 2661 #endif /* DRV_BYTE_ORDER */ 2662 } ism330dhcx_slv3_config_t; 2663 2664 #define ISM330DHCX_DATAWRITE_SLV0 0x21U 2665 typedef struct 2666 { 2667 uint8_t slave0_dataw : 8; 2668 } ism330dhcx_datawrite_slv0_t; 2669 2670 #define ISM330DHCX_STATUS_MASTER 0x22U 2671 typedef struct 2672 { 2673 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2674 uint8_t sens_hub_endop : 1; 2675 uint8_t not_used_01 : 2; 2676 uint8_t slave0_nack : 1; 2677 uint8_t slave1_nack : 1; 2678 uint8_t slave2_nack : 1; 2679 uint8_t slave3_nack : 1; 2680 uint8_t wr_once_done : 1; 2681 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2682 uint8_t wr_once_done : 1; 2683 uint8_t slave3_nack : 1; 2684 uint8_t slave2_nack : 1; 2685 uint8_t slave1_nack : 1; 2686 uint8_t slave0_nack : 1; 2687 uint8_t not_used_01 : 2; 2688 uint8_t sens_hub_endop : 1; 2689 #endif /* DRV_BYTE_ORDER */ 2690 } ism330dhcx_status_master_t; 2691 2692 /** 2693 * @} 2694 * 2695 */ 2696 2697 /** 2698 * @defgroup ISM330DHCX_Register_Union 2699 * @brief This union group all the registers having a bit-field 2700 * description. 2701 * This union is useful but it's not needed by the driver. 2702 * 2703 * REMOVING this union you are compliant with: 2704 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 2705 * 2706 * @{ 2707 * 2708 */ 2709 typedef union 2710 { 2711 ism330dhcx_func_cfg_access_t func_cfg_access; 2712 ism330dhcx_pin_ctrl_t pin_ctrl; 2713 ism330dhcx_fifo_ctrl1_t fifo_ctrl1; 2714 ism330dhcx_fifo_ctrl2_t fifo_ctrl2; 2715 ism330dhcx_fifo_ctrl3_t fifo_ctrl3; 2716 ism330dhcx_fifo_ctrl4_t fifo_ctrl4; 2717 ism330dhcx_counter_bdr_reg1_t counter_bdr_reg1; 2718 ism330dhcx_counter_bdr_reg2_t counter_bdr_reg2; 2719 ism330dhcx_int1_ctrl_t int1_ctrl; 2720 ism330dhcx_int2_ctrl_t int2_ctrl; 2721 ism330dhcx_ctrl1_xl_t ctrl1_xl; 2722 ism330dhcx_ctrl2_g_t ctrl2_g; 2723 ism330dhcx_ctrl3_c_t ctrl3_c; 2724 ism330dhcx_ctrl4_c_t ctrl4_c; 2725 ism330dhcx_ctrl5_c_t ctrl5_c; 2726 ism330dhcx_ctrl6_c_t ctrl6_c; 2727 ism330dhcx_ctrl7_g_t ctrl7_g; 2728 ism330dhcx_ctrl8_xl_t ctrl8_xl; 2729 ism330dhcx_ctrl9_xl_t ctrl9_xl; 2730 ism330dhcx_ctrl10_c_t ctrl10_c; 2731 ism330dhcx_all_int_src_t all_int_src; 2732 ism330dhcx_wake_up_src_t wake_up_src; 2733 ism330dhcx_tap_src_t tap_src; 2734 ism330dhcx_d6d_src_t d6d_src; 2735 ism330dhcx_status_reg_t status_reg; 2736 ism330dhcx_status_spiaux_t status_spiaux; 2737 ism330dhcx_fifo_status1_t fifo_status1; 2738 ism330dhcx_fifo_status2_t fifo_status2; 2739 ism330dhcx_tap_cfg0_t tap_cfg0; 2740 ism330dhcx_tap_cfg1_t tap_cfg1; 2741 ism330dhcx_tap_cfg2_t tap_cfg2; 2742 ism330dhcx_tap_ths_6d_t tap_ths_6d; 2743 ism330dhcx_int_dur2_t int_dur2; 2744 ism330dhcx_wake_up_ths_t wake_up_ths; 2745 ism330dhcx_wake_up_dur_t wake_up_dur; 2746 ism330dhcx_free_fall_t free_fall; 2747 ism330dhcx_md1_cfg_t md1_cfg; 2748 ism330dhcx_md2_cfg_t md2_cfg; 2749 ism330dhcx_internal_freq_fine_t internal_freq_fine; 2750 ism330dhcx_int_ois_t int_ois; 2751 ism330dhcx_ctrl1_ois_t ctrl1_ois; 2752 ism330dhcx_ctrl2_ois_t ctrl2_ois; 2753 ism330dhcx_ctrl3_ois_t ctrl3_ois; 2754 ism330dhcx_fifo_data_out_tag_t fifo_data_out_tag; 2755 ism330dhcx_page_sel_t page_sel; 2756 ism330dhcx_emb_func_en_a_t emb_func_en_a; 2757 ism330dhcx_emb_func_en_b_t emb_func_en_b; 2758 ism330dhcx_page_address_t page_address; 2759 ism330dhcx_page_value_t page_value; 2760 ism330dhcx_emb_func_int1_t emb_func_int1; 2761 ism330dhcx_fsm_int1_a_t fsm_int1_a; 2762 ism330dhcx_fsm_int1_b_t fsm_int1_b; 2763 ism330dhcx_mlc_int1_t mlc_int1; 2764 ism330dhcx_emb_func_int2_t emb_func_int2; 2765 ism330dhcx_fsm_int2_a_t fsm_int2_a; 2766 ism330dhcx_fsm_int2_b_t fsm_int2_b; 2767 ism330dhcx_mlc_int2_t mlc_int2; 2768 ism330dhcx_emb_func_status_t emb_func_status; 2769 ism330dhcx_fsm_status_a_t fsm_status_a; 2770 ism330dhcx_fsm_status_b_t fsm_status_b; 2771 ism330dhcx_mlc_status_mainpage_t mlc_status_mainpage; 2772 ism330dhcx_page_rw_t page_rw; 2773 ism330dhcx_emb_func_fifo_cfg_t emb_func_fifo_cfg; 2774 ism330dhcx_fsm_enable_a_t fsm_enable_a; 2775 ism330dhcx_fsm_enable_b_t fsm_enable_b; 2776 ism330dhcx_fsm_long_counter_clear_t fsm_long_counter_clear; 2777 ism330dhcx_fsm_outs1_t fsm_outs1; 2778 ism330dhcx_fsm_outs2_t fsm_outs2; 2779 ism330dhcx_fsm_outs3_t fsm_outs3; 2780 ism330dhcx_fsm_outs4_t fsm_outs4; 2781 ism330dhcx_fsm_outs5_t fsm_outs5; 2782 ism330dhcx_fsm_outs6_t fsm_outs6; 2783 ism330dhcx_fsm_outs7_t fsm_outs7; 2784 ism330dhcx_fsm_outs8_t fsm_outs8; 2785 ism330dhcx_fsm_outs9_t fsm_outs9; 2786 ism330dhcx_fsm_outs10_t fsm_outs10; 2787 ism330dhcx_fsm_outs11_t fsm_outs11; 2788 ism330dhcx_fsm_outs12_t fsm_outs12; 2789 ism330dhcx_fsm_outs13_t fsm_outs13; 2790 ism330dhcx_fsm_outs14_t fsm_outs14; 2791 ism330dhcx_fsm_outs15_t fsm_outs15; 2792 ism330dhcx_fsm_outs16_t fsm_outs16; 2793 ism330dhcx_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; 2794 ism330dhcx_emb_func_odr_cfg_c_t emb_func_odr_cfg_c_t; 2795 ism330dhcx_emb_func_src_t emb_func_src; 2796 ism330dhcx_emb_func_init_a_t emb_func_init_a; 2797 ism330dhcx_emb_func_init_b_t emb_func_init_b; 2798 ism330dhcx_mag_cfg_a_t mag_cfg_a; 2799 ism330dhcx_mag_cfg_b_t mag_cfg_b; 2800 ism330dhcx_pedo_cmd_reg_t pedo_cmd_reg; 2801 ism330dhcx_sensor_hub_1_t sensor_hub_1; 2802 ism330dhcx_sensor_hub_2_t sensor_hub_2; 2803 ism330dhcx_sensor_hub_3_t sensor_hub_3; 2804 ism330dhcx_sensor_hub_4_t sensor_hub_4; 2805 ism330dhcx_sensor_hub_5_t sensor_hub_5; 2806 ism330dhcx_sensor_hub_6_t sensor_hub_6; 2807 ism330dhcx_sensor_hub_7_t sensor_hub_7; 2808 ism330dhcx_sensor_hub_8_t sensor_hub_8; 2809 ism330dhcx_sensor_hub_9_t sensor_hub_9; 2810 ism330dhcx_sensor_hub_10_t sensor_hub_10; 2811 ism330dhcx_sensor_hub_11_t sensor_hub_11; 2812 ism330dhcx_sensor_hub_12_t sensor_hub_12; 2813 ism330dhcx_sensor_hub_13_t sensor_hub_13; 2814 ism330dhcx_sensor_hub_14_t sensor_hub_14; 2815 ism330dhcx_sensor_hub_15_t sensor_hub_15; 2816 ism330dhcx_sensor_hub_16_t sensor_hub_16; 2817 ism330dhcx_sensor_hub_17_t sensor_hub_17; 2818 ism330dhcx_sensor_hub_18_t sensor_hub_18; 2819 ism330dhcx_master_config_t master_config; 2820 ism330dhcx_slv0_add_t slv0_add; 2821 ism330dhcx_slv0_subadd_t slv0_subadd; 2822 ism330dhcx_slv0_config_t slv0_config; 2823 ism330dhcx_slv1_add_t slv1_add; 2824 ism330dhcx_slv1_subadd_t slv1_subadd; 2825 ism330dhcx_slv1_config_t slv1_config; 2826 ism330dhcx_slv2_add_t slv2_add; 2827 ism330dhcx_slv2_subadd_t slv2_subadd; 2828 ism330dhcx_slv2_config_t slv2_config; 2829 ism330dhcx_slv3_add_t slv3_add; 2830 ism330dhcx_slv3_subadd_t slv3_subadd; 2831 ism330dhcx_slv3_config_t slv3_config; 2832 ism330dhcx_datawrite_slv0_t datawrite_slv0; 2833 ism330dhcx_status_master_t status_master; 2834 bitwise_t bitwise; 2835 uint8_t byte; 2836 } ism330dhcx_reg_t; 2837 2838 /** 2839 * @} 2840 * 2841 */ 2842 2843 #ifndef __weak 2844 #define __weak __attribute__((weak)) 2845 #endif /* __weak */ 2846 2847 /* 2848 * These are the basic platform dependent I/O routines to read 2849 * and write device registers connected on a standard bus. 2850 * The driver keeps offering a default implementation based on function 2851 * pointers to read/write routines for backward compatibility. 2852 * The __weak directive allows the final application to overwrite 2853 * them with a custom implementation. 2854 */ 2855 int32_t ism330dhcx_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 2856 uint8_t *data, 2857 uint16_t len); 2858 int32_t ism330dhcx_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 2859 uint8_t *data, 2860 uint16_t len); 2861 2862 float_t ism330dhcx_from_fs2g_to_mg(int16_t lsb); 2863 float_t ism330dhcx_from_fs4g_to_mg(int16_t lsb); 2864 float_t ism330dhcx_from_fs8g_to_mg(int16_t lsb); 2865 float_t ism330dhcx_from_fs16g_to_mg(int16_t lsb); 2866 2867 float_t ism330dhcx_from_fs125dps_to_mdps(int16_t lsb); 2868 float_t ism330dhcx_from_fs250dps_to_mdps(int16_t lsb); 2869 float_t ism330dhcx_from_fs500dps_to_mdps(int16_t lsb); 2870 float_t ism330dhcx_from_fs1000dps_to_mdps(int16_t lsb); 2871 float_t ism330dhcx_from_fs2000dps_to_mdps(int16_t lsb); 2872 float_t ism330dhcx_from_fs4000dps_to_mdps(int16_t lsb); 2873 2874 float_t ism330dhcx_from_lsb_to_celsius(int16_t lsb); 2875 2876 uint64_t ism330dhcx_from_lsb_to_nsec(uint32_t lsb); 2877 2878 typedef enum 2879 { 2880 ISM330DHCX_2g = 0, 2881 ISM330DHCX_16g = 1, /* if XL_FS_MODE = '1' -> ISM330DHCX_2g */ 2882 ISM330DHCX_4g = 2, 2883 ISM330DHCX_8g = 3, 2884 } ism330dhcx_fs_xl_t; 2885 int32_t ism330dhcx_xl_full_scale_set(const stmdev_ctx_t *ctx, 2886 ism330dhcx_fs_xl_t val); 2887 int32_t ism330dhcx_xl_full_scale_get(const stmdev_ctx_t *ctx, 2888 ism330dhcx_fs_xl_t *val); 2889 2890 typedef enum 2891 { 2892 ISM330DHCX_XL_ODR_OFF = 0, 2893 ISM330DHCX_XL_ODR_12Hz5 = 1, 2894 ISM330DHCX_XL_ODR_26Hz = 2, 2895 ISM330DHCX_XL_ODR_52Hz = 3, 2896 ISM330DHCX_XL_ODR_104Hz = 4, 2897 ISM330DHCX_XL_ODR_208Hz = 5, 2898 ISM330DHCX_XL_ODR_416Hz = 6, 2899 ISM330DHCX_XL_ODR_833Hz = 7, 2900 ISM330DHCX_XL_ODR_1666Hz = 8, 2901 ISM330DHCX_XL_ODR_3332Hz = 9, 2902 ISM330DHCX_XL_ODR_6667Hz = 10, 2903 ISM330DHCX_XL_ODR_1Hz6 = 11, /* (low power only) */ 2904 } ism330dhcx_odr_xl_t; 2905 int32_t ism330dhcx_xl_data_rate_set(const stmdev_ctx_t *ctx, 2906 ism330dhcx_odr_xl_t val); 2907 int32_t ism330dhcx_xl_data_rate_get(const stmdev_ctx_t *ctx, 2908 ism330dhcx_odr_xl_t *val); 2909 2910 typedef enum 2911 { 2912 ISM330DHCX_125dps = 2, 2913 ISM330DHCX_250dps = 0, 2914 ISM330DHCX_500dps = 4, 2915 ISM330DHCX_1000dps = 8, 2916 ISM330DHCX_2000dps = 12, 2917 ISM330DHCX_4000dps = 1, 2918 } ism330dhcx_fs_g_t; 2919 int32_t ism330dhcx_gy_full_scale_set(const stmdev_ctx_t *ctx, 2920 ism330dhcx_fs_g_t val); 2921 int32_t ism330dhcx_gy_full_scale_get(const stmdev_ctx_t *ctx, 2922 ism330dhcx_fs_g_t *val); 2923 2924 typedef enum 2925 { 2926 ISM330DHCX_GY_ODR_OFF = 0, 2927 ISM330DHCX_GY_ODR_12Hz5 = 1, 2928 ISM330DHCX_GY_ODR_26Hz = 2, 2929 ISM330DHCX_GY_ODR_52Hz = 3, 2930 ISM330DHCX_GY_ODR_104Hz = 4, 2931 ISM330DHCX_GY_ODR_208Hz = 5, 2932 ISM330DHCX_GY_ODR_416Hz = 6, 2933 ISM330DHCX_GY_ODR_833Hz = 7, 2934 ISM330DHCX_GY_ODR_1666Hz = 8, 2935 ISM330DHCX_GY_ODR_3332Hz = 9, 2936 ISM330DHCX_GY_ODR_6667Hz = 10, 2937 } ism330dhcx_odr_g_t; 2938 int32_t ism330dhcx_gy_data_rate_set(const stmdev_ctx_t *ctx, 2939 ism330dhcx_odr_g_t val); 2940 int32_t ism330dhcx_gy_data_rate_get(const stmdev_ctx_t *ctx, 2941 ism330dhcx_odr_g_t *val); 2942 2943 int32_t ism330dhcx_block_data_update_set(const stmdev_ctx_t *ctx, 2944 uint8_t val); 2945 int32_t ism330dhcx_block_data_update_get(const stmdev_ctx_t *ctx, 2946 uint8_t *val); 2947 2948 typedef enum 2949 { 2950 ISM330DHCX_LSb_1mg = 0, 2951 ISM330DHCX_LSb_16mg = 1, 2952 } ism330dhcx_usr_off_w_t; 2953 int32_t ism330dhcx_xl_offset_weight_set(const stmdev_ctx_t *ctx, 2954 ism330dhcx_usr_off_w_t val); 2955 int32_t ism330dhcx_xl_offset_weight_get(const stmdev_ctx_t *ctx, 2956 ism330dhcx_usr_off_w_t *val); 2957 2958 typedef enum 2959 { 2960 ISM330DHCX_HIGH_PERFORMANCE_MD = 0, 2961 ISM330DHCX_LOW_NORMAL_POWER_MD = 1, 2962 } ism330dhcx_xl_hm_mode_t; 2963 int32_t ism330dhcx_xl_power_mode_set(const stmdev_ctx_t *ctx, 2964 ism330dhcx_xl_hm_mode_t val); 2965 int32_t ism330dhcx_xl_power_mode_get(const stmdev_ctx_t *ctx, 2966 ism330dhcx_xl_hm_mode_t *val); 2967 2968 typedef enum 2969 { 2970 ISM330DHCX_GY_HIGH_PERFORMANCE = 0, 2971 ISM330DHCX_GY_NORMAL = 1, 2972 } ism330dhcx_g_hm_mode_t; 2973 int32_t ism330dhcx_gy_power_mode_set(const stmdev_ctx_t *ctx, 2974 ism330dhcx_g_hm_mode_t val); 2975 int32_t ism330dhcx_gy_power_mode_get(const stmdev_ctx_t *ctx, 2976 ism330dhcx_g_hm_mode_t *val); 2977 2978 typedef struct 2979 { 2980 ism330dhcx_all_int_src_t all_int_src; 2981 ism330dhcx_wake_up_src_t wake_up_src; 2982 ism330dhcx_tap_src_t tap_src; 2983 ism330dhcx_d6d_src_t d6d_src; 2984 ism330dhcx_status_reg_t status_reg; 2985 ism330dhcx_emb_func_status_t emb_func_status; 2986 ism330dhcx_fsm_status_a_t fsm_status_a; 2987 ism330dhcx_fsm_status_b_t fsm_status_b; 2988 ism330dhcx_mlc_status_mainpage_t mlc_status; 2989 } ism330dhcx_all_sources_t; 2990 int32_t ism330dhcx_all_sources_get(const stmdev_ctx_t *ctx, 2991 ism330dhcx_all_sources_t *val); 2992 2993 int32_t ism330dhcx_status_reg_get(const stmdev_ctx_t *ctx, 2994 ism330dhcx_status_reg_t *val); 2995 2996 int32_t ism330dhcx_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, 2997 uint8_t *val); 2998 2999 int32_t ism330dhcx_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, 3000 uint8_t *val); 3001 3002 int32_t ism330dhcx_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, 3003 uint8_t *val); 3004 3005 int32_t ism330dhcx_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, 3006 uint8_t *val); 3007 int32_t ism330dhcx_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, 3008 uint8_t *val); 3009 3010 int32_t ism330dhcx_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, 3011 uint8_t *val); 3012 int32_t ism330dhcx_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, 3013 uint8_t *val); 3014 3015 int32_t ism330dhcx_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, 3016 uint8_t *val); 3017 int32_t ism330dhcx_xl_usr_offset_z_get(const stmdev_ctx_t *ctx, 3018 uint8_t *val); 3019 3020 int32_t ism330dhcx_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val); 3021 int32_t ism330dhcx_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val); 3022 3023 int32_t ism330dhcx_timestamp_rst(const stmdev_ctx_t *ctx); 3024 3025 int32_t ism330dhcx_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); 3026 int32_t ism330dhcx_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); 3027 3028 int32_t ism330dhcx_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val); 3029 3030 typedef enum 3031 { 3032 ISM330DHCX_NO_ROUND = 0, 3033 ISM330DHCX_ROUND_XL = 1, 3034 ISM330DHCX_ROUND_GY = 2, 3035 ISM330DHCX_ROUND_GY_XL = 3, 3036 } ism330dhcx_rounding_t; 3037 int32_t ism330dhcx_rounding_mode_set(const stmdev_ctx_t *ctx, 3038 ism330dhcx_rounding_t val); 3039 int32_t ism330dhcx_rounding_mode_get(const stmdev_ctx_t *ctx, 3040 ism330dhcx_rounding_t *val); 3041 3042 int32_t ism330dhcx_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 3043 3044 int32_t ism330dhcx_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 3045 3046 int32_t ism330dhcx_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 3047 3048 int32_t ism330dhcx_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *val); 3049 3050 int32_t ism330dhcx_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *val); 3051 3052 int32_t ism330dhcx_device_conf_set(const stmdev_ctx_t *ctx, uint8_t val); 3053 int32_t ism330dhcx_device_conf_get(const stmdev_ctx_t *ctx, uint8_t *val); 3054 3055 int32_t ism330dhcx_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val); 3056 int32_t ism330dhcx_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val); 3057 3058 int32_t ism330dhcx_number_of_steps_get(const stmdev_ctx_t *ctx, uint16_t *val); 3059 3060 int32_t ism330dhcx_steps_reset(const stmdev_ctx_t *ctx); 3061 3062 typedef enum 3063 { 3064 ISM330DHCX_USER_BANK = 0, 3065 ISM330DHCX_SENSOR_HUB_BANK = 1, 3066 ISM330DHCX_EMBEDDED_FUNC_BANK = 2, 3067 } ism330dhcx_reg_access_t; 3068 int32_t ism330dhcx_mem_bank_set(const stmdev_ctx_t *ctx, 3069 ism330dhcx_reg_access_t val); 3070 int32_t ism330dhcx_mem_bank_get(const stmdev_ctx_t *ctx, 3071 ism330dhcx_reg_access_t *val); 3072 3073 int32_t ism330dhcx_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t address, 3074 uint8_t *val); 3075 int32_t ism330dhcx_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, 3076 uint8_t *buf, uint8_t len); 3077 int32_t ism330dhcx_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t add, 3078 uint8_t *val); 3079 int32_t ism330dhcx_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, 3080 uint8_t *val); 3081 3082 typedef enum 3083 { 3084 ISM330DHCX_DRDY_LATCHED = 0, 3085 ISM330DHCX_DRDY_PULSED = 1, 3086 } ism330dhcx_dataready_pulsed_t; 3087 int32_t ism330dhcx_data_ready_mode_set(const stmdev_ctx_t *ctx, 3088 ism330dhcx_dataready_pulsed_t val); 3089 int32_t ism330dhcx_data_ready_mode_get(const stmdev_ctx_t *ctx, 3090 ism330dhcx_dataready_pulsed_t *val); 3091 3092 int32_t ism330dhcx_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val); 3093 3094 int32_t ism330dhcx_reset_set(const stmdev_ctx_t *ctx, uint8_t val); 3095 int32_t ism330dhcx_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); 3096 3097 int32_t ism330dhcx_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); 3098 int32_t ism330dhcx_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); 3099 3100 int32_t ism330dhcx_boot_set(const stmdev_ctx_t *ctx, uint8_t val); 3101 int32_t ism330dhcx_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); 3102 3103 typedef enum 3104 { 3105 ISM330DHCX_XL_ST_DISABLE = 0, 3106 ISM330DHCX_XL_ST_POSITIVE = 1, 3107 ISM330DHCX_XL_ST_NEGATIVE = 2, 3108 } ism330dhcx_st_xl_t; 3109 int32_t ism330dhcx_xl_self_test_set(const stmdev_ctx_t *ctx, 3110 ism330dhcx_st_xl_t val); 3111 int32_t ism330dhcx_xl_self_test_get(const stmdev_ctx_t *ctx, 3112 ism330dhcx_st_xl_t *val); 3113 3114 typedef enum 3115 { 3116 ISM330DHCX_GY_ST_DISABLE = 0, 3117 ISM330DHCX_GY_ST_POSITIVE = 1, 3118 ISM330DHCX_GY_ST_NEGATIVE = 3, 3119 } ism330dhcx_st_g_t; 3120 int32_t ism330dhcx_gy_self_test_set(const stmdev_ctx_t *ctx, 3121 ism330dhcx_st_g_t val); 3122 int32_t ism330dhcx_gy_self_test_get(const stmdev_ctx_t *ctx, 3123 ism330dhcx_st_g_t *val); 3124 3125 int32_t ism330dhcx_xl_filter_lp2_set(const stmdev_ctx_t *ctx, uint8_t val); 3126 int32_t ism330dhcx_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val); 3127 3128 int32_t ism330dhcx_gy_filter_lp1_set(const stmdev_ctx_t *ctx, uint8_t val); 3129 int32_t ism330dhcx_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val); 3130 3131 int32_t ism330dhcx_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val); 3132 int32_t ism330dhcx_filter_settling_mask_get(const stmdev_ctx_t *ctx, uint8_t *val); 3133 3134 typedef enum 3135 { 3136 ISM330DHCX_ULTRA_LIGHT = 0, 3137 ISM330DHCX_VERY_LIGHT = 1, 3138 ISM330DHCX_LIGHT = 2, 3139 ISM330DHCX_MEDIUM = 3, 3140 ISM330DHCX_STRONG = 4, 3141 ISM330DHCX_VERY_STRONG = 5, 3142 ISM330DHCX_AGGRESSIVE = 6, 3143 ISM330DHCX_XTREME = 7, 3144 } ism330dhcx_ftype_t; 3145 int32_t ism330dhcx_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, 3146 ism330dhcx_ftype_t val); 3147 int32_t ism330dhcx_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, 3148 ism330dhcx_ftype_t *val); 3149 3150 int32_t ism330dhcx_xl_lp2_on_6d_set(const stmdev_ctx_t *ctx, uint8_t val); 3151 int32_t ism330dhcx_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val); 3152 3153 typedef enum 3154 { 3155 ISM330DHCX_HP_PATH_DISABLE_ON_OUT = 0x00, 3156 ISM330DHCX_SLOPE_ODR_DIV_4 = 0x10, 3157 ISM330DHCX_HP_ODR_DIV_10 = 0x11, 3158 ISM330DHCX_HP_ODR_DIV_20 = 0x12, 3159 ISM330DHCX_HP_ODR_DIV_45 = 0x13, 3160 ISM330DHCX_HP_ODR_DIV_100 = 0x14, 3161 ISM330DHCX_HP_ODR_DIV_200 = 0x15, 3162 ISM330DHCX_HP_ODR_DIV_400 = 0x16, 3163 ISM330DHCX_HP_ODR_DIV_800 = 0x17, 3164 ISM330DHCX_HP_REF_MD_ODR_DIV_10 = 0x31, 3165 ISM330DHCX_HP_REF_MD_ODR_DIV_20 = 0x32, 3166 ISM330DHCX_HP_REF_MD_ODR_DIV_45 = 0x33, 3167 ISM330DHCX_HP_REF_MD_ODR_DIV_100 = 0x34, 3168 ISM330DHCX_HP_REF_MD_ODR_DIV_200 = 0x35, 3169 ISM330DHCX_HP_REF_MD_ODR_DIV_400 = 0x36, 3170 ISM330DHCX_HP_REF_MD_ODR_DIV_800 = 0x37, 3171 ISM330DHCX_LP_ODR_DIV_10 = 0x01, 3172 ISM330DHCX_LP_ODR_DIV_20 = 0x02, 3173 ISM330DHCX_LP_ODR_DIV_45 = 0x03, 3174 ISM330DHCX_LP_ODR_DIV_100 = 0x04, 3175 ISM330DHCX_LP_ODR_DIV_200 = 0x05, 3176 ISM330DHCX_LP_ODR_DIV_400 = 0x06, 3177 ISM330DHCX_LP_ODR_DIV_800 = 0x07, 3178 } ism330dhcx_hp_slope_xl_en_t; 3179 int32_t ism330dhcx_xl_hp_path_on_out_set(const stmdev_ctx_t *ctx, 3180 ism330dhcx_hp_slope_xl_en_t val); 3181 int32_t ism330dhcx_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, 3182 ism330dhcx_hp_slope_xl_en_t *val); 3183 3184 int32_t ism330dhcx_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val); 3185 int32_t ism330dhcx_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val); 3186 3187 typedef enum 3188 { 3189 ISM330DHCX_USE_SLOPE = 0, 3190 ISM330DHCX_USE_HPF = 1, 3191 } ism330dhcx_slope_fds_t; 3192 int32_t ism330dhcx_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, 3193 ism330dhcx_slope_fds_t val); 3194 int32_t ism330dhcx_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, 3195 ism330dhcx_slope_fds_t *val); 3196 3197 typedef enum 3198 { 3199 ISM330DHCX_HP_FILTER_NONE = 0x00, 3200 ISM330DHCX_HP_FILTER_16mHz = 0x80, 3201 ISM330DHCX_HP_FILTER_65mHz = 0x81, 3202 ISM330DHCX_HP_FILTER_260mHz = 0x82, 3203 ISM330DHCX_HP_FILTER_1Hz04 = 0x83, 3204 } ism330dhcx_hpm_g_t; 3205 int32_t ism330dhcx_gy_hp_path_internal_set(const stmdev_ctx_t *ctx, 3206 ism330dhcx_hpm_g_t val); 3207 int32_t ism330dhcx_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, 3208 ism330dhcx_hpm_g_t *val); 3209 3210 typedef enum 3211 { 3212 ISM330DHCX_AUX_PULL_UP_DISC = 0, 3213 ISM330DHCX_AUX_PULL_UP_CONNECT = 1, 3214 } ism330dhcx_ois_pu_dis_t; 3215 int32_t ism330dhcx_aux_sdo_ocs_mode_set(const stmdev_ctx_t *ctx, 3216 ism330dhcx_ois_pu_dis_t val); 3217 int32_t ism330dhcx_aux_sdo_ocs_mode_get(const stmdev_ctx_t *ctx, 3218 ism330dhcx_ois_pu_dis_t *val); 3219 3220 typedef enum 3221 { 3222 ISM330DHCX_AUX_ON = 1, 3223 ISM330DHCX_AUX_ON_BY_AUX_INTERFACE = 0, 3224 } ism330dhcx_ois_on_t; 3225 int32_t ism330dhcx_aux_pw_on_ctrl_set(const stmdev_ctx_t *ctx, 3226 ism330dhcx_ois_on_t val); 3227 int32_t ism330dhcx_aux_pw_on_ctrl_get(const stmdev_ctx_t *ctx, 3228 ism330dhcx_ois_on_t *val); 3229 3230 int32_t ism330dhcx_aux_status_reg_get(const stmdev_ctx_t *ctx, 3231 ism330dhcx_status_spiaux_t *val); 3232 3233 int32_t ism330dhcx_aux_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, 3234 uint8_t *val); 3235 3236 int32_t ism330dhcx_aux_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, 3237 uint8_t *val); 3238 3239 int32_t ism330dhcx_aux_gy_flag_settling_get(const stmdev_ctx_t *ctx, 3240 uint8_t *val); 3241 3242 typedef enum 3243 { 3244 ISM330DHCX_AUX_XL_DISABLE = 0, 3245 ISM330DHCX_AUX_XL_POS = 1, 3246 ISM330DHCX_AUX_XL_NEG = 2, 3247 } ism330dhcx_st_xl_ois_t; 3248 int32_t ism330dhcx_aux_xl_self_test_set(const stmdev_ctx_t *ctx, 3249 ism330dhcx_st_xl_ois_t val); 3250 int32_t ism330dhcx_aux_xl_self_test_get(const stmdev_ctx_t *ctx, 3251 ism330dhcx_st_xl_ois_t *val); 3252 3253 typedef enum 3254 { 3255 ISM330DHCX_AUX_DEN_ACTIVE_LOW = 0, 3256 ISM330DHCX_AUX_DEN_ACTIVE_HIGH = 1, 3257 } ism330dhcx_den_lh_ois_t; 3258 int32_t ism330dhcx_aux_den_polarity_set(const stmdev_ctx_t *ctx, 3259 ism330dhcx_den_lh_ois_t val); 3260 int32_t ism330dhcx_aux_den_polarity_get(const stmdev_ctx_t *ctx, 3261 ism330dhcx_den_lh_ois_t *val); 3262 3263 typedef enum 3264 { 3265 ISM330DHCX_AUX_DEN_DISABLE = 0, 3266 ISM330DHCX_AUX_DEN_LEVEL_LATCH = 3, 3267 ISM330DHCX_AUX_DEN_LEVEL_TRIG = 2, 3268 } ism330dhcx_lvl2_ois_t; 3269 int32_t ism330dhcx_aux_den_mode_set(const stmdev_ctx_t *ctx, 3270 ism330dhcx_lvl2_ois_t val); 3271 int32_t ism330dhcx_aux_den_mode_get(const stmdev_ctx_t *ctx, 3272 ism330dhcx_lvl2_ois_t *val); 3273 3274 int32_t ism330dhcx_aux_drdy_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val); 3275 int32_t ism330dhcx_aux_drdy_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val); 3276 3277 typedef enum 3278 { 3279 ISM330DHCX_AUX_DISABLE = 0, 3280 ISM330DHCX_MODE_3_GY = 1, 3281 ISM330DHCX_MODE_4_GY_XL = 3, 3282 } ism330dhcx_ois_en_spi2_t; 3283 int32_t ism330dhcx_aux_mode_set(const stmdev_ctx_t *ctx, 3284 ism330dhcx_ois_en_spi2_t val); 3285 int32_t ism330dhcx_aux_mode_get(const stmdev_ctx_t *ctx, 3286 ism330dhcx_ois_en_spi2_t *val); 3287 3288 typedef enum 3289 { 3290 ISM330DHCX_125dps_AUX = 0x04, 3291 ISM330DHCX_250dps_AUX = 0x00, 3292 ISM330DHCX_500dps_AUX = 0x01, 3293 ISM330DHCX_1000dps_AUX = 0x02, 3294 ISM330DHCX_2000dps_AUX = 0x03, 3295 } ism330dhcx_fs_g_ois_t; 3296 int32_t ism330dhcx_aux_gy_full_scale_set(const stmdev_ctx_t *ctx, 3297 ism330dhcx_fs_g_ois_t val); 3298 int32_t ism330dhcx_aux_gy_full_scale_get(const stmdev_ctx_t *ctx, 3299 ism330dhcx_fs_g_ois_t *val); 3300 3301 typedef enum 3302 { 3303 ISM330DHCX_AUX_SPI_4_WIRE = 0, 3304 ISM330DHCX_AUX_SPI_3_WIRE = 1, 3305 } ism330dhcx_sim_ois_t; 3306 int32_t ism330dhcx_aux_spi_mode_set(const stmdev_ctx_t *ctx, 3307 ism330dhcx_sim_ois_t val); 3308 int32_t ism330dhcx_aux_spi_mode_get(const stmdev_ctx_t *ctx, 3309 ism330dhcx_sim_ois_t *val); 3310 3311 typedef enum 3312 { 3313 ISM330DHCX_351Hz39 = 0, 3314 ISM330DHCX_236Hz63 = 1, 3315 ISM330DHCX_172Hz70 = 2, 3316 ISM330DHCX_937Hz91 = 3, 3317 } ism330dhcx_ftype_ois_t; 3318 int32_t ism330dhcx_aux_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, 3319 ism330dhcx_ftype_ois_t val); 3320 int32_t ism330dhcx_aux_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, 3321 ism330dhcx_ftype_ois_t *val); 3322 3323 typedef enum 3324 { 3325 ISM330DHCX_AUX_HP_DISABLE = 0x00, 3326 ISM330DHCX_AUX_HP_Hz016 = 0x10, 3327 ISM330DHCX_AUX_HP_Hz065 = 0x11, 3328 ISM330DHCX_AUX_HP_Hz260 = 0x12, 3329 ISM330DHCX_AUX_HP_1Hz040 = 0x13, 3330 } ism330dhcx_hpm_ois_t; 3331 int32_t ism330dhcx_aux_gy_hp_bandwidth_set(const stmdev_ctx_t *ctx, 3332 ism330dhcx_hpm_ois_t val); 3333 int32_t ism330dhcx_aux_gy_hp_bandwidth_get(const stmdev_ctx_t *ctx, 3334 ism330dhcx_hpm_ois_t *val); 3335 3336 typedef enum 3337 { 3338 ISM330DHCX_ENABLE_CLAMP = 0, 3339 ISM330DHCX_DISABLE_CLAMP = 1, 3340 } ism330dhcx_st_ois_clampdis_t; 3341 int32_t ism330dhcx_aux_gy_clamp_set(const stmdev_ctx_t *ctx, 3342 ism330dhcx_st_ois_clampdis_t val); 3343 int32_t ism330dhcx_aux_gy_clamp_get(const stmdev_ctx_t *ctx, 3344 ism330dhcx_st_ois_clampdis_t *val); 3345 3346 typedef enum 3347 { 3348 ISM330DHCX_AUX_GY_DISABLE = 0, 3349 ISM330DHCX_AUX_GY_POS = 1, 3350 ISM330DHCX_AUX_GY_NEG = 3, 3351 } ism330dhcx_st_ois_t; 3352 int32_t ism330dhcx_aux_gy_self_test_set(const stmdev_ctx_t *ctx, 3353 ism330dhcx_st_ois_t val); 3354 int32_t ism330dhcx_aux_gy_self_test_get(const stmdev_ctx_t *ctx, 3355 ism330dhcx_st_ois_t *val); 3356 3357 typedef enum 3358 { 3359 ISM330DHCX_631Hz = 0, 3360 ISM330DHCX_295Hz = 1, 3361 ISM330DHCX_140Hz = 2, 3362 ISM330DHCX_68Hz2 = 3, 3363 ISM330DHCX_33Hz6 = 4, 3364 ISM330DHCX_16Hz7 = 5, 3365 ISM330DHCX_8Hz3 = 6, 3366 ISM330DHCX_4Hz11 = 7, 3367 } ism330dhcx_filter_xl_conf_ois_t; 3368 int32_t ism330dhcx_aux_xl_bandwidth_set(const stmdev_ctx_t *ctx, 3369 ism330dhcx_filter_xl_conf_ois_t val); 3370 int32_t ism330dhcx_aux_xl_bandwidth_get(const stmdev_ctx_t *ctx, 3371 ism330dhcx_filter_xl_conf_ois_t *val); 3372 3373 typedef enum 3374 { 3375 ISM330DHCX_AUX_2g = 0, 3376 ISM330DHCX_AUX_16g = 1, 3377 ISM330DHCX_AUX_4g = 2, 3378 ISM330DHCX_AUX_8g = 3, 3379 } ism330dhcx_fs_xl_ois_t; 3380 int32_t ism330dhcx_aux_xl_full_scale_set(const stmdev_ctx_t *ctx, 3381 ism330dhcx_fs_xl_ois_t val); 3382 int32_t ism330dhcx_aux_xl_full_scale_get(const stmdev_ctx_t *ctx, 3383 ism330dhcx_fs_xl_ois_t *val); 3384 3385 typedef enum 3386 { 3387 ISM330DHCX_PULL_UP_DISC = 0, 3388 ISM330DHCX_PULL_UP_CONNECT = 1, 3389 } ism330dhcx_sdo_pu_en_t; 3390 int32_t ism330dhcx_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, 3391 ism330dhcx_sdo_pu_en_t val); 3392 int32_t ism330dhcx_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, 3393 ism330dhcx_sdo_pu_en_t *val); 3394 3395 typedef enum 3396 { 3397 ISM330DHCX_SPI_4_WIRE = 0, 3398 ISM330DHCX_SPI_3_WIRE = 1, 3399 } ism330dhcx_sim_t; 3400 int32_t ism330dhcx_spi_mode_set(const stmdev_ctx_t *ctx, 3401 ism330dhcx_sim_t val); 3402 int32_t ism330dhcx_spi_mode_get(const stmdev_ctx_t *ctx, 3403 ism330dhcx_sim_t *val); 3404 3405 typedef enum 3406 { 3407 ISM330DHCX_I2C_ENABLE = 0, 3408 ISM330DHCX_I2C_DISABLE = 1, 3409 } ism330dhcx_i2c_disable_t; 3410 int32_t ism330dhcx_i2c_interface_set(const stmdev_ctx_t *ctx, 3411 ism330dhcx_i2c_disable_t val); 3412 int32_t ism330dhcx_i2c_interface_get(const stmdev_ctx_t *ctx, 3413 ism330dhcx_i2c_disable_t *val); 3414 3415 typedef struct 3416 { 3417 ism330dhcx_int1_ctrl_t int1_ctrl; 3418 ism330dhcx_md1_cfg_t md1_cfg; 3419 ism330dhcx_emb_func_int1_t emb_func_int1; 3420 ism330dhcx_fsm_int1_a_t fsm_int1_a; 3421 ism330dhcx_fsm_int1_b_t fsm_int1_b; 3422 ism330dhcx_mlc_int1_t mlc_int1; 3423 } ism330dhcx_pin_int1_route_t; 3424 int32_t ism330dhcx_pin_int1_route_set(const stmdev_ctx_t *ctx, 3425 ism330dhcx_pin_int1_route_t *val); 3426 int32_t ism330dhcx_pin_int1_route_get(const stmdev_ctx_t *ctx, 3427 ism330dhcx_pin_int1_route_t *val); 3428 3429 typedef struct 3430 { 3431 ism330dhcx_int2_ctrl_t int2_ctrl; 3432 ism330dhcx_md2_cfg_t md2_cfg; 3433 ism330dhcx_emb_func_int2_t emb_func_int2; 3434 ism330dhcx_fsm_int2_a_t fsm_int2_a; 3435 ism330dhcx_fsm_int2_b_t fsm_int2_b; 3436 ism330dhcx_mlc_int2_t mlc_int2; 3437 } ism330dhcx_pin_int2_route_t; 3438 int32_t ism330dhcx_pin_int2_route_set(const stmdev_ctx_t *ctx, 3439 ism330dhcx_pin_int2_route_t *val); 3440 int32_t ism330dhcx_pin_int2_route_get(const stmdev_ctx_t *ctx, 3441 ism330dhcx_pin_int2_route_t *val); 3442 3443 typedef enum 3444 { 3445 ISM330DHCX_PUSH_PULL = 0, 3446 ISM330DHCX_OPEN_DRAIN = 1, 3447 } ism330dhcx_pp_od_t; 3448 int32_t ism330dhcx_pin_mode_set(const stmdev_ctx_t *ctx, 3449 ism330dhcx_pp_od_t val); 3450 int32_t ism330dhcx_pin_mode_get(const stmdev_ctx_t *ctx, 3451 ism330dhcx_pp_od_t *val); 3452 3453 typedef enum 3454 { 3455 ISM330DHCX_ACTIVE_HIGH = 0, 3456 ISM330DHCX_ACTIVE_LOW = 1, 3457 } ism330dhcx_h_lactive_t; 3458 int32_t ism330dhcx_pin_polarity_set(const stmdev_ctx_t *ctx, 3459 ism330dhcx_h_lactive_t val); 3460 int32_t ism330dhcx_pin_polarity_get(const stmdev_ctx_t *ctx, 3461 ism330dhcx_h_lactive_t *val); 3462 3463 int32_t ism330dhcx_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); 3464 int32_t ism330dhcx_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); 3465 3466 typedef enum 3467 { 3468 ISM330DHCX_ALL_INT_PULSED = 0, 3469 ISM330DHCX_BASE_LATCHED_EMB_PULSED = 1, 3470 ISM330DHCX_BASE_PULSED_EMB_LATCHED = 2, 3471 ISM330DHCX_ALL_INT_LATCHED = 3, 3472 } ism330dhcx_lir_t; 3473 int32_t ism330dhcx_int_notification_set(const stmdev_ctx_t *ctx, 3474 ism330dhcx_lir_t val); 3475 int32_t ism330dhcx_int_notification_get(const stmdev_ctx_t *ctx, 3476 ism330dhcx_lir_t *val); 3477 3478 typedef enum 3479 { 3480 ISM330DHCX_LSb_FS_DIV_64 = 0, 3481 ISM330DHCX_LSb_FS_DIV_256 = 1, 3482 } ism330dhcx_wake_ths_w_t; 3483 int32_t ism330dhcx_wkup_ths_weight_set(const stmdev_ctx_t *ctx, 3484 ism330dhcx_wake_ths_w_t val); 3485 int32_t ism330dhcx_wkup_ths_weight_get(const stmdev_ctx_t *ctx, 3486 ism330dhcx_wake_ths_w_t *val); 3487 3488 int32_t ism330dhcx_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); 3489 int32_t ism330dhcx_wkup_threshold_get(const stmdev_ctx_t *ctx, 3490 uint8_t *val); 3491 3492 int32_t ism330dhcx_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx, 3493 uint8_t val); 3494 int32_t ism330dhcx_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, 3495 uint8_t *val); 3496 3497 int32_t ism330dhcx_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 3498 int32_t ism330dhcx_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 3499 3500 int32_t ism330dhcx_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 3501 int32_t ism330dhcx_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); 3502 3503 typedef enum 3504 { 3505 ISM330DHCX_DRIVE_SLEEP_CHG_EVENT = 0, 3506 ISM330DHCX_DRIVE_SLEEP_STATUS = 1, 3507 } ism330dhcx_sleep_status_on_int_t; 3508 int32_t ism330dhcx_act_pin_notification_set(const stmdev_ctx_t *ctx, 3509 ism330dhcx_sleep_status_on_int_t val); 3510 int32_t ism330dhcx_act_pin_notification_get(const stmdev_ctx_t *ctx, 3511 ism330dhcx_sleep_status_on_int_t *val); 3512 3513 typedef enum 3514 { 3515 ISM330DHCX_XL_AND_GY_NOT_AFFECTED = 0, 3516 ISM330DHCX_XL_12Hz5_GY_NOT_AFFECTED = 1, 3517 ISM330DHCX_XL_12Hz5_GY_SLEEP = 2, 3518 ISM330DHCX_XL_12Hz5_GY_PD = 3, 3519 } ism330dhcx_inact_en_t; 3520 int32_t ism330dhcx_act_mode_set(const stmdev_ctx_t *ctx, 3521 ism330dhcx_inact_en_t val); 3522 int32_t ism330dhcx_act_mode_get(const stmdev_ctx_t *ctx, 3523 ism330dhcx_inact_en_t *val); 3524 3525 int32_t ism330dhcx_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 3526 int32_t ism330dhcx_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 3527 3528 int32_t ism330dhcx_tap_detection_on_z_set(const stmdev_ctx_t *ctx, 3529 uint8_t val); 3530 int32_t ism330dhcx_tap_detection_on_z_get(const stmdev_ctx_t *ctx, 3531 uint8_t *val); 3532 3533 int32_t ism330dhcx_tap_detection_on_y_set(const stmdev_ctx_t *ctx, 3534 uint8_t val); 3535 int32_t ism330dhcx_tap_detection_on_y_get(const stmdev_ctx_t *ctx, 3536 uint8_t *val); 3537 3538 int32_t ism330dhcx_tap_detection_on_x_set(const stmdev_ctx_t *ctx, 3539 uint8_t val); 3540 int32_t ism330dhcx_tap_detection_on_x_get(const stmdev_ctx_t *ctx, 3541 uint8_t *val); 3542 3543 int32_t ism330dhcx_tap_threshold_x_set(const stmdev_ctx_t *ctx, 3544 uint8_t val); 3545 int32_t ism330dhcx_tap_threshold_x_get(const stmdev_ctx_t *ctx, 3546 uint8_t *val); 3547 3548 typedef enum 3549 { 3550 ISM330DHCX_XYZ = 0, 3551 ISM330DHCX_YXZ = 1, 3552 ISM330DHCX_XZY = 2, 3553 ISM330DHCX_ZYX = 3, 3554 ISM330DHCX_YZX = 5, 3555 ISM330DHCX_ZXY = 6, 3556 } ism330dhcx_tap_priority_t; 3557 int32_t ism330dhcx_tap_axis_priority_set(const stmdev_ctx_t *ctx, 3558 ism330dhcx_tap_priority_t val); 3559 int32_t ism330dhcx_tap_axis_priority_get(const stmdev_ctx_t *ctx, 3560 ism330dhcx_tap_priority_t *val); 3561 3562 int32_t ism330dhcx_tap_threshold_y_set(const stmdev_ctx_t *ctx, 3563 uint8_t val); 3564 int32_t ism330dhcx_tap_threshold_y_get(const stmdev_ctx_t *ctx, 3565 uint8_t *val); 3566 3567 int32_t ism330dhcx_tap_threshold_z_set(const stmdev_ctx_t *ctx, 3568 uint8_t val); 3569 int32_t ism330dhcx_tap_threshold_z_get(const stmdev_ctx_t *ctx, 3570 uint8_t *val); 3571 3572 int32_t ism330dhcx_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val); 3573 int32_t ism330dhcx_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val); 3574 3575 int32_t ism330dhcx_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val); 3576 int32_t ism330dhcx_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val); 3577 3578 int32_t ism330dhcx_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 3579 int32_t ism330dhcx_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 3580 3581 typedef enum 3582 { 3583 ISM330DHCX_ONLY_SINGLE = 0, 3584 ISM330DHCX_BOTH_SINGLE_DOUBLE = 1, 3585 } ism330dhcx_single_double_tap_t; 3586 int32_t ism330dhcx_tap_mode_set(const stmdev_ctx_t *ctx, 3587 ism330dhcx_single_double_tap_t val); 3588 int32_t ism330dhcx_tap_mode_get(const stmdev_ctx_t *ctx, 3589 ism330dhcx_single_double_tap_t *val); 3590 3591 typedef enum 3592 { 3593 ISM330DHCX_DEG_80 = 0, 3594 ISM330DHCX_DEG_70 = 1, 3595 ISM330DHCX_DEG_60 = 2, 3596 ISM330DHCX_DEG_50 = 3, 3597 } ism330dhcx_sixd_ths_t; 3598 int32_t ism330dhcx_6d_threshold_set(const stmdev_ctx_t *ctx, 3599 ism330dhcx_sixd_ths_t val); 3600 int32_t ism330dhcx_6d_threshold_get(const stmdev_ctx_t *ctx, 3601 ism330dhcx_sixd_ths_t *val); 3602 3603 int32_t ism330dhcx_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 3604 int32_t ism330dhcx_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); 3605 3606 typedef enum 3607 { 3608 ISM330DHCX_FF_TSH_156mg = 0, 3609 ISM330DHCX_FF_TSH_219mg = 1, 3610 ISM330DHCX_FF_TSH_250mg = 2, 3611 ISM330DHCX_FF_TSH_312mg = 3, 3612 ISM330DHCX_FF_TSH_344mg = 4, 3613 ISM330DHCX_FF_TSH_406mg = 5, 3614 ISM330DHCX_FF_TSH_469mg = 6, 3615 ISM330DHCX_FF_TSH_500mg = 7, 3616 } ism330dhcx_ff_ths_t; 3617 int32_t ism330dhcx_ff_threshold_set(const stmdev_ctx_t *ctx, 3618 ism330dhcx_ff_ths_t val); 3619 int32_t ism330dhcx_ff_threshold_get(const stmdev_ctx_t *ctx, 3620 ism330dhcx_ff_ths_t *val); 3621 3622 int32_t ism330dhcx_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 3623 int32_t ism330dhcx_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 3624 3625 int32_t ism330dhcx_fifo_watermark_set(const stmdev_ctx_t *ctx, 3626 uint16_t val); 3627 int32_t ism330dhcx_fifo_watermark_get(const stmdev_ctx_t *ctx, 3628 uint16_t *val); 3629 3630 int32_t ism330dhcx_compression_algo_init_set(const stmdev_ctx_t *ctx, 3631 uint8_t val); 3632 int32_t ism330dhcx_compression_algo_init_get(const stmdev_ctx_t *ctx, 3633 uint8_t *val); 3634 3635 typedef enum 3636 { 3637 ISM330DHCX_CMP_DISABLE = 0x00, 3638 ISM330DHCX_CMP_ALWAYS = 0x04, 3639 ISM330DHCX_CMP_8_TO_1 = 0x05, 3640 ISM330DHCX_CMP_16_TO_1 = 0x06, 3641 ISM330DHCX_CMP_32_TO_1 = 0x07, 3642 } ism330dhcx_uncoptr_rate_t; 3643 int32_t ism330dhcx_compression_algo_set(const stmdev_ctx_t *ctx, 3644 ism330dhcx_uncoptr_rate_t val); 3645 int32_t ism330dhcx_compression_algo_get(const stmdev_ctx_t *ctx, 3646 ism330dhcx_uncoptr_rate_t *val); 3647 3648 int32_t ism330dhcx_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, 3649 uint8_t val); 3650 int32_t ism330dhcx_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, 3651 uint8_t *val); 3652 3653 int32_t ism330dhcx_compression_algo_real_time_set(const stmdev_ctx_t *ctx, 3654 uint8_t val); 3655 int32_t ism330dhcx_compression_algo_real_time_get(const stmdev_ctx_t *ctx, 3656 uint8_t *val); 3657 3658 int32_t ism330dhcx_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, 3659 uint8_t val); 3660 int32_t ism330dhcx_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, 3661 uint8_t *val); 3662 3663 typedef enum 3664 { 3665 ISM330DHCX_XL_NOT_BATCHED = 0, 3666 ISM330DHCX_XL_BATCHED_AT_12Hz5 = 1, 3667 ISM330DHCX_XL_BATCHED_AT_26Hz = 2, 3668 ISM330DHCX_XL_BATCHED_AT_52Hz = 3, 3669 ISM330DHCX_XL_BATCHED_AT_104Hz = 4, 3670 ISM330DHCX_XL_BATCHED_AT_208Hz = 5, 3671 ISM330DHCX_XL_BATCHED_AT_417Hz = 6, 3672 ISM330DHCX_XL_BATCHED_AT_833Hz = 7, 3673 ISM330DHCX_XL_BATCHED_AT_1667Hz = 8, 3674 ISM330DHCX_XL_BATCHED_AT_3333Hz = 9, 3675 ISM330DHCX_XL_BATCHED_AT_6667Hz = 10, 3676 ISM330DHCX_XL_BATCHED_AT_6Hz5 = 11, 3677 } ism330dhcx_bdr_xl_t; 3678 int32_t ism330dhcx_fifo_xl_batch_set(const stmdev_ctx_t *ctx, 3679 ism330dhcx_bdr_xl_t val); 3680 int32_t ism330dhcx_fifo_xl_batch_get(const stmdev_ctx_t *ctx, 3681 ism330dhcx_bdr_xl_t *val); 3682 3683 typedef enum 3684 { 3685 ISM330DHCX_GY_NOT_BATCHED = 0, 3686 ISM330DHCX_GY_BATCHED_AT_12Hz5 = 1, 3687 ISM330DHCX_GY_BATCHED_AT_26Hz = 2, 3688 ISM330DHCX_GY_BATCHED_AT_52Hz = 3, 3689 ISM330DHCX_GY_BATCHED_AT_104Hz = 4, 3690 ISM330DHCX_GY_BATCHED_AT_208Hz = 5, 3691 ISM330DHCX_GY_BATCHED_AT_417Hz = 6, 3692 ISM330DHCX_GY_BATCHED_AT_833Hz = 7, 3693 ISM330DHCX_GY_BATCHED_AT_1667Hz = 8, 3694 ISM330DHCX_GY_BATCHED_AT_3333Hz = 9, 3695 ISM330DHCX_GY_BATCHED_AT_6667Hz = 10, 3696 ISM330DHCX_GY_BATCHED_6Hz5 = 11, 3697 } ism330dhcx_bdr_gy_t; 3698 int32_t ism330dhcx_fifo_gy_batch_set(const stmdev_ctx_t *ctx, 3699 ism330dhcx_bdr_gy_t val); 3700 int32_t ism330dhcx_fifo_gy_batch_get(const stmdev_ctx_t *ctx, 3701 ism330dhcx_bdr_gy_t *val); 3702 3703 typedef enum 3704 { 3705 ISM330DHCX_BYPASS_MODE = 0, 3706 ISM330DHCX_FIFO_MODE = 1, 3707 ISM330DHCX_STREAM_TO_FIFO_MODE = 3, 3708 ISM330DHCX_BYPASS_TO_STREAM_MODE = 4, 3709 ISM330DHCX_STREAM_MODE = 6, 3710 ISM330DHCX_BYPASS_TO_FIFO_MODE = 7, 3711 } ism330dhcx_fifo_mode_t; 3712 int32_t ism330dhcx_fifo_mode_set(const stmdev_ctx_t *ctx, 3713 ism330dhcx_fifo_mode_t val); 3714 int32_t ism330dhcx_fifo_mode_get(const stmdev_ctx_t *ctx, 3715 ism330dhcx_fifo_mode_t *val); 3716 3717 typedef enum 3718 { 3719 ISM330DHCX_TEMP_NOT_BATCHED = 0, 3720 ISM330DHCX_TEMP_BATCHED_AT_52Hz = 1, 3721 ISM330DHCX_TEMP_BATCHED_AT_12Hz5 = 2, 3722 ISM330DHCX_TEMP_BATCHED_AT_1Hz6 = 3, 3723 } ism330dhcx_odr_t_batch_t; 3724 int32_t ism330dhcx_fifo_temp_batch_set(const stmdev_ctx_t *ctx, 3725 ism330dhcx_odr_t_batch_t val); 3726 int32_t ism330dhcx_fifo_temp_batch_get(const stmdev_ctx_t *ctx, 3727 ism330dhcx_odr_t_batch_t *val); 3728 3729 typedef enum 3730 { 3731 ISM330DHCX_NO_DECIMATION = 0, 3732 ISM330DHCX_DEC_1 = 1, 3733 ISM330DHCX_DEC_8 = 2, 3734 ISM330DHCX_DEC_32 = 3, 3735 } ism330dhcx_odr_ts_batch_t; 3736 int32_t ism330dhcx_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx, 3737 ism330dhcx_odr_ts_batch_t val); 3738 int32_t ism330dhcx_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, 3739 ism330dhcx_odr_ts_batch_t *val); 3740 3741 typedef enum 3742 { 3743 ISM330DHCX_XL_BATCH_EVENT = 0, 3744 ISM330DHCX_GYRO_BATCH_EVENT = 1, 3745 } ism330dhcx_trig_counter_bdr_t; 3746 int32_t ism330dhcx_fifo_cnt_event_batch_set(const stmdev_ctx_t *ctx, 3747 ism330dhcx_trig_counter_bdr_t val); 3748 int32_t ism330dhcx_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx, 3749 ism330dhcx_trig_counter_bdr_t *val); 3750 3751 int32_t ism330dhcx_rst_batch_counter_set(const stmdev_ctx_t *ctx, 3752 uint8_t val); 3753 int32_t ism330dhcx_rst_batch_counter_get(const stmdev_ctx_t *ctx, 3754 uint8_t *val); 3755 3756 int32_t ism330dhcx_batch_counter_threshold_set(const stmdev_ctx_t *ctx, 3757 uint16_t val); 3758 int32_t ism330dhcx_batch_counter_threshold_get(const stmdev_ctx_t *ctx, 3759 uint16_t *val); 3760 3761 int32_t ism330dhcx_fifo_data_level_get(const stmdev_ctx_t *ctx, 3762 uint16_t *val); 3763 3764 int32_t ism330dhcx_fifo_status_get(const stmdev_ctx_t *ctx, 3765 ism330dhcx_fifo_status2_t *val); 3766 3767 int32_t ism330dhcx_fifo_full_flag_get(const stmdev_ctx_t *ctx, 3768 uint8_t *val); 3769 3770 int32_t ism330dhcx_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 3771 3772 int32_t ism330dhcx_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 3773 3774 typedef enum 3775 { 3776 ISM330DHCX_GYRO_NC_TAG = 1, 3777 ISM330DHCX_XL_NC_TAG, 3778 ISM330DHCX_TEMPERATURE_TAG, 3779 ISM330DHCX_TIMESTAMP_TAG, 3780 ISM330DHCX_CFG_CHANGE_TAG, 3781 ISM330DHCX_XL_NC_T_2_TAG, 3782 ISM330DHCX_XL_NC_T_1_TAG, 3783 ISM330DHCX_XL_2XC_TAG, 3784 ISM330DHCX_XL_3XC_TAG, 3785 ISM330DHCX_GYRO_NC_T_2_TAG, 3786 ISM330DHCX_GYRO_NC_T_1_TAG, 3787 ISM330DHCX_GYRO_2XC_TAG, 3788 ISM330DHCX_GYRO_3XC_TAG, 3789 ISM330DHCX_SENSORHUB_SLAVE0_TAG, 3790 ISM330DHCX_SENSORHUB_SLAVE1_TAG, 3791 ISM330DHCX_SENSORHUB_SLAVE2_TAG, 3792 ISM330DHCX_SENSORHUB_SLAVE3_TAG, 3793 ISM330DHCX_STEP_CPUNTER_TAG, 3794 ISM330DHCX_GAME_ROTATION_TAG, 3795 ISM330DHCX_GEOMAG_ROTATION_TAG, 3796 ISM330DHCX_ROTATION_TAG, 3797 ISM330DHCX_SENSORHUB_NACK_TAG = 0x19, 3798 } ism330dhcx_fifo_tag_t; 3799 int32_t ism330dhcx_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, 3800 ism330dhcx_fifo_tag_t *val); 3801 3802 int32_t ism330dhcx_fifo_pedo_batch_set(const stmdev_ctx_t *ctx, 3803 uint8_t val); 3804 int32_t ism330dhcx_fifo_pedo_batch_get(const stmdev_ctx_t *ctx, 3805 uint8_t *val); 3806 3807 int32_t ism330dhcx_sh_batch_slave_0_set(const stmdev_ctx_t *ctx, 3808 uint8_t val); 3809 int32_t ism330dhcx_sh_batch_slave_0_get(const stmdev_ctx_t *ctx, 3810 uint8_t *val); 3811 3812 int32_t ism330dhcx_sh_batch_slave_1_set(const stmdev_ctx_t *ctx, 3813 uint8_t val); 3814 int32_t ism330dhcx_sh_batch_slave_1_get(const stmdev_ctx_t *ctx, 3815 uint8_t *val); 3816 3817 int32_t ism330dhcx_sh_batch_slave_2_set(const stmdev_ctx_t *ctx, 3818 uint8_t val); 3819 int32_t ism330dhcx_sh_batch_slave_2_get(const stmdev_ctx_t *ctx, 3820 uint8_t *val); 3821 3822 int32_t ism330dhcx_sh_batch_slave_3_set(const stmdev_ctx_t *ctx, 3823 uint8_t val); 3824 int32_t ism330dhcx_sh_batch_slave_3_get(const stmdev_ctx_t *ctx, 3825 uint8_t *val); 3826 3827 typedef enum 3828 { 3829 ISM330DHCX_DEN_DISABLE = 0, 3830 ISM330DHCX_LEVEL_FIFO = 6, 3831 ISM330DHCX_LEVEL_LETCHED = 3, 3832 ISM330DHCX_LEVEL_TRIGGER = 2, 3833 ISM330DHCX_EDGE_TRIGGER = 4, 3834 } ism330dhcx_den_mode_t; 3835 int32_t ism330dhcx_den_mode_set(const stmdev_ctx_t *ctx, 3836 ism330dhcx_den_mode_t val); 3837 int32_t ism330dhcx_den_mode_get(const stmdev_ctx_t *ctx, 3838 ism330dhcx_den_mode_t *val); 3839 3840 typedef enum 3841 { 3842 ISM330DHCX_DEN_ACT_LOW = 0, 3843 ISM330DHCX_DEN_ACT_HIGH = 1, 3844 } ism330dhcx_den_lh_t; 3845 int32_t ism330dhcx_den_polarity_set(const stmdev_ctx_t *ctx, 3846 ism330dhcx_den_lh_t val); 3847 int32_t ism330dhcx_den_polarity_get(const stmdev_ctx_t *ctx, 3848 ism330dhcx_den_lh_t *val); 3849 3850 typedef enum 3851 { 3852 ISM330DHCX_STAMP_IN_GY_DATA = 0, 3853 ISM330DHCX_STAMP_IN_XL_DATA = 1, 3854 ISM330DHCX_STAMP_IN_GY_XL_DATA = 2, 3855 } ism330dhcx_den_xl_g_t; 3856 int32_t ism330dhcx_den_enable_set(const stmdev_ctx_t *ctx, 3857 ism330dhcx_den_xl_g_t val); 3858 int32_t ism330dhcx_den_enable_get(const stmdev_ctx_t *ctx, 3859 ism330dhcx_den_xl_g_t *val); 3860 3861 int32_t ism330dhcx_den_mark_axis_x_set(const stmdev_ctx_t *ctx, 3862 uint8_t val); 3863 int32_t ism330dhcx_den_mark_axis_x_get(const stmdev_ctx_t *ctx, 3864 uint8_t *val); 3865 3866 int32_t ism330dhcx_den_mark_axis_y_set(const stmdev_ctx_t *ctx, 3867 uint8_t val); 3868 int32_t ism330dhcx_den_mark_axis_y_get(const stmdev_ctx_t *ctx, 3869 uint8_t *val); 3870 3871 int32_t ism330dhcx_den_mark_axis_z_set(const stmdev_ctx_t *ctx, 3872 uint8_t val); 3873 int32_t ism330dhcx_den_mark_axis_z_get(const stmdev_ctx_t *ctx, 3874 uint8_t *val); 3875 3876 int32_t ism330dhcx_pedo_sens_set(const stmdev_ctx_t *ctx, uint8_t val); 3877 int32_t ism330dhcx_pedo_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); 3878 3879 int32_t ism330dhcx_pedo_step_detect_get(const stmdev_ctx_t *ctx, 3880 uint8_t *val); 3881 3882 int32_t ism330dhcx_pedo_debounce_steps_set(const stmdev_ctx_t *ctx, 3883 uint8_t *val); 3884 int32_t ism330dhcx_pedo_debounce_steps_get(const stmdev_ctx_t *ctx, 3885 uint8_t *val); 3886 3887 int32_t ism330dhcx_pedo_steps_period_set(const stmdev_ctx_t *ctx, 3888 uint16_t val); 3889 int32_t ism330dhcx_pedo_steps_period_get(const stmdev_ctx_t *ctx, 3890 uint16_t *val); 3891 3892 typedef enum 3893 { 3894 ISM330DHCX_EVERY_STEP = 0, 3895 ISM330DHCX_COUNT_OVERFLOW = 1, 3896 } ism330dhcx_carry_count_en_t; 3897 int32_t ism330dhcx_pedo_int_mode_set(const stmdev_ctx_t *ctx, 3898 ism330dhcx_carry_count_en_t val); 3899 int32_t ism330dhcx_pedo_int_mode_get(const stmdev_ctx_t *ctx, 3900 ism330dhcx_carry_count_en_t *val); 3901 3902 int32_t ism330dhcx_motion_sens_set(const stmdev_ctx_t *ctx, uint8_t val); 3903 int32_t ism330dhcx_motion_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); 3904 3905 int32_t ism330dhcx_motion_flag_data_ready_get(const stmdev_ctx_t *ctx, 3906 uint8_t *val); 3907 3908 int32_t ism330dhcx_tilt_sens_set(const stmdev_ctx_t *ctx, uint8_t val); 3909 int32_t ism330dhcx_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); 3910 3911 int32_t ism330dhcx_tilt_flag_data_ready_get(const stmdev_ctx_t *ctx, 3912 uint8_t *val); 3913 3914 int32_t ism330dhcx_mag_sensitivity_set(const stmdev_ctx_t *ctx, 3915 uint16_t val); 3916 int32_t ism330dhcx_mag_sensitivity_get(const stmdev_ctx_t *ctx, 3917 uint16_t *val); 3918 3919 int32_t ism330dhcx_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val); 3920 int32_t ism330dhcx_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val); 3921 3922 int32_t ism330dhcx_mag_soft_iron_set(const stmdev_ctx_t *ctx, 3923 uint16_t *val); 3924 int32_t ism330dhcx_mag_soft_iron_get(const stmdev_ctx_t *ctx, 3925 uint16_t *val); 3926 3927 typedef enum 3928 { 3929 ISM330DHCX_Z_EQ_Y = 0, 3930 ISM330DHCX_Z_EQ_MIN_Y = 1, 3931 ISM330DHCX_Z_EQ_X = 2, 3932 ISM330DHCX_Z_EQ_MIN_X = 3, 3933 ISM330DHCX_Z_EQ_MIN_Z = 4, 3934 ISM330DHCX_Z_EQ_Z = 5, 3935 } ism330dhcx_mag_z_axis_t; 3936 int32_t ism330dhcx_mag_z_orient_set(const stmdev_ctx_t *ctx, 3937 ism330dhcx_mag_z_axis_t val); 3938 int32_t ism330dhcx_mag_z_orient_get(const stmdev_ctx_t *ctx, 3939 ism330dhcx_mag_z_axis_t *val); 3940 3941 typedef enum 3942 { 3943 ISM330DHCX_Y_EQ_Y = 0, 3944 ISM330DHCX_Y_EQ_MIN_Y = 1, 3945 ISM330DHCX_Y_EQ_X = 2, 3946 ISM330DHCX_Y_EQ_MIN_X = 3, 3947 ISM330DHCX_Y_EQ_MIN_Z = 4, 3948 ISM330DHCX_Y_EQ_Z = 5, 3949 } ism330dhcx_mag_y_axis_t; 3950 int32_t ism330dhcx_mag_y_orient_set(const stmdev_ctx_t *ctx, 3951 ism330dhcx_mag_y_axis_t val); 3952 int32_t ism330dhcx_mag_y_orient_get(const stmdev_ctx_t *ctx, 3953 ism330dhcx_mag_y_axis_t *val); 3954 3955 typedef enum 3956 { 3957 ISM330DHCX_X_EQ_Y = 0, 3958 ISM330DHCX_X_EQ_MIN_Y = 1, 3959 ISM330DHCX_X_EQ_X = 2, 3960 ISM330DHCX_X_EQ_MIN_X = 3, 3961 ISM330DHCX_X_EQ_MIN_Z = 4, 3962 ISM330DHCX_X_EQ_Z = 5, 3963 } ism330dhcx_mag_x_axis_t; 3964 int32_t ism330dhcx_mag_x_orient_set(const stmdev_ctx_t *ctx, 3965 ism330dhcx_mag_x_axis_t val); 3966 int32_t ism330dhcx_mag_x_orient_get(const stmdev_ctx_t *ctx, 3967 ism330dhcx_mag_x_axis_t *val); 3968 3969 int32_t ism330dhcx_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, 3970 uint8_t *val); 3971 3972 int32_t ism330dhcx_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val); 3973 int32_t ism330dhcx_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val); 3974 3975 typedef struct 3976 { 3977 ism330dhcx_fsm_enable_a_t fsm_enable_a; 3978 ism330dhcx_fsm_enable_b_t fsm_enable_b; 3979 } ism330dhcx_emb_fsm_enable_t; 3980 int32_t ism330dhcx_fsm_enable_set(const stmdev_ctx_t *ctx, 3981 ism330dhcx_emb_fsm_enable_t *val); 3982 int32_t ism330dhcx_fsm_enable_get(const stmdev_ctx_t *ctx, 3983 ism330dhcx_emb_fsm_enable_t *val); 3984 3985 int32_t ism330dhcx_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val); 3986 int32_t ism330dhcx_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val); 3987 3988 typedef enum 3989 { 3990 ISM330DHCX_LC_NORMAL = 0, 3991 ISM330DHCX_LC_CLEAR = 1, 3992 ISM330DHCX_LC_CLEAR_DONE = 2, 3993 } ism330dhcx_fsm_lc_clr_t; 3994 int32_t ism330dhcx_long_clr_set(const stmdev_ctx_t *ctx, 3995 ism330dhcx_fsm_lc_clr_t val); 3996 int32_t ism330dhcx_long_clr_get(const stmdev_ctx_t *ctx, 3997 ism330dhcx_fsm_lc_clr_t *val); 3998 3999 typedef struct 4000 { 4001 ism330dhcx_fsm_outs1_t fsm_outs1; 4002 ism330dhcx_fsm_outs2_t fsm_outs2; 4003 ism330dhcx_fsm_outs3_t fsm_outs3; 4004 ism330dhcx_fsm_outs4_t fsm_outs4; 4005 ism330dhcx_fsm_outs5_t fsm_outs5; 4006 ism330dhcx_fsm_outs6_t fsm_outs6; 4007 ism330dhcx_fsm_outs7_t fsm_outs7; 4008 ism330dhcx_fsm_outs8_t fsm_outs8; 4009 ism330dhcx_fsm_outs9_t fsm_outs9; 4010 ism330dhcx_fsm_outs10_t fsm_outs10; 4011 ism330dhcx_fsm_outs11_t fsm_outs11; 4012 ism330dhcx_fsm_outs12_t fsm_outs12; 4013 ism330dhcx_fsm_outs13_t fsm_outs13; 4014 ism330dhcx_fsm_outs14_t fsm_outs14; 4015 ism330dhcx_fsm_outs15_t fsm_outs15; 4016 ism330dhcx_fsm_outs16_t fsm_outs16; 4017 } ism330dhcx_fsm_out_t; 4018 int32_t ism330dhcx_fsm_out_get(const stmdev_ctx_t *ctx, 4019 ism330dhcx_fsm_out_t *val); 4020 4021 typedef enum 4022 { 4023 ISM330DHCX_ODR_FSM_12Hz5 = 0, 4024 ISM330DHCX_ODR_FSM_26Hz = 1, 4025 ISM330DHCX_ODR_FSM_52Hz = 2, 4026 ISM330DHCX_ODR_FSM_104Hz = 3, 4027 } ism330dhcx_fsm_odr_t; 4028 int32_t ism330dhcx_fsm_data_rate_set(const stmdev_ctx_t *ctx, 4029 ism330dhcx_fsm_odr_t val); 4030 int32_t ism330dhcx_fsm_data_rate_get(const stmdev_ctx_t *ctx, 4031 ism330dhcx_fsm_odr_t *val); 4032 4033 int32_t ism330dhcx_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val); 4034 int32_t ism330dhcx_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val); 4035 4036 int32_t ism330dhcx_long_cnt_int_value_set(const stmdev_ctx_t *ctx, 4037 uint16_t val); 4038 int32_t ism330dhcx_long_cnt_int_value_get(const stmdev_ctx_t *ctx, 4039 uint16_t *val); 4040 4041 int32_t ism330dhcx_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, 4042 uint8_t *val); 4043 int32_t ism330dhcx_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, 4044 uint8_t *val); 4045 4046 int32_t ism330dhcx_fsm_start_address_set(const stmdev_ctx_t *ctx, 4047 uint16_t val); 4048 int32_t ism330dhcx_fsm_start_address_get(const stmdev_ctx_t *ctx, 4049 uint16_t *val); 4050 4051 int32_t ism330dhcx_mlc_set(const stmdev_ctx_t *ctx, uint8_t val); 4052 int32_t ism330dhcx_mlc_get(const stmdev_ctx_t *ctx, uint8_t *val); 4053 4054 int32_t ism330dhcx_mlc_status_get(const stmdev_ctx_t *ctx, 4055 ism330dhcx_mlc_status_mainpage_t *val); 4056 4057 typedef enum 4058 { 4059 ISM330DHCX_ODR_PRGS_12Hz5 = 0, 4060 ISM330DHCX_ODR_PRGS_26Hz = 1, 4061 ISM330DHCX_ODR_PRGS_52Hz = 2, 4062 ISM330DHCX_ODR_PRGS_104Hz = 3, 4063 } ism330dhcx_mlc_odr_t; 4064 int32_t ism330dhcx_mlc_data_rate_set(const stmdev_ctx_t *ctx, 4065 ism330dhcx_mlc_odr_t val); 4066 int32_t ism330dhcx_mlc_data_rate_get(const stmdev_ctx_t *ctx, 4067 ism330dhcx_mlc_odr_t *val); 4068 4069 int32_t ism330dhcx_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff); 4070 int32_t ism330dhcx_mlc_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val); 4071 int32_t ism330dhcx_mlc_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val); 4072 4073 typedef struct 4074 { 4075 ism330dhcx_sensor_hub_1_t sh_byte_1; 4076 ism330dhcx_sensor_hub_2_t sh_byte_2; 4077 ism330dhcx_sensor_hub_3_t sh_byte_3; 4078 ism330dhcx_sensor_hub_4_t sh_byte_4; 4079 ism330dhcx_sensor_hub_5_t sh_byte_5; 4080 ism330dhcx_sensor_hub_6_t sh_byte_6; 4081 ism330dhcx_sensor_hub_7_t sh_byte_7; 4082 ism330dhcx_sensor_hub_8_t sh_byte_8; 4083 ism330dhcx_sensor_hub_9_t sh_byte_9; 4084 ism330dhcx_sensor_hub_10_t sh_byte_10; 4085 ism330dhcx_sensor_hub_11_t sh_byte_11; 4086 ism330dhcx_sensor_hub_12_t sh_byte_12; 4087 ism330dhcx_sensor_hub_13_t sh_byte_13; 4088 ism330dhcx_sensor_hub_14_t sh_byte_14; 4089 ism330dhcx_sensor_hub_15_t sh_byte_15; 4090 ism330dhcx_sensor_hub_16_t sh_byte_16; 4091 ism330dhcx_sensor_hub_17_t sh_byte_17; 4092 ism330dhcx_sensor_hub_18_t sh_byte_18; 4093 } ism330dhcx_emb_sh_read_t; 4094 int32_t ism330dhcx_sh_read_data_raw_get(const stmdev_ctx_t *ctx, 4095 ism330dhcx_emb_sh_read_t *val, 4096 uint8_t len); 4097 4098 typedef enum 4099 { 4100 ISM330DHCX_SLV_0 = 0, 4101 ISM330DHCX_SLV_0_1 = 1, 4102 ISM330DHCX_SLV_0_1_2 = 2, 4103 ISM330DHCX_SLV_0_1_2_3 = 3, 4104 } ism330dhcx_aux_sens_on_t; 4105 int32_t ism330dhcx_sh_slave_connected_set(const stmdev_ctx_t *ctx, 4106 ism330dhcx_aux_sens_on_t val); 4107 int32_t ism330dhcx_sh_slave_connected_get(const stmdev_ctx_t *ctx, 4108 ism330dhcx_aux_sens_on_t *val); 4109 4110 int32_t ism330dhcx_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val); 4111 int32_t ism330dhcx_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val); 4112 4113 typedef enum 4114 { 4115 ISM330DHCX_EXT_PULL_UP = 0, 4116 ISM330DHCX_INTERNAL_PULL_UP = 1, 4117 } ism330dhcx_shub_pu_en_t; 4118 int32_t ism330dhcx_sh_pin_mode_set(const stmdev_ctx_t *ctx, 4119 ism330dhcx_shub_pu_en_t val); 4120 int32_t ism330dhcx_sh_pin_mode_get(const stmdev_ctx_t *ctx, 4121 ism330dhcx_shub_pu_en_t *val); 4122 4123 int32_t ism330dhcx_sh_pass_through_set(const stmdev_ctx_t *ctx, 4124 uint8_t val); 4125 int32_t ism330dhcx_sh_pass_through_get(const stmdev_ctx_t *ctx, 4126 uint8_t *val); 4127 4128 typedef enum 4129 { 4130 ISM330DHCX_EXT_ON_INT2_PIN = 1, 4131 ISM330DHCX_XL_GY_DRDY = 0, 4132 } ism330dhcx_start_config_t; 4133 int32_t ism330dhcx_sh_syncro_mode_set(const stmdev_ctx_t *ctx, 4134 ism330dhcx_start_config_t val); 4135 int32_t ism330dhcx_sh_syncro_mode_get(const stmdev_ctx_t *ctx, 4136 ism330dhcx_start_config_t *val); 4137 4138 typedef enum 4139 { 4140 ISM330DHCX_EACH_SH_CYCLE = 0, 4141 ISM330DHCX_ONLY_FIRST_CYCLE = 1, 4142 } ism330dhcx_write_once_t; 4143 int32_t ism330dhcx_sh_write_mode_set(const stmdev_ctx_t *ctx, 4144 ism330dhcx_write_once_t val); 4145 int32_t ism330dhcx_sh_write_mode_get(const stmdev_ctx_t *ctx, 4146 ism330dhcx_write_once_t *val); 4147 4148 int32_t ism330dhcx_sh_reset_set(const stmdev_ctx_t *ctx); 4149 int32_t ism330dhcx_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); 4150 4151 typedef enum 4152 { 4153 ISM330DHCX_SH_ODR_104Hz = 0, 4154 ISM330DHCX_SH_ODR_52Hz = 1, 4155 ISM330DHCX_SH_ODR_26Hz = 2, 4156 ISM330DHCX_SH_ODR_13Hz = 3, 4157 } ism330dhcx_shub_odr_t; 4158 int32_t ism330dhcx_sh_data_rate_set(const stmdev_ctx_t *ctx, 4159 ism330dhcx_shub_odr_t val); 4160 int32_t ism330dhcx_sh_data_rate_get(const stmdev_ctx_t *ctx, 4161 ism330dhcx_shub_odr_t *val); 4162 4163 typedef struct 4164 { 4165 uint8_t slv0_add; 4166 uint8_t slv0_subadd; 4167 uint8_t slv0_data; 4168 } ism330dhcx_sh_cfg_write_t; 4169 int32_t ism330dhcx_sh_cfg_write(const stmdev_ctx_t *ctx, 4170 ism330dhcx_sh_cfg_write_t *val); 4171 4172 typedef struct 4173 { 4174 uint8_t slv_add; 4175 uint8_t slv_subadd; 4176 uint8_t slv_len; 4177 } ism330dhcx_sh_cfg_read_t; 4178 int32_t ism330dhcx_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, 4179 ism330dhcx_sh_cfg_read_t *val); 4180 int32_t ism330dhcx_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, 4181 ism330dhcx_sh_cfg_read_t *val); 4182 int32_t ism330dhcx_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, 4183 ism330dhcx_sh_cfg_read_t *val); 4184 int32_t ism330dhcx_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, 4185 ism330dhcx_sh_cfg_read_t *val); 4186 4187 int32_t ism330dhcx_sh_status_get(const stmdev_ctx_t *ctx, 4188 ism330dhcx_status_master_t *val); 4189 4190 /** 4191 *@} 4192 * 4193 */ 4194 4195 #ifdef __cplusplus 4196 } 4197 #endif 4198 4199 #endif /* ISM330DHCX_REGS_H */ 4200 4201 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 4202
