1 /**
2 ******************************************************************************
3 * @file ism330dhcx_reg.c
4 * @author Sensors Software Solution Team
5 * @brief ISM330DHCX driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "ism330dhcx_reg.h"
21
22 /**
23 * @defgroup ISM330DHCX
24 * @brief This file provides a set of functions needed to drive the
25 * ism330dhcx enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup ISM330DHCX_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
ism330dhcx_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak ism330dhcx_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 if (ctx == NULL)
56 {
57 return -1;
58 }
59
60 ret = ctx->read_reg(ctx->handle, reg, data, len);
61
62 return ret;
63 }
64
65 /**
66 * @brief Write generic device register
67 *
68 * @param ctx read / write interface definitions(ptr)
69 * @param reg register to write
70 * @param data pointer to data to write in register reg(ptr)
71 * @param len number of consecutive register to write
72 * @retval interface status (MANDATORY: return 0 -> no Error)
73 *
74 */
ism330dhcx_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)75 int32_t __weak ism330dhcx_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
76 uint8_t *data,
77 uint16_t len)
78 {
79 int32_t ret;
80
81 if (ctx == NULL)
82 {
83 return -1;
84 }
85
86 ret = ctx->write_reg(ctx->handle, reg, data, len);
87
88 return ret;
89 }
90
91 /**
92 * @}
93 *
94 */
95
96 /**
97 * @defgroup ISM330DHCX_Sensitivity
98 * @brief These functions convert raw-data into engineering units.
99 * @{
100 *
101 */
102
ism330dhcx_from_fs2g_to_mg(int16_t lsb)103 float_t ism330dhcx_from_fs2g_to_mg(int16_t lsb)
104 {
105 return ((float_t)lsb * 0.061f);
106 }
107
ism330dhcx_from_fs4g_to_mg(int16_t lsb)108 float_t ism330dhcx_from_fs4g_to_mg(int16_t lsb)
109 {
110 return ((float_t)lsb * 0.122f);
111 }
112
ism330dhcx_from_fs8g_to_mg(int16_t lsb)113 float_t ism330dhcx_from_fs8g_to_mg(int16_t lsb)
114 {
115 return ((float_t)lsb * 0.244f);
116 }
117
ism330dhcx_from_fs16g_to_mg(int16_t lsb)118 float_t ism330dhcx_from_fs16g_to_mg(int16_t lsb)
119 {
120 return ((float_t)lsb * 0.488f);
121 }
122
ism330dhcx_from_fs125dps_to_mdps(int16_t lsb)123 float_t ism330dhcx_from_fs125dps_to_mdps(int16_t lsb)
124 {
125 return ((float_t)lsb * 4.375f);
126 }
127
ism330dhcx_from_fs250dps_to_mdps(int16_t lsb)128 float_t ism330dhcx_from_fs250dps_to_mdps(int16_t lsb)
129 {
130 return ((float_t)lsb * 8.75f);
131 }
132
ism330dhcx_from_fs500dps_to_mdps(int16_t lsb)133 float_t ism330dhcx_from_fs500dps_to_mdps(int16_t lsb)
134 {
135 return ((float_t)lsb * 17.50f);
136 }
137
ism330dhcx_from_fs1000dps_to_mdps(int16_t lsb)138 float_t ism330dhcx_from_fs1000dps_to_mdps(int16_t lsb)
139 {
140 return ((float_t)lsb * 35.0f);
141 }
142
ism330dhcx_from_fs2000dps_to_mdps(int16_t lsb)143 float_t ism330dhcx_from_fs2000dps_to_mdps(int16_t lsb)
144 {
145 return ((float_t)lsb * 70.0f);
146 }
147
ism330dhcx_from_fs4000dps_to_mdps(int16_t lsb)148 float_t ism330dhcx_from_fs4000dps_to_mdps(int16_t lsb)
149 {
150 return ((float_t)lsb * 140.0f);
151 }
152
ism330dhcx_from_lsb_to_celsius(int16_t lsb)153 float_t ism330dhcx_from_lsb_to_celsius(int16_t lsb)
154 {
155 return (((float_t)lsb / 256.0f) + 25.0f);
156 }
157
ism330dhcx_from_lsb_to_nsec(uint32_t lsb)158 uint64_t ism330dhcx_from_lsb_to_nsec(uint32_t lsb)
159 {
160 return ((uint64_t)lsb * 25000ULL);
161 }
162
163 /**
164 * @}
165 *
166 */
167
168 /**
169 * @defgroup LSM9DS1_Data_generation
170 * @brief This section groups all the functions concerning data
171 * generation
172 * @{
173 *
174 */
175
176 /**
177 * @brief Accelerometer full-scale selection[set]
178 *
179 * @param ctx Read / write interface definitions.(ptr)
180 * @param val Change the values of fs_xl in reg CTRL1_XL
181 * @retval Interface status (MANDATORY: return 0 -> no Error).
182 *
183 */
ism330dhcx_xl_full_scale_set(const stmdev_ctx_t * ctx,ism330dhcx_fs_xl_t val)184 int32_t ism330dhcx_xl_full_scale_set(const stmdev_ctx_t *ctx,
185 ism330dhcx_fs_xl_t val)
186 {
187 ism330dhcx_ctrl1_xl_t ctrl1_xl;
188 int32_t ret;
189 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL1_XL,
190 (uint8_t *)&ctrl1_xl, 1);
191
192 if (ret == 0)
193 {
194 ctrl1_xl.fs_xl = (uint8_t)val;
195 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL1_XL,
196 (uint8_t *)&ctrl1_xl, 1);
197 }
198
199 return ret;
200 }
201
202 /**
203 * @brief Accelerometer full-scale selection.[get]
204 *
205 * @param ctx Read / write interface definitions.(ptr)
206 * @param val Get the values of fs_xl in reg CTRL1_XL
207 * @retval Interface status (MANDATORY: return 0 -> no Error).
208 *
209 */
ism330dhcx_xl_full_scale_get(const stmdev_ctx_t * ctx,ism330dhcx_fs_xl_t * val)210 int32_t ism330dhcx_xl_full_scale_get(const stmdev_ctx_t *ctx,
211 ism330dhcx_fs_xl_t *val)
212 {
213 ism330dhcx_ctrl1_xl_t ctrl1_xl;
214 int32_t ret;
215 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL1_XL,
216 (uint8_t *)&ctrl1_xl, 1);
217
218 switch (ctrl1_xl.fs_xl)
219 {
220 case ISM330DHCX_2g:
221 *val = ISM330DHCX_2g;
222 break;
223
224 case ISM330DHCX_16g:
225 *val = ISM330DHCX_16g;
226 break;
227
228 case ISM330DHCX_4g:
229 *val = ISM330DHCX_4g;
230 break;
231
232 case ISM330DHCX_8g:
233 *val = ISM330DHCX_8g;
234 break;
235
236 default:
237 *val = ISM330DHCX_2g;
238 break;
239 }
240
241 return ret;
242 }
243
244 /**
245 * @brief Accelerometer UI data rate selection.[set]
246 *
247 * @param ctx Read / write interface definitions.(ptr)
248 * @param val Change the values of odr_xl in reg CTRL1_XL
249 * @retval Interface status (MANDATORY: return 0 -> no Error).
250 *
251 */
ism330dhcx_xl_data_rate_set(const stmdev_ctx_t * ctx,ism330dhcx_odr_xl_t val)252 int32_t ism330dhcx_xl_data_rate_set(const stmdev_ctx_t *ctx,
253 ism330dhcx_odr_xl_t val)
254 {
255 ism330dhcx_odr_xl_t odr_xl = val;
256 ism330dhcx_emb_fsm_enable_t fsm_enable;
257 ism330dhcx_fsm_odr_t fsm_odr;
258 uint8_t mlc_enable;
259 ism330dhcx_mlc_odr_t mlc_odr;
260 ism330dhcx_ctrl1_xl_t ctrl1_xl;
261 int32_t ret;
262
263 /* Check the Finite State Machine data rate constraints */
264 ret = ism330dhcx_fsm_enable_get(ctx, &fsm_enable);
265
266 if (ret == 0)
267 {
268 if ((fsm_enable.fsm_enable_a.fsm1_en |
269 fsm_enable.fsm_enable_a.fsm2_en |
270 fsm_enable.fsm_enable_a.fsm3_en |
271 fsm_enable.fsm_enable_a.fsm4_en |
272 fsm_enable.fsm_enable_a.fsm5_en |
273 fsm_enable.fsm_enable_a.fsm6_en |
274 fsm_enable.fsm_enable_a.fsm7_en |
275 fsm_enable.fsm_enable_a.fsm8_en |
276 fsm_enable.fsm_enable_b.fsm9_en |
277 fsm_enable.fsm_enable_b.fsm10_en |
278 fsm_enable.fsm_enable_b.fsm11_en |
279 fsm_enable.fsm_enable_b.fsm12_en |
280 fsm_enable.fsm_enable_b.fsm13_en |
281 fsm_enable.fsm_enable_b.fsm14_en |
282 fsm_enable.fsm_enable_b.fsm15_en |
283 fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
284 {
285 ret = ism330dhcx_fsm_data_rate_get(ctx, &fsm_odr);
286
287 if (ret == 0)
288 {
289 switch (fsm_odr)
290 {
291 case ISM330DHCX_ODR_FSM_12Hz5:
292 if (val == ISM330DHCX_XL_ODR_OFF)
293 {
294 odr_xl = ISM330DHCX_XL_ODR_12Hz5;
295 }
296
297 else
298 {
299 odr_xl = val;
300 }
301
302 break;
303
304 case ISM330DHCX_ODR_FSM_26Hz:
305 if (val == ISM330DHCX_XL_ODR_OFF)
306 {
307 odr_xl = ISM330DHCX_XL_ODR_26Hz;
308 }
309
310 else if (val == ISM330DHCX_XL_ODR_12Hz5)
311 {
312 odr_xl = ISM330DHCX_XL_ODR_26Hz;
313 }
314
315 else
316 {
317 odr_xl = val;
318 }
319
320 break;
321
322 case ISM330DHCX_ODR_FSM_52Hz:
323 if (val == ISM330DHCX_XL_ODR_OFF)
324 {
325 odr_xl = ISM330DHCX_XL_ODR_52Hz;
326 }
327
328 else if (val == ISM330DHCX_XL_ODR_12Hz5)
329 {
330 odr_xl = ISM330DHCX_XL_ODR_52Hz;
331 }
332
333 else if (val == ISM330DHCX_XL_ODR_26Hz)
334 {
335 odr_xl = ISM330DHCX_XL_ODR_52Hz;
336 }
337
338 else
339 {
340 odr_xl = val;
341 }
342
343 break;
344
345 case ISM330DHCX_ODR_FSM_104Hz:
346 if (val == ISM330DHCX_XL_ODR_OFF)
347 {
348 odr_xl = ISM330DHCX_XL_ODR_104Hz;
349 }
350
351 else if (val == ISM330DHCX_XL_ODR_12Hz5)
352 {
353 odr_xl = ISM330DHCX_XL_ODR_104Hz;
354 }
355
356 else if (val == ISM330DHCX_XL_ODR_26Hz)
357 {
358 odr_xl = ISM330DHCX_XL_ODR_104Hz;
359 }
360
361 else if (val == ISM330DHCX_XL_ODR_52Hz)
362 {
363 odr_xl = ISM330DHCX_XL_ODR_104Hz;
364 }
365
366 else
367 {
368 odr_xl = val;
369 }
370
371 break;
372
373 default:
374 odr_xl = val;
375 break;
376 }
377 }
378 }
379 }
380
381 /* Check the Machine Learning Core data rate constraints */
382 mlc_enable = PROPERTY_DISABLE;
383
384 if (ret == 0)
385 {
386 ret = ism330dhcx_mlc_get(ctx, &mlc_enable);
387
388 if (mlc_enable == PROPERTY_ENABLE)
389 {
390 ret = ism330dhcx_mlc_data_rate_get(ctx, &mlc_odr);
391
392 if (ret == 0)
393 {
394 switch (mlc_odr)
395 {
396 case ISM330DHCX_ODR_PRGS_12Hz5:
397 if (val == ISM330DHCX_XL_ODR_OFF)
398 {
399 odr_xl = ISM330DHCX_XL_ODR_12Hz5;
400 }
401
402 else
403 {
404 odr_xl = val;
405 }
406
407 break;
408
409 case ISM330DHCX_ODR_PRGS_26Hz:
410 if (val == ISM330DHCX_XL_ODR_OFF)
411 {
412 odr_xl = ISM330DHCX_XL_ODR_26Hz;
413 }
414
415 else if (val == ISM330DHCX_XL_ODR_12Hz5)
416 {
417 odr_xl = ISM330DHCX_XL_ODR_26Hz;
418 }
419
420 else
421 {
422 odr_xl = val;
423 }
424
425 break;
426
427 case ISM330DHCX_ODR_PRGS_52Hz:
428 if (val == ISM330DHCX_XL_ODR_OFF)
429 {
430 odr_xl = ISM330DHCX_XL_ODR_52Hz;
431 }
432
433 else if (val == ISM330DHCX_XL_ODR_12Hz5)
434 {
435 odr_xl = ISM330DHCX_XL_ODR_52Hz;
436 }
437
438 else if (val == ISM330DHCX_XL_ODR_26Hz)
439 {
440 odr_xl = ISM330DHCX_XL_ODR_52Hz;
441 }
442
443 else
444 {
445 odr_xl = val;
446 }
447
448 break;
449
450 case ISM330DHCX_ODR_PRGS_104Hz:
451 if (val == ISM330DHCX_XL_ODR_OFF)
452 {
453 odr_xl = ISM330DHCX_XL_ODR_104Hz;
454 }
455
456 else if (val == ISM330DHCX_XL_ODR_12Hz5)
457 {
458 odr_xl = ISM330DHCX_XL_ODR_104Hz;
459 }
460
461 else if (val == ISM330DHCX_XL_ODR_26Hz)
462 {
463 odr_xl = ISM330DHCX_XL_ODR_104Hz;
464 }
465
466 else if (val == ISM330DHCX_XL_ODR_52Hz)
467 {
468 odr_xl = ISM330DHCX_XL_ODR_104Hz;
469 }
470
471 else
472 {
473 odr_xl = val;
474 }
475
476 break;
477
478 default:
479 odr_xl = val;
480 break;
481 }
482 }
483 }
484 }
485
486 if (ret == 0)
487 {
488 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL1_XL,
489 (uint8_t *)&ctrl1_xl, 1);
490 }
491
492 if (ret == 0)
493 {
494 ctrl1_xl.odr_xl = (uint8_t)odr_xl;
495 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL1_XL,
496 (uint8_t *)&ctrl1_xl, 1);
497 }
498
499 return ret;
500 }
501
502 /**
503 * @brief Accelerometer UI data rate selection.[get]
504 *
505 * @param ctx Read / write interface definitions.(ptr)
506 * @param val Get the values of odr_xl in reg CTRL1_XL
507 * @retval Interface status (MANDATORY: return 0 -> no Error).
508 *
509 */
ism330dhcx_xl_data_rate_get(const stmdev_ctx_t * ctx,ism330dhcx_odr_xl_t * val)510 int32_t ism330dhcx_xl_data_rate_get(const stmdev_ctx_t *ctx,
511 ism330dhcx_odr_xl_t *val)
512 {
513 ism330dhcx_ctrl1_xl_t ctrl1_xl;
514 int32_t ret;
515 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL1_XL,
516 (uint8_t *)&ctrl1_xl, 1);
517
518 switch (ctrl1_xl.odr_xl)
519 {
520 case ISM330DHCX_XL_ODR_OFF:
521 *val = ISM330DHCX_XL_ODR_OFF;
522 break;
523
524 case ISM330DHCX_XL_ODR_12Hz5:
525 *val = ISM330DHCX_XL_ODR_12Hz5;
526 break;
527
528 case ISM330DHCX_XL_ODR_26Hz:
529 *val = ISM330DHCX_XL_ODR_26Hz;
530 break;
531
532 case ISM330DHCX_XL_ODR_52Hz:
533 *val = ISM330DHCX_XL_ODR_52Hz;
534 break;
535
536 case ISM330DHCX_XL_ODR_104Hz:
537 *val = ISM330DHCX_XL_ODR_104Hz;
538 break;
539
540 case ISM330DHCX_XL_ODR_208Hz:
541 *val = ISM330DHCX_XL_ODR_208Hz;
542 break;
543
544 case ISM330DHCX_XL_ODR_416Hz:
545 *val = ISM330DHCX_XL_ODR_416Hz;
546 break;
547
548 case ISM330DHCX_XL_ODR_833Hz:
549 *val = ISM330DHCX_XL_ODR_833Hz;
550 break;
551
552 case ISM330DHCX_XL_ODR_1666Hz:
553 *val = ISM330DHCX_XL_ODR_1666Hz;
554 break;
555
556 case ISM330DHCX_XL_ODR_3332Hz:
557 *val = ISM330DHCX_XL_ODR_3332Hz;
558 break;
559
560 case ISM330DHCX_XL_ODR_6667Hz:
561 *val = ISM330DHCX_XL_ODR_6667Hz;
562 break;
563
564 case ISM330DHCX_XL_ODR_1Hz6:
565 *val = ISM330DHCX_XL_ODR_1Hz6;
566 break;
567
568 default:
569 *val = ISM330DHCX_XL_ODR_OFF;
570 break;
571 }
572
573 return ret;
574 }
575
576 /**
577 * @brief Gyroscope UI chain full-scale selection.[set]
578 *
579 * @param ctx Read / write interface definitions.(ptr)
580 * @param val Change the values of fs_g in reg CTRL2_G
581 * @retval Interface status (MANDATORY: return 0 -> no Error).
582 *
583 */
ism330dhcx_gy_full_scale_set(const stmdev_ctx_t * ctx,ism330dhcx_fs_g_t val)584 int32_t ism330dhcx_gy_full_scale_set(const stmdev_ctx_t *ctx,
585 ism330dhcx_fs_g_t val)
586 {
587 ism330dhcx_ctrl2_g_t ctrl2_g;
588 int32_t ret;
589 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL2_G,
590 (uint8_t *)&ctrl2_g, 1);
591
592 if (ret == 0)
593 {
594 ctrl2_g.fs_g = (uint8_t)val;
595 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL2_G,
596 (uint8_t *)&ctrl2_g, 1);
597 }
598
599 return ret;
600 }
601
602 /**
603 * @brief Gyroscope UI chain full-scale selection.[get]
604 *
605 * @param ctx Read / write interface definitions.(ptr)
606 * @param val Get the values of fs_g in reg CTRL2_G
607 * @retval Interface status (MANDATORY: return 0 -> no Error).
608 *
609 */
ism330dhcx_gy_full_scale_get(const stmdev_ctx_t * ctx,ism330dhcx_fs_g_t * val)610 int32_t ism330dhcx_gy_full_scale_get(const stmdev_ctx_t *ctx,
611 ism330dhcx_fs_g_t *val)
612 {
613 ism330dhcx_ctrl2_g_t ctrl2_g;
614 int32_t ret;
615 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL2_G,
616 (uint8_t *)&ctrl2_g, 1);
617
618 switch (ctrl2_g.fs_g)
619 {
620 case ISM330DHCX_125dps:
621 *val = ISM330DHCX_125dps;
622 break;
623
624 case ISM330DHCX_250dps:
625 *val = ISM330DHCX_250dps;
626 break;
627
628 case ISM330DHCX_500dps:
629 *val = ISM330DHCX_500dps;
630 break;
631
632 case ISM330DHCX_1000dps:
633 *val = ISM330DHCX_1000dps;
634 break;
635
636 case ISM330DHCX_2000dps:
637 *val = ISM330DHCX_2000dps;
638 break;
639
640 case ISM330DHCX_4000dps:
641 *val = ISM330DHCX_4000dps;
642 break;
643
644 default:
645 *val = ISM330DHCX_125dps;
646 break;
647 }
648
649 return ret;
650 }
651
652 /**
653 * @brief Gyroscope data rate.[set]
654 *
655 * @param ctx Read / write interface definitions.(ptr)
656 * @param val Change the values of odr_g in reg CTRL2_G
657 * @retval Interface status (MANDATORY: return 0 -> no Error).
658 *
659 */
ism330dhcx_gy_data_rate_set(const stmdev_ctx_t * ctx,ism330dhcx_odr_g_t val)660 int32_t ism330dhcx_gy_data_rate_set(const stmdev_ctx_t *ctx,
661 ism330dhcx_odr_g_t val)
662 {
663 ism330dhcx_odr_g_t odr_gy = val;
664 ism330dhcx_emb_fsm_enable_t fsm_enable;
665 ism330dhcx_fsm_odr_t fsm_odr;
666 uint8_t mlc_enable;
667 ism330dhcx_mlc_odr_t mlc_odr;
668 ism330dhcx_ctrl2_g_t ctrl2_g;
669 int32_t ret;
670
671 /* Check the Finite State Machine data rate constraints */
672 ret = ism330dhcx_fsm_enable_get(ctx, &fsm_enable);
673
674 if (ret == 0)
675 {
676 if ((fsm_enable.fsm_enable_a.fsm1_en |
677 fsm_enable.fsm_enable_a.fsm2_en |
678 fsm_enable.fsm_enable_a.fsm3_en |
679 fsm_enable.fsm_enable_a.fsm4_en |
680 fsm_enable.fsm_enable_a.fsm5_en |
681 fsm_enable.fsm_enable_a.fsm6_en |
682 fsm_enable.fsm_enable_a.fsm7_en |
683 fsm_enable.fsm_enable_a.fsm8_en |
684 fsm_enable.fsm_enable_b.fsm9_en |
685 fsm_enable.fsm_enable_b.fsm10_en |
686 fsm_enable.fsm_enable_b.fsm11_en |
687 fsm_enable.fsm_enable_b.fsm12_en |
688 fsm_enable.fsm_enable_b.fsm13_en |
689 fsm_enable.fsm_enable_b.fsm14_en |
690 fsm_enable.fsm_enable_b.fsm15_en |
691 fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
692 {
693 ret = ism330dhcx_fsm_data_rate_get(ctx, &fsm_odr);
694
695 if (ret == 0)
696 {
697 switch (fsm_odr)
698 {
699 case ISM330DHCX_ODR_FSM_12Hz5:
700 if (val == ISM330DHCX_GY_ODR_OFF)
701 {
702 odr_gy = ISM330DHCX_GY_ODR_12Hz5;
703 }
704
705 else
706 {
707 odr_gy = val;
708 }
709
710 break;
711
712 case ISM330DHCX_ODR_FSM_26Hz:
713 if (val == ISM330DHCX_GY_ODR_OFF)
714 {
715 odr_gy = ISM330DHCX_GY_ODR_26Hz;
716 }
717
718 else if (val == ISM330DHCX_GY_ODR_12Hz5)
719 {
720 odr_gy = ISM330DHCX_GY_ODR_26Hz;
721 }
722
723 else
724 {
725 odr_gy = val;
726 }
727
728 break;
729
730 case ISM330DHCX_ODR_FSM_52Hz:
731 if (val == ISM330DHCX_GY_ODR_OFF)
732 {
733 odr_gy = ISM330DHCX_GY_ODR_52Hz;
734 }
735
736 else if (val == ISM330DHCX_GY_ODR_12Hz5)
737 {
738 odr_gy = ISM330DHCX_GY_ODR_52Hz;
739 }
740
741 else if (val == ISM330DHCX_GY_ODR_26Hz)
742 {
743 odr_gy = ISM330DHCX_GY_ODR_52Hz;
744 }
745
746 else
747 {
748 odr_gy = val;
749 }
750
751 break;
752
753 case ISM330DHCX_ODR_FSM_104Hz:
754 if (val == ISM330DHCX_GY_ODR_OFF)
755 {
756 odr_gy = ISM330DHCX_GY_ODR_104Hz;
757 }
758
759 else if (val == ISM330DHCX_GY_ODR_12Hz5)
760 {
761 odr_gy = ISM330DHCX_GY_ODR_104Hz;
762 }
763
764 else if (val == ISM330DHCX_GY_ODR_26Hz)
765 {
766 odr_gy = ISM330DHCX_GY_ODR_104Hz;
767 }
768
769 else if (val == ISM330DHCX_GY_ODR_52Hz)
770 {
771 odr_gy = ISM330DHCX_GY_ODR_104Hz;
772 }
773
774 else
775 {
776 odr_gy = val;
777 }
778
779 break;
780
781 default:
782 odr_gy = val;
783 break;
784 }
785 }
786 }
787 }
788
789 /* Check the Machine Learning Core data rate constraints */
790 mlc_enable = PROPERTY_DISABLE;
791
792 if (ret == 0)
793 {
794 ret = ism330dhcx_mlc_get(ctx, &mlc_enable);
795
796 if (mlc_enable == PROPERTY_ENABLE)
797 {
798 ret = ism330dhcx_mlc_data_rate_get(ctx, &mlc_odr);
799
800 if (ret == 0)
801 {
802 switch (mlc_odr)
803 {
804 case ISM330DHCX_ODR_PRGS_12Hz5:
805 if (val == ISM330DHCX_GY_ODR_OFF)
806 {
807 odr_gy = ISM330DHCX_GY_ODR_12Hz5;
808 }
809
810 else
811 {
812 odr_gy = val;
813 }
814
815 break;
816
817 case ISM330DHCX_ODR_PRGS_26Hz:
818 if (val == ISM330DHCX_GY_ODR_OFF)
819 {
820 odr_gy = ISM330DHCX_GY_ODR_26Hz;
821 }
822
823 else if (val == ISM330DHCX_GY_ODR_12Hz5)
824 {
825 odr_gy = ISM330DHCX_GY_ODR_26Hz;
826 }
827
828 else
829 {
830 odr_gy = val;
831 }
832
833 break;
834
835 case ISM330DHCX_ODR_PRGS_52Hz:
836 if (val == ISM330DHCX_GY_ODR_OFF)
837 {
838 odr_gy = ISM330DHCX_GY_ODR_52Hz;
839 }
840
841 else if (val == ISM330DHCX_GY_ODR_12Hz5)
842 {
843 odr_gy = ISM330DHCX_GY_ODR_52Hz;
844 }
845
846 else if (val == ISM330DHCX_GY_ODR_26Hz)
847 {
848 odr_gy = ISM330DHCX_GY_ODR_52Hz;
849 }
850
851 else
852 {
853 odr_gy = val;
854 }
855
856 break;
857
858 case ISM330DHCX_ODR_PRGS_104Hz:
859 if (val == ISM330DHCX_GY_ODR_OFF)
860 {
861 odr_gy = ISM330DHCX_GY_ODR_104Hz;
862 }
863
864 else if (val == ISM330DHCX_GY_ODR_12Hz5)
865 {
866 odr_gy = ISM330DHCX_GY_ODR_104Hz;
867 }
868
869 else if (val == ISM330DHCX_GY_ODR_26Hz)
870 {
871 odr_gy = ISM330DHCX_GY_ODR_104Hz;
872 }
873
874 else if (val == ISM330DHCX_GY_ODR_52Hz)
875 {
876 odr_gy = ISM330DHCX_GY_ODR_104Hz;
877 }
878
879 else
880 {
881 odr_gy = val;
882 }
883
884 break;
885
886 default:
887 odr_gy = val;
888 break;
889 }
890 }
891 }
892 }
893
894 if (ret == 0)
895 {
896 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL2_G,
897 (uint8_t *)&ctrl2_g, 1);
898 }
899
900 if (ret == 0)
901 {
902 ctrl2_g.odr_g = (uint8_t)odr_gy;
903 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL2_G,
904 (uint8_t *)&ctrl2_g, 1);
905 }
906
907 return ret;
908 }
909
910 /**
911 * @brief Gyroscope data rate.[get]
912 *
913 * @param ctx Read / write interface definitions.(ptr)
914 * @param val Get the values of odr_g in reg CTRL2_G
915 * @retval Interface status (MANDATORY: return 0 -> no Error).
916 *
917 */
ism330dhcx_gy_data_rate_get(const stmdev_ctx_t * ctx,ism330dhcx_odr_g_t * val)918 int32_t ism330dhcx_gy_data_rate_get(const stmdev_ctx_t *ctx,
919 ism330dhcx_odr_g_t *val)
920 {
921 ism330dhcx_ctrl2_g_t ctrl2_g;
922 int32_t ret;
923 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL2_G,
924 (uint8_t *)&ctrl2_g, 1);
925
926 switch (ctrl2_g.odr_g)
927 {
928 case ISM330DHCX_GY_ODR_OFF:
929 *val = ISM330DHCX_GY_ODR_OFF;
930 break;
931
932 case ISM330DHCX_GY_ODR_12Hz5:
933 *val = ISM330DHCX_GY_ODR_12Hz5;
934 break;
935
936 case ISM330DHCX_GY_ODR_26Hz:
937 *val = ISM330DHCX_GY_ODR_26Hz;
938 break;
939
940 case ISM330DHCX_GY_ODR_52Hz:
941 *val = ISM330DHCX_GY_ODR_52Hz;
942 break;
943
944 case ISM330DHCX_GY_ODR_104Hz:
945 *val = ISM330DHCX_GY_ODR_104Hz;
946 break;
947
948 case ISM330DHCX_GY_ODR_208Hz:
949 *val = ISM330DHCX_GY_ODR_208Hz;
950 break;
951
952 case ISM330DHCX_GY_ODR_416Hz:
953 *val = ISM330DHCX_GY_ODR_416Hz;
954 break;
955
956 case ISM330DHCX_GY_ODR_833Hz:
957 *val = ISM330DHCX_GY_ODR_833Hz;
958 break;
959
960 case ISM330DHCX_GY_ODR_1666Hz:
961 *val = ISM330DHCX_GY_ODR_1666Hz;
962 break;
963
964 case ISM330DHCX_GY_ODR_3332Hz:
965 *val = ISM330DHCX_GY_ODR_3332Hz;
966 break;
967
968 case ISM330DHCX_GY_ODR_6667Hz:
969 *val = ISM330DHCX_GY_ODR_6667Hz;
970 break;
971
972 default:
973 *val = ISM330DHCX_GY_ODR_OFF;
974 break;
975 }
976
977 return ret;
978 }
979
980 /**
981 * @brief Block data update.[set]
982 *
983 * @param ctx Read / write interface definitions.(ptr)
984 * @param val Change the values of bdu in reg CTRL3_C
985 * @retval Interface status (MANDATORY: return 0 -> no Error).
986 *
987 */
ism330dhcx_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)988 int32_t ism330dhcx_block_data_update_set(const stmdev_ctx_t *ctx,
989 uint8_t val)
990 {
991 ism330dhcx_ctrl3_c_t ctrl3_c;
992 int32_t ret;
993 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C,
994 (uint8_t *)&ctrl3_c, 1);
995
996 if (ret == 0)
997 {
998 ctrl3_c.bdu = (uint8_t)val;
999 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL3_C,
1000 (uint8_t *)&ctrl3_c, 1);
1001 }
1002
1003 return ret;
1004 }
1005
1006 /**
1007 * @brief Block data update.[get]
1008 *
1009 * @param ctx Read / write interface definitions.(ptr)
1010 * @param val Change the values of bdu in reg CTRL3_C
1011 * @retval Interface status (MANDATORY: return 0 -> no Error).
1012 *
1013 */
ism330dhcx_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)1014 int32_t ism330dhcx_block_data_update_get(const stmdev_ctx_t *ctx,
1015 uint8_t *val)
1016 {
1017 ism330dhcx_ctrl3_c_t ctrl3_c;
1018 int32_t ret;
1019 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C,
1020 (uint8_t *)&ctrl3_c, 1);
1021 *val = ctrl3_c.bdu;
1022
1023 return ret;
1024 }
1025
1026 /**
1027 * @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
1028 * Y_OFS_USR (74h), Z_OFS_USR (75h).[set]
1029 *
1030 * @param ctx Read / write interface definitions.(ptr)
1031 * @param val Change the values of usr_off_w in reg CTRL6_C
1032 * @retval Interface status (MANDATORY: return 0 -> no Error).
1033 *
1034 */
ism330dhcx_xl_offset_weight_set(const stmdev_ctx_t * ctx,ism330dhcx_usr_off_w_t val)1035 int32_t ism330dhcx_xl_offset_weight_set(const stmdev_ctx_t *ctx,
1036 ism330dhcx_usr_off_w_t val)
1037 {
1038 ism330dhcx_ctrl6_c_t ctrl6_c;
1039 int32_t ret;
1040 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL6_C,
1041 (uint8_t *)&ctrl6_c, 1);
1042
1043 if (ret == 0)
1044 {
1045 ctrl6_c.usr_off_w = (uint8_t)val;
1046 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL6_C,
1047 (uint8_t *)&ctrl6_c, 1);
1048 }
1049
1050 return ret;
1051 }
1052
1053 /**
1054 * @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
1055 * Y_OFS_USR (74h), Z_OFS_USR (75h).[get]
1056 *
1057 * @param ctx Read / write interface definitions.(ptr)
1058 * @param val Get the values of usr_off_w in reg CTRL6_C
1059 * @retval Interface status (MANDATORY: return 0 -> no Error).
1060 *
1061 */
ism330dhcx_xl_offset_weight_get(const stmdev_ctx_t * ctx,ism330dhcx_usr_off_w_t * val)1062 int32_t ism330dhcx_xl_offset_weight_get(const stmdev_ctx_t *ctx,
1063 ism330dhcx_usr_off_w_t *val)
1064 {
1065 ism330dhcx_ctrl6_c_t ctrl6_c;
1066 int32_t ret;
1067 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL6_C,
1068 (uint8_t *)&ctrl6_c, 1);
1069
1070 switch (ctrl6_c.usr_off_w)
1071 {
1072 case ISM330DHCX_LSb_1mg:
1073 *val = ISM330DHCX_LSb_1mg;
1074 break;
1075
1076 case ISM330DHCX_LSb_16mg:
1077 *val = ISM330DHCX_LSb_16mg;
1078 break;
1079
1080 default:
1081 *val = ISM330DHCX_LSb_1mg;
1082 break;
1083 }
1084
1085 return ret;
1086 }
1087
1088 /**
1089 * @brief Accelerometer power mode.[set]
1090 *
1091 * @param ctx Read / write interface definitions.(ptr)
1092 * @param val Change the values of xl_hm_mode in reg CTRL6_C
1093 * @retval Interface status (MANDATORY: return 0 -> no Error).
1094 *
1095 */
ism330dhcx_xl_power_mode_set(const stmdev_ctx_t * ctx,ism330dhcx_xl_hm_mode_t val)1096 int32_t ism330dhcx_xl_power_mode_set(const stmdev_ctx_t *ctx,
1097 ism330dhcx_xl_hm_mode_t val)
1098 {
1099 ism330dhcx_ctrl6_c_t ctrl6_c;
1100 int32_t ret;
1101 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL6_C,
1102 (uint8_t *)&ctrl6_c, 1);
1103
1104 if (ret == 0)
1105 {
1106 ctrl6_c.xl_hm_mode = (uint8_t)val & 0x01U;
1107 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL6_C,
1108 (uint8_t *)&ctrl6_c, 1);
1109 }
1110
1111 return ret;
1112 }
1113
1114 /**
1115 * @brief Accelerometer power mode[get]
1116 *
1117 * @param ctx Read / write interface definitions.(ptr)
1118 * @param val Get the values of xl_hm_mode in reg CTRL6_C
1119 * @retval Interface status (MANDATORY: return 0 -> no Error).
1120 *
1121 */
ism330dhcx_xl_power_mode_get(const stmdev_ctx_t * ctx,ism330dhcx_xl_hm_mode_t * val)1122 int32_t ism330dhcx_xl_power_mode_get(const stmdev_ctx_t *ctx,
1123 ism330dhcx_xl_hm_mode_t *val)
1124 {
1125 ism330dhcx_ctrl6_c_t ctrl6_c;
1126 int32_t ret;
1127 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL6_C,
1128 (uint8_t *)&ctrl6_c, 1);
1129
1130 switch (ctrl6_c.xl_hm_mode)
1131 {
1132 case ISM330DHCX_HIGH_PERFORMANCE_MD:
1133 *val = ISM330DHCX_HIGH_PERFORMANCE_MD;
1134 break;
1135
1136 case ISM330DHCX_LOW_NORMAL_POWER_MD:
1137 *val = ISM330DHCX_LOW_NORMAL_POWER_MD;
1138 break;
1139
1140 default:
1141 *val = ISM330DHCX_HIGH_PERFORMANCE_MD;
1142 break;
1143 }
1144
1145 return ret;
1146 }
1147
1148 /**
1149 * @brief Operating mode for gyroscope.[set]
1150 *
1151 * @param ctx Read / write interface definitions.(ptr)
1152 * @param val Change the values of g_hm_mode in reg CTRL7_G
1153 * @retval Interface status (MANDATORY: return 0 -> no Error).
1154 *
1155 */
ism330dhcx_gy_power_mode_set(const stmdev_ctx_t * ctx,ism330dhcx_g_hm_mode_t val)1156 int32_t ism330dhcx_gy_power_mode_set(const stmdev_ctx_t *ctx,
1157 ism330dhcx_g_hm_mode_t val)
1158 {
1159 ism330dhcx_ctrl7_g_t ctrl7_g;
1160 int32_t ret;
1161 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL7_G,
1162 (uint8_t *)&ctrl7_g, 1);
1163
1164 if (ret == 0)
1165 {
1166 ctrl7_g.g_hm_mode = (uint8_t)val;
1167 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL7_G,
1168 (uint8_t *)&ctrl7_g, 1);
1169 }
1170
1171 return ret;
1172 }
1173
1174 /**
1175 * @brief gy_power_mode: [get] Operating mode for gyroscope.
1176 *
1177 * @param ctx Read / write interface definitions.(ptr)
1178 * @param val Get the values of g_hm_mode in reg CTRL7_G
1179 * @retval Interface status (MANDATORY: return 0 -> no Error).
1180 *
1181 */
ism330dhcx_gy_power_mode_get(const stmdev_ctx_t * ctx,ism330dhcx_g_hm_mode_t * val)1182 int32_t ism330dhcx_gy_power_mode_get(const stmdev_ctx_t *ctx,
1183 ism330dhcx_g_hm_mode_t *val)
1184 {
1185 ism330dhcx_ctrl7_g_t ctrl7_g;
1186 int32_t ret;
1187 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL7_G,
1188 (uint8_t *)&ctrl7_g, 1);
1189
1190 switch (ctrl7_g.g_hm_mode)
1191 {
1192 case ISM330DHCX_GY_HIGH_PERFORMANCE:
1193 *val = ISM330DHCX_GY_HIGH_PERFORMANCE;
1194 break;
1195
1196 case ISM330DHCX_GY_NORMAL:
1197 *val = ISM330DHCX_GY_NORMAL;
1198 break;
1199
1200 default:
1201 *val = ISM330DHCX_GY_HIGH_PERFORMANCE;
1202 break;
1203 }
1204
1205 return ret;
1206 }
1207
1208 /**
1209 * @brief Read all the interrupt flag of the device.
1210 *[get]
1211 * @param ctx Read / write interface definitions.(ptr)
1212 * @param val Get registers ALL_INT_SRC; WAKE_UP_SRC;
1213 * TAP_SRC; D6D_SRC; STATUS_REG;
1214 * EMB_FUNC_STATUS; FSM_STATUS_A/B
1215 * @retval Interface status (MANDATORY: return 0 -> no Error).
1216 *
1217 */
ism330dhcx_all_sources_get(const stmdev_ctx_t * ctx,ism330dhcx_all_sources_t * val)1218 int32_t ism330dhcx_all_sources_get(const stmdev_ctx_t *ctx,
1219 ism330dhcx_all_sources_t *val)
1220 {
1221 int32_t ret;
1222
1223 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_ALL_INT_SRC,
1224 (uint8_t *)&val->all_int_src, 1);
1225
1226 if (ret == 0)
1227 {
1228 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_WAKE_UP_SRC,
1229 (uint8_t *)&val->wake_up_src, 1);
1230 }
1231
1232 if (ret == 0)
1233 {
1234 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_SRC,
1235 (uint8_t *)&val->tap_src, 1);
1236 }
1237
1238 if (ret == 0)
1239 {
1240 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_D6D_SRC,
1241 (uint8_t *)&val->d6d_src, 1);
1242 }
1243
1244 if (ret == 0)
1245 {
1246 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_STATUS_REG,
1247 (uint8_t *)&val->status_reg, 1);
1248 }
1249
1250 if (ret == 0)
1251 {
1252 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
1253 }
1254
1255 if (ret == 0)
1256 {
1257 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_STATUS,
1258 (uint8_t *)&val->emb_func_status, 1);
1259 }
1260
1261 if (ret == 0)
1262 {
1263 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FSM_STATUS_A,
1264 (uint8_t *)&val->fsm_status_a, 1);
1265 }
1266
1267 if (ret == 0)
1268 {
1269 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FSM_STATUS_B,
1270 (uint8_t *)&val->fsm_status_b, 1);
1271 }
1272
1273 if (ret == 0)
1274 {
1275 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
1276 }
1277
1278 return ret;
1279 }
1280
1281 /**
1282 * @brief The STATUS_REG register is read by the primary interface.[get]
1283 *
1284 * @param ctx Read / write interface definitions.(ptr)
1285 * @param val Get register STATUS_REG
1286 * @retval Interface status (MANDATORY: return 0 -> no Error).
1287 *
1288 */
ism330dhcx_status_reg_get(const stmdev_ctx_t * ctx,ism330dhcx_status_reg_t * val)1289 int32_t ism330dhcx_status_reg_get(const stmdev_ctx_t *ctx,
1290 ism330dhcx_status_reg_t *val)
1291 {
1292 int32_t ret;
1293
1294 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_STATUS_REG, (uint8_t *) val, 1);
1295
1296 return ret;
1297 }
1298
1299 /**
1300 * @brief Accelerometer new data available.[get]
1301 *
1302 * @param ctx Read / write interface definitions.(ptr)
1303 * @param val Change the values of xlda in reg STATUS_REG
1304 * @retval Interface status (MANDATORY: return 0 -> no Error).
1305 *
1306 */
ism330dhcx_xl_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)1307 int32_t ism330dhcx_xl_flag_data_ready_get(const stmdev_ctx_t *ctx,
1308 uint8_t *val)
1309 {
1310 ism330dhcx_status_reg_t status_reg;
1311 int32_t ret;
1312
1313 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_STATUS_REG,
1314 (uint8_t *)&status_reg, 1);
1315 *val = status_reg.xlda;
1316
1317 return ret;
1318 }
1319
1320 /**
1321 * @brief Gyroscope new data available.[get]
1322 *
1323 * @param ctx Read / write interface definitions.(ptr)
1324 * @param val Change the values of gda in reg STATUS_REG
1325 * @retval Interface status (MANDATORY: return 0 -> no Error).
1326 *
1327 */
ism330dhcx_gy_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)1328 int32_t ism330dhcx_gy_flag_data_ready_get(const stmdev_ctx_t *ctx,
1329 uint8_t *val)
1330 {
1331 ism330dhcx_status_reg_t status_reg;
1332 int32_t ret;
1333
1334 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_STATUS_REG,
1335 (uint8_t *)&status_reg, 1);
1336 *val = status_reg.gda;
1337
1338 return ret;
1339 }
1340
1341 /**
1342 * @brief Temperature new data available.[get]
1343 *
1344 * @param ctx Read / write interface definitions.(ptr)
1345 * @param val Change the values of tda in reg STATUS_REG
1346 * @retval Interface status (MANDATORY: return 0 -> no Error).
1347 *
1348 */
ism330dhcx_temp_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)1349 int32_t ism330dhcx_temp_flag_data_ready_get(const stmdev_ctx_t *ctx,
1350 uint8_t *val)
1351 {
1352 ism330dhcx_status_reg_t status_reg;
1353 int32_t ret;
1354
1355 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_STATUS_REG,
1356 (uint8_t *)&status_reg, 1);
1357 *val = status_reg.tda;
1358
1359 return ret;
1360 }
1361
1362 /**
1363 * @brief Accelerometer X-axis user offset correction expressed in two's
1364 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1365 * The value must be in the range [-127 127].[set]
1366 *
1367 * @param ctx Read / write interface definitions.(ptr)
1368 * @param buff Buffer that contains data to write
1369 * @retval Interface status (MANDATORY: return 0 -> no Error).
1370 *
1371 */
ism330dhcx_xl_usr_offset_x_set(const stmdev_ctx_t * ctx,uint8_t * buff)1372 int32_t ism330dhcx_xl_usr_offset_x_set(const stmdev_ctx_t *ctx,
1373 uint8_t *buff)
1374 {
1375 int32_t ret;
1376
1377 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_X_OFS_USR, buff, 1);
1378
1379 return ret;
1380 }
1381
1382 /**
1383 * @brief Accelerometer X-axis user offset correction expressed in two's
1384 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1385 * The value must be in the range [-127 127].[get]
1386 *
1387 * @param ctx Read / write interface definitions.(ptr)
1388 * @param buff Buffer that stores data read
1389 * @retval Interface status (MANDATORY: return 0 -> no Error).
1390 *
1391 */
ism330dhcx_xl_usr_offset_x_get(const stmdev_ctx_t * ctx,uint8_t * buff)1392 int32_t ism330dhcx_xl_usr_offset_x_get(const stmdev_ctx_t *ctx,
1393 uint8_t *buff)
1394 {
1395 int32_t ret;
1396
1397 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_X_OFS_USR, buff, 1);
1398
1399 return ret;
1400 }
1401
1402 /**
1403 * @brief Accelerometer Y-axis user offset correction expressed in two's
1404 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1405 * The value must be in the range [-127 127].[set]
1406 *
1407 * @param ctx Read / write interface definitions.(ptr)
1408 * @param buff Buffer that contains data to write
1409 * @retval Interface status (MANDATORY: return 0 -> no Error).
1410 *
1411 */
ism330dhcx_xl_usr_offset_y_set(const stmdev_ctx_t * ctx,uint8_t * buff)1412 int32_t ism330dhcx_xl_usr_offset_y_set(const stmdev_ctx_t *ctx,
1413 uint8_t *buff)
1414 {
1415 int32_t ret;
1416
1417 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_Y_OFS_USR, buff, 1);
1418
1419 return ret;
1420 }
1421
1422 /**
1423 * @brief Accelerometer Y-axis user offset correction expressed in two's
1424 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1425 * The value must be in the range [-127 127].[get]
1426 *
1427 * @param ctx Read / write interface definitions.(ptr)
1428 * @param buff Buffer that stores data read
1429 * @retval Interface status (MANDATORY: return 0 -> no Error).
1430 *
1431 */
ism330dhcx_xl_usr_offset_y_get(const stmdev_ctx_t * ctx,uint8_t * buff)1432 int32_t ism330dhcx_xl_usr_offset_y_get(const stmdev_ctx_t *ctx,
1433 uint8_t *buff)
1434 {
1435 int32_t ret;
1436
1437 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_Y_OFS_USR, buff, 1);
1438
1439 return ret;
1440 }
1441
1442 /**
1443 * @brief Accelerometer Z-axis user offset correction expressed in two's
1444 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1445 * The value must be in the range [-127 127].[set]
1446 *
1447 * @param ctx Read / write interface definitions.(ptr)
1448 * @param buff Buffer that contains data to write
1449 * @retval Interface status (MANDATORY: return 0 -> no Error).
1450 *
1451 */
ism330dhcx_xl_usr_offset_z_set(const stmdev_ctx_t * ctx,uint8_t * buff)1452 int32_t ism330dhcx_xl_usr_offset_z_set(const stmdev_ctx_t *ctx,
1453 uint8_t *buff)
1454 {
1455 int32_t ret;
1456
1457 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_Z_OFS_USR, buff, 1);
1458
1459 return ret;
1460 }
1461
1462 /**
1463 * @brief Accelerometer X-axis user offset correction expressed in two's
1464 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1465 * The value must be in the range [-127 127].[get]
1466 *
1467 * @param ctx Read / write interface definitions.(ptr)
1468 * @param buff Buffer that stores data read
1469 * @retval Interface status (MANDATORY: return 0 -> no Error).
1470 *
1471 */
ism330dhcx_xl_usr_offset_z_get(const stmdev_ctx_t * ctx,uint8_t * buff)1472 int32_t ism330dhcx_xl_usr_offset_z_get(const stmdev_ctx_t *ctx,
1473 uint8_t *buff)
1474 {
1475 int32_t ret;
1476
1477 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_Z_OFS_USR, buff, 1);
1478
1479 return ret;
1480 }
1481
1482 /**
1483 * @brief Enables user offset on out.[set]
1484 *
1485 * @param ctx Read / write interface definitions.(ptr)
1486 * @param val Change the values of usr_off_on_out in reg CTRL7_G
1487 * @retval Interface status (MANDATORY: return 0 -> no Error).
1488 *
1489 */
ism330dhcx_xl_usr_offset_set(const stmdev_ctx_t * ctx,uint8_t val)1490 int32_t ism330dhcx_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val)
1491 {
1492 ism330dhcx_ctrl7_g_t ctrl7_g;
1493 int32_t ret;
1494
1495 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL7_G,
1496 (uint8_t *)&ctrl7_g, 1);
1497
1498 if (ret == 0)
1499 {
1500 ctrl7_g.usr_off_on_out = (uint8_t)val;
1501 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL7_G,
1502 (uint8_t *)&ctrl7_g, 1);
1503 }
1504
1505 return ret;
1506 }
1507
1508 /**
1509 * @brief Get user offset on out flag.[get]
1510 *
1511 * @param ctx Read / write interface definitions.(ptr)
1512 * @param val Get values of usr_off_on_out in reg CTRL7_G
1513 * @retval Interface status (MANDATORY: return 0 -> no Error).
1514 *
1515 */
ism330dhcx_xl_usr_offset_get(const stmdev_ctx_t * ctx,uint8_t * val)1516 int32_t ism330dhcx_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val)
1517 {
1518 ism330dhcx_ctrl7_g_t ctrl7_g;
1519 int32_t ret;
1520
1521 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL7_G,
1522 (uint8_t *)&ctrl7_g, 1);
1523 *val = ctrl7_g.usr_off_on_out;
1524
1525 return ret;
1526 }
1527
1528 /**
1529 * @}
1530 *
1531 */
1532
1533 /**
1534 * @defgroup ISM330DHCX_Timestamp
1535 * @brief This section groups all the functions that manage the
1536 * timestamp generation.
1537 * @{
1538 *
1539 */
1540
1541 /**
1542 * @brief Reset timestamp counter.[set]
1543 *
1544 * @param ctx Read / write interface definitions.(ptr)
1545 * @retval Interface status (MANDATORY: return 0 -> no Error).
1546 *
1547 */
ism330dhcx_timestamp_rst(const stmdev_ctx_t * ctx)1548 int32_t ism330dhcx_timestamp_rst(const stmdev_ctx_t *ctx)
1549 {
1550 uint8_t rst_val = 0xAA;
1551 return ism330dhcx_write_reg(ctx, ISM330DHCX_TIMESTAMP2, &rst_val, 1);
1552 }
1553
1554 /**
1555 * @brief Enables timestamp counter.[set]
1556 *
1557 * @param ctx Read / write interface definitions.(ptr)
1558 * @param val Change the values of timestamp_en in reg CTRL10_C
1559 * @retval Interface status (MANDATORY: return 0 -> no Error).
1560 *
1561 */
ism330dhcx_timestamp_set(const stmdev_ctx_t * ctx,uint8_t val)1562 int32_t ism330dhcx_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val)
1563 {
1564 ism330dhcx_ctrl10_c_t ctrl10_c;
1565 int32_t ret;
1566
1567 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL10_C,
1568 (uint8_t *)&ctrl10_c, 1);
1569
1570 if (ret == 0)
1571 {
1572 ctrl10_c.timestamp_en = (uint8_t)val;
1573 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL10_C,
1574 (uint8_t *)&ctrl10_c, 1);
1575 }
1576
1577 return ret;
1578 }
1579
1580 /**
1581 * @brief Enables timestamp counter.[get]
1582 *
1583 * @param ctx Read / write interface definitions.(ptr)
1584 * @param val Change the values of timestamp_en in reg CTRL10_C
1585 * @retval Interface status (MANDATORY: return 0 -> no Error).
1586 *
1587 */
ism330dhcx_timestamp_get(const stmdev_ctx_t * ctx,uint8_t * val)1588 int32_t ism330dhcx_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val)
1589 {
1590 ism330dhcx_ctrl10_c_t ctrl10_c;
1591 int32_t ret;
1592
1593 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL10_C,
1594 (uint8_t *)&ctrl10_c, 1);
1595 *val = ctrl10_c.timestamp_en;
1596
1597 return ret;
1598 }
1599
1600 /**
1601 * @brief Timestamp first data output register (r).
1602 * The value is expressed as a 32-bit word and the bit resolution
1603 * is 25 us.[get]
1604 *
1605 * @param ctx Read / write interface definitions.(ptr)
1606 * @param buff Buffer that stores data read
1607 * @retval Interface status (MANDATORY: return 0 -> no Error).
1608 *
1609 */
ism330dhcx_timestamp_raw_get(const stmdev_ctx_t * ctx,uint32_t * val)1610 int32_t ism330dhcx_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val)
1611 {
1612 uint8_t buff[4];
1613 int32_t ret;
1614
1615 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TIMESTAMP0, buff, 4);
1616 *val = buff[3];
1617 *val = (*val * 256U) + buff[2];
1618 *val = (*val * 256U) + buff[1];
1619 *val = (*val * 256U) + buff[0];
1620
1621 return ret;
1622 }
1623
1624 /**
1625 * @}
1626 *
1627 */
1628
1629 /**
1630 * @defgroup ISM330DHCX_Data output
1631 * @brief This section groups all the data output functions.
1632 * @{
1633 *
1634 */
1635
1636 /**
1637 * @brief Circular burst-mode (rounding) read of the output registers.[set]
1638 *
1639 * @param ctx Read / write interface definitions.(ptr)
1640 * @param val Change the values of rounding in reg CTRL5_C
1641 * @retval Interface status (MANDATORY: return 0 -> no Error).
1642 *
1643 */
ism330dhcx_rounding_mode_set(const stmdev_ctx_t * ctx,ism330dhcx_rounding_t val)1644 int32_t ism330dhcx_rounding_mode_set(const stmdev_ctx_t *ctx,
1645 ism330dhcx_rounding_t val)
1646 {
1647 ism330dhcx_ctrl5_c_t ctrl5_c;
1648 int32_t ret;
1649
1650 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL5_C,
1651 (uint8_t *)&ctrl5_c, 1);
1652
1653 if (ret == 0)
1654 {
1655 ctrl5_c.rounding = (uint8_t)val;
1656 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL5_C,
1657 (uint8_t *)&ctrl5_c, 1);
1658 }
1659
1660 return ret;
1661 }
1662
1663 /**
1664 * @brief Gyroscope UI chain full-scale selection.[get]
1665 *
1666 * @param ctx Read / write interface definitions.(ptr)
1667 * @param val Get the values of rounding in reg CTRL5_C
1668 * @retval Interface status (MANDATORY: return 0 -> no Error).
1669 *
1670 */
ism330dhcx_rounding_mode_get(const stmdev_ctx_t * ctx,ism330dhcx_rounding_t * val)1671 int32_t ism330dhcx_rounding_mode_get(const stmdev_ctx_t *ctx,
1672 ism330dhcx_rounding_t *val)
1673 {
1674 ism330dhcx_ctrl5_c_t ctrl5_c;
1675 int32_t ret;
1676
1677 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL5_C,
1678 (uint8_t *)&ctrl5_c, 1);
1679
1680 switch (ctrl5_c.rounding)
1681 {
1682 case ISM330DHCX_NO_ROUND:
1683 *val = ISM330DHCX_NO_ROUND;
1684 break;
1685
1686 case ISM330DHCX_ROUND_XL:
1687 *val = ISM330DHCX_ROUND_XL;
1688 break;
1689
1690 case ISM330DHCX_ROUND_GY:
1691 *val = ISM330DHCX_ROUND_GY;
1692 break;
1693
1694 case ISM330DHCX_ROUND_GY_XL:
1695 *val = ISM330DHCX_ROUND_GY_XL;
1696 break;
1697
1698 default:
1699 *val = ISM330DHCX_NO_ROUND;
1700 break;
1701 }
1702
1703 return ret;
1704 }
1705
1706 /**
1707 * @brief Temperature data output register (r).
1708 * L and H registers together express a 16-bit word in two's
1709 * complement.[get]
1710 *
1711 * @param ctx Read / write interface definitions.(ptr)
1712 * @param buff Buffer that stores data read
1713 * @retval Interface status (MANDATORY: return 0 -> no Error).
1714 *
1715 */
ism330dhcx_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1716 int32_t ism330dhcx_temperature_raw_get(const stmdev_ctx_t *ctx,
1717 int16_t *val)
1718 {
1719 uint8_t buff[2];
1720 int32_t ret;
1721
1722 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_OUT_TEMP_L, buff, 2);
1723 *val = (int16_t)buff[1];
1724 *val = (*val * 256) + (int16_t)buff[0];
1725
1726 return ret;
1727 }
1728
1729 /**
1730 * @brief Angular rate sensor. The value is expressed as a 16-bit
1731 * word in two's complement.[get]
1732 *
1733 * @param ctx Read / write interface definitions.(ptr)
1734 * @param buff Buffer that stores data read
1735 * @retval Interface status (MANDATORY: return 0 -> no Error).
1736 *
1737 */
ism330dhcx_angular_rate_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1738 int32_t ism330dhcx_angular_rate_raw_get(const stmdev_ctx_t *ctx,
1739 int16_t *val)
1740 {
1741 uint8_t buff[6];
1742 int32_t ret;
1743
1744 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_OUTX_L_G, buff, 6);
1745 val[0] = (int16_t)buff[1];
1746 val[0] = (val[0] * 256) + (int16_t)buff[0];
1747 val[1] = (int16_t)buff[3];
1748 val[1] = (val[1] * 256) + (int16_t)buff[2];
1749 val[2] = (int16_t)buff[5];
1750 val[2] = (val[2] * 256) + (int16_t)buff[4];
1751
1752 return ret;
1753 }
1754
1755 /**
1756 * @brief Linear acceleration output register. The value is expressed as a
1757 * 16-bit word in two's complement.[get]
1758 *
1759 * @param ctx Read / write interface definitions.(ptr)
1760 * @param buff Buffer that stores data read
1761 * @retval Interface status (MANDATORY: return 0 -> no Error).
1762 *
1763 */
ism330dhcx_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1764 int32_t ism330dhcx_acceleration_raw_get(const stmdev_ctx_t *ctx,
1765 int16_t *val)
1766 {
1767 uint8_t buff[6];
1768 int32_t ret;
1769
1770 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_OUTX_L_A, buff, 6);
1771 val[0] = (int16_t)buff[1];
1772 val[0] = (val[0] * 256) + (int16_t)buff[0];
1773 val[1] = (int16_t)buff[3];
1774 val[1] = (val[1] * 256) + (int16_t)buff[2];
1775 val[2] = (int16_t)buff[5];
1776 val[2] = (val[2] * 256) + (int16_t)buff[4];
1777
1778 return ret;
1779 }
1780
1781 /**
1782 * @brief FIFO data output.[get]
1783 *
1784 * @param ctx Read / write interface definitions.(ptr)
1785 * @param buff Buffer that stores data read
1786 * @retval Interface status (MANDATORY: return 0 -> no Error).
1787 *
1788 */
ism330dhcx_fifo_out_raw_get(const stmdev_ctx_t * ctx,uint8_t * buff)1789 int32_t ism330dhcx_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff)
1790 {
1791 int32_t ret;
1792
1793 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_DATA_OUT_X_L, buff, 6);
1794
1795 return ret;
1796 }
1797
1798 /**
1799 * @brief Step counter output register.[get]
1800 *
1801 * @param ctx Read / write interface definitions.(ptr)
1802 * @param buff Buffer that stores data read
1803 * @retval Interface status (MANDATORY: return 0 -> no Error).
1804 *
1805 */
ism330dhcx_number_of_steps_get(const stmdev_ctx_t * ctx,uint16_t * val)1806 int32_t ism330dhcx_number_of_steps_get(const stmdev_ctx_t *ctx,
1807 uint16_t *val)
1808 {
1809 uint8_t buff[2];
1810 int32_t ret;
1811
1812 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
1813
1814 if (ret == 0)
1815 {
1816 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_STEP_COUNTER_L, buff, 2);
1817 *val = buff[1];
1818 *val = (*val * 256U) + buff[0];
1819 }
1820
1821 if (ret == 0)
1822 {
1823 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
1824 }
1825
1826 return ret;
1827 }
1828
1829 /**
1830 * @brief Reset step counter register.[get]
1831 *
1832 * @param ctx Read / write interface definitions.(ptr)
1833 * @retval Interface status (MANDATORY: return 0 -> no Error).
1834 *
1835 */
ism330dhcx_steps_reset(const stmdev_ctx_t * ctx)1836 int32_t ism330dhcx_steps_reset(const stmdev_ctx_t *ctx)
1837 {
1838 ism330dhcx_emb_func_src_t emb_func_src;
1839 int32_t ret;
1840
1841 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
1842
1843 if (ret == 0)
1844 {
1845 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_SRC,
1846 (uint8_t *)&emb_func_src, 1);
1847 }
1848
1849 if (ret == 0)
1850 {
1851 emb_func_src.pedo_rst_step = PROPERTY_ENABLE;
1852 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_EMB_FUNC_SRC,
1853 (uint8_t *)&emb_func_src, 1);
1854 }
1855
1856 if (ret == 0)
1857 {
1858 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
1859 }
1860
1861 return ret;
1862 }
1863
1864 /**
1865 * @}
1866 *
1867 */
1868
1869 /**
1870 * @defgroup ISM330DHCX_common
1871 * @brief This section groups common useful functions.
1872 * @{
1873 *
1874 */
1875
1876 /**
1877 * @brief DEVICE_CONF bit configuration[set]
1878 *
1879 * @param ctx Read / write interface definitions.(ptr)
1880 * @param val Change the values of device_conf in reg CTRL9_XL
1881 * @retval Interface status (MANDATORY: return 0 -> no Error).
1882 *
1883 */
ism330dhcx_device_conf_set(const stmdev_ctx_t * ctx,uint8_t val)1884 int32_t ism330dhcx_device_conf_set(const stmdev_ctx_t *ctx, uint8_t val)
1885 {
1886 ism330dhcx_ctrl9_xl_t ctrl9_xl;
1887 int32_t ret;
1888
1889 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL9_XL,
1890 (uint8_t *)&ctrl9_xl, 1);
1891
1892 if (ret == 0)
1893 {
1894 ctrl9_xl.device_conf = (uint8_t)val;
1895 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL9_XL,
1896 (uint8_t *)&ctrl9_xl, 1);
1897 }
1898
1899 return ret;
1900 }
1901
1902 /**
1903 * @brief DEVICE_CONF bit configuration[get]
1904 *
1905 * @param ctx Read / write interface definitions.(ptr)
1906 * @param val Get the values of device_conf in reg CTRL9_XL
1907 * @retval Interface status (MANDATORY: return 0 -> no Error).
1908 *
1909 */
ism330dhcx_device_conf_get(const stmdev_ctx_t * ctx,uint8_t * val)1910 int32_t ism330dhcx_device_conf_get(const stmdev_ctx_t *ctx, uint8_t *val)
1911 {
1912 ism330dhcx_ctrl9_xl_t ctrl9_xl;
1913 int32_t ret;
1914
1915 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL9_XL,
1916 (uint8_t *)&ctrl9_xl, 1);
1917 *val = ctrl9_xl.device_conf;
1918
1919 return ret;
1920 }
1921
1922 /**
1923 * @brief Difference in percentage of the effective ODR (and timestamp rate)
1924 * with respect to the typical.[set]
1925 * Step: 0.15%. 8-bit format, 2's complement.
1926 *
1927 * @param ctx Read / write interface definitions.(ptr)
1928 * @param val Change the values of freq_fine in reg INTERNAL_FREQ_FINE
1929 * @retval Interface status (MANDATORY: return 0 -> no Error).
1930 *
1931 */
ism330dhcx_odr_cal_reg_set(const stmdev_ctx_t * ctx,uint8_t val)1932 int32_t ism330dhcx_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val)
1933 {
1934 ism330dhcx_internal_freq_fine_t internal_freq_fine;
1935 int32_t ret;
1936
1937 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INTERNAL_FREQ_FINE,
1938 (uint8_t *)&internal_freq_fine, 1);
1939
1940 if (ret == 0)
1941 {
1942 internal_freq_fine.freq_fine = (uint8_t)val;
1943 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_INTERNAL_FREQ_FINE,
1944 (uint8_t *)&internal_freq_fine, 1);
1945 }
1946
1947 return ret;
1948 }
1949
1950 /**
1951 * @brief Difference in percentage of the effective ODR (and timestamp rate)
1952 * with respect to the typical.[get]
1953 * Step: 0.15%. 8-bit format, 2's complement.
1954 *
1955 * @param ctx Read / write interface definitions.(ptr)
1956 * @param val Change the values of freq_fine in reg INTERNAL_FREQ_FINE
1957 * @retval Interface status (MANDATORY: return 0 -> no Error).
1958 *
1959 */
ism330dhcx_odr_cal_reg_get(const stmdev_ctx_t * ctx,uint8_t * val)1960 int32_t ism330dhcx_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val)
1961 {
1962 ism330dhcx_internal_freq_fine_t internal_freq_fine;
1963 int32_t ret;
1964
1965 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INTERNAL_FREQ_FINE,
1966 (uint8_t *)&internal_freq_fine, 1);
1967 *val = internal_freq_fine.freq_fine;
1968
1969 return ret;
1970 }
1971
1972 /**
1973 * @brief Enable access to the embedded functions/sensor hub configuration
1974 * registers.[set]
1975 *
1976 * @param ctx Read / write interface definitions.(ptr)
1977 * @param val Change the values of reg_access in reg FUNC_CFG_ACCESS
1978 * @retval Interface status (MANDATORY: return 0 -> no Error).
1979 *
1980 */
ism330dhcx_mem_bank_set(const stmdev_ctx_t * ctx,ism330dhcx_reg_access_t val)1981 int32_t ism330dhcx_mem_bank_set(const stmdev_ctx_t *ctx,
1982 ism330dhcx_reg_access_t val)
1983 {
1984 ism330dhcx_func_cfg_access_t func_cfg_access;
1985 int32_t ret;
1986
1987 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FUNC_CFG_ACCESS,
1988 (uint8_t *)&func_cfg_access, 1);
1989
1990 if (ret == 0)
1991 {
1992 func_cfg_access.reg_access = (uint8_t)val;
1993 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_FUNC_CFG_ACCESS,
1994 (uint8_t *)&func_cfg_access, 1);
1995 }
1996
1997 return ret;
1998 }
1999
2000 /**
2001 * @brief Enable access to the embedded functions/sensor hub configuration
2002 * registers.[get]
2003 *
2004 * @param ctx Read / write interface definitions.(ptr)
2005 * @param val Get the values of reg_access in reg FUNC_CFG_ACCESS
2006 * @retval Interface status (MANDATORY: return 0 -> no Error).
2007 *
2008 */
ism330dhcx_mem_bank_get(const stmdev_ctx_t * ctx,ism330dhcx_reg_access_t * val)2009 int32_t ism330dhcx_mem_bank_get(const stmdev_ctx_t *ctx,
2010 ism330dhcx_reg_access_t *val)
2011 {
2012 ism330dhcx_func_cfg_access_t func_cfg_access;
2013 int32_t ret;
2014
2015 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FUNC_CFG_ACCESS,
2016 (uint8_t *)&func_cfg_access, 1);
2017
2018 switch (func_cfg_access.reg_access)
2019 {
2020 case ISM330DHCX_USER_BANK:
2021 *val = ISM330DHCX_USER_BANK;
2022 break;
2023
2024 case ISM330DHCX_SENSOR_HUB_BANK:
2025 *val = ISM330DHCX_SENSOR_HUB_BANK;
2026 break;
2027
2028 case ISM330DHCX_EMBEDDED_FUNC_BANK:
2029 *val = ISM330DHCX_EMBEDDED_FUNC_BANK;
2030 break;
2031
2032 default:
2033 *val = ISM330DHCX_USER_BANK;
2034 break;
2035 }
2036
2037 return ret;
2038 }
2039
2040 /**
2041 * @brief Write a line(byte) in a page.[set]
2042 *
2043 * @param ctx Read / write interface definitions.(ptr)
2044 * @param add Page line address
2045 * @param val Value to write
2046 * @retval Interface status (MANDATORY: return 0 -> no Error).
2047 *
2048 */
ism330dhcx_ln_pg_write_byte(const stmdev_ctx_t * ctx,uint16_t add,uint8_t * val)2049 int32_t ism330dhcx_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t add,
2050 uint8_t *val)
2051 {
2052 ism330dhcx_page_rw_t page_rw;
2053 ism330dhcx_page_sel_t page_sel;
2054 ism330dhcx_page_address_t page_address;
2055 int32_t ret;
2056
2057 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
2058
2059 if (ret == 0)
2060 {
2061 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_RW,
2062 (uint8_t *)&page_rw, 1);
2063 }
2064
2065 if (ret == 0)
2066 {
2067 page_rw.page_rw = 0x02U; /* page_write enable */
2068 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_RW,
2069 (uint8_t *)&page_rw, 1);
2070 }
2071
2072 if (ret == 0)
2073 {
2074 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_SEL,
2075 (uint8_t *)&page_sel, 1);
2076 }
2077
2078 if (ret == 0)
2079 {
2080 page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU);
2081 page_sel.not_used_01 = 1;
2082 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_SEL,
2083 (uint8_t *)&page_sel, 1);
2084 }
2085
2086 if (ret == 0)
2087 {
2088 page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U));
2089 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_ADDRESS,
2090 (uint8_t *)&page_address, 1);
2091 }
2092
2093 if (ret == 0)
2094 {
2095 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_VALUE, val, 1);
2096 }
2097
2098 if (ret == 0)
2099 {
2100 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_RW,
2101 (uint8_t *)&page_rw, 1);
2102 }
2103
2104 if (ret == 0)
2105 {
2106 page_rw.page_rw = 0x00; /* page_write disable */
2107 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_RW,
2108 (uint8_t *)&page_rw, 1);
2109 }
2110
2111 if (ret == 0)
2112 {
2113 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
2114 }
2115
2116 return ret;
2117 }
2118
2119 /**
2120 * @brief Write buffer in a page.[set]
2121 *
2122 * @param ctx Read / write interface definitions.(ptr)
2123 * @param buf Page line address.(ptr)
2124 * @param val Value to write.
2125 * @param len buffer length.
2126 * @retval Interface status (MANDATORY: return 0 -> no Error).
2127 *
2128 */
ism330dhcx_ln_pg_write(const stmdev_ctx_t * ctx,uint16_t add,uint8_t * buf,uint8_t len)2129 int32_t ism330dhcx_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t add,
2130 uint8_t *buf, uint8_t len)
2131 {
2132 ism330dhcx_page_rw_t page_rw;
2133 ism330dhcx_page_sel_t page_sel;
2134 ism330dhcx_page_address_t page_address;
2135 uint8_t msb;
2136 uint8_t lsb;
2137 int32_t ret;
2138 uint8_t i ;
2139
2140 msb = (uint8_t)((add / 256U) & 0x0FU);
2141 lsb = (uint8_t)(add - (msb * 256U));
2142 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
2143
2144 if (ret == 0)
2145 {
2146 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_RW,
2147 (uint8_t *)&page_rw, 1);
2148 }
2149
2150 if (ret == 0)
2151 {
2152 page_rw.page_rw = 0x02U; /* page_write enable*/
2153 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_RW,
2154 (uint8_t *)&page_rw, 1);
2155 }
2156
2157 if (ret == 0)
2158 {
2159 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_SEL,
2160 (uint8_t *)&page_sel, 1);
2161 }
2162
2163 if (ret == 0)
2164 {
2165 page_sel.page_sel = msb;
2166 page_sel.not_used_01 = 1;
2167 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_SEL,
2168 (uint8_t *)&page_sel, 1);
2169 }
2170
2171 if (ret == 0)
2172 {
2173 page_address.page_addr = lsb;
2174 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_ADDRESS,
2175 (uint8_t *)&page_address, 1);
2176 }
2177
2178 for (i = 0; i < len; i++)
2179 {
2180 if (ret == 0)
2181 {
2182 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_VALUE, &buf[i], 1);
2183
2184 if (ret == 0)
2185 {
2186 /* Check if page wrap */
2187 if (lsb == 0x00U)
2188 {
2189 msb++;
2190 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_SEL,
2191 (uint8_t *)&page_sel, 1);
2192 }
2193
2194 lsb++;
2195 }
2196
2197 if (ret == 0)
2198 {
2199 page_sel.page_sel = msb;
2200 page_sel.not_used_01 = 1;
2201 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_SEL,
2202 (uint8_t *)&page_sel, 1);
2203 }
2204 }
2205 }
2206
2207 if (ret == 0)
2208 {
2209 page_sel.page_sel = 0;
2210 page_sel.not_used_01 = 1;
2211 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_SEL,
2212 (uint8_t *)&page_sel, 1);
2213 }
2214
2215 if (ret == 0)
2216 {
2217 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_RW,
2218 (uint8_t *)&page_rw, 1);
2219 }
2220
2221 if (ret == 0)
2222 {
2223 page_rw.page_rw = 0x00U; /* page_write disable */
2224 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_RW,
2225 (uint8_t *)&page_rw, 1);
2226 }
2227
2228 if (ret == 0)
2229 {
2230 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
2231 }
2232
2233 return ret;
2234 }
2235
2236 /**
2237 * @brief Read a line(byte) in a page.[get]
2238 *
2239 * @param ctx Read / write interface definitions.(ptr)
2240 * @param add Page line address.
2241 * @param val Read value.(ptr)
2242 * @retval Interface status (MANDATORY: return 0 -> no Error).
2243 *
2244 */
ism330dhcx_ln_pg_read_byte(const stmdev_ctx_t * ctx,uint16_t add,uint8_t * val)2245 int32_t ism330dhcx_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t add,
2246 uint8_t *val)
2247 {
2248 ism330dhcx_page_rw_t page_rw;
2249 ism330dhcx_page_sel_t page_sel;
2250 ism330dhcx_page_address_t page_address;
2251 int32_t ret;
2252
2253 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
2254
2255 if (ret == 0)
2256 {
2257 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_RW,
2258 (uint8_t *)&page_rw, 1);
2259 }
2260
2261 if (ret == 0)
2262 {
2263 page_rw.page_rw = 0x01U; /* page_read enable*/
2264 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_RW,
2265 (uint8_t *)&page_rw, 1);
2266 }
2267
2268 if (ret == 0)
2269 {
2270 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_SEL,
2271 (uint8_t *)&page_sel, 1);
2272 }
2273
2274 if (ret == 0)
2275 {
2276 page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU);
2277 page_sel.not_used_01 = 1;
2278 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_SEL,
2279 (uint8_t *)&page_sel, 1);
2280 }
2281
2282 if (ret == 0)
2283 {
2284 page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U));
2285 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_ADDRESS,
2286 (uint8_t *)&page_address, 1);
2287 }
2288
2289 if (ret == 0)
2290 {
2291 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_VALUE, val, 2);
2292 }
2293
2294 if (ret == 0)
2295 {
2296 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_RW,
2297 (uint8_t *)&page_rw, 1);
2298 }
2299
2300 if (ret == 0)
2301 {
2302 page_rw.page_rw = 0x00U; /* page_read disable */
2303 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_RW,
2304 (uint8_t *)&page_rw, 1);
2305 }
2306
2307 if (ret == 0)
2308 {
2309 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
2310 }
2311
2312 return ret;
2313 }
2314
2315 /**
2316 * @brief Data-ready pulsed / letched mode.[set]
2317 *
2318 * @param ctx Read / write interface definitions.(ptr)
2319 * @param val Change the values of dataready_pulsed in
2320 * reg COUNTER_BDR_REG1
2321 * @retval Interface status (MANDATORY: return 0 -> no Error).
2322 *
2323 */
ism330dhcx_data_ready_mode_set(const stmdev_ctx_t * ctx,ism330dhcx_dataready_pulsed_t val)2324 int32_t ism330dhcx_data_ready_mode_set(const stmdev_ctx_t *ctx,
2325 ism330dhcx_dataready_pulsed_t val)
2326 {
2327 ism330dhcx_counter_bdr_reg1_t counter_bdr_reg1;
2328 int32_t ret;
2329
2330 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_COUNTER_BDR_REG1,
2331 (uint8_t *)&counter_bdr_reg1, 1);
2332
2333 if (ret == 0)
2334 {
2335 counter_bdr_reg1.dataready_pulsed = (uint8_t)val;
2336 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_COUNTER_BDR_REG1,
2337 (uint8_t *)&counter_bdr_reg1, 1);
2338 }
2339
2340 return ret;
2341 }
2342
2343 /**
2344 * @brief Data-ready pulsed / letched mode.[get]
2345 *
2346 * @param ctx Read / write interface definitions.(ptr)
2347 * @param val Get the values of dataready_pulsed in
2348 * reg COUNTER_BDR_REG1
2349 * @retval Interface status (MANDATORY: return 0 -> no Error).
2350 *
2351 */
ism330dhcx_data_ready_mode_get(const stmdev_ctx_t * ctx,ism330dhcx_dataready_pulsed_t * val)2352 int32_t ism330dhcx_data_ready_mode_get(const stmdev_ctx_t *ctx,
2353 ism330dhcx_dataready_pulsed_t *val)
2354 {
2355 ism330dhcx_counter_bdr_reg1_t counter_bdr_reg1;
2356 int32_t ret;
2357
2358 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_COUNTER_BDR_REG1,
2359 (uint8_t *)&counter_bdr_reg1, 1);
2360
2361 switch (counter_bdr_reg1.dataready_pulsed)
2362 {
2363 case ISM330DHCX_DRDY_LATCHED:
2364 *val = ISM330DHCX_DRDY_LATCHED;
2365 break;
2366
2367 case ISM330DHCX_DRDY_PULSED:
2368 *val = ISM330DHCX_DRDY_PULSED;
2369 break;
2370
2371 default:
2372 *val = ISM330DHCX_DRDY_LATCHED;
2373 break;
2374 }
2375
2376 return ret;
2377 }
2378
2379 /**
2380 * @brief Device Who am I.[get]
2381 *
2382 * @param ctx Read / write interface definitions.(ptr)
2383 * @param buff Buffer that stores data read
2384 * @retval Interface status (MANDATORY: return 0 -> no Error).
2385 *
2386 */
ism330dhcx_device_id_get(const stmdev_ctx_t * ctx,uint8_t * buff)2387 int32_t ism330dhcx_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
2388 {
2389 int32_t ret;
2390
2391 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_WHO_AM_I, buff, 1);
2392
2393 return ret;
2394 }
2395
2396 /**
2397 * @brief Software reset. Restore the default values in user registers.[set]
2398 *
2399 * @param ctx Read / write interface definitions.(ptr)
2400 * @param val Change the values of sw_reset in reg CTRL3_C
2401 * @retval Interface status (MANDATORY: return 0 -> no Error).
2402 *
2403 */
ism330dhcx_reset_set(const stmdev_ctx_t * ctx,uint8_t val)2404 int32_t ism330dhcx_reset_set(const stmdev_ctx_t *ctx, uint8_t val)
2405 {
2406 ism330dhcx_ctrl3_c_t ctrl3_c;
2407 int32_t ret;
2408
2409 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C,
2410 (uint8_t *)&ctrl3_c, 1);
2411
2412 if (ret == 0)
2413 {
2414 ctrl3_c.sw_reset = (uint8_t)val;
2415 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL3_C,
2416 (uint8_t *)&ctrl3_c, 1);
2417 }
2418
2419 return ret;
2420 }
2421
2422 /**
2423 * @brief Software reset. Restore the default values in user registers.[get]
2424 *
2425 * @param ctx Read / write interface definitions.(ptr)
2426 * @param val Change the values of sw_reset in reg CTRL3_C
2427 * @retval Interface status (MANDATORY: return 0 -> no Error).
2428 *
2429 */
ism330dhcx_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)2430 int32_t ism330dhcx_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
2431 {
2432 ism330dhcx_ctrl3_c_t ctrl3_c;
2433 int32_t ret;
2434
2435 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C,
2436 (uint8_t *)&ctrl3_c, 1);
2437 *val = ctrl3_c.sw_reset;
2438
2439 return ret;
2440 }
2441
2442 /**
2443 * @brief Register address automatically incremented during a multiple byte
2444 * access with a serial interface.[set]
2445 *
2446 * @param ctx Read / write interface definitions.(ptr)
2447 * @param val Change the values of if_inc in reg CTRL3_C
2448 * @retval Interface status (MANDATORY: return 0 -> no Error).
2449 *
2450 */
ism330dhcx_auto_increment_set(const stmdev_ctx_t * ctx,uint8_t val)2451 int32_t ism330dhcx_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val)
2452 {
2453 ism330dhcx_ctrl3_c_t ctrl3_c;
2454 int32_t ret;
2455
2456 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C,
2457 (uint8_t *)&ctrl3_c, 1);
2458
2459 if (ret == 0)
2460 {
2461 ctrl3_c.if_inc = (uint8_t)val;
2462 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL3_C,
2463 (uint8_t *)&ctrl3_c, 1);
2464 }
2465
2466 return ret;
2467 }
2468
2469 /**
2470 * @brief Register address automatically incremented during a multiple byte
2471 * access with a serial interface.[get]
2472 *
2473 * @param ctx Read / write interface definitions.(ptr)
2474 * @param val Change the values of if_inc in reg CTRL3_C
2475 * @retval Interface status (MANDATORY: return 0 -> no Error).
2476 *
2477 */
ism330dhcx_auto_increment_get(const stmdev_ctx_t * ctx,uint8_t * val)2478 int32_t ism330dhcx_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val)
2479 {
2480 ism330dhcx_ctrl3_c_t ctrl3_c;
2481 int32_t ret;
2482
2483 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C,
2484 (uint8_t *)&ctrl3_c, 1);
2485 *val = ctrl3_c.if_inc;
2486
2487 return ret;
2488 }
2489
2490 /**
2491 * @brief Reboot memory content. Reload the calibration parameters.[set]
2492 *
2493 * @param ctx Read / write interface definitions.(ptr)
2494 * @param val Change the values of boot in reg CTRL3_C
2495 * @retval Interface status (MANDATORY: return 0 -> no Error).
2496 *
2497 */
ism330dhcx_boot_set(const stmdev_ctx_t * ctx,uint8_t val)2498 int32_t ism330dhcx_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
2499 {
2500 ism330dhcx_ctrl3_c_t ctrl3_c;
2501 int32_t ret;
2502
2503 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C,
2504 (uint8_t *)&ctrl3_c, 1);
2505
2506 if (ret == 0)
2507 {
2508 ctrl3_c.boot = (uint8_t)val;
2509 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL3_C,
2510 (uint8_t *)&ctrl3_c, 1);
2511 }
2512
2513 return ret;
2514 }
2515
2516 /**
2517 * @brief Reboot memory content. Reload the calibration parameters.[get]
2518 *
2519 * @param ctx Read / write interface definitions.(ptr)
2520 * @param val Change the values of boot in reg CTRL3_C
2521 * @retval Interface status (MANDATORY: return 0 -> no Error).
2522 *
2523 */
ism330dhcx_boot_get(const stmdev_ctx_t * ctx,uint8_t * val)2524 int32_t ism330dhcx_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
2525 {
2526 ism330dhcx_ctrl3_c_t ctrl3_c;
2527 int32_t ret;
2528
2529 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C,
2530 (uint8_t *)&ctrl3_c, 1);
2531 *val = ctrl3_c.boot;
2532
2533 return ret;
2534 }
2535
2536
2537
2538 /**
2539 * @brief Linear acceleration sensor self-test enable.[set]
2540 *
2541 * @param ctx Read / write interface definitions.(ptr)
2542 * @param val Change the values of st_xl in reg CTRL5_C
2543 * @retval Interface status (MANDATORY: return 0 -> no Error).
2544 *
2545 */
ism330dhcx_xl_self_test_set(const stmdev_ctx_t * ctx,ism330dhcx_st_xl_t val)2546 int32_t ism330dhcx_xl_self_test_set(const stmdev_ctx_t *ctx,
2547 ism330dhcx_st_xl_t val)
2548 {
2549 ism330dhcx_ctrl5_c_t ctrl5_c;
2550 int32_t ret;
2551
2552 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL5_C,
2553 (uint8_t *)&ctrl5_c, 1);
2554
2555 if (ret == 0)
2556 {
2557 ctrl5_c.st_xl = (uint8_t)val;
2558 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL5_C,
2559 (uint8_t *)&ctrl5_c, 1);
2560 }
2561
2562 return ret;
2563 }
2564
2565 /**
2566 * @brief Linear acceleration sensor self-test enable.[get]
2567 *
2568 * @param ctx Read / write interface definitions.(ptr)
2569 * @param val Get the values of st_xl in reg CTRL5_C
2570 * @retval Interface status (MANDATORY: return 0 -> no Error).
2571 *
2572 */
ism330dhcx_xl_self_test_get(const stmdev_ctx_t * ctx,ism330dhcx_st_xl_t * val)2573 int32_t ism330dhcx_xl_self_test_get(const stmdev_ctx_t *ctx,
2574 ism330dhcx_st_xl_t *val)
2575 {
2576 ism330dhcx_ctrl5_c_t ctrl5_c;
2577 int32_t ret;
2578
2579 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL5_C,
2580 (uint8_t *)&ctrl5_c, 1);
2581
2582 switch (ctrl5_c.st_xl)
2583 {
2584 case ISM330DHCX_XL_ST_DISABLE:
2585 *val = ISM330DHCX_XL_ST_DISABLE;
2586 break;
2587
2588 case ISM330DHCX_XL_ST_POSITIVE:
2589 *val = ISM330DHCX_XL_ST_POSITIVE;
2590 break;
2591
2592 case ISM330DHCX_XL_ST_NEGATIVE:
2593 *val = ISM330DHCX_XL_ST_NEGATIVE;
2594 break;
2595
2596 default:
2597 *val = ISM330DHCX_XL_ST_DISABLE;
2598 break;
2599 }
2600
2601 return ret;
2602 }
2603
2604 /**
2605 * @brief Angular rate sensor self-test enable.[set]
2606 *
2607 * @param ctx Read / write interface definitions.(ptr)
2608 * @param val Change the values of st_g in reg CTRL5_C
2609 * @retval Interface status (MANDATORY: return 0 -> no Error).
2610 *
2611 */
ism330dhcx_gy_self_test_set(const stmdev_ctx_t * ctx,ism330dhcx_st_g_t val)2612 int32_t ism330dhcx_gy_self_test_set(const stmdev_ctx_t *ctx,
2613 ism330dhcx_st_g_t val)
2614 {
2615 ism330dhcx_ctrl5_c_t ctrl5_c;
2616 int32_t ret;
2617
2618 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL5_C,
2619 (uint8_t *)&ctrl5_c, 1);
2620
2621 if (ret == 0)
2622 {
2623 ctrl5_c.st_g = (uint8_t)val;
2624 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL5_C,
2625 (uint8_t *)&ctrl5_c, 1);
2626 }
2627
2628 return ret;
2629 }
2630
2631 /**
2632 * @brief Angular rate sensor self-test enable.[get]
2633 *
2634 * @param ctx Read / write interface definitions.(ptr)
2635 * @param val Get the values of st_g in reg CTRL5_C
2636 * @retval Interface status (MANDATORY: return 0 -> no Error).
2637 *
2638 */
ism330dhcx_gy_self_test_get(const stmdev_ctx_t * ctx,ism330dhcx_st_g_t * val)2639 int32_t ism330dhcx_gy_self_test_get(const stmdev_ctx_t *ctx,
2640 ism330dhcx_st_g_t *val)
2641 {
2642 ism330dhcx_ctrl5_c_t ctrl5_c;
2643 int32_t ret;
2644
2645 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL5_C,
2646 (uint8_t *)&ctrl5_c, 1);
2647
2648 switch (ctrl5_c.st_g)
2649 {
2650 case ISM330DHCX_GY_ST_DISABLE:
2651 *val = ISM330DHCX_GY_ST_DISABLE;
2652 break;
2653
2654 case ISM330DHCX_GY_ST_POSITIVE:
2655 *val = ISM330DHCX_GY_ST_POSITIVE;
2656 break;
2657
2658 case ISM330DHCX_GY_ST_NEGATIVE:
2659 *val = ISM330DHCX_GY_ST_NEGATIVE;
2660 break;
2661
2662 default:
2663 *val = ISM330DHCX_GY_ST_DISABLE;
2664 break;
2665 }
2666
2667 return ret;
2668 }
2669
2670 /**
2671 * @}
2672 *
2673 */
2674
2675 /**
2676 * @defgroup ISM330DHCX_filters
2677 * @brief This section group all the functions concerning the
2678 * filters configuration
2679 * @{
2680 *
2681 */
2682
2683 /**
2684 * @brief Accelerometer output from LPF2 filtering stage selection.[set]
2685 *
2686 * @param ctx Read / write interface definitions.(ptr)
2687 * @param val Change the values of lpf2_xl_en in reg CTRL1_XL
2688 * @retval Interface status (MANDATORY: return 0 -> no Error).
2689 *
2690 */
ism330dhcx_xl_filter_lp2_set(const stmdev_ctx_t * ctx,uint8_t val)2691 int32_t ism330dhcx_xl_filter_lp2_set(const stmdev_ctx_t *ctx, uint8_t val)
2692 {
2693 ism330dhcx_ctrl1_xl_t ctrl1_xl;
2694 int32_t ret;
2695
2696 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL1_XL,
2697 (uint8_t *)&ctrl1_xl, 1);
2698
2699 if (ret == 0)
2700 {
2701 ctrl1_xl.lpf2_xl_en = (uint8_t)val;
2702 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL1_XL,
2703 (uint8_t *)&ctrl1_xl, 1);
2704 }
2705
2706 return ret;
2707 }
2708
2709 /**
2710 * @brief Accelerometer output from LPF2 filtering stage selection.[get]
2711 *
2712 * @param ctx Read / write interface definitions.(ptr)
2713 * @param val Change the values of lpf2_xl_en in reg CTRL1_XL
2714 * @retval Interface status (MANDATORY: return 0 -> no Error).
2715 *
2716 */
ism330dhcx_xl_filter_lp2_get(const stmdev_ctx_t * ctx,uint8_t * val)2717 int32_t ism330dhcx_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val)
2718 {
2719 ism330dhcx_ctrl1_xl_t ctrl1_xl;
2720 int32_t ret;
2721
2722 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL1_XL,
2723 (uint8_t *)&ctrl1_xl, 1);
2724 *val = ctrl1_xl.lpf2_xl_en;
2725
2726 return ret;
2727 }
2728
2729 /**
2730 * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
2731 * the bandwidth can be selected through FTYPE [2:0] in CTRL6_C.[set]
2732 *
2733 * @param ctx Read / write interface definitions.(ptr)
2734 * @param val Change the values of lpf1_sel_g in reg CTRL4_C
2735 * @retval Interface status (MANDATORY: return 0 -> no Error).
2736 *
2737 */
ism330dhcx_gy_filter_lp1_set(const stmdev_ctx_t * ctx,uint8_t val)2738 int32_t ism330dhcx_gy_filter_lp1_set(const stmdev_ctx_t *ctx, uint8_t val)
2739 {
2740 ism330dhcx_ctrl4_c_t ctrl4_c;
2741 int32_t ret;
2742
2743 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL4_C,
2744 (uint8_t *)&ctrl4_c, 1);
2745
2746 if (ret == 0)
2747 {
2748 ctrl4_c.lpf1_sel_g = (uint8_t)val;
2749 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL4_C,
2750 (uint8_t *)&ctrl4_c, 1);
2751 }
2752
2753 return ret;
2754 }
2755
2756 /**
2757 * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
2758 * the bandwidth can be selected through FTYPE [2:0] in CTRL6_C.[get]
2759 *
2760 * @param ctx Read / write interface definitions.(ptr)
2761 * @param val Change the values of lpf1_sel_g in reg CTRL4_C
2762 * @retval Interface status (MANDATORY: return 0 -> no Error).
2763 *
2764 */
ism330dhcx_gy_filter_lp1_get(const stmdev_ctx_t * ctx,uint8_t * val)2765 int32_t ism330dhcx_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val)
2766 {
2767 ism330dhcx_ctrl4_c_t ctrl4_c;
2768 int32_t ret;
2769
2770 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL4_C,
2771 (uint8_t *)&ctrl4_c, 1);
2772 *val = ctrl4_c.lpf1_sel_g;
2773
2774 return ret;
2775 }
2776
2777 /**
2778 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
2779 * (XL and Gyro independently masked).[set]
2780 *
2781 * @param ctx Read / write interface definitions.(ptr)
2782 * @param val Change the values of drdy_mask in reg CTRL4_C
2783 * @retval Interface status (MANDATORY: return 0 -> no Error).
2784 *
2785 */
ism330dhcx_filter_settling_mask_set(const stmdev_ctx_t * ctx,uint8_t val)2786 int32_t ism330dhcx_filter_settling_mask_set(const stmdev_ctx_t *ctx,
2787 uint8_t val)
2788 {
2789 ism330dhcx_ctrl4_c_t ctrl4_c;
2790 int32_t ret;
2791
2792 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL4_C,
2793 (uint8_t *)&ctrl4_c, 1);
2794
2795 if (ret == 0)
2796 {
2797 ctrl4_c.drdy_mask = (uint8_t)val;
2798 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL4_C,
2799 (uint8_t *)&ctrl4_c, 1);
2800 }
2801
2802 return ret;
2803 }
2804
2805 /**
2806 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
2807 * (XL and Gyro independently masked).[get]
2808 *
2809 * @param ctx Read / write interface definitions.(ptr)
2810 * @param val Change the values of drdy_mask in reg CTRL4_C
2811 * @retval Interface status (MANDATORY: return 0 -> no Error).
2812 *
2813 */
ism330dhcx_filter_settling_mask_get(const stmdev_ctx_t * ctx,uint8_t * val)2814 int32_t ism330dhcx_filter_settling_mask_get(const stmdev_ctx_t *ctx,
2815 uint8_t *val)
2816 {
2817 ism330dhcx_ctrl4_c_t ctrl4_c;
2818 int32_t ret;
2819
2820 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL4_C,
2821 (uint8_t *)&ctrl4_c, 1);
2822 *val = ctrl4_c.drdy_mask;
2823
2824 return ret;
2825 }
2826
2827 /**
2828 * @brief Gyroscope low pass filter 1 bandwidth.[set]
2829 *
2830 * @param ctx Read / write interface definitions.(ptr)
2831 * @param val Change the values of ftype in reg CTRL6_C
2832 * @retval Interface status (MANDATORY: return 0 -> no Error).
2833 *
2834 */
ism330dhcx_gy_lp1_bandwidth_set(const stmdev_ctx_t * ctx,ism330dhcx_ftype_t val)2835 int32_t ism330dhcx_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx,
2836 ism330dhcx_ftype_t val)
2837 {
2838 ism330dhcx_ctrl6_c_t ctrl6_c;
2839 int32_t ret;
2840
2841 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL6_C,
2842 (uint8_t *)&ctrl6_c, 1);
2843
2844 if (ret == 0)
2845 {
2846 ctrl6_c.ftype = (uint8_t)val;
2847 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL6_C,
2848 (uint8_t *)&ctrl6_c, 1);
2849 }
2850
2851 return ret;
2852 }
2853
2854 /**
2855 * @brief Gyroscope low pass filter 1 bandwidth.[get]
2856 *
2857 * @param ctx Read / write interface definitions.(ptr)
2858 * @param val Get the values of ftype in reg CTRL6_C
2859 * @retval Interface status (MANDATORY: return 0 -> no Error).
2860 *
2861 */
ism330dhcx_gy_lp1_bandwidth_get(const stmdev_ctx_t * ctx,ism330dhcx_ftype_t * val)2862 int32_t ism330dhcx_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx,
2863 ism330dhcx_ftype_t *val)
2864 {
2865 ism330dhcx_ctrl6_c_t ctrl6_c;
2866 int32_t ret;
2867
2868 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL6_C,
2869 (uint8_t *)&ctrl6_c, 1);
2870
2871 switch (ctrl6_c.ftype)
2872 {
2873 case ISM330DHCX_ULTRA_LIGHT:
2874 *val = ISM330DHCX_ULTRA_LIGHT;
2875 break;
2876
2877 case ISM330DHCX_VERY_LIGHT:
2878 *val = ISM330DHCX_VERY_LIGHT;
2879 break;
2880
2881 case ISM330DHCX_LIGHT:
2882 *val = ISM330DHCX_LIGHT;
2883 break;
2884
2885 case ISM330DHCX_MEDIUM:
2886 *val = ISM330DHCX_MEDIUM;
2887 break;
2888
2889 case ISM330DHCX_STRONG:
2890 *val = ISM330DHCX_STRONG;
2891 break;
2892
2893 case ISM330DHCX_VERY_STRONG:
2894 *val = ISM330DHCX_VERY_STRONG;
2895 break;
2896
2897 case ISM330DHCX_AGGRESSIVE:
2898 *val = ISM330DHCX_AGGRESSIVE;
2899 break;
2900
2901 case ISM330DHCX_XTREME:
2902 *val = ISM330DHCX_XTREME;
2903 break;
2904
2905 default:
2906 *val = ISM330DHCX_ULTRA_LIGHT;
2907 break;
2908 }
2909
2910 return ret;
2911 }
2912
2913 /**
2914 * @brief Low pass filter 2 on 6D function selection.[set]
2915 *
2916 * @param ctx Read / write interface definitions.(ptr)
2917 * @param val Change the values of low_pass_on_6d in reg CTRL8_XL
2918 * @retval Interface status (MANDATORY: return 0 -> no Error).
2919 *
2920 */
ism330dhcx_xl_lp2_on_6d_set(const stmdev_ctx_t * ctx,uint8_t val)2921 int32_t ism330dhcx_xl_lp2_on_6d_set(const stmdev_ctx_t *ctx, uint8_t val)
2922 {
2923 ism330dhcx_ctrl8_xl_t ctrl8_xl;
2924 int32_t ret;
2925
2926 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL8_XL,
2927 (uint8_t *)&ctrl8_xl, 1);
2928
2929 if (ret == 0)
2930 {
2931 ctrl8_xl.low_pass_on_6d = (uint8_t)val;
2932 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL8_XL,
2933 (uint8_t *)&ctrl8_xl, 1);
2934 }
2935
2936 return ret;
2937 }
2938
2939 /**
2940 * @brief Low pass filter 2 on 6D function selection.[get]
2941 *
2942 * @param ctx Read / write interface definitions.(ptr)
2943 * @param val Change the values of low_pass_on_6d in reg CTRL8_XL
2944 * @retval Interface status (MANDATORY: return 0 -> no Error).
2945 *
2946 */
ism330dhcx_xl_lp2_on_6d_get(const stmdev_ctx_t * ctx,uint8_t * val)2947 int32_t ism330dhcx_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val)
2948 {
2949 ism330dhcx_ctrl8_xl_t ctrl8_xl;
2950 int32_t ret;
2951
2952 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL8_XL,
2953 (uint8_t *)&ctrl8_xl, 1);
2954 *val = ctrl8_xl.low_pass_on_6d;
2955
2956 return ret;
2957 }
2958
2959 /**
2960 * @brief Accelerometer slope filter / high-pass filter selection
2961 * on output.[set]
2962 *
2963 * @param ctx Read / write interface definitions.(ptr)
2964 * @param val Change the values of hp_slope_xl_en in reg CTRL8_XL
2965 * @retval Interface status (MANDATORY: return 0 -> no Error).
2966 *
2967 */
ism330dhcx_xl_hp_path_on_out_set(const stmdev_ctx_t * ctx,ism330dhcx_hp_slope_xl_en_t val)2968 int32_t ism330dhcx_xl_hp_path_on_out_set(const stmdev_ctx_t *ctx,
2969 ism330dhcx_hp_slope_xl_en_t val)
2970 {
2971 ism330dhcx_ctrl8_xl_t ctrl8_xl;
2972 int32_t ret;
2973
2974 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL8_XL,
2975 (uint8_t *)&ctrl8_xl, 1);
2976
2977 if (ret == 0)
2978 {
2979 ctrl8_xl.hp_slope_xl_en = (((uint8_t)val & 0x10U) >> 4);
2980 ctrl8_xl.hp_ref_mode_xl = (((uint8_t)val & 0x20U) >> 5);
2981 ctrl8_xl.hpcf_xl = (uint8_t)val & 0x07U;
2982 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL8_XL,
2983 (uint8_t *)&ctrl8_xl, 1);
2984 }
2985
2986 return ret;
2987 }
2988
2989 /**
2990 * @brief Accelerometer slope filter / high-pass filter selection on
2991 * output.[get]
2992 *
2993 * @param ctx Read / write interface definitions.(ptr)
2994 * @param val Get the values of hp_slope_xl_en in reg CTRL8_XL
2995 * @retval Interface status (MANDATORY: return 0 -> no Error).
2996 *
2997 */
ism330dhcx_xl_hp_path_on_out_get(const stmdev_ctx_t * ctx,ism330dhcx_hp_slope_xl_en_t * val)2998 int32_t ism330dhcx_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx,
2999 ism330dhcx_hp_slope_xl_en_t *val)
3000 {
3001 ism330dhcx_ctrl8_xl_t ctrl8_xl;
3002 int32_t ret;
3003
3004 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL8_XL,
3005 (uint8_t *)&ctrl8_xl, 1);
3006
3007 switch (((ctrl8_xl.hp_ref_mode_xl << 5) + (ctrl8_xl.hp_slope_xl_en <<
3008 4) +
3009 ctrl8_xl.hpcf_xl))
3010 {
3011 case ISM330DHCX_HP_PATH_DISABLE_ON_OUT:
3012 *val = ISM330DHCX_HP_PATH_DISABLE_ON_OUT;
3013 break;
3014
3015 case ISM330DHCX_SLOPE_ODR_DIV_4:
3016 *val = ISM330DHCX_SLOPE_ODR_DIV_4;
3017 break;
3018
3019 case ISM330DHCX_HP_ODR_DIV_10:
3020 *val = ISM330DHCX_HP_ODR_DIV_10;
3021 break;
3022
3023 case ISM330DHCX_HP_ODR_DIV_20:
3024 *val = ISM330DHCX_HP_ODR_DIV_20;
3025 break;
3026
3027 case ISM330DHCX_HP_ODR_DIV_45:
3028 *val = ISM330DHCX_HP_ODR_DIV_45;
3029 break;
3030
3031 case ISM330DHCX_HP_ODR_DIV_100:
3032 *val = ISM330DHCX_HP_ODR_DIV_100;
3033 break;
3034
3035 case ISM330DHCX_HP_ODR_DIV_200:
3036 *val = ISM330DHCX_HP_ODR_DIV_200;
3037 break;
3038
3039 case ISM330DHCX_HP_ODR_DIV_400:
3040 *val = ISM330DHCX_HP_ODR_DIV_400;
3041 break;
3042
3043 case ISM330DHCX_HP_ODR_DIV_800:
3044 *val = ISM330DHCX_HP_ODR_DIV_800;
3045 break;
3046
3047 case ISM330DHCX_HP_REF_MD_ODR_DIV_10:
3048 *val = ISM330DHCX_HP_REF_MD_ODR_DIV_10;
3049 break;
3050
3051 case ISM330DHCX_HP_REF_MD_ODR_DIV_20:
3052 *val = ISM330DHCX_HP_REF_MD_ODR_DIV_20;
3053 break;
3054
3055 case ISM330DHCX_HP_REF_MD_ODR_DIV_45:
3056 *val = ISM330DHCX_HP_REF_MD_ODR_DIV_45;
3057 break;
3058
3059 case ISM330DHCX_HP_REF_MD_ODR_DIV_100:
3060 *val = ISM330DHCX_HP_REF_MD_ODR_DIV_100;
3061 break;
3062
3063 case ISM330DHCX_HP_REF_MD_ODR_DIV_200:
3064 *val = ISM330DHCX_HP_REF_MD_ODR_DIV_200;
3065 break;
3066
3067 case ISM330DHCX_HP_REF_MD_ODR_DIV_400:
3068 *val = ISM330DHCX_HP_REF_MD_ODR_DIV_400;
3069 break;
3070
3071 case ISM330DHCX_HP_REF_MD_ODR_DIV_800:
3072 *val = ISM330DHCX_HP_REF_MD_ODR_DIV_800;
3073 break;
3074
3075 case ISM330DHCX_LP_ODR_DIV_10:
3076 *val = ISM330DHCX_LP_ODR_DIV_10;
3077 break;
3078
3079 case ISM330DHCX_LP_ODR_DIV_20:
3080 *val = ISM330DHCX_LP_ODR_DIV_20;
3081 break;
3082
3083 case ISM330DHCX_LP_ODR_DIV_45:
3084 *val = ISM330DHCX_LP_ODR_DIV_45;
3085 break;
3086
3087 case ISM330DHCX_LP_ODR_DIV_100:
3088 *val = ISM330DHCX_LP_ODR_DIV_100;
3089 break;
3090
3091 case ISM330DHCX_LP_ODR_DIV_200:
3092 *val = ISM330DHCX_LP_ODR_DIV_200;
3093 break;
3094
3095 case ISM330DHCX_LP_ODR_DIV_400:
3096 *val = ISM330DHCX_LP_ODR_DIV_400;
3097 break;
3098
3099 case ISM330DHCX_LP_ODR_DIV_800:
3100 *val = ISM330DHCX_LP_ODR_DIV_800;
3101 break;
3102
3103 default:
3104 *val = ISM330DHCX_HP_PATH_DISABLE_ON_OUT;
3105 break;
3106 }
3107
3108 return ret;
3109 }
3110
3111 /**
3112 * @brief Enables accelerometer LPF2 and HPF fast-settling mode.
3113 * The filter sets the second samples after writing this bit.
3114 * Active only during device exit from powerdown mode.[set]
3115 *
3116 * @param ctx Read / write interface definitions.(ptr)
3117 * @param val Change the values of fastsettl_mode_xl in reg CTRL8_XL
3118 * @retval Interface status (MANDATORY: return 0 -> no Error).
3119 *
3120 */
ism330dhcx_xl_fast_settling_set(const stmdev_ctx_t * ctx,uint8_t val)3121 int32_t ism330dhcx_xl_fast_settling_set(const stmdev_ctx_t *ctx,
3122 uint8_t val)
3123 {
3124 ism330dhcx_ctrl8_xl_t ctrl8_xl;
3125 int32_t ret;
3126
3127 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL8_XL,
3128 (uint8_t *)&ctrl8_xl, 1);
3129
3130 if (ret == 0)
3131 {
3132 ctrl8_xl.fastsettl_mode_xl = (uint8_t)val;
3133 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL8_XL,
3134 (uint8_t *)&ctrl8_xl, 1);
3135 }
3136
3137 return ret;
3138 }
3139
3140 /**
3141 * @brief Enables accelerometer LPF2 and HPF fast-settling mode.
3142 * The filter sets the second samples after writing
3143 * this bit. Active only during device exit from powerdown mode.[get]
3144 *
3145 * @param ctx Read / write interface definitions.(ptr)
3146 * @param val Change the values of fastsettl_mode_xl in reg CTRL8_XL
3147 * @retval Interface status (MANDATORY: return 0 -> no Error).
3148 *
3149 */
ism330dhcx_xl_fast_settling_get(const stmdev_ctx_t * ctx,uint8_t * val)3150 int32_t ism330dhcx_xl_fast_settling_get(const stmdev_ctx_t *ctx,
3151 uint8_t *val)
3152 {
3153 ism330dhcx_ctrl8_xl_t ctrl8_xl;
3154 int32_t ret;
3155
3156 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL8_XL,
3157 (uint8_t *)&ctrl8_xl, 1);
3158 *val = ctrl8_xl.fastsettl_mode_xl;
3159
3160 return ret;
3161 }
3162
3163 /**
3164 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
3165 * functions.[set]
3166 *
3167 * @param ctx Read / write interface definitions.(ptr)
3168 * @param val Change the values of slope_fds in reg TAP_CFG0
3169 * @retval Interface status (MANDATORY: return 0 -> no Error).
3170 *
3171 */
ism330dhcx_xl_hp_path_internal_set(const stmdev_ctx_t * ctx,ism330dhcx_slope_fds_t val)3172 int32_t ism330dhcx_xl_hp_path_internal_set(const stmdev_ctx_t *ctx,
3173 ism330dhcx_slope_fds_t val)
3174 {
3175 ism330dhcx_tap_cfg0_t tap_cfg0;
3176 int32_t ret;
3177
3178 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG0,
3179 (uint8_t *)&tap_cfg0, 1);
3180
3181 if (ret == 0)
3182 {
3183 tap_cfg0.slope_fds = (uint8_t)val;
3184 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_TAP_CFG0,
3185 (uint8_t *)&tap_cfg0, 1);
3186 }
3187
3188 return ret;
3189 }
3190
3191 /**
3192 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
3193 * functions.[get]
3194 *
3195 * @param ctx Read / write interface definitions.(ptr)
3196 * @param val Get the values of slope_fds in reg TAP_CFG0
3197 * @retval Interface status (MANDATORY: return 0 -> no Error).
3198 *
3199 */
ism330dhcx_xl_hp_path_internal_get(const stmdev_ctx_t * ctx,ism330dhcx_slope_fds_t * val)3200 int32_t ism330dhcx_xl_hp_path_internal_get(const stmdev_ctx_t *ctx,
3201 ism330dhcx_slope_fds_t *val)
3202 {
3203 ism330dhcx_tap_cfg0_t tap_cfg0;
3204 int32_t ret;
3205
3206 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG0,
3207 (uint8_t *)&tap_cfg0, 1);
3208
3209 switch (tap_cfg0.slope_fds)
3210 {
3211 case ISM330DHCX_USE_SLOPE:
3212 *val = ISM330DHCX_USE_SLOPE;
3213 break;
3214
3215 case ISM330DHCX_USE_HPF:
3216 *val = ISM330DHCX_USE_HPF;
3217 break;
3218
3219 default:
3220 *val = ISM330DHCX_USE_SLOPE;
3221 break;
3222 }
3223
3224 return ret;
3225 }
3226
3227 /**
3228 * @brief Enables gyroscope digital high-pass filter. The filter is enabled
3229 * only if the gyro is in HP mode.[set]
3230 *
3231 * @param ctx Read / write interface definitions.(ptr)
3232 * @param val Get the values of hp_en_g and hp_en_g in reg CTRL7_G
3233 * @retval Interface status (MANDATORY: return 0 -> no Error).
3234 *
3235 */
ism330dhcx_gy_hp_path_internal_set(const stmdev_ctx_t * ctx,ism330dhcx_hpm_g_t val)3236 int32_t ism330dhcx_gy_hp_path_internal_set(const stmdev_ctx_t *ctx,
3237 ism330dhcx_hpm_g_t val)
3238 {
3239 ism330dhcx_ctrl7_g_t ctrl7_g;
3240 int32_t ret;
3241
3242 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL7_G,
3243 (uint8_t *)&ctrl7_g, 1);
3244
3245 if (ret == 0)
3246 {
3247 ctrl7_g.hp_en_g = (((uint8_t)val & 0x80U) >> 7);
3248 ctrl7_g.hpm_g = (uint8_t)val & 0x03U;
3249 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL7_G,
3250 (uint8_t *)&ctrl7_g, 1);
3251 }
3252
3253 return ret;
3254 }
3255
3256 /**
3257 * @brief Enables gyroscope digital high-pass filter. The filter is
3258 * enabled only if the gyro is in HP mode.[get]
3259 *
3260 * @param ctx Read / write interface definitions.(ptr)
3261 * @param val Get the values of hp_en_g and hp_en_g in reg CTRL7_G
3262 * @retval Interface status (MANDATORY: return 0 -> no Error).
3263 *
3264 */
ism330dhcx_gy_hp_path_internal_get(const stmdev_ctx_t * ctx,ism330dhcx_hpm_g_t * val)3265 int32_t ism330dhcx_gy_hp_path_internal_get(const stmdev_ctx_t *ctx,
3266 ism330dhcx_hpm_g_t *val)
3267 {
3268 ism330dhcx_ctrl7_g_t ctrl7_g;
3269 int32_t ret;
3270
3271 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL7_G,
3272 (uint8_t *)&ctrl7_g, 1);
3273
3274 switch ((ctrl7_g.hp_en_g << 7) + ctrl7_g.hpm_g)
3275 {
3276 case ISM330DHCX_HP_FILTER_NONE:
3277 *val = ISM330DHCX_HP_FILTER_NONE;
3278 break;
3279
3280 case ISM330DHCX_HP_FILTER_16mHz:
3281 *val = ISM330DHCX_HP_FILTER_16mHz;
3282 break;
3283
3284 case ISM330DHCX_HP_FILTER_65mHz:
3285 *val = ISM330DHCX_HP_FILTER_65mHz;
3286 break;
3287
3288 case ISM330DHCX_HP_FILTER_260mHz:
3289 *val = ISM330DHCX_HP_FILTER_260mHz;
3290 break;
3291
3292 case ISM330DHCX_HP_FILTER_1Hz04:
3293 *val = ISM330DHCX_HP_FILTER_1Hz04;
3294 break;
3295
3296 default:
3297 *val = ISM330DHCX_HP_FILTER_NONE;
3298 break;
3299 }
3300
3301 return ret;
3302 }
3303
3304 /**
3305 * @}
3306 *
3307 */
3308
3309 /**
3310 * @defgroup ISM330DHCX_ Auxiliary_interface
3311 * @brief This section groups all the functions concerning
3312 * auxiliary interface.
3313 * @{
3314 *
3315 */
3316
3317 /**
3318 * @brief On auxiliary interface connect/disconnect SDO and OCS
3319 * internal pull-up.[set]
3320 *
3321 * @param ctx Read / write interface definitions.(ptr)
3322 * @param val Change the values of ois_pu_dis in reg PIN_CTRL
3323 * @retval Interface status (MANDATORY: return 0 -> no Error).
3324 *
3325 */
ism330dhcx_aux_sdo_ocs_mode_set(const stmdev_ctx_t * ctx,ism330dhcx_ois_pu_dis_t val)3326 int32_t ism330dhcx_aux_sdo_ocs_mode_set(const stmdev_ctx_t *ctx,
3327 ism330dhcx_ois_pu_dis_t val)
3328 {
3329 ism330dhcx_pin_ctrl_t pin_ctrl;
3330 int32_t ret;
3331
3332 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PIN_CTRL,
3333 (uint8_t *)&pin_ctrl, 1);
3334
3335 if (ret == 0)
3336 {
3337 pin_ctrl.ois_pu_dis = (uint8_t)val;
3338 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PIN_CTRL,
3339 (uint8_t *)&pin_ctrl, 1);
3340 }
3341
3342 return ret;
3343 }
3344
3345 /**
3346 * @brief On auxiliary interface connect/disconnect SDO and OCS
3347 * internal pull-up.[get]
3348 *
3349 * @param ctx Read / write interface definitions.(ptr)
3350 * @param val Get the values of ois_pu_dis in reg PIN_CTRL
3351 * @retval Interface status (MANDATORY: return 0 -> no Error).
3352 *
3353 */
ism330dhcx_aux_sdo_ocs_mode_get(const stmdev_ctx_t * ctx,ism330dhcx_ois_pu_dis_t * val)3354 int32_t ism330dhcx_aux_sdo_ocs_mode_get(const stmdev_ctx_t *ctx,
3355 ism330dhcx_ois_pu_dis_t *val)
3356 {
3357 ism330dhcx_pin_ctrl_t pin_ctrl;
3358 int32_t ret;
3359
3360 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PIN_CTRL,
3361 (uint8_t *)&pin_ctrl, 1);
3362
3363 switch (pin_ctrl.ois_pu_dis)
3364 {
3365 case ISM330DHCX_AUX_PULL_UP_DISC:
3366 *val = ISM330DHCX_AUX_PULL_UP_DISC;
3367 break;
3368
3369 case ISM330DHCX_AUX_PULL_UP_CONNECT:
3370 *val = ISM330DHCX_AUX_PULL_UP_CONNECT;
3371 break;
3372
3373 default:
3374 *val = ISM330DHCX_AUX_PULL_UP_DISC;
3375 break;
3376 }
3377
3378 return ret;
3379 }
3380
3381 /**
3382 * @brief OIS chain on aux interface power on mode.[set]
3383 *
3384 * @param ctx Read / write interface definitions.(ptr)
3385 * @param val Change the values of ois_on in reg CTRL7_G
3386 * @retval Interface status (MANDATORY: return 0 -> no Error).
3387 *
3388 */
ism330dhcx_aux_pw_on_ctrl_set(const stmdev_ctx_t * ctx,ism330dhcx_ois_on_t val)3389 int32_t ism330dhcx_aux_pw_on_ctrl_set(const stmdev_ctx_t *ctx,
3390 ism330dhcx_ois_on_t val)
3391 {
3392 ism330dhcx_ctrl7_g_t ctrl7_g;
3393 int32_t ret;
3394
3395 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL7_G,
3396 (uint8_t *)&ctrl7_g, 1);
3397
3398 if (ret == 0)
3399 {
3400 ctrl7_g.ois_on_en = (uint8_t)val & 0x01U;
3401 ctrl7_g.ois_on = (uint8_t)val & 0x01U;
3402 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL7_G,
3403 (uint8_t *)&ctrl7_g, 1);
3404 }
3405
3406 return ret;
3407 }
3408
3409 /**
3410 * @brief OIS chain on aux interface power on mode[get]
3411 *
3412 * @param ctx Read / write interface definitions.(ptr)
3413 * @param val Get the values of ois_on in reg CTRL7_G
3414 * @retval Interface status (MANDATORY: return 0 -> no Error).
3415 *
3416 */
ism330dhcx_aux_pw_on_ctrl_get(const stmdev_ctx_t * ctx,ism330dhcx_ois_on_t * val)3417 int32_t ism330dhcx_aux_pw_on_ctrl_get(const stmdev_ctx_t *ctx,
3418 ism330dhcx_ois_on_t *val)
3419 {
3420 ism330dhcx_ctrl7_g_t ctrl7_g;
3421 int32_t ret;
3422
3423 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL7_G,
3424 (uint8_t *)&ctrl7_g, 1);
3425
3426 switch (ctrl7_g.ois_on)
3427 {
3428 case ISM330DHCX_AUX_ON:
3429 *val = ISM330DHCX_AUX_ON;
3430 break;
3431
3432 case ISM330DHCX_AUX_ON_BY_AUX_INTERFACE:
3433 *val = ISM330DHCX_AUX_ON_BY_AUX_INTERFACE;
3434 break;
3435
3436 default:
3437 *val = ISM330DHCX_AUX_ON;
3438 break;
3439 }
3440
3441 return ret;
3442 }
3443
3444 /**
3445 * @brief The STATUS_SPIAux register is read by the auxiliary SPI.[get]
3446 *
3447 * @param ctx Read / write interface definitions.(ptr)
3448 * @param ism330dhcx_status_spiaux_t: registers STATUS_SPIAUX
3449 * @retval Interface status (MANDATORY: return 0 -> no Error).
3450 *
3451 */
ism330dhcx_aux_status_reg_get(const stmdev_ctx_t * ctx,ism330dhcx_status_spiaux_t * val)3452 int32_t ism330dhcx_aux_status_reg_get(const stmdev_ctx_t *ctx,
3453 ism330dhcx_status_spiaux_t *val)
3454 {
3455 int32_t ret;
3456
3457 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_STATUS_SPIAUX,
3458 (uint8_t *)val, 1);
3459
3460 return ret;
3461 }
3462
3463 /**
3464 * @brief AUX accelerometer data available.[get]
3465 *
3466 * @param ctx Read / write interface definitions.(ptr)
3467 * @param val Change the values of xlda in reg STATUS_SPIAUX
3468 * @retval Interface status (MANDATORY: return 0 -> no Error).
3469 *
3470 */
ism330dhcx_aux_xl_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)3471 int32_t ism330dhcx_aux_xl_flag_data_ready_get(const stmdev_ctx_t *ctx,
3472 uint8_t *val)
3473 {
3474 ism330dhcx_status_spiaux_t status_spiaux;
3475 int32_t ret;
3476
3477 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_STATUS_SPIAUX,
3478 (uint8_t *)&status_spiaux, 1);
3479 *val = status_spiaux.xlda;
3480
3481 return ret;
3482 }
3483
3484 /**
3485 * @brief AUX gyroscope data available.[get]
3486 *
3487 * @param ctx Read / write interface definitions.(ptr)
3488 * @param val Change the values of gda in reg STATUS_SPIAUX
3489 * @retval Interface status (MANDATORY: return 0 -> no Error).
3490 *
3491 */
ism330dhcx_aux_gy_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)3492 int32_t ism330dhcx_aux_gy_flag_data_ready_get(const stmdev_ctx_t *ctx,
3493 uint8_t *val)
3494 {
3495 ism330dhcx_status_spiaux_t status_spiaux;
3496 int32_t ret;
3497
3498 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_STATUS_SPIAUX,
3499 (uint8_t *)&status_spiaux, 1);
3500 *val = status_spiaux.gda;
3501
3502 return ret;
3503 }
3504
3505 /**
3506 * @brief High when the gyroscope output is in the settling phase.[get]
3507 *
3508 * @param ctx Read / write interface definitions.(ptr)
3509 * @param val Change the values of gyro_settling in reg STATUS_SPIAUX
3510 * @retval Interface status (MANDATORY: return 0 -> no Error).
3511 *
3512 */
ism330dhcx_aux_gy_flag_settling_get(const stmdev_ctx_t * ctx,uint8_t * val)3513 int32_t ism330dhcx_aux_gy_flag_settling_get(const stmdev_ctx_t *ctx,
3514 uint8_t *val)
3515 {
3516 ism330dhcx_status_spiaux_t status_spiaux;
3517 int32_t ret;
3518
3519 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_STATUS_SPIAUX,
3520 (uint8_t *)&status_spiaux, 1);
3521 *val = status_spiaux.gyro_settling;
3522
3523 return ret;
3524 }
3525
3526 /**
3527 * @brief Selects accelerometer self-test. Effective only if XL OIS chain is
3528 * enabled.[set]
3529 *
3530 * @param ctx Read / write interface definitions.(ptr)
3531 * @param val Change the values of st_xl_ois in reg INT_OIS
3532 * @retval Interface status (MANDATORY: return 0 -> no Error).
3533 *
3534 */
ism330dhcx_aux_xl_self_test_set(const stmdev_ctx_t * ctx,ism330dhcx_st_xl_ois_t val)3535 int32_t ism330dhcx_aux_xl_self_test_set(const stmdev_ctx_t *ctx,
3536 ism330dhcx_st_xl_ois_t val)
3537 {
3538 ism330dhcx_int_ois_t int_ois;
3539 int32_t ret;
3540
3541 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_OIS,
3542 (uint8_t *)&int_ois, 1);
3543
3544 if (ret == 0)
3545 {
3546 int_ois.st_xl_ois = (uint8_t)val;
3547 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_INT_OIS,
3548 (uint8_t *)&int_ois, 1);
3549 }
3550
3551 return ret;
3552 }
3553
3554 /**
3555 * @brief Selects accelerometer self-test. Effective only if XL OIS chain
3556 * is enabled.[get]
3557 *
3558 * @param ctx Read / write interface definitions.(ptr)
3559 * @param val Get the values of st_xl_ois in reg INT_OIS
3560 * @retval Interface status (MANDATORY: return 0 -> no Error).
3561 *
3562 */
ism330dhcx_aux_xl_self_test_get(const stmdev_ctx_t * ctx,ism330dhcx_st_xl_ois_t * val)3563 int32_t ism330dhcx_aux_xl_self_test_get(const stmdev_ctx_t *ctx,
3564 ism330dhcx_st_xl_ois_t *val)
3565 {
3566 ism330dhcx_int_ois_t int_ois;
3567 int32_t ret;
3568
3569 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_OIS,
3570 (uint8_t *)&int_ois, 1);
3571
3572 switch (int_ois.st_xl_ois)
3573 {
3574 case ISM330DHCX_AUX_XL_DISABLE:
3575 *val = ISM330DHCX_AUX_XL_DISABLE;
3576 break;
3577
3578 case ISM330DHCX_AUX_XL_POS:
3579 *val = ISM330DHCX_AUX_XL_POS;
3580 break;
3581
3582 case ISM330DHCX_AUX_XL_NEG:
3583 *val = ISM330DHCX_AUX_XL_NEG;
3584 break;
3585
3586 default:
3587 *val = ISM330DHCX_AUX_XL_DISABLE;
3588 break;
3589 }
3590
3591 return ret;
3592 }
3593
3594 /**
3595 * @brief Indicates polarity of DEN signal on OIS chain.[set]
3596 *
3597 * @param ctx Read / write interface definitions.(ptr)
3598 * @param val Change the values of den_lh_ois in reg INT_OIS
3599 * @retval Interface status (MANDATORY: return 0 -> no Error).
3600 *
3601 */
ism330dhcx_aux_den_polarity_set(const stmdev_ctx_t * ctx,ism330dhcx_den_lh_ois_t val)3602 int32_t ism330dhcx_aux_den_polarity_set(const stmdev_ctx_t *ctx,
3603 ism330dhcx_den_lh_ois_t val)
3604 {
3605 ism330dhcx_int_ois_t int_ois;
3606 int32_t ret;
3607
3608 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_OIS,
3609 (uint8_t *)&int_ois, 1);
3610
3611 if (ret == 0)
3612 {
3613 int_ois.den_lh_ois = (uint8_t)val;
3614 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_INT_OIS,
3615 (uint8_t *)&int_ois, 1);
3616 }
3617
3618 return ret;
3619 }
3620
3621 /**
3622 * @brief Indicates polarity of DEN signal on OIS chain.[get]
3623 *
3624 * @param ctx Read / write interface definitions.(ptr)
3625 * @param val Get the values of den_lh_ois in reg INT_OIS
3626 * @retval Interface status (MANDATORY: return 0 -> no Error).
3627 *
3628 */
ism330dhcx_aux_den_polarity_get(const stmdev_ctx_t * ctx,ism330dhcx_den_lh_ois_t * val)3629 int32_t ism330dhcx_aux_den_polarity_get(const stmdev_ctx_t *ctx,
3630 ism330dhcx_den_lh_ois_t *val)
3631 {
3632 ism330dhcx_int_ois_t int_ois;
3633 int32_t ret;
3634
3635 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_OIS,
3636 (uint8_t *)&int_ois, 1);
3637
3638 switch (int_ois.den_lh_ois)
3639 {
3640 case ISM330DHCX_AUX_DEN_ACTIVE_LOW:
3641 *val = ISM330DHCX_AUX_DEN_ACTIVE_LOW;
3642 break;
3643
3644 case ISM330DHCX_AUX_DEN_ACTIVE_HIGH:
3645 *val = ISM330DHCX_AUX_DEN_ACTIVE_HIGH;
3646 break;
3647
3648 default:
3649 *val = ISM330DHCX_AUX_DEN_ACTIVE_LOW;
3650 break;
3651 }
3652
3653 return ret;
3654 }
3655
3656 /**
3657 * @brief Configure DEN mode on the OIS chain.[set]
3658 *
3659 * @param ctx Read / write interface definitions.(ptr)
3660 * @param val Change the values of lvl2_ois in reg INT_OIS
3661 * @retval Interface status (MANDATORY: return 0 -> no Error).
3662 *
3663 */
ism330dhcx_aux_den_mode_set(const stmdev_ctx_t * ctx,ism330dhcx_lvl2_ois_t val)3664 int32_t ism330dhcx_aux_den_mode_set(const stmdev_ctx_t *ctx,
3665 ism330dhcx_lvl2_ois_t val)
3666 {
3667 ism330dhcx_int_ois_t int_ois;
3668 ism330dhcx_ctrl1_ois_t ctrl1_ois;
3669 int32_t ret;
3670
3671 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_OIS,
3672 (uint8_t *)&int_ois, 1);
3673
3674 if (ret == 0)
3675 {
3676 int_ois.lvl2_ois = (uint8_t)val & 0x01U;
3677 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_INT_OIS,
3678 (uint8_t *)&int_ois, 1);
3679 }
3680
3681 if (ret == 0)
3682 {
3683 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL1_OIS,
3684 (uint8_t *)&ctrl1_ois, 1);
3685 }
3686
3687 if (ret == 0)
3688 {
3689 ctrl1_ois.lvl1_ois = ((uint8_t)val & 0x02U) >> 1;
3690 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL1_OIS,
3691 (uint8_t *)&ctrl1_ois, 1);
3692 }
3693
3694 return ret;
3695 }
3696
3697 /**
3698 * @brief Configure DEN mode on the OIS chain.[get]
3699 *
3700 * @param ctx Read / write interface definitions.(ptr)
3701 * @param val Get the values of lvl2_ois in reg INT_OIS
3702 * @retval Interface status (MANDATORY: return 0 -> no Error).
3703 *
3704 */
ism330dhcx_aux_den_mode_get(const stmdev_ctx_t * ctx,ism330dhcx_lvl2_ois_t * val)3705 int32_t ism330dhcx_aux_den_mode_get(const stmdev_ctx_t *ctx,
3706 ism330dhcx_lvl2_ois_t *val)
3707 {
3708 ism330dhcx_int_ois_t int_ois;
3709 ism330dhcx_ctrl1_ois_t ctrl1_ois;
3710 int32_t ret;
3711
3712 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_OIS,
3713 (uint8_t *)&int_ois, 1);
3714
3715 if (ret == 0)
3716 {
3717 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL1_OIS,
3718 (uint8_t *)&ctrl1_ois, 1);
3719 }
3720
3721 switch ((ctrl1_ois.lvl1_ois << 1) + int_ois.lvl2_ois)
3722 {
3723 case ISM330DHCX_AUX_DEN_DISABLE:
3724 *val = ISM330DHCX_AUX_DEN_DISABLE;
3725 break;
3726
3727 case ISM330DHCX_AUX_DEN_LEVEL_LATCH:
3728 *val = ISM330DHCX_AUX_DEN_LEVEL_LATCH;
3729 break;
3730
3731 case ISM330DHCX_AUX_DEN_LEVEL_TRIG:
3732 *val = ISM330DHCX_AUX_DEN_LEVEL_TRIG;
3733 break;
3734
3735 default:
3736 *val = ISM330DHCX_AUX_DEN_DISABLE;
3737 break;
3738 }
3739
3740 return ret;
3741 }
3742
3743 /**
3744 * @brief Enables/Disable OIS chain DRDY on INT2 pin. This setting has
3745 * priority over all other INT2 settings.[set]
3746 *
3747 * @param ctx Read / write interface definitions.(ptr)
3748 * @param val Change the values of int2_drdy_ois in reg INT_OIS
3749 * @retval Interface status (MANDATORY: return 0 -> no Error).
3750 *
3751 */
ism330dhcx_aux_drdy_on_int2_set(const stmdev_ctx_t * ctx,uint8_t val)3752 int32_t ism330dhcx_aux_drdy_on_int2_set(const stmdev_ctx_t *ctx,
3753 uint8_t val)
3754 {
3755 ism330dhcx_int_ois_t int_ois;
3756 int32_t ret;
3757
3758 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_OIS,
3759 (uint8_t *)&int_ois, 1);
3760
3761 if (ret == 0)
3762 {
3763 int_ois.int2_drdy_ois = (uint8_t)val;
3764 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_INT_OIS,
3765 (uint8_t *)&int_ois, 1);
3766 }
3767
3768 return ret;
3769 }
3770
3771 /**
3772 * @brief Enables/Disable OIS chain DRDY on INT2 pin. This setting has
3773 * priority over all other INT2 settings.[get]
3774 *
3775 * @param ctx Read / write interface definitions.(ptr)
3776 * @param val Change the values of int2_drdy_ois in reg INT_OIS
3777 * @retval Interface status (MANDATORY: return 0 -> no Error).
3778 *
3779 */
ism330dhcx_aux_drdy_on_int2_get(const stmdev_ctx_t * ctx,uint8_t * val)3780 int32_t ism330dhcx_aux_drdy_on_int2_get(const stmdev_ctx_t *ctx,
3781 uint8_t *val)
3782 {
3783 ism330dhcx_int_ois_t int_ois;
3784 int32_t ret;
3785
3786 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_OIS,
3787 (uint8_t *)&int_ois, 1);
3788 *val = int_ois.int2_drdy_ois;
3789
3790 return ret;
3791 }
3792
3793 /**
3794 * @brief Enables OIS chain data processing for gyro in Mode 3 and Mode 4
3795 * (mode4_en = 1) and accelerometer data in and Mode 4 (mode4_en = 1).
3796 * When the OIS chain is enabled, the OIS outputs are available
3797 * through the SPI2 in registers OUTX_L_G (22h) through OUTZ_H_G(27h)
3798 * and STATUS_REG (1Eh) / STATUS_SPIAux, and LPF1 is dedicated to
3799 * this chain.[set]
3800 *
3801 * @param ctx Read / write interface definitions.(ptr)
3802 * @param val Change the values of ois_en_spi2 in reg CTRL1_OIS
3803 * @retval Interface status (MANDATORY: return 0 -> no Error).
3804 *
3805 */
ism330dhcx_aux_mode_set(const stmdev_ctx_t * ctx,ism330dhcx_ois_en_spi2_t val)3806 int32_t ism330dhcx_aux_mode_set(const stmdev_ctx_t *ctx,
3807 ism330dhcx_ois_en_spi2_t val)
3808 {
3809 ism330dhcx_ctrl1_ois_t ctrl1_ois;
3810 int32_t ret;
3811
3812 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL1_OIS,
3813 (uint8_t *)&ctrl1_ois, 1);
3814
3815 if (ret == 0)
3816 {
3817 ctrl1_ois.ois_en_spi2 = (uint8_t)val & 0x01U;
3818 ctrl1_ois.mode4_en = ((uint8_t)val & 0x02U) >> 1;
3819 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL1_OIS,
3820 (uint8_t *)&ctrl1_ois, 1);
3821 }
3822
3823 return ret;
3824 }
3825
3826 /**
3827 * @brief Enables OIS chain data processing for gyro in Mode 3 and Mode 4
3828 * (mode4_en = 1) and accelerometer data in and Mode 4 (mode4_en = 1).
3829 * When the OIS chain is enabled, the OIS outputs are available
3830 * through the SPI2 in registers OUTX_L_G (22h) through OUTZ_H_G(27h)
3831 * and STATUS_REG (1Eh) / STATUS_SPIAux, and LPF1 is dedicated to
3832 * this chain.[get]
3833 *
3834 * @param ctx Read / write interface definitions.(ptr)
3835 * @param val Get the values of ois_en_spi2 in
3836 * reg CTRL1_OIS
3837 * @retval Interface status (MANDATORY: return 0 -> no Error).
3838 *
3839 */
ism330dhcx_aux_mode_get(const stmdev_ctx_t * ctx,ism330dhcx_ois_en_spi2_t * val)3840 int32_t ism330dhcx_aux_mode_get(const stmdev_ctx_t *ctx,
3841 ism330dhcx_ois_en_spi2_t *val)
3842 {
3843 ism330dhcx_ctrl1_ois_t ctrl1_ois;
3844 int32_t ret;
3845
3846 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL1_OIS,
3847 (uint8_t *)&ctrl1_ois, 1);
3848
3849 switch (((ctrl1_ois.mode4_en << 1) + ctrl1_ois.ois_en_spi2))
3850 {
3851 case ISM330DHCX_AUX_DISABLE:
3852 *val = ISM330DHCX_AUX_DISABLE;
3853 break;
3854
3855 case ISM330DHCX_MODE_3_GY:
3856 *val = ISM330DHCX_MODE_3_GY;
3857 break;
3858
3859 case ISM330DHCX_MODE_4_GY_XL:
3860 *val = ISM330DHCX_MODE_4_GY_XL;
3861 break;
3862
3863 default:
3864 *val = ISM330DHCX_AUX_DISABLE;
3865 break;
3866 }
3867
3868 return ret;
3869 }
3870
3871 /**
3872 * @brief Selects gyroscope OIS chain full-scale.[set]
3873 *
3874 * @param ctx Read / write interface definitions.(ptr)
3875 * @param val Change the values of fs_g_ois in reg CTRL1_OIS
3876 * @retval Interface status (MANDATORY: return 0 -> no Error).
3877 *
3878 */
ism330dhcx_aux_gy_full_scale_set(const stmdev_ctx_t * ctx,ism330dhcx_fs_g_ois_t val)3879 int32_t ism330dhcx_aux_gy_full_scale_set(const stmdev_ctx_t *ctx,
3880 ism330dhcx_fs_g_ois_t val)
3881 {
3882 ism330dhcx_ctrl1_ois_t ctrl1_ois;
3883 int32_t ret;
3884
3885 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL1_OIS,
3886 (uint8_t *)&ctrl1_ois, 1);
3887
3888 if (ret == 0)
3889 {
3890 ctrl1_ois.fs_g_ois = (uint8_t)val & 0x03U;
3891 ctrl1_ois.fs_125_ois = ((uint8_t)val & 0x04U) >> 2;
3892 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL1_OIS,
3893 (uint8_t *)&ctrl1_ois, 1);
3894 }
3895
3896 return ret;
3897 }
3898
3899 /**
3900 * @brief Selects gyroscope OIS chain full-scale.[get]
3901 *
3902 * @param ctx Read / write interface definitions.(ptr)
3903 * @param val Get the values of fs_g_ois in reg CTRL1_OIS
3904 * @retval Interface status (MANDATORY: return 0 -> no Error).
3905 *
3906 */
ism330dhcx_aux_gy_full_scale_get(const stmdev_ctx_t * ctx,ism330dhcx_fs_g_ois_t * val)3907 int32_t ism330dhcx_aux_gy_full_scale_get(const stmdev_ctx_t *ctx,
3908 ism330dhcx_fs_g_ois_t *val)
3909 {
3910 ism330dhcx_ctrl1_ois_t ctrl1_ois;
3911 int32_t ret;
3912
3913 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL1_OIS,
3914 (uint8_t *)&ctrl1_ois, 1);
3915
3916 switch ((ctrl1_ois.fs_125_ois << 2) + ctrl1_ois.fs_g_ois)
3917 {
3918 case ISM330DHCX_250dps_AUX:
3919 *val = ISM330DHCX_250dps_AUX;
3920 break;
3921
3922 case ISM330DHCX_125dps_AUX:
3923 *val = ISM330DHCX_125dps_AUX;
3924 break;
3925
3926 case ISM330DHCX_500dps_AUX:
3927 *val = ISM330DHCX_500dps_AUX;
3928 break;
3929
3930 case ISM330DHCX_1000dps_AUX:
3931 *val = ISM330DHCX_1000dps_AUX;
3932 break;
3933
3934 case ISM330DHCX_2000dps_AUX:
3935 *val = ISM330DHCX_2000dps_AUX;
3936 break;
3937
3938 default:
3939 *val = ISM330DHCX_250dps_AUX;
3940 break;
3941 }
3942
3943 return ret;
3944 }
3945
3946 /**
3947 * @brief SPI2 3- or 4-wire interface.[set]
3948 *
3949 * @param ctx Read / write interface definitions.(ptr)
3950 * @param val Change the values of sim_ois in reg CTRL1_OIS
3951 * @retval Interface status (MANDATORY: return 0 -> no Error).
3952 *
3953 */
ism330dhcx_aux_spi_mode_set(const stmdev_ctx_t * ctx,ism330dhcx_sim_ois_t val)3954 int32_t ism330dhcx_aux_spi_mode_set(const stmdev_ctx_t *ctx,
3955 ism330dhcx_sim_ois_t val)
3956 {
3957 ism330dhcx_ctrl1_ois_t ctrl1_ois;
3958 int32_t ret;
3959
3960 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL1_OIS,
3961 (uint8_t *)&ctrl1_ois, 1);
3962
3963 if (ret == 0)
3964 {
3965 ctrl1_ois.sim_ois = (uint8_t)val;
3966 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL1_OIS,
3967 (uint8_t *)&ctrl1_ois, 1);
3968 }
3969
3970 return ret;
3971 }
3972
3973 /**
3974 * @brief SPI2 3- or 4-wire interface.[get]
3975 *
3976 * @param ctx Read / write interface definitions.(ptr)
3977 * @param val Get the values of sim_ois in reg CTRL1_OIS
3978 * @retval Interface status (MANDATORY: return 0 -> no Error).
3979 *
3980 */
ism330dhcx_aux_spi_mode_get(const stmdev_ctx_t * ctx,ism330dhcx_sim_ois_t * val)3981 int32_t ism330dhcx_aux_spi_mode_get(const stmdev_ctx_t *ctx,
3982 ism330dhcx_sim_ois_t *val)
3983 {
3984 ism330dhcx_ctrl1_ois_t ctrl1_ois;
3985 int32_t ret;
3986
3987 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL1_OIS,
3988 (uint8_t *)&ctrl1_ois, 1);
3989
3990 switch (ctrl1_ois.sim_ois)
3991 {
3992 case ISM330DHCX_AUX_SPI_4_WIRE:
3993 *val = ISM330DHCX_AUX_SPI_4_WIRE;
3994 break;
3995
3996 case ISM330DHCX_AUX_SPI_3_WIRE:
3997 *val = ISM330DHCX_AUX_SPI_3_WIRE;
3998 break;
3999
4000 default:
4001 *val = ISM330DHCX_AUX_SPI_4_WIRE;
4002 break;
4003 }
4004
4005 return ret;
4006 }
4007
4008 /**
4009 * @brief Selects gyroscope digital LPF1 filter bandwidth.[set]
4010 *
4011 * @param ctx Read / write interface definitions.(ptr)
4012 * @param val Change the values of ftype_ois in reg CTRL2_OIS
4013 * @retval Interface status (MANDATORY: return 0 -> no Error).
4014 *
4015 */
ism330dhcx_aux_gy_lp1_bandwidth_set(const stmdev_ctx_t * ctx,ism330dhcx_ftype_ois_t val)4016 int32_t ism330dhcx_aux_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx,
4017 ism330dhcx_ftype_ois_t val)
4018 {
4019 ism330dhcx_ctrl2_ois_t ctrl2_ois;
4020 int32_t ret;
4021
4022 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL2_OIS,
4023 (uint8_t *)&ctrl2_ois, 1);
4024
4025 if (ret == 0)
4026 {
4027 ctrl2_ois.ftype_ois = (uint8_t)val;
4028 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL2_OIS,
4029 (uint8_t *)&ctrl2_ois, 1);
4030 }
4031
4032 return ret;
4033 }
4034
4035 /**
4036 * @brief Selects gyroscope digital LPF1 filter bandwidth.[get]
4037 *
4038 * @param ctx Read / write interface definitions.(ptr)
4039 * @param val Get the values of ftype_ois in reg CTRL2_OIS
4040 * @retval Interface status (MANDATORY: return 0 -> no Error).
4041 *
4042 */
ism330dhcx_aux_gy_lp1_bandwidth_get(const stmdev_ctx_t * ctx,ism330dhcx_ftype_ois_t * val)4043 int32_t ism330dhcx_aux_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx,
4044 ism330dhcx_ftype_ois_t *val)
4045 {
4046 ism330dhcx_ctrl2_ois_t ctrl2_ois;
4047 int32_t ret;
4048
4049 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL2_OIS,
4050 (uint8_t *)&ctrl2_ois, 1);
4051
4052 switch (ctrl2_ois.ftype_ois)
4053 {
4054 case ISM330DHCX_351Hz39:
4055 *val = ISM330DHCX_351Hz39;
4056 break;
4057
4058 case ISM330DHCX_236Hz63:
4059 *val = ISM330DHCX_236Hz63;
4060 break;
4061
4062 case ISM330DHCX_172Hz70:
4063 *val = ISM330DHCX_172Hz70;
4064 break;
4065
4066 case ISM330DHCX_937Hz91:
4067 *val = ISM330DHCX_937Hz91;
4068 break;
4069
4070 default:
4071 *val = ISM330DHCX_351Hz39;
4072 break;
4073 }
4074
4075 return ret;
4076 }
4077
4078 /**
4079 * @brief Selects gyroscope OIS chain digital high-pass filter cutoff.[set]
4080 *
4081 * @param ctx Read / write interface definitions.(ptr)
4082 * @param val Change the values of hpm_ois in reg CTRL2_OIS
4083 * @retval Interface status (MANDATORY: return 0 -> no Error).
4084 *
4085 */
ism330dhcx_aux_gy_hp_bandwidth_set(const stmdev_ctx_t * ctx,ism330dhcx_hpm_ois_t val)4086 int32_t ism330dhcx_aux_gy_hp_bandwidth_set(const stmdev_ctx_t *ctx,
4087 ism330dhcx_hpm_ois_t val)
4088 {
4089 ism330dhcx_ctrl2_ois_t ctrl2_ois;
4090 int32_t ret;
4091
4092 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL2_OIS,
4093 (uint8_t *)&ctrl2_ois, 1);
4094
4095 if (ret == 0)
4096 {
4097 ctrl2_ois.hpm_ois = (uint8_t)val & 0x03U;
4098 ctrl2_ois.hp_en_ois = ((uint8_t)val & 0x10U) >> 4;
4099 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL2_OIS,
4100 (uint8_t *)&ctrl2_ois, 1);
4101 }
4102
4103 return ret;
4104 }
4105
4106 /**
4107 * @brief Selects gyroscope OIS chain digital high-pass filter cutoff.[get]
4108 *
4109 * @param ctx Read / write interface definitions.(ptr)
4110 * @param val Get the values of hpm_ois in reg CTRL2_OIS
4111 * @retval Interface status (MANDATORY: return 0 -> no Error).
4112 *
4113 */
ism330dhcx_aux_gy_hp_bandwidth_get(const stmdev_ctx_t * ctx,ism330dhcx_hpm_ois_t * val)4114 int32_t ism330dhcx_aux_gy_hp_bandwidth_get(const stmdev_ctx_t *ctx,
4115 ism330dhcx_hpm_ois_t *val)
4116 {
4117 ism330dhcx_ctrl2_ois_t ctrl2_ois;
4118 int32_t ret;
4119
4120 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL2_OIS,
4121 (uint8_t *)&ctrl2_ois, 1);
4122
4123 switch ((ctrl2_ois.hp_en_ois << 4) + ctrl2_ois.hpm_ois)
4124 {
4125 case ISM330DHCX_AUX_HP_DISABLE:
4126 *val = ISM330DHCX_AUX_HP_DISABLE;
4127 break;
4128
4129 case ISM330DHCX_AUX_HP_Hz016:
4130 *val = ISM330DHCX_AUX_HP_Hz016;
4131 break;
4132
4133 case ISM330DHCX_AUX_HP_Hz065:
4134 *val = ISM330DHCX_AUX_HP_Hz065;
4135 break;
4136
4137 case ISM330DHCX_AUX_HP_Hz260:
4138 *val = ISM330DHCX_AUX_HP_Hz260;
4139 break;
4140
4141 case ISM330DHCX_AUX_HP_1Hz040:
4142 *val = ISM330DHCX_AUX_HP_1Hz040;
4143 break;
4144
4145 default:
4146 *val = ISM330DHCX_AUX_HP_DISABLE;
4147 break;
4148 }
4149
4150 return ret;
4151 }
4152
4153 /**
4154 * @brief Enable / Disables OIS chain clamp. Enable: All OIS chain
4155 * outputs = 8000h during self-test; Disable: OIS chain self-test
4156 * outputs dependent from the aux gyro full scale selected.[set]
4157 *
4158 * @param ctx Read / write interface definitions.(ptr)
4159 * @param val Change the values of st_ois_clampdis in reg CTRL3_OIS
4160 * @retval Interface status (MANDATORY: return 0 -> no Error).
4161 *
4162 */
ism330dhcx_aux_gy_clamp_set(const stmdev_ctx_t * ctx,ism330dhcx_st_ois_clampdis_t val)4163 int32_t ism330dhcx_aux_gy_clamp_set(const stmdev_ctx_t *ctx,
4164 ism330dhcx_st_ois_clampdis_t val)
4165 {
4166 ism330dhcx_ctrl3_ois_t ctrl3_ois;
4167 int32_t ret;
4168
4169 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_OIS,
4170 (uint8_t *)&ctrl3_ois, 1);
4171
4172 if (ret == 0)
4173 {
4174 ctrl3_ois.st_ois_clampdis = (uint8_t)val;
4175 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL3_OIS,
4176 (uint8_t *)&ctrl3_ois, 1);
4177 }
4178
4179 return ret;
4180 }
4181
4182 /**
4183 * @brief Enable / Disables OIS chain clamp. Enable: All OIS chain
4184 * outputs = 8000h during self-test; Disable: OIS chain self-test
4185 * outputs dependent from the aux gyro full scale selected.[get]
4186 *
4187 * @param ctx Read / write interface definitions.(ptr)
4188 * @param val Get the values of st_ois_clampdis in reg CTRL3_OIS
4189 * @retval Interface status (MANDATORY: return 0 -> no Error).
4190 *
4191 */
ism330dhcx_aux_gy_clamp_get(const stmdev_ctx_t * ctx,ism330dhcx_st_ois_clampdis_t * val)4192 int32_t ism330dhcx_aux_gy_clamp_get(const stmdev_ctx_t *ctx,
4193 ism330dhcx_st_ois_clampdis_t *val)
4194 {
4195 ism330dhcx_ctrl3_ois_t ctrl3_ois;
4196 int32_t ret;
4197
4198 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_OIS,
4199 (uint8_t *)&ctrl3_ois, 1);
4200
4201 switch (ctrl3_ois.st_ois_clampdis)
4202 {
4203 case ISM330DHCX_ENABLE_CLAMP:
4204 *val = ISM330DHCX_ENABLE_CLAMP;
4205 break;
4206
4207 case ISM330DHCX_DISABLE_CLAMP:
4208 *val = ISM330DHCX_DISABLE_CLAMP;
4209 break;
4210
4211 default:
4212 *val = ISM330DHCX_ENABLE_CLAMP;
4213 break;
4214 }
4215
4216 return ret;
4217 }
4218
4219 /**
4220 * @brief Selects gyroscope OIS chain self-test.[set]
4221 *
4222 * @param ctx Read / write interface definitions.(ptr)
4223 * @param val Change the values of st_ois in reg CTRL3_OIS
4224 * @retval Interface status (MANDATORY: return 0 -> no Error).
4225 *
4226 */
ism330dhcx_aux_gy_self_test_set(const stmdev_ctx_t * ctx,ism330dhcx_st_ois_t val)4227 int32_t ism330dhcx_aux_gy_self_test_set(const stmdev_ctx_t *ctx,
4228 ism330dhcx_st_ois_t val)
4229 {
4230 ism330dhcx_ctrl3_ois_t ctrl3_ois;
4231 int32_t ret;
4232
4233 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_OIS,
4234 (uint8_t *)&ctrl3_ois, 1);
4235
4236 if (ret == 0)
4237 {
4238 ctrl3_ois.st_ois = (uint8_t)val;
4239 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL3_OIS,
4240 (uint8_t *)&ctrl3_ois, 1);
4241 }
4242
4243 return ret;
4244 }
4245
4246 /**
4247 * @brief Selects gyroscope OIS chain self-test.[get]
4248 *
4249 * @param ctx Read / write interface definitions.(ptr)
4250 * @param val Get the values of st_ois in reg CTRL3_OIS
4251 * @retval Interface status (MANDATORY: return 0 -> no Error).
4252 *
4253 */
ism330dhcx_aux_gy_self_test_get(const stmdev_ctx_t * ctx,ism330dhcx_st_ois_t * val)4254 int32_t ism330dhcx_aux_gy_self_test_get(const stmdev_ctx_t *ctx,
4255 ism330dhcx_st_ois_t *val)
4256 {
4257 ism330dhcx_ctrl3_ois_t ctrl3_ois;
4258 int32_t ret;
4259
4260 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_OIS,
4261 (uint8_t *)&ctrl3_ois, 1);
4262
4263 switch (ctrl3_ois.st_ois)
4264 {
4265 case ISM330DHCX_AUX_GY_DISABLE:
4266 *val = ISM330DHCX_AUX_GY_DISABLE;
4267 break;
4268
4269 case ISM330DHCX_AUX_GY_POS:
4270 *val = ISM330DHCX_AUX_GY_POS;
4271 break;
4272
4273 case ISM330DHCX_AUX_GY_NEG:
4274 *val = ISM330DHCX_AUX_GY_NEG;
4275 break;
4276
4277 default:
4278 *val = ISM330DHCX_AUX_GY_DISABLE;
4279 break;
4280 }
4281
4282 return ret;
4283 }
4284
4285 /**
4286 * @brief Selects accelerometer OIS channel bandwidth.[set]
4287 *
4288 * @param ctx Read / write interface definitions.(ptr)
4289 * @param val Change the values of filter_xl_conf_ois in reg CTRL3_OIS
4290 * @retval Interface status (MANDATORY: return 0 -> no Error).
4291 *
4292 */
ism330dhcx_aux_xl_bandwidth_set(const stmdev_ctx_t * ctx,ism330dhcx_filter_xl_conf_ois_t val)4293 int32_t ism330dhcx_aux_xl_bandwidth_set(const stmdev_ctx_t *ctx,
4294 ism330dhcx_filter_xl_conf_ois_t val)
4295 {
4296 ism330dhcx_ctrl3_ois_t ctrl3_ois;
4297 int32_t ret;
4298
4299 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_OIS,
4300 (uint8_t *)&ctrl3_ois, 1);
4301
4302 if (ret == 0)
4303 {
4304 ctrl3_ois.filter_xl_conf_ois = (uint8_t)val;
4305 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL3_OIS,
4306 (uint8_t *)&ctrl3_ois, 1);
4307 }
4308
4309 return ret;
4310 }
4311
4312 /**
4313 * @brief Selects accelerometer OIS channel bandwidth.[get]
4314 *
4315 * @param ctx Read / write interface definitions.(ptr)
4316 * @param val Get the values of filter_xl_conf_ois in reg CTRL3_OIS
4317 * @retval Interface status (MANDATORY: return 0 -> no Error).
4318 *
4319 */
ism330dhcx_aux_xl_bandwidth_get(const stmdev_ctx_t * ctx,ism330dhcx_filter_xl_conf_ois_t * val)4320 int32_t ism330dhcx_aux_xl_bandwidth_get(const stmdev_ctx_t *ctx,
4321 ism330dhcx_filter_xl_conf_ois_t *val)
4322 {
4323 ism330dhcx_ctrl3_ois_t ctrl3_ois;
4324 int32_t ret;
4325
4326 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_OIS,
4327 (uint8_t *)&ctrl3_ois, 1);
4328
4329 switch (ctrl3_ois.filter_xl_conf_ois)
4330 {
4331 case ISM330DHCX_631Hz:
4332 *val = ISM330DHCX_631Hz;
4333 break;
4334
4335 case ISM330DHCX_295Hz:
4336 *val = ISM330DHCX_295Hz;
4337 break;
4338
4339 case ISM330DHCX_140Hz:
4340 *val = ISM330DHCX_140Hz;
4341 break;
4342
4343 case ISM330DHCX_68Hz2:
4344 *val = ISM330DHCX_68Hz2;
4345 break;
4346
4347 case ISM330DHCX_33Hz6:
4348 *val = ISM330DHCX_33Hz6;
4349 break;
4350
4351 case ISM330DHCX_16Hz7:
4352 *val = ISM330DHCX_16Hz7;
4353 break;
4354
4355 case ISM330DHCX_8Hz3:
4356 *val = ISM330DHCX_8Hz3;
4357 break;
4358
4359 case ISM330DHCX_4Hz11:
4360 *val = ISM330DHCX_4Hz11;
4361 break;
4362
4363 default:
4364 *val = ISM330DHCX_631Hz;
4365 break;
4366 }
4367
4368 return ret;
4369 }
4370
4371 /**
4372 * @brief Selects accelerometer OIS channel full-scale.[set]
4373 *
4374 * @param ctx Read / write interface definitions.(ptr)
4375 * @param val Change the values of fs_xl_ois in reg CTRL3_OIS
4376 * @retval Interface status (MANDATORY: return 0 -> no Error).
4377 *
4378 */
ism330dhcx_aux_xl_full_scale_set(const stmdev_ctx_t * ctx,ism330dhcx_fs_xl_ois_t val)4379 int32_t ism330dhcx_aux_xl_full_scale_set(const stmdev_ctx_t *ctx,
4380 ism330dhcx_fs_xl_ois_t val)
4381 {
4382 ism330dhcx_ctrl3_ois_t ctrl3_ois;
4383 int32_t ret;
4384
4385 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_OIS,
4386 (uint8_t *)&ctrl3_ois, 1);
4387
4388 if (ret == 0)
4389 {
4390 ctrl3_ois.fs_xl_ois = (uint8_t)val;
4391 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL3_OIS,
4392 (uint8_t *)&ctrl3_ois, 1);
4393 }
4394
4395 return ret;
4396 }
4397
4398 /**
4399 * @brief Selects accelerometer OIS channel full-scale.[get]
4400 *
4401 * @param ctx Read / write interface definitions.(ptr)
4402 * @param val Get the values of fs_xl_ois in reg CTRL3_OIS
4403 * @retval Interface status (MANDATORY: return 0 -> no Error).
4404 *
4405 */
ism330dhcx_aux_xl_full_scale_get(const stmdev_ctx_t * ctx,ism330dhcx_fs_xl_ois_t * val)4406 int32_t ism330dhcx_aux_xl_full_scale_get(const stmdev_ctx_t *ctx,
4407 ism330dhcx_fs_xl_ois_t *val)
4408 {
4409 ism330dhcx_ctrl3_ois_t ctrl3_ois;
4410 int32_t ret;
4411
4412 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_OIS,
4413 (uint8_t *)&ctrl3_ois, 1);
4414
4415 switch (ctrl3_ois.fs_xl_ois)
4416 {
4417 case ISM330DHCX_AUX_2g:
4418 *val = ISM330DHCX_AUX_2g;
4419 break;
4420
4421 case ISM330DHCX_AUX_16g:
4422 *val = ISM330DHCX_AUX_16g;
4423 break;
4424
4425 case ISM330DHCX_AUX_4g:
4426 *val = ISM330DHCX_AUX_4g;
4427 break;
4428
4429 case ISM330DHCX_AUX_8g:
4430 *val = ISM330DHCX_AUX_8g;
4431 break;
4432
4433 default:
4434 *val = ISM330DHCX_AUX_2g;
4435 break;
4436 }
4437
4438 return ret;
4439 }
4440
4441 /**
4442 * @}
4443 *
4444 */
4445
4446 /**
4447 * @defgroup ISM330DHCX_ main_serial_interface
4448 * @brief This section groups all the functions concerning main
4449 * serial interface management (not auxiliary)
4450 * @{
4451 *
4452 */
4453
4454 /**
4455 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[set]
4456 *
4457 * @param ctx Read / write interface definitions.(ptr)
4458 * @param val Change the values of sdo_pu_en in reg PIN_CTRL
4459 * @retval Interface status (MANDATORY: return 0 -> no Error).
4460 *
4461 */
ism330dhcx_sdo_sa0_mode_set(const stmdev_ctx_t * ctx,ism330dhcx_sdo_pu_en_t val)4462 int32_t ism330dhcx_sdo_sa0_mode_set(const stmdev_ctx_t *ctx,
4463 ism330dhcx_sdo_pu_en_t val)
4464 {
4465 ism330dhcx_pin_ctrl_t pin_ctrl;
4466 int32_t ret;
4467
4468 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PIN_CTRL,
4469 (uint8_t *)&pin_ctrl, 1);
4470
4471 if (ret == 0)
4472 {
4473 pin_ctrl.sdo_pu_en = (uint8_t)val;
4474 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PIN_CTRL,
4475 (uint8_t *)&pin_ctrl, 1);
4476 }
4477
4478 return ret;
4479 }
4480
4481 /**
4482 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[get]
4483 *
4484 * @param ctx Read / write interface definitions.(ptr)
4485 * @param val Get the values of sdo_pu_en in reg PIN_CTRL
4486 * @retval Interface status (MANDATORY: return 0 -> no Error).
4487 *
4488 */
ism330dhcx_sdo_sa0_mode_get(const stmdev_ctx_t * ctx,ism330dhcx_sdo_pu_en_t * val)4489 int32_t ism330dhcx_sdo_sa0_mode_get(const stmdev_ctx_t *ctx,
4490 ism330dhcx_sdo_pu_en_t *val)
4491 {
4492 ism330dhcx_pin_ctrl_t pin_ctrl;
4493 int32_t ret;
4494
4495 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PIN_CTRL,
4496 (uint8_t *)&pin_ctrl, 1);
4497
4498 switch (pin_ctrl.sdo_pu_en)
4499 {
4500 case ISM330DHCX_PULL_UP_DISC:
4501 *val = ISM330DHCX_PULL_UP_DISC;
4502 break;
4503
4504 case ISM330DHCX_PULL_UP_CONNECT:
4505 *val = ISM330DHCX_PULL_UP_CONNECT;
4506 break;
4507
4508 default:
4509 *val = ISM330DHCX_PULL_UP_DISC;
4510 break;
4511 }
4512
4513 return ret;
4514 }
4515
4516 /**
4517 * @brief SPI Serial Interface Mode selection.[set]
4518 *
4519 * @param ctx Read / write interface definitions.(ptr)
4520 * @param val Change the values of sim in reg CTRL3_C
4521 * @retval Interface status (MANDATORY: return 0 -> no Error).
4522 *
4523 */
ism330dhcx_spi_mode_set(const stmdev_ctx_t * ctx,ism330dhcx_sim_t val)4524 int32_t ism330dhcx_spi_mode_set(const stmdev_ctx_t *ctx,
4525 ism330dhcx_sim_t val)
4526 {
4527 ism330dhcx_ctrl3_c_t ctrl3_c;
4528 int32_t ret;
4529
4530 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C,
4531 (uint8_t *)&ctrl3_c, 1);
4532
4533 if (ret == 0)
4534 {
4535 ctrl3_c.sim = (uint8_t)val;
4536 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL3_C,
4537 (uint8_t *)&ctrl3_c, 1);
4538 }
4539
4540 return ret;
4541 }
4542
4543 /**
4544 * @brief SPI Serial Interface Mode selection.[get]
4545 *
4546 * @param ctx Read / write interface definitions.(ptr)
4547 * @param val Get the values of sim in reg CTRL3_C
4548 * @retval Interface status (MANDATORY: return 0 -> no Error).
4549 *
4550 */
ism330dhcx_spi_mode_get(const stmdev_ctx_t * ctx,ism330dhcx_sim_t * val)4551 int32_t ism330dhcx_spi_mode_get(const stmdev_ctx_t *ctx,
4552 ism330dhcx_sim_t *val)
4553 {
4554 ism330dhcx_ctrl3_c_t ctrl3_c;
4555 int32_t ret;
4556
4557 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C,
4558 (uint8_t *)&ctrl3_c, 1);
4559
4560 switch (ctrl3_c.sim)
4561 {
4562 case ISM330DHCX_SPI_4_WIRE:
4563 *val = ISM330DHCX_SPI_4_WIRE;
4564 break;
4565
4566 case ISM330DHCX_SPI_3_WIRE:
4567 *val = ISM330DHCX_SPI_3_WIRE;
4568 break;
4569
4570 default:
4571 *val = ISM330DHCX_SPI_4_WIRE;
4572 break;
4573 }
4574
4575 return ret;
4576 }
4577
4578 /**
4579 * @brief Disable / Enable I2C interface.[set]
4580 *
4581 * @param ctx Read / write interface definitions.(ptr)
4582 * @param val Change the values of i2c_disable in reg CTRL4_C
4583 * @retval Interface status (MANDATORY: return 0 -> no Error).
4584 *
4585 */
ism330dhcx_i2c_interface_set(const stmdev_ctx_t * ctx,ism330dhcx_i2c_disable_t val)4586 int32_t ism330dhcx_i2c_interface_set(const stmdev_ctx_t *ctx,
4587 ism330dhcx_i2c_disable_t val)
4588 {
4589 ism330dhcx_ctrl4_c_t ctrl4_c;
4590 int32_t ret;
4591
4592 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL4_C,
4593 (uint8_t *)&ctrl4_c, 1);
4594
4595 if (ret == 0)
4596 {
4597 ctrl4_c.i2c_disable = (uint8_t)val;
4598 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL4_C,
4599 (uint8_t *)&ctrl4_c, 1);
4600 }
4601
4602 return ret;
4603 }
4604
4605 /**
4606 * @brief Disable / Enable I2C interface.[get]
4607 *
4608 * @param ctx Read / write interface definitions.(ptr)
4609 * @param val Get the values of i2c reg CTRL4_C
4610 * @retval Interface status (MANDATORY: return 0 -> no Error).
4611 *
4612 */
ism330dhcx_i2c_interface_get(const stmdev_ctx_t * ctx,ism330dhcx_i2c_disable_t * val)4613 int32_t ism330dhcx_i2c_interface_get(const stmdev_ctx_t *ctx,
4614 ism330dhcx_i2c_disable_t *val)
4615 {
4616 ism330dhcx_ctrl4_c_t ctrl4_c;
4617 int32_t ret;
4618
4619 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL4_C,
4620 (uint8_t *)&ctrl4_c, 1);
4621
4622 switch (ctrl4_c.i2c_disable)
4623 {
4624 case ISM330DHCX_I2C_ENABLE:
4625 *val = ISM330DHCX_I2C_ENABLE;
4626 break;
4627
4628 case ISM330DHCX_I2C_DISABLE:
4629 *val = ISM330DHCX_I2C_DISABLE;
4630 break;
4631
4632 default:
4633 *val = ISM330DHCX_I2C_ENABLE;
4634 break;
4635 }
4636
4637 return ret;
4638 }
4639
4640 /**
4641 * @}
4642 *
4643 */
4644
4645 /**
4646 * @defgroup ISM330DHCX_interrupt_pins
4647 * @brief This section groups all the functions that manage
4648 * interrupt pins
4649 * @{
4650 *
4651 */
4652
4653 /**
4654 * @brief Select the signal that need to route on int1 pad[set]
4655 *
4656 * @param ctx Read / write interface definitions.(ptr)
4657 * @param val Structure of registers: INT1_CTRL,MD1_CFG,
4658 * EMB_FUNC_INT1, FSM_INT1_A, FSM_INT1_B
4659 * @retval Interface status (MANDATORY: return 0 -> no Error).
4660 *
4661 */
ism330dhcx_pin_int1_route_set(const stmdev_ctx_t * ctx,ism330dhcx_pin_int1_route_t * val)4662 int32_t ism330dhcx_pin_int1_route_set(const stmdev_ctx_t *ctx,
4663 ism330dhcx_pin_int1_route_t *val)
4664 {
4665 ism330dhcx_tap_cfg2_t tap_cfg2;
4666 int32_t ret;
4667
4668 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
4669
4670 if (ret == 0)
4671 {
4672 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_MLC_INT1,
4673 (uint8_t *)&val->mlc_int1, 1);
4674 }
4675
4676 if (ret == 0)
4677 {
4678 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_EMB_FUNC_INT1,
4679 (uint8_t *)&val->emb_func_int1, 1);
4680 }
4681
4682 if (ret == 0)
4683 {
4684 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_FSM_INT1_A,
4685 (uint8_t *)&val->fsm_int1_a, 1);
4686 }
4687
4688 if (ret == 0)
4689 {
4690 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_FSM_INT1_B,
4691 (uint8_t *)&val->fsm_int1_b, 1);
4692 }
4693
4694 if (ret == 0)
4695 {
4696 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
4697 }
4698
4699 if (ret == 0)
4700 {
4701 if ((val->emb_func_int1.int1_fsm_lc |
4702 val->emb_func_int1.int1_sig_mot |
4703 val->emb_func_int1.int1_step_detector |
4704 val->emb_func_int1.int1_tilt |
4705 val->fsm_int1_a.int1_fsm1 |
4706 val->fsm_int1_a.int1_fsm2 |
4707 val->fsm_int1_a.int1_fsm3 |
4708 val->fsm_int1_a.int1_fsm4 |
4709 val->fsm_int1_a.int1_fsm5 |
4710 val->fsm_int1_a.int1_fsm6 |
4711 val->fsm_int1_a.int1_fsm7 |
4712 val->fsm_int1_a.int1_fsm8 |
4713 val->fsm_int1_b.int1_fsm9 |
4714 val->fsm_int1_b.int1_fsm10 |
4715 val->fsm_int1_b.int1_fsm11 |
4716 val->fsm_int1_b.int1_fsm12 |
4717 val->fsm_int1_b.int1_fsm13 |
4718 val->fsm_int1_b.int1_fsm14 |
4719 val->fsm_int1_b.int1_fsm15 |
4720 val->fsm_int1_b.int1_fsm16 |
4721 val->mlc_int1.int1_mlc1 |
4722 val->mlc_int1.int1_mlc2 |
4723 val->mlc_int1.int1_mlc3 |
4724 val->mlc_int1.int1_mlc4 |
4725 val->mlc_int1.int1_mlc5 |
4726 val->mlc_int1.int1_mlc6 |
4727 val->mlc_int1.int1_mlc7 |
4728 val->mlc_int1.int1_mlc8) != PROPERTY_DISABLE)
4729 {
4730 val->md1_cfg.int1_emb_func = PROPERTY_ENABLE;
4731 }
4732 else
4733 {
4734 val->md1_cfg.int1_emb_func = PROPERTY_DISABLE;
4735 }
4736
4737 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_INT1_CTRL,
4738 (uint8_t *)&val->int1_ctrl, 1);
4739 }
4740
4741 if (ret == 0)
4742 {
4743 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_MD1_CFG,
4744 (uint8_t *)&val->md1_cfg, 1);
4745 }
4746
4747 if (ret == 0)
4748 {
4749 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG2,
4750 (uint8_t *)&tap_cfg2, 1);
4751
4752 if ((val->int1_ctrl.den_drdy_flag |
4753 val->int1_ctrl.int1_boot |
4754 val->int1_ctrl.int1_cnt_bdr |
4755 val->int1_ctrl.int1_drdy_g |
4756 val->int1_ctrl.int1_drdy_xl |
4757 val->int1_ctrl.int1_fifo_full |
4758 val->int1_ctrl.int1_fifo_ovr |
4759 val->int1_ctrl.int1_fifo_th |
4760 val->md1_cfg.int1_shub |
4761 val->md1_cfg.int1_6d |
4762 val->md1_cfg.int1_double_tap |
4763 val->md1_cfg.int1_ff |
4764 val->md1_cfg.int1_wu |
4765 val->md1_cfg.int1_single_tap |
4766 val->md1_cfg.int1_sleep_change) != PROPERTY_DISABLE)
4767 {
4768 tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
4769 }
4770
4771 else
4772 {
4773 tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
4774 }
4775 }
4776
4777 if (ret == 0)
4778 {
4779 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_TAP_CFG2,
4780 (uint8_t *)&tap_cfg2, 1);
4781 }
4782
4783 return ret;
4784 }
4785
4786 /**
4787 * @brief Select the signal that need to route on int1 pad.[get]
4788 *
4789 * @param ctx Read / write interface definitions.(ptr)
4790 * @param val Structure of registers: INT1_CTRL, MD1_CFG,
4791 * EMB_FUNC_INT1, FSM_INT1_A, FSM_INT1_B.(ptr)
4792 * @retval Interface status (MANDATORY: return 0 -> no Error).
4793 *
4794 */
ism330dhcx_pin_int1_route_get(const stmdev_ctx_t * ctx,ism330dhcx_pin_int1_route_t * val)4795 int32_t ism330dhcx_pin_int1_route_get(const stmdev_ctx_t *ctx,
4796 ism330dhcx_pin_int1_route_t *val)
4797 {
4798 int32_t ret;
4799
4800 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
4801
4802 if (ret == 0)
4803 {
4804 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_MLC_INT1,
4805 (uint8_t *)&val->mlc_int1, 1);
4806 }
4807
4808 if (ret == 0)
4809 {
4810 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_INT1,
4811 (uint8_t *)&val->emb_func_int1, 1);
4812 }
4813
4814 if (ret == 0)
4815 {
4816 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FSM_INT1_A,
4817 (uint8_t *)&val->fsm_int1_a, 1);
4818 }
4819
4820 if (ret == 0)
4821 {
4822 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FSM_INT1_B,
4823 (uint8_t *)&val->fsm_int1_b, 1);
4824 }
4825
4826 if (ret == 0)
4827 {
4828 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
4829 }
4830
4831 if (ret == 0)
4832 {
4833 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT1_CTRL,
4834 (uint8_t *)&val->int1_ctrl, 1);
4835 }
4836
4837 if (ret == 0)
4838 {
4839 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_MD1_CFG,
4840 (uint8_t *)&val->md1_cfg, 1);
4841 }
4842
4843 return ret;
4844 }
4845
4846 /**
4847 * @brief Select the signal that need to route on int2 pad[set]
4848 *
4849 * @param ctx Read / write interface definitions.(ptr)
4850 * @param val Structure of registers INT2_CTRL, MD2_CFG,
4851 * EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B
4852 * @retval Interface status (MANDATORY: return 0 -> no Error).
4853 *
4854 */
ism330dhcx_pin_int2_route_set(const stmdev_ctx_t * ctx,ism330dhcx_pin_int2_route_t * val)4855 int32_t ism330dhcx_pin_int2_route_set(const stmdev_ctx_t *ctx,
4856 ism330dhcx_pin_int2_route_t *val)
4857 {
4858 ism330dhcx_tap_cfg2_t tap_cfg2;
4859 int32_t ret;
4860
4861 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
4862
4863 if (ret == 0)
4864 {
4865 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_MLC_INT2,
4866 (uint8_t *)&val->mlc_int2, 1);
4867 }
4868
4869 if (ret == 0)
4870 {
4871 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_EMB_FUNC_INT2,
4872 (uint8_t *)&val->emb_func_int2, 1);
4873 }
4874
4875 if (ret == 0)
4876 {
4877 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_FSM_INT2_A,
4878 (uint8_t *)&val->fsm_int2_a, 1);
4879 }
4880
4881 if (ret == 0)
4882 {
4883 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_FSM_INT2_B,
4884 (uint8_t *)&val->fsm_int2_b, 1);
4885 }
4886
4887 if (ret == 0)
4888 {
4889 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
4890 }
4891
4892 if (ret == 0)
4893 {
4894 if ((val->emb_func_int2.int2_step_detector |
4895 val->emb_func_int2.int2_tilt |
4896 val->emb_func_int2.int2_sig_mot |
4897 val->emb_func_int2.int2_fsm_lc |
4898 val->fsm_int2_a.int2_fsm1 |
4899 val->fsm_int2_a.int2_fsm2 |
4900 val->fsm_int2_a.int2_fsm3 |
4901 val->fsm_int2_a.int2_fsm4 |
4902 val->fsm_int2_a.int2_fsm5 |
4903 val->fsm_int2_a.int2_fsm6 |
4904 val->fsm_int2_a.int2_fsm7 |
4905 val->fsm_int2_a.int2_fsm8 |
4906 val->fsm_int2_b.int2_fsm9 |
4907 val->fsm_int2_b.int2_fsm10 |
4908 val->fsm_int2_b.int2_fsm11 |
4909 val->fsm_int2_b.int2_fsm12 |
4910 val->fsm_int2_b.int2_fsm13 |
4911 val->fsm_int2_b.int2_fsm14 |
4912 val->fsm_int2_b.int2_fsm15 |
4913 val->fsm_int2_b.int2_fsm16 |
4914 val->mlc_int2.int2_mlc1 |
4915 val->mlc_int2.int2_mlc2 |
4916 val->mlc_int2.int2_mlc3 |
4917 val->mlc_int2.int2_mlc4 |
4918 val->mlc_int2.int2_mlc5 |
4919 val->mlc_int2.int2_mlc6 |
4920 val->mlc_int2.int2_mlc7 |
4921 val->mlc_int2.int2_mlc8) != PROPERTY_DISABLE)
4922 {
4923 val->md2_cfg.int2_emb_func = PROPERTY_ENABLE;
4924 }
4925 else
4926 {
4927 val->md2_cfg.int2_emb_func = PROPERTY_DISABLE;
4928 }
4929
4930 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_INT2_CTRL,
4931 (uint8_t *)&val->int2_ctrl, 1);
4932 }
4933
4934 if (ret == 0)
4935 {
4936 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_MD2_CFG,
4937 (uint8_t *)&val->md2_cfg, 1);
4938 }
4939
4940 if (ret == 0)
4941 {
4942 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG2,
4943 (uint8_t *)&tap_cfg2, 1);
4944 }
4945
4946 if (ret == 0)
4947 {
4948 if ((val->int2_ctrl.int2_drdy_xl |
4949 val->int2_ctrl.int2_drdy_g |
4950 val->int2_ctrl.int2_drdy_temp |
4951 val->int2_ctrl.int2_fifo_th |
4952 val->int2_ctrl.int2_fifo_ovr |
4953 val->int2_ctrl.int2_fifo_full |
4954 val->int2_ctrl.int2_cnt_bdr |
4955 val->md2_cfg.int2_6d |
4956 val->md2_cfg.int2_double_tap |
4957 val->md2_cfg.int2_ff |
4958 val->md2_cfg.int2_wu |
4959 val->md2_cfg.int2_single_tap |
4960 val->md2_cfg.int2_sleep_change) != PROPERTY_DISABLE)
4961 {
4962 tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
4963 }
4964
4965 else
4966 {
4967 tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
4968 }
4969
4970 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_TAP_CFG2,
4971 (uint8_t *)&tap_cfg2, 1);
4972 }
4973
4974 return ret;
4975 }
4976
4977 /**
4978 * @brief Select the signal that need to route on int2 pad.[get]
4979 *
4980 * @param ctx Read / write interface definitions.(ptr)
4981 * @param val Structure of registers INT2_CTRL, MD2_CFG,
4982 * EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B.[get]
4983 * @retval Interface status (MANDATORY: return 0 -> no Error).
4984 *
4985 */
ism330dhcx_pin_int2_route_get(const stmdev_ctx_t * ctx,ism330dhcx_pin_int2_route_t * val)4986 int32_t ism330dhcx_pin_int2_route_get(const stmdev_ctx_t *ctx,
4987 ism330dhcx_pin_int2_route_t *val)
4988 {
4989 int32_t ret;
4990
4991 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
4992
4993 if (ret == 0)
4994 {
4995 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_MLC_INT2,
4996 (uint8_t *)&val->mlc_int2, 1);
4997 }
4998
4999 if (ret == 0)
5000 {
5001 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_INT2,
5002 (uint8_t *)&val->emb_func_int2, 1);
5003 }
5004
5005 if (ret == 0)
5006 {
5007 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FSM_INT2_A,
5008 (uint8_t *)&val->fsm_int2_a, 1);
5009 }
5010
5011 if (ret == 0)
5012 {
5013 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FSM_INT2_B,
5014 (uint8_t *)&val->fsm_int2_b, 1);
5015 }
5016
5017 if (ret == 0)
5018 {
5019 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
5020 }
5021
5022 if (ret == 0)
5023 {
5024 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT2_CTRL,
5025 (uint8_t *)&val->int2_ctrl, 1);
5026 }
5027
5028 if (ret == 0)
5029 {
5030 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_MD2_CFG,
5031 (uint8_t *)&val->md2_cfg, 1);
5032 }
5033
5034 return ret;
5035 }
5036
5037 /**
5038 * @brief Push-pull/open drain selection on interrupt pads.[set]
5039 *
5040 * @param ctx Read / write interface definitions.(ptr)
5041 * @param val Change the values of pp_od in reg CTRL3_C
5042 * @retval Interface status (MANDATORY: return 0 -> no Error).
5043 *
5044 */
ism330dhcx_pin_mode_set(const stmdev_ctx_t * ctx,ism330dhcx_pp_od_t val)5045 int32_t ism330dhcx_pin_mode_set(const stmdev_ctx_t *ctx,
5046 ism330dhcx_pp_od_t val)
5047 {
5048 ism330dhcx_ctrl3_c_t ctrl3_c;
5049 int32_t ret;
5050
5051 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C,
5052 (uint8_t *)&ctrl3_c, 1);
5053
5054 if (ret == 0)
5055 {
5056 ctrl3_c.pp_od = (uint8_t)val;
5057 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL3_C,
5058 (uint8_t *)&ctrl3_c, 1);
5059 }
5060
5061 return ret;
5062 }
5063
5064 /**
5065 * @brief Push-pull/open drain selection on interrupt pads.[get]
5066 *
5067 * @param ctx Read / write interface definitions.(ptr)
5068 * @param val Get the values of pp_od in reg CTRL3_C
5069 * @retval Interface status (MANDATORY: return 0 -> no Error).
5070 *
5071 */
ism330dhcx_pin_mode_get(const stmdev_ctx_t * ctx,ism330dhcx_pp_od_t * val)5072 int32_t ism330dhcx_pin_mode_get(const stmdev_ctx_t *ctx,
5073 ism330dhcx_pp_od_t *val)
5074 {
5075 ism330dhcx_ctrl3_c_t ctrl3_c;
5076 int32_t ret;
5077
5078 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C,
5079 (uint8_t *)&ctrl3_c, 1);
5080
5081 switch (ctrl3_c.pp_od)
5082 {
5083 case ISM330DHCX_PUSH_PULL:
5084 *val = ISM330DHCX_PUSH_PULL;
5085 break;
5086
5087 case ISM330DHCX_OPEN_DRAIN:
5088 *val = ISM330DHCX_OPEN_DRAIN;
5089 break;
5090
5091 default:
5092 *val = ISM330DHCX_PUSH_PULL;
5093 break;
5094 }
5095
5096 return ret;
5097 }
5098
5099 /**
5100 * @brief Interrupt active-high/low.[set]
5101 *
5102 * @param ctx Read / write interface definitions.(ptr)
5103 * @param val Change the values of h_lactive in reg CTRL3_C
5104 * @retval Interface status (MANDATORY: return 0 -> no Error).
5105 *
5106 */
ism330dhcx_pin_polarity_set(const stmdev_ctx_t * ctx,ism330dhcx_h_lactive_t val)5107 int32_t ism330dhcx_pin_polarity_set(const stmdev_ctx_t *ctx,
5108 ism330dhcx_h_lactive_t val)
5109 {
5110 ism330dhcx_ctrl3_c_t ctrl3_c;
5111 int32_t ret;
5112
5113 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C,
5114 (uint8_t *)&ctrl3_c, 1);
5115
5116 if (ret == 0)
5117 {
5118 ctrl3_c.h_lactive = (uint8_t)val;
5119 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL3_C,
5120 (uint8_t *)&ctrl3_c, 1);
5121 }
5122
5123 return ret;
5124 }
5125
5126 /**
5127 * @brief Interrupt active-high/low.[get]
5128 *
5129 * @param ctx Read / write interface definitions.(ptr)
5130 * @param val Get the values of h_lactive in reg CTRL3_C
5131 * @retval Interface status (MANDATORY: return 0 -> no Error).
5132 *
5133 */
ism330dhcx_pin_polarity_get(const stmdev_ctx_t * ctx,ism330dhcx_h_lactive_t * val)5134 int32_t ism330dhcx_pin_polarity_get(const stmdev_ctx_t *ctx,
5135 ism330dhcx_h_lactive_t *val)
5136 {
5137 ism330dhcx_ctrl3_c_t ctrl3_c;
5138 int32_t ret;
5139
5140 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C,
5141 (uint8_t *)&ctrl3_c, 1);
5142
5143 switch (ctrl3_c.h_lactive)
5144 {
5145 case ISM330DHCX_ACTIVE_HIGH:
5146 *val = ISM330DHCX_ACTIVE_HIGH;
5147 break;
5148
5149 case ISM330DHCX_ACTIVE_LOW:
5150 *val = ISM330DHCX_ACTIVE_LOW;
5151 break;
5152
5153 default:
5154 *val = ISM330DHCX_ACTIVE_HIGH;
5155 break;
5156 }
5157
5158 return ret;
5159 }
5160
5161 /**
5162 * @brief All interrupt signals become available on INT1 pin.[set]
5163 *
5164 * @param ctx Read / write interface definitions.(ptr)
5165 * @param val Change the values of int2_on_int1 in reg CTRL4_C
5166 * @retval Interface status (MANDATORY: return 0 -> no Error).
5167 *
5168 */
ism330dhcx_all_on_int1_set(const stmdev_ctx_t * ctx,uint8_t val)5169 int32_t ism330dhcx_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val)
5170 {
5171 ism330dhcx_ctrl4_c_t ctrl4_c;
5172 int32_t ret;
5173
5174 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL4_C,
5175 (uint8_t *)&ctrl4_c, 1);
5176
5177 if (ret == 0)
5178 {
5179 ctrl4_c.int2_on_int1 = (uint8_t)val;
5180 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL4_C,
5181 (uint8_t *)&ctrl4_c, 1);
5182 }
5183
5184 return ret;
5185 }
5186
5187 /**
5188 * @brief All interrupt signals become available on INT1 pin.[get]
5189 *
5190 * @param ctx Read / write interface definitions.(ptr)
5191 * @param val Change the values of int2_on_int1 in reg CTRL4_C
5192 * @retval Interface status (MANDATORY: return 0 -> no Error).
5193 *
5194 */
ism330dhcx_all_on_int1_get(const stmdev_ctx_t * ctx,uint8_t * val)5195 int32_t ism330dhcx_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val)
5196 {
5197 ism330dhcx_ctrl4_c_t ctrl4_c;
5198 int32_t ret;
5199
5200 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL4_C,
5201 (uint8_t *)&ctrl4_c, 1);
5202 *val = ctrl4_c.int2_on_int1;
5203
5204 return ret;
5205 }
5206
5207 /**
5208 * @brief All interrupt signals notification mode.[set]
5209 *
5210 * @param ctx Read / write interface definitions.(ptr)
5211 * @param val Change the values of lir in reg TAP_CFG0
5212 * @retval Interface status (MANDATORY: return 0 -> no Error).
5213 *
5214 */
ism330dhcx_int_notification_set(const stmdev_ctx_t * ctx,ism330dhcx_lir_t val)5215 int32_t ism330dhcx_int_notification_set(const stmdev_ctx_t *ctx,
5216 ism330dhcx_lir_t val)
5217 {
5218 ism330dhcx_tap_cfg0_t tap_cfg0;
5219 ism330dhcx_page_rw_t page_rw;
5220 int32_t ret;
5221
5222 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG0,
5223 (uint8_t *)&tap_cfg0, 1);
5224
5225 if (ret == 0)
5226 {
5227 tap_cfg0.lir = (uint8_t)val & 0x01U;
5228 tap_cfg0.int_clr_on_read = (uint8_t)val & 0x01U;
5229 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_TAP_CFG0,
5230 (uint8_t *)&tap_cfg0, 1);
5231 }
5232
5233 if (ret == 0)
5234 {
5235 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
5236 }
5237
5238 if (ret == 0)
5239 {
5240 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_RW,
5241 (uint8_t *)&page_rw, 1);
5242 }
5243
5244 if (ret == 0)
5245 {
5246 page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1;
5247 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_RW,
5248 (uint8_t *)&page_rw, 1);
5249 }
5250
5251 if (ret == 0)
5252 {
5253 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
5254 }
5255
5256 return ret;
5257 }
5258
5259 /**
5260 * @brief All interrupt signals notification mode.[get]
5261 *
5262 * @param ctx Read / write interface definitions.(ptr)
5263 * @param val Get the values of lir in reg TAP_CFG0
5264 * @retval Interface status (MANDATORY: return 0 -> no Error).
5265 *
5266 */
ism330dhcx_int_notification_get(const stmdev_ctx_t * ctx,ism330dhcx_lir_t * val)5267 int32_t ism330dhcx_int_notification_get(const stmdev_ctx_t *ctx,
5268 ism330dhcx_lir_t *val)
5269 {
5270 ism330dhcx_tap_cfg0_t tap_cfg0;
5271 ism330dhcx_page_rw_t page_rw;
5272 int32_t ret;
5273
5274 *val = ISM330DHCX_ALL_INT_PULSED;
5275 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG0,
5276 (uint8_t *)&tap_cfg0, 1);
5277
5278 if (ret == 0)
5279 {
5280 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
5281 }
5282
5283 if (ret == 0)
5284 {
5285 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_RW,
5286 (uint8_t *)&page_rw, 1);
5287 }
5288
5289 if (ret == 0)
5290 {
5291 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
5292 }
5293
5294 switch ((page_rw.emb_func_lir << 1) + tap_cfg0.lir)
5295 {
5296 case ISM330DHCX_ALL_INT_PULSED:
5297 *val = ISM330DHCX_ALL_INT_PULSED;
5298 break;
5299
5300 case ISM330DHCX_BASE_LATCHED_EMB_PULSED:
5301 *val = ISM330DHCX_BASE_LATCHED_EMB_PULSED;
5302 break;
5303
5304 case ISM330DHCX_BASE_PULSED_EMB_LATCHED:
5305 *val = ISM330DHCX_BASE_PULSED_EMB_LATCHED;
5306 break;
5307
5308 case ISM330DHCX_ALL_INT_LATCHED:
5309 *val = ISM330DHCX_ALL_INT_LATCHED;
5310 break;
5311
5312 default:
5313 *val = ISM330DHCX_ALL_INT_PULSED;
5314 break;
5315 }
5316
5317 return ret;
5318 }
5319
5320 /**
5321 * @}
5322 *
5323 */
5324
5325 /**
5326 * @defgroup ISM330DHCX_Wake_Up_event
5327 * @brief This section groups all the functions that manage the
5328 * Wake Up event generation.
5329 * @{
5330 *
5331 */
5332
5333 /**
5334 * @brief Weight of 1 LSB of wakeup threshold.[set]
5335 * 0: 1 LSB =FS_XL / 64
5336 * 1: 1 LSB = FS_XL / 256
5337 *
5338 * @param ctx Read / write interface definitions.(ptr)
5339 * @param val Change the values of wake_ths_w in reg WAKE_UP_DUR
5340 * @retval Interface status (MANDATORY: return 0 -> no Error).
5341 *
5342 */
ism330dhcx_wkup_ths_weight_set(const stmdev_ctx_t * ctx,ism330dhcx_wake_ths_w_t val)5343 int32_t ism330dhcx_wkup_ths_weight_set(const stmdev_ctx_t *ctx,
5344 ism330dhcx_wake_ths_w_t val)
5345 {
5346 ism330dhcx_wake_up_dur_t wake_up_dur;
5347 int32_t ret;
5348
5349 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_WAKE_UP_DUR,
5350 (uint8_t *)&wake_up_dur, 1);
5351
5352 if (ret == 0)
5353 {
5354 wake_up_dur.wake_ths_w = (uint8_t)val;
5355 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_WAKE_UP_DUR,
5356 (uint8_t *)&wake_up_dur, 1);
5357 }
5358
5359 return ret;
5360 }
5361
5362 /**
5363 * @brief Weight of 1 LSB of wakeup threshold.[get]
5364 * 0: 1 LSB =FS_XL / 64
5365 * 1: 1 LSB = FS_XL / 256
5366 *
5367 * @param ctx Read / write interface definitions.(ptr)
5368 * @param val Get the values of wake_ths_w in reg WAKE_UP_DUR
5369 * @retval Interface status (MANDATORY: return 0 -> no Error).
5370 *
5371 */
ism330dhcx_wkup_ths_weight_get(const stmdev_ctx_t * ctx,ism330dhcx_wake_ths_w_t * val)5372 int32_t ism330dhcx_wkup_ths_weight_get(const stmdev_ctx_t *ctx,
5373 ism330dhcx_wake_ths_w_t *val)
5374 {
5375 ism330dhcx_wake_up_dur_t wake_up_dur;
5376 int32_t ret;
5377
5378 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_WAKE_UP_DUR,
5379 (uint8_t *)&wake_up_dur, 1);
5380
5381 switch (wake_up_dur.wake_ths_w)
5382 {
5383 case ISM330DHCX_LSb_FS_DIV_64:
5384 *val = ISM330DHCX_LSb_FS_DIV_64;
5385 break;
5386
5387 case ISM330DHCX_LSb_FS_DIV_256:
5388 *val = ISM330DHCX_LSb_FS_DIV_256;
5389 break;
5390
5391 default:
5392 *val = ISM330DHCX_LSb_FS_DIV_64;
5393 break;
5394 }
5395
5396 return ret;
5397 }
5398
5399 /**
5400 * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
5401 * WAKE_UP_DUR.[set]
5402 *
5403 * @param ctx Read / write interface definitions.(ptr)
5404 * @param val Change the values of wk_ths in reg WAKE_UP_THS
5405 * @retval Interface status (MANDATORY: return 0 -> no Error).
5406 *
5407 */
ism330dhcx_wkup_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)5408 int32_t ism330dhcx_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
5409 {
5410 ism330dhcx_wake_up_ths_t wake_up_ths;
5411 int32_t ret;
5412
5413 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_WAKE_UP_THS,
5414 (uint8_t *)&wake_up_ths, 1);
5415
5416 if (ret == 0)
5417 {
5418 wake_up_ths.wk_ths = (uint8_t)val;
5419 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_WAKE_UP_THS,
5420 (uint8_t *)&wake_up_ths, 1);
5421 }
5422
5423 return ret;
5424 }
5425
5426 /**
5427 * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
5428 * WAKE_UP_DUR.[get]
5429 *
5430 * @param ctx Read / write interface definitions.(ptr)
5431 * @param val Change the values of wk_ths in reg WAKE_UP_THS
5432 * @retval Interface status (MANDATORY: return 0 -> no Error).
5433 *
5434 */
ism330dhcx_wkup_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)5435 int32_t ism330dhcx_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
5436 {
5437 ism330dhcx_wake_up_ths_t wake_up_ths;
5438 int32_t ret;
5439
5440 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_WAKE_UP_THS,
5441 (uint8_t *)&wake_up_ths, 1);
5442 *val = wake_up_ths.wk_ths;
5443
5444 return ret;
5445 }
5446
5447 /**
5448 * @brief Wake up duration event( 1LSb = 1 / ODR ).[set]
5449 *
5450 * @param ctx Read / write interface definitions.(ptr)
5451 * @param val Change the values of usr_off_on_wu in reg WAKE_UP_THS
5452 * @retval Interface status (MANDATORY: return 0 -> no Error).
5453 *
5454 */
ism330dhcx_xl_usr_offset_on_wkup_set(const stmdev_ctx_t * ctx,uint8_t val)5455 int32_t ism330dhcx_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx,
5456 uint8_t val)
5457 {
5458 ism330dhcx_wake_up_ths_t wake_up_ths;
5459 int32_t ret;
5460
5461 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_WAKE_UP_THS,
5462 (uint8_t *)&wake_up_ths, 1);
5463
5464 if (ret == 0)
5465 {
5466 wake_up_ths.usr_off_on_wu = (uint8_t)val;
5467 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_WAKE_UP_THS,
5468 (uint8_t *)&wake_up_ths, 1);
5469 }
5470
5471 return ret;
5472 }
5473
5474 /**
5475 * @brief Wake up duration event( 1LSb = 1 / ODR ).[get]
5476 *
5477 * @param ctx Read / write interface definitions.(ptr)
5478 * @param val Change the values of usr_off_on_wu in reg WAKE_UP_THS
5479 * @retval Interface status (MANDATORY: return 0 -> no Error).
5480 *
5481 */
ism330dhcx_xl_usr_offset_on_wkup_get(const stmdev_ctx_t * ctx,uint8_t * val)5482 int32_t ism330dhcx_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx,
5483 uint8_t *val)
5484 {
5485 ism330dhcx_wake_up_ths_t wake_up_ths;
5486 int32_t ret;
5487
5488 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_WAKE_UP_THS,
5489 (uint8_t *)&wake_up_ths, 1);
5490 *val = wake_up_ths.usr_off_on_wu;
5491
5492 return ret;
5493 }
5494
5495 /**
5496 * @brief Wake up duration event(1LSb = 1 / ODR).[set]
5497 *
5498 * @param ctx Read / write interface definitions.(ptr)
5499 * @param val Change the values of wake_dur in reg WAKE_UP_DUR
5500 * @retval Interface status (MANDATORY: return 0 -> no Error).
5501 *
5502 */
ism330dhcx_wkup_dur_set(const stmdev_ctx_t * ctx,uint8_t val)5503 int32_t ism330dhcx_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
5504 {
5505 ism330dhcx_wake_up_dur_t wake_up_dur;
5506 int32_t ret;
5507
5508 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_WAKE_UP_DUR,
5509 (uint8_t *)&wake_up_dur, 1);
5510
5511 if (ret == 0)
5512 {
5513 wake_up_dur.wake_dur = (uint8_t)val;
5514 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_WAKE_UP_DUR,
5515 (uint8_t *)&wake_up_dur, 1);
5516 }
5517
5518 return ret;
5519 }
5520
5521 /**
5522 * @brief Wake up duration event(1LSb = 1 / ODR).[get]
5523 *
5524 * @param ctx Read / write interface definitions.(ptr)
5525 * @param val Change the values of wake_dur in reg WAKE_UP_DUR
5526 * @retval Interface status (MANDATORY: return 0 -> no Error).
5527 *
5528 */
ism330dhcx_wkup_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)5529 int32_t ism330dhcx_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
5530 {
5531 ism330dhcx_wake_up_dur_t wake_up_dur;
5532 int32_t ret;
5533
5534 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_WAKE_UP_DUR,
5535 (uint8_t *)&wake_up_dur, 1);
5536 *val = wake_up_dur.wake_dur;
5537
5538 return ret;
5539 }
5540
5541 /**
5542 * @}
5543 *
5544 */
5545
5546 /**
5547 * @defgroup ISM330DHCX_ Activity/Inactivity_detection
5548 * @brief This section groups all the functions concerning
5549 * activity/inactivity detection.
5550 * @{
5551 *
5552 */
5553
5554 /**
5555 * @brief Enables gyroscope Sleep mode.[set]
5556 *
5557 * @param ctx Read / write interface definitions.(ptr)
5558 * @param val Change the values of sleep_g in reg CTRL4_C
5559 * @retval Interface status (MANDATORY: return 0 -> no Error).
5560 *
5561 */
ism330dhcx_gy_sleep_mode_set(const stmdev_ctx_t * ctx,uint8_t val)5562 int32_t ism330dhcx_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
5563 {
5564 ism330dhcx_ctrl4_c_t ctrl4_c;
5565 int32_t ret;
5566
5567 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL4_C,
5568 (uint8_t *)&ctrl4_c, 1);
5569
5570 if (ret == 0)
5571 {
5572 ctrl4_c.sleep_g = (uint8_t)val;
5573 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL4_C,
5574 (uint8_t *)&ctrl4_c, 1);
5575 }
5576
5577 return ret;
5578 }
5579
5580 /**
5581 * @brief Enables gyroscope Sleep mode.[get]
5582 *
5583 * @param ctx Read / write interface definitions.(ptr)
5584 * @param val Change the values of sleep_g in reg CTRL4_C
5585 * @retval Interface status (MANDATORY: return 0 -> no Error).
5586 *
5587 */
ism330dhcx_gy_sleep_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)5588 int32_t ism330dhcx_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
5589 {
5590 ism330dhcx_ctrl4_c_t ctrl4_c;
5591 int32_t ret;
5592
5593 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL4_C,
5594 (uint8_t *)&ctrl4_c, 1);
5595 *val = ctrl4_c.sleep_g;
5596
5597 return ret;
5598 }
5599
5600 /**
5601 * @brief Drives the sleep status instead of sleep change on INT pins
5602 * (only if INT1_SLEEP_CHANGE or INT2_SLEEP_CHANGE bits
5603 * are enabled).[set]
5604 *
5605 * @param ctx Read / write interface definitions.(ptr)
5606 * @param val Change the values of sleep_status_on_int in reg TAP_CFG0
5607 * @retval Interface status (MANDATORY: return 0 -> no Error).
5608 *
5609 */
ism330dhcx_act_pin_notification_set(const stmdev_ctx_t * ctx,ism330dhcx_sleep_status_on_int_t val)5610 int32_t ism330dhcx_act_pin_notification_set(const stmdev_ctx_t *ctx,
5611 ism330dhcx_sleep_status_on_int_t val)
5612 {
5613 ism330dhcx_tap_cfg0_t tap_cfg0;
5614 int32_t ret;
5615
5616 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG0,
5617 (uint8_t *)&tap_cfg0, 1);
5618
5619 if (ret == 0)
5620 {
5621 tap_cfg0. sleep_status_on_int = (uint8_t)val;
5622 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_TAP_CFG0,
5623 (uint8_t *)&tap_cfg0, 1);
5624 }
5625
5626 return ret;
5627 }
5628
5629 /**
5630 * @brief Drives the sleep status instead of sleep change on INT pins
5631 * (only if INT1_SLEEP_CHANGE or INT2_SLEEP_CHANGE bits
5632 * are enabled).[get]
5633 *
5634 * @param ctx Read / write interface definitions.(ptr)
5635 * @param val Get the values of sleep_status_on_int in reg TAP_CFG0
5636 * @retval Interface status (MANDATORY: return 0 -> no Error).
5637 *
5638 */
ism330dhcx_act_pin_notification_get(const stmdev_ctx_t * ctx,ism330dhcx_sleep_status_on_int_t * val)5639 int32_t ism330dhcx_act_pin_notification_get(const stmdev_ctx_t *ctx,
5640 ism330dhcx_sleep_status_on_int_t *val)
5641 {
5642 ism330dhcx_tap_cfg0_t tap_cfg0;
5643 int32_t ret;
5644
5645 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG0,
5646 (uint8_t *)&tap_cfg0, 1);
5647
5648 switch (tap_cfg0. sleep_status_on_int)
5649 {
5650 case ISM330DHCX_DRIVE_SLEEP_CHG_EVENT:
5651 *val = ISM330DHCX_DRIVE_SLEEP_CHG_EVENT;
5652 break;
5653
5654 case ISM330DHCX_DRIVE_SLEEP_STATUS:
5655 *val = ISM330DHCX_DRIVE_SLEEP_STATUS;
5656 break;
5657
5658 default:
5659 *val = ISM330DHCX_DRIVE_SLEEP_CHG_EVENT;
5660 break;
5661 }
5662
5663 return ret;
5664 }
5665
5666 /**
5667 * @brief Enable inactivity function.[set]
5668 *
5669 * @param ctx Read / write interface definitions.(ptr)
5670 * @param val Change the values of inact_en in reg TAP_CFG2
5671 * @retval Interface status (MANDATORY: return 0 -> no Error).
5672 *
5673 */
ism330dhcx_act_mode_set(const stmdev_ctx_t * ctx,ism330dhcx_inact_en_t val)5674 int32_t ism330dhcx_act_mode_set(const stmdev_ctx_t *ctx,
5675 ism330dhcx_inact_en_t val)
5676 {
5677 ism330dhcx_tap_cfg2_t tap_cfg2;
5678 int32_t ret;
5679
5680 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG2,
5681 (uint8_t *)&tap_cfg2, 1);
5682
5683 if (ret == 0)
5684 {
5685 tap_cfg2.inact_en = (uint8_t)val;
5686 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_TAP_CFG2,
5687 (uint8_t *)&tap_cfg2, 1);
5688 }
5689
5690 return ret;
5691 }
5692
5693 /**
5694 * @brief Enable inactivity function.[get]
5695 *
5696 * @param ctx Read / write interface definitions.(ptr)
5697 * @param val Get the values of inact_en in reg TAP_CFG2
5698 * @retval Interface status (MANDATORY: return 0 -> no Error).
5699 *
5700 */
ism330dhcx_act_mode_get(const stmdev_ctx_t * ctx,ism330dhcx_inact_en_t * val)5701 int32_t ism330dhcx_act_mode_get(const stmdev_ctx_t *ctx,
5702 ism330dhcx_inact_en_t *val)
5703 {
5704 ism330dhcx_tap_cfg2_t tap_cfg2;
5705 int32_t ret;
5706
5707 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG2,
5708 (uint8_t *)&tap_cfg2, 1);
5709
5710 switch (tap_cfg2.inact_en)
5711 {
5712 case ISM330DHCX_XL_AND_GY_NOT_AFFECTED:
5713 *val = ISM330DHCX_XL_AND_GY_NOT_AFFECTED;
5714 break;
5715
5716 case ISM330DHCX_XL_12Hz5_GY_NOT_AFFECTED:
5717 *val = ISM330DHCX_XL_12Hz5_GY_NOT_AFFECTED;
5718 break;
5719
5720 case ISM330DHCX_XL_12Hz5_GY_SLEEP:
5721 *val = ISM330DHCX_XL_12Hz5_GY_SLEEP;
5722 break;
5723
5724 case ISM330DHCX_XL_12Hz5_GY_PD:
5725 *val = ISM330DHCX_XL_12Hz5_GY_PD;
5726 break;
5727
5728 default:
5729 *val = ISM330DHCX_XL_AND_GY_NOT_AFFECTED;
5730 break;
5731 }
5732
5733 return ret;
5734 }
5735
5736 /**
5737 * @brief Duration to go in sleep mode (1 LSb = 512 / ODR).[set]
5738 *
5739 * @param ctx Read / write interface definitions.(ptr)
5740 * @param val Change the values of sleep_dur in reg WAKE_UP_DUR
5741 * @retval Interface status (MANDATORY: return 0 -> no Error).
5742 *
5743 */
ism330dhcx_act_sleep_dur_set(const stmdev_ctx_t * ctx,uint8_t val)5744 int32_t ism330dhcx_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
5745 {
5746 ism330dhcx_wake_up_dur_t wake_up_dur;
5747 int32_t ret;
5748
5749 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_WAKE_UP_DUR,
5750 (uint8_t *)&wake_up_dur, 1);
5751
5752 if (ret == 0)
5753 {
5754 wake_up_dur.sleep_dur = (uint8_t)val;
5755 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_WAKE_UP_DUR,
5756 (uint8_t *)&wake_up_dur, 1);
5757 }
5758
5759 return ret;
5760 }
5761
5762 /**
5763 * @brief Duration to go in sleep mode.(1 LSb = 512 / ODR).[get]
5764 *
5765 * @param ctx Read / write interface definitions.(ptr)
5766 * @param val Change the values of sleep_dur in reg WAKE_UP_DUR
5767 * @retval Interface status (MANDATORY: return 0 -> no Error).
5768 *
5769 */
ism330dhcx_act_sleep_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)5770 int32_t ism330dhcx_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
5771 {
5772 ism330dhcx_wake_up_dur_t wake_up_dur;
5773 int32_t ret;
5774
5775 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_WAKE_UP_DUR,
5776 (uint8_t *)&wake_up_dur, 1);
5777 *val = wake_up_dur.sleep_dur;
5778
5779 return ret;
5780 }
5781
5782 /**
5783 * @}
5784 *
5785 */
5786
5787 /**
5788 * @defgroup ISM330DHCX_tap_generator
5789 * @brief This section groups all the functions that manage the
5790 * tap and double tap event generation.
5791 * @{
5792 *
5793 */
5794
5795 /**
5796 * @brief Enable Z direction in tap recognition.[set]
5797 *
5798 * @param ctx Read / write interface definitions.(ptr)
5799 * @param val Change the values of tap_z_en in reg TAP_CFG0
5800 * @retval Interface status (MANDATORY: return 0 -> no Error).
5801 *
5802 */
ism330dhcx_tap_detection_on_z_set(const stmdev_ctx_t * ctx,uint8_t val)5803 int32_t ism330dhcx_tap_detection_on_z_set(const stmdev_ctx_t *ctx,
5804 uint8_t val)
5805 {
5806 ism330dhcx_tap_cfg0_t tap_cfg0;
5807 int32_t ret;
5808
5809 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG0,
5810 (uint8_t *)&tap_cfg0, 1);
5811
5812 if (ret == 0)
5813 {
5814 tap_cfg0.tap_z_en = (uint8_t)val;
5815 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_TAP_CFG0,
5816 (uint8_t *)&tap_cfg0, 1);
5817 }
5818
5819 return ret;
5820 }
5821
5822 /**
5823 * @brief Enable Z direction in tap recognition.[get]
5824 *
5825 * @param ctx Read / write interface definitions.(ptr)
5826 * @param val Change the values of tap_z_en in reg TAP_CFG0
5827 * @retval Interface status (MANDATORY: return 0 -> no Error).
5828 *
5829 */
ism330dhcx_tap_detection_on_z_get(const stmdev_ctx_t * ctx,uint8_t * val)5830 int32_t ism330dhcx_tap_detection_on_z_get(const stmdev_ctx_t *ctx,
5831 uint8_t *val)
5832 {
5833 ism330dhcx_tap_cfg0_t tap_cfg0;
5834 int32_t ret;
5835
5836 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG0,
5837 (uint8_t *)&tap_cfg0, 1);
5838 *val = tap_cfg0.tap_z_en;
5839
5840 return ret;
5841 }
5842
5843 /**
5844 * @brief Enable Y direction in tap recognition.[set]
5845 *
5846 * @param ctx Read / write interface definitions.(ptr)
5847 * @param val Change the values of tap_y_en in reg TAP_CFG0
5848 * @retval Interface status (MANDATORY: return 0 -> no Error).
5849 *
5850 */
ism330dhcx_tap_detection_on_y_set(const stmdev_ctx_t * ctx,uint8_t val)5851 int32_t ism330dhcx_tap_detection_on_y_set(const stmdev_ctx_t *ctx,
5852 uint8_t val)
5853 {
5854 ism330dhcx_tap_cfg0_t tap_cfg0;
5855 int32_t ret;
5856
5857 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG0,
5858 (uint8_t *)&tap_cfg0, 1);
5859
5860 if (ret == 0)
5861 {
5862 tap_cfg0.tap_y_en = (uint8_t)val;
5863 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_TAP_CFG0,
5864 (uint8_t *)&tap_cfg0, 1);
5865 }
5866
5867 return ret;
5868 }
5869
5870 /**
5871 * @brief Enable Y direction in tap recognition.[get]
5872 *
5873 * @param ctx Read / write interface definitions.(ptr)
5874 * @param val Change the values of tap_y_en in reg TAP_CFG0
5875 * @retval Interface status (MANDATORY: return 0 -> no Error).
5876 *
5877 */
ism330dhcx_tap_detection_on_y_get(const stmdev_ctx_t * ctx,uint8_t * val)5878 int32_t ism330dhcx_tap_detection_on_y_get(const stmdev_ctx_t *ctx,
5879 uint8_t *val)
5880 {
5881 ism330dhcx_tap_cfg0_t tap_cfg0;
5882 int32_t ret;
5883
5884 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG0,
5885 (uint8_t *)&tap_cfg0, 1);
5886 *val = tap_cfg0.tap_y_en;
5887
5888 return ret;
5889 }
5890
5891 /**
5892 * @brief Enable X direction in tap recognition.[set]
5893 *
5894 * @param ctx Read / write interface definitions.(ptr)
5895 * @param val Change the values of tap_x_en in reg TAP_CFG0
5896 * @retval Interface status (MANDATORY: return 0 -> no Error).
5897 *
5898 */
ism330dhcx_tap_detection_on_x_set(const stmdev_ctx_t * ctx,uint8_t val)5899 int32_t ism330dhcx_tap_detection_on_x_set(const stmdev_ctx_t *ctx,
5900 uint8_t val)
5901 {
5902 ism330dhcx_tap_cfg0_t tap_cfg0;
5903 int32_t ret;
5904
5905 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG0,
5906 (uint8_t *)&tap_cfg0, 1);
5907
5908 if (ret == 0)
5909 {
5910 tap_cfg0.tap_x_en = (uint8_t)val;
5911 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_TAP_CFG0,
5912 (uint8_t *)&tap_cfg0, 1);
5913 }
5914
5915 return ret;
5916 }
5917
5918 /**
5919 * @brief Enable X direction in tap recognition.[get]
5920 *
5921 * @param ctx Read / write interface definitions.(ptr)
5922 * @param val Change the values of tap_x_en in reg TAP_CFG0
5923 * @retval Interface status (MANDATORY: return 0 -> no Error).
5924 *
5925 */
ism330dhcx_tap_detection_on_x_get(const stmdev_ctx_t * ctx,uint8_t * val)5926 int32_t ism330dhcx_tap_detection_on_x_get(const stmdev_ctx_t *ctx,
5927 uint8_t *val)
5928 {
5929 ism330dhcx_tap_cfg0_t tap_cfg0;
5930 int32_t ret;
5931
5932 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG0,
5933 (uint8_t *)&tap_cfg0, 1);
5934 *val = tap_cfg0.tap_x_en;
5935
5936 return ret;
5937 }
5938
5939 /**
5940 * @brief X-axis tap recognition threshold.[set]
5941 *
5942 * @param ctx Read / write interface definitions.(ptr)
5943 * @param val Change the values of tap_ths_x in reg TAP_CFG1
5944 * @retval Interface status (MANDATORY: return 0 -> no Error).
5945 *
5946 */
ism330dhcx_tap_threshold_x_set(const stmdev_ctx_t * ctx,uint8_t val)5947 int32_t ism330dhcx_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val)
5948 {
5949 ism330dhcx_tap_cfg1_t tap_cfg1;
5950 int32_t ret;
5951
5952 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG1,
5953 (uint8_t *)&tap_cfg1, 1);
5954
5955 if (ret == 0)
5956 {
5957 tap_cfg1.tap_ths_x = (uint8_t)val;
5958 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_TAP_CFG1,
5959 (uint8_t *)&tap_cfg1, 1);
5960 }
5961
5962 return ret;
5963 }
5964
5965 /**
5966 * @brief X-axis tap recognition threshold.[get]
5967 *
5968 * @param ctx Read / write interface definitions.(ptr)
5969 * @param val Change the values of tap_ths_x in reg TAP_CFG1
5970 * @retval Interface status (MANDATORY: return 0 -> no Error).
5971 *
5972 */
ism330dhcx_tap_threshold_x_get(const stmdev_ctx_t * ctx,uint8_t * val)5973 int32_t ism330dhcx_tap_threshold_x_get(const stmdev_ctx_t *ctx,
5974 uint8_t *val)
5975 {
5976 ism330dhcx_tap_cfg1_t tap_cfg1;
5977 int32_t ret;
5978
5979 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG1,
5980 (uint8_t *)&tap_cfg1, 1);
5981 *val = tap_cfg1.tap_ths_x;
5982
5983 return ret;
5984 }
5985
5986 /**
5987 * @brief Selection of axis priority for TAP detection.[set]
5988 *
5989 * @param ctx Read / write interface definitions.(ptr)
5990 * @param val Change the values of tap_priority in reg TAP_CFG1
5991 * @retval Interface status (MANDATORY: return 0 -> no Error).
5992 *
5993 */
ism330dhcx_tap_axis_priority_set(const stmdev_ctx_t * ctx,ism330dhcx_tap_priority_t val)5994 int32_t ism330dhcx_tap_axis_priority_set(const stmdev_ctx_t *ctx,
5995 ism330dhcx_tap_priority_t val)
5996 {
5997 ism330dhcx_tap_cfg1_t tap_cfg1;
5998 int32_t ret;
5999
6000 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG1,
6001 (uint8_t *)&tap_cfg1, 1);
6002
6003 if (ret == 0)
6004 {
6005 tap_cfg1.tap_priority = (uint8_t)val;
6006 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_TAP_CFG1,
6007 (uint8_t *)&tap_cfg1, 1);
6008 }
6009
6010 return ret;
6011 }
6012
6013 /**
6014 * @brief Selection of axis priority for TAP detection[get]
6015 *
6016 * @param ctx Read / write interface definitions.(ptr)
6017 * @param val Get the values of tap_priority in reg TAP_CFG1
6018 * @retval Interface status (MANDATORY: return 0 -> no Error).
6019 *
6020 */
ism330dhcx_tap_axis_priority_get(const stmdev_ctx_t * ctx,ism330dhcx_tap_priority_t * val)6021 int32_t ism330dhcx_tap_axis_priority_get(const stmdev_ctx_t *ctx,
6022 ism330dhcx_tap_priority_t *val)
6023 {
6024 ism330dhcx_tap_cfg1_t tap_cfg1;
6025 int32_t ret;
6026
6027 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG1,
6028 (uint8_t *)&tap_cfg1, 1);
6029
6030 switch (tap_cfg1.tap_priority)
6031 {
6032 case ISM330DHCX_XYZ:
6033 *val = ISM330DHCX_XYZ;
6034 break;
6035
6036 case ISM330DHCX_YXZ:
6037 *val = ISM330DHCX_YXZ;
6038 break;
6039
6040 case ISM330DHCX_XZY:
6041 *val = ISM330DHCX_XZY;
6042 break;
6043
6044 case ISM330DHCX_ZYX:
6045 *val = ISM330DHCX_ZYX;
6046 break;
6047
6048 case ISM330DHCX_YZX:
6049 *val = ISM330DHCX_YZX;
6050 break;
6051
6052 case ISM330DHCX_ZXY:
6053 *val = ISM330DHCX_ZXY;
6054 break;
6055
6056 default:
6057 *val = ISM330DHCX_XYZ;
6058 break;
6059 }
6060
6061 return ret;
6062 }
6063
6064 /**
6065 * @brief Y-axis tap recognition threshold.[set]
6066 *
6067 * @param ctx Read / write interface definitions.(ptr)
6068 * @param val Change the values of tap_ths_y in reg TAP_CFG2
6069 * @retval Interface status (MANDATORY: return 0 -> no Error).
6070 *
6071 */
ism330dhcx_tap_threshold_y_set(const stmdev_ctx_t * ctx,uint8_t val)6072 int32_t ism330dhcx_tap_threshold_y_set(const stmdev_ctx_t *ctx, uint8_t val)
6073 {
6074 ism330dhcx_tap_cfg2_t tap_cfg2;
6075 int32_t ret;
6076
6077 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG2,
6078 (uint8_t *)&tap_cfg2, 1);
6079
6080 if (ret == 0)
6081 {
6082 tap_cfg2.tap_ths_y = (uint8_t)val;
6083 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_TAP_CFG2,
6084 (uint8_t *)&tap_cfg2, 1);
6085 }
6086
6087 return ret;
6088 }
6089
6090 /**
6091 * @brief Y-axis tap recognition threshold.[get]
6092 *
6093 * @param ctx Read / write interface definitions.(ptr)
6094 * @param val Change the values of tap_ths_y in reg TAP_CFG2
6095 * @retval Interface status (MANDATORY: return 0 -> no Error).
6096 *
6097 */
ism330dhcx_tap_threshold_y_get(const stmdev_ctx_t * ctx,uint8_t * val)6098 int32_t ism330dhcx_tap_threshold_y_get(const stmdev_ctx_t *ctx,
6099 uint8_t *val)
6100 {
6101 ism330dhcx_tap_cfg2_t tap_cfg2;
6102 int32_t ret;
6103
6104 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG2,
6105 (uint8_t *)&tap_cfg2, 1);
6106 *val = tap_cfg2.tap_ths_y;
6107
6108 return ret;
6109 }
6110
6111 /**
6112 * @brief Z-axis recognition threshold.[set]
6113 *
6114 * @param ctx Read / write interface definitions.(ptr)
6115 * @param val Change the values of tap_ths_z in reg TAP_THS_6D
6116 * @retval Interface status (MANDATORY: return 0 -> no Error).
6117 *
6118 */
ism330dhcx_tap_threshold_z_set(const stmdev_ctx_t * ctx,uint8_t val)6119 int32_t ism330dhcx_tap_threshold_z_set(const stmdev_ctx_t *ctx, uint8_t val)
6120 {
6121 ism330dhcx_tap_ths_6d_t tap_ths_6d;
6122 int32_t ret;
6123
6124 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_THS_6D,
6125 (uint8_t *)&tap_ths_6d, 1);
6126
6127 if (ret == 0)
6128 {
6129 tap_ths_6d.tap_ths_z = (uint8_t)val;
6130 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_TAP_THS_6D,
6131 (uint8_t *)&tap_ths_6d, 1);
6132 }
6133
6134 return ret;
6135 }
6136
6137 /**
6138 * @brief Z-axis recognition threshold.[get]
6139 *
6140 * @param ctx Read / write interface definitions.(ptr)
6141 * @param val Change the values of tap_ths_z in reg TAP_THS_6D
6142 * @retval Interface status (MANDATORY: return 0 -> no Error).
6143 *
6144 */
ism330dhcx_tap_threshold_z_get(const stmdev_ctx_t * ctx,uint8_t * val)6145 int32_t ism330dhcx_tap_threshold_z_get(const stmdev_ctx_t *ctx,
6146 uint8_t *val)
6147 {
6148 ism330dhcx_tap_ths_6d_t tap_ths_6d;
6149 int32_t ret;
6150
6151 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_THS_6D,
6152 (uint8_t *)&tap_ths_6d, 1);
6153 *val = tap_ths_6d.tap_ths_z;
6154
6155 return ret;
6156 }
6157
6158 /**
6159 * @brief Maximum duration is the maximum time of an overthreshold signal
6160 * detection to be recognized as a tap event. The default value of
6161 * these bits is 00b which corresponds to 4*ODR_XL time.
6162 * If the SHOCK[1:0] bits are set to a different value, 1LSB
6163 * corresponds to 8*ODR_XL time.[set]
6164 *
6165 * @param ctx Read / write interface definitions.(ptr)
6166 * @param val Change the values of shock in reg INT_DUR2
6167 * @retval Interface status (MANDATORY: return 0 -> no Error).
6168 *
6169 */
ism330dhcx_tap_shock_set(const stmdev_ctx_t * ctx,uint8_t val)6170 int32_t ism330dhcx_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val)
6171 {
6172 ism330dhcx_int_dur2_t int_dur2;
6173 int32_t ret;
6174
6175 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_DUR2,
6176 (uint8_t *)&int_dur2, 1);
6177
6178 if (ret == 0)
6179 {
6180 int_dur2.shock = (uint8_t)val;
6181 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_INT_DUR2,
6182 (uint8_t *)&int_dur2, 1);
6183 }
6184
6185 return ret;
6186 }
6187
6188 /**
6189 * @brief Maximum duration is the maximum time of an overthreshold signal
6190 * detection to be recognized as a tap event. The default value of
6191 * these bits is 00b which corresponds to 4*ODR_XL time.
6192 * If the SHOCK[1:0] bits are set to a different value, 1LSB
6193 * corresponds to 8*ODR_XL time.[get]
6194 *
6195 * @param ctx Read / write interface definitions.(ptr)
6196 * @param val Change the values of shock in reg INT_DUR2
6197 * @retval Interface status (MANDATORY: return 0 -> no Error).
6198 *
6199 */
ism330dhcx_tap_shock_get(const stmdev_ctx_t * ctx,uint8_t * val)6200 int32_t ism330dhcx_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val)
6201 {
6202 ism330dhcx_int_dur2_t int_dur2;
6203 int32_t ret;
6204
6205 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_DUR2,
6206 (uint8_t *)&int_dur2, 1);
6207 *val = int_dur2.shock;
6208
6209 return ret;
6210 }
6211
6212 /**
6213 * @brief Quiet time is the time after the first detected tap in which
6214 * there must not be any overthreshold event.
6215 * The default value of these bits is 00b which corresponds to
6216 * 2*ODR_XL time. If the QUIET[1:0] bits are set to a different
6217 * value, 1LSB corresponds to 4*ODR_XL time.[set]
6218 *
6219 * @param ctx Read / write interface definitions.(ptr)
6220 * @param val Change the values of quiet in reg INT_DUR2
6221 * @retval Interface status (MANDATORY: return 0 -> no Error).
6222 *
6223 */
ism330dhcx_tap_quiet_set(const stmdev_ctx_t * ctx,uint8_t val)6224 int32_t ism330dhcx_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val)
6225 {
6226 ism330dhcx_int_dur2_t int_dur2;
6227 int32_t ret;
6228
6229 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_DUR2,
6230 (uint8_t *)&int_dur2, 1);
6231
6232 if (ret == 0)
6233 {
6234 int_dur2.quiet = (uint8_t)val;
6235 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_INT_DUR2,
6236 (uint8_t *)&int_dur2, 1);
6237 }
6238
6239 return ret;
6240 }
6241
6242 /**
6243 * @brief Quiet time is the time after the first detected tap in which
6244 * there must not be any overthreshold event.
6245 * The default value of these bits is 00b which corresponds to
6246 * 2*ODR_XL time. If the QUIET[1:0] bits are set to a different
6247 * value, 1LSB corresponds to 4*ODR_XL time.[get]
6248 *
6249 * @param ctx Read / write interface definitions.(ptr)
6250 * @param val Change the values of quiet in reg INT_DUR2
6251 * @retval Interface status (MANDATORY: return 0 -> no Error).
6252 *
6253 */
ism330dhcx_tap_quiet_get(const stmdev_ctx_t * ctx,uint8_t * val)6254 int32_t ism330dhcx_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val)
6255 {
6256 ism330dhcx_int_dur2_t int_dur2;
6257 int32_t ret;
6258
6259 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_DUR2,
6260 (uint8_t *)&int_dur2, 1);
6261 *val = int_dur2.quiet;
6262
6263 return ret;
6264 }
6265
6266 /**
6267 * @brief When double tap recognition is enabled, this register expresses
6268 * the maximum time between two consecutive detected taps to
6269 * determine a double tap event.
6270 * The default value of these bits is 0000b which corresponds to
6271 * 16*ODR_XL time.
6272 * If the DUR[3:0] bits are set to a different value, 1LSB
6273 * corresponds to 32*ODR_XL time.[set]
6274 *
6275 * @param ctx Read / write interface definitions.(ptr)
6276 * @param val Change the values of dur in reg INT_DUR2
6277 * @retval Interface status (MANDATORY: return 0 -> no Error).
6278 *
6279 */
ism330dhcx_tap_dur_set(const stmdev_ctx_t * ctx,uint8_t val)6280 int32_t ism330dhcx_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
6281 {
6282 ism330dhcx_int_dur2_t int_dur2;
6283 int32_t ret;
6284
6285 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_DUR2,
6286 (uint8_t *)&int_dur2, 1);
6287
6288 if (ret == 0)
6289 {
6290 int_dur2.dur = (uint8_t)val;
6291 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_INT_DUR2,
6292 (uint8_t *)&int_dur2, 1);
6293 }
6294
6295 return ret;
6296 }
6297
6298 /**
6299 * @brief When double tap recognition is enabled, this register expresses the
6300 * maximum time between two consecutive detected taps to determine
6301 * a double tap event. The default value of these bits is 0000b which
6302 * corresponds to 16*ODR_XL time. If the DUR[3:0] bits are set to
6303 * a different value, 1LSB corresponds to 32*ODR_XL time.[get]
6304 *
6305 * @param ctx Read / write interface definitions.(ptr)
6306 * @param val Change the values of dur in reg INT_DUR2
6307 * @retval Interface status (MANDATORY: return 0 -> no Error).
6308 *
6309 */
ism330dhcx_tap_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)6310 int32_t ism330dhcx_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
6311 {
6312 ism330dhcx_int_dur2_t int_dur2;
6313 int32_t ret;
6314
6315 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_DUR2,
6316 (uint8_t *)&int_dur2, 1);
6317 *val = int_dur2.dur;
6318
6319 return ret;
6320 }
6321
6322 /**
6323 * @brief Single/double-tap event enable.[set]
6324 *
6325 * @param ctx Read / write interface definitions.(ptr)
6326 * @param val Change the values of single_double_tap in reg WAKE_UP_THS
6327 * @retval Interface status (MANDATORY: return 0 -> no Error).
6328 *
6329 */
ism330dhcx_tap_mode_set(const stmdev_ctx_t * ctx,ism330dhcx_single_double_tap_t val)6330 int32_t ism330dhcx_tap_mode_set(const stmdev_ctx_t *ctx,
6331 ism330dhcx_single_double_tap_t val)
6332 {
6333 ism330dhcx_wake_up_ths_t wake_up_ths;
6334 int32_t ret;
6335
6336 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_WAKE_UP_THS,
6337 (uint8_t *)&wake_up_ths, 1);
6338
6339 if (ret == 0)
6340 {
6341 wake_up_ths.single_double_tap = (uint8_t)val;
6342 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_WAKE_UP_THS,
6343 (uint8_t *)&wake_up_ths, 1);
6344 }
6345
6346 return ret;
6347 }
6348
6349 /**
6350 * @brief Single/double-tap event enable.[get]
6351 *
6352 * @param ctx Read / write interface definitions.(ptr)
6353 * @param val Get the values of single_double_tap in reg WAKE_UP_THS
6354 * @retval Interface status (MANDATORY: return 0 -> no Error).
6355 *
6356 */
ism330dhcx_tap_mode_get(const stmdev_ctx_t * ctx,ism330dhcx_single_double_tap_t * val)6357 int32_t ism330dhcx_tap_mode_get(const stmdev_ctx_t *ctx,
6358 ism330dhcx_single_double_tap_t *val)
6359 {
6360 ism330dhcx_wake_up_ths_t wake_up_ths;
6361 int32_t ret;
6362
6363 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_WAKE_UP_THS,
6364 (uint8_t *)&wake_up_ths, 1);
6365
6366 switch (wake_up_ths.single_double_tap)
6367 {
6368 case ISM330DHCX_ONLY_SINGLE:
6369 *val = ISM330DHCX_ONLY_SINGLE;
6370 break;
6371
6372 case ISM330DHCX_BOTH_SINGLE_DOUBLE:
6373 *val = ISM330DHCX_BOTH_SINGLE_DOUBLE;
6374 break;
6375
6376 default:
6377 *val = ISM330DHCX_ONLY_SINGLE;
6378 break;
6379 }
6380
6381 return ret;
6382 }
6383
6384 /**
6385 * @}
6386 *
6387 */
6388
6389 /**
6390 * @defgroup ISM330DHCX_ Six_position_detection(6D/4D)
6391 * @brief This section groups all the functions concerning six
6392 * position detection (6D).
6393 * @{
6394 *
6395 */
6396
6397 /**
6398 * @brief Threshold for 4D/6D function.[set]
6399 *
6400 * @param ctx Read / write interface definitions.(ptr)
6401 * @param val Change the values of sixd_ths in reg TAP_THS_6D
6402 * @retval Interface status (MANDATORY: return 0 -> no Error).
6403 *
6404 */
ism330dhcx_6d_threshold_set(const stmdev_ctx_t * ctx,ism330dhcx_sixd_ths_t val)6405 int32_t ism330dhcx_6d_threshold_set(const stmdev_ctx_t *ctx,
6406 ism330dhcx_sixd_ths_t val)
6407 {
6408 ism330dhcx_tap_ths_6d_t tap_ths_6d;
6409 int32_t ret;
6410
6411 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_THS_6D,
6412 (uint8_t *)&tap_ths_6d, 1);
6413
6414 if (ret == 0)
6415 {
6416 tap_ths_6d.sixd_ths = (uint8_t)val;
6417 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_TAP_THS_6D,
6418 (uint8_t *)&tap_ths_6d, 1);
6419 }
6420
6421 return ret;
6422 }
6423
6424 /**
6425 * @brief Threshold for 4D/6D function.[get]
6426 *
6427 * @param ctx Read / write interface definitions.(ptr)
6428 * @param val Get the values of sixd_ths in reg TAP_THS_6D
6429 * @retval Interface status (MANDATORY: return 0 -> no Error).
6430 *
6431 */
ism330dhcx_6d_threshold_get(const stmdev_ctx_t * ctx,ism330dhcx_sixd_ths_t * val)6432 int32_t ism330dhcx_6d_threshold_get(const stmdev_ctx_t *ctx,
6433 ism330dhcx_sixd_ths_t *val)
6434 {
6435 ism330dhcx_tap_ths_6d_t tap_ths_6d;
6436 int32_t ret;
6437
6438 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_THS_6D,
6439 (uint8_t *)&tap_ths_6d, 1);
6440
6441 switch (tap_ths_6d.sixd_ths)
6442 {
6443 case ISM330DHCX_DEG_80:
6444 *val = ISM330DHCX_DEG_80;
6445 break;
6446
6447 case ISM330DHCX_DEG_70:
6448 *val = ISM330DHCX_DEG_70;
6449 break;
6450
6451 case ISM330DHCX_DEG_60:
6452 *val = ISM330DHCX_DEG_60;
6453 break;
6454
6455 case ISM330DHCX_DEG_50:
6456 *val = ISM330DHCX_DEG_50;
6457 break;
6458
6459 default:
6460 *val = ISM330DHCX_DEG_80;
6461 break;
6462 }
6463
6464 return ret;
6465 }
6466
6467 /**
6468 * @brief 4D orientation detection enable.[set]
6469 *
6470 * @param ctx Read / write interface definitions.(ptr)
6471 * @param val Change the values of d4d_en in reg TAP_THS_6D
6472 * @retval Interface status (MANDATORY: return 0 -> no Error).
6473 *
6474 */
ism330dhcx_4d_mode_set(const stmdev_ctx_t * ctx,uint8_t val)6475 int32_t ism330dhcx_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
6476 {
6477 ism330dhcx_tap_ths_6d_t tap_ths_6d;
6478 int32_t ret;
6479
6480 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_THS_6D,
6481 (uint8_t *)&tap_ths_6d, 1);
6482
6483 if (ret == 0)
6484 {
6485 tap_ths_6d.d4d_en = (uint8_t)val;
6486 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_TAP_THS_6D,
6487 (uint8_t *)&tap_ths_6d, 1);
6488 }
6489
6490 return ret;
6491 }
6492
6493 /**
6494 * @brief 4D orientation detection enable.[get]
6495 *
6496 * @param ctx Read / write interface definitions.(ptr)
6497 * @param val Change the values of d4d_en in reg TAP_THS_6D
6498 * @retval Interface status (MANDATORY: return 0 -> no Error).
6499 *
6500 */
ism330dhcx_4d_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)6501 int32_t ism330dhcx_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
6502 {
6503 ism330dhcx_tap_ths_6d_t tap_ths_6d;
6504 int32_t ret;
6505
6506 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_THS_6D,
6507 (uint8_t *)&tap_ths_6d, 1);
6508 *val = tap_ths_6d.d4d_en;
6509
6510 return ret;
6511 }
6512
6513 /**
6514 * @}
6515 *
6516 */
6517
6518 /**
6519 * @defgroup ISM330DHCX_free_fall
6520 * @brief This section group all the functions concerning the free
6521 * fall detection.
6522 * @{
6523 *
6524 */
6525
6526 /**
6527 * @brief Free fall threshold setting.[set]
6528 *
6529 * @param ctx Read / write interface definitions.(ptr)
6530 * @param val Change the values of ff_ths in reg FREE_FALL
6531 * @retval Interface status (MANDATORY: return 0 -> no Error).
6532 *
6533 */
ism330dhcx_ff_threshold_set(const stmdev_ctx_t * ctx,ism330dhcx_ff_ths_t val)6534 int32_t ism330dhcx_ff_threshold_set(const stmdev_ctx_t *ctx,
6535 ism330dhcx_ff_ths_t val)
6536 {
6537 ism330dhcx_free_fall_t free_fall;
6538 int32_t ret;
6539
6540 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FREE_FALL,
6541 (uint8_t *)&free_fall, 1);
6542
6543 if (ret == 0)
6544 {
6545 free_fall.ff_ths = (uint8_t)val;
6546 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_FREE_FALL,
6547 (uint8_t *)&free_fall, 1);
6548 }
6549
6550 return ret;
6551 }
6552
6553 /**
6554 * @brief Free fall threshold setting.[get]
6555 *
6556 * @param ctx Read / write interface definitions.(ptr)
6557 * @param val Get the values of ff_ths in reg FREE_FALL
6558 * @retval Interface status (MANDATORY: return 0 -> no Error).
6559 *
6560 */
ism330dhcx_ff_threshold_get(const stmdev_ctx_t * ctx,ism330dhcx_ff_ths_t * val)6561 int32_t ism330dhcx_ff_threshold_get(const stmdev_ctx_t *ctx,
6562 ism330dhcx_ff_ths_t *val)
6563 {
6564 ism330dhcx_free_fall_t free_fall;
6565 int32_t ret;
6566
6567 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FREE_FALL,
6568 (uint8_t *)&free_fall, 1);
6569
6570 switch (free_fall.ff_ths)
6571 {
6572 case ISM330DHCX_FF_TSH_156mg:
6573 *val = ISM330DHCX_FF_TSH_156mg;
6574 break;
6575
6576 case ISM330DHCX_FF_TSH_219mg:
6577 *val = ISM330DHCX_FF_TSH_219mg;
6578 break;
6579
6580 case ISM330DHCX_FF_TSH_250mg:
6581 *val = ISM330DHCX_FF_TSH_250mg;
6582 break;
6583
6584 case ISM330DHCX_FF_TSH_312mg:
6585 *val = ISM330DHCX_FF_TSH_312mg;
6586 break;
6587
6588 case ISM330DHCX_FF_TSH_344mg:
6589 *val = ISM330DHCX_FF_TSH_344mg;
6590 break;
6591
6592 case ISM330DHCX_FF_TSH_406mg:
6593 *val = ISM330DHCX_FF_TSH_406mg;
6594 break;
6595
6596 case ISM330DHCX_FF_TSH_469mg:
6597 *val = ISM330DHCX_FF_TSH_469mg;
6598 break;
6599
6600 case ISM330DHCX_FF_TSH_500mg:
6601 *val = ISM330DHCX_FF_TSH_500mg;
6602 break;
6603
6604 default:
6605 *val = ISM330DHCX_FF_TSH_156mg;
6606 break;
6607 }
6608
6609 return ret;
6610 }
6611
6612 /**
6613 * @brief Free-fall duration event(1LSb = 1 / ODR).[set]
6614 *
6615 * @param ctx Read / write interface definitions.(ptr)
6616 * @param val Change the values of ff_dur in reg FREE_FALL
6617 * @retval Interface status (MANDATORY: return 0 -> no Error).
6618 *
6619 */
ism330dhcx_ff_dur_set(const stmdev_ctx_t * ctx,uint8_t val)6620 int32_t ism330dhcx_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
6621 {
6622 ism330dhcx_wake_up_dur_t wake_up_dur;
6623 ism330dhcx_free_fall_t free_fall;
6624 int32_t ret;
6625
6626 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_WAKE_UP_DUR,
6627 (uint8_t *)&wake_up_dur, 1);
6628
6629 if (ret == 0)
6630 {
6631 wake_up_dur.ff_dur = (val & 0x20U) >> 5;
6632 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_WAKE_UP_DUR,
6633 (uint8_t *)&wake_up_dur, 1);
6634 }
6635
6636 if (ret == 0)
6637 {
6638 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FREE_FALL,
6639 (uint8_t *)&free_fall, 1);
6640 }
6641
6642 if (ret == 0)
6643 {
6644 free_fall.ff_dur = val & 0x1FU;
6645 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_FREE_FALL,
6646 (uint8_t *)&free_fall, 1);
6647 }
6648
6649 return ret;
6650 }
6651
6652 /**
6653 * @brief Free-fall duration event(1LSb = 1 / ODR).[get]
6654 *
6655 * @param ctx Read / write interface definitions.(ptr)
6656 * @param val Change the values of ff_dur in reg FREE_FALL
6657 * @retval Interface status (MANDATORY: return 0 -> no Error).
6658 *
6659 */
ism330dhcx_ff_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)6660 int32_t ism330dhcx_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
6661 {
6662 ism330dhcx_wake_up_dur_t wake_up_dur;
6663 ism330dhcx_free_fall_t free_fall;
6664 int32_t ret;
6665
6666 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_WAKE_UP_DUR,
6667 (uint8_t *)&wake_up_dur, 1);
6668
6669 if (ret == 0)
6670 {
6671 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FREE_FALL,
6672 (uint8_t *)&free_fall, 1);
6673 }
6674
6675 *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
6676
6677 return ret;
6678 }
6679
6680 /**
6681 * @}
6682 *
6683 */
6684
6685 /**
6686 * @defgroup ISM330DHCX_fifo
6687 * @brief This section group all the functions concerning
6688 * the fifo usage
6689 * @{
6690 *
6691 */
6692
6693 /**
6694 * @brief FIFO watermark level selection.[set]
6695 *
6696 * @param ctx Read / write interface definitions.(ptr)
6697 * @param val Change the values of wtm in reg FIFO_CTRL1
6698 * @retval Interface status (MANDATORY: return 0 -> no Error).
6699 *
6700 */
ism330dhcx_fifo_watermark_set(const stmdev_ctx_t * ctx,uint16_t val)6701 int32_t ism330dhcx_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val)
6702 {
6703 ism330dhcx_fifo_ctrl1_t fifo_ctrl1;
6704 ism330dhcx_fifo_ctrl2_t fifo_ctrl2;
6705 int32_t ret;
6706
6707 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1);
6708 ret += ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
6709
6710 if (ret == 0)
6711 {
6712 fifo_ctrl1.wtm = (uint8_t)(val & 0xFFU);
6713 fifo_ctrl2.wtm = (uint8_t)(val / 256U) & 0x01U;
6714
6715 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1);
6716 ret += ism330dhcx_write_reg(ctx, ISM330DHCX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
6717 }
6718
6719 return ret;
6720 }
6721
6722 /**
6723 * @brief FIFO watermark level selection.[get]
6724 *
6725 * @param ctx Read / write interface definitions.(ptr)
6726 * @param val Change the values of wtm in reg FIFO_CTRL1
6727 * @retval Interface status (MANDATORY: return 0 -> no Error).
6728 *
6729 */
ism330dhcx_fifo_watermark_get(const stmdev_ctx_t * ctx,uint16_t * val)6730 int32_t ism330dhcx_fifo_watermark_get(const stmdev_ctx_t *ctx,
6731 uint16_t *val)
6732 {
6733 ism330dhcx_fifo_ctrl1_t fifo_ctrl1;
6734 ism330dhcx_fifo_ctrl2_t fifo_ctrl2;
6735 int32_t ret;
6736
6737 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1);
6738 ret += ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
6739
6740 *val = fifo_ctrl2.wtm;
6741 *val = (*val * 256U) + fifo_ctrl1.wtm;;
6742
6743 return ret;
6744 }
6745
6746 /**
6747 * @brief FIFO compression feature initialization request.[set].
6748 *
6749 * @param ctx Read / write interface definitions.(ptr)
6750 * @param val Change the values of FIFO_COMPR_INIT in reg EMB_FUNC_INIT_B
6751 * @retval Interface status (MANDATORY: return 0 -> no Error).
6752 *
6753 */
ism330dhcx_compression_algo_init_set(const stmdev_ctx_t * ctx,uint8_t val)6754 int32_t ism330dhcx_compression_algo_init_set(const stmdev_ctx_t *ctx,
6755 uint8_t val)
6756 {
6757 ism330dhcx_emb_func_init_b_t emb_func_init_b;
6758 int32_t ret;
6759
6760 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
6761
6762 if (ret == 0)
6763 {
6764 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_INIT_B,
6765 (uint8_t *)&emb_func_init_b, 1);
6766 }
6767
6768 if (ret == 0)
6769 {
6770 emb_func_init_b.fifo_compr_init = (uint8_t)val;
6771 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_EMB_FUNC_INIT_B,
6772 (uint8_t *)&emb_func_init_b, 1);
6773 }
6774
6775 if (ret == 0)
6776 {
6777 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
6778 }
6779
6780 return ret;
6781 }
6782
6783 /**
6784 * @brief FIFO compression feature initialization request.[get].
6785 *
6786 * @param ctx Read / write interface definitions.(ptr)
6787 * @param val change the values of FIFO_COMPR_INIT in
6788 * reg EMB_FUNC_INIT_B
6789 * @retval Interface status (MANDATORY: return 0 -> no Error).
6790 *
6791 */
ism330dhcx_compression_algo_init_get(const stmdev_ctx_t * ctx,uint8_t * val)6792 int32_t ism330dhcx_compression_algo_init_get(const stmdev_ctx_t *ctx,
6793 uint8_t *val)
6794 {
6795 ism330dhcx_emb_func_init_b_t emb_func_init_b;
6796 int32_t ret;
6797
6798 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
6799
6800 if (ret == 0)
6801 {
6802 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_INIT_B,
6803 (uint8_t *)&emb_func_init_b, 1);
6804 }
6805
6806 if (ret == 0)
6807 {
6808 *val = emb_func_init_b.fifo_compr_init;
6809 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
6810 }
6811
6812 return ret;
6813 }
6814
6815 /**
6816 * @brief Enable and configure compression algo.[set]
6817 *
6818 * @param ctx Read / write interface definitions.(ptr)
6819 * @param val Change the values of uncoptr_rate in reg FIFO_CTRL2
6820 * @retval Interface status (MANDATORY: return 0 -> no Error).
6821 *
6822 */
ism330dhcx_compression_algo_set(const stmdev_ctx_t * ctx,ism330dhcx_uncoptr_rate_t val)6823 int32_t ism330dhcx_compression_algo_set(const stmdev_ctx_t *ctx,
6824 ism330dhcx_uncoptr_rate_t val)
6825 {
6826 ism330dhcx_fifo_ctrl2_t fifo_ctrl2;
6827 ism330dhcx_emb_func_en_b_t emb_func_en_b;
6828 int32_t ret;
6829
6830 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
6831
6832 if (ret == 0)
6833 {
6834 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_EN_B,
6835 (uint8_t *)&emb_func_en_b, 1);
6836 }
6837
6838 if (ret == 0)
6839 {
6840 emb_func_en_b.fifo_compr_en = ((uint8_t)val & 0x04U) >> 2;
6841 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_EMB_FUNC_EN_B,
6842 (uint8_t *)&emb_func_en_b, 1);
6843 }
6844
6845 if (ret == 0)
6846 {
6847 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
6848 }
6849
6850 if (ret == 0)
6851 {
6852 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL2,
6853 (uint8_t *)&fifo_ctrl2, 1);
6854 }
6855
6856 if (ret == 0)
6857 {
6858 fifo_ctrl2.fifo_compr_rt_en = ((uint8_t)val & 0x04U) >> 2;
6859 fifo_ctrl2.uncoptr_rate = (uint8_t)val & 0x03U;
6860 }
6861
6862 if (ret == 0)
6863 {
6864 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_FIFO_CTRL2,
6865 (uint8_t *)&fifo_ctrl2, 1);
6866 }
6867
6868 return ret;
6869 }
6870
6871 /**
6872 * @brief Enable and configure compression algo.[get]
6873 *
6874 * @param ctx Read / write interface definitions.(ptr)
6875 * @param val Get the values of uncoptr_rate in reg FIFO_CTRL2
6876 * @retval Interface status (MANDATORY: return 0 -> no Error).
6877 *
6878 */
ism330dhcx_compression_algo_get(const stmdev_ctx_t * ctx,ism330dhcx_uncoptr_rate_t * val)6879 int32_t ism330dhcx_compression_algo_get(const stmdev_ctx_t *ctx,
6880 ism330dhcx_uncoptr_rate_t *val)
6881 {
6882 ism330dhcx_fifo_ctrl2_t fifo_ctrl2;
6883 int32_t ret;
6884
6885 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL2,
6886 (uint8_t *)&fifo_ctrl2, 1);
6887
6888 switch ((fifo_ctrl2.fifo_compr_rt_en << 2) +
6889 fifo_ctrl2.uncoptr_rate)
6890 {
6891 case ISM330DHCX_CMP_DISABLE:
6892 *val = ISM330DHCX_CMP_DISABLE;
6893 break;
6894
6895 case ISM330DHCX_CMP_ALWAYS:
6896 *val = ISM330DHCX_CMP_ALWAYS;
6897 break;
6898
6899 case ISM330DHCX_CMP_8_TO_1:
6900 *val = ISM330DHCX_CMP_8_TO_1;
6901 break;
6902
6903 case ISM330DHCX_CMP_16_TO_1:
6904 *val = ISM330DHCX_CMP_16_TO_1;
6905 break;
6906
6907 case ISM330DHCX_CMP_32_TO_1:
6908 *val = ISM330DHCX_CMP_32_TO_1;
6909 break;
6910
6911 default:
6912 *val = ISM330DHCX_CMP_DISABLE;
6913 break;
6914 }
6915
6916 return ret;
6917 }
6918
6919 /**
6920 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set]
6921 *
6922 * @param ctx Read / write interface definitions.(ptr)
6923 * @param val Change the values of odrchg_en in reg FIFO_CTRL2
6924 * @retval Interface status (MANDATORY: return 0 -> no Error).
6925 *
6926 */
ism330dhcx_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t * ctx,uint8_t val)6927 int32_t ism330dhcx_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx,
6928 uint8_t val)
6929 {
6930 ism330dhcx_fifo_ctrl2_t fifo_ctrl2;
6931 int32_t ret;
6932
6933 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL2,
6934 (uint8_t *)&fifo_ctrl2, 1);
6935
6936 if (ret == 0)
6937 {
6938 fifo_ctrl2.odrchg_en = (uint8_t)val;
6939 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_FIFO_CTRL2,
6940 (uint8_t *)&fifo_ctrl2, 1);
6941 }
6942
6943 return ret;
6944 }
6945
6946 /**
6947 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get]
6948 *
6949 * @param ctx Read / write interface definitions.(ptr)
6950 * @param val Change the values of odrchg_en in reg FIFO_CTRL2
6951 * @retval Interface status (MANDATORY: return 0 -> no Error).
6952 *
6953 */
ism330dhcx_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t * ctx,uint8_t * val)6954 int32_t ism330dhcx_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx,
6955 uint8_t *val)
6956 {
6957 ism330dhcx_fifo_ctrl2_t fifo_ctrl2;
6958 int32_t ret;
6959
6960 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL2,
6961 (uint8_t *)&fifo_ctrl2, 1);
6962 *val = fifo_ctrl2.odrchg_en;
6963
6964 return ret;
6965 }
6966
6967 /**
6968 * @brief Enables/Disables compression algorithm runtime[set]
6969 *
6970 * @param ctx Read / write interface definitions.(ptr)
6971 * @param val Change the values of fifo_compr_rt_en in reg FIFO_CTRL2
6972 * @retval Interface status (MANDATORY: return 0 -> no Error).
6973 *
6974 */
ism330dhcx_compression_algo_real_time_set(const stmdev_ctx_t * ctx,uint8_t val)6975 int32_t ism330dhcx_compression_algo_real_time_set(const stmdev_ctx_t *ctx,
6976 uint8_t val)
6977 {
6978 ism330dhcx_fifo_ctrl2_t fifo_ctrl2;
6979 int32_t ret;
6980
6981 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL2,
6982 (uint8_t *)&fifo_ctrl2, 1);
6983
6984 if (ret == 0)
6985 {
6986 fifo_ctrl2.fifo_compr_rt_en = (uint8_t)val;
6987 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_FIFO_CTRL2,
6988 (uint8_t *)&fifo_ctrl2, 1);
6989 }
6990
6991 return ret;
6992 }
6993
6994 /**
6995 * @brief Enables/Disables compression algorithm runtime.[get]
6996 *
6997 * @param ctx Read / write interface definitions.(ptr)
6998 * @param val Change the values of fifo_compr_rt_en in reg FIFO_CTRL2
6999 * @retval Interface status (MANDATORY: return 0 -> no Error).
7000 *
7001 */
ism330dhcx_compression_algo_real_time_get(const stmdev_ctx_t * ctx,uint8_t * val)7002 int32_t ism330dhcx_compression_algo_real_time_get(const stmdev_ctx_t *ctx,
7003 uint8_t *val)
7004 {
7005 ism330dhcx_fifo_ctrl2_t fifo_ctrl2;
7006 int32_t ret;
7007
7008 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL2,
7009 (uint8_t *)&fifo_ctrl2, 1);
7010 *val = fifo_ctrl2.fifo_compr_rt_en;
7011
7012 return ret;
7013 }
7014
7015 /**
7016 * @brief Sensing chain FIFO stop values memorization at threshold
7017 * level.[set]
7018 *
7019 * @param ctx Read / write interface definitions.(ptr)
7020 * @param val Change the values of stop_on_wtm in reg FIFO_CTRL2
7021 * @retval Interface status (MANDATORY: return 0 -> no Error).
7022 *
7023 */
ism330dhcx_fifo_stop_on_wtm_set(const stmdev_ctx_t * ctx,uint8_t val)7024 int32_t ism330dhcx_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx,
7025 uint8_t val)
7026 {
7027 ism330dhcx_fifo_ctrl2_t fifo_ctrl2;
7028 int32_t ret;
7029
7030 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL2,
7031 (uint8_t *)&fifo_ctrl2, 1);
7032
7033 if (ret == 0)
7034 {
7035 fifo_ctrl2.stop_on_wtm = (uint8_t)val;
7036 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_FIFO_CTRL2,
7037 (uint8_t *)&fifo_ctrl2, 1);
7038 }
7039
7040 return ret;
7041 }
7042
7043 /**
7044 * @brief Sensing chain FIFO stop values memorization at threshold
7045 * level.[get]
7046 *
7047 * @param ctx Read / write interface definitions.(ptr)
7048 * @param val Change the values of stop_on_wtm in reg FIFO_CTRL2
7049 * @retval Interface status (MANDATORY: return 0 -> no Error).
7050 *
7051 */
ism330dhcx_fifo_stop_on_wtm_get(const stmdev_ctx_t * ctx,uint8_t * val)7052 int32_t ism330dhcx_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx,
7053 uint8_t *val)
7054 {
7055 ism330dhcx_fifo_ctrl2_t fifo_ctrl2;
7056 int32_t ret;
7057
7058 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL2,
7059 (uint8_t *)&fifo_ctrl2, 1);
7060 *val = fifo_ctrl2.stop_on_wtm;
7061
7062 return ret;
7063 }
7064
7065 /**
7066 * @brief Selects Batching Data Rate (writing frequency in FIFO)
7067 * for accelerometer data.[set]
7068 *
7069 * @param ctx Read / write interface definitions.(ptr)
7070 * @param val Change the values of bdr_xl in reg FIFO_CTRL3
7071 * @retval Interface status (MANDATORY: return 0 -> no Error).
7072 *
7073 */
ism330dhcx_fifo_xl_batch_set(const stmdev_ctx_t * ctx,ism330dhcx_bdr_xl_t val)7074 int32_t ism330dhcx_fifo_xl_batch_set(const stmdev_ctx_t *ctx,
7075 ism330dhcx_bdr_xl_t val)
7076 {
7077 ism330dhcx_fifo_ctrl3_t fifo_ctrl3;
7078 int32_t ret;
7079
7080 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL3,
7081 (uint8_t *)&fifo_ctrl3, 1);
7082
7083 if (ret == 0)
7084 {
7085 fifo_ctrl3.bdr_xl = (uint8_t)val;
7086 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_FIFO_CTRL3,
7087 (uint8_t *)&fifo_ctrl3, 1);
7088 }
7089
7090 return ret;
7091 }
7092
7093 /**
7094 * @brief Selects Batching Data Rate (writing frequency in FIFO)
7095 * for accelerometer data.[get]
7096 *
7097 * @param ctx Read / write interface definitions.(ptr)
7098 * @param val Get the values of bdr_xl in reg FIFO_CTRL3
7099 * @retval Interface status (MANDATORY: return 0 -> no Error).
7100 *
7101 */
ism330dhcx_fifo_xl_batch_get(const stmdev_ctx_t * ctx,ism330dhcx_bdr_xl_t * val)7102 int32_t ism330dhcx_fifo_xl_batch_get(const stmdev_ctx_t *ctx,
7103 ism330dhcx_bdr_xl_t *val)
7104 {
7105 ism330dhcx_fifo_ctrl3_t fifo_ctrl3;
7106 int32_t ret;
7107
7108 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL3,
7109 (uint8_t *)&fifo_ctrl3, 1);
7110
7111 switch (fifo_ctrl3.bdr_xl)
7112 {
7113 case ISM330DHCX_XL_NOT_BATCHED:
7114 *val = ISM330DHCX_XL_NOT_BATCHED;
7115 break;
7116
7117 case ISM330DHCX_XL_BATCHED_AT_12Hz5:
7118 *val = ISM330DHCX_XL_BATCHED_AT_12Hz5;
7119 break;
7120
7121 case ISM330DHCX_XL_BATCHED_AT_26Hz:
7122 *val = ISM330DHCX_XL_BATCHED_AT_26Hz;
7123 break;
7124
7125 case ISM330DHCX_XL_BATCHED_AT_52Hz:
7126 *val = ISM330DHCX_XL_BATCHED_AT_52Hz;
7127 break;
7128
7129 case ISM330DHCX_XL_BATCHED_AT_104Hz:
7130 *val = ISM330DHCX_XL_BATCHED_AT_104Hz;
7131 break;
7132
7133 case ISM330DHCX_XL_BATCHED_AT_208Hz:
7134 *val = ISM330DHCX_XL_BATCHED_AT_208Hz;
7135 break;
7136
7137 case ISM330DHCX_XL_BATCHED_AT_417Hz:
7138 *val = ISM330DHCX_XL_BATCHED_AT_417Hz;
7139 break;
7140
7141 case ISM330DHCX_XL_BATCHED_AT_833Hz:
7142 *val = ISM330DHCX_XL_BATCHED_AT_833Hz;
7143 break;
7144
7145 case ISM330DHCX_XL_BATCHED_AT_1667Hz:
7146 *val = ISM330DHCX_XL_BATCHED_AT_1667Hz;
7147 break;
7148
7149 case ISM330DHCX_XL_BATCHED_AT_3333Hz:
7150 *val = ISM330DHCX_XL_BATCHED_AT_3333Hz;
7151 break;
7152
7153 case ISM330DHCX_XL_BATCHED_AT_6667Hz:
7154 *val = ISM330DHCX_XL_BATCHED_AT_6667Hz;
7155 break;
7156
7157 case ISM330DHCX_XL_BATCHED_AT_6Hz5:
7158 *val = ISM330DHCX_XL_BATCHED_AT_6Hz5;
7159 break;
7160
7161 default:
7162 *val = ISM330DHCX_XL_NOT_BATCHED;
7163 break;
7164 }
7165
7166 return ret;
7167 }
7168
7169 /**
7170 * @brief Selects Batching Data Rate (writing frequency in FIFO)
7171 * for gyroscope data.[set]
7172 *
7173 * @param ctx Read / write interface definitions.(ptr)
7174 * @param val Change the values of bdr_gy in reg FIFO_CTRL3
7175 * @retval Interface status (MANDATORY: return 0 -> no Error).
7176 *
7177 */
ism330dhcx_fifo_gy_batch_set(const stmdev_ctx_t * ctx,ism330dhcx_bdr_gy_t val)7178 int32_t ism330dhcx_fifo_gy_batch_set(const stmdev_ctx_t *ctx,
7179 ism330dhcx_bdr_gy_t val)
7180 {
7181 ism330dhcx_fifo_ctrl3_t fifo_ctrl3;
7182 int32_t ret;
7183
7184 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL3,
7185 (uint8_t *)&fifo_ctrl3, 1);
7186
7187 if (ret == 0)
7188 {
7189 fifo_ctrl3.bdr_gy = (uint8_t)val;
7190 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_FIFO_CTRL3,
7191 (uint8_t *)&fifo_ctrl3, 1);
7192 }
7193
7194 return ret;
7195 }
7196
7197 /**
7198 * @brief Selects Batching Data Rate (writing frequency in FIFO)
7199 * for gyroscope data.[get]
7200 *
7201 * @param ctx Read / write interface definitions.(ptr)
7202 * @param val Get the values of bdr_gy in reg FIFO_CTRL3
7203 * @retval Interface status (MANDATORY: return 0 -> no Error).
7204 *
7205 */
ism330dhcx_fifo_gy_batch_get(const stmdev_ctx_t * ctx,ism330dhcx_bdr_gy_t * val)7206 int32_t ism330dhcx_fifo_gy_batch_get(const stmdev_ctx_t *ctx,
7207 ism330dhcx_bdr_gy_t *val)
7208 {
7209 ism330dhcx_fifo_ctrl3_t fifo_ctrl3;
7210 int32_t ret;
7211
7212 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL3,
7213 (uint8_t *)&fifo_ctrl3, 1);
7214
7215 switch (fifo_ctrl3.bdr_gy)
7216 {
7217 case ISM330DHCX_GY_NOT_BATCHED:
7218 *val = ISM330DHCX_GY_NOT_BATCHED;
7219 break;
7220
7221 case ISM330DHCX_GY_BATCHED_AT_12Hz5:
7222 *val = ISM330DHCX_GY_BATCHED_AT_12Hz5;
7223 break;
7224
7225 case ISM330DHCX_GY_BATCHED_AT_26Hz:
7226 *val = ISM330DHCX_GY_BATCHED_AT_26Hz;
7227 break;
7228
7229 case ISM330DHCX_GY_BATCHED_AT_52Hz:
7230 *val = ISM330DHCX_GY_BATCHED_AT_52Hz;
7231 break;
7232
7233 case ISM330DHCX_GY_BATCHED_AT_104Hz:
7234 *val = ISM330DHCX_GY_BATCHED_AT_104Hz;
7235 break;
7236
7237 case ISM330DHCX_GY_BATCHED_AT_208Hz:
7238 *val = ISM330DHCX_GY_BATCHED_AT_208Hz;
7239 break;
7240
7241 case ISM330DHCX_GY_BATCHED_AT_417Hz:
7242 *val = ISM330DHCX_GY_BATCHED_AT_417Hz;
7243 break;
7244
7245 case ISM330DHCX_GY_BATCHED_AT_833Hz:
7246 *val = ISM330DHCX_GY_BATCHED_AT_833Hz;
7247 break;
7248
7249 case ISM330DHCX_GY_BATCHED_AT_1667Hz:
7250 *val = ISM330DHCX_GY_BATCHED_AT_1667Hz;
7251 break;
7252
7253 case ISM330DHCX_GY_BATCHED_AT_3333Hz:
7254 *val = ISM330DHCX_GY_BATCHED_AT_3333Hz;
7255 break;
7256
7257 case ISM330DHCX_GY_BATCHED_AT_6667Hz:
7258 *val = ISM330DHCX_GY_BATCHED_AT_6667Hz;
7259 break;
7260
7261 case ISM330DHCX_GY_BATCHED_6Hz5:
7262 *val = ISM330DHCX_GY_BATCHED_6Hz5;
7263 break;
7264
7265 default:
7266 *val = ISM330DHCX_GY_NOT_BATCHED;
7267 break;
7268 }
7269
7270 return ret;
7271 }
7272
7273 /**
7274 * @brief FIFO mode selection.[set]
7275 *
7276 * @param ctx Read / write interface definitions.(ptr)
7277 * @param val Change the values of fifo_mode in reg FIFO_CTRL4
7278 * @retval Interface status (MANDATORY: return 0 -> no Error).
7279 *
7280 */
ism330dhcx_fifo_mode_set(const stmdev_ctx_t * ctx,ism330dhcx_fifo_mode_t val)7281 int32_t ism330dhcx_fifo_mode_set(const stmdev_ctx_t *ctx,
7282 ism330dhcx_fifo_mode_t val)
7283 {
7284 ism330dhcx_fifo_ctrl4_t fifo_ctrl4;
7285 int32_t ret;
7286
7287 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL4,
7288 (uint8_t *)&fifo_ctrl4, 1);
7289
7290 if (ret == 0)
7291 {
7292 fifo_ctrl4.fifo_mode = (uint8_t)val;
7293 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_FIFO_CTRL4,
7294 (uint8_t *)&fifo_ctrl4, 1);
7295 }
7296
7297 return ret;
7298 }
7299
7300 /**
7301 * @brief FIFO mode selection.[get]
7302 *
7303 * @param ctx Read / write interface definitions.(ptr)
7304 * @param val Get the values of fifo_mode in reg FIFO_CTRL4
7305 * @retval Interface status (MANDATORY: return 0 -> no Error).
7306 *
7307 */
ism330dhcx_fifo_mode_get(const stmdev_ctx_t * ctx,ism330dhcx_fifo_mode_t * val)7308 int32_t ism330dhcx_fifo_mode_get(const stmdev_ctx_t *ctx,
7309 ism330dhcx_fifo_mode_t *val)
7310 {
7311 ism330dhcx_fifo_ctrl4_t fifo_ctrl4;
7312 int32_t ret;
7313
7314 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL4,
7315 (uint8_t *)&fifo_ctrl4, 1);
7316
7317 switch (fifo_ctrl4.fifo_mode)
7318 {
7319 case ISM330DHCX_BYPASS_MODE:
7320 *val = ISM330DHCX_BYPASS_MODE;
7321 break;
7322
7323 case ISM330DHCX_FIFO_MODE:
7324 *val = ISM330DHCX_FIFO_MODE;
7325 break;
7326
7327 case ISM330DHCX_STREAM_TO_FIFO_MODE:
7328 *val = ISM330DHCX_STREAM_TO_FIFO_MODE;
7329 break;
7330
7331 case ISM330DHCX_BYPASS_TO_STREAM_MODE:
7332 *val = ISM330DHCX_BYPASS_TO_STREAM_MODE;
7333 break;
7334
7335 case ISM330DHCX_STREAM_MODE:
7336 *val = ISM330DHCX_STREAM_MODE;
7337 break;
7338
7339 case ISM330DHCX_BYPASS_TO_FIFO_MODE:
7340 *val = ISM330DHCX_BYPASS_TO_FIFO_MODE;
7341 break;
7342
7343 default:
7344 *val = ISM330DHCX_BYPASS_MODE;
7345 break;
7346 }
7347
7348 return ret;
7349 }
7350
7351 /**
7352 * @brief Selects Batching Data Rate (writing frequency in FIFO)
7353 * for temperature data.[set]
7354 *
7355 * @param ctx Read / write interface definitions.(ptr)
7356 * @param val Change the values of odr_t_batch in reg FIFO_CTRL4
7357 * @retval Interface status (MANDATORY: return 0 -> no Error).
7358 *
7359 */
ism330dhcx_fifo_temp_batch_set(const stmdev_ctx_t * ctx,ism330dhcx_odr_t_batch_t val)7360 int32_t ism330dhcx_fifo_temp_batch_set(const stmdev_ctx_t *ctx,
7361 ism330dhcx_odr_t_batch_t val)
7362 {
7363 ism330dhcx_fifo_ctrl4_t fifo_ctrl4;
7364 int32_t ret;
7365
7366 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL4,
7367 (uint8_t *)&fifo_ctrl4, 1);
7368
7369 if (ret == 0)
7370 {
7371 fifo_ctrl4.odr_t_batch = (uint8_t)val;
7372 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_FIFO_CTRL4,
7373 (uint8_t *)&fifo_ctrl4, 1);
7374 }
7375
7376 return ret;
7377 }
7378
7379 /**
7380 * @brief Selects Batching Data Rate (writing frequency in FIFO)
7381 * for temperature data.[get]
7382 *
7383 * @param ctx Read / write interface definitions.(ptr)
7384 * @param val Get the values of odr_t_batch in reg FIFO_CTRL4
7385 * @retval Interface status (MANDATORY: return 0 -> no Error).
7386 *
7387 */
ism330dhcx_fifo_temp_batch_get(const stmdev_ctx_t * ctx,ism330dhcx_odr_t_batch_t * val)7388 int32_t ism330dhcx_fifo_temp_batch_get(const stmdev_ctx_t *ctx,
7389 ism330dhcx_odr_t_batch_t *val)
7390 {
7391 ism330dhcx_fifo_ctrl4_t fifo_ctrl4;
7392 int32_t ret;
7393
7394 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL4,
7395 (uint8_t *)&fifo_ctrl4, 1);
7396
7397 switch (fifo_ctrl4.odr_t_batch)
7398 {
7399 case ISM330DHCX_TEMP_NOT_BATCHED:
7400 *val = ISM330DHCX_TEMP_NOT_BATCHED;
7401 break;
7402
7403 case ISM330DHCX_TEMP_BATCHED_AT_52Hz:
7404 *val = ISM330DHCX_TEMP_BATCHED_AT_52Hz;
7405 break;
7406
7407 case ISM330DHCX_TEMP_BATCHED_AT_12Hz5:
7408 *val = ISM330DHCX_TEMP_BATCHED_AT_12Hz5;
7409 break;
7410
7411 case ISM330DHCX_TEMP_BATCHED_AT_1Hz6:
7412 *val = ISM330DHCX_TEMP_BATCHED_AT_1Hz6;
7413 break;
7414
7415 default:
7416 *val = ISM330DHCX_TEMP_NOT_BATCHED;
7417 break;
7418 }
7419
7420 return ret;
7421 }
7422
7423 /**
7424 * @brief Selects decimation for timestamp batching in FIFO.
7425 * Writing rate will be the maximum rate between XL and
7426 * GYRO BDR divided by decimation decoder.[set]
7427 *
7428 * @param ctx Read / write interface definitions.(ptr)
7429 * @param val Change the values of odr_ts_batch in reg FIFO_CTRL4
7430 * @retval Interface status (MANDATORY: return 0 -> no Error).
7431 *
7432 */
ism330dhcx_fifo_timestamp_decimation_set(const stmdev_ctx_t * ctx,ism330dhcx_odr_ts_batch_t val)7433 int32_t ism330dhcx_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx,
7434 ism330dhcx_odr_ts_batch_t val)
7435 {
7436 ism330dhcx_fifo_ctrl4_t fifo_ctrl4;
7437 int32_t ret;
7438
7439 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL4,
7440 (uint8_t *)&fifo_ctrl4, 1);
7441
7442 if (ret == 0)
7443 {
7444 fifo_ctrl4.odr_ts_batch = (uint8_t)val;
7445 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_FIFO_CTRL4,
7446 (uint8_t *)&fifo_ctrl4, 1);
7447 }
7448
7449 return ret;
7450 }
7451
7452 /**
7453 * @brief Selects decimation for timestamp batching in FIFO.
7454 * Writing rate will be the maximum rate between XL and
7455 * GYRO BDR divided by decimation decoder.[get]
7456 *
7457 * @param ctx Read / write interface definitions.(ptr)
7458 * @param val Get the values of odr_ts_batch in reg
7459 * FIFO_CTRL4
7460 * @retval Interface status (MANDATORY: return 0 -> no Error).
7461 *
7462 */
ism330dhcx_fifo_timestamp_decimation_get(const stmdev_ctx_t * ctx,ism330dhcx_odr_ts_batch_t * val)7463 int32_t ism330dhcx_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx,
7464 ism330dhcx_odr_ts_batch_t *val)
7465 {
7466 ism330dhcx_fifo_ctrl4_t fifo_ctrl4;
7467 int32_t ret;
7468
7469 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL4,
7470 (uint8_t *)&fifo_ctrl4, 1);
7471
7472 switch (fifo_ctrl4.odr_ts_batch)
7473 {
7474 case ISM330DHCX_NO_DECIMATION:
7475 *val = ISM330DHCX_NO_DECIMATION;
7476 break;
7477
7478 case ISM330DHCX_DEC_1:
7479 *val = ISM330DHCX_DEC_1;
7480 break;
7481
7482 case ISM330DHCX_DEC_8:
7483 *val = ISM330DHCX_DEC_8;
7484 break;
7485
7486 case ISM330DHCX_DEC_32:
7487 *val = ISM330DHCX_DEC_32;
7488 break;
7489
7490 default:
7491 *val = ISM330DHCX_NO_DECIMATION;
7492 break;
7493 }
7494
7495 return ret;
7496 }
7497
7498 /**
7499 * @brief Selects the trigger for the internal counter of batching events
7500 * between XL and gyro.[set]
7501 *
7502 * @param ctx Read / write interface definitions.(ptr)
7503 * @param val Change the values of trig_counter_bdr in
7504 * reg COUNTER_BDR_REG1
7505 * @retval Interface status (MANDATORY: return 0 -> no Error).
7506 *
7507 */
ism330dhcx_fifo_cnt_event_batch_set(const stmdev_ctx_t * ctx,ism330dhcx_trig_counter_bdr_t val)7508 int32_t ism330dhcx_fifo_cnt_event_batch_set(const stmdev_ctx_t *ctx,
7509 ism330dhcx_trig_counter_bdr_t val)
7510 {
7511 ism330dhcx_counter_bdr_reg1_t counter_bdr_reg1;
7512 int32_t ret;
7513
7514 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_COUNTER_BDR_REG1,
7515 (uint8_t *)&counter_bdr_reg1, 1);
7516
7517 if (ret == 0)
7518 {
7519 counter_bdr_reg1.trig_counter_bdr = (uint8_t)val;
7520 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_COUNTER_BDR_REG1,
7521 (uint8_t *)&counter_bdr_reg1, 1);
7522 }
7523
7524 return ret;
7525 }
7526
7527 /**
7528 * @brief Selects the trigger for the internal counter of batching events
7529 * between XL and gyro.[get]
7530 *
7531 * @param ctx Read / write interface definitions.(ptr)
7532 * @param val Get the values of trig_counter_bdr
7533 * in reg COUNTER_BDR_REG1
7534 * @retval Interface status (MANDATORY: return 0 -> no Error).
7535 *
7536 */
ism330dhcx_fifo_cnt_event_batch_get(const stmdev_ctx_t * ctx,ism330dhcx_trig_counter_bdr_t * val)7537 int32_t ism330dhcx_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx,
7538 ism330dhcx_trig_counter_bdr_t *val)
7539 {
7540 ism330dhcx_counter_bdr_reg1_t counter_bdr_reg1;
7541 int32_t ret;
7542
7543 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_COUNTER_BDR_REG1,
7544 (uint8_t *)&counter_bdr_reg1, 1);
7545
7546 switch (counter_bdr_reg1.trig_counter_bdr)
7547 {
7548 case ISM330DHCX_XL_BATCH_EVENT:
7549 *val = ISM330DHCX_XL_BATCH_EVENT;
7550 break;
7551
7552 case ISM330DHCX_GYRO_BATCH_EVENT:
7553 *val = ISM330DHCX_GYRO_BATCH_EVENT;
7554 break;
7555
7556 default:
7557 *val = ISM330DHCX_XL_BATCH_EVENT;
7558 break;
7559 }
7560
7561 return ret;
7562 }
7563
7564 /**
7565 * @brief Resets the internal counter of batching events for a single sensor.
7566 * This bit is automatically reset to zero if it was set to '1'.[set]
7567 *
7568 * @param ctx Read / write interface definitions.(ptr)
7569 * @param val Change the values of rst_counter_bdr in reg COUNTER_BDR_REG1
7570 * @retval Interface status (MANDATORY: return 0 -> no Error).
7571 *
7572 */
ism330dhcx_rst_batch_counter_set(const stmdev_ctx_t * ctx,uint8_t val)7573 int32_t ism330dhcx_rst_batch_counter_set(const stmdev_ctx_t *ctx,
7574 uint8_t val)
7575 {
7576 ism330dhcx_counter_bdr_reg1_t counter_bdr_reg1;
7577 int32_t ret;
7578
7579 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_COUNTER_BDR_REG1,
7580 (uint8_t *)&counter_bdr_reg1, 1);
7581
7582 if (ret == 0)
7583 {
7584 counter_bdr_reg1.rst_counter_bdr = (uint8_t)val;
7585 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_COUNTER_BDR_REG1,
7586 (uint8_t *)&counter_bdr_reg1, 1);
7587 }
7588
7589 return ret;
7590 }
7591
7592 /**
7593 * @brief Resets the internal counter of batching events for a single sensor.
7594 * This bit is automatically reset to zero if it was set to '1'.[get]
7595 *
7596 * @param ctx Read / write interface definitions.(ptr)
7597 * @param val Change the values of rst_counter_bdr in reg COUNTER_BDR_REG1
7598 * @retval Interface status (MANDATORY: return 0 -> no Error).
7599 *
7600 */
ism330dhcx_rst_batch_counter_get(const stmdev_ctx_t * ctx,uint8_t * val)7601 int32_t ism330dhcx_rst_batch_counter_get(const stmdev_ctx_t *ctx,
7602 uint8_t *val)
7603 {
7604 ism330dhcx_counter_bdr_reg1_t counter_bdr_reg1;
7605 int32_t ret;
7606
7607 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_COUNTER_BDR_REG1,
7608 (uint8_t *)&counter_bdr_reg1, 1);
7609 *val = counter_bdr_reg1.rst_counter_bdr;
7610
7611 return ret;
7612 }
7613
7614 /**
7615 * @brief Batch data rate counter.[set]
7616 *
7617 * @param ctx Read / write interface definitions.(ptr)
7618 * @param val Change the values of cnt_bdr_th in reg COUNTER_BDR_REG2
7619 * and COUNTER_BDR_REG1.
7620 * @retval Interface status (MANDATORY: return 0 -> no Error).
7621 *
7622 */
ism330dhcx_batch_counter_threshold_set(const stmdev_ctx_t * ctx,uint16_t val)7623 int32_t ism330dhcx_batch_counter_threshold_set(const stmdev_ctx_t *ctx,
7624 uint16_t val)
7625 {
7626 ism330dhcx_counter_bdr_reg2_t counter_bdr_reg1;
7627 ism330dhcx_counter_bdr_reg2_t counter_bdr_reg2;
7628 int32_t ret;
7629
7630 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_COUNTER_BDR_REG1,
7631 (uint8_t *)&counter_bdr_reg1, 1);
7632
7633 if (ret == 0)
7634 {
7635 counter_bdr_reg1.cnt_bdr_th = (uint8_t)((val / 256U) & 0x07U);
7636 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_COUNTER_BDR_REG1,
7637 (uint8_t *)&counter_bdr_reg1, 1);
7638 }
7639
7640 if (ret == 0)
7641 {
7642 counter_bdr_reg2.cnt_bdr_th = (uint8_t)(val -
7643 (counter_bdr_reg1.cnt_bdr_th * 256U));
7644 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_COUNTER_BDR_REG2,
7645 (uint8_t *)&counter_bdr_reg2, 1);
7646 }
7647
7648 return ret;
7649 }
7650
7651 /**
7652 * @brief Batch data rate counter.[get]
7653 *
7654 * @param ctx Read / write interface definitions.(ptr)
7655 * @param val Change the values of cnt_bdr_th in reg COUNTER_BDR_REG2
7656 * and COUNTER_BDR_REG1.
7657 * @retval Interface status (MANDATORY: return 0 -> no Error).
7658 *
7659 */
ism330dhcx_batch_counter_threshold_get(const stmdev_ctx_t * ctx,uint16_t * val)7660 int32_t ism330dhcx_batch_counter_threshold_get(const stmdev_ctx_t *ctx,
7661 uint16_t *val)
7662 {
7663 ism330dhcx_counter_bdr_reg1_t counter_bdr_reg1;
7664 ism330dhcx_counter_bdr_reg2_t counter_bdr_reg2;
7665 int32_t ret;
7666
7667 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_COUNTER_BDR_REG1,
7668 (uint8_t *)&counter_bdr_reg1, 1);
7669
7670 if (ret == 0)
7671 {
7672 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_COUNTER_BDR_REG2,
7673 (uint8_t *)&counter_bdr_reg2, 1);
7674 }
7675
7676 *val = counter_bdr_reg1.cnt_bdr_th;
7677 *val = (*val * 256U) + counter_bdr_reg2.cnt_bdr_th;
7678
7679 return ret;
7680 }
7681
7682 /**
7683 * @brief Number of unread sensor data (TAG + 6 bytes) stored in FIFO.[get]
7684 *
7685 * @param ctx Read / write interface definitions.(ptr)
7686 * @param val Read the value of diff_fifo in reg FIFO_STATUS1 and FIFO_STATUS2
7687 * @retval Interface status (MANDATORY: return 0 -> no Error).
7688 *
7689 */
ism330dhcx_fifo_data_level_get(const stmdev_ctx_t * ctx,uint16_t * val)7690 int32_t ism330dhcx_fifo_data_level_get(const stmdev_ctx_t *ctx,
7691 uint16_t *val)
7692 {
7693 uint8_t reg[2];
7694 ism330dhcx_fifo_status1_t *fifo_status1 = (ism330dhcx_fifo_status1_t *)®[0];
7695 ism330dhcx_fifo_status2_t *fifo_status2 = (ism330dhcx_fifo_status2_t *)®[1];
7696 int32_t ret;
7697
7698 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
7699 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_STATUS1, (uint8_t *)reg, 2);
7700 if (ret == 0)
7701 {
7702 *val = fifo_status2->diff_fifo;
7703 *val = (*val * 256U) + fifo_status1->diff_fifo;
7704 }
7705
7706 return ret;
7707 }
7708
7709 /**
7710 * @brief Smart FIFO status.[get]
7711 *
7712 * @param ctx Read / write interface definitions.(ptr)
7713 * @param val Read registers FIFO_STATUS2
7714 * @retval Interface status (MANDATORY: return 0 -> no Error).
7715 *
7716 */
ism330dhcx_fifo_status_get(const stmdev_ctx_t * ctx,ism330dhcx_fifo_status2_t * val)7717 int32_t ism330dhcx_fifo_status_get(const stmdev_ctx_t *ctx,
7718 ism330dhcx_fifo_status2_t *val)
7719 {
7720 uint8_t reg[2];
7721 ism330dhcx_fifo_status2_t *fifo_status2 = (ism330dhcx_fifo_status2_t *)®[1];
7722 int32_t ret;
7723
7724 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
7725 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_STATUS1, (uint8_t *)reg, 2);
7726 if (ret == 0)
7727 {
7728 *val = *fifo_status2;
7729 }
7730
7731 return ret;
7732 }
7733
7734 /**
7735 * @brief Smart FIFO full status.[get]
7736 *
7737 * @param ctx Read / write interface definitions.(ptr)
7738 * @param val Read the values of fifo_full_ia in reg FIFO_STATUS2
7739 * @retval Interface status (MANDATORY: return 0 -> no Error).
7740 *
7741 */
ism330dhcx_fifo_full_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)7742 int32_t ism330dhcx_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
7743 {
7744 uint8_t reg[2];
7745 ism330dhcx_fifo_status2_t *fifo_status2 = (ism330dhcx_fifo_status2_t *)®[1];
7746 int32_t ret;
7747
7748 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
7749 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_STATUS1, (uint8_t *)reg, 2);
7750 if (ret == 0)
7751 {
7752 *val = fifo_status2->fifo_full_ia;
7753 }
7754
7755 return ret;
7756 }
7757
7758 /**
7759 * @brief FIFO overrun status.[get]
7760 *
7761 * @param ctx Read / write interface definitions.(ptr)
7762 * @param val Read the values of fifo_over_run_latched in
7763 * reg FIFO_STATUS2
7764 * @retval Interface status (MANDATORY: return 0 -> no Error).
7765 *
7766 */
ism330dhcx_fifo_ovr_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)7767 int32_t ism330dhcx_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
7768 {
7769 uint8_t reg[2];
7770 ism330dhcx_fifo_status2_t *fifo_status2 = (ism330dhcx_fifo_status2_t *)®[1];
7771 int32_t ret;
7772
7773 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
7774 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_STATUS1, (uint8_t *)reg, 2);
7775 if (ret == 0)
7776 {
7777 *val = fifo_status2->fifo_ovr_ia;
7778 }
7779
7780 return ret;
7781 }
7782
7783 /**
7784 * @brief FIFO watermark status.[get]
7785 *
7786 * @param ctx Read / write interface definitions.(ptr)
7787 * @param val Read the values of fifo_wtm_ia in reg FIFO_STATUS2
7788 * @retval Interface status (MANDATORY: return 0 -> no Error).
7789 *
7790 */
ism330dhcx_fifo_wtm_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)7791 int32_t ism330dhcx_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
7792 {
7793 uint8_t reg[2];
7794 ism330dhcx_fifo_status2_t *fifo_status2 = (ism330dhcx_fifo_status2_t *)®[1];
7795 int32_t ret;
7796
7797 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
7798 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_STATUS1, (uint8_t *)reg, 2);
7799 if (ret == 0)
7800 {
7801 *val = fifo_status2->fifo_wtm_ia;
7802 }
7803
7804 return ret;
7805 }
7806
7807 /**
7808 * @brief Identifies the sensor in FIFO_DATA_OUT.[get]
7809 *
7810 * @param ctx Read / write interface definitions.(ptr)
7811 * @param val Change the values of tag_sensor in reg FIFO_DATA_OUT_TAG
7812 * @retval Interface status (MANDATORY: return 0 -> no Error).
7813 *
7814 */
ism330dhcx_fifo_sensor_tag_get(const stmdev_ctx_t * ctx,ism330dhcx_fifo_tag_t * val)7815 int32_t ism330dhcx_fifo_sensor_tag_get(const stmdev_ctx_t *ctx,
7816 ism330dhcx_fifo_tag_t *val)
7817 {
7818 ism330dhcx_fifo_data_out_tag_t fifo_data_out_tag;
7819 int32_t ret;
7820
7821 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_DATA_OUT_TAG,
7822 (uint8_t *)&fifo_data_out_tag, 1);
7823
7824 switch (fifo_data_out_tag.tag_sensor)
7825 {
7826 case ISM330DHCX_GYRO_NC_TAG:
7827 *val = ISM330DHCX_GYRO_NC_TAG;
7828 break;
7829
7830 case ISM330DHCX_XL_NC_TAG:
7831 *val = ISM330DHCX_XL_NC_TAG;
7832 break;
7833
7834 case ISM330DHCX_TEMPERATURE_TAG:
7835 *val = ISM330DHCX_TEMPERATURE_TAG;
7836 break;
7837
7838 case ISM330DHCX_TIMESTAMP_TAG:
7839 *val = ISM330DHCX_TIMESTAMP_TAG;
7840 break;
7841
7842 case ISM330DHCX_CFG_CHANGE_TAG:
7843 *val = ISM330DHCX_CFG_CHANGE_TAG;
7844 break;
7845
7846 case ISM330DHCX_XL_NC_T_2_TAG:
7847 *val = ISM330DHCX_XL_NC_T_2_TAG;
7848 break;
7849
7850 case ISM330DHCX_XL_NC_T_1_TAG:
7851 *val = ISM330DHCX_XL_NC_T_1_TAG;
7852 break;
7853
7854 case ISM330DHCX_XL_2XC_TAG:
7855 *val = ISM330DHCX_XL_2XC_TAG;
7856 break;
7857
7858 case ISM330DHCX_XL_3XC_TAG:
7859 *val = ISM330DHCX_XL_3XC_TAG;
7860 break;
7861
7862 case ISM330DHCX_GYRO_NC_T_2_TAG:
7863 *val = ISM330DHCX_GYRO_NC_T_2_TAG;
7864 break;
7865
7866 case ISM330DHCX_GYRO_NC_T_1_TAG:
7867 *val = ISM330DHCX_GYRO_NC_T_1_TAG;
7868 break;
7869
7870 case ISM330DHCX_GYRO_2XC_TAG:
7871 *val = ISM330DHCX_GYRO_2XC_TAG;
7872 break;
7873
7874 case ISM330DHCX_GYRO_3XC_TAG:
7875 *val = ISM330DHCX_GYRO_3XC_TAG;
7876 break;
7877
7878 case ISM330DHCX_SENSORHUB_SLAVE0_TAG:
7879 *val = ISM330DHCX_SENSORHUB_SLAVE0_TAG;
7880 break;
7881
7882 case ISM330DHCX_SENSORHUB_SLAVE1_TAG:
7883 *val = ISM330DHCX_SENSORHUB_SLAVE1_TAG;
7884 break;
7885
7886 case ISM330DHCX_SENSORHUB_SLAVE2_TAG:
7887 *val = ISM330DHCX_SENSORHUB_SLAVE2_TAG;
7888 break;
7889
7890 case ISM330DHCX_SENSORHUB_SLAVE3_TAG:
7891 *val = ISM330DHCX_SENSORHUB_SLAVE3_TAG;
7892 break;
7893
7894 case ISM330DHCX_STEP_CPUNTER_TAG:
7895 *val = ISM330DHCX_STEP_CPUNTER_TAG;
7896 break;
7897
7898 case ISM330DHCX_GAME_ROTATION_TAG:
7899 *val = ISM330DHCX_GAME_ROTATION_TAG;
7900 break;
7901
7902 case ISM330DHCX_GEOMAG_ROTATION_TAG:
7903 *val = ISM330DHCX_GEOMAG_ROTATION_TAG;
7904 break;
7905
7906 case ISM330DHCX_ROTATION_TAG:
7907 *val = ISM330DHCX_ROTATION_TAG;
7908 break;
7909
7910 case ISM330DHCX_SENSORHUB_NACK_TAG:
7911 *val = ISM330DHCX_SENSORHUB_NACK_TAG;
7912 break;
7913
7914 default:
7915 *val = ISM330DHCX_SENSORHUB_NACK_TAG;
7916 break;
7917 }
7918
7919 return ret;
7920 }
7921
7922 /**
7923 * @brief Enable FIFO batching of pedometer embedded function values.[set]
7924 *
7925 * @param ctx Read / write interface definitions.(ptr)
7926 * @param val Change the values of gbias_fifo_en in
7927 * reg ISM330DHCX_EMB_FUNC_FIFO_CFG
7928 * @retval Interface status (MANDATORY: return 0 -> no Error).
7929 *
7930 */
ism330dhcx_fifo_pedo_batch_set(const stmdev_ctx_t * ctx,uint8_t val)7931 int32_t ism330dhcx_fifo_pedo_batch_set(const stmdev_ctx_t *ctx, uint8_t val)
7932 {
7933 ism330dhcx_emb_func_fifo_cfg_t emb_func_fifo_cfg;
7934 int32_t ret;
7935
7936 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
7937
7938 if (ret == 0)
7939 {
7940 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_FIFO_CFG,
7941 (uint8_t *)&emb_func_fifo_cfg, 1);
7942 }
7943
7944 if (ret == 0)
7945 {
7946 emb_func_fifo_cfg.pedo_fifo_en = (uint8_t)val;
7947 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_EMB_FUNC_FIFO_CFG,
7948 (uint8_t *)&emb_func_fifo_cfg, 1);
7949 }
7950
7951 if (ret == 0)
7952 {
7953 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
7954 }
7955
7956 return ret;
7957 }
7958
7959 /**
7960 * @brief Enable FIFO batching of pedometer embedded function values.[get]
7961 *
7962 * @param ctx Read / write interface definitions.(ptr)
7963 * @param val Change the values of pedo_fifo_en in reg
7964 * ISM330DHCX_EMB_FUNC_FIFO_CFG
7965 * @retval Interface status (MANDATORY: return 0 -> no Error).
7966 *
7967 */
ism330dhcx_fifo_pedo_batch_get(const stmdev_ctx_t * ctx,uint8_t * val)7968 int32_t ism330dhcx_fifo_pedo_batch_get(const stmdev_ctx_t *ctx,
7969 uint8_t *val)
7970 {
7971 ism330dhcx_emb_func_fifo_cfg_t emb_func_fifo_cfg;
7972 int32_t ret;
7973
7974 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
7975
7976 if (ret == 0)
7977 {
7978 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_FIFO_CFG,
7979 (uint8_t *)&emb_func_fifo_cfg, 1);
7980 *val = emb_func_fifo_cfg.pedo_fifo_en;
7981 }
7982
7983 if (ret == 0)
7984 {
7985 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
7986 }
7987
7988 return ret;
7989 }
7990
7991 /**
7992 * @brief Enable FIFO batching data of first slave.[set]
7993 *
7994 * @param ctx Read / write interface definitions.(ptr)
7995 * @param val Change the values of batch_ext_sens_0_en in reg SLV0_CONFIG
7996 * @retval Interface status (MANDATORY: return 0 -> no Error).
7997 *
7998 */
ism330dhcx_sh_batch_slave_0_set(const stmdev_ctx_t * ctx,uint8_t val)7999 int32_t ism330dhcx_sh_batch_slave_0_set(const stmdev_ctx_t *ctx,
8000 uint8_t val)
8001 {
8002 ism330dhcx_slv0_config_t slv0_config;
8003 int32_t ret;
8004
8005 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
8006
8007 if (ret == 0)
8008 {
8009 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_SLV0_CONFIG,
8010 (uint8_t *)&slv0_config, 1);
8011 }
8012
8013 if (ret == 0)
8014 {
8015 slv0_config. batch_ext_sens_0_en = (uint8_t)val;
8016 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_SLV0_CONFIG,
8017 (uint8_t *)&slv0_config, 1);
8018 }
8019
8020 if (ret == 0)
8021 {
8022 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
8023 }
8024
8025 return ret;
8026 }
8027
8028 /**
8029 * @brief Enable FIFO batching data of first slave.[get]
8030 *
8031 * @param ctx Read / write interface definitions.(ptr)
8032 * @param val Change the values of batch_ext_sens_0_en in
8033 * reg SLV0_CONFIG
8034 * @retval Interface status (MANDATORY: return 0 -> no Error).
8035 *
8036 */
ism330dhcx_sh_batch_slave_0_get(const stmdev_ctx_t * ctx,uint8_t * val)8037 int32_t ism330dhcx_sh_batch_slave_0_get(const stmdev_ctx_t *ctx,
8038 uint8_t *val)
8039 {
8040 ism330dhcx_slv0_config_t slv0_config;
8041 int32_t ret;
8042
8043 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
8044
8045 if (ret == 0)
8046 {
8047 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_SLV0_CONFIG,
8048 (uint8_t *)&slv0_config, 1);
8049 }
8050
8051 if (ret == 0)
8052 {
8053 *val = slv0_config. batch_ext_sens_0_en;
8054 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
8055 }
8056
8057 return ret;
8058 }
8059
8060 /**
8061 * @brief Enable FIFO batching data of second slave.[set]
8062 *
8063 * @param ctx Read / write interface definitions.(ptr)
8064 * @param val Change the values of batch_ext_sens_1_en in
8065 * reg SLV1_CONFIG
8066 * @retval Interface status (MANDATORY: return 0 -> no Error).
8067 *
8068 */
ism330dhcx_sh_batch_slave_1_set(const stmdev_ctx_t * ctx,uint8_t val)8069 int32_t ism330dhcx_sh_batch_slave_1_set(const stmdev_ctx_t *ctx,
8070 uint8_t val)
8071 {
8072 ism330dhcx_slv1_config_t slv1_config;
8073 int32_t ret;
8074
8075 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
8076
8077 if (ret == 0)
8078 {
8079 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_SLV1_CONFIG,
8080 (uint8_t *)&slv1_config, 1);
8081 }
8082
8083 if (ret == 0)
8084 {
8085 slv1_config. batch_ext_sens_1_en = (uint8_t)val;
8086 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_SLV1_CONFIG,
8087 (uint8_t *)&slv1_config, 1);
8088 }
8089
8090 if (ret == 0)
8091 {
8092 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
8093 }
8094
8095 return ret;
8096 }
8097
8098 /**
8099 * @brief Enable FIFO batching data of second slave.[get]
8100 *
8101 * @param ctx Read / write interface definitions.(ptr)
8102 * @param val Change the values of batch_ext_sens_1_en in
8103 * reg SLV1_CONFIG
8104 * @retval Interface status (MANDATORY: return 0 -> no Error).
8105 *
8106 */
ism330dhcx_sh_batch_slave_1_get(const stmdev_ctx_t * ctx,uint8_t * val)8107 int32_t ism330dhcx_sh_batch_slave_1_get(const stmdev_ctx_t *ctx,
8108 uint8_t *val)
8109 {
8110 ism330dhcx_slv1_config_t slv1_config;
8111 int32_t ret;
8112
8113 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
8114
8115 if (ret == 0)
8116 {
8117 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_SLV1_CONFIG,
8118 (uint8_t *)&slv1_config, 1);
8119 *val = slv1_config. batch_ext_sens_1_en;
8120 }
8121
8122 if (ret == 0)
8123 {
8124 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
8125 }
8126
8127 return ret;
8128 }
8129
8130 /**
8131 * @brief Enable FIFO batching data of third slave.[set]
8132 *
8133 * @param ctx Read / write interface definitions.(ptr)
8134 * @param val Change the values of batch_ext_sens_2_en in
8135 * reg SLV2_CONFIG
8136 * @retval Interface status (MANDATORY: return 0 -> no Error).
8137 *
8138 */
ism330dhcx_sh_batch_slave_2_set(const stmdev_ctx_t * ctx,uint8_t val)8139 int32_t ism330dhcx_sh_batch_slave_2_set(const stmdev_ctx_t *ctx,
8140 uint8_t val)
8141 {
8142 ism330dhcx_slv2_config_t slv2_config;
8143 int32_t ret;
8144
8145 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
8146
8147 if (ret == 0)
8148 {
8149 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_SLV2_CONFIG,
8150 (uint8_t *)&slv2_config, 1);
8151 }
8152
8153 if (ret == 0)
8154 {
8155 slv2_config. batch_ext_sens_2_en = (uint8_t)val;
8156 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_SLV2_CONFIG,
8157 (uint8_t *)&slv2_config, 1);
8158 }
8159
8160 if (ret == 0)
8161 {
8162 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
8163 }
8164
8165 return ret;
8166 }
8167
8168 /**
8169 * @brief Enable FIFO batching data of third slave.[get]
8170 *
8171 * @param ctx Read / write interface definitions.(ptr)
8172 * @param val Change the values of batch_ext_sens_2_en in
8173 * reg SLV2_CONFIG
8174 * @retval Interface status (MANDATORY: return 0 -> no Error).
8175 *
8176 */
ism330dhcx_sh_batch_slave_2_get(const stmdev_ctx_t * ctx,uint8_t * val)8177 int32_t ism330dhcx_sh_batch_slave_2_get(const stmdev_ctx_t *ctx,
8178 uint8_t *val)
8179 {
8180 ism330dhcx_slv2_config_t slv2_config;
8181 int32_t ret;
8182
8183 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
8184
8185 if (ret == 0)
8186 {
8187 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_SLV2_CONFIG,
8188 (uint8_t *)&slv2_config, 1);
8189 }
8190
8191 if (ret == 0)
8192 {
8193 *val = slv2_config. batch_ext_sens_2_en;
8194 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
8195 }
8196
8197 return ret;
8198 }
8199
8200 /**
8201 * @brief Enable FIFO batching data of fourth slave.[set]
8202 *
8203 * @param ctx Read / write interface definitions.(ptr)
8204 * @param val Change the values of batch_ext_sens_3_en in
8205 * reg SLV3_CONFIG
8206 * @retval Interface status (MANDATORY: return 0 -> no Error).
8207 *
8208 */
ism330dhcx_sh_batch_slave_3_set(const stmdev_ctx_t * ctx,uint8_t val)8209 int32_t ism330dhcx_sh_batch_slave_3_set(const stmdev_ctx_t *ctx,
8210 uint8_t val)
8211 {
8212 ism330dhcx_slv3_config_t slv3_config;
8213 int32_t ret;
8214
8215 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
8216
8217 if (ret == 0)
8218 {
8219 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_SLV3_CONFIG,
8220 (uint8_t *)&slv3_config, 1);
8221 }
8222
8223 if (ret == 0)
8224 {
8225 slv3_config. batch_ext_sens_3_en = (uint8_t)val;
8226 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_SLV3_CONFIG,
8227 (uint8_t *)&slv3_config, 1);
8228 }
8229
8230 if (ret == 0)
8231 {
8232 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
8233 }
8234
8235 return ret;
8236 }
8237
8238 /**
8239 * @brief Enable FIFO batching data of fourth slave.[get]
8240 *
8241 * @param ctx Read / write interface definitions.(ptr)
8242 * @param val Change the values of batch_ext_sens_3_en in
8243 * reg SLV3_CONFIG
8244 * @retval Interface status (MANDATORY: return 0 -> no Error).
8245 *
8246 */
ism330dhcx_sh_batch_slave_3_get(const stmdev_ctx_t * ctx,uint8_t * val)8247 int32_t ism330dhcx_sh_batch_slave_3_get(const stmdev_ctx_t *ctx,
8248 uint8_t *val)
8249 {
8250 ism330dhcx_slv3_config_t slv3_config;
8251 int32_t ret;
8252
8253 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
8254
8255 if (ret == 0)
8256 {
8257 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_SLV3_CONFIG,
8258 (uint8_t *)&slv3_config, 1);
8259 *val = slv3_config. batch_ext_sens_3_en;
8260 }
8261
8262 if (ret == 0)
8263 {
8264 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
8265 }
8266
8267 return ret;
8268 }
8269
8270 /**
8271 * @}
8272 *
8273 */
8274
8275 /**
8276 * @defgroup ISM330DHCX_DEN_functionality
8277 * @brief This section groups all the functions concerning
8278 * DEN functionality.
8279 * @{
8280 *
8281 */
8282
8283 /**
8284 * @brief DEN functionality marking mode.[set]
8285 *
8286 * @param ctx Read / write interface definitions.(ptr)
8287 * @param val Change the values of den_mode in reg CTRL6_C
8288 * @retval Interface status (MANDATORY: return 0 -> no Error).
8289 *
8290 */
ism330dhcx_den_mode_set(const stmdev_ctx_t * ctx,ism330dhcx_den_mode_t val)8291 int32_t ism330dhcx_den_mode_set(const stmdev_ctx_t *ctx,
8292 ism330dhcx_den_mode_t val)
8293 {
8294 ism330dhcx_ctrl6_c_t ctrl6_c;
8295 int32_t ret;
8296
8297 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL6_C,
8298 (uint8_t *)&ctrl6_c, 1);
8299
8300 if (ret == 0)
8301 {
8302 ctrl6_c.den_mode = (uint8_t)val;
8303 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL6_C,
8304 (uint8_t *)&ctrl6_c, 1);
8305 }
8306
8307 return ret;
8308 }
8309
8310 /**
8311 * @brief DEN functionality marking mode.[get]
8312 *
8313 * @param ctx Read / write interface definitions.(ptr)
8314 * @param val Get the values of den_mode in reg CTRL6_C
8315 * @retval Interface status (MANDATORY: return 0 -> no Error).
8316 *
8317 */
ism330dhcx_den_mode_get(const stmdev_ctx_t * ctx,ism330dhcx_den_mode_t * val)8318 int32_t ism330dhcx_den_mode_get(const stmdev_ctx_t *ctx,
8319 ism330dhcx_den_mode_t *val)
8320 {
8321 ism330dhcx_ctrl6_c_t ctrl6_c;
8322 int32_t ret;
8323
8324 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL6_C,
8325 (uint8_t *)&ctrl6_c, 1);
8326
8327 switch (ctrl6_c.den_mode)
8328 {
8329 case ISM330DHCX_DEN_DISABLE:
8330 *val = ISM330DHCX_DEN_DISABLE;
8331 break;
8332
8333 case ISM330DHCX_LEVEL_FIFO:
8334 *val = ISM330DHCX_LEVEL_FIFO;
8335 break;
8336
8337 case ISM330DHCX_LEVEL_LETCHED:
8338 *val = ISM330DHCX_LEVEL_LETCHED;
8339 break;
8340
8341 case ISM330DHCX_LEVEL_TRIGGER:
8342 *val = ISM330DHCX_LEVEL_TRIGGER;
8343 break;
8344
8345 case ISM330DHCX_EDGE_TRIGGER:
8346 *val = ISM330DHCX_EDGE_TRIGGER;
8347 break;
8348
8349 default:
8350 *val = ISM330DHCX_DEN_DISABLE;
8351 break;
8352 }
8353
8354 return ret;
8355 }
8356
8357 /**
8358 * @brief DEN active level configuration.[set]
8359 *
8360 * @param ctx Read / write interface definitions.(ptr)
8361 * @param val Change the values of den_lh in reg CTRL9_XL
8362 * @retval Interface status (MANDATORY: return 0 -> no Error).
8363 *
8364 */
ism330dhcx_den_polarity_set(const stmdev_ctx_t * ctx,ism330dhcx_den_lh_t val)8365 int32_t ism330dhcx_den_polarity_set(const stmdev_ctx_t *ctx,
8366 ism330dhcx_den_lh_t val)
8367 {
8368 ism330dhcx_ctrl9_xl_t ctrl9_xl;
8369 int32_t ret;
8370
8371 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL9_XL,
8372 (uint8_t *)&ctrl9_xl, 1);
8373
8374 if (ret == 0)
8375 {
8376 ctrl9_xl.den_lh = (uint8_t)val;
8377 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL9_XL,
8378 (uint8_t *)&ctrl9_xl, 1);
8379 }
8380
8381 return ret;
8382 }
8383
8384 /**
8385 * @brief DEN active level configuration.[get]
8386 *
8387 * @param ctx Read / write interface definitions.(ptr)
8388 * @param val Get the values of den_lh in reg CTRL9_XL
8389 * @retval Interface status (MANDATORY: return 0 -> no Error).
8390 *
8391 */
ism330dhcx_den_polarity_get(const stmdev_ctx_t * ctx,ism330dhcx_den_lh_t * val)8392 int32_t ism330dhcx_den_polarity_get(const stmdev_ctx_t *ctx,
8393 ism330dhcx_den_lh_t *val)
8394 {
8395 ism330dhcx_ctrl9_xl_t ctrl9_xl;
8396 int32_t ret;
8397
8398 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL9_XL,
8399 (uint8_t *)&ctrl9_xl, 1);
8400
8401 switch (ctrl9_xl.den_lh)
8402 {
8403 case ISM330DHCX_DEN_ACT_LOW:
8404 *val = ISM330DHCX_DEN_ACT_LOW;
8405 break;
8406
8407 case ISM330DHCX_DEN_ACT_HIGH:
8408 *val = ISM330DHCX_DEN_ACT_HIGH;
8409 break;
8410
8411 default:
8412 *val = ISM330DHCX_DEN_ACT_LOW;
8413 break;
8414 }
8415
8416 return ret;
8417 }
8418
8419 /**
8420 * @brief DEN configuration.[set]
8421 *
8422 * @param ctx Read / write interface definitions.(ptr)
8423 * @param val Change the values of den_xl_g in reg CTRL9_XL
8424 * @retval Interface status (MANDATORY: return 0 -> no Error).
8425 *
8426 */
ism330dhcx_den_enable_set(const stmdev_ctx_t * ctx,ism330dhcx_den_xl_g_t val)8427 int32_t ism330dhcx_den_enable_set(const stmdev_ctx_t *ctx,
8428 ism330dhcx_den_xl_g_t val)
8429 {
8430 ism330dhcx_ctrl9_xl_t ctrl9_xl;
8431 int32_t ret;
8432
8433 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL9_XL,
8434 (uint8_t *)&ctrl9_xl, 1);
8435
8436 if (ret == 0)
8437 {
8438 ctrl9_xl.den_xl_g = (uint8_t)val;
8439 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL9_XL,
8440 (uint8_t *)&ctrl9_xl, 1);
8441 }
8442
8443 return ret;
8444 }
8445
8446 /**
8447 * @brief DEN configuration.[get]
8448 *
8449 * @param ctx Read / write interface definitions.(ptr)
8450 * @param val Get the values of den_xl_g in reg CTRL9_XL
8451 * @retval Interface status (MANDATORY: return 0 -> no Error).
8452 *
8453 */
ism330dhcx_den_enable_get(const stmdev_ctx_t * ctx,ism330dhcx_den_xl_g_t * val)8454 int32_t ism330dhcx_den_enable_get(const stmdev_ctx_t *ctx,
8455 ism330dhcx_den_xl_g_t *val)
8456 {
8457 ism330dhcx_ctrl9_xl_t ctrl9_xl;
8458 int32_t ret;
8459
8460 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL9_XL,
8461 (uint8_t *)&ctrl9_xl, 1);
8462
8463 switch (ctrl9_xl.den_xl_g)
8464 {
8465 case ISM330DHCX_STAMP_IN_GY_DATA:
8466 *val = ISM330DHCX_STAMP_IN_GY_DATA;
8467 break;
8468
8469 case ISM330DHCX_STAMP_IN_XL_DATA:
8470 *val = ISM330DHCX_STAMP_IN_XL_DATA;
8471 break;
8472
8473 case ISM330DHCX_STAMP_IN_GY_XL_DATA:
8474 *val = ISM330DHCX_STAMP_IN_GY_XL_DATA;
8475 break;
8476
8477 default:
8478 *val = ISM330DHCX_STAMP_IN_GY_DATA;
8479 break;
8480 }
8481
8482 return ret;
8483 }
8484
8485 /**
8486 * @brief DEN value stored in LSB of X-axis.[set]
8487 *
8488 * @param ctx Read / write interface definitions.(ptr)
8489 * @param val Change the values of den_z in reg CTRL9_XL
8490 * @retval Interface status (MANDATORY: return 0 -> no Error).
8491 *
8492 */
ism330dhcx_den_mark_axis_x_set(const stmdev_ctx_t * ctx,uint8_t val)8493 int32_t ism330dhcx_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val)
8494 {
8495 ism330dhcx_ctrl9_xl_t ctrl9_xl;
8496 int32_t ret;
8497
8498 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL9_XL,
8499 (uint8_t *)&ctrl9_xl, 1);
8500
8501 if (ret == 0)
8502 {
8503 ctrl9_xl.den_z = (uint8_t)val;
8504 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL9_XL,
8505 (uint8_t *)&ctrl9_xl, 1);
8506 }
8507
8508 return ret;
8509 }
8510
8511 /**
8512 * @brief DEN value stored in LSB of X-axis.[get]
8513 *
8514 * @param ctx Read / write interface definitions.(ptr)
8515 * @param val Change the values of den_z in reg CTRL9_XL
8516 * @retval Interface status (MANDATORY: return 0 -> no Error).
8517 *
8518 */
ism330dhcx_den_mark_axis_x_get(const stmdev_ctx_t * ctx,uint8_t * val)8519 int32_t ism330dhcx_den_mark_axis_x_get(const stmdev_ctx_t *ctx,
8520 uint8_t *val)
8521 {
8522 ism330dhcx_ctrl9_xl_t ctrl9_xl;
8523 int32_t ret;
8524
8525 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL9_XL,
8526 (uint8_t *)&ctrl9_xl, 1);
8527 *val = ctrl9_xl.den_z;
8528
8529 return ret;
8530 }
8531
8532 /**
8533 * @brief DEN value stored in LSB of Y-axis.[set]
8534 *
8535 * @param ctx Read / write interface definitions.(ptr)
8536 * @param val Change the values of den_y in reg CTRL9_XL
8537 * @retval Interface status (MANDATORY: return 0 -> no Error).
8538 *
8539 */
ism330dhcx_den_mark_axis_y_set(const stmdev_ctx_t * ctx,uint8_t val)8540 int32_t ism330dhcx_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val)
8541 {
8542 ism330dhcx_ctrl9_xl_t ctrl9_xl;
8543 int32_t ret;
8544
8545 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL9_XL,
8546 (uint8_t *)&ctrl9_xl, 1);
8547
8548 if (ret == 0)
8549 {
8550 ctrl9_xl.den_y = (uint8_t)val;
8551 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL9_XL,
8552 (uint8_t *)&ctrl9_xl, 1);
8553 }
8554
8555 return ret;
8556 }
8557
8558 /**
8559 * @brief DEN value stored in LSB of Y-axis.[get]
8560 *
8561 * @param ctx Read / write interface definitions.(ptr)
8562 * @param val Change the values of den_y in reg CTRL9_XL
8563 * @retval Interface status (MANDATORY: return 0 -> no Error).
8564 *
8565 */
ism330dhcx_den_mark_axis_y_get(const stmdev_ctx_t * ctx,uint8_t * val)8566 int32_t ism330dhcx_den_mark_axis_y_get(const stmdev_ctx_t *ctx,
8567 uint8_t *val)
8568 {
8569 ism330dhcx_ctrl9_xl_t ctrl9_xl;
8570 int32_t ret;
8571
8572 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL9_XL,
8573 (uint8_t *)&ctrl9_xl, 1);
8574 *val = ctrl9_xl.den_y;
8575
8576 return ret;
8577 }
8578
8579 /**
8580 * @brief DEN value stored in LSB of Z-axis.[set]
8581 *
8582 * @param ctx Read / write interface definitions.(ptr)
8583 * @param val Change the values of den_x in reg CTRL9_XL
8584 * @retval Interface status (MANDATORY: return 0 -> no Error).
8585 *
8586 */
ism330dhcx_den_mark_axis_z_set(const stmdev_ctx_t * ctx,uint8_t val)8587 int32_t ism330dhcx_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val)
8588 {
8589 ism330dhcx_ctrl9_xl_t ctrl9_xl;
8590 int32_t ret;
8591
8592 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL9_XL,
8593 (uint8_t *)&ctrl9_xl, 1);
8594
8595 if (ret == 0)
8596 {
8597 ctrl9_xl.den_x = (uint8_t)val;
8598 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL9_XL,
8599 (uint8_t *)&ctrl9_xl, 1);
8600 }
8601
8602 return ret;
8603 }
8604
8605 /**
8606 * @brief DEN value stored in LSB of Z-axis.[get]
8607 *
8608 * @param ctx Read / write interface definitions.(ptr)
8609 * @param val Change the values of den_x in reg CTRL9_XL
8610 * @retval Interface status (MANDATORY: return 0 -> no Error).
8611 *
8612 */
ism330dhcx_den_mark_axis_z_get(const stmdev_ctx_t * ctx,uint8_t * val)8613 int32_t ism330dhcx_den_mark_axis_z_get(const stmdev_ctx_t *ctx,
8614 uint8_t *val)
8615 {
8616 ism330dhcx_ctrl9_xl_t ctrl9_xl;
8617 int32_t ret;
8618
8619 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL9_XL,
8620 (uint8_t *)&ctrl9_xl, 1);
8621 *val = ctrl9_xl.den_x;
8622
8623 return ret;
8624 }
8625
8626 /**
8627 * @}
8628 *
8629 */
8630
8631 /**
8632 * @defgroup ISM330DHCX_Pedometer
8633 * @brief This section groups all the functions that manage pedometer.
8634 * @{
8635 *
8636 */
8637
8638 /**
8639 * @brief Enable pedometer algorithm.[set]
8640 *
8641 * @param ctx Read / write interface definitions.(ptr)
8642 * @param val Change the values of pedo_en in reg EMB_FUNC_EN_A
8643 * @retval Interface status (MANDATORY: return 0 -> no Error).
8644 *
8645 */
ism330dhcx_pedo_sens_set(const stmdev_ctx_t * ctx,uint8_t val)8646 int32_t ism330dhcx_pedo_sens_set(const stmdev_ctx_t *ctx, uint8_t val)
8647 {
8648 ism330dhcx_emb_func_en_a_t emb_func_en_a;
8649 int32_t ret;
8650
8651 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
8652
8653 if (ret == 0)
8654 {
8655 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_EN_A,
8656 (uint8_t *)&emb_func_en_a, 1);
8657 }
8658
8659 if (ret == 0)
8660 {
8661 emb_func_en_a.pedo_en = (uint8_t)val;
8662 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_EMB_FUNC_EN_A,
8663 (uint8_t *)&emb_func_en_a, 1);
8664 }
8665
8666 if (ret == 0)
8667 {
8668 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
8669 }
8670
8671 return ret;
8672 }
8673
8674 /**
8675 * @brief Enable pedometer algorithm.[get]
8676 *
8677 * @param ctx Read / write interface definitions.(ptr)
8678 * @param val Change the values of pedo_en in reg EMB_FUNC_EN_A
8679 * @retval Interface status (MANDATORY: return 0 -> no Error).
8680 *
8681 */
ism330dhcx_pedo_sens_get(const stmdev_ctx_t * ctx,uint8_t * val)8682 int32_t ism330dhcx_pedo_sens_get(const stmdev_ctx_t *ctx, uint8_t *val)
8683 {
8684 ism330dhcx_emb_func_en_a_t emb_func_en_a;
8685 int32_t ret;
8686
8687 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
8688
8689 if (ret == 0)
8690 {
8691 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_EN_A,
8692 (uint8_t *)&emb_func_en_a, 1);
8693 *val = emb_func_en_a.pedo_en;
8694 }
8695
8696 if (ret == 0)
8697 {
8698 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
8699 }
8700
8701 return ret;
8702 }
8703
8704 /**
8705 * @brief Interrupt status bit for step detection.[get]
8706 *
8707 * @param ctx Read / write interface definitions.(ptr)
8708 * @param val Change the values of is_step_det in reg EMB_FUNC_STATUS
8709 * @retval Interface status (MANDATORY: return 0 -> no Error).
8710 *
8711 */
ism330dhcx_pedo_step_detect_get(const stmdev_ctx_t * ctx,uint8_t * val)8712 int32_t ism330dhcx_pedo_step_detect_get(const stmdev_ctx_t *ctx,
8713 uint8_t *val)
8714 {
8715 ism330dhcx_emb_func_status_t emb_func_status;
8716 int32_t ret;
8717
8718 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
8719
8720 if (ret == 0)
8721 {
8722 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_STATUS,
8723 (uint8_t *)&emb_func_status, 1);
8724 *val = emb_func_status.is_step_det;
8725 }
8726
8727 if (ret == 0)
8728 {
8729 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
8730 }
8731
8732 return ret;
8733 }
8734
8735 /**
8736 * @brief Pedometer debounce configuration register (r/w).[set]
8737 *
8738 * @param ctx Read / write interface definitions.(ptr)
8739 * @param buff Buffer that contains data to write
8740 * @retval Interface status (MANDATORY: return 0 -> no Error).
8741 *
8742 */
ism330dhcx_pedo_debounce_steps_set(const stmdev_ctx_t * ctx,uint8_t * buff)8743 int32_t ism330dhcx_pedo_debounce_steps_set(const stmdev_ctx_t *ctx,
8744 uint8_t *buff)
8745 {
8746 int32_t ret;
8747
8748 ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_PEDO_DEB_STEPS_CONF,
8749 buff);
8750
8751 return ret;
8752 }
8753
8754 /**
8755 * @brief Pedometer debounce configuration register (r/w).[get]
8756 *
8757 * @param ctx Read / write interface definitions.(ptr)
8758 * @param buff Buffer that stores data read
8759 * @retval Interface status (MANDATORY: return 0 -> no Error).
8760 *
8761 */
ism330dhcx_pedo_debounce_steps_get(const stmdev_ctx_t * ctx,uint8_t * buff)8762 int32_t ism330dhcx_pedo_debounce_steps_get(const stmdev_ctx_t *ctx,
8763 uint8_t *buff)
8764 {
8765 int32_t ret;
8766
8767 ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_PEDO_DEB_STEPS_CONF,
8768 buff);
8769
8770 return ret;
8771 }
8772
8773 /**
8774 * @brief Time period register for step detection on delta time (r/w).[set]
8775 *
8776 * @param ctx Read / write interface definitions.(ptr)
8777 * @param buff Buffer that contains data to write
8778 * @retval Interface status (MANDATORY: return 0 -> no Error).
8779 *
8780 */
ism330dhcx_pedo_steps_period_set(const stmdev_ctx_t * ctx,uint16_t val)8781 int32_t ism330dhcx_pedo_steps_period_set(const stmdev_ctx_t *ctx,
8782 uint16_t val)
8783 {
8784 uint8_t buff[2];
8785 int32_t ret;
8786
8787 buff[1] = (uint8_t)(val / 256U);
8788 buff[0] = (uint8_t)(val - (buff[1] * 256U));
8789 ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_PEDO_SC_DELTAT_L,
8790 &buff[0]);
8791
8792 if (ret == 0)
8793 {
8794 ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_PEDO_SC_DELTAT_H,
8795 &buff[1]);
8796 }
8797
8798 return ret;
8799 }
8800
8801 /**
8802 * @brief Time period register for step detection on delta time (r/w).[get]
8803 *
8804 * @param ctx Read / write interface definitions.(ptr)
8805 * @param buff Buffer that stores data read
8806 * @retval Interface status (MANDATORY: return 0 -> no Error).
8807 *
8808 */
ism330dhcx_pedo_steps_period_get(const stmdev_ctx_t * ctx,uint16_t * val)8809 int32_t ism330dhcx_pedo_steps_period_get(const stmdev_ctx_t *ctx,
8810 uint16_t *val)
8811 {
8812 uint8_t buff[2];
8813 int32_t ret;
8814
8815 ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_PEDO_SC_DELTAT_L,
8816 &buff[0]);
8817
8818 if (ret == 0)
8819 {
8820 ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_PEDO_SC_DELTAT_H,
8821 &buff[1]);
8822 *val = buff[1];
8823 *val = (*val * 256U) + buff[0];
8824 }
8825
8826 return ret;
8827 }
8828
8829 /**
8830 * @brief Set when user wants to generate interrupt on count overflow
8831 * event/every step.[set]
8832 *
8833 * @param ctx Read / write interface definitions.(ptr)
8834 * @param val Change the values of carry_count_en in reg PEDO_CMD_REG
8835 * @retval Interface status (MANDATORY: return 0 -> no Error).
8836 *
8837 */
ism330dhcx_pedo_int_mode_set(const stmdev_ctx_t * ctx,ism330dhcx_carry_count_en_t val)8838 int32_t ism330dhcx_pedo_int_mode_set(const stmdev_ctx_t *ctx,
8839 ism330dhcx_carry_count_en_t val)
8840 {
8841 ism330dhcx_pedo_cmd_reg_t pedo_cmd_reg;
8842 int32_t ret;
8843
8844 ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_PEDO_CMD_REG,
8845 (uint8_t *)&pedo_cmd_reg);
8846
8847 if (ret == 0)
8848 {
8849 pedo_cmd_reg.carry_count_en = (uint8_t)val;
8850 ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_PEDO_CMD_REG,
8851 (uint8_t *)&pedo_cmd_reg);
8852 }
8853
8854 return ret;
8855 }
8856
8857 /**
8858 * @brief Set when user wants to generate interrupt on count overflow
8859 * event/every step.[get]
8860 *
8861 * @param ctx Read / write interface definitions.(ptr)
8862 * @param val Get the values of carry_count_en in reg PEDO_CMD_REG
8863 * @retval Interface status (MANDATORY: return 0 -> no Error).
8864 *
8865 */
ism330dhcx_pedo_int_mode_get(const stmdev_ctx_t * ctx,ism330dhcx_carry_count_en_t * val)8866 int32_t ism330dhcx_pedo_int_mode_get(const stmdev_ctx_t *ctx,
8867 ism330dhcx_carry_count_en_t *val)
8868 {
8869 ism330dhcx_pedo_cmd_reg_t pedo_cmd_reg;
8870 int32_t ret;
8871
8872 ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_PEDO_CMD_REG,
8873 (uint8_t *)&pedo_cmd_reg);
8874
8875 switch (pedo_cmd_reg.carry_count_en)
8876 {
8877 case ISM330DHCX_EVERY_STEP:
8878 *val = ISM330DHCX_EVERY_STEP;
8879 break;
8880
8881 case ISM330DHCX_COUNT_OVERFLOW:
8882 *val = ISM330DHCX_COUNT_OVERFLOW;
8883 break;
8884
8885 default:
8886 *val = ISM330DHCX_EVERY_STEP;
8887 break;
8888 }
8889
8890 return ret;
8891 }
8892
8893 /**
8894 * @}
8895 *
8896 */
8897
8898 /**
8899 * @defgroup ISM330DHCX_significant_motion
8900 * @brief This section groups all the functions that manage the
8901 * significant motion detection.
8902 * @{
8903 *
8904 */
8905
8906 /**
8907 * @brief Enable significant motion detection function.[set]
8908 *
8909 * @param ctx Read / write interface definitions.(ptr)
8910 * @param val Change the values of sign_motion_en in reg EMB_FUNC_EN_A
8911 * @retval Interface status (MANDATORY: return 0 -> no Error).
8912 *
8913 */
ism330dhcx_motion_sens_set(const stmdev_ctx_t * ctx,uint8_t val)8914 int32_t ism330dhcx_motion_sens_set(const stmdev_ctx_t *ctx, uint8_t val)
8915 {
8916 ism330dhcx_emb_func_en_a_t emb_func_en_a;
8917 int32_t ret;
8918
8919 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
8920
8921 if (ret == 0)
8922 {
8923 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_EN_A,
8924 (uint8_t *)&emb_func_en_a, 1);
8925 }
8926
8927 if (ret == 0)
8928 {
8929 emb_func_en_a.sign_motion_en = (uint8_t)val;
8930 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_EMB_FUNC_EN_A,
8931 (uint8_t *)&emb_func_en_a, 1);
8932 }
8933
8934 if (ret == 0)
8935 {
8936 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
8937 }
8938
8939 return ret;
8940 }
8941
8942 /**
8943 * @brief Enable significant motion detection function.[get]
8944 *
8945 * @param ctx Read / write interface definitions.(ptr)
8946 * @param val Change the values of sign_motion_en in reg EMB_FUNC_EN_A
8947 * @retval Interface status (MANDATORY: return 0 -> no Error).
8948 *
8949 */
ism330dhcx_motion_sens_get(const stmdev_ctx_t * ctx,uint8_t * val)8950 int32_t ism330dhcx_motion_sens_get(const stmdev_ctx_t *ctx, uint8_t *val)
8951 {
8952 ism330dhcx_emb_func_en_a_t emb_func_en_a;
8953 int32_t ret;
8954
8955 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
8956
8957 if (ret == 0)
8958 {
8959 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_EN_A,
8960 (uint8_t *)&emb_func_en_a, 1);
8961 }
8962
8963 if (ret == 0)
8964 {
8965 *val = emb_func_en_a.sign_motion_en;
8966 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
8967 }
8968
8969 return ret;
8970 }
8971
8972 /**
8973 * @brief Interrupt status bit for significant motion detection.[get]
8974 *
8975 * @param ctx Read / write interface definitions.(ptr)
8976 * @param val Change the values of is_sigmot in reg EMB_FUNC_STATUS
8977 * @retval Interface status (MANDATORY: return 0 -> no Error).
8978 *
8979 */
ism330dhcx_motion_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)8980 int32_t ism330dhcx_motion_flag_data_ready_get(const stmdev_ctx_t *ctx,
8981 uint8_t *val)
8982 {
8983 ism330dhcx_emb_func_status_t emb_func_status;
8984 int32_t ret;
8985
8986 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
8987
8988 if (ret == 0)
8989 {
8990 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_STATUS,
8991 (uint8_t *)&emb_func_status, 1);
8992 }
8993
8994 if (ret == 0)
8995 {
8996 *val = emb_func_status.is_sigmot;
8997 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
8998 }
8999
9000 return ret;
9001 }
9002
9003 /**
9004 * @}
9005 *
9006 */
9007
9008 /**
9009 * @defgroup ISM330DHCX_tilt_detection
9010 * @brief This section groups all the functions that manage the tilt
9011 * event detection.
9012 * @{
9013 *
9014 */
9015
9016 /**
9017 * @brief Enable tilt calculation.[set]
9018 *
9019 * @param ctx Read / write interface definitions.(ptr)
9020 * @param val Change the values of tilt_en in reg EMB_FUNC_EN_A
9021 * @retval Interface status (MANDATORY: return 0 -> no Error).
9022 *
9023 */
ism330dhcx_tilt_sens_set(const stmdev_ctx_t * ctx,uint8_t val)9024 int32_t ism330dhcx_tilt_sens_set(const stmdev_ctx_t *ctx, uint8_t val)
9025 {
9026 ism330dhcx_emb_func_en_a_t emb_func_en_a;
9027 int32_t ret;
9028
9029 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
9030
9031 if (ret == 0)
9032 {
9033 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_EN_A,
9034 (uint8_t *)&emb_func_en_a, 1);
9035 }
9036
9037 if (ret == 0)
9038 {
9039 emb_func_en_a.tilt_en = (uint8_t)val;
9040 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_EMB_FUNC_EN_A,
9041 (uint8_t *)&emb_func_en_a, 1);
9042 }
9043
9044 if (ret == 0)
9045 {
9046 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
9047 }
9048
9049 return ret;
9050 }
9051
9052 /**
9053 * @brief Enable tilt calculation.[get]
9054 *
9055 * @param ctx Read / write interface definitions.(ptr)
9056 * @param val Change the values of tilt_en in reg EMB_FUNC_EN_A
9057 * @retval Interface status (MANDATORY: return 0 -> no Error).
9058 *
9059 */
ism330dhcx_tilt_sens_get(const stmdev_ctx_t * ctx,uint8_t * val)9060 int32_t ism330dhcx_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val)
9061 {
9062 ism330dhcx_emb_func_en_a_t emb_func_en_a;
9063 int32_t ret;
9064
9065 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
9066
9067 if (ret == 0)
9068 {
9069 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_EN_A,
9070 (uint8_t *)&emb_func_en_a, 1);
9071 }
9072
9073 if (ret == 0)
9074 {
9075 *val = emb_func_en_a.tilt_en;
9076 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
9077 }
9078
9079 return ret;
9080 }
9081
9082 /**
9083 * @brief Interrupt status bit for tilt detection.[get]
9084 *
9085 * @param ctx Read / write interface definitions.(ptr)
9086 * @param val Change the values of is_tilt in reg EMB_FUNC_STATUS
9087 * @retval Interface status (MANDATORY: return 0 -> no Error).
9088 *
9089 */
ism330dhcx_tilt_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)9090 int32_t ism330dhcx_tilt_flag_data_ready_get(const stmdev_ctx_t *ctx,
9091 uint8_t *val)
9092 {
9093 ism330dhcx_emb_func_status_t emb_func_status;
9094 int32_t ret;
9095
9096 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
9097
9098 if (ret == 0)
9099 {
9100 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_STATUS,
9101 (uint8_t *)&emb_func_status, 1);
9102 }
9103
9104 if (ret == 0)
9105 {
9106 *val = emb_func_status.is_tilt;
9107 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
9108 }
9109
9110 return ret;
9111 }
9112
9113 /**
9114 * @}
9115 *
9116 */
9117
9118 /**
9119 * @defgroup ISM330DHCX_ magnetometer_sensor
9120 * @brief This section groups all the functions that manage additional
9121 * magnetometer sensor.
9122 * @{
9123 *
9124 */
9125
9126 /**
9127 * @brief External magnetometer sensitivity value register.[set]
9128 *
9129 * @param ctx Read / write interface definitions.(ptr)
9130 * @param buff Buffer that contains data to write
9131 * @retval Interface status (MANDATORY: return 0 -> no Error).
9132 *
9133 */
ism330dhcx_mag_sensitivity_set(const stmdev_ctx_t * ctx,uint16_t val)9134 int32_t ism330dhcx_mag_sensitivity_set(const stmdev_ctx_t *ctx,
9135 uint16_t val)
9136 {
9137 uint8_t buff[2];
9138 int32_t ret;
9139
9140 buff[1] = (uint8_t)(val / 256U);
9141 buff[0] = (uint8_t)(val - (buff[1] * 256U));
9142 ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_SENSITIVITY_L,
9143 &buff[0]);
9144
9145 if (ret == 0)
9146 {
9147 ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_SENSITIVITY_H,
9148 &buff[1]);
9149 }
9150
9151 return ret;
9152 }
9153
9154 /**
9155 * @brief External magnetometer sensitivity value register.[get]
9156 *
9157 * @param ctx Read / write interface definitions.(ptr)
9158 * @param buff Buffer that stores data read
9159 * @retval Interface status (MANDATORY: return 0 -> no Error).
9160 *
9161 */
ism330dhcx_mag_sensitivity_get(const stmdev_ctx_t * ctx,uint16_t * val)9162 int32_t ism330dhcx_mag_sensitivity_get(const stmdev_ctx_t *ctx,
9163 uint16_t *val)
9164 {
9165 uint8_t buff[2];
9166 int32_t ret;
9167
9168 ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_SENSITIVITY_L,
9169 &buff[0]);
9170
9171 if (ret == 0)
9172 {
9173 ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_SENSITIVITY_H,
9174 &buff[1]);
9175 *val = buff[1];
9176 *val = (*val * 256U) + buff[0];
9177 }
9178
9179 return ret;
9180 }
9181
9182 /**
9183 * @brief Offset for hard-iron compensation register (r/w).[set]
9184 *
9185 * @param ctx Read / write interface definitions.(ptr)
9186 * @param buff Buffer that contains data to write
9187 * @retval Interface status (MANDATORY: return 0 -> no Error).
9188 *
9189 */
ism330dhcx_mag_offset_set(const stmdev_ctx_t * ctx,int16_t * val)9190 int32_t ism330dhcx_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val)
9191 {
9192 uint8_t buff[6];
9193 int32_t ret;
9194 uint8_t i;
9195
9196 buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
9197 buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
9198 buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
9199 buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
9200 buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
9201 buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
9202 i = 0x00U;
9203 ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_OFFX_L, &buff[i]);
9204
9205 if (ret == 0)
9206 {
9207 i++;
9208 ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_OFFX_H, &buff[i]);
9209 }
9210
9211 if (ret == 0)
9212 {
9213 i++;
9214 ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_OFFY_L, &buff[i]);
9215 }
9216
9217 if (ret == 0)
9218 {
9219 i++;
9220 ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_OFFY_H, &buff[i]);
9221 }
9222
9223 if (ret == 0)
9224 {
9225 i++;
9226 ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_OFFZ_L, &buff[i]);
9227 }
9228
9229 if (ret == 0)
9230 {
9231 i++;
9232 ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_OFFZ_H, &buff[i]);
9233 }
9234
9235 return ret;
9236 }
9237
9238 /**
9239 * @brief Offset for hard-iron compensation register (r/w).[get]
9240 *
9241 * @param ctx Read / write interface definitions.(ptr)
9242 * @param buff Buffer that stores data read
9243 * @retval Interface status (MANDATORY: return 0 -> no Error).
9244 *
9245 */
ism330dhcx_mag_offset_get(const stmdev_ctx_t * ctx,int16_t * val)9246 int32_t ism330dhcx_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val)
9247 {
9248 uint8_t buff[6];
9249 int32_t ret;
9250 uint8_t i;
9251
9252 i = 0x00U;
9253 ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_OFFX_L, &buff[i]);
9254
9255 if (ret == 0)
9256 {
9257 i++;
9258 ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_OFFX_H, &buff[i]);
9259 }
9260
9261 if (ret == 0)
9262 {
9263 i++;
9264 ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_OFFY_L, &buff[i]);
9265 }
9266
9267 if (ret == 0)
9268 {
9269 i++;
9270 ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_OFFY_H, &buff[i]);
9271 }
9272
9273 if (ret == 0)
9274 {
9275 i++;
9276 ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_OFFZ_L, &buff[i]);
9277 }
9278
9279 if (ret == 0)
9280 {
9281 i++;
9282 ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_OFFZ_H, &buff[i]);
9283
9284 val[0] = (int16_t)buff[1];
9285 val[0] = (val[0] * 256) + (int16_t)buff[0];
9286 val[1] = (int16_t)buff[3];
9287 val[1] = (val[1] * 256) + (int16_t)buff[2];
9288 val[2] = (int16_t)buff[5];
9289 val[2] = (val[2] * 256) + (int16_t)buff[4];
9290 }
9291
9292 return ret;
9293 }
9294
9295 /**
9296 * @brief Soft-iron (3x3 symmetric) matrix correction register (r/w).
9297 * The value is expressed as half-precision floating-point format:
9298 * SEEEEEFFFFFFFFFF
9299 * S: 1 sign bit;
9300 * E: 5 exponent bits;
9301 * F: 10 fraction bits).[set]
9302 *
9303 * @param ctx Read / write interface definitions.(ptr)
9304 * @param buff Buffer that contains data to write
9305 * @retval Interface status (MANDATORY: return 0 -> no Error).
9306 *
9307 */
ism330dhcx_mag_soft_iron_set(const stmdev_ctx_t * ctx,uint16_t * val)9308 int32_t ism330dhcx_mag_soft_iron_set(const stmdev_ctx_t *ctx, uint16_t *val)
9309 {
9310 uint8_t buff[12];
9311 int32_t ret;
9312 uint8_t i;
9313
9314 buff[1] = (uint8_t)(val[0] / 256U);
9315 buff[0] = (uint8_t)(val[0] - (buff[1] * 256U));
9316 buff[3] = (uint8_t)(val[1] / 256U);
9317 buff[2] = (uint8_t)(val[1] - (buff[3] * 256U));
9318 buff[5] = (uint8_t)(val[2] / 256U);
9319 buff[4] = (uint8_t)(val[2] - (buff[5] * 256U));
9320 buff[7] = (uint8_t)(val[3] / 256U);
9321 buff[6] = (uint8_t)(val[3] - (buff[1] * 256U));
9322 buff[9] = (uint8_t)(val[4] / 256U);
9323 buff[8] = (uint8_t)(val[4] - (buff[3] * 256U));
9324 buff[11] = (uint8_t)(val[5] / 256U);
9325 buff[10] = (uint8_t)(val[5] - (buff[5] * 256U));
9326 i = 0x00U;
9327 ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_SI_XX_L,
9328 &buff[i]);
9329
9330 if (ret == 0)
9331 {
9332 i++;
9333 ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_SI_XX_H,
9334 &buff[i]);
9335 }
9336
9337 if (ret == 0)
9338 {
9339 i++;
9340 ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_SI_XY_L,
9341 &buff[i]);
9342 }
9343
9344 if (ret == 0)
9345 {
9346 i++;
9347 ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_SI_XY_H,
9348 &buff[i]);
9349 }
9350
9351 if (ret == 0)
9352 {
9353 i++;
9354 ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_SI_XZ_L,
9355 &buff[i]);
9356 }
9357
9358 if (ret == 0)
9359 {
9360 i++;
9361 ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_SI_XZ_H,
9362 &buff[i]);
9363 }
9364
9365 if (ret == 0)
9366 {
9367 i++;
9368 ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_SI_YY_L,
9369 &buff[i]);
9370 }
9371
9372 if (ret == 0)
9373 {
9374 i++;
9375 ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_SI_YY_H,
9376 &buff[i]);
9377 }
9378
9379 if (ret == 0)
9380 {
9381 i++;
9382 ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_SI_YZ_L,
9383 &buff[i]);
9384 }
9385
9386 if (ret == 0)
9387 {
9388 i++;
9389 ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_SI_YZ_H,
9390 &buff[i]);
9391 }
9392
9393 if (ret == 0)
9394 {
9395 i++;
9396 ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_SI_ZZ_L,
9397 &buff[i]);
9398 }
9399
9400 if (ret == 0)
9401 {
9402 i++;
9403 ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_SI_ZZ_H,
9404 &buff[i]);
9405 }
9406
9407 return ret;
9408 }
9409
9410 /**
9411 * @brief Soft-iron (3x3 symmetric) matrix correction register (r/w).
9412 * The value is expressed as half-precision floating-point format:
9413 * SEEEEEFFFFFFFFFF
9414 * S: 1 sign bit;
9415 * E: 5 exponent bits;
9416 * F: 10 fraction bits).[get]
9417 *
9418 * @param ctx Read / write interface definitions.(ptr)
9419 * @param buff Buffer that stores data read
9420 * @retval Interface status (MANDATORY: return 0 -> no Error).
9421 *
9422 */
ism330dhcx_mag_soft_iron_get(const stmdev_ctx_t * ctx,uint16_t * val)9423 int32_t ism330dhcx_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint16_t *val)
9424 {
9425 uint8_t buff[12];
9426 int32_t ret;
9427 uint8_t i;
9428
9429 i = 0x00U;
9430 ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_SI_XX_L,
9431 &buff[i]);
9432
9433 if (ret == 0)
9434 {
9435 i++;
9436 ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_SI_XX_H,
9437 &buff[i]);
9438 }
9439
9440 if (ret == 0)
9441 {
9442 i++;
9443 ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_SI_XY_L,
9444 &buff[i]);
9445 }
9446
9447 if (ret == 0)
9448 {
9449 i++;
9450 ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_SI_XY_H,
9451 &buff[i]);
9452 }
9453
9454 if (ret == 0)
9455 {
9456 i++;
9457 ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_SI_XZ_L,
9458 &buff[i]);
9459 }
9460
9461 if (ret == 0)
9462 {
9463 i++;
9464 ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_SI_XZ_H,
9465 &buff[i]);
9466 }
9467
9468 if (ret == 0)
9469 {
9470 i++;
9471 ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_SI_YY_L,
9472 &buff[i]);
9473 }
9474
9475 if (ret == 0)
9476 {
9477 i++;
9478 ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_SI_YY_H,
9479 &buff[i]);
9480 }
9481
9482 if (ret == 0)
9483 {
9484 i++;
9485 ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_SI_YZ_L,
9486 &buff[i]);
9487 }
9488
9489 if (ret == 0)
9490 {
9491 i++;
9492 ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_SI_YZ_H,
9493 &buff[i]);
9494 }
9495
9496 if (ret == 0)
9497 {
9498 i++;
9499 ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_SI_ZZ_L,
9500 &buff[i]);
9501 }
9502
9503 if (ret == 0)
9504 {
9505 i++;
9506 ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_SI_ZZ_H,
9507 &buff[i]);
9508 }
9509
9510 val[0] = buff[1];
9511 val[0] = (val[0] * 256U) + buff[0];
9512 val[1] = buff[3];
9513 val[1] = (val[1] * 256U) + buff[2];
9514 val[2] = buff[5];
9515 val[2] = (val[2] * 256U) + buff[4];
9516 val[3] = buff[7];
9517 val[3] = (val[3] * 256U) + buff[6];
9518 val[4] = buff[9];
9519 val[4] = (val[4] * 256U) + buff[8];
9520 val[5] = buff[11];
9521 val[6] = (val[5] * 256U) + buff[10];
9522
9523 return ret;
9524 }
9525
9526 /**
9527 * @brief Magnetometer Z-axis coordinates rotation (to be aligned to
9528 * accelerometer/gyroscope axes orientation).[set]
9529 *
9530 * @param ctx Read / write interface definitions.(ptr)
9531 * @param val Change the values of mag_z_axis in reg MAG_CFG_A
9532 * @retval Interface status (MANDATORY: return 0 -> no Error).
9533 *
9534 */
ism330dhcx_mag_z_orient_set(const stmdev_ctx_t * ctx,ism330dhcx_mag_z_axis_t val)9535 int32_t ism330dhcx_mag_z_orient_set(const stmdev_ctx_t *ctx,
9536 ism330dhcx_mag_z_axis_t val)
9537 {
9538 ism330dhcx_mag_cfg_a_t mag_cfg_a;
9539 int32_t ret;
9540
9541 ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_CFG_A,
9542 (uint8_t *)&mag_cfg_a);
9543
9544 if (ret == 0)
9545 {
9546 mag_cfg_a.mag_z_axis = (uint8_t)val;
9547 ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_CFG_A,
9548 (uint8_t *)&mag_cfg_a);
9549 }
9550
9551 return ret;
9552 }
9553
9554 /**
9555 * @brief Magnetometer Z-axis coordinates rotation (to be aligned to
9556 * accelerometer/gyroscope axes orientation).[get]
9557 *
9558 * @param ctx Read / write interface definitions.(ptr)
9559 * @param val Get the values of mag_z_axis in reg MAG_CFG_A
9560 * @retval Interface status (MANDATORY: return 0 -> no Error).
9561 *
9562 */
ism330dhcx_mag_z_orient_get(const stmdev_ctx_t * ctx,ism330dhcx_mag_z_axis_t * val)9563 int32_t ism330dhcx_mag_z_orient_get(const stmdev_ctx_t *ctx,
9564 ism330dhcx_mag_z_axis_t *val)
9565 {
9566 ism330dhcx_mag_cfg_a_t mag_cfg_a;
9567 int32_t ret;
9568
9569 ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_CFG_A,
9570 (uint8_t *)&mag_cfg_a);
9571
9572 switch (mag_cfg_a.mag_z_axis)
9573 {
9574 case ISM330DHCX_Z_EQ_Y:
9575 *val = ISM330DHCX_Z_EQ_Y;
9576 break;
9577
9578 case ISM330DHCX_Z_EQ_MIN_Y:
9579 *val = ISM330DHCX_Z_EQ_MIN_Y;
9580 break;
9581
9582 case ISM330DHCX_Z_EQ_X:
9583 *val = ISM330DHCX_Z_EQ_X;
9584 break;
9585
9586 case ISM330DHCX_Z_EQ_MIN_X:
9587 *val = ISM330DHCX_Z_EQ_MIN_X;
9588 break;
9589
9590 case ISM330DHCX_Z_EQ_MIN_Z:
9591 *val = ISM330DHCX_Z_EQ_MIN_Z;
9592 break;
9593
9594 case ISM330DHCX_Z_EQ_Z:
9595 *val = ISM330DHCX_Z_EQ_Z;
9596 break;
9597
9598 default:
9599 *val = ISM330DHCX_Z_EQ_Y;
9600 break;
9601 }
9602
9603 return ret;
9604 }
9605
9606 /**
9607 * @brief Magnetometer Y-axis coordinates rotation (to be aligned to
9608 * accelerometer/gyroscope axes orientation).[set]
9609 *
9610 * @param ctx Read / write interface definitions.(ptr)
9611 * @param val Change the values of mag_y_axis in
9612 * reg MAG_CFG_A
9613 * @retval Interface status (MANDATORY: return 0 -> no Error).
9614 *
9615 */
ism330dhcx_mag_y_orient_set(const stmdev_ctx_t * ctx,ism330dhcx_mag_y_axis_t val)9616 int32_t ism330dhcx_mag_y_orient_set(const stmdev_ctx_t *ctx,
9617 ism330dhcx_mag_y_axis_t val)
9618 {
9619 ism330dhcx_mag_cfg_a_t mag_cfg_a;
9620 int32_t ret;
9621
9622 ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_CFG_A,
9623 (uint8_t *)&mag_cfg_a);
9624
9625 if (ret == 0)
9626 {
9627 mag_cfg_a.mag_y_axis = (uint8_t)val;
9628 ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_CFG_A,
9629 (uint8_t *)&mag_cfg_a);
9630 }
9631
9632 return ret;
9633 }
9634
9635 /**
9636 * @brief Magnetometer Y-axis coordinates rotation (to be aligned to
9637 * accelerometer/gyroscope axes orientation).[get]
9638 *
9639 * @param ctx Read / write interface definitions.(ptr)
9640 * @param val Get the values of mag_y_axis in reg MAG_CFG_A
9641 * @retval Interface status (MANDATORY: return 0 -> no Error).
9642 *
9643 */
ism330dhcx_mag_y_orient_get(const stmdev_ctx_t * ctx,ism330dhcx_mag_y_axis_t * val)9644 int32_t ism330dhcx_mag_y_orient_get(const stmdev_ctx_t *ctx,
9645 ism330dhcx_mag_y_axis_t *val)
9646 {
9647 ism330dhcx_mag_cfg_a_t mag_cfg_a;
9648 int32_t ret;
9649
9650 ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_CFG_A,
9651 (uint8_t *)&mag_cfg_a);
9652
9653 switch (mag_cfg_a.mag_y_axis)
9654 {
9655 case ISM330DHCX_Y_EQ_Y:
9656 *val = ISM330DHCX_Y_EQ_Y;
9657 break;
9658
9659 case ISM330DHCX_Y_EQ_MIN_Y:
9660 *val = ISM330DHCX_Y_EQ_MIN_Y;
9661 break;
9662
9663 case ISM330DHCX_Y_EQ_X:
9664 *val = ISM330DHCX_Y_EQ_X;
9665 break;
9666
9667 case ISM330DHCX_Y_EQ_MIN_X:
9668 *val = ISM330DHCX_Y_EQ_MIN_X;
9669 break;
9670
9671 case ISM330DHCX_Y_EQ_MIN_Z:
9672 *val = ISM330DHCX_Y_EQ_MIN_Z;
9673 break;
9674
9675 case ISM330DHCX_Y_EQ_Z:
9676 *val = ISM330DHCX_Y_EQ_Z;
9677 break;
9678
9679 default:
9680 *val = ISM330DHCX_Y_EQ_Y;
9681 break;
9682 }
9683
9684 return ret;
9685 }
9686
9687 /**
9688 * @brief Magnetometer X-axis coordinates rotation (to be aligned to
9689 * accelerometer/gyroscope axes orientation).[set]
9690 *
9691 * @param ctx Read / write interface definitions.(ptr)
9692 * @param val Change the values of mag_x_axis in reg MAG_CFG_B
9693 * @retval Interface status (MANDATORY: return 0 -> no Error).
9694 *
9695 */
ism330dhcx_mag_x_orient_set(const stmdev_ctx_t * ctx,ism330dhcx_mag_x_axis_t val)9696 int32_t ism330dhcx_mag_x_orient_set(const stmdev_ctx_t *ctx,
9697 ism330dhcx_mag_x_axis_t val)
9698 {
9699 ism330dhcx_mag_cfg_b_t mag_cfg_b;
9700 int32_t ret;
9701
9702 ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_CFG_B,
9703 (uint8_t *)&mag_cfg_b);
9704
9705 if (ret == 0)
9706 {
9707 mag_cfg_b.mag_x_axis = (uint8_t)val;
9708 ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_CFG_B,
9709 (uint8_t *)&mag_cfg_b);
9710 }
9711
9712 return ret;
9713 }
9714
9715 /**
9716 * @brief Magnetometer X-axis coordinates rotation (to be aligned to
9717 * accelerometer/gyroscope axes orientation).[get]
9718 *
9719 * @param ctx Read / write interface definitions.(ptr)
9720 * @param val Get the values of mag_x_axis in reg MAG_CFG_B
9721 * @retval Interface status (MANDATORY: return 0 -> no Error).
9722 *
9723 */
ism330dhcx_mag_x_orient_get(const stmdev_ctx_t * ctx,ism330dhcx_mag_x_axis_t * val)9724 int32_t ism330dhcx_mag_x_orient_get(const stmdev_ctx_t *ctx,
9725 ism330dhcx_mag_x_axis_t *val)
9726 {
9727 ism330dhcx_mag_cfg_b_t mag_cfg_b;
9728 int32_t ret;
9729
9730 ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_CFG_B,
9731 (uint8_t *)&mag_cfg_b);
9732
9733 switch (mag_cfg_b.mag_x_axis)
9734 {
9735 case ISM330DHCX_X_EQ_Y:
9736 *val = ISM330DHCX_X_EQ_Y;
9737 break;
9738
9739 case ISM330DHCX_X_EQ_MIN_Y:
9740 *val = ISM330DHCX_X_EQ_MIN_Y;
9741 break;
9742
9743 case ISM330DHCX_X_EQ_X:
9744 *val = ISM330DHCX_X_EQ_X;
9745 break;
9746
9747 case ISM330DHCX_X_EQ_MIN_X:
9748 *val = ISM330DHCX_X_EQ_MIN_X;
9749 break;
9750
9751 case ISM330DHCX_X_EQ_MIN_Z:
9752 *val = ISM330DHCX_X_EQ_MIN_Z;
9753 break;
9754
9755 case ISM330DHCX_X_EQ_Z:
9756 *val = ISM330DHCX_X_EQ_Z;
9757 break;
9758
9759 default:
9760 *val = ISM330DHCX_X_EQ_Y;
9761 break;
9762 }
9763
9764 return ret;
9765 }
9766
9767 /**
9768 * @}
9769 *
9770 */
9771
9772 /**
9773 * @defgroup ISM330DHCX_finite_state_machine
9774 * @brief This section groups all the functions that manage the
9775 * state_machine.
9776 * @{
9777 *
9778 */
9779
9780 /**
9781 * @brief Interrupt status bit for FSM long counter timeout interrupt
9782 * event.[get]
9783 *
9784 * @param ctx Read / write interface definitions.(ptr)
9785 * @param val Change the values of is_fsm_lc in reg EMB_FUNC_STATUS
9786 * @retval Interface status (MANDATORY: return 0 -> no Error).
9787 *
9788 */
ism330dhcx_long_cnt_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)9789 int32_t ism330dhcx_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx,
9790 uint8_t *val)
9791 {
9792 ism330dhcx_emb_func_status_t emb_func_status;
9793 int32_t ret;
9794
9795 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
9796
9797 if (ret == 0)
9798 {
9799 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_STATUS,
9800 (uint8_t *)&emb_func_status, 1);
9801 }
9802
9803 if (ret == 0)
9804 {
9805 *val = emb_func_status.is_fsm_lc;
9806 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
9807 }
9808
9809 return ret;
9810 }
9811
9812 /**
9813 * @brief Embedded final state machine functions mode.[set]
9814 *
9815 * @param ctx Read / write interface definitions.(ptr)
9816 * @param val Change the values of fsm_en in reg EMB_FUNC_EN_B
9817 * @retval Interface status (MANDATORY: return 0 -> no Error).
9818 *
9819 */
ism330dhcx_emb_fsm_en_set(const stmdev_ctx_t * ctx,uint8_t val)9820 int32_t ism330dhcx_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val)
9821 {
9822 int32_t ret;
9823
9824 ism330dhcx_emb_func_en_b_t emb_func_en_b;
9825 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
9826
9827 if (ret == 0)
9828 {
9829 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_EN_B,
9830 (uint8_t *)&emb_func_en_b, 1);
9831 }
9832
9833 if (ret == 0)
9834 {
9835 emb_func_en_b.fsm_en = (uint8_t)val;
9836 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_EMB_FUNC_EN_B,
9837 (uint8_t *)&emb_func_en_b, 1);
9838 }
9839
9840 if (ret == 0)
9841 {
9842 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
9843 }
9844
9845 return ret;
9846 }
9847
9848 /**
9849 * @brief Embedded final state machine functions mode.[get]
9850 *
9851 * @param ctx Read / write interface definitions.(ptr)
9852 * @param val Get the values of fsm_en in reg EMB_FUNC_EN_B
9853 * @retval Interface status (MANDATORY: return 0 -> no Error).
9854 *
9855 */
ism330dhcx_emb_fsm_en_get(const stmdev_ctx_t * ctx,uint8_t * val)9856 int32_t ism330dhcx_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val)
9857 {
9858 int32_t ret;
9859 ism330dhcx_emb_func_en_b_t emb_func_en_b;
9860
9861 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
9862
9863 if (ret == 0)
9864 {
9865 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_EN_B,
9866 (uint8_t *)&emb_func_en_b, 1);
9867 }
9868
9869 if (ret == 0)
9870 {
9871 *val = emb_func_en_b.fsm_en;
9872 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_EMB_FUNC_EN_B,
9873 (uint8_t *)&emb_func_en_b, 1);
9874 }
9875
9876 if (ret == 0)
9877 {
9878 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
9879 }
9880
9881 return ret;
9882 }
9883
9884 /**
9885 * @brief Embedded final state machine functions mode.[set]
9886 *
9887 * @param ctx Read / write interface definitions.(ptr)
9888 * @param val Structure of registers from FSM_ENABLE_A to FSM_ENABLE_B
9889 * @retval Interface status (MANDATORY: return 0 -> no Error).
9890 *
9891 */
ism330dhcx_fsm_enable_set(const stmdev_ctx_t * ctx,ism330dhcx_emb_fsm_enable_t * val)9892 int32_t ism330dhcx_fsm_enable_set(const stmdev_ctx_t *ctx,
9893 ism330dhcx_emb_fsm_enable_t *val)
9894 {
9895 ism330dhcx_emb_func_en_b_t emb_func_en_b;
9896 int32_t ret;
9897
9898 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
9899
9900 if (ret == 0)
9901 {
9902 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_FSM_ENABLE_A,
9903 (uint8_t *)&val->fsm_enable_a, 1);
9904 }
9905
9906 if (ret == 0)
9907 {
9908 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_FSM_ENABLE_B,
9909 (uint8_t *)&val->fsm_enable_b, 1);
9910 }
9911
9912 if (ret == 0)
9913 {
9914 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_EN_B,
9915 (uint8_t *)&emb_func_en_b, 1);
9916 }
9917
9918 if (ret == 0)
9919 {
9920 if ((val->fsm_enable_a.fsm1_en |
9921 val->fsm_enable_a.fsm2_en |
9922 val->fsm_enable_a.fsm3_en |
9923 val->fsm_enable_a.fsm4_en |
9924 val->fsm_enable_a.fsm5_en |
9925 val->fsm_enable_a.fsm6_en |
9926 val->fsm_enable_a.fsm7_en |
9927 val->fsm_enable_a.fsm8_en |
9928 val->fsm_enable_b.fsm9_en |
9929 val->fsm_enable_b.fsm10_en |
9930 val->fsm_enable_b.fsm11_en |
9931 val->fsm_enable_b.fsm12_en |
9932 val->fsm_enable_b.fsm13_en |
9933 val->fsm_enable_b.fsm14_en |
9934 val->fsm_enable_b.fsm15_en |
9935 val->fsm_enable_b.fsm16_en) != PROPERTY_DISABLE)
9936 {
9937 emb_func_en_b.fsm_en = PROPERTY_ENABLE;
9938 }
9939
9940 else
9941 {
9942 emb_func_en_b.fsm_en = PROPERTY_DISABLE;
9943 }
9944 }
9945
9946 if (ret == 0)
9947 {
9948 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_EMB_FUNC_EN_B,
9949 (uint8_t *)&emb_func_en_b, 1);
9950 }
9951
9952 if (ret == 0)
9953 {
9954 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
9955 }
9956
9957 return ret;
9958 }
9959
9960 /**
9961 * @brief Embedded final state machine functions mode.[get]
9962 *
9963 * @param ctx Read / write interface definitions.(ptr)
9964 * @param val Structure of registers from FSM_ENABLE_A to FSM_ENABLE_B
9965 * @retval Interface status (MANDATORY: return 0 -> no Error).
9966 *
9967 */
ism330dhcx_fsm_enable_get(const stmdev_ctx_t * ctx,ism330dhcx_emb_fsm_enable_t * val)9968 int32_t ism330dhcx_fsm_enable_get(const stmdev_ctx_t *ctx,
9969 ism330dhcx_emb_fsm_enable_t *val)
9970 {
9971 int32_t ret;
9972
9973 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
9974
9975 if (ret == 0)
9976 {
9977 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FSM_ENABLE_A,
9978 (uint8_t *)&val->fsm_enable_a, 1);
9979 }
9980
9981 if (ret == 0)
9982 {
9983 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FSM_ENABLE_B,
9984 (uint8_t *)&val->fsm_enable_b, 1);
9985 }
9986
9987 if (ret == 0)
9988 {
9989 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
9990 }
9991
9992 return ret;
9993 }
9994
9995 /**
9996 * @brief FSM long counter status register. Long counter value is an
9997 * unsigned integer value (16-bit format).[set]
9998 *
9999 * @param ctx Read / write interface definitions.(ptr)
10000 * @param buff Buffer that contains data to write
10001 * @retval Interface status (MANDATORY: return 0 -> no Error).
10002 *
10003 */
ism330dhcx_long_cnt_set(const stmdev_ctx_t * ctx,uint16_t val)10004 int32_t ism330dhcx_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val)
10005 {
10006 uint8_t buff[2];
10007 int32_t ret;
10008
10009 buff[1] = (uint8_t)(val / 256U);
10010 buff[0] = (uint8_t)(val - (buff[1] * 256U));
10011 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
10012
10013 if (ret == 0)
10014 {
10015 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_FSM_LONG_COUNTER_L, buff,
10016 2);
10017 }
10018
10019 if (ret == 0)
10020 {
10021 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
10022 }
10023
10024 return ret;
10025 }
10026
10027 /**
10028 * @brief FSM long counter status register. Long counter value is an
10029 * unsigned integer value (16-bit format).[get]
10030 *
10031 * @param ctx Read / write interface definitions.(ptr)
10032 * @param buff Buffer that stores data read
10033 * @retval Interface status (MANDATORY: return 0 -> no Error).
10034 *
10035 */
ism330dhcx_long_cnt_get(const stmdev_ctx_t * ctx,uint16_t * val)10036 int32_t ism330dhcx_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val)
10037 {
10038 uint8_t buff[2];
10039 int32_t ret;
10040
10041 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
10042
10043 if (ret == 0)
10044 {
10045 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FSM_LONG_COUNTER_L, buff,
10046 2);
10047 *val = buff[1];
10048 *val = (*val * 256U) + buff[0];
10049 }
10050
10051 if (ret == 0)
10052 {
10053 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
10054 }
10055
10056 return ret;
10057 }
10058
10059 /**
10060 * @brief Clear FSM long counter value.[set]
10061 *
10062 * @param ctx Read / write interface definitions.(ptr)
10063 * @param val Change the values of fsm_lc_clr in reg
10064 * FSM_LONG_COUNTER_CLEAR
10065 * @retval Interface status (MANDATORY: return 0 -> no Error).
10066 *
10067 */
ism330dhcx_long_clr_set(const stmdev_ctx_t * ctx,ism330dhcx_fsm_lc_clr_t val)10068 int32_t ism330dhcx_long_clr_set(const stmdev_ctx_t *ctx,
10069 ism330dhcx_fsm_lc_clr_t val)
10070 {
10071 ism330dhcx_fsm_long_counter_clear_t fsm_long_counter_clear;
10072 int32_t ret;
10073
10074 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
10075
10076 if (ret == 0)
10077 {
10078 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FSM_LONG_COUNTER_CLEAR,
10079 (uint8_t *)&fsm_long_counter_clear, 1);
10080 }
10081
10082 if (ret == 0)
10083 {
10084 fsm_long_counter_clear.fsm_lc_clr = (uint8_t)val;
10085 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_FSM_LONG_COUNTER_CLEAR,
10086 (uint8_t *)&fsm_long_counter_clear, 1);
10087 }
10088
10089 if (ret == 0)
10090 {
10091 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
10092 }
10093
10094 return ret;
10095 }
10096
10097 /**
10098 * @brief Clear FSM long counter value.[get]
10099 *
10100 * @param ctx Read / write interface definitions.(ptr)
10101 * @param val Get the values of fsm_lc_clr in reg FSM_LONG_COUNTER_CLEAR
10102 * @retval Interface status (MANDATORY: return 0 -> no Error).
10103 *
10104 */
ism330dhcx_long_clr_get(const stmdev_ctx_t * ctx,ism330dhcx_fsm_lc_clr_t * val)10105 int32_t ism330dhcx_long_clr_get(const stmdev_ctx_t *ctx,
10106 ism330dhcx_fsm_lc_clr_t *val)
10107 {
10108 ism330dhcx_fsm_long_counter_clear_t fsm_long_counter_clear;
10109 int32_t ret;
10110
10111 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
10112
10113 if (ret == 0)
10114 {
10115 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FSM_LONG_COUNTER_CLEAR,
10116 (uint8_t *)&fsm_long_counter_clear, 1);
10117 }
10118
10119 if (ret == 0)
10120 {
10121 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
10122 }
10123
10124 switch (fsm_long_counter_clear.fsm_lc_clr)
10125 {
10126 case ISM330DHCX_LC_NORMAL:
10127 *val = ISM330DHCX_LC_NORMAL;
10128 break;
10129
10130 case ISM330DHCX_LC_CLEAR:
10131 *val = ISM330DHCX_LC_CLEAR;
10132 break;
10133
10134 case ISM330DHCX_LC_CLEAR_DONE:
10135 *val = ISM330DHCX_LC_CLEAR_DONE;
10136 break;
10137
10138 default:
10139 *val = ISM330DHCX_LC_NORMAL;
10140 break;
10141 }
10142
10143 return ret;
10144 }
10145
10146 /**
10147 * @brief FSM output registers.[get]
10148 *
10149 * @param ctx Read / write interface definitions.(ptr)
10150 * @param val Structure of registers from FSM_OUTS1 to FSM_OUTS16
10151 * @retval Interface status (MANDATORY: return 0 -> no Error).
10152 *
10153 */
ism330dhcx_fsm_out_get(const stmdev_ctx_t * ctx,ism330dhcx_fsm_out_t * val)10154 int32_t ism330dhcx_fsm_out_get(const stmdev_ctx_t *ctx,
10155 ism330dhcx_fsm_out_t *val)
10156 {
10157 int32_t ret;
10158
10159 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
10160
10161 if (ret == 0)
10162 {
10163 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FSM_OUTS1,
10164 (uint8_t *)&val->fsm_outs1, 16);
10165 }
10166
10167 if (ret == 0)
10168 {
10169 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
10170 }
10171
10172 return ret;
10173 }
10174
10175 /**
10176 * @brief Finite State Machine ODR configuration.[set]
10177 *
10178 * @param ctx Read / write interface definitions.(ptr)
10179 * @param val Change the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
10180 * @retval Interface status (MANDATORY: return 0 -> no Error).
10181 *
10182 */
ism330dhcx_fsm_data_rate_set(const stmdev_ctx_t * ctx,ism330dhcx_fsm_odr_t val)10183 int32_t ism330dhcx_fsm_data_rate_set(const stmdev_ctx_t *ctx,
10184 ism330dhcx_fsm_odr_t val)
10185 {
10186 ism330dhcx_emb_func_odr_cfg_b_t emb_func_odr_cfg_b;
10187 int32_t ret;
10188
10189 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
10190
10191 if (ret == 0)
10192 {
10193 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_ODR_CFG_B,
10194 (uint8_t *)&emb_func_odr_cfg_b, 1);
10195 }
10196
10197 if (ret == 0)
10198 {
10199 emb_func_odr_cfg_b.not_used_01 = 3; /* set default values */
10200 emb_func_odr_cfg_b.not_used_02 = 1; /* set default values */
10201 emb_func_odr_cfg_b.fsm_odr = (uint8_t)val;
10202 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_EMB_FUNC_ODR_CFG_B,
10203 (uint8_t *)&emb_func_odr_cfg_b, 1);
10204 }
10205
10206 if (ret == 0)
10207 {
10208 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
10209 }
10210
10211 return ret;
10212 }
10213
10214 /**
10215 * @brief Finite State Machine ODR configuration.[get]
10216 *
10217 * @param ctx Read / write interface definitions.(ptr)
10218 * @param val Get the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
10219 * @retval Interface status (MANDATORY: return 0 -> no Error).
10220 *
10221 */
ism330dhcx_fsm_data_rate_get(const stmdev_ctx_t * ctx,ism330dhcx_fsm_odr_t * val)10222 int32_t ism330dhcx_fsm_data_rate_get(const stmdev_ctx_t *ctx,
10223 ism330dhcx_fsm_odr_t *val)
10224 {
10225 ism330dhcx_emb_func_odr_cfg_b_t emb_func_odr_cfg_b;
10226 int32_t ret;
10227
10228 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
10229
10230 if (ret == 0)
10231 {
10232 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_ODR_CFG_B,
10233 (uint8_t *)&emb_func_odr_cfg_b, 1);
10234 }
10235
10236 if (ret == 0)
10237 {
10238 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
10239 }
10240
10241 switch (emb_func_odr_cfg_b.fsm_odr)
10242 {
10243 case ISM330DHCX_ODR_FSM_12Hz5:
10244 *val = ISM330DHCX_ODR_FSM_12Hz5;
10245 break;
10246
10247 case ISM330DHCX_ODR_FSM_26Hz:
10248 *val = ISM330DHCX_ODR_FSM_26Hz;
10249 break;
10250
10251 case ISM330DHCX_ODR_FSM_52Hz:
10252 *val = ISM330DHCX_ODR_FSM_52Hz;
10253 break;
10254
10255 case ISM330DHCX_ODR_FSM_104Hz:
10256 *val = ISM330DHCX_ODR_FSM_104Hz;
10257 break;
10258
10259 default:
10260 *val = ISM330DHCX_ODR_FSM_12Hz5;
10261 break;
10262 }
10263
10264 return ret;
10265 }
10266
10267 /**
10268 * @brief FSM initialization request.[set]
10269 *
10270 * @param ctx Read / write interface definitions.(ptr)
10271 * @param val Change the values of fsm_init in reg FSM_INIT
10272 * @retval Interface status (MANDATORY: return 0 -> no Error).
10273 *
10274 */
ism330dhcx_fsm_init_set(const stmdev_ctx_t * ctx,uint8_t val)10275 int32_t ism330dhcx_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val)
10276 {
10277 ism330dhcx_emb_func_init_b_t emb_func_init_b;
10278 int32_t ret;
10279
10280 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
10281
10282 if (ret == 0)
10283 {
10284 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_INIT_B,
10285 (uint8_t *)&emb_func_init_b, 1);
10286 }
10287
10288 if (ret == 0)
10289 {
10290 emb_func_init_b.fsm_init = (uint8_t)val;
10291 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_EMB_FUNC_INIT_B,
10292 (uint8_t *)&emb_func_init_b, 1);
10293 }
10294
10295 if (ret == 0)
10296 {
10297 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
10298 }
10299
10300 return ret;
10301 }
10302
10303 /**
10304 * @brief FSM initialization request.[get]
10305 *
10306 * @param ctx Read / write interface definitions.(ptr)
10307 * @param val Change the values of fsm_init in reg FSM_INIT
10308 * @retval Interface status (MANDATORY: return 0 -> no Error).
10309 *
10310 */
ism330dhcx_fsm_init_get(const stmdev_ctx_t * ctx,uint8_t * val)10311 int32_t ism330dhcx_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val)
10312 {
10313 ism330dhcx_emb_func_init_b_t emb_func_init_b;
10314 int32_t ret;
10315
10316 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
10317
10318 if (ret == 0)
10319 {
10320 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_INIT_B,
10321 (uint8_t *)&emb_func_init_b, 1);
10322 }
10323
10324 if (ret == 0)
10325 {
10326 *val = emb_func_init_b.fsm_init;
10327 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
10328 }
10329
10330 return ret;
10331 }
10332
10333 /**
10334 * @brief FSM long counter timeout register (r/w). The long counter
10335 * timeout value is an unsigned integer value (16-bit format).
10336 * When the long counter value reached this value, the FSM
10337 * generates an interrupt.[set]
10338 *
10339 * @param ctx Read / write interface definitions.(ptr)
10340 * @param buff Buffer that contains data to write
10341 * @retval Interface status (MANDATORY: return 0 -> no Error).
10342 *
10343 */
ism330dhcx_long_cnt_int_value_set(const stmdev_ctx_t * ctx,uint16_t val)10344 int32_t ism330dhcx_long_cnt_int_value_set(const stmdev_ctx_t *ctx,
10345 uint16_t val)
10346 {
10347 uint8_t buff[2];
10348 int32_t ret;
10349
10350 buff[1] = (uint8_t)(val / 256U);
10351 buff[0] = (uint8_t)(val - (buff[1] * 256U));
10352 ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_FSM_LC_TIMEOUT_L,
10353 &buff[0]);
10354
10355 if (ret == 0)
10356 {
10357 ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_FSM_LC_TIMEOUT_H,
10358 &buff[1]);
10359 }
10360
10361 return ret;
10362 }
10363
10364 /**
10365 * @brief FSM long counter timeout register (r/w). The long counter
10366 * timeout value is an unsigned integer value (16-bit format).
10367 * When the long counter value reached this value, the FSM generates
10368 * an interrupt.[get]
10369 *
10370 * @param ctx Read / write interface definitions.(ptr)
10371 * @param buff Buffer that stores data read
10372 * @retval Interface status (MANDATORY: return 0 -> no Error).
10373 *
10374 */
ism330dhcx_long_cnt_int_value_get(const stmdev_ctx_t * ctx,uint16_t * val)10375 int32_t ism330dhcx_long_cnt_int_value_get(const stmdev_ctx_t *ctx,
10376 uint16_t *val)
10377 {
10378 uint8_t buff[2];
10379 int32_t ret;
10380
10381 ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_FSM_LC_TIMEOUT_L,
10382 &buff[0]);
10383
10384 if (ret == 0)
10385 {
10386 ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_FSM_LC_TIMEOUT_H,
10387 &buff[1]);
10388 *val = buff[1];
10389 *val = (*val * 256U) + buff[0];
10390 }
10391
10392 return ret;
10393 }
10394
10395 /**
10396 * @brief FSM number of programs register.[set]
10397 *
10398 * @param ctx Read / write interface definitions.(ptr)
10399 * @param buff Buffer that contains data to write
10400 * @retval Interface status (MANDATORY: return 0 -> no Error).
10401 *
10402 */
ism330dhcx_fsm_number_of_programs_set(const stmdev_ctx_t * ctx,uint8_t * buff)10403 int32_t ism330dhcx_fsm_number_of_programs_set(const stmdev_ctx_t *ctx,
10404 uint8_t *buff)
10405 {
10406 int32_t ret;
10407
10408 ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_FSM_PROGRAMS, buff);
10409
10410 if (ret == 0)
10411 {
10412 ret = ism330dhcx_ln_pg_write_byte(ctx,
10413 ISM330DHCX_FSM_PROGRAMS + 0x01U,
10414 buff);
10415 }
10416
10417 return ret;
10418 }
10419
10420 /**
10421 * @brief FSM number of programs register.[get]
10422 *
10423 * @param ctx Read / write interface definitions.(ptr)
10424 * @param buff Buffer that stores data read
10425 * @retval Interface status (MANDATORY: return 0 -> no Error).
10426 *
10427 */
ism330dhcx_fsm_number_of_programs_get(const stmdev_ctx_t * ctx,uint8_t * buff)10428 int32_t ism330dhcx_fsm_number_of_programs_get(const stmdev_ctx_t *ctx,
10429 uint8_t *buff)
10430 {
10431 int32_t ret;
10432
10433 ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_FSM_PROGRAMS, buff);
10434
10435 return ret;
10436 }
10437
10438 /**
10439 * @brief FSM start address register (r/w). First available address is
10440 * 0x033C.[set]
10441 *
10442 * @param ctx Read / write interface definitions.(ptr)
10443 * @param buff Buffer that contains data to write
10444 * @retval Interface status (MANDATORY: return 0 -> no Error).
10445 *
10446 */
ism330dhcx_fsm_start_address_set(const stmdev_ctx_t * ctx,uint16_t val)10447 int32_t ism330dhcx_fsm_start_address_set(const stmdev_ctx_t *ctx,
10448 uint16_t val)
10449 {
10450 uint8_t buff[2];
10451 int32_t ret;
10452
10453 buff[1] = (uint8_t)(val / 256U);
10454 buff[0] = (uint8_t)(val - (buff[1] * 256U));
10455 ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_FSM_START_ADD_L,
10456 &buff[0]);
10457
10458 if (ret == 0)
10459 {
10460 ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_FSM_START_ADD_H,
10461 &buff[1]);
10462 }
10463
10464 return ret;
10465 }
10466
10467 /**
10468 * @brief FSM start address register (r/w). First available address
10469 * is 0x033C.[get]
10470 *
10471 * @param ctx Read / write interface definitions.(ptr)
10472 * @param buff Buffer that stores data read
10473 * @retval Interface status (MANDATORY: return 0 -> no Error).
10474 *
10475 */
ism330dhcx_fsm_start_address_get(const stmdev_ctx_t * ctx,uint16_t * val)10476 int32_t ism330dhcx_fsm_start_address_get(const stmdev_ctx_t *ctx,
10477 uint16_t *val)
10478 {
10479 uint8_t buff[2];
10480 int32_t ret;
10481
10482 ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_FSM_START_ADD_L,
10483 &buff[0]);
10484
10485 if (ret == 0)
10486 {
10487 ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_FSM_START_ADD_H,
10488 &buff[1]);
10489 *val = buff[1];
10490 *val = (*val * 256U) + buff[0];
10491 }
10492
10493 return ret;
10494 }
10495
10496 /**
10497 * @}
10498 *
10499 */
10500
10501 /**
10502 * @addtogroup Machine Learning Core
10503 * @brief This section group all the functions concerning the
10504 * usage of Machine Learning Core
10505 * @{
10506 *
10507 */
10508
10509 /**
10510 * @brief Enable Machine Learning Core.[set]
10511 *
10512 * @param ctx read / write interface definitions
10513 * @param val change the values of mlc_en in
10514 * reg EMB_FUNC_EN_B and mlc_init
10515 * in EMB_FUNC_INIT_B
10516 *
10517 */
ism330dhcx_mlc_set(const stmdev_ctx_t * ctx,uint8_t val)10518 int32_t ism330dhcx_mlc_set(const stmdev_ctx_t *ctx, uint8_t val)
10519 {
10520 ism330dhcx_emb_func_en_b_t reg;
10521 int32_t ret;
10522
10523 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
10524
10525 if (ret == 0)
10526 {
10527 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_EN_B,
10528 (uint8_t *)®, 1);
10529 }
10530
10531 if (ret == 0)
10532 {
10533 reg.mlc_en = val;
10534 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_EMB_FUNC_EN_B,
10535 (uint8_t *)®, 1);
10536 }
10537
10538 if ((val != PROPERTY_DISABLE) && (ret == 0))
10539 {
10540 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_INIT_B,
10541 (uint8_t *)®, 1);
10542
10543 if (ret == 0)
10544 {
10545 reg.mlc_en = val;
10546 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_EMB_FUNC_INIT_B,
10547 (uint8_t *)®, 1);
10548 }
10549 }
10550
10551 if (ret == 0)
10552 {
10553 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
10554 }
10555
10556 return ret;
10557 }
10558
10559 /**
10560 * @brief Enable Machine Learning Core.[get]
10561 *
10562 * @param ctx read / write interface definitions
10563 * @param val Get the values of mlc_en in
10564 * reg EMB_FUNC_EN_B
10565 *
10566 */
ism330dhcx_mlc_get(const stmdev_ctx_t * ctx,uint8_t * val)10567 int32_t ism330dhcx_mlc_get(const stmdev_ctx_t *ctx, uint8_t *val)
10568 {
10569 ism330dhcx_emb_func_en_b_t reg;
10570 int32_t ret;
10571
10572 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
10573
10574 if (ret == 0)
10575 {
10576 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_EN_B,
10577 (uint8_t *)®, 1);
10578 }
10579
10580 if (ret == 0)
10581 {
10582 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
10583 *val = reg.mlc_en;
10584 }
10585
10586 return ret;
10587 }
10588
10589 /**
10590 * @brief Machine Learning Core status register[get]
10591 *
10592 * @param ctx read / write interface definitions
10593 * @param val register MLC_STATUS_MAINPAGE
10594 *
10595 */
ism330dhcx_mlc_status_get(const stmdev_ctx_t * ctx,ism330dhcx_mlc_status_mainpage_t * val)10596 int32_t ism330dhcx_mlc_status_get(const stmdev_ctx_t *ctx,
10597 ism330dhcx_mlc_status_mainpage_t *val)
10598 {
10599 return ism330dhcx_read_reg(ctx, ISM330DHCX_MLC_STATUS_MAINPAGE,
10600 (uint8_t *) val, 1);
10601 }
10602
10603 /**
10604 * @brief Machine Learning Core data rate selection.[set]
10605 *
10606 * @param ctx read / write interface definitions
10607 * @param val get the values of mlc_odr in
10608 * reg EMB_FUNC_ODR_CFG_C
10609 *
10610 */
ism330dhcx_mlc_data_rate_set(const stmdev_ctx_t * ctx,ism330dhcx_mlc_odr_t val)10611 int32_t ism330dhcx_mlc_data_rate_set(const stmdev_ctx_t *ctx,
10612 ism330dhcx_mlc_odr_t val)
10613 {
10614 ism330dhcx_emb_func_odr_cfg_c_t reg;
10615 int32_t ret;
10616
10617 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
10618
10619 if (ret == 0)
10620 {
10621 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_ODR_CFG_C,
10622 (uint8_t *)®, 1);
10623 }
10624
10625 if (ret == 0)
10626 {
10627 reg.mlc_odr = (uint8_t)val;
10628 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_EMB_FUNC_ODR_CFG_C,
10629 (uint8_t *)®, 1);
10630 }
10631
10632 if (ret == 0)
10633 {
10634 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
10635 }
10636
10637 return ret;
10638 }
10639
10640 /**
10641 * @brief Machine Learning Core data rate selection.[get]
10642 *
10643 * @param ctx read / write interface definitions
10644 * @param val change the values of mlc_odr in
10645 * reg EMB_FUNC_ODR_CFG_C
10646 *
10647 */
ism330dhcx_mlc_data_rate_get(const stmdev_ctx_t * ctx,ism330dhcx_mlc_odr_t * val)10648 int32_t ism330dhcx_mlc_data_rate_get(const stmdev_ctx_t *ctx,
10649 ism330dhcx_mlc_odr_t *val)
10650 {
10651 ism330dhcx_emb_func_odr_cfg_c_t reg;
10652 int32_t ret;
10653
10654 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
10655
10656 if (ret == 0)
10657 {
10658 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_ODR_CFG_C,
10659 (uint8_t *)®, 1);
10660 }
10661
10662 if (ret == 0)
10663 {
10664 switch (reg.mlc_odr)
10665 {
10666 case ISM330DHCX_ODR_PRGS_12Hz5:
10667 *val = ISM330DHCX_ODR_PRGS_12Hz5;
10668 break;
10669
10670 case ISM330DHCX_ODR_PRGS_26Hz:
10671 *val = ISM330DHCX_ODR_PRGS_26Hz;
10672 break;
10673
10674 case ISM330DHCX_ODR_PRGS_52Hz:
10675 *val = ISM330DHCX_ODR_PRGS_52Hz;
10676 break;
10677
10678 case ISM330DHCX_ODR_PRGS_104Hz:
10679 *val = ISM330DHCX_ODR_PRGS_104Hz;
10680 break;
10681
10682 default:
10683 *val = ISM330DHCX_ODR_PRGS_12Hz5;
10684 break;
10685 }
10686
10687 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
10688 }
10689
10690 return ret;
10691 }
10692
10693 /**
10694 * @brief prgsens_out: [get] Output value of all MLCx decision trees.
10695 *
10696 * @param ctx_t *ctx: read / write interface definitions
10697 * @param uint8_t * : buffer that stores data read
10698 *
10699 */
ism330dhcx_mlc_out_get(const stmdev_ctx_t * ctx,uint8_t * buff)10700 int32_t ism330dhcx_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff)
10701 {
10702 int32_t ret;
10703
10704 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
10705
10706 if (ret == 0)
10707 {
10708 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_MLC0_SRC, buff, 8);
10709 }
10710
10711 if (ret == 0)
10712 {
10713 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
10714 }
10715
10716 return ret;
10717 }
10718
10719 /**
10720 * @brief External magnetometer sensitivity value register for
10721 * Machine Learning Core.[set]
10722 *
10723 * @param ctx read / write interface definitions
10724 * @param buff buffer that contains data to write
10725 *
10726 */
ism330dhcx_mlc_mag_sensitivity_set(const stmdev_ctx_t * ctx,uint16_t val)10727 int32_t ism330dhcx_mlc_mag_sensitivity_set(const stmdev_ctx_t *ctx,
10728 uint16_t val)
10729 {
10730 uint8_t buff[2];
10731 int32_t ret;
10732
10733 buff[1] = (uint8_t)(val / 256U);
10734 buff[0] = (uint8_t)(val - (buff[1] * 256U));
10735 ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MLC_MAG_SENSITIVITY_L,
10736 &buff[0]);
10737
10738 if (ret == 0)
10739 {
10740 ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MLC_MAG_SENSITIVITY_H,
10741 &buff[1]);
10742 }
10743
10744 return ret;
10745 }
10746
10747 /**
10748 * @brief External magnetometer sensitivity value register for
10749 * Machine Learning Core.[get]
10750 *
10751 * @param ctx read / write interface definitions
10752 * @param buff buffer that stores data read
10753 *
10754 */
ism330dhcx_mlc_mag_sensitivity_get(const stmdev_ctx_t * ctx,uint16_t * val)10755 int32_t ism330dhcx_mlc_mag_sensitivity_get(const stmdev_ctx_t *ctx,
10756 uint16_t *val)
10757 {
10758 uint8_t buff[2];
10759 int32_t ret;
10760
10761 ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MLC_MAG_SENSITIVITY_L,
10762 &buff[0]);
10763
10764 if (ret == 0)
10765 {
10766 ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MLC_MAG_SENSITIVITY_H,
10767 &buff[1]);
10768 *val = buff[1];
10769 *val = (*val * 256U) + buff[0];
10770 }
10771
10772 return ret;
10773 }
10774
10775 /**
10776 * @}
10777 *
10778 */
10779
10780 /**
10781 * @defgroup ISM330DHCX_Sensor_hub
10782 * @brief This section groups all the functions that manage the
10783 * sensor hub.
10784 * @{
10785 *
10786 */
10787
10788 /**
10789 * @brief Sensor hub output registers.[get]
10790 *
10791 * @param ctx Read / write interface definitions.(ptr)
10792 * @param val Structure of registers from SENSOR_HUB_1 to SENSOR_HUB_18
10793 * @retval Interface status (MANDATORY: return 0 -> no Error).
10794 *
10795 */
ism330dhcx_sh_read_data_raw_get(const stmdev_ctx_t * ctx,ism330dhcx_emb_sh_read_t * val,uint8_t len)10796 int32_t ism330dhcx_sh_read_data_raw_get(const stmdev_ctx_t *ctx,
10797 ism330dhcx_emb_sh_read_t *val,
10798 uint8_t len)
10799 {
10800 int32_t ret;
10801
10802 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
10803
10804 if (ret == 0)
10805 {
10806 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_SENSOR_HUB_1,
10807 (uint8_t *)val, len);
10808 }
10809
10810 if (ret == 0)
10811 {
10812 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
10813 }
10814
10815 return ret;
10816 }
10817
10818 /**
10819 * @brief Number of external sensors to be read by the sensor hub.[set]
10820 *
10821 * @param ctx Read / write interface definitions.(ptr)
10822 * @param val Change the values of aux_sens_on in reg MASTER_CONFIG
10823 * @retval Interface status (MANDATORY: return 0 -> no Error).
10824 *
10825 */
ism330dhcx_sh_slave_connected_set(const stmdev_ctx_t * ctx,ism330dhcx_aux_sens_on_t val)10826 int32_t ism330dhcx_sh_slave_connected_set(const stmdev_ctx_t *ctx,
10827 ism330dhcx_aux_sens_on_t val)
10828 {
10829 ism330dhcx_master_config_t master_config;
10830 int32_t ret;
10831
10832 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
10833
10834 if (ret == 0)
10835 {
10836 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_MASTER_CONFIG,
10837 (uint8_t *)&master_config, 1);
10838 }
10839
10840 if (ret == 0)
10841 {
10842 master_config.aux_sens_on = (uint8_t)val;
10843 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_MASTER_CONFIG,
10844 (uint8_t *)&master_config, 1);
10845 }
10846
10847 if (ret == 0)
10848 {
10849 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
10850 }
10851
10852 return ret;
10853 }
10854
10855 /**
10856 * @brief Number of external sensors to be read by the sensor hub.[get]
10857 *
10858 * @param ctx Read / write interface definitions.(ptr)
10859 * @param val Get the values of aux_sens_on in reg MASTER_CONFIG
10860 * @retval Interface status (MANDATORY: return 0 -> no Error).
10861 *
10862 */
ism330dhcx_sh_slave_connected_get(const stmdev_ctx_t * ctx,ism330dhcx_aux_sens_on_t * val)10863 int32_t ism330dhcx_sh_slave_connected_get(const stmdev_ctx_t *ctx,
10864 ism330dhcx_aux_sens_on_t *val)
10865 {
10866 ism330dhcx_master_config_t master_config;
10867 int32_t ret;
10868
10869 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
10870
10871 if (ret == 0)
10872 {
10873 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_MASTER_CONFIG,
10874 (uint8_t *)&master_config, 1);
10875 }
10876
10877 if (ret == 0)
10878 {
10879 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
10880 }
10881
10882 switch (master_config.aux_sens_on)
10883 {
10884 case ISM330DHCX_SLV_0:
10885 *val = ISM330DHCX_SLV_0;
10886 break;
10887
10888 case ISM330DHCX_SLV_0_1:
10889 *val = ISM330DHCX_SLV_0_1;
10890 break;
10891
10892 case ISM330DHCX_SLV_0_1_2:
10893 *val = ISM330DHCX_SLV_0_1_2;
10894 break;
10895
10896 case ISM330DHCX_SLV_0_1_2_3:
10897 *val = ISM330DHCX_SLV_0_1_2_3;
10898 break;
10899
10900 default:
10901 *val = ISM330DHCX_SLV_0;
10902 break;
10903 }
10904
10905 return ret;
10906 }
10907
10908 /**
10909 * @brief Sensor hub I2C master enable.[set]
10910 *
10911 * @param ctx Read / write interface definitions.(ptr)
10912 * @param val Change the values of master_on in reg MASTER_CONFIG
10913 * @retval Interface status (MANDATORY: return 0 -> no Error).
10914 *
10915 */
ism330dhcx_sh_master_set(const stmdev_ctx_t * ctx,uint8_t val)10916 int32_t ism330dhcx_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val)
10917 {
10918 ism330dhcx_master_config_t master_config;
10919 int32_t ret;
10920
10921 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
10922
10923 if (ret == 0)
10924 {
10925 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_MASTER_CONFIG,
10926 (uint8_t *)&master_config, 1);
10927 }
10928
10929 if (ret == 0)
10930 {
10931 master_config.master_on = (uint8_t)val;
10932 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_MASTER_CONFIG,
10933 (uint8_t *)&master_config, 1);
10934 }
10935
10936 if (ret == 0)
10937 {
10938 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
10939 }
10940
10941 return ret;
10942 }
10943
10944 /**
10945 * @brief Sensor hub I2C master enable.[get]
10946 *
10947 * @param ctx Read / write interface definitions.(ptr)
10948 * @param val Change the values of master_on in reg MASTER_CONFIG
10949 * @retval Interface status (MANDATORY: return 0 -> no Error).
10950 *
10951 */
ism330dhcx_sh_master_get(const stmdev_ctx_t * ctx,uint8_t * val)10952 int32_t ism330dhcx_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val)
10953 {
10954 ism330dhcx_master_config_t master_config;
10955 int32_t ret;
10956
10957 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
10958
10959 if (ret == 0)
10960 {
10961 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_MASTER_CONFIG,
10962 (uint8_t *)&master_config, 1);
10963 }
10964
10965 if (ret == 0)
10966 {
10967 *val = master_config.master_on;
10968 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
10969 }
10970
10971 return ret;
10972 }
10973
10974 /**
10975 * @brief Master I2C pull-up enable.[set]
10976 *
10977 * @param ctx Read / write interface definitions.(ptr)
10978 * @param val Change the values of shub_pu_en in reg MASTER_CONFIG
10979 * @retval Interface status (MANDATORY: return 0 -> no Error).
10980 *
10981 */
ism330dhcx_sh_pin_mode_set(const stmdev_ctx_t * ctx,ism330dhcx_shub_pu_en_t val)10982 int32_t ism330dhcx_sh_pin_mode_set(const stmdev_ctx_t *ctx,
10983 ism330dhcx_shub_pu_en_t val)
10984 {
10985 ism330dhcx_master_config_t master_config;
10986 int32_t ret;
10987
10988 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
10989
10990 if (ret == 0)
10991 {
10992 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_MASTER_CONFIG,
10993 (uint8_t *)&master_config, 1);
10994 }
10995
10996 if (ret == 0)
10997 {
10998 master_config.shub_pu_en = (uint8_t)val;
10999 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_MASTER_CONFIG,
11000 (uint8_t *)&master_config, 1);
11001 }
11002
11003 if (ret == 0)
11004 {
11005 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
11006 }
11007
11008 return ret;
11009 }
11010
11011 /**
11012 * @brief Master I2C pull-up enable.[get]
11013 *
11014 * @param ctx Read / write interface definitions.(ptr)
11015 * @param val Get the values of shub_pu_en in reg MASTER_CONFIG
11016 * @retval Interface status (MANDATORY: return 0 -> no Error).
11017 *
11018 */
ism330dhcx_sh_pin_mode_get(const stmdev_ctx_t * ctx,ism330dhcx_shub_pu_en_t * val)11019 int32_t ism330dhcx_sh_pin_mode_get(const stmdev_ctx_t *ctx,
11020 ism330dhcx_shub_pu_en_t *val)
11021 {
11022 ism330dhcx_master_config_t master_config;
11023 int32_t ret;
11024
11025 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
11026
11027 if (ret == 0)
11028 {
11029 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_MASTER_CONFIG,
11030 (uint8_t *)&master_config, 1);
11031 }
11032
11033 if (ret == 0)
11034 {
11035 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
11036 }
11037
11038 switch (master_config.shub_pu_en)
11039 {
11040 case ISM330DHCX_EXT_PULL_UP:
11041 *val = ISM330DHCX_EXT_PULL_UP;
11042 break;
11043
11044 case ISM330DHCX_INTERNAL_PULL_UP:
11045 *val = ISM330DHCX_INTERNAL_PULL_UP;
11046 break;
11047
11048 default:
11049 *val = ISM330DHCX_EXT_PULL_UP;
11050 break;
11051 }
11052
11053 return ret;
11054 }
11055
11056 /**
11057 * @brief I2C interface pass-through.[set]
11058 *
11059 * @param ctx Read / write interface definitions.(ptr)
11060 * @param val Change the values of pass_through_mode in reg MASTER_CONFIG
11061 * @retval Interface status (MANDATORY: return 0 -> no Error).
11062 *
11063 */
ism330dhcx_sh_pass_through_set(const stmdev_ctx_t * ctx,uint8_t val)11064 int32_t ism330dhcx_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val)
11065 {
11066 ism330dhcx_master_config_t master_config;
11067 int32_t ret;
11068
11069 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
11070
11071 if (ret == 0)
11072 {
11073 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_MASTER_CONFIG,
11074 (uint8_t *)&master_config, 1);
11075 }
11076
11077 if (ret == 0)
11078 {
11079 master_config.pass_through_mode = (uint8_t)val;
11080 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_MASTER_CONFIG,
11081 (uint8_t *)&master_config, 1);
11082 }
11083
11084 if (ret == 0)
11085 {
11086 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
11087 }
11088
11089 return ret;
11090 }
11091
11092 /**
11093 * @brief I2C interface pass-through.[get]
11094 *
11095 * @param ctx Read / write interface definitions.(ptr)
11096 * @param val Change the values of pass_through_mode in reg MASTER_CONFIG
11097 * @retval Interface status (MANDATORY: return 0 -> no Error).
11098 *
11099 */
ism330dhcx_sh_pass_through_get(const stmdev_ctx_t * ctx,uint8_t * val)11100 int32_t ism330dhcx_sh_pass_through_get(const stmdev_ctx_t *ctx,
11101 uint8_t *val)
11102 {
11103 ism330dhcx_master_config_t master_config;
11104 int32_t ret;
11105
11106 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
11107
11108 if (ret == 0)
11109 {
11110 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_MASTER_CONFIG,
11111 (uint8_t *)&master_config, 1);
11112 }
11113
11114 if (ret == 0)
11115 {
11116 *val = master_config.pass_through_mode;
11117 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
11118 }
11119
11120 return ret;
11121 }
11122
11123 /**
11124 * @brief Sensor hub trigger signal selection.[set]
11125 *
11126 * @param ctx Read / write interface definitions.(ptr)
11127 * @param val Change the values of start_config in reg MASTER_CONFIG
11128 * @retval Interface status (MANDATORY: return 0 -> no Error).
11129 *
11130 */
ism330dhcx_sh_syncro_mode_set(const stmdev_ctx_t * ctx,ism330dhcx_start_config_t val)11131 int32_t ism330dhcx_sh_syncro_mode_set(const stmdev_ctx_t *ctx,
11132 ism330dhcx_start_config_t val)
11133 {
11134 ism330dhcx_master_config_t master_config;
11135 int32_t ret;
11136
11137 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
11138
11139 if (ret == 0)
11140 {
11141 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_MASTER_CONFIG,
11142 (uint8_t *)&master_config, 1);
11143 }
11144
11145 if (ret == 0)
11146 {
11147 master_config.start_config = (uint8_t)val;
11148 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_MASTER_CONFIG,
11149 (uint8_t *)&master_config, 1);
11150 }
11151
11152 if (ret == 0)
11153 {
11154 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
11155 }
11156
11157 return ret;
11158 }
11159
11160 /**
11161 * @brief Sensor hub trigger signal selection.[get]
11162 *
11163 * @param ctx Read / write interface definitions.(ptr)
11164 * @param val Get the values of start_config in reg MASTER_CONFIG
11165 * @retval Interface status (MANDATORY: return 0 -> no Error).
11166 *
11167 */
ism330dhcx_sh_syncro_mode_get(const stmdev_ctx_t * ctx,ism330dhcx_start_config_t * val)11168 int32_t ism330dhcx_sh_syncro_mode_get(const stmdev_ctx_t *ctx,
11169 ism330dhcx_start_config_t *val)
11170 {
11171 ism330dhcx_master_config_t master_config;
11172 int32_t ret;
11173
11174 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
11175
11176 if (ret == 0)
11177 {
11178 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_MASTER_CONFIG,
11179 (uint8_t *)&master_config, 1);
11180 }
11181
11182 if (ret == 0)
11183 {
11184 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
11185 }
11186
11187 switch (master_config.start_config)
11188 {
11189 case ISM330DHCX_EXT_ON_INT2_PIN:
11190 *val = ISM330DHCX_EXT_ON_INT2_PIN;
11191 break;
11192
11193 case ISM330DHCX_XL_GY_DRDY:
11194 *val = ISM330DHCX_XL_GY_DRDY;
11195 break;
11196
11197 default:
11198 *val = ISM330DHCX_EXT_ON_INT2_PIN;
11199 break;
11200 }
11201
11202 return ret;
11203 }
11204
11205 /**
11206 * @brief Slave 0 write operation is performed only at the first sensor
11207 * hub cycle.[set]
11208 *
11209 * @param ctx Read / write interface definitions.(ptr)
11210 * @param val Change the values of write_once in reg MASTER_CONFIG
11211 * @retval Interface status (MANDATORY: return 0 -> no Error).
11212 *
11213 */
ism330dhcx_sh_write_mode_set(const stmdev_ctx_t * ctx,ism330dhcx_write_once_t val)11214 int32_t ism330dhcx_sh_write_mode_set(const stmdev_ctx_t *ctx,
11215 ism330dhcx_write_once_t val)
11216 {
11217 ism330dhcx_master_config_t master_config;
11218 int32_t ret;
11219
11220 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
11221
11222 if (ret == 0)
11223 {
11224 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_MASTER_CONFIG,
11225 (uint8_t *)&master_config, 1);
11226 }
11227
11228 if (ret == 0)
11229 {
11230 master_config.write_once = (uint8_t)val;
11231 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_MASTER_CONFIG,
11232 (uint8_t *)&master_config, 1);
11233 }
11234
11235 if (ret == 0)
11236 {
11237 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
11238 }
11239
11240 return ret;
11241 }
11242
11243 /**
11244 * @brief Slave 0 write operation is performed only at the first sensor
11245 * hub cycle.[get]
11246 *
11247 * @param ctx Read / write interface definitions.(ptr)
11248 * @param val Get the values of write_once in reg MASTER_CONFIG
11249 * @retval Interface status (MANDATORY: return 0 -> no Error).
11250 *
11251 */
ism330dhcx_sh_write_mode_get(const stmdev_ctx_t * ctx,ism330dhcx_write_once_t * val)11252 int32_t ism330dhcx_sh_write_mode_get(const stmdev_ctx_t *ctx,
11253 ism330dhcx_write_once_t *val)
11254 {
11255 ism330dhcx_master_config_t master_config;
11256 int32_t ret;
11257
11258 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
11259
11260 if (ret == 0)
11261 {
11262 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_MASTER_CONFIG,
11263 (uint8_t *)&master_config, 1);
11264 }
11265
11266 if (ret == 0)
11267 {
11268 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
11269 }
11270
11271 switch (master_config.write_once)
11272 {
11273 case ISM330DHCX_EACH_SH_CYCLE:
11274 *val = ISM330DHCX_EACH_SH_CYCLE;
11275 break;
11276
11277 case ISM330DHCX_ONLY_FIRST_CYCLE:
11278 *val = ISM330DHCX_ONLY_FIRST_CYCLE;
11279 break;
11280
11281 default:
11282 *val = ISM330DHCX_EACH_SH_CYCLE;
11283 break;
11284 }
11285
11286 return ret;
11287 }
11288
11289 /**
11290 * @brief Reset Master logic and output registers.[set]
11291 *
11292 * @param ctx Read / write interface definitions.(ptr)
11293 * @retval Interface status (MANDATORY: return 0 -> no Error).
11294 *
11295 */
ism330dhcx_sh_reset_set(const stmdev_ctx_t * ctx)11296 int32_t ism330dhcx_sh_reset_set(const stmdev_ctx_t *ctx)
11297 {
11298 ism330dhcx_master_config_t master_config;
11299 int32_t ret;
11300
11301 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
11302
11303 if (ret == 0)
11304 {
11305 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_MASTER_CONFIG,
11306 (uint8_t *)&master_config, 1);
11307 }
11308
11309 if (ret == 0)
11310 {
11311 master_config.rst_master_regs = PROPERTY_ENABLE;
11312 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_MASTER_CONFIG,
11313 (uint8_t *)&master_config, 1);
11314 }
11315
11316 if (ret == 0)
11317 {
11318 master_config.rst_master_regs = PROPERTY_DISABLE;
11319 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_MASTER_CONFIG,
11320 (uint8_t *)&master_config, 1);
11321 }
11322
11323 if (ret == 0)
11324 {
11325 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
11326 }
11327
11328 return ret;
11329 }
11330
11331 /**
11332 * @brief Reset Master logic and output registers.[get]
11333 *
11334 * @param ctx Read / write interface definitions.(ptr)
11335 * @param val Change the values of rst_master_regs in reg MASTER_CONFIG
11336 * @retval Interface status (MANDATORY: return 0 -> no Error).
11337 *
11338 */
ism330dhcx_sh_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)11339 int32_t ism330dhcx_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
11340 {
11341 ism330dhcx_master_config_t master_config;
11342 int32_t ret;
11343
11344 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
11345
11346 if (ret == 0)
11347 {
11348 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_MASTER_CONFIG,
11349 (uint8_t *)&master_config, 1);
11350 *val = master_config.rst_master_regs;
11351 }
11352
11353 if (ret == 0)
11354 {
11355 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
11356 }
11357
11358 return ret;
11359 }
11360
11361 /**
11362 * @brief Rate at which the master communicates.[set]
11363 *
11364 * @param ctx Read / write interface definitions.(ptr)
11365 * @param val Change the values of shub_odr in reg SLV0_CONFIG
11366 * @retval Interface status (MANDATORY: return 0 -> no Error).
11367 *
11368 */
ism330dhcx_sh_data_rate_set(const stmdev_ctx_t * ctx,ism330dhcx_shub_odr_t val)11369 int32_t ism330dhcx_sh_data_rate_set(const stmdev_ctx_t *ctx,
11370 ism330dhcx_shub_odr_t val)
11371 {
11372 ism330dhcx_slv0_config_t slv0_config;
11373 int32_t ret;
11374
11375 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
11376
11377 if (ret == 0)
11378 {
11379 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_SLV0_CONFIG,
11380 (uint8_t *)&slv0_config, 1);
11381 }
11382
11383 if (ret == 0)
11384 {
11385 slv0_config.shub_odr = (uint8_t)val;
11386 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_SLV0_CONFIG,
11387 (uint8_t *)&slv0_config, 1);
11388 }
11389
11390 if (ret == 0)
11391 {
11392 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
11393 }
11394
11395 return ret;
11396 }
11397
11398 /**
11399 * @brief Rate at which the master communicates.[get]
11400 *
11401 * @param ctx Read / write interface definitions.(ptr)
11402 * @param val Get the values of shub_odr in reg slv1_CONFIG
11403 * @retval Interface status (MANDATORY: return 0 -> no Error).
11404 *
11405 */
ism330dhcx_sh_data_rate_get(const stmdev_ctx_t * ctx,ism330dhcx_shub_odr_t * val)11406 int32_t ism330dhcx_sh_data_rate_get(const stmdev_ctx_t *ctx,
11407 ism330dhcx_shub_odr_t *val)
11408 {
11409 ism330dhcx_slv0_config_t slv0_config;
11410 int32_t ret;
11411
11412 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
11413
11414 if (ret == 0)
11415 {
11416 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_SLV0_CONFIG,
11417 (uint8_t *)&slv0_config, 1);
11418 }
11419
11420 if (ret == 0)
11421 {
11422 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
11423 }
11424
11425 switch (slv0_config.shub_odr)
11426 {
11427 case ISM330DHCX_SH_ODR_104Hz:
11428 *val = ISM330DHCX_SH_ODR_104Hz;
11429 break;
11430
11431 case ISM330DHCX_SH_ODR_52Hz:
11432 *val = ISM330DHCX_SH_ODR_52Hz;
11433 break;
11434
11435 case ISM330DHCX_SH_ODR_26Hz:
11436 *val = ISM330DHCX_SH_ODR_26Hz;
11437 break;
11438
11439 case ISM330DHCX_SH_ODR_13Hz:
11440 *val = ISM330DHCX_SH_ODR_13Hz;
11441 break;
11442
11443 default:
11444 *val = ISM330DHCX_SH_ODR_104Hz;
11445 break;
11446 }
11447
11448 return ret;
11449 }
11450
11451 /**
11452 * @brief Configure slave 0 for perform a write.[set]
11453 *
11454 * @param ctx Read / write interface definitions.(ptr)
11455 * @param val Structure that contain
11456 * - uint8_t slv0_add; 8 bit i2c device address
11457 * - uint8_t slv0_subadd; 8 bit register device address
11458 * - uint8_t slv0_data; 8 bit data to write
11459 * @retval Interface status (MANDATORY: return 0 -> no Error).
11460 *
11461 */
ism330dhcx_sh_cfg_write(const stmdev_ctx_t * ctx,ism330dhcx_sh_cfg_write_t * val)11462 int32_t ism330dhcx_sh_cfg_write(const stmdev_ctx_t *ctx,
11463 ism330dhcx_sh_cfg_write_t *val)
11464 {
11465 ism330dhcx_slv0_add_t slv0_add;
11466 int32_t ret;
11467
11468 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
11469
11470 if (ret == 0)
11471 {
11472 slv0_add.slave0 = (uint8_t)(val->slv0_add >> 1);
11473 slv0_add.rw_0 = 0;
11474 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_SLV0_ADD,
11475 (uint8_t *) & (slv0_add), 1);
11476 }
11477
11478 if (ret == 0)
11479 {
11480 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_SLV0_SUBADD,
11481 (uint8_t *) & (val->slv0_subadd), 1);
11482 }
11483
11484 if (ret == 0)
11485 {
11486 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_DATAWRITE_SLV0,
11487 (uint8_t *) & (val->slv0_data), 1);
11488 }
11489
11490 if (ret == 0)
11491 {
11492 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
11493 }
11494
11495 return ret;
11496 }
11497
11498 /**
11499 * @brief Configure slave 0 for perform a write/read.[get]
11500 *
11501 * @param ctx Read / write interface definitions.(ptr)
11502 * @param val Structure that contain
11503 * - uint8_t slv_add; 8 bit i2c device address
11504 * - uint8_t slv_subadd; 8 bit register device address
11505 * - uint8_t slv_len; num of bit to read
11506 * @retval Interface status (MANDATORY: return 0 -> no Error).
11507 *
11508 */
ism330dhcx_sh_slv0_cfg_read(const stmdev_ctx_t * ctx,ism330dhcx_sh_cfg_read_t * val)11509 int32_t ism330dhcx_sh_slv0_cfg_read(const stmdev_ctx_t *ctx,
11510 ism330dhcx_sh_cfg_read_t *val)
11511 {
11512 ism330dhcx_slv0_config_t slv0_config;
11513 ism330dhcx_slv0_add_t slv0_add;
11514 int32_t ret;
11515
11516 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
11517
11518 if (ret == 0)
11519 {
11520 slv0_add.slave0 = (uint8_t) val->slv_add >> 1;
11521 slv0_add.rw_0 = 1;
11522 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_SLV0_ADD,
11523 (uint8_t *) & (slv0_add), 1);
11524 }
11525
11526 if (ret == 0)
11527 {
11528 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_SLV0_SUBADD,
11529 &(val->slv_subadd), 1);
11530 }
11531
11532 if (ret == 0)
11533 {
11534 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_SLV0_CONFIG,
11535 (uint8_t *)&slv0_config, 1);
11536 }
11537
11538 if (ret == 0)
11539 {
11540 slv0_config.slave0_numop = val->slv_len;
11541 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_SLV0_CONFIG,
11542 (uint8_t *)&slv0_config, 1);
11543 }
11544
11545 if (ret == 0)
11546 {
11547 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
11548 }
11549
11550 return ret;
11551 }
11552
11553 /**
11554 * @brief Configure slave 0 for perform a write/read.[get]
11555 *
11556 * @param ctx Read / write interface definitions.(ptr)
11557 * @param val Structure that contain
11558 * - uint8_t slv_add; 8 bit i2c device address
11559 * - uint8_t slv_subadd; 8 bit register device address
11560 * - uint8_t slv_len; num of bit to read
11561 * @retval Interface status (MANDATORY: return 0 -> no Error).
11562 *
11563 */
ism330dhcx_sh_slv1_cfg_read(const stmdev_ctx_t * ctx,ism330dhcx_sh_cfg_read_t * val)11564 int32_t ism330dhcx_sh_slv1_cfg_read(const stmdev_ctx_t *ctx,
11565 ism330dhcx_sh_cfg_read_t *val)
11566 {
11567 ism330dhcx_slv1_config_t slv1_config;
11568 ism330dhcx_slv1_add_t slv1_add;
11569 int32_t ret;
11570
11571 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
11572
11573 if (ret == 0)
11574 {
11575 slv1_add.slave1_add = (uint8_t)(val->slv_add >> 1);
11576 slv1_add.r_1 = 1;
11577 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_SLV1_ADD,
11578 (uint8_t *)&slv1_add, 1);
11579 }
11580
11581 if (ret == 0)
11582 {
11583 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_SLV1_SUBADD,
11584 &(val->slv_subadd), 1);
11585 }
11586
11587 if (ret == 0)
11588 {
11589 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_SLV1_CONFIG,
11590 (uint8_t *)&slv1_config, 1);
11591 }
11592
11593 if (ret == 0)
11594 {
11595 slv1_config.slave1_numop = val->slv_len;
11596 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_SLV1_CONFIG,
11597 (uint8_t *)&slv1_config, 1);
11598 }
11599
11600 if (ret == 0)
11601 {
11602 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
11603 }
11604
11605 return ret;
11606 }
11607
11608 /**
11609 * @brief Configure slave 2 for perform a write/read.[get]
11610 *
11611 * @param ctx Read / write interface definitions.(ptr)
11612 * @param val Structure that contain
11613 * - uint8_t slv_add; 8 bit i2c device address
11614 * - uint8_t slv_subadd; 8 bit register device address
11615 * - uint8_t slv_len; num of bit to read
11616 * @retval Interface status (MANDATORY: return 0 -> no Error).
11617 *
11618 */
ism330dhcx_sh_slv2_cfg_read(const stmdev_ctx_t * ctx,ism330dhcx_sh_cfg_read_t * val)11619 int32_t ism330dhcx_sh_slv2_cfg_read(const stmdev_ctx_t *ctx,
11620 ism330dhcx_sh_cfg_read_t *val)
11621 {
11622 ism330dhcx_slv2_config_t slv2_config;
11623 ism330dhcx_slv2_add_t slv2_add;
11624 int32_t ret;
11625
11626 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
11627
11628 if (ret == 0)
11629 {
11630 slv2_add.slave2_add = (uint8_t)(val->slv_add >> 1);
11631 slv2_add.r_2 = 1;
11632 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_SLV2_ADD,
11633 (uint8_t *)&slv2_add, 1);
11634 }
11635
11636 if (ret == 0)
11637 {
11638 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_SLV2_SUBADD,
11639 (uint8_t *) & (val->slv_subadd), 1);
11640 }
11641
11642 if (ret == 0)
11643 {
11644 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_SLV2_CONFIG,
11645 (uint8_t *)&slv2_config, 1);
11646 }
11647
11648 if (ret == 0)
11649 {
11650 slv2_config.slave2_numop = val->slv_len;
11651 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_SLV2_CONFIG,
11652 (uint8_t *)&slv2_config, 1);
11653 }
11654
11655 if (ret == 0)
11656 {
11657 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
11658 }
11659
11660 return ret;
11661 }
11662
11663 /**
11664 * @brief Configure slave 3 for perform a write/read.[get]
11665 *
11666 * @param ctx Read / write interface definitions.(ptr)
11667 * @param val Structure that contain
11668 * - uint8_t slv_add; 8 bit i2c device address
11669 * - uint8_t slv_subadd; 8 bit register device address
11670 * - uint8_t slv_len; num of bit to read
11671 * @retval Interface status (MANDATORY: return 0 -> no Error).
11672 *
11673 */
ism330dhcx_sh_slv3_cfg_read(const stmdev_ctx_t * ctx,ism330dhcx_sh_cfg_read_t * val)11674 int32_t ism330dhcx_sh_slv3_cfg_read(const stmdev_ctx_t *ctx,
11675 ism330dhcx_sh_cfg_read_t *val)
11676 {
11677 ism330dhcx_slv3_config_t slv3_config;
11678 ism330dhcx_slv3_add_t slv3_add;
11679 int32_t ret;
11680
11681 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
11682
11683 if (ret == 0)
11684 {
11685 slv3_add.slave3_add = (uint8_t)(val->slv_add >> 1);
11686 slv3_add.r_3 = 1;
11687 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_SLV3_ADD,
11688 (uint8_t *)&slv3_add, 1);
11689 }
11690
11691 if (ret == 0)
11692 {
11693 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_SLV3_SUBADD,
11694 &(val->slv_subadd), 1);
11695 }
11696
11697 if (ret == 0)
11698 {
11699 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_SLV3_CONFIG,
11700 (uint8_t *)&slv3_config, 1);
11701 }
11702
11703 if (ret == 0)
11704 {
11705 slv3_config.slave3_numop = val->slv_len;
11706 ret = ism330dhcx_write_reg(ctx, ISM330DHCX_SLV3_CONFIG,
11707 (uint8_t *)&slv3_config, 1);
11708 }
11709
11710 if (ret == 0)
11711 {
11712 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
11713 }
11714
11715 return ret;
11716 }
11717
11718 /**
11719 * @brief Sensor hub source register.[get]
11720 *
11721 * @param ctx Read / write interface definitions.(ptr)
11722 * @param val Registers from STATUS_MASTER
11723 * @retval Interface status (MANDATORY: return 0 -> no Error).
11724 *
11725 */
ism330dhcx_sh_status_get(const stmdev_ctx_t * ctx,ism330dhcx_status_master_t * val)11726 int32_t ism330dhcx_sh_status_get(const stmdev_ctx_t *ctx,
11727 ism330dhcx_status_master_t *val)
11728 {
11729 int32_t ret;
11730
11731 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
11732
11733 if (ret == 0)
11734 {
11735 ret = ism330dhcx_read_reg(ctx, ISM330DHCX_STATUS_MASTER,
11736 (uint8_t *)val, 1);
11737 }
11738
11739 if (ret == 0)
11740 {
11741 ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
11742 }
11743
11744 return ret;
11745 }
11746
11747 /**
11748 * @}
11749 *
11750 */
11751
11752 /**
11753 * @}
11754 *
11755 */
11756
11757 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
11758
