1 /** 2 ****************************************************************************** 3 * @file iis3dwb_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * iis3dwb_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef IIS3DWB_REGS_H 23 #define IIS3DWB_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup IIS3DWB 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup IIS3DWB Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ 172 #define IIS3DWB_I2C_ADD_L 0xD5U 173 #define IIS3DWB_I2C_ADD_H 0xD7U 174 175 /** Device Identification (Who am I) **/ 176 #define IIS3DWB_ID 0x7BU 177 178 /** 179 * @} 180 * 181 */ 182 183 #define IIS3DWB_PIN_CTRL 0x02U 184 typedef struct 185 { 186 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 187 uint8_t not_used_01 : 6; 188 uint8_t sdo_pu_en : 1; 189 uint8_t not_used_02 : 1; 190 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 191 uint8_t not_used_02 : 1; 192 uint8_t sdo_pu_en : 1; 193 uint8_t not_used_01 : 6; 194 #endif /* DRV_BYTE_ORDER */ 195 } iis3dwb_pin_ctrl_t; 196 197 #define IIS3DWB_FIFO_CTRL1 0x07U 198 typedef struct 199 { 200 uint8_t wtm : 8; 201 } iis3dwb_fifo_ctrl1_t; 202 203 #define IIS3DWB_FIFO_CTRL2 0x08U 204 typedef struct 205 { 206 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 207 uint8_t wtm : 1; 208 uint8_t not_used_01 : 6; 209 uint8_t stop_on_wtm : 1; 210 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 211 uint8_t stop_on_wtm : 1; 212 uint8_t not_used_01 : 6; 213 uint8_t wtm : 1; 214 #endif /* DRV_BYTE_ORDER */ 215 } iis3dwb_fifo_ctrl2_t; 216 217 #define IIS3DWB_FIFO_CTRL3 0x09U 218 typedef struct 219 { 220 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 221 uint8_t bdr_xl : 4; 222 uint8_t not_used_01 : 4; 223 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 224 uint8_t not_used_01 : 4; 225 uint8_t bdr_xl : 4; 226 #endif /* DRV_BYTE_ORDER */ 227 } iis3dwb_fifo_ctrl3_t; 228 229 #define IIS3DWB_FIFO_CTRL4 0x0AU 230 typedef struct 231 { 232 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 233 uint8_t fifo_mode : 3; 234 uint8_t not_used_01 : 1; 235 uint8_t odr_t_batch : 2; 236 uint8_t odr_ts_batch : 2; 237 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 238 uint8_t odr_ts_batch : 2; 239 uint8_t odr_t_batch : 2; 240 uint8_t not_used_01 : 1; 241 uint8_t fifo_mode : 3; 242 #endif /* DRV_BYTE_ORDER */ 243 } iis3dwb_fifo_ctrl4_t; 244 245 #define IIS3DWB_COUNTER_BDR_REG1 0x0BU 246 typedef struct 247 { 248 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 249 uint8_t cnt_bdr_th : 3; 250 uint8_t not_used_01 : 3; 251 uint8_t rst_counter_bdr : 1; 252 uint8_t dataready_pulsed : 1; 253 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 254 uint8_t dataready_pulsed : 1; 255 uint8_t rst_counter_bdr : 1; 256 uint8_t not_used_01 : 3; 257 uint8_t cnt_bdr_th : 3; 258 #endif /* DRV_BYTE_ORDER */ 259 } iis3dwb_counter_bdr_reg1_t; 260 261 #define IIS3DWB_COUNTER_BDR_REG2 0x0CU 262 typedef struct 263 { 264 uint8_t cnt_bdr_th : 8; 265 } iis3dwb_counter_bdr_reg2_t; 266 267 #define IIS3DWB_INT1_CTRL 0x0DU 268 typedef struct 269 { 270 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 271 uint8_t int1_drdy_xl : 1; 272 uint8_t not_used_01 : 1; 273 uint8_t int1_boot : 1; 274 uint8_t int1_fifo_th : 1; 275 uint8_t int1_fifo_ovr : 1; 276 uint8_t int1_fifo_full : 1; 277 uint8_t int1_cnt_bdr : 1; 278 uint8_t not_used_02 : 1; 279 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 280 uint8_t not_used_02 : 1; 281 uint8_t int1_cnt_bdr : 1; 282 uint8_t int1_fifo_full : 1; 283 uint8_t int1_fifo_ovr : 1; 284 uint8_t int1_fifo_th : 1; 285 uint8_t int1_boot : 1; 286 uint8_t not_used_01 : 1; 287 uint8_t int1_drdy_xl : 1; 288 #endif /* DRV_BYTE_ORDER */ 289 } iis3dwb_int1_ctrl_t; 290 291 #define IIS3DWB_INT2_CTRL 0x0EU 292 typedef struct 293 { 294 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 295 uint8_t int2_drdy_xl : 1; 296 uint8_t not_used_01 : 1; 297 uint8_t int2_drdy_temp : 1; 298 uint8_t int2_fifo_th : 1; 299 uint8_t int2_fifo_ovr : 1; 300 uint8_t int2_fifo_full : 1; 301 uint8_t int2_cnt_bdr : 1; 302 uint8_t not_used_02 : 1; 303 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 304 uint8_t not_used_02 : 1; 305 uint8_t int2_cnt_bdr : 1; 306 uint8_t int2_fifo_full : 1; 307 uint8_t int2_fifo_ovr : 1; 308 uint8_t int2_fifo_th : 1; 309 uint8_t int2_drdy_temp : 1; 310 uint8_t not_used_01 : 1; 311 uint8_t int2_drdy_xl : 1; 312 #endif /* DRV_BYTE_ORDER */ 313 } iis3dwb_int2_ctrl_t; 314 315 #define IIS3DWB_WHO_AM_I 0x0FU 316 #define IIS3DWB_CTRL1_XL 0x10U 317 typedef struct 318 { 319 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 320 uint8_t not_used_01 : 1; 321 uint8_t lpf2_xl_en : 1; 322 uint8_t fs_xl : 2; 323 uint8_t not_used_02 : 1; 324 uint8_t xl_en : 3; 325 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 326 uint8_t xl_en : 3; 327 uint8_t not_used_02 : 1; 328 uint8_t fs_xl : 2; 329 uint8_t lpf2_xl_en : 1; 330 uint8_t not_used_01 : 1; 331 #endif /* DRV_BYTE_ORDER */ 332 } iis3dwb_ctrl1_xl_t; 333 334 #define IIS3DWB_CTRL3_C 0x12U 335 typedef struct 336 { 337 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 338 uint8_t sw_reset : 1; 339 uint8_t not_used_01 : 1; 340 uint8_t if_inc : 1; 341 uint8_t sim : 1; 342 uint8_t pp_od : 1; 343 uint8_t h_lactive : 1; 344 uint8_t bdu : 1; 345 uint8_t boot : 1; 346 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 347 uint8_t boot : 1; 348 uint8_t bdu : 1; 349 uint8_t h_lactive : 1; 350 uint8_t pp_od : 1; 351 uint8_t sim : 1; 352 uint8_t if_inc : 1; 353 uint8_t not_used_01 : 1; 354 uint8_t sw_reset : 1; 355 #endif /* DRV_BYTE_ORDER */ 356 } iis3dwb_ctrl3_c_t; 357 358 #define IIS3DWB_CTRL4_C 0x13U 359 typedef struct 360 { 361 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 362 uint8_t _1ax_to_3regout : 1; 363 uint8_t lpf1_sel_g : 1; 364 uint8_t i2c_disable : 1; 365 uint8_t drdy_mask : 1; 366 uint8_t not_used_02 : 1; 367 uint8_t int2_on_int1 : 1; 368 uint8_t not_used_03 : 2; 369 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 370 uint8_t not_used_03 : 2; 371 uint8_t int2_on_int1 : 1; 372 uint8_t not_used_02 : 1; 373 uint8_t drdy_mask : 1; 374 uint8_t i2c_disable : 1; 375 uint8_t lpf1_sel_g : 1; 376 uint8_t _1ax_to_3regout : 1; 377 #endif /* DRV_BYTE_ORDER */ 378 } iis3dwb_ctrl4_c_t; 379 380 #define IIS3DWB_CTRL5_C 0x14U 381 typedef struct 382 { 383 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 384 uint8_t st_xl : 2; 385 uint8_t not_used_01 : 3; 386 uint8_t rounding : 2; 387 uint8_t not_used_02 : 1; 388 uint8_t i2c_disable : 1; 389 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 390 uint8_t i2c_disable : 1; 391 uint8_t not_used_02 : 1; 392 uint8_t rounding : 2; 393 uint8_t not_used_01 : 3; 394 uint8_t st_xl : 2; 395 #endif /* DRV_BYTE_ORDER */ 396 } iis3dwb_ctrl5_c_t; 397 398 #define IIS3DWB_CTRL6_C 0x15U 399 typedef struct 400 { 401 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 402 uint8_t xl_axis_sel : 2; 403 uint8_t not_used_01 : 1; 404 uint8_t usr_off_w : 1; 405 uint8_t not_used_02 : 4; 406 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 407 uint8_t not_used_02 : 4; 408 uint8_t usr_off_w : 1; 409 uint8_t not_used_01 : 1; 410 uint8_t xl_axis_sel : 2; 411 #endif /* DRV_BYTE_ORDER */ 412 } iis3dwb_ctrl6_c_t; 413 #define IIS3DWB_CTRL7_C 0x16U 414 typedef struct 415 { 416 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 417 uint8_t not_used_01 : 1; 418 uint8_t usr_off_on_out : 1; 419 uint8_t not_used_02 : 6; 420 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 421 uint8_t not_used_02 : 6; 422 uint8_t usr_off_on_out : 1; 423 uint8_t not_used_01 : 1; 424 #endif /* DRV_BYTE_ORDER */ 425 } iis3dwb_ctrl7_c_t; 426 427 #define IIS3DWB_CTRL8_XL 0x17U 428 typedef struct 429 { 430 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 431 uint8_t not_used_01 : 2; 432 uint8_t fds : 1; 433 uint8_t fastsettl_mode_xl : 1; 434 uint8_t hp_ref_mode_xl : 1; 435 uint8_t hpcf_xl : 3; 436 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 437 uint8_t hpcf_xl : 3; 438 uint8_t hp_ref_mode_xl : 1; 439 uint8_t fastsettl_mode_xl : 1; 440 uint8_t fds : 1; 441 uint8_t not_used_01 : 2; 442 #endif /* DRV_BYTE_ORDER */ 443 } iis3dwb_ctrl8_xl_t; 444 445 #define IIS3DWB_CTRL10_C 0x19U 446 typedef struct 447 { 448 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 449 uint8_t not_used_01 : 5; 450 uint8_t timestamp_en : 1; 451 uint8_t not_used_02 : 2; 452 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 453 uint8_t not_used_02 : 2; 454 uint8_t timestamp_en : 1; 455 uint8_t not_used_01 : 5; 456 #endif /* DRV_BYTE_ORDER */ 457 } iis3dwb_ctrl10_c_t; 458 459 #define IIS3DWB_ALL_INT_SRC 0x1AU 460 typedef struct 461 { 462 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 463 uint8_t not_used_01 : 1; 464 uint8_t wu_ia : 1; 465 uint8_t not_used_02 : 3; 466 uint8_t sleep_change : 1; 467 uint8_t not_used_03 : 1; 468 uint8_t timestamp_endcount : 1; 469 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 470 uint8_t timestamp_endcount : 1; 471 uint8_t not_used_03 : 1; 472 uint8_t sleep_change : 1; 473 uint8_t not_used_02 : 3; 474 uint8_t wu_ia : 1; 475 uint8_t not_used_01 : 1; 476 #endif /* DRV_BYTE_ORDER */ 477 } iis3dwb_all_int_src_t; 478 479 #define IIS3DWB_WAKE_UP_SRC 0x1BU 480 typedef struct 481 { 482 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 483 uint8_t z_wu : 1; 484 uint8_t y_wu : 1; 485 uint8_t x_wu : 1; 486 uint8_t wu_ia : 1; 487 uint8_t sleep_state_ia : 1; 488 uint8_t not_used_01 : 1; 489 uint8_t sleep_change_ia : 1; 490 uint8_t not_used_02 : 1; 491 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 492 uint8_t not_used_02 : 1; 493 uint8_t sleep_change_ia : 1; 494 uint8_t not_used_01 : 1; 495 uint8_t sleep_state_ia : 1; 496 uint8_t wu_ia : 1; 497 uint8_t x_wu : 1; 498 uint8_t y_wu : 1; 499 uint8_t z_wu : 1; 500 #endif /* DRV_BYTE_ORDER */ 501 } iis3dwb_wake_up_src_t; 502 503 #define IIS3DWB_STATUS_REG 0x1EU 504 typedef struct 505 { 506 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 507 uint8_t xlda : 1; 508 uint8_t not_used_01 : 1; 509 uint8_t tda : 1; 510 uint8_t not_used_02 : 5; 511 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 512 uint8_t not_used_02 : 5; 513 uint8_t tda : 1; 514 uint8_t not_used_01 : 1; 515 uint8_t xlda : 1; 516 #endif /* DRV_BYTE_ORDER */ 517 } iis3dwb_status_reg_t; 518 519 #define IIS3DWB_OUT_TEMP_L 0x20U 520 #define IIS3DWB_OUT_TEMP_H 0x21U 521 #define IIS3DWB_OUTX_L_A 0x28U 522 #define IIS3DWB_OUTX_H_A 0x29U 523 #define IIS3DWB_OUTY_L_A 0x2AU 524 #define IIS3DWB_OUTY_H_A 0x2BU 525 #define IIS3DWB_OUTZ_L_A 0x2CU 526 #define IIS3DWB_OUTZ_H_A 0x2DU 527 #define IIS3DWB_FIFO_STATUS1 0x3AU 528 typedef struct 529 { 530 uint8_t diff_fifo : 8; 531 } iis3dwb_fifo_status1_t; 532 533 #define IIS3DWB_FIFO_STATUS2 0x3BU 534 typedef struct 535 { 536 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 537 uint8_t diff_fifo : 2; 538 uint8_t not_used_01 : 1; 539 uint8_t fifo_ovr_latched : 1; 540 uint8_t counter_bdr_ia : 1; 541 uint8_t fifo_full_ia : 1; 542 uint8_t fifo_ovr_ia : 1; 543 uint8_t fifo_wtm_ia : 1; 544 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 545 uint8_t fifo_wtm_ia : 1; 546 uint8_t fifo_ovr_ia : 1; 547 uint8_t fifo_full_ia : 1; 548 uint8_t counter_bdr_ia : 1; 549 uint8_t fifo_ovr_latched : 1; 550 uint8_t not_used_01 : 1; 551 uint8_t diff_fifo : 2; 552 #endif /* DRV_BYTE_ORDER */ 553 } iis3dwb_fifo_status2_t; 554 555 #define IIS3DWB_TIMESTAMP0 0x40U 556 #define IIS3DWB_TIMESTAMP1 0x41U 557 #define IIS3DWB_TIMESTAMP2 0x42U 558 #define IIS3DWB_TIMESTAMP3 0x43U 559 #define IIS3DWB_SLOPE_EN 0x56U 560 typedef struct 561 { 562 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 563 uint8_t lir : 1; 564 uint8_t not_used_01 : 3; 565 uint8_t slope_fds : 1; 566 uint8_t sleep_status_on_int : 1; 567 uint8_t not_used_02 : 2; 568 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 569 uint8_t not_used_02 : 2; 570 uint8_t sleep_status_on_int : 1; 571 uint8_t slope_fds : 1; 572 uint8_t not_used_01 : 3; 573 uint8_t lir : 1; 574 #endif /* DRV_BYTE_ORDER */ 575 } iis3dwb_slope_en_t; 576 577 #define IIS3DWB_INTERRUPTS_EN 0x58U 578 typedef struct 579 { 580 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 581 uint8_t not_used_01 : 7; 582 uint8_t interrupts_enable : 1; 583 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 584 uint8_t interrupts_enable : 1; 585 uint8_t not_used_01 : 7; 586 #endif /* DRV_BYTE_ORDER */ 587 } iis3dwb_interrupts_en_t; 588 589 #define IIS3DWB_WAKE_UP_THS 0x5BU 590 typedef struct 591 { 592 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 593 uint8_t wk_ths : 6; 594 uint8_t usr_off_on_wu : 1; 595 uint8_t not_used_01 : 1; 596 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 597 uint8_t not_used_01 : 1; 598 uint8_t usr_off_on_wu : 1; 599 uint8_t wk_ths : 6; 600 #endif /* DRV_BYTE_ORDER */ 601 } iis3dwb_wake_up_ths_t; 602 603 #define IIS3DWB_WAKE_UP_DUR 0x5CU 604 typedef struct 605 { 606 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 607 uint8_t sleep_dur : 4; 608 uint8_t wake_ths_w : 1; 609 uint8_t wake_dur : 2; 610 uint8_t not_used_01 : 1; 611 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 612 uint8_t not_used_01 : 1; 613 uint8_t wake_dur : 2; 614 uint8_t wake_ths_w : 1; 615 uint8_t sleep_dur : 4; 616 #endif /* DRV_BYTE_ORDER */ 617 } iis3dwb_wake_up_dur_t; 618 619 #define IIS3DWB_MD1_CFG 0x5EU 620 typedef struct 621 { 622 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 623 uint8_t not_used_01 : 5; 624 uint8_t int1_wu : 1; 625 uint8_t not_used_02 : 1; 626 uint8_t int1_sleep_change : 1; 627 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 628 uint8_t int1_sleep_change : 1; 629 uint8_t not_used_02 : 1; 630 uint8_t int1_wu : 1; 631 uint8_t not_used_01 : 5; 632 #endif /* DRV_BYTE_ORDER */ 633 } iis3dwb_md1_cfg_t; 634 635 #define IIS3DWB_MD2_CFG 0x5FU 636 typedef struct 637 { 638 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 639 uint8_t int2_timestamp : 1; 640 uint8_t not_used_01 : 4; 641 uint8_t int2_wu : 1; 642 uint8_t not_used_02 : 1; 643 uint8_t int2_sleep_change : 1; 644 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 645 uint8_t int2_sleep_change : 1; 646 uint8_t not_used_02 : 1; 647 uint8_t int2_wu : 1; 648 uint8_t not_used_01 : 4; 649 uint8_t int2_timestamp : 1; 650 #endif /* DRV_BYTE_ORDER */ 651 } iis3dwb_md2_cfg_t; 652 653 #define IIS3DWB_INTERNAL_FREQ_FINE 0x63U 654 typedef struct 655 { 656 uint8_t freq_fine : 8; 657 } iis3dwb_internal_freq_fine_t; 658 659 #define IIS3DWB_X_OFS_USR 0x73U 660 #define IIS3DWB_Y_OFS_USR 0x74U 661 #define IIS3DWB_Z_OFS_USR 0x75U 662 #define IIS3DWB_FIFO_DATA_OUT_TAG 0x78U 663 typedef struct 664 { 665 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 666 uint8_t tag_parity : 1; 667 uint8_t tag_cnt : 2; 668 uint8_t tag_sensor : 5; 669 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 670 uint8_t tag_sensor : 5; 671 uint8_t tag_cnt : 2; 672 uint8_t tag_parity : 1; 673 #endif /* DRV_BYTE_ORDER */ 674 } iis3dwb_fifo_data_out_tag_t; 675 676 #define IIS3DWB_FIFO_DATA_OUT_X_L 0x79U 677 #define IIS3DWB_FIFO_DATA_OUT_X_H 0x7AU 678 #define IIS3DWB_FIFO_DATA_OUT_Y_L 0x7BU 679 #define IIS3DWB_FIFO_DATA_OUT_Y_H 0x7CU 680 #define IIS3DWB_FIFO_DATA_OUT_Z_L 0x7DU 681 #define IIS3DWB_FIFO_DATA_OUT_Z_H 0x7EU 682 683 /** 684 * @defgroup IIS3DWB_Register_Union 685 * @brief This union group all the registers having a bit-field 686 * description. 687 * This union is useful but it's not needed by the driver. 688 * 689 * REMOVING this union you are compliant with: 690 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 691 * 692 * @{ 693 * 694 */ 695 typedef union 696 { 697 iis3dwb_pin_ctrl_t pin_ctrl; 698 iis3dwb_fifo_ctrl1_t fifo_ctrl1; 699 iis3dwb_fifo_ctrl2_t fifo_ctrl2; 700 iis3dwb_fifo_ctrl3_t fifo_ctrl3; 701 iis3dwb_fifo_ctrl4_t fifo_ctrl4; 702 iis3dwb_counter_bdr_reg1_t counter_bdr_reg1; 703 iis3dwb_counter_bdr_reg2_t counter_bdr_reg2; 704 iis3dwb_int1_ctrl_t int1_ctrl; 705 iis3dwb_int2_ctrl_t int2_ctrl; 706 iis3dwb_ctrl1_xl_t ctrl1_xl; 707 iis3dwb_ctrl3_c_t ctrl3_c; 708 iis3dwb_ctrl4_c_t ctrl4_c; 709 iis3dwb_ctrl5_c_t ctrl5_c; 710 iis3dwb_ctrl6_c_t ctrl6_c; 711 iis3dwb_ctrl7_c_t ctrl7_c; 712 iis3dwb_ctrl8_xl_t ctrl8_xl; 713 iis3dwb_ctrl10_c_t ctrl10_c; 714 iis3dwb_all_int_src_t all_int_src; 715 iis3dwb_wake_up_src_t wake_up_src; 716 iis3dwb_status_reg_t status_reg; 717 iis3dwb_fifo_status1_t fifo_status1; 718 iis3dwb_fifo_status2_t fifo_status2; 719 iis3dwb_slope_en_t slope_en; 720 iis3dwb_interrupts_en_t interrupts_en; 721 iis3dwb_wake_up_ths_t wake_up_ths; 722 iis3dwb_wake_up_dur_t wake_up_dur; 723 iis3dwb_md1_cfg_t md1_cfg; 724 iis3dwb_md2_cfg_t md2_cfg; 725 iis3dwb_internal_freq_fine_t internal_freq_fine; 726 iis3dwb_fifo_data_out_tag_t fifo_data_out_tag; 727 bitwise_t bitwise; 728 uint8_t byte; 729 } iis3dwb_reg_t; 730 731 /** 732 * @} 733 * 734 */ 735 736 #ifndef __weak 737 #define __weak __attribute__((weak)) 738 #endif /* __weak */ 739 740 /* 741 * These are the basic platform dependent I/O routines to read 742 * and write device registers connected on a standard bus. 743 * The driver keeps offering a default implementation based on function 744 * pointers to read/write routines for backward compatibility. 745 * The __weak directive allows the final application to overwrite 746 * them with a custom implementation. 747 */ 748 749 int32_t iis3dwb_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 750 uint8_t *data, 751 uint16_t len); 752 int32_t iis3dwb_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 753 uint8_t *data, 754 uint16_t len); 755 756 float_t iis3dwb_from_fs2g_to_mg(int16_t lsb); 757 float_t iis3dwb_from_fs4g_to_mg(int16_t lsb); 758 float_t iis3dwb_from_fs8g_to_mg(int16_t lsb); 759 float_t iis3dwb_from_fs16g_to_mg(int16_t lsb); 760 761 extern float_t iis3dwb_from_lsb_to_celsius(int16_t lsb); 762 763 extern float_t iis3dwb_from_lsb_to_nsec(int32_t lsb); 764 765 typedef enum 766 { 767 IIS3DWB_2g = 0, 768 IIS3DWB_16g = 1, /* if XL_FS_MODE = '1' -> IIS3DWB_2g */ 769 IIS3DWB_4g = 2, 770 IIS3DWB_8g = 3, 771 } iis3dwb_fs_xl_t; 772 int32_t iis3dwb_xl_full_scale_set(const stmdev_ctx_t *ctx, 773 iis3dwb_fs_xl_t val); 774 int32_t iis3dwb_xl_full_scale_get(const stmdev_ctx_t *ctx, 775 iis3dwb_fs_xl_t *val); 776 777 typedef enum 778 { 779 IIS3DWB_XL_ODR_OFF = 0, 780 IIS3DWB_XL_ODR_26k7Hz = 5, 781 } iis3dwb_odr_xl_t; 782 int32_t iis3dwb_xl_data_rate_set(const stmdev_ctx_t *ctx, 783 iis3dwb_odr_xl_t val); 784 int32_t iis3dwb_xl_data_rate_get(const stmdev_ctx_t *ctx, 785 iis3dwb_odr_xl_t *val); 786 787 int32_t iis3dwb_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); 788 int32_t iis3dwb_block_data_update_get(const stmdev_ctx_t *ctx, 789 uint8_t *val); 790 791 typedef enum 792 { 793 IIS3DWB_LSb_1mg = 0, 794 IIS3DWB_LSb_16mg = 1, 795 } iis3dwb_usr_off_w_t; 796 int32_t iis3dwb_xl_offset_weight_set(const stmdev_ctx_t *ctx, 797 iis3dwb_usr_off_w_t val); 798 int32_t iis3dwb_xl_offset_weight_get(const stmdev_ctx_t *ctx, 799 iis3dwb_usr_off_w_t *val); 800 801 typedef enum 802 { 803 IIS3DWB_ENABLE_ALL = 0, 804 IIS3DWB_ONLY_X_ON_ONE_OUT_REG = 0x01, 805 IIS3DWB_ONLY_Y_ON_ONE_OUT_REG = 0x02, 806 IIS3DWB_ONLY_Z_ON_ONE_OUT_REG = 0x03, 807 IIS3DWB_ONLY_X_ON_ALL_OUT_REG = 0x11, 808 IIS3DWB_ONLY_Y_ON_ALL_OUT_REG = 0x12, 809 IIS3DWB_ONLY_Z_ON_ALL_OUT_REG = 0x13, 810 } iis3dwb_xl_axis_sel_t; 811 int32_t iis3dwb_xl_axis_selection_set(const stmdev_ctx_t *ctx, 812 iis3dwb_xl_axis_sel_t val); 813 int32_t iis3dwb_xl_axis_selection_get(const stmdev_ctx_t *ctx, 814 iis3dwb_xl_axis_sel_t *val); 815 816 typedef struct 817 { 818 iis3dwb_all_int_src_t all_int_src; 819 iis3dwb_wake_up_src_t wake_up_src; 820 iis3dwb_status_reg_t status_reg; 821 } iis3dwb_all_sources_t; 822 int32_t iis3dwb_all_sources_get(const stmdev_ctx_t *ctx, 823 iis3dwb_all_sources_t *val); 824 825 int32_t iis3dwb_status_reg_get(const stmdev_ctx_t *ctx, 826 iis3dwb_status_reg_t *val); 827 828 int32_t iis3dwb_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, 829 uint8_t *val); 830 831 int32_t iis3dwb_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, 832 uint8_t *val); 833 834 int32_t iis3dwb_usr_offset_block_set(const stmdev_ctx_t *ctx, uint8_t val); 835 int32_t iis3dwb_usr_offset_block_get(const stmdev_ctx_t *ctx, uint8_t *val); 836 837 int32_t iis3dwb_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff); 838 int32_t iis3dwb_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff); 839 840 int32_t iis3dwb_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff); 841 int32_t iis3dwb_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff); 842 843 int32_t iis3dwb_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff); 844 int32_t iis3dwb_xl_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff); 845 846 int32_t iis3dwb_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val); 847 int32_t iis3dwb_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val); 848 849 int32_t iis3dwb_timestamp_rst(const stmdev_ctx_t *ctx); 850 851 int32_t iis3dwb_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); 852 int32_t iis3dwb_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); 853 854 int32_t iis3dwb_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val); 855 856 typedef enum 857 { 858 IIS3DWB_NO_ROUND = 0, 859 IIS3DWB_ROUND = 1, 860 } iis3dwb_rounding_t; 861 int32_t iis3dwb_rounding_mode_set(const stmdev_ctx_t *ctx, 862 iis3dwb_rounding_t val); 863 int32_t iis3dwb_rounding_mode_get(const stmdev_ctx_t *ctx, 864 iis3dwb_rounding_t *val); 865 866 int32_t iis3dwb_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 867 868 int32_t iis3dwb_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 869 870 int32_t iis3dwb_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val); 871 int32_t iis3dwb_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val); 872 873 typedef enum 874 { 875 IIS3DWB_DRDY_LATCHED = 0, 876 IIS3DWB_DRDY_PULSED = 1, 877 } iis3dwb_dataready_pulsed_t; 878 int32_t iis3dwb_data_ready_mode_set(const stmdev_ctx_t *ctx, 879 iis3dwb_dataready_pulsed_t val); 880 int32_t iis3dwb_data_ready_mode_get(const stmdev_ctx_t *ctx, 881 iis3dwb_dataready_pulsed_t *val); 882 883 int32_t iis3dwb_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); 884 885 int32_t iis3dwb_reset_set(const stmdev_ctx_t *ctx, uint8_t val); 886 int32_t iis3dwb_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); 887 888 int32_t iis3dwb_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); 889 int32_t iis3dwb_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); 890 891 int32_t iis3dwb_boot_set(const stmdev_ctx_t *ctx, uint8_t val); 892 int32_t iis3dwb_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); 893 894 typedef enum 895 { 896 IIS3DWB_XL_ST_DISABLE = 0, 897 IIS3DWB_XL_ST_POSITIVE = 1, 898 IIS3DWB_XL_ST_NEGATIVE = 2, 899 } iis3dwb_st_xl_t; 900 int32_t iis3dwb_xl_self_test_set(const stmdev_ctx_t *ctx, 901 iis3dwb_st_xl_t val); 902 int32_t iis3dwb_xl_self_test_get(const stmdev_ctx_t *ctx, 903 iis3dwb_st_xl_t *val); 904 905 int32_t iis3dwb_filter_settling_mask_set(const stmdev_ctx_t *ctx, 906 uint8_t val); 907 int32_t iis3dwb_filter_settling_mask_get(const stmdev_ctx_t *ctx, 908 uint8_t *val); 909 910 typedef enum 911 { 912 IIS3DWB_SLOPE_ODR_DIV_4 = 0x10, 913 IIS3DWB_HP_REF_MODE = 0x37, 914 IIS3DWB_HP_ODR_DIV_10 = 0x11, 915 IIS3DWB_HP_ODR_DIV_20 = 0x12, 916 IIS3DWB_HP_ODR_DIV_45 = 0x13, 917 IIS3DWB_HP_ODR_DIV_100 = 0x14, 918 IIS3DWB_HP_ODR_DIV_200 = 0x15, 919 IIS3DWB_HP_ODR_DIV_400 = 0x16, 920 IIS3DWB_HP_ODR_DIV_800 = 0x17, 921 IIS3DWB_LP_6k3Hz = 0x00, 922 IIS3DWB_LP_ODR_DIV_4 = 0x80, 923 IIS3DWB_LP_ODR_DIV_10 = 0x81, 924 IIS3DWB_LP_ODR_DIV_20 = 0x82, 925 IIS3DWB_LP_ODR_DIV_45 = 0x83, 926 IIS3DWB_LP_ODR_DIV_100 = 0x84, 927 IIS3DWB_LP_ODR_DIV_200 = 0x85, 928 IIS3DWB_LP_ODR_DIV_400 = 0x86, 929 IIS3DWB_LP_ODR_DIV_800 = 0x87, 930 } iis3dwb_filt_xl_en_t; 931 int32_t iis3dwb_xl_filt_path_on_out_set(const stmdev_ctx_t *ctx, 932 iis3dwb_filt_xl_en_t val); 933 int32_t iis3dwb_xl_filt_path_on_out_get(const stmdev_ctx_t *ctx, 934 iis3dwb_filt_xl_en_t *val); 935 936 int32_t iis3dwb_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val); 937 int32_t iis3dwb_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val); 938 939 typedef enum 940 { 941 IIS3DWB_USE_SLOPE = 0, 942 IIS3DWB_USE_HPF = 1, 943 } iis3dwb_slope_fds_t; 944 int32_t iis3dwb_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, 945 iis3dwb_slope_fds_t val); 946 int32_t iis3dwb_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, 947 iis3dwb_slope_fds_t *val); 948 949 typedef enum 950 { 951 IIS3DWB_PULL_UP_DISC = 0, 952 IIS3DWB_PULL_UP_CONNECT = 1, 953 } iis3dwb_sdo_pu_en_t; 954 int32_t iis3dwb_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, 955 iis3dwb_sdo_pu_en_t val); 956 int32_t iis3dwb_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, 957 iis3dwb_sdo_pu_en_t *val); 958 959 typedef enum 960 { 961 IIS3DWB_SPI_4_WIRE = 0, 962 IIS3DWB_SPI_3_WIRE = 1, 963 } iis3dwb_sim_t; 964 int32_t iis3dwb_spi_mode_set(const stmdev_ctx_t *ctx, iis3dwb_sim_t val); 965 int32_t iis3dwb_spi_mode_get(const stmdev_ctx_t *ctx, iis3dwb_sim_t *val); 966 967 typedef enum 968 { 969 IIS3DWB_I2C_ENABLE = 0, 970 IIS3DWB_I2C_DISABLE = 1, 971 } iis3dwb_i2c_disable_t; 972 int32_t iis3dwb_i2c_interface_set(const stmdev_ctx_t *ctx, 973 iis3dwb_i2c_disable_t val); 974 int32_t iis3dwb_i2c_interface_get(const stmdev_ctx_t *ctx, 975 iis3dwb_i2c_disable_t *val); 976 977 typedef struct 978 { 979 uint8_t drdy_xl : 1; /* Accelerometer data ready */ 980 uint8_t boot : 1; /* Restoring calibration parameters */ 981 uint8_t fifo_th : 1; /* FIFO threshold reached */ 982 uint8_t fifo_ovr : 1; /* FIFO overrun */ 983 uint8_t fifo_full : 1; /* FIFO full */ 984 uint8_t fifo_bdr : 1; /* FIFO Batch counter threshold reached */ 985 uint8_t wake_up : 1; /* wake up event */ 986 uint8_t sleep_change : 987 1; /* Act/Inact (or Vice-versa) status changed */ 988 uint8_t sleep_status : 1; /* Act/Inact status */ 989 } iis3dwb_pin_int1_route_t; 990 int32_t iis3dwb_pin_int1_route_set(const stmdev_ctx_t *ctx, 991 iis3dwb_pin_int1_route_t *val); 992 int32_t iis3dwb_pin_int1_route_get(const stmdev_ctx_t *ctx, 993 iis3dwb_pin_int1_route_t *val); 994 995 typedef struct 996 { 997 uint8_t drdy_xl : 1; /* Accelerometer data ready */ 998 uint8_t drdy_temp : 1; /* Temperature data ready */ 999 uint8_t fifo_th : 1; /* FIFO threshold reached */ 1000 uint8_t fifo_ovr : 1; /* FIFO overrun */ 1001 uint8_t fifo_full : 1; /* FIFO full */ 1002 uint8_t fifo_bdr : 1; /* FIFO Batch counter threshold reached */ 1003 uint8_t timestamp : 1; /* timestamp overflow */ 1004 uint8_t wake_up : 1; /* wake up event */ 1005 uint8_t sleep_change : 1; /* Act/Inact (or Vice-versa) status changed */ 1006 uint8_t sleep_status : 1; /* Act/Inact status */ 1007 } iis3dwb_pin_int2_route_t; 1008 int32_t iis3dwb_pin_int2_route_set(const stmdev_ctx_t *ctx, 1009 iis3dwb_pin_int2_route_t *val); 1010 int32_t iis3dwb_pin_int2_route_get(const stmdev_ctx_t *ctx, 1011 iis3dwb_pin_int2_route_t *val); 1012 1013 typedef enum 1014 { 1015 IIS3DWB_PUSH_PULL = 0, 1016 IIS3DWB_OPEN_DRAIN = 1, 1017 } iis3dwb_pp_od_t; 1018 int32_t iis3dwb_pin_mode_set(const stmdev_ctx_t *ctx, iis3dwb_pp_od_t val); 1019 int32_t iis3dwb_pin_mode_get(const stmdev_ctx_t *ctx, iis3dwb_pp_od_t *val); 1020 1021 typedef enum 1022 { 1023 IIS3DWB_ACTIVE_HIGH = 0, 1024 IIS3DWB_ACTIVE_LOW = 1, 1025 } iis3dwb_h_lactive_t; 1026 int32_t iis3dwb_pin_polarity_set(const stmdev_ctx_t *ctx, 1027 iis3dwb_h_lactive_t val); 1028 int32_t iis3dwb_pin_polarity_get(const stmdev_ctx_t *ctx, 1029 iis3dwb_h_lactive_t *val); 1030 1031 int32_t iis3dwb_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); 1032 int32_t iis3dwb_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); 1033 1034 typedef enum 1035 { 1036 IIS3DWB_INT_PULSED = 0, 1037 IIS3DWB_INT_LATCHED = 1, 1038 } iis3dwb_lir_t; 1039 int32_t iis3dwb_int_notification_set(const stmdev_ctx_t *ctx, 1040 iis3dwb_lir_t val); 1041 int32_t iis3dwb_int_notification_get(const stmdev_ctx_t *ctx, 1042 iis3dwb_lir_t *val); 1043 1044 typedef enum 1045 { 1046 IIS3DWB_LSb_FS_DIV_64 = 0, 1047 IIS3DWB_LSb_FS_DIV_256 = 1, 1048 } iis3dwb_wake_ths_w_t; 1049 int32_t iis3dwb_wkup_ths_weight_set(const stmdev_ctx_t *ctx, 1050 iis3dwb_wake_ths_w_t val); 1051 int32_t iis3dwb_wkup_ths_weight_get(const stmdev_ctx_t *ctx, 1052 iis3dwb_wake_ths_w_t *val); 1053 1054 int32_t iis3dwb_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); 1055 int32_t iis3dwb_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); 1056 1057 int32_t iis3dwb_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx, 1058 uint8_t val); 1059 int32_t iis3dwb_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, 1060 uint8_t *val); 1061 1062 int32_t iis3dwb_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 1063 int32_t iis3dwb_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 1064 1065 int32_t iis3dwb_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 1066 int32_t iis3dwb_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 1067 1068 int32_t iis3dwb_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val); 1069 int32_t iis3dwb_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val); 1070 1071 int32_t iis3dwb_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); 1072 int32_t iis3dwb_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); 1073 1074 typedef enum 1075 { 1076 IIS3DWB_XL_NOT_BATCHED = 0, 1077 IIS3DWB_XL_BATCHED_AT_26k7Hz = 10, 1078 } iis3dwb_bdr_xl_t; 1079 int32_t iis3dwb_fifo_xl_batch_set(const stmdev_ctx_t *ctx, 1080 iis3dwb_bdr_xl_t val); 1081 int32_t iis3dwb_fifo_xl_batch_get(const stmdev_ctx_t *ctx, 1082 iis3dwb_bdr_xl_t *val); 1083 1084 typedef enum 1085 { 1086 IIS3DWB_BYPASS_MODE = 0, 1087 IIS3DWB_FIFO_MODE = 1, 1088 IIS3DWB_STREAM_TO_FIFO_MODE = 3, 1089 IIS3DWB_BYPASS_TO_STREAM_MODE = 4, 1090 IIS3DWB_STREAM_MODE = 6, 1091 IIS3DWB_BYPASS_TO_FIFO_MODE = 7, 1092 } iis3dwb_fifo_mode_t; 1093 int32_t iis3dwb_fifo_mode_set(const stmdev_ctx_t *ctx, 1094 iis3dwb_fifo_mode_t val); 1095 int32_t iis3dwb_fifo_mode_get(const stmdev_ctx_t *ctx, 1096 iis3dwb_fifo_mode_t *val); 1097 1098 typedef enum 1099 { 1100 IIS3DWB_TEMP_NOT_BATCHED = 0, 1101 IIS3DWB_TEMP_BATCHED_AT_104Hz = 3, 1102 } iis3dwb_odr_t_batch_t; 1103 int32_t iis3dwb_fifo_temp_batch_set(const stmdev_ctx_t *ctx, 1104 iis3dwb_odr_t_batch_t val); 1105 int32_t iis3dwb_fifo_temp_batch_get(const stmdev_ctx_t *ctx, 1106 iis3dwb_odr_t_batch_t *val); 1107 1108 typedef enum 1109 { 1110 IIS3DWB_NO_DECIMATION = 0, 1111 IIS3DWB_DEC_1 = 1, 1112 IIS3DWB_DEC_8 = 2, 1113 IIS3DWB_DEC_32 = 3, 1114 } iis3dwb_fifo_timestamp_batch_t; 1115 int32_t iis3dwb_fifo_timestamp_batch_set(const stmdev_ctx_t *ctx, 1116 iis3dwb_fifo_timestamp_batch_t val); 1117 int32_t iis3dwb_fifo_timestamp_batch_get(const stmdev_ctx_t *ctx, 1118 iis3dwb_fifo_timestamp_batch_t *val); 1119 1120 int32_t iis3dwb_rst_batch_counter_set(const stmdev_ctx_t *ctx, uint8_t val); 1121 int32_t iis3dwb_rst_batch_counter_get(const stmdev_ctx_t *ctx, 1122 uint8_t *val); 1123 1124 int32_t iis3dwb_batch_counter_threshold_set(const stmdev_ctx_t *ctx, 1125 uint16_t val); 1126 int32_t iis3dwb_batch_counter_threshold_get(const stmdev_ctx_t *ctx, 1127 uint16_t *val); 1128 1129 int32_t iis3dwb_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val); 1130 1131 typedef struct 1132 { 1133 uint16_t fifo_level : 10; 1134 uint8_t fifo_bdr : 1; 1135 uint8_t fifo_full : 1; 1136 uint8_t fifo_ovr : 1; 1137 uint8_t fifo_th : 1; 1138 } iis3dwb_fifo_status_t; 1139 int32_t iis3dwb_fifo_status_get(const stmdev_ctx_t *ctx, 1140 iis3dwb_fifo_status_t *val); 1141 1142 typedef struct 1143 { 1144 uint8_t tag; 1145 uint8_t data[6]; 1146 } iis3dwb_fifo_out_raw_t; 1147 int32_t iis3dwb_fifo_out_raw_get(const stmdev_ctx_t *ctx, iis3dwb_fifo_out_raw_t *val); 1148 int32_t iis3dwb_fifo_out_multi_raw_get(const stmdev_ctx_t *ctx, 1149 iis3dwb_fifo_out_raw_t *fdata, 1150 uint16_t num); 1151 1152 typedef enum 1153 { 1154 IIS3DWB_XL_TAG = 2, 1155 IIS3DWB_TEMPERATURE_TAG, 1156 IIS3DWB_TIMESTAMP_TAG, 1157 } iis3dwb_fifo_tag_t; 1158 int32_t iis3dwb_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, 1159 iis3dwb_fifo_tag_t *val); 1160 1161 /** 1162 *@} 1163 * 1164 */ 1165 1166 #ifdef __cplusplus 1167 } 1168 #endif 1169 1170 #endif /* IIS3DWB_REGS_H */ 1171 1172 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1173
