1 /** 2 ****************************************************************************** 3 * @file iis3dhhc_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * iis3dhhc_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef IIS3DHHC_REGS_H 23 #define IIS3DHHC_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup IIS3DHHC 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup IIS3DHHC_Infos 167 * @{ 168 * 169 */ 170 171 /** Device Identification (Who am I) **/ 172 #define IIS3DHHC_ID 0x11U 173 174 /** 175 * @} 176 * 177 */ 178 179 #define IIS3DHHC_WHO_AM_I 0x0FU 180 typedef struct 181 { 182 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 183 uint8_t not_used_01 : 7; 184 uint8_t asic_id : 1; 185 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 186 uint8_t asic_id : 1; 187 uint8_t not_used_01 : 7; 188 #endif /* DRV_BYTE_ORDER */ 189 } iis3dhhc_id_reg_t; 190 191 #define IIS3DHHC_CTRL_REG1 0x20U 192 typedef struct 193 { 194 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 195 uint8_t bdu : 1; 196 uint8_t drdy_pulse : 1; 197 uint8_t sw_reset : 1; 198 uint8_t boot : 1; 199 uint8_t not_used_01 : 2; 200 uint8_t if_add_inc : 1; 201 uint8_t norm_mod_en : 1; 202 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 203 uint8_t norm_mod_en : 1; 204 uint8_t if_add_inc : 1; 205 uint8_t not_used_01 : 2; 206 uint8_t boot : 1; 207 uint8_t sw_reset : 1; 208 uint8_t drdy_pulse : 1; 209 uint8_t bdu : 1; 210 #endif /* DRV_BYTE_ORDER */ 211 } iis3dhhc_ctrl_reg1_t; 212 213 #define IIS3DHHC_INT1_CTRL 0x21U 214 typedef struct 215 { 216 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 217 uint8_t not_used_01 : 2; 218 uint8_t int1_ext : 1; 219 uint8_t int1_fth : 1; 220 uint8_t int1_fss5 : 1; 221 uint8_t int1_ovr : 1; 222 uint8_t int1_boot : 1; 223 uint8_t int1_drdy : 1; 224 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 225 uint8_t int1_drdy : 1; 226 uint8_t int1_boot : 1; 227 uint8_t int1_ovr : 1; 228 uint8_t int1_fss5 : 1; 229 uint8_t int1_fth : 1; 230 uint8_t int1_ext : 1; 231 uint8_t not_used_01 : 2; 232 #endif /* DRV_BYTE_ORDER */ 233 } iis3dhhc_int1_ctrl_t; 234 235 #define IIS3DHHC_INT2_CTRL 0x22U 236 typedef struct 237 { 238 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 239 uint8_t not_used_01 : 3; 240 uint8_t int2_fth : 1; 241 uint8_t int2_fss5 : 1; 242 uint8_t int2_ovr : 1; 243 uint8_t int2_boot : 1; 244 uint8_t int2_drdy : 1; 245 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 246 uint8_t int2_drdy : 1; 247 uint8_t int2_boot : 1; 248 uint8_t int2_ovr : 1; 249 uint8_t int2_fss5 : 1; 250 uint8_t int2_fth : 1; 251 uint8_t not_used_01 : 3; 252 #endif /* DRV_BYTE_ORDER */ 253 } iis3dhhc_int2_ctrl_t; 254 255 #define IIS3DHHC_CTRL_REG4 0x23U 256 typedef struct 257 { 258 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 259 uint8_t off_tcomp_en : 1; 260 uint8_t fifo_en : 1; 261 uint8_t pp_od : 2; 262 uint8_t st : 2; 263 uint8_t dsp : 2; /* dsp_lp_type + dsp_bw_sel */ 264 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 265 uint8_t dsp : 2; /* dsp_lp_type + dsp_bw_sel */ 266 uint8_t st : 2; 267 uint8_t pp_od : 2; 268 uint8_t fifo_en : 1; 269 uint8_t off_tcomp_en : 1; 270 #endif /* DRV_BYTE_ORDER */ 271 } iis3dhhc_ctrl_reg4_t; 272 273 #define IIS3DHHC_CTRL_REG5 0x24U 274 typedef struct 275 { 276 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 277 uint8_t fifo_spi_hs_on : 1; 278 uint8_t not_used_01 : 7; 279 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 280 uint8_t not_used_01 : 7; 281 uint8_t fifo_spi_hs_on : 1; 282 #endif /* DRV_BYTE_ORDER */ 283 } iis3dhhc_ctrl_reg5_t; 284 285 #define IIS3DHHC_OUT_TEMP_L 0x25U 286 #define IIS3DHHC_OUT_TEMP_H 0x26U 287 #define IIS3DHHC_STATUS 0x27U 288 typedef struct 289 { 290 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 291 uint8_t xda : 1; 292 uint8_t yda : 1; 293 uint8_t zda : 1; 294 uint8_t zyxda : 1; 295 uint8_t _xor : 1; 296 uint8_t yor : 1; 297 uint8_t zor : 1; 298 uint8_t zyxor : 1; 299 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 300 uint8_t zyxor : 1; 301 uint8_t zor : 1; 302 uint8_t yor : 1; 303 uint8_t _xor : 1; 304 uint8_t zyxda : 1; 305 uint8_t zda : 1; 306 uint8_t yda : 1; 307 uint8_t xda : 1; 308 #endif /* DRV_BYTE_ORDER */ 309 } iis3dhhc_status_t; 310 311 #define IIS3DHHC_OUT_X_L_XL 0x28U 312 #define IIS3DHHC_OUT_X_H_XL 0x29U 313 #define IIS3DHHC_OUT_Y_L_XL 0x2AU 314 #define IIS3DHHC_OUT_Y_H_XL 0x2BU 315 #define IIS3DHHC_OUT_Z_L_XL 0x2CU 316 #define IIS3DHHC_OUT_Z_H_XL 0x2DU 317 #define IIS3DHHC_FIFO_CTRL 0x2EU 318 typedef struct 319 { 320 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 321 uint8_t fth : 5; 322 uint8_t fmode : 3; 323 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 324 uint8_t fmode : 3; 325 uint8_t fth : 5; 326 #endif /* DRV_BYTE_ORDER */ 327 } iis3dhhc_fifo_ctrl_t; 328 329 #define IIS3DHHC_FIFO_SRC 0x2FU 330 typedef struct 331 { 332 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 333 uint8_t fss : 6; 334 uint8_t ovrn : 1; 335 uint8_t fth : 1; 336 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 337 uint8_t fth : 1; 338 uint8_t ovrn : 1; 339 uint8_t fss : 6; 340 #endif /* DRV_BYTE_ORDER */ 341 } iis3dhhc_fifo_src_t; 342 343 /** 344 * @defgroup IIS3DHHC_Register_Union 345 * @brief This union group all the registers having a bit-field 346 * description. 347 * This union is useful but it's not needed by the driver. 348 * 349 * REMOVING this union you are compliant with: 350 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 351 * 352 * @{ 353 * 354 */ 355 typedef union 356 { 357 iis3dhhc_id_reg_t id_reg; 358 iis3dhhc_ctrl_reg1_t ctrl_reg1; 359 iis3dhhc_int1_ctrl_t int1_ctrl; 360 iis3dhhc_int2_ctrl_t int2_ctrl; 361 iis3dhhc_ctrl_reg4_t ctrl_reg4; 362 iis3dhhc_ctrl_reg5_t ctrl_reg5; 363 iis3dhhc_status_t status; 364 iis3dhhc_fifo_ctrl_t fifo_ctrl; 365 iis3dhhc_fifo_src_t fifo_src; 366 bitwise_t bitwise; 367 uint8_t byte; 368 } iis3dhhc_reg_t; 369 370 /** 371 * @} 372 * 373 */ 374 375 #ifndef __weak 376 #define __weak __attribute__((weak)) 377 #endif /* __weak */ 378 379 /* 380 * These are the basic platform dependent I/O routines to read 381 * and write device registers connected on a standard bus. 382 * The driver keeps offering a default implementation based on function 383 * pointers to read/write routines for backward compatibility. 384 * The __weak directive allows the final application to overwrite 385 * them with a custom implementation. 386 */ 387 388 int32_t iis3dhhc_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 389 uint8_t *data, 390 uint16_t len); 391 int32_t iis3dhhc_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 392 uint8_t *data, 393 uint16_t len); 394 395 float_t iis3dhhc_from_lsb_to_mg(int16_t lsb); 396 float_t iis3dhhc_from_lsb_to_celsius(int16_t lsb); 397 398 int32_t iis3dhhc_block_data_update_set(const stmdev_ctx_t *ctx, 399 uint8_t val); 400 int32_t iis3dhhc_block_data_update_get(const stmdev_ctx_t *ctx, 401 uint8_t *val); 402 403 typedef enum 404 { 405 IIS3DHHC_POWER_DOWN = 0, 406 IIS3DHHC_1kHz1 = 1, 407 } iis3dhhc_norm_mod_en_t; 408 int32_t iis3dhhc_data_rate_set(const stmdev_ctx_t *ctx, 409 iis3dhhc_norm_mod_en_t val); 410 int32_t iis3dhhc_data_rate_get(const stmdev_ctx_t *ctx, 411 iis3dhhc_norm_mod_en_t *val); 412 413 int32_t iis3dhhc_offset_temp_comp_set(const stmdev_ctx_t *ctx, uint8_t val); 414 int32_t iis3dhhc_offset_temp_comp_get(const stmdev_ctx_t *ctx, 415 uint8_t *val); 416 417 int32_t iis3dhhc_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 418 419 int32_t iis3dhhc_acceleration_raw_get(const stmdev_ctx_t *ctx, 420 int16_t *val); 421 422 int32_t iis3dhhc_xl_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); 423 424 int32_t iis3dhhc_xl_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val); 425 426 int32_t iis3dhhc_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); 427 428 int32_t iis3dhhc_reset_set(const stmdev_ctx_t *ctx, uint8_t val); 429 int32_t iis3dhhc_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); 430 431 int32_t iis3dhhc_boot_set(const stmdev_ctx_t *ctx, uint8_t val); 432 int32_t iis3dhhc_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); 433 434 typedef enum 435 { 436 IIS3DHHC_ST_DISABLE = 0, 437 IIS3DHHC_ST_POSITIVE = 1, 438 IIS3DHHC_ST_NEGATIVE = 2, 439 } iis3dhhc_st_t; 440 int32_t iis3dhhc_self_test_set(const stmdev_ctx_t *ctx, iis3dhhc_st_t val); 441 int32_t iis3dhhc_self_test_get(const stmdev_ctx_t *ctx, iis3dhhc_st_t *val); 442 443 typedef enum 444 { 445 IIS3DHHC_LINEAR_PHASE_440Hz = 0, 446 IIS3DHHC_LINEAR_PHASE_235Hz = 1, 447 IIS3DHHC_NO_LINEAR_PHASE_440Hz = 2, 448 IIS3DHHC_NO_LINEAR_PHASE_235Hz = 3, 449 } iis3dhhc_dsp_t; 450 int32_t iis3dhhc_filter_config_set(const stmdev_ctx_t *ctx, 451 iis3dhhc_dsp_t val); 452 int32_t iis3dhhc_filter_config_get(const stmdev_ctx_t *ctx, 453 iis3dhhc_dsp_t *val); 454 455 int32_t iis3dhhc_status_get(const stmdev_ctx_t *ctx, 456 iis3dhhc_status_t *val); 457 458 typedef enum 459 { 460 IIS3DHHC_LATCHED = 0, 461 IIS3DHHC_PULSED = 1, 462 } iis3dhhc_drdy_pulse_t; 463 int32_t iis3dhhc_drdy_notification_mode_set(const stmdev_ctx_t *ctx, 464 iis3dhhc_drdy_pulse_t val); 465 int32_t iis3dhhc_drdy_notification_mode_get(const stmdev_ctx_t *ctx, 466 iis3dhhc_drdy_pulse_t *val); 467 468 typedef enum 469 { 470 IIS3DHHC_PIN_AS_INTERRUPT = 0, 471 IIS3DHHC_PIN_AS_TRIGGER = 1, 472 } iis3dhhc_int1_ext_t; 473 int32_t iis3dhhc_int1_mode_set(const stmdev_ctx_t *ctx, 474 iis3dhhc_int1_ext_t val); 475 int32_t iis3dhhc_int1_mode_get(const stmdev_ctx_t *ctx, 476 iis3dhhc_int1_ext_t *val); 477 478 int32_t iis3dhhc_fifo_threshold_on_int1_set(const stmdev_ctx_t *ctx, 479 uint8_t val); 480 int32_t iis3dhhc_fifo_threshold_on_int1_get(const stmdev_ctx_t *ctx, 481 uint8_t *val); 482 483 int32_t iis3dhhc_fifo_full_on_int1_set(const stmdev_ctx_t *ctx, 484 uint8_t val); 485 int32_t iis3dhhc_fifo_full_on_int1_get(const stmdev_ctx_t *ctx, 486 uint8_t *val); 487 488 int32_t iis3dhhc_fifo_ovr_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); 489 int32_t iis3dhhc_fifo_ovr_on_int1_get(const stmdev_ctx_t *ctx, 490 uint8_t *val); 491 492 int32_t iis3dhhc_boot_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); 493 int32_t iis3dhhc_boot_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); 494 495 int32_t iis3dhhc_drdy_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); 496 int32_t iis3dhhc_drdy_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); 497 498 int32_t iis3dhhc_fifo_threshold_on_int2_set(const stmdev_ctx_t *ctx, 499 uint8_t val); 500 int32_t iis3dhhc_fifo_threshold_on_int2_get(const stmdev_ctx_t *ctx, 501 uint8_t *val); 502 503 int32_t iis3dhhc_fifo_full_on_int2_set(const stmdev_ctx_t *ctx, 504 uint8_t val); 505 int32_t iis3dhhc_fifo_full_on_int2_get(const stmdev_ctx_t *ctx, 506 uint8_t *val); 507 508 int32_t iis3dhhc_fifo_ovr_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val); 509 int32_t iis3dhhc_fifo_ovr_on_int2_get(const stmdev_ctx_t *ctx, 510 uint8_t *val); 511 512 int32_t iis3dhhc_boot_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val); 513 int32_t iis3dhhc_boot_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val); 514 515 int32_t iis3dhhc_drdy_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val); 516 int32_t iis3dhhc_drdy_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val); 517 518 typedef enum 519 { 520 IIS3DHHC_ALL_PUSH_PULL = 0, 521 IIS3DHHC_INT1_OD_INT2_PP = 1, 522 IIS3DHHC_INT1_PP_INT2_OD = 2, 523 IIS3DHHC_ALL_OPEN_DRAIN = 3, 524 } iis3dhhc_pp_od_t; 525 int32_t iis3dhhc_pin_mode_set(const stmdev_ctx_t *ctx, 526 iis3dhhc_pp_od_t val); 527 int32_t iis3dhhc_pin_mode_get(const stmdev_ctx_t *ctx, 528 iis3dhhc_pp_od_t *val); 529 530 int32_t iis3dhhc_fifo_set(const stmdev_ctx_t *ctx, uint8_t val); 531 int32_t iis3dhhc_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val); 532 533 int32_t iis3dhhc_fifo_block_spi_hs_set(const stmdev_ctx_t *ctx, 534 uint8_t val); 535 int32_t iis3dhhc_fifo_block_spi_hs_get(const stmdev_ctx_t *ctx, 536 uint8_t *val); 537 538 int32_t iis3dhhc_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); 539 int32_t iis3dhhc_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); 540 541 typedef enum 542 { 543 IIS3DHHC_BYPASS_MODE = 0, 544 IIS3DHHC_FIFO_MODE = 1, 545 IIS3DHHC_STREAM_TO_FIFO_MODE = 3, 546 IIS3DHHC_BYPASS_TO_STREAM_MODE = 4, 547 IIS3DHHC_DYNAMIC_STREAM_MODE = 6, 548 } iis3dhhc_fmode_t; 549 int32_t iis3dhhc_fifo_mode_set(const stmdev_ctx_t *ctx, 550 iis3dhhc_fmode_t val); 551 int32_t iis3dhhc_fifo_mode_get(const stmdev_ctx_t *ctx, 552 iis3dhhc_fmode_t *val); 553 554 int32_t iis3dhhc_fifo_status_get(const stmdev_ctx_t *ctx, 555 iis3dhhc_fifo_src_t *val); 556 557 int32_t iis3dhhc_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 558 559 int32_t iis3dhhc_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 560 561 int32_t iis3dhhc_fifo_fth_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 562 563 int32_t iis3dhhc_auto_add_inc_set(const stmdev_ctx_t *ctx, uint8_t val); 564 int32_t iis3dhhc_auto_add_inc_get(const stmdev_ctx_t *ctx, uint8_t *val); 565 566 /** 567 *@} 568 * 569 */ 570 571 #ifdef __cplusplus 572 } 573 #endif 574 575 #endif /* IIS3DHHC_REGS_H */ 576 577 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 578
