1 /**
2 ******************************************************************************
3 * @file iis3dhhc_reg.c
4 * @author Sensors Software Solution Team
5 * @brief IIS3DHHC driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "iis3dhhc_reg.h"
21
22 /**
23 * @defgroup IIS3DHHC
24 * @brief This file provides a set of functions needed to drive the
25 * iis3dhhc enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup IIS3DHHC_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
iis3dhhc_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak iis3dhhc_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 if (ctx == NULL) return -1;
56
57 ret = ctx->read_reg(ctx->handle, reg, data, len);
58
59 return ret;
60 }
61
62 /**
63 * @brief Write generic device register
64 *
65 * @param ctx read / write interface definitions(ptr)
66 * @param reg register to write
67 * @param data pointer to data to write in register reg(ptr)
68 * @param len number of consecutive register to write
69 * @retval interface status (MANDATORY: return 0 -> no Error)
70 *
71 */
iis3dhhc_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)72 int32_t __weak iis3dhhc_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
73 uint8_t *data,
74 uint16_t len)
75 {
76 int32_t ret;
77
78 if (ctx == NULL) return -1;
79
80 ret = ctx->write_reg(ctx->handle, reg, data, len);
81
82 return ret;
83 }
84
85 /**
86 * @}
87 *
88 */
89
90 /**
91 * @defgroup IIS3DHHC_Sensitivity
92 * @brief These functions convert raw-data into engineering units.
93 * @{
94 *
95 */
96
iis3dhhc_from_lsb_to_mg(int16_t lsb)97 float_t iis3dhhc_from_lsb_to_mg(int16_t lsb)
98 {
99 return ((float_t)lsb * 0.076f);
100 }
101
iis3dhhc_from_lsb_to_celsius(int16_t lsb)102 float_t iis3dhhc_from_lsb_to_celsius(int16_t lsb)
103 {
104 return (((float_t)lsb / 16.0f) + 25.0f);
105 }
106
107 /**
108 * @}
109 *
110 */
111
112 /**
113 * @defgroup IIS3DHHC_Data_generation
114 * @brief This section groups all the functions concerning data
115 * generation
116 * @{
117 *
118 */
119
120 /**
121 * @brief Blockdataupdate.[set]
122 *
123 * @param ctx Read / write interface definitions.(ptr)
124 * @param val Change the values of bdu in reg CTRL_REG1.
125 * @retval Interface status (MANDATORY: return 0 -> no Error).
126 *
127 */
iis3dhhc_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)128 int32_t iis3dhhc_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val)
129 {
130 iis3dhhc_ctrl_reg1_t ctrl_reg1;
131 int32_t ret;
132
133 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG1,
134 (uint8_t *)&ctrl_reg1, 1);
135
136 if (ret == 0)
137 {
138 ctrl_reg1.bdu = val;
139 ret = iis3dhhc_write_reg(ctx, IIS3DHHC_CTRL_REG1,
140 (uint8_t *)&ctrl_reg1, 1);
141 }
142
143 return ret;
144 }
145
146 /**
147 * @brief Blockdataupdate.[get]
148 *
149 * @param ctx Read / write interface definitions.(ptr)
150 * @param val Get the values of bdu in reg CTRL_REG1.(ptr)
151 * @retval Interface status (MANDATORY: return 0 -> no Error).
152 *
153 */
iis3dhhc_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)154 int32_t iis3dhhc_block_data_update_get(const stmdev_ctx_t *ctx,
155 uint8_t *val)
156 {
157 iis3dhhc_ctrl_reg1_t ctrl_reg1;
158 int32_t ret;
159
160 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG1,
161 (uint8_t *)&ctrl_reg1, 1);
162 *val = ctrl_reg1.bdu;
163
164 return ret;
165 }
166
167 /**
168 * @brief Output data rate selection.[set]
169 *
170 * @param ctx Read / write interface definitions.(ptr)
171 * @param val Change the values of norm_mod_en in reg CTRL_REG1
172 * @retval Interface status (MANDATORY: return 0 -> no Error).
173 *
174 */
iis3dhhc_data_rate_set(const stmdev_ctx_t * ctx,iis3dhhc_norm_mod_en_t val)175 int32_t iis3dhhc_data_rate_set(const stmdev_ctx_t *ctx,
176 iis3dhhc_norm_mod_en_t val)
177 {
178 iis3dhhc_ctrl_reg1_t ctrl_reg1;
179 int32_t ret;
180
181 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG1,
182 (uint8_t *)&ctrl_reg1, 1);
183
184 if (ret == 0)
185 {
186 ctrl_reg1.norm_mod_en = (uint8_t)val;
187 ret = iis3dhhc_write_reg(ctx, IIS3DHHC_CTRL_REG1,
188 (uint8_t *)&ctrl_reg1, 1);
189 }
190
191 return ret;
192 }
193
194 /**
195 * @brief Output data rate selection.[get]
196 *
197 * @param ctx Read / write interface definitions.(ptr)
198 * @param val Get the values of norm_mod_en in reg CTRL_REG1.(ptr)
199 * @retval Interface status (MANDATORY: return 0 -> no Error).
200 *
201 */
iis3dhhc_data_rate_get(const stmdev_ctx_t * ctx,iis3dhhc_norm_mod_en_t * val)202 int32_t iis3dhhc_data_rate_get(const stmdev_ctx_t *ctx,
203 iis3dhhc_norm_mod_en_t *val)
204 {
205 iis3dhhc_ctrl_reg1_t ctrl_reg1;
206 int32_t ret;
207
208 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG1,
209 (uint8_t *)&ctrl_reg1, 1);
210
211 switch (ctrl_reg1.norm_mod_en)
212 {
213 case IIS3DHHC_POWER_DOWN:
214 *val = IIS3DHHC_POWER_DOWN;
215 break;
216
217 case IIS3DHHC_1kHz1:
218 *val = IIS3DHHC_1kHz1;
219 break;
220
221 default:
222 *val = IIS3DHHC_POWER_DOWN;
223 break;
224 }
225
226 return ret;
227 }
228
229 /**
230 * @brief Offset temperature compensation enable.[set]
231 *
232 * @param ctx Read / write interface definitions.(ptr)
233 * @param val Change the values of off_tcomp_en in reg CTRL_REG4
234 * @retval Interface status (MANDATORY: return 0 -> no Error).
235 *
236 */
iis3dhhc_offset_temp_comp_set(const stmdev_ctx_t * ctx,uint8_t val)237 int32_t iis3dhhc_offset_temp_comp_set(const stmdev_ctx_t *ctx, uint8_t val)
238 {
239 iis3dhhc_ctrl_reg4_t ctrl_reg4;
240 int32_t ret;
241
242 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG4,
243 (uint8_t *)&ctrl_reg4, 1);
244
245 if (ret == 0)
246 {
247 ctrl_reg4.off_tcomp_en = val;
248 ret = iis3dhhc_write_reg(ctx, IIS3DHHC_CTRL_REG4,
249 (uint8_t *)&ctrl_reg4, 1);
250 }
251
252 return ret;
253 }
254
255 /**
256 * @brief Offset temperature compensation enable.[get]
257 *
258 * @param ctx Read / write interface definitions.(ptr)
259 * @param val Get the values of off_tcomp_en in reg CTRL_REG4.(ptr)
260 * @retval Interface status (MANDATORY: return 0 -> no Error).
261 *
262 */
iis3dhhc_offset_temp_comp_get(const stmdev_ctx_t * ctx,uint8_t * val)263 int32_t iis3dhhc_offset_temp_comp_get(const stmdev_ctx_t *ctx, uint8_t *val)
264 {
265 iis3dhhc_ctrl_reg4_t ctrl_reg4;
266 int32_t ret;
267
268 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG4,
269 (uint8_t *)&ctrl_reg4, 1);
270 *val = ctrl_reg4.off_tcomp_en;
271
272 return ret;
273 }
274
275 /**
276 * @brief Temperature output value.[get]
277 *
278 * @param ctx Read / write interface definitions.(ptr)
279 * @param buff Buffer that stores data read
280 * @retval Interface status (MANDATORY: return 0 -> no Error).
281 *
282 */
iis3dhhc_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * val)283 int32_t iis3dhhc_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
284 {
285 uint8_t buff[2];
286 int32_t ret;
287
288 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_OUT_TEMP_L, buff, 2);
289 *val = (int16_t)buff[1];
290 *val = (*val * 256) + (int16_t)buff[0];
291
292 return ret;
293 }
294
295 /**
296 * @brief acceleration output value.[get]
297 *
298 * @param ctx Read / write interface definitions.(ptr)
299 * @param buff Buffer that stores data read
300 * @retval Interface status (MANDATORY: return 0 -> no Error).
301 *
302 */
iis3dhhc_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)303 int32_t iis3dhhc_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
304 {
305 uint8_t buff[6];
306 int32_t ret;
307
308 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_OUT_X_L_XL, buff, 6);
309 val[0] = (int16_t)buff[1];
310 val[0] = (val[0] * 256) + (int16_t)buff[0];
311 val[1] = (int16_t)buff[3];
312 val[1] = (val[1] * 256) + (int16_t)buff[2];
313 val[2] = (int16_t)buff[5];
314 val[2] = (val[2] * 256) + (int16_t)buff[4];
315
316 return ret;
317 }
318
319 /**
320 * @brief Acceleration set of data available.[get]
321 *
322 * @param ctx Read / write interface definitions.(ptr)
323 * @param val Get the values of zyxda in reg STATUS.(ptr)
324 * @retval Interface status (MANDATORY: return 0 -> no Error).
325 *
326 */
iis3dhhc_xl_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)327 int32_t iis3dhhc_xl_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val)
328 {
329 iis3dhhc_status_t status;
330 int32_t ret;
331
332 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_STATUS, (uint8_t *)&status, 1);
333 *val = status.zyxda;
334
335 return ret;
336 }
337
338 /**
339 * @brief Acceleration set of data overrun.[get]
340 *
341 * @param ctx Read / write interface definitions.(ptr)
342 * @param val Get the values of zyxor in reg STATUS.(ptr)
343 * @retval Interface status (MANDATORY: return 0 -> no Error).
344 *
345 */
iis3dhhc_xl_data_ovr_get(const stmdev_ctx_t * ctx,uint8_t * val)346 int32_t iis3dhhc_xl_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val)
347 {
348 iis3dhhc_status_t status;
349 int32_t ret;
350
351 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_STATUS, (uint8_t *)&status, 1);
352 *val = status.zyxor;
353
354 return ret;
355 }
356
357 /**
358 * @}
359 *
360 */
361
362 /**
363 * @defgroup IIS3DHHC_common
364 * @brief This section group common useful functions
365 * @{
366 *
367 */
368
369 /**
370 * @brief DeviceWhoamI.[get]
371 *
372 * @param ctx Read / write interface definitions.(ptr)
373 * @param buff Buffer that stores data read
374 * @retval Interface status (MANDATORY: return 0 -> no Error).
375 *
376 */
iis3dhhc_device_id_get(const stmdev_ctx_t * ctx,uint8_t * buff)377 int32_t iis3dhhc_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
378 {
379 int32_t ret;
380
381 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_WHO_AM_I, buff, 1);
382
383 return ret;
384 }
385
386 /**
387 * @brief Software reset. Restore the default values in user registers.[set]
388 *
389 * @param ctx Read / write interface definitions.(ptr)
390 * @param val Change the values of sw_reset in reg CTRL_REG1.
391 * @retval Interface status (MANDATORY: return 0 -> no Error).
392 *
393 */
iis3dhhc_reset_set(const stmdev_ctx_t * ctx,uint8_t val)394 int32_t iis3dhhc_reset_set(const stmdev_ctx_t *ctx, uint8_t val)
395 {
396 iis3dhhc_ctrl_reg1_t ctrl_reg1;
397 int32_t ret;
398
399 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG1,
400 (uint8_t *)&ctrl_reg1, 1);
401
402 if (ret == 0)
403 {
404 ctrl_reg1.sw_reset = val;
405 ret = iis3dhhc_write_reg(ctx, IIS3DHHC_CTRL_REG1,
406 (uint8_t *)&ctrl_reg1, 1);
407 }
408
409 return ret;
410 }
411
412 /**
413 * @brief Software reset. Restore the default values in user registers.[get]
414 *
415 * @param ctx Read / write interface definitions.(ptr)
416 * @param val Get the values of sw_reset in reg CTRL_REG1.(ptr)
417 * @retval Interface status (MANDATORY: return 0 -> no Error).
418 *
419 */
iis3dhhc_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)420 int32_t iis3dhhc_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
421 {
422 iis3dhhc_ctrl_reg1_t ctrl_reg1;
423 int32_t ret;
424
425 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG1,
426 (uint8_t *)&ctrl_reg1, 1);
427 *val = ctrl_reg1.sw_reset;
428
429 return ret;
430 }
431
432 /**
433 * @brief Reboot memory content. Reload the calibration parameters.[set]
434 *
435 * @param ctx Read / write interface definitions.(ptr)
436 * @param val Change the values of boot in reg CTRL_REG1
437 * @retval Interface status (MANDATORY: return 0 -> no Error).
438 *
439 */
iis3dhhc_boot_set(const stmdev_ctx_t * ctx,uint8_t val)440 int32_t iis3dhhc_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
441 {
442 iis3dhhc_ctrl_reg1_t ctrl_reg1;
443 int32_t ret;
444
445 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG1,
446 (uint8_t *)&ctrl_reg1, 1);
447
448 if (ret == 0)
449 {
450 ctrl_reg1.boot = val;
451 ret = iis3dhhc_write_reg(ctx, IIS3DHHC_CTRL_REG1,
452 (uint8_t *)&ctrl_reg1, 1);
453 }
454
455 return ret;
456 }
457
458 /**
459 * @brief Reboot memory content. Reload the calibration parameters.[get]
460 *
461 * @param ctx Read / write interface definitions.(ptr)
462 * @param val Get the values of boot in reg CTRL_REG1.(ptr)
463 * @retval Interface status (MANDATORY: return 0 -> no Error).
464 *
465 */
iis3dhhc_boot_get(const stmdev_ctx_t * ctx,uint8_t * val)466 int32_t iis3dhhc_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
467 {
468 iis3dhhc_ctrl_reg1_t ctrl_reg1;
469 int32_t ret;
470
471 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG1,
472 (uint8_t *)&ctrl_reg1, 1);
473 *val = ctrl_reg1.boot;
474
475 return ret;
476 }
477
478 /**
479 * @brief Selftest.[set]
480 *
481 * @param ctx Read / write interface definitions.(ptr)
482 * @param val Change the values of st in reg CTRL_REG4
483 * @retval Interface status (MANDATORY: return 0 -> no Error).
484 *
485 */
iis3dhhc_self_test_set(const stmdev_ctx_t * ctx,iis3dhhc_st_t val)486 int32_t iis3dhhc_self_test_set(const stmdev_ctx_t *ctx, iis3dhhc_st_t val)
487 {
488 iis3dhhc_ctrl_reg4_t ctrl_reg4;
489 int32_t ret;
490
491 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG4,
492 (uint8_t *)&ctrl_reg4, 1);
493
494 if (ret == 0)
495 {
496 ctrl_reg4.st = (uint8_t)val;
497 ret = iis3dhhc_write_reg(ctx, IIS3DHHC_CTRL_REG4,
498 (uint8_t *)&ctrl_reg4, 1);
499 }
500
501 return ret;
502 }
503
504 /**
505 * @brief Selftest.[get]
506 *
507 * @param ctx Read / write interface definitions.(ptr)
508 * @param val Get the values of st in reg CTRL_REG4.(ptr)
509 * @retval Interface status (MANDATORY: return 0 -> no Error).
510 *
511 */
iis3dhhc_self_test_get(const stmdev_ctx_t * ctx,iis3dhhc_st_t * val)512 int32_t iis3dhhc_self_test_get(const stmdev_ctx_t *ctx, iis3dhhc_st_t *val)
513 {
514 iis3dhhc_ctrl_reg4_t ctrl_reg4;
515 int32_t ret;
516
517 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG4,
518 (uint8_t *)&ctrl_reg4, 1);
519
520 switch (ctrl_reg4.st)
521 {
522 case IIS3DHHC_ST_DISABLE:
523 *val = IIS3DHHC_ST_DISABLE;
524 break;
525
526 case IIS3DHHC_ST_POSITIVE:
527 *val = IIS3DHHC_ST_POSITIVE;
528 break;
529
530 case IIS3DHHC_ST_NEGATIVE:
531 *val = IIS3DHHC_ST_NEGATIVE;
532 break;
533
534 default:
535 *val = IIS3DHHC_ST_DISABLE;
536 break;
537 }
538
539 return ret;
540 }
541
542 /**
543 * @brief Digital filtering Phase/bandwidth selection.[set]
544 *
545 * @param ctx Read / write interface definitions.(ptr)
546 * @param val Change the values of dsp in reg CTRL_REG4
547 * @retval Interface status (MANDATORY: return 0 -> no Error).
548 *
549 */
iis3dhhc_filter_config_set(const stmdev_ctx_t * ctx,iis3dhhc_dsp_t val)550 int32_t iis3dhhc_filter_config_set(const stmdev_ctx_t *ctx,
551 iis3dhhc_dsp_t val)
552 {
553 iis3dhhc_ctrl_reg4_t ctrl_reg4;
554 int32_t ret;
555
556 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG4,
557 (uint8_t *)&ctrl_reg4, 1);
558
559 if (ret == 0)
560 {
561 ctrl_reg4.dsp = (uint8_t)val;
562 ret = iis3dhhc_write_reg(ctx, IIS3DHHC_CTRL_REG4,
563 (uint8_t *)&ctrl_reg4, 1);
564 }
565
566 return ret;
567 }
568
569 /**
570 * @brief Digital filtering Phase/bandwidth selection.[get]
571 *
572 * @param ctx Read / write interface definitions.(ptr)
573 * @param val Get the values of dsp in reg CTRL_REG4.(ptr)
574 * @retval Interface status (MANDATORY: return 0 -> no Error).
575 *
576 */
iis3dhhc_filter_config_get(const stmdev_ctx_t * ctx,iis3dhhc_dsp_t * val)577 int32_t iis3dhhc_filter_config_get(const stmdev_ctx_t *ctx,
578 iis3dhhc_dsp_t *val)
579 {
580 iis3dhhc_ctrl_reg4_t ctrl_reg4;
581 int32_t ret;
582
583 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG4,
584 (uint8_t *)&ctrl_reg4, 1);
585
586 switch (ctrl_reg4.dsp)
587 {
588 case IIS3DHHC_LINEAR_PHASE_440Hz:
589 *val = IIS3DHHC_LINEAR_PHASE_440Hz;
590 break;
591
592 case IIS3DHHC_LINEAR_PHASE_235Hz:
593 *val = IIS3DHHC_LINEAR_PHASE_235Hz;
594 break;
595
596 case IIS3DHHC_NO_LINEAR_PHASE_440Hz:
597 *val = IIS3DHHC_NO_LINEAR_PHASE_440Hz;
598 break;
599
600 case IIS3DHHC_NO_LINEAR_PHASE_235Hz:
601 *val = IIS3DHHC_NO_LINEAR_PHASE_235Hz;
602 break;
603
604 default:
605 *val = IIS3DHHC_LINEAR_PHASE_440Hz;
606 break;
607 }
608
609 return ret;
610 }
611
612 /**
613 * @brief Statusregister.[get]
614 *
615 * @param ctx Read / write interface definitions.(ptr)
616 * @param val Get registers STATUS.(ptr)
617 * @retval Interface status (MANDATORY: return 0 -> no Error).
618 *
619 */
iis3dhhc_status_get(const stmdev_ctx_t * ctx,iis3dhhc_status_t * val)620 int32_t iis3dhhc_status_get(const stmdev_ctx_t *ctx, iis3dhhc_status_t *val)
621 {
622 int32_t ret;
623
624 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_STATUS, (uint8_t *) val, 1);
625
626 return ret;
627 }
628
629 /**
630 * @}
631 *
632 */
633
634 /**
635 * @defgroup IIS3DHHC_interrupts
636 * @brief This section group all the functions that manage interrupts
637 * @{
638 *
639 */
640
641 /**
642 * @brief DRDY latched / pulsed, pulse duration is 1/4 ODR.[set]
643 *
644 * @param ctx Read / write interface definitions.(ptr)
645 * @param val Change the values of drdy_pulse in reg CTRL_REG1
646 * @retval Interface status (MANDATORY: return 0 -> no Error).
647 *
648 */
iis3dhhc_drdy_notification_mode_set(const stmdev_ctx_t * ctx,iis3dhhc_drdy_pulse_t val)649 int32_t iis3dhhc_drdy_notification_mode_set(const stmdev_ctx_t *ctx,
650 iis3dhhc_drdy_pulse_t val)
651 {
652 iis3dhhc_ctrl_reg1_t ctrl_reg1;
653 int32_t ret;
654
655 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG1,
656 (uint8_t *)&ctrl_reg1, 1);
657
658 if (ret == 0)
659 {
660 ctrl_reg1.drdy_pulse = (uint8_t)val;
661 ret = iis3dhhc_write_reg(ctx, IIS3DHHC_CTRL_REG1,
662 (uint8_t *)&ctrl_reg1, 1);
663 }
664
665 return ret;
666 }
667
668 /**
669 * @brief DRDY latched / pulsed, pulse duration is 1/4 ODR.[get]
670 *
671 * @param ctx Read / write interface definitions.(ptr)
672 * @param val Get the values of drdy_pulse in reg CTRL_REG1.(ptr)
673 * @retval Interface status (MANDATORY: return 0 -> no Error).
674 *
675 */
iis3dhhc_drdy_notification_mode_get(const stmdev_ctx_t * ctx,iis3dhhc_drdy_pulse_t * val)676 int32_t iis3dhhc_drdy_notification_mode_get(const stmdev_ctx_t *ctx,
677 iis3dhhc_drdy_pulse_t *val)
678 {
679 iis3dhhc_ctrl_reg1_t ctrl_reg1;
680 int32_t ret;
681
682 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG1,
683 (uint8_t *)&ctrl_reg1, 1);
684
685 switch (ctrl_reg1.drdy_pulse)
686 {
687 case IIS3DHHC_LATCHED:
688 *val = IIS3DHHC_LATCHED;
689 break;
690
691 case IIS3DHHC_PULSED:
692 *val = IIS3DHHC_PULSED;
693 break;
694
695 default:
696 *val = IIS3DHHC_LATCHED;
697 break;
698 }
699
700 return ret;
701 }
702
703 /**
704 * @brief It configures the INT1 pad as output for FIFO flags or as
705 * external asynchronous input trigger to FIFO.[set]
706 *
707 * @param ctx Read / write interface definitions.(ptr)
708 * @param val Change the values of int1_ext in reg INT1_CTRL
709 * @retval Interface status (MANDATORY: return 0 -> no Error).
710 *
711 */
iis3dhhc_int1_mode_set(const stmdev_ctx_t * ctx,iis3dhhc_int1_ext_t val)712 int32_t iis3dhhc_int1_mode_set(const stmdev_ctx_t *ctx,
713 iis3dhhc_int1_ext_t val)
714 {
715 iis3dhhc_int1_ctrl_t int1_ctrl;
716 int32_t ret;
717
718 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT1_CTRL,
719 (uint8_t *)&int1_ctrl, 1);
720
721 if (ret == 0)
722 {
723 int1_ctrl.int1_ext = (uint8_t)val;
724 ret = iis3dhhc_write_reg(ctx, IIS3DHHC_INT1_CTRL,
725 (uint8_t *)&int1_ctrl, 1);
726 }
727
728 return ret;
729 }
730
731 /**
732 * @brief It configures the INT1 pad as output for FIFO flags or as
733 * external asynchronous input trigger to FIFO.[get]
734 *
735 * @param ctx Read / write interface definitions.(ptr)
736 * @param val Get the values of int1_ext in reg INT1_CTRL.(ptr)
737 * @retval Interface status (MANDATORY: return 0 -> no Error).
738 *
739 */
iis3dhhc_int1_mode_get(const stmdev_ctx_t * ctx,iis3dhhc_int1_ext_t * val)740 int32_t iis3dhhc_int1_mode_get(const stmdev_ctx_t *ctx,
741 iis3dhhc_int1_ext_t *val)
742 {
743 iis3dhhc_int1_ctrl_t int1_ctrl;
744 int32_t ret;
745
746 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT1_CTRL,
747 (uint8_t *)&int1_ctrl, 1);
748
749 switch (int1_ctrl.int1_ext)
750 {
751 case IIS3DHHC_PIN_AS_INTERRUPT:
752 *val = IIS3DHHC_PIN_AS_INTERRUPT;
753 break;
754
755 case IIS3DHHC_PIN_AS_TRIGGER:
756 *val = IIS3DHHC_PIN_AS_TRIGGER;
757 break;
758
759 default:
760 *val = IIS3DHHC_PIN_AS_INTERRUPT;
761 break;
762 }
763
764 return ret;
765 }
766
767 /**
768 * @brief FIFO watermark status on INT1 pin.[set]
769 *
770 * @param ctx Read / write interface definitions.(ptr)
771 * @param val Change the values of int1_fth in reg INT1_CTRL
772 * @retval Interface status (MANDATORY: return 0 -> no Error).
773 *
774 */
iis3dhhc_fifo_threshold_on_int1_set(const stmdev_ctx_t * ctx,uint8_t val)775 int32_t iis3dhhc_fifo_threshold_on_int1_set(const stmdev_ctx_t *ctx,
776 uint8_t val)
777 {
778 iis3dhhc_int1_ctrl_t int1_ctrl;
779 int32_t ret;
780
781 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT1_CTRL,
782 (uint8_t *)&int1_ctrl, 1);
783
784 if (ret == 0)
785 {
786 int1_ctrl.int1_fth = val;
787 ret = iis3dhhc_write_reg(ctx, IIS3DHHC_INT1_CTRL,
788 (uint8_t *)&int1_ctrl, 1);
789 }
790
791 return ret;
792 }
793
794 /**
795 * @brief FIFO watermark status on INT1 pin.[get]
796 *
797 * @param ctx Read / write interface definitions.(ptr)
798 * @param val Get the values of int1_fth in reg INT1_CTRL.(ptr)
799 * @retval Interface status (MANDATORY: return 0 -> no Error).
800 *
801 */
iis3dhhc_fifo_threshold_on_int1_get(const stmdev_ctx_t * ctx,uint8_t * val)802 int32_t iis3dhhc_fifo_threshold_on_int1_get(const stmdev_ctx_t *ctx,
803 uint8_t *val)
804 {
805 iis3dhhc_int1_ctrl_t int1_ctrl;
806 int32_t ret;
807
808 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT1_CTRL,
809 (uint8_t *)&int1_ctrl, 1);
810 *val = int1_ctrl.int1_fth;
811
812 return ret;
813 }
814
815 /**
816 * @brief FIFO full flag on INT1 pin.[set]
817 *
818 * @param ctx Read / write interface definitions.(ptr)
819 * @param val Change the values of int1_fss5 in reg INT1_CTRL
820 * @retval Interface status (MANDATORY: return 0 -> no Error).
821 *
822 */
iis3dhhc_fifo_full_on_int1_set(const stmdev_ctx_t * ctx,uint8_t val)823 int32_t iis3dhhc_fifo_full_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val)
824 {
825 iis3dhhc_int1_ctrl_t int1_ctrl;
826 int32_t ret;
827
828 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT1_CTRL,
829 (uint8_t *)&int1_ctrl, 1);
830
831 if (ret == 0)
832 {
833 int1_ctrl.int1_fss5 = val;
834 ret = iis3dhhc_write_reg(ctx, IIS3DHHC_INT1_CTRL,
835 (uint8_t *)&int1_ctrl, 1);
836 }
837
838 return ret;
839 }
840
841 /**
842 * @brief FIFO full flag on INT1 pin.[get]
843 *
844 * @param ctx Read / write interface definitions.(ptr)
845 * @param val Get the values of int1_fss5 in reg INT1_CTRL.(ptr)
846 * @retval Interface status (MANDATORY: return 0 -> no Error).
847 *
848 */
iis3dhhc_fifo_full_on_int1_get(const stmdev_ctx_t * ctx,uint8_t * val)849 int32_t iis3dhhc_fifo_full_on_int1_get(const stmdev_ctx_t *ctx,
850 uint8_t *val)
851 {
852 iis3dhhc_int1_ctrl_t int1_ctrl;
853 int32_t ret;
854
855 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT1_CTRL,
856 (uint8_t *)&int1_ctrl, 1);
857 *val = int1_ctrl.int1_fss5;
858
859 return ret;
860 }
861
862 /**
863 * @brief FIFO overrun interrupt on INT1 pin.[set]
864 *
865 * @param ctx Read / write interface definitions.(ptr)
866 * @param val Change the values of int1_ovr in reg INT1_CTRL
867 * @retval Interface status (MANDATORY: return 0 -> no Error).
868 *
869 */
iis3dhhc_fifo_ovr_on_int1_set(const stmdev_ctx_t * ctx,uint8_t val)870 int32_t iis3dhhc_fifo_ovr_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val)
871 {
872 iis3dhhc_int1_ctrl_t int1_ctrl;
873 int32_t ret;
874
875 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT1_CTRL,
876 (uint8_t *)&int1_ctrl, 1);
877
878 if (ret == 0)
879 {
880 int1_ctrl.int1_ovr = val;
881 ret = iis3dhhc_write_reg(ctx, IIS3DHHC_INT1_CTRL,
882 (uint8_t *)&int1_ctrl, 1);
883 }
884
885 return ret;
886 }
887
888 /**
889 * @brief FIFO overrun interrupt on INT1 pin.[get]
890 *
891 * @param ctx Read / write interface definitions.(ptr)
892 * @param val Get the values of int1_ovr in reg INT1_CTRL.(ptr)
893 * @retval Interface status (MANDATORY: return 0 -> no Error).
894 *
895 */
iis3dhhc_fifo_ovr_on_int1_get(const stmdev_ctx_t * ctx,uint8_t * val)896 int32_t iis3dhhc_fifo_ovr_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val)
897 {
898 iis3dhhc_int1_ctrl_t int1_ctrl;
899 int32_t ret;
900
901 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT1_CTRL,
902 (uint8_t *)&int1_ctrl, 1);
903 *val = int1_ctrl.int1_ovr;
904
905 return ret;
906 }
907
908 /**
909 * @brief BOOT status on INT1 pin.[set]
910 *
911 * @param ctx Read / write interface definitions.(ptr)
912 * @param val Change the values of int1_boot in reg INT1_CTRL
913 * @retval Interface status (MANDATORY: return 0 -> no Error).
914 *
915 */
iis3dhhc_boot_on_int1_set(const stmdev_ctx_t * ctx,uint8_t val)916 int32_t iis3dhhc_boot_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val)
917 {
918 iis3dhhc_int1_ctrl_t int1_ctrl;
919 int32_t ret;
920
921 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT1_CTRL,
922 (uint8_t *)&int1_ctrl, 1);
923
924 if (ret == 0)
925 {
926 int1_ctrl.int1_boot = val;
927 ret = iis3dhhc_write_reg(ctx, IIS3DHHC_INT1_CTRL,
928 (uint8_t *)&int1_ctrl, 1);
929 }
930
931 return ret;
932 }
933
934 /**
935 * @brief BOOT status on INT1 pin.[get]
936 *
937 * @param ctx Read / write interface definitions.(ptr)
938 * @param val Get the values of int1_boot in reg INT1_CTRL.(ptr)
939 * @retval Interface status (MANDATORY: return 0 -> no Error).
940 *
941 */
iis3dhhc_boot_on_int1_get(const stmdev_ctx_t * ctx,uint8_t * val)942 int32_t iis3dhhc_boot_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val)
943 {
944 iis3dhhc_int1_ctrl_t int1_ctrl;
945 int32_t ret;
946
947 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT1_CTRL,
948 (uint8_t *)&int1_ctrl, 1);
949 *val = int1_ctrl.int1_boot;
950
951 return ret;
952 }
953
954 /**
955 * @brief Data-ready signal on INT1 pin.[set]
956 *
957 * @param ctx Read / write interface definitions.(ptr)
958 * @param val Change the values of int1_drdy in reg INT1_CTRL
959 * @retval Interface status (MANDATORY: return 0 -> no Error).
960 *
961 */
iis3dhhc_drdy_on_int1_set(const stmdev_ctx_t * ctx,uint8_t val)962 int32_t iis3dhhc_drdy_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val)
963 {
964 iis3dhhc_int1_ctrl_t int1_ctrl;
965 int32_t ret;
966
967 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT1_CTRL,
968 (uint8_t *)&int1_ctrl, 1);
969
970 if (ret == 0)
971 {
972 int1_ctrl.int1_drdy = val;
973 ret = iis3dhhc_write_reg(ctx, IIS3DHHC_INT1_CTRL,
974 (uint8_t *)&int1_ctrl, 1);
975 }
976
977 return ret;
978 }
979
980 /**
981 * @brief Data-ready signal on INT1 pin.[get]
982 *
983 * @param ctx Read / write interface definitions.(ptr)
984 * @param val Get the values of int1_drdy in reg INT1_CTRL.(ptr)
985 * @retval Interface status (MANDATORY: return 0 -> no Error).
986 *
987 */
iis3dhhc_drdy_on_int1_get(const stmdev_ctx_t * ctx,uint8_t * val)988 int32_t iis3dhhc_drdy_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val)
989 {
990 iis3dhhc_int1_ctrl_t int1_ctrl;
991 int32_t ret;
992
993 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT1_CTRL,
994 (uint8_t *)&int1_ctrl, 1);
995 *val = int1_ctrl.int1_drdy;
996
997 return ret;
998 }
999
1000 /**
1001 * @brief FIFO watermark status on INT2 pin.[set]
1002 *
1003 * @param ctx Read / write interface definitions.(ptr)
1004 * @param val Change the values of int2_fth in reg INT2_CTRL
1005 * @retval Interface status (MANDATORY: return 0 -> no Error).
1006 *
1007 */
iis3dhhc_fifo_threshold_on_int2_set(const stmdev_ctx_t * ctx,uint8_t val)1008 int32_t iis3dhhc_fifo_threshold_on_int2_set(const stmdev_ctx_t *ctx,
1009 uint8_t val)
1010 {
1011 iis3dhhc_int2_ctrl_t int2_ctrl;
1012 int32_t ret;
1013
1014 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT2_CTRL,
1015 (uint8_t *)&int2_ctrl, 1);
1016
1017 if (ret == 0)
1018 {
1019 int2_ctrl.int2_fth = val;
1020 ret = iis3dhhc_write_reg(ctx, IIS3DHHC_INT2_CTRL,
1021 (uint8_t *)&int2_ctrl, 1);
1022 }
1023
1024 return ret;
1025 }
1026
1027 /**
1028 * @brief FIFO watermark status on INT2 pin.[get]
1029 *
1030 * @param ctx Read / write interface definitions.(ptr)
1031 * @param val Get the values of int2_fth in reg INT2_CTRL.(ptr)
1032 * @retval Interface status (MANDATORY: return 0 -> no Error).
1033 *
1034 */
iis3dhhc_fifo_threshold_on_int2_get(const stmdev_ctx_t * ctx,uint8_t * val)1035 int32_t iis3dhhc_fifo_threshold_on_int2_get(const stmdev_ctx_t *ctx,
1036 uint8_t *val)
1037 {
1038 iis3dhhc_int2_ctrl_t int2_ctrl;
1039 int32_t ret;
1040
1041 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT2_CTRL,
1042 (uint8_t *)&int2_ctrl, 1);
1043 *val = int2_ctrl.int2_fth;
1044
1045 return ret;
1046 }
1047
1048 /**
1049 * @brief FIFO full flag on INT2 pin.[set]
1050 *
1051 * @param ctx Read / write interface definitions.(ptr)
1052 * @param val Change the values of int2_fss5 in reg INT2_CTRL
1053 * @retval Interface status (MANDATORY: return 0 -> no Error).
1054 *
1055 */
iis3dhhc_fifo_full_on_int2_set(const stmdev_ctx_t * ctx,uint8_t val)1056 int32_t iis3dhhc_fifo_full_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val)
1057 {
1058 iis3dhhc_int2_ctrl_t int2_ctrl;
1059 int32_t ret;
1060
1061 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT2_CTRL,
1062 (uint8_t *)&int2_ctrl, 1);
1063
1064 if (ret == 0)
1065 {
1066 int2_ctrl.int2_fss5 = val;
1067 ret = iis3dhhc_write_reg(ctx, IIS3DHHC_INT2_CTRL,
1068 (uint8_t *)&int2_ctrl, 1);
1069 }
1070
1071 return ret;
1072 }
1073
1074 /**
1075 * @brief FIFO full flag on INT2 pin.[get]
1076 *
1077 * @param ctx Read / write interface definitions.(ptr)
1078 * @param val Get the values of int2_fss5 in reg INT2_CTRL.(ptr)
1079 * @retval Interface status (MANDATORY: return 0 -> no Error).
1080 *
1081 */
iis3dhhc_fifo_full_on_int2_get(const stmdev_ctx_t * ctx,uint8_t * val)1082 int32_t iis3dhhc_fifo_full_on_int2_get(const stmdev_ctx_t *ctx,
1083 uint8_t *val)
1084 {
1085 iis3dhhc_int2_ctrl_t int2_ctrl;
1086 int32_t ret;
1087
1088 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT2_CTRL,
1089 (uint8_t *)&int2_ctrl, 1);
1090 *val = int2_ctrl.int2_fss5;
1091
1092 return ret;
1093 }
1094
1095 /**
1096 * @brief FIFO overrun interrupt on INT2 pin.[set]
1097 *
1098 * @param ctx Read / write interface definitions.(ptr)
1099 * @param val Change the values of int2_ovr in reg INT2_CTRL
1100 * @retval Interface status (MANDATORY: return 0 -> no Error).
1101 *
1102 */
iis3dhhc_fifo_ovr_on_int2_set(const stmdev_ctx_t * ctx,uint8_t val)1103 int32_t iis3dhhc_fifo_ovr_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val)
1104 {
1105 iis3dhhc_int2_ctrl_t int2_ctrl;
1106 int32_t ret;
1107
1108 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT2_CTRL,
1109 (uint8_t *)&int2_ctrl, 1);
1110
1111 if (ret == 0)
1112 {
1113 int2_ctrl.int2_ovr = val;
1114 ret = iis3dhhc_write_reg(ctx, IIS3DHHC_INT2_CTRL,
1115 (uint8_t *)&int2_ctrl, 1);
1116 }
1117
1118 return ret;
1119 }
1120
1121 /**
1122 * @brief FIFO overrun interrupt on INT2 pin.[get]
1123 *
1124 * @param ctx Read / write interface definitions.(ptr)
1125 * @param val Get the values of int2_ovr in reg INT2_CTRL.(ptr)
1126 * @retval Interface status (MANDATORY: return 0 -> no Error).
1127 *
1128 */
iis3dhhc_fifo_ovr_on_int2_get(const stmdev_ctx_t * ctx,uint8_t * val)1129 int32_t iis3dhhc_fifo_ovr_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val)
1130 {
1131 iis3dhhc_int2_ctrl_t int2_ctrl;
1132 int32_t ret;
1133
1134 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT2_CTRL,
1135 (uint8_t *)&int2_ctrl, 1);
1136 *val = int2_ctrl.int2_ovr;
1137
1138 return ret;
1139 }
1140
1141 /**
1142 * @brief BOOT status on INT2 pin.[set]
1143 *
1144 * @param ctx Read / write interface definitions.(ptr)
1145 * @param val Change the values of int2_boot in reg INT2_CTRL
1146 * @retval Interface status (MANDATORY: return 0 -> no Error).
1147 *
1148 */
iis3dhhc_boot_on_int2_set(const stmdev_ctx_t * ctx,uint8_t val)1149 int32_t iis3dhhc_boot_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val)
1150 {
1151 iis3dhhc_int2_ctrl_t int2_ctrl;
1152 int32_t ret;
1153
1154 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT2_CTRL,
1155 (uint8_t *)&int2_ctrl, 1);
1156
1157 if (ret == 0)
1158 {
1159 int2_ctrl.int2_boot = val;
1160 ret = iis3dhhc_write_reg(ctx, IIS3DHHC_INT2_CTRL,
1161 (uint8_t *)&int2_ctrl, 1);
1162 }
1163
1164 return ret;
1165 }
1166
1167 /**
1168 * @brief BOOT status on INT2 pin.[get]
1169 *
1170 * @param ctx Read / write interface definitions.(ptr)
1171 * @param val Get the values of int2_boot in reg INT2_CTRL.(ptr)
1172 * @retval Interface status (MANDATORY: return 0 -> no Error).
1173 *
1174 */
iis3dhhc_boot_on_int2_get(const stmdev_ctx_t * ctx,uint8_t * val)1175 int32_t iis3dhhc_boot_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val)
1176 {
1177 iis3dhhc_int2_ctrl_t int2_ctrl;
1178 int32_t ret;
1179
1180 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT2_CTRL,
1181 (uint8_t *)&int2_ctrl, 1);
1182 *val = int2_ctrl.int2_boot;
1183
1184 return ret;
1185 }
1186
1187 /**
1188 * @brief Data-ready signal on INT2 pin.[set]
1189 *
1190 * @param ctx Read / write interface definitions.(ptr)
1191 * @param val Change the values of int2_drdy in reg INT2_CTRL
1192 * @retval Interface status (MANDATORY: return 0 -> no Error).
1193 *
1194 */
iis3dhhc_drdy_on_int2_set(const stmdev_ctx_t * ctx,uint8_t val)1195 int32_t iis3dhhc_drdy_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val)
1196 {
1197 iis3dhhc_int2_ctrl_t int2_ctrl;
1198 int32_t ret;
1199
1200 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT2_CTRL,
1201 (uint8_t *)&int2_ctrl, 1);
1202
1203 if (ret == 0)
1204 {
1205 int2_ctrl.int2_drdy = val;
1206 ret = iis3dhhc_write_reg(ctx, IIS3DHHC_INT2_CTRL,
1207 (uint8_t *)&int2_ctrl, 1);
1208 }
1209
1210 return ret;
1211 }
1212
1213 /**
1214 * @brief Data-ready signal on INT2 pin.[get]
1215 *
1216 * @param ctx Read / write interface definitions.(ptr)
1217 * @param val Get the values of int2_drdy in reg INT2_CTRL.(ptr)
1218 * @retval Interface status (MANDATORY: return 0 -> no Error).
1219 *
1220 */
iis3dhhc_drdy_on_int2_get(const stmdev_ctx_t * ctx,uint8_t * val)1221 int32_t iis3dhhc_drdy_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val)
1222 {
1223 iis3dhhc_int2_ctrl_t int2_ctrl;
1224 int32_t ret;
1225
1226 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT2_CTRL,
1227 (uint8_t *)&int2_ctrl, 1);
1228 *val = int2_ctrl.int2_drdy;
1229
1230 return ret;
1231 }
1232
1233 /**
1234 * @brief Push-pull/open drain selection on interrupt pads.[set]
1235 *
1236 * @param ctx Read / write interface definitions.(ptr)
1237 * @param val Change the values of pp_od in reg CTRL_REG4
1238 * @retval Interface status (MANDATORY: return 0 -> no Error).
1239 *
1240 */
iis3dhhc_pin_mode_set(const stmdev_ctx_t * ctx,iis3dhhc_pp_od_t val)1241 int32_t iis3dhhc_pin_mode_set(const stmdev_ctx_t *ctx, iis3dhhc_pp_od_t val)
1242 {
1243 iis3dhhc_ctrl_reg4_t ctrl_reg4;
1244 int32_t ret;
1245
1246 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG4,
1247 (uint8_t *)&ctrl_reg4, 1);
1248
1249 if (ret == 0)
1250 {
1251 ctrl_reg4.pp_od = (uint8_t)val;
1252 ret = iis3dhhc_write_reg(ctx, IIS3DHHC_CTRL_REG4,
1253 (uint8_t *)&ctrl_reg4, 1);
1254 }
1255
1256 return ret;
1257 }
1258
1259 /**
1260 * @brief Push-pull/open drain selection on interrupt pads.[get]
1261 *
1262 * @param ctx Read / write interface definitions.(ptr)
1263 * @param val Get the values of pp_od in reg CTRL_REG4.(ptr)
1264 * @retval Interface status (MANDATORY: return 0 -> no Error).
1265 *
1266 */
iis3dhhc_pin_mode_get(const stmdev_ctx_t * ctx,iis3dhhc_pp_od_t * val)1267 int32_t iis3dhhc_pin_mode_get(const stmdev_ctx_t *ctx,
1268 iis3dhhc_pp_od_t *val)
1269 {
1270 iis3dhhc_ctrl_reg4_t ctrl_reg4;
1271 int32_t ret;
1272
1273 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG4,
1274 (uint8_t *)&ctrl_reg4, 1);
1275
1276 switch (ctrl_reg4.pp_od)
1277 {
1278 case IIS3DHHC_ALL_PUSH_PULL:
1279 *val = IIS3DHHC_ALL_PUSH_PULL;
1280 break;
1281
1282 case IIS3DHHC_INT1_OD_INT2_PP:
1283 *val = IIS3DHHC_INT1_OD_INT2_PP;
1284 break;
1285
1286 case IIS3DHHC_INT1_PP_INT2_OD:
1287 *val = IIS3DHHC_INT1_PP_INT2_OD;
1288 break;
1289
1290 case IIS3DHHC_ALL_OPEN_DRAIN:
1291 *val = IIS3DHHC_ALL_OPEN_DRAIN;
1292 break;
1293
1294 default:
1295 *val = IIS3DHHC_ALL_PUSH_PULL;
1296 break;
1297 }
1298
1299 return ret;
1300 }
1301
1302 /**
1303 * @}
1304 *
1305 */
1306
1307 /**
1308 * @defgroup IIS3DHHC_fifo
1309 * @brief This section group all the functions concerning the
1310 * fifo usage
1311 * @{
1312 *
1313 */
1314
1315 /**
1316 * @brief FIFOenable.[set]
1317 *
1318 * @param ctx Read / write interface definitions.(ptr)
1319 * @param val Change the values of fifo_en in reg CTRL_REG4
1320 * @retval Interface status (MANDATORY: return 0 -> no Error).
1321 *
1322 */
iis3dhhc_fifo_set(const stmdev_ctx_t * ctx,uint8_t val)1323 int32_t iis3dhhc_fifo_set(const stmdev_ctx_t *ctx, uint8_t val)
1324 {
1325 iis3dhhc_ctrl_reg4_t ctrl_reg4;
1326 int32_t ret;
1327
1328 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG4,
1329 (uint8_t *)&ctrl_reg4, 1);
1330
1331 if (ret == 0)
1332 {
1333 ctrl_reg4.fifo_en = val;
1334 ret = iis3dhhc_write_reg(ctx, IIS3DHHC_CTRL_REG4,
1335 (uint8_t *)&ctrl_reg4, 1);
1336 }
1337
1338 return ret;
1339 }
1340
1341 /**
1342 * @brief FIFOenable.[get]
1343 *
1344 * @param ctx Read / write interface definitions.(ptr)
1345 * @param val Get the values of fifo_en in reg CTRL_REG4.(ptr)
1346 * @retval Interface status (MANDATORY: return 0 -> no Error).
1347 *
1348 */
iis3dhhc_fifo_get(const stmdev_ctx_t * ctx,uint8_t * val)1349 int32_t iis3dhhc_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val)
1350 {
1351 iis3dhhc_ctrl_reg4_t ctrl_reg4;
1352 int32_t ret;
1353
1354 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG4,
1355 (uint8_t *)&ctrl_reg4, 1);
1356 *val = ctrl_reg4.fifo_en;
1357
1358 return ret;
1359 }
1360
1361 /**
1362 * @brief Enables the SPI high speed configuration for the FIFO block that
1363 is used to guarantee a minimum duration of the window in which
1364 writing operation of RAM output is blocked. This bit is recommended
1365 for SPI clock frequencies higher than 6 MHz.[set]
1366 *
1367 * @param ctx Read / write interface definitions.(ptr)
1368 * @param val Change the values of fifo_spi_hs_on in reg CTRL_REG5
1369 * @retval Interface status (MANDATORY: return 0 -> no Error).
1370 *
1371 */
iis3dhhc_fifo_block_spi_hs_set(const stmdev_ctx_t * ctx,uint8_t val)1372 int32_t iis3dhhc_fifo_block_spi_hs_set(const stmdev_ctx_t *ctx, uint8_t val)
1373 {
1374 iis3dhhc_ctrl_reg5_t ctrl_reg5;
1375 int32_t ret;
1376
1377 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG5,
1378 (uint8_t *)&ctrl_reg5, 1);
1379
1380 if (ret == 0)
1381 {
1382 ctrl_reg5.fifo_spi_hs_on = val;
1383 ret = iis3dhhc_write_reg(ctx, IIS3DHHC_CTRL_REG5,
1384 (uint8_t *)&ctrl_reg5, 1);
1385 }
1386
1387 return ret;
1388 }
1389
1390 /**
1391 * @brief Enables the SPI high speed configuration for the FIFO block that
1392 is used to guarantee a minimum duration of the window in which
1393 writing operation of RAM output is blocked. This bit is recommended
1394 for SPI clock frequencies higher than 6 MHz.[get]
1395 *
1396 * @param ctx Read / write interface definitions.(ptr)
1397 * @param val Get the values of fifo_spi_hs_on in reg CTRL_REG5.(ptr)
1398 * @retval Interface status (MANDATORY: return 0 -> no Error).
1399 *
1400 */
iis3dhhc_fifo_block_spi_hs_get(const stmdev_ctx_t * ctx,uint8_t * val)1401 int32_t iis3dhhc_fifo_block_spi_hs_get(const stmdev_ctx_t *ctx,
1402 uint8_t *val)
1403 {
1404 iis3dhhc_ctrl_reg5_t ctrl_reg5;
1405 int32_t ret;
1406
1407 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG5,
1408 (uint8_t *)&ctrl_reg5, 1);
1409 *val = ctrl_reg5.fifo_spi_hs_on;
1410
1411 return ret;
1412 }
1413
1414 /**
1415 * @brief FIFO watermark level selection.[set]
1416 *
1417 * @param ctx Read / write interface definitions.(ptr)
1418 * @param val Change the values of fth in reg FIFO_CTRL
1419 * @retval Interface status (MANDATORY: return 0 -> no Error).
1420 *
1421 */
iis3dhhc_fifo_watermark_set(const stmdev_ctx_t * ctx,uint8_t val)1422 int32_t iis3dhhc_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val)
1423 {
1424 iis3dhhc_fifo_ctrl_t fifo_ctrl;
1425 int32_t ret;
1426
1427 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_FIFO_CTRL,
1428 (uint8_t *)&fifo_ctrl, 1);
1429
1430 if (ret == 0)
1431 {
1432 fifo_ctrl.fth = val;
1433 ret = iis3dhhc_write_reg(ctx, IIS3DHHC_FIFO_CTRL,
1434 (uint8_t *)&fifo_ctrl, 1);
1435 }
1436
1437 return ret;
1438 }
1439
1440 /**
1441 * @brief FIFO watermark level selection.[get]
1442 *
1443 * @param ctx Read / write interface definitions.(ptr)
1444 * @param val Get the values of fth in reg FIFO_CTRL.(ptr)
1445 * @retval Interface status (MANDATORY: return 0 -> no Error).
1446 *
1447 */
iis3dhhc_fifo_watermark_get(const stmdev_ctx_t * ctx,uint8_t * val)1448 int32_t iis3dhhc_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val)
1449 {
1450 iis3dhhc_fifo_ctrl_t fifo_ctrl;
1451 int32_t ret;
1452
1453 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_FIFO_CTRL,
1454 (uint8_t *)&fifo_ctrl, 1);
1455 *val = fifo_ctrl.fth;
1456
1457 return ret;
1458 }
1459
1460 /**
1461 * @brief FIFO mode selection.[set]
1462 *
1463 * @param ctx Read / write interface definitions.(ptr)
1464 * @param val Change the values of fmode in reg FIFO_CTRL
1465 * @retval Interface status (MANDATORY: return 0 -> no Error).
1466 *
1467 */
iis3dhhc_fifo_mode_set(const stmdev_ctx_t * ctx,iis3dhhc_fmode_t val)1468 int32_t iis3dhhc_fifo_mode_set(const stmdev_ctx_t *ctx,
1469 iis3dhhc_fmode_t val)
1470 {
1471 iis3dhhc_fifo_ctrl_t fifo_ctrl;
1472 int32_t ret;
1473
1474 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_FIFO_CTRL,
1475 (uint8_t *)&fifo_ctrl, 1);
1476
1477 if (ret == 0)
1478 {
1479 fifo_ctrl.fmode = (uint8_t)val;
1480 ret = iis3dhhc_write_reg(ctx, IIS3DHHC_FIFO_CTRL,
1481 (uint8_t *)&fifo_ctrl, 1);
1482 }
1483
1484 return ret;
1485 }
1486
1487 /**
1488 * @brief FIFO mode selection.[get]
1489 *
1490 * @param ctx Read / write interface definitions.(ptr)
1491 * @param val Get the values of fmode in reg FIFO_CTRL.(ptr)
1492 * @retval Interface status (MANDATORY: return 0 -> no Error).
1493 *
1494 */
iis3dhhc_fifo_mode_get(const stmdev_ctx_t * ctx,iis3dhhc_fmode_t * val)1495 int32_t iis3dhhc_fifo_mode_get(const stmdev_ctx_t *ctx,
1496 iis3dhhc_fmode_t *val)
1497 {
1498 iis3dhhc_fifo_ctrl_t fifo_ctrl;
1499 int32_t ret;
1500
1501 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_FIFO_CTRL,
1502 (uint8_t *)&fifo_ctrl, 1);
1503
1504 switch (fifo_ctrl.fmode)
1505 {
1506 case IIS3DHHC_BYPASS_MODE:
1507 *val = IIS3DHHC_BYPASS_MODE;
1508 break;
1509
1510 case IIS3DHHC_FIFO_MODE:
1511 *val = IIS3DHHC_FIFO_MODE;
1512 break;
1513
1514 case IIS3DHHC_STREAM_TO_FIFO_MODE:
1515 *val = IIS3DHHC_STREAM_TO_FIFO_MODE;
1516 break;
1517
1518 case IIS3DHHC_BYPASS_TO_STREAM_MODE:
1519 *val = IIS3DHHC_BYPASS_TO_STREAM_MODE;
1520 break;
1521
1522 case IIS3DHHC_DYNAMIC_STREAM_MODE:
1523 *val = IIS3DHHC_DYNAMIC_STREAM_MODE;
1524 break;
1525
1526 default:
1527 *val = IIS3DHHC_BYPASS_MODE;
1528 break;
1529 }
1530
1531 return ret;
1532 }
1533
1534 /**
1535 * @brief FIFO status register.[get]
1536 *
1537 * @param ctx Read / write interface definitions.(ptr)
1538 * @param val Get registers FIFO_SRC.(ptr)
1539 * @retval Interface status (MANDATORY: return 0 -> no Error).
1540 *
1541 */
iis3dhhc_fifo_status_get(const stmdev_ctx_t * ctx,iis3dhhc_fifo_src_t * val)1542 int32_t iis3dhhc_fifo_status_get(const stmdev_ctx_t *ctx,
1543 iis3dhhc_fifo_src_t *val)
1544 {
1545 int32_t ret;
1546
1547 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_FIFO_SRC, (uint8_t *) val, 1);
1548
1549 return ret;
1550 }
1551
1552 /**
1553 * @brief FIFO stored data level.[get]
1554 *
1555 * @param ctx Read / write interface definitions.(ptr)
1556 * @param val Get the values of fss in reg FIFO_SRC.(ptr)
1557 * @retval Interface status (MANDATORY: return 0 -> no Error).
1558 *
1559 */
iis3dhhc_fifo_full_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)1560 int32_t iis3dhhc_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
1561 {
1562 iis3dhhc_fifo_src_t fifo_src;
1563 int32_t ret;
1564
1565 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_FIFO_SRC, (uint8_t *)&fifo_src, 1);
1566 *val = fifo_src.fss;
1567
1568 return ret;
1569 }
1570
1571 /**
1572 * @brief FIFO overrun status flag.[get]
1573 *
1574 * @param ctx Read / write interface definitions.(ptr)
1575 * @param val Get the values of ovrn in reg FIFO_SRC.(ptr)
1576 * @retval Interface status (MANDATORY: return 0 -> no Error).
1577 *
1578 */
iis3dhhc_fifo_ovr_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)1579 int32_t iis3dhhc_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
1580 {
1581 iis3dhhc_fifo_src_t fifo_src;
1582 int32_t ret;
1583
1584 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_FIFO_SRC, (uint8_t *)&fifo_src, 1);
1585 *val = fifo_src.ovrn;
1586
1587 return ret;
1588 }
1589
1590 /**
1591 * @brief FIFO watermark status.[get]
1592 *
1593 * @param ctx Read / write interface definitions.(ptr)
1594 * @param val Get the values of fth in reg FIFO_SRC.(ptr)
1595 * @retval Interface status (MANDATORY: return 0 -> no Error).
1596 *
1597 */
iis3dhhc_fifo_fth_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)1598 int32_t iis3dhhc_fifo_fth_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
1599 {
1600 iis3dhhc_fifo_src_t fifo_src;
1601 int32_t ret;
1602
1603 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_FIFO_SRC, (uint8_t *)&fifo_src, 1);
1604 *val = fifo_src.fth;
1605
1606 return ret;
1607 }
1608
1609 /**
1610 * @}
1611 *
1612 */
1613
1614 /**
1615 * @defgroup IIS3DHHC_serial_interface
1616 * @brief This section group all the functions concerning serial
1617 * interface management
1618 * @{
1619 *
1620 */
1621
1622 /**
1623 * @brief Register address automatically incremented during a multiple byte
1624 * access with a serial interface (I2C or SPI).[set]
1625 *
1626 * @param ctx Read / write interface definitions.(ptr)
1627 * @param val Change the values of if_add_inc in reg CTRL_REG1
1628 * @retval Interface status (MANDATORY: return 0 -> no Error).
1629 *
1630 */
iis3dhhc_auto_add_inc_set(const stmdev_ctx_t * ctx,uint8_t val)1631 int32_t iis3dhhc_auto_add_inc_set(const stmdev_ctx_t *ctx, uint8_t val)
1632 {
1633 iis3dhhc_ctrl_reg1_t ctrl_reg1;
1634 int32_t ret;
1635
1636 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG1,
1637 (uint8_t *)&ctrl_reg1, 1);
1638
1639 if (ret == 0)
1640 {
1641 ctrl_reg1.if_add_inc = val;
1642 ret = iis3dhhc_write_reg(ctx, IIS3DHHC_CTRL_REG1,
1643 (uint8_t *)&ctrl_reg1, 1);
1644 }
1645
1646 return ret;
1647 }
1648
1649 /**
1650 * @brief Register address automatically incremented during a multiple byte
1651 * access with a serial interface (I2C or SPI).[get]
1652 *
1653 * @param ctx Read / write interface definitions.(ptr)
1654 * @param val Get the values of if_add_inc in reg CTRL_REG1.(ptr)
1655 * @retval Interface status (MANDATORY: return 0 -> no Error).
1656 *
1657 */
iis3dhhc_auto_add_inc_get(const stmdev_ctx_t * ctx,uint8_t * val)1658 int32_t iis3dhhc_auto_add_inc_get(const stmdev_ctx_t *ctx, uint8_t *val)
1659 {
1660 iis3dhhc_ctrl_reg1_t ctrl_reg1;
1661 int32_t ret;
1662
1663 ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG1,
1664 (uint8_t *)&ctrl_reg1, 1);
1665 *val = ctrl_reg1.if_add_inc;
1666
1667 return ret;
1668 }
1669
1670 /**
1671 * @}
1672 *
1673 */
1674
1675 /**
1676 * @}
1677 *
1678 */
1679
1680 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1681
