1 /** 2 ****************************************************************************** 3 * @file iis2mdc_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * iis2mdc_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef IIS2MDC_REGS_H 23 #define IIS2MDC_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup IIS2MDC 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 /* #define DRV_BYTE_ORDER DRV_BIG_ENDIAN */ 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup iis2mdc_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format **/ 172 #define IIS2MDC_I2C_ADD 0x3DU 173 174 /** Device Identification (Who am I) **/ 175 #define IIS2MDC_ID 0x40U 176 177 /** 178 * @} 179 * 180 */ 181 182 #define IIS2MDC_OFFSET_X_REG_L 0x45U 183 #define IIS2MDC_OFFSET_X_REG_H 0x46U 184 #define IIS2MDC_OFFSET_Y_REG_L 0x47U 185 #define IIS2MDC_OFFSET_Y_REG_H 0x48U 186 #define IIS2MDC_OFFSET_Z_REG_L 0x49U 187 #define IIS2MDC_OFFSET_Z_REG_H 0x4AU 188 #define IIS2MDC_WHO_AM_I 0x4FU 189 #define IIS2MDC_CFG_REG_A 0x60U 190 typedef struct 191 { 192 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 193 uint8_t md : 2; 194 uint8_t odr : 2; 195 uint8_t lp : 1; 196 uint8_t soft_rst : 1; 197 uint8_t reboot : 1; 198 uint8_t comp_temp_en : 1; 199 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 200 uint8_t comp_temp_en : 1; 201 uint8_t reboot : 1; 202 uint8_t soft_rst : 1; 203 uint8_t lp : 1; 204 uint8_t odr : 2; 205 uint8_t md : 2; 206 #endif /* DRV_BYTE_ORDER */ 207 } iis2mdc_cfg_reg_a_t; 208 209 #define IIS2MDC_CFG_REG_B 0x61U 210 typedef struct 211 { 212 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 213 uint8_t lpf : 1; 214 uint8_t set_rst : 2; /* OFF_CANC + Set_FREQ */ 215 uint8_t int_on_dataoff : 1; 216 uint8_t off_canc_one_shot : 1; 217 uint8_t not_used_01 : 3; 218 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 219 uint8_t not_used_01 : 3; 220 uint8_t off_canc_one_shot : 1; 221 uint8_t int_on_dataoff : 1; 222 uint8_t set_rst : 2; /* OFF_CANC + Set_FREQ */ 223 uint8_t lpf : 1; 224 #endif /* DRV_BYTE_ORDER */ 225 } iis2mdc_cfg_reg_b_t; 226 227 #define IIS2MDC_CFG_REG_C 0x62U 228 typedef struct 229 { 230 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 231 uint8_t drdy_on_pin : 1; 232 uint8_t self_test : 1; 233 uint8_t not_used_01 : 1; 234 uint8_t ble : 1; 235 uint8_t bdu : 1; 236 uint8_t i2c_dis : 1; 237 uint8_t int_on_pin : 1; 238 uint8_t not_used_02 : 1; 239 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 240 uint8_t not_used_02 : 1; 241 uint8_t int_on_pin : 1; 242 uint8_t i2c_dis : 1; 243 uint8_t bdu : 1; 244 uint8_t ble : 1; 245 uint8_t not_used_01 : 1; 246 uint8_t self_test : 1; 247 uint8_t drdy_on_pin : 1; 248 #endif /* DRV_BYTE_ORDER */ 249 } iis2mdc_cfg_reg_c_t; 250 251 #define IIS2MDC_INT_CRTL_REG 0x63U 252 typedef struct 253 { 254 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 255 uint8_t ien : 1; 256 uint8_t iel : 1; 257 uint8_t iea : 1; 258 uint8_t not_used_01 : 2; 259 uint8_t zien : 1; 260 uint8_t yien : 1; 261 uint8_t xien : 1; 262 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 263 uint8_t xien : 1; 264 uint8_t yien : 1; 265 uint8_t zien : 1; 266 uint8_t not_used_01 : 2; 267 uint8_t iea : 1; 268 uint8_t iel : 1; 269 uint8_t ien : 1; 270 #endif /* DRV_BYTE_ORDER */ 271 } iis2mdc_int_crtl_reg_t; 272 273 #define IIS2MDC_INT_SOURCE_REG 0x64U 274 typedef struct 275 { 276 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 277 uint8_t _int : 1; 278 uint8_t mroi : 1; 279 uint8_t n_th_s_z : 1; 280 uint8_t n_th_s_y : 1; 281 uint8_t n_th_s_x : 1; 282 uint8_t p_th_s_z : 1; 283 uint8_t p_th_s_y : 1; 284 uint8_t p_th_s_x : 1; 285 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 286 uint8_t p_th_s_x : 1; 287 uint8_t p_th_s_y : 1; 288 uint8_t p_th_s_z : 1; 289 uint8_t n_th_s_x : 1; 290 uint8_t n_th_s_y : 1; 291 uint8_t n_th_s_z : 1; 292 uint8_t mroi : 1; 293 uint8_t _int : 1; 294 #endif /* DRV_BYTE_ORDER */ 295 296 } iis2mdc_int_source_reg_t; 297 298 #define IIS2MDC_INT_THS_L_REG 0x65U 299 #define IIS2MDC_INT_THS_H_REG 0x66U 300 #define IIS2MDC_STATUS_REG 0x67U 301 typedef struct 302 { 303 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 304 uint8_t xda : 1; 305 uint8_t yda : 1; 306 uint8_t zda : 1; 307 uint8_t zyxda : 1; 308 uint8_t _xor : 1; 309 uint8_t yor : 1; 310 uint8_t zor : 1; 311 uint8_t zyxor : 1; 312 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 313 uint8_t zyxor : 1; 314 uint8_t zor : 1; 315 uint8_t yor : 1; 316 uint8_t _xor : 1; 317 uint8_t zyxda : 1; 318 uint8_t zda : 1; 319 uint8_t yda : 1; 320 uint8_t xda : 1; 321 #endif /* DRV_BYTE_ORDER */ 322 } iis2mdc_status_reg_t; 323 324 #define IIS2MDC_OUTX_L_REG 0x68U 325 #define IIS2MDC_OUTX_H_REG 0x69U 326 #define IIS2MDC_OUTY_L_REG 0x6AU 327 #define IIS2MDC_OUTY_H_REG 0x6BU 328 #define IIS2MDC_OUTZ_L_REG 0x6CU 329 #define IIS2MDC_OUTZ_H_REG 0x6DU 330 #define IIS2MDC_TEMP_OUT_L_REG 0x6EU 331 #define IIS2MDC_TEMP_OUT_H_REG 0x6FU 332 333 typedef union 334 { 335 iis2mdc_cfg_reg_a_t cfg_reg_a; 336 iis2mdc_cfg_reg_b_t cfg_reg_b; 337 iis2mdc_cfg_reg_c_t cfg_reg_c; 338 iis2mdc_int_crtl_reg_t int_crtl_reg; 339 iis2mdc_int_source_reg_t int_source_reg; 340 iis2mdc_status_reg_t status_reg; 341 bitwise_t bitwise; 342 uint8_t byte; 343 } iis2mdc_reg_t; 344 345 #ifndef __weak 346 #define __weak __attribute__((weak)) 347 #endif /* __weak */ 348 349 /* 350 * These are the basic platform dependent I/O routines to read 351 * and write device registers connected on a standard bus. 352 * The driver keeps offering a default implementation based on function 353 * pointers to read/write routines for backward compatibility. 354 * The __weak directive allows the final application to overwrite 355 * them with a custom implementation. 356 */ 357 int32_t iis2mdc_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 358 uint8_t *data, 359 uint16_t len); 360 int32_t iis2mdc_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 361 uint8_t *data, 362 uint16_t len); 363 364 float_t iis2mdc_from_lsb_to_mgauss(int16_t lsb); 365 float_t iis2mdc_from_lsb_to_celsius(int16_t lsb); 366 367 int32_t iis2mdc_mag_user_offset_set(const stmdev_ctx_t *ctx, int16_t *val); 368 int32_t iis2mdc_mag_user_offset_get(const stmdev_ctx_t *ctx, int16_t *val); 369 typedef enum 370 { 371 IIS2MDC_CONTINUOUS_MODE = 0, 372 IIS2MDC_SINGLE_TRIGGER = 1, 373 IIS2MDC_POWER_DOWN = 2, 374 } iis2mdc_md_t; 375 int32_t iis2mdc_operating_mode_set(const stmdev_ctx_t *ctx, 376 iis2mdc_md_t val); 377 int32_t iis2mdc_operating_mode_get(const stmdev_ctx_t *ctx, 378 iis2mdc_md_t *val); 379 380 typedef enum 381 { 382 IIS2MDC_ODR_10Hz = 0, 383 IIS2MDC_ODR_20Hz = 1, 384 IIS2MDC_ODR_50Hz = 2, 385 IIS2MDC_ODR_100Hz = 3, 386 } iis2mdc_odr_t; 387 int32_t iis2mdc_data_rate_set(const stmdev_ctx_t *ctx, iis2mdc_odr_t val); 388 int32_t iis2mdc_data_rate_get(const stmdev_ctx_t *ctx, iis2mdc_odr_t *val); 389 390 typedef enum 391 { 392 IIS2MDC_HIGH_RESOLUTION = 0, 393 IIS2MDC_LOW_POWER = 1, 394 } iis2mdc_lp_t; 395 int32_t iis2mdc_power_mode_set(const stmdev_ctx_t *ctx, iis2mdc_lp_t val); 396 int32_t iis2mdc_power_mode_get(const stmdev_ctx_t *ctx, iis2mdc_lp_t *val); 397 398 int32_t iis2mdc_offset_temp_comp_set(const stmdev_ctx_t *ctx, uint8_t val); 399 int32_t iis2mdc_offset_temp_comp_get(const stmdev_ctx_t *ctx, uint8_t *val); 400 401 typedef enum 402 { 403 IIS2MDC_ODR_DIV_2 = 0, 404 IIS2MDC_ODR_DIV_4 = 1, 405 } iis2mdc_lpf_t; 406 int32_t iis2mdc_low_pass_bandwidth_set(const stmdev_ctx_t *ctx, 407 iis2mdc_lpf_t val); 408 int32_t iis2mdc_low_pass_bandwidth_get(const stmdev_ctx_t *ctx, 409 iis2mdc_lpf_t *val); 410 411 typedef enum 412 { 413 IIS2MDC_SET_SENS_ODR_DIV_63 = 0, 414 IIS2MDC_SENS_OFF_CANC_EVERY_ODR = 1, 415 IIS2MDC_SET_SENS_ONLY_AT_POWER_ON = 2, 416 } iis2mdc_set_rst_t; 417 int32_t iis2mdc_set_rst_mode_set(const stmdev_ctx_t *ctx, 418 iis2mdc_set_rst_t val); 419 int32_t iis2mdc_set_rst_mode_get(const stmdev_ctx_t *ctx, 420 iis2mdc_set_rst_t *val); 421 422 int32_t iis2mdc_set_rst_sensor_single_set(const stmdev_ctx_t *ctx, 423 uint8_t val); 424 int32_t iis2mdc_set_rst_sensor_single_get(const stmdev_ctx_t *ctx, 425 uint8_t *val); 426 427 int32_t iis2mdc_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); 428 int32_t iis2mdc_block_data_update_get(const stmdev_ctx_t *ctx, 429 uint8_t *val); 430 431 int32_t iis2mdc_mag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); 432 433 int32_t iis2mdc_mag_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val); 434 435 int32_t iis2mdc_magnetic_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 436 437 int32_t iis2mdc_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 438 439 int32_t iis2mdc_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); 440 441 int32_t iis2mdc_reset_set(const stmdev_ctx_t *ctx, uint8_t val); 442 int32_t iis2mdc_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); 443 444 int32_t iis2mdc_boot_set(const stmdev_ctx_t *ctx, uint8_t val); 445 int32_t iis2mdc_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); 446 447 int32_t iis2mdc_self_test_set(const stmdev_ctx_t *ctx, uint8_t val); 448 int32_t iis2mdc_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val); 449 450 typedef enum 451 { 452 IIS2MDC_LSB_AT_LOW_ADD = 0, 453 IIS2MDC_MSB_AT_LOW_ADD = 1, 454 } iis2mdc_ble_t; 455 int32_t iis2mdc_data_format_set(const stmdev_ctx_t *ctx, iis2mdc_ble_t val); 456 int32_t iis2mdc_data_format_get(const stmdev_ctx_t *ctx, 457 iis2mdc_ble_t *val); 458 459 int32_t iis2mdc_status_get(const stmdev_ctx_t *ctx, 460 iis2mdc_status_reg_t *val); 461 462 typedef enum 463 { 464 IIS2MDC_CHECK_BEFORE = 0, 465 IIS2MDC_CHECK_AFTER = 1, 466 } iis2mdc_int_on_dataoff_t; 467 int32_t iis2mdc_offset_int_conf_set(const stmdev_ctx_t *ctx, 468 iis2mdc_int_on_dataoff_t val); 469 int32_t iis2mdc_offset_int_conf_get(const stmdev_ctx_t *ctx, 470 iis2mdc_int_on_dataoff_t *val); 471 472 int32_t iis2mdc_drdy_on_pin_set(const stmdev_ctx_t *ctx, uint8_t val); 473 int32_t iis2mdc_drdy_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val); 474 475 int32_t iis2mdc_int_on_pin_set(const stmdev_ctx_t *ctx, uint8_t val); 476 int32_t iis2mdc_int_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val); 477 478 int32_t iis2mdc_int_gen_conf_set(const stmdev_ctx_t *ctx, 479 iis2mdc_int_crtl_reg_t *val); 480 int32_t iis2mdc_int_gen_conf_get(const stmdev_ctx_t *ctx, 481 iis2mdc_int_crtl_reg_t *val); 482 483 int32_t iis2mdc_int_gen_source_get(const stmdev_ctx_t *ctx, 484 iis2mdc_int_source_reg_t *val); 485 486 int32_t iis2mdc_int_gen_threshold_set(const stmdev_ctx_t *ctx, int16_t val); 487 int32_t iis2mdc_int_gen_threshold_get(const stmdev_ctx_t *ctx, int16_t *val); 488 489 typedef enum 490 { 491 IIS2MDC_I2C_ENABLE = 0, 492 IIS2MDC_I2C_DISABLE = 1, 493 } iis2mdc_i2c_dis_t; 494 int32_t iis2mdc_i2c_interface_set(const stmdev_ctx_t *ctx, 495 iis2mdc_i2c_dis_t val); 496 int32_t iis2mdc_i2c_interface_get(const stmdev_ctx_t *ctx, 497 iis2mdc_i2c_dis_t *val); 498 499 /** 500 * @} 501 * 502 */ 503 504 #ifdef __cplusplus 505 } 506 #endif 507 508 #endif /* IIS2MDC_REGS_H */ 509 510 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 511
