1 /**
2 ******************************************************************************
3 * @file iis2mdc_reg.c
4 * @author Sensors Software Solution Team
5 * @brief IIS2MDC driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "iis2mdc_reg.h"
21 /**
22 * @defgroup IIS2MDC
23 * @brief This file provides a set of functions needed to drive the
24 * iis2mdc enhanced inertial module.
25 * @{
26 *
27 */
28
29 /**
30 * @defgroup IIS2MDC_Interfaces_Functions
31 * @brief This section provide a set of functions used to read and
32 * write a generic register of the device.
33 * MANDATORY: return 0 -> no Error.
34 * @{
35 *
36 */
37
38 /**
39 * @brief Read generic device register
40 *
41 * @param ctx read / write interface definitions(ptr)
42 * @param reg register to read
43 * @param data pointer to buffer that store the data read(ptr)
44 * @param len number of consecutive register to read
45 * @retval interface status (MANDATORY: return 0 -> no Error)
46 *
47 */
iis2mdc_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)48 int32_t __weak iis2mdc_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
49 uint8_t *data,
50 uint16_t len)
51 {
52 int32_t ret;
53
54 if (ctx == NULL) return -1;
55
56 ret = ctx->read_reg(ctx->handle, reg, data, len);
57
58 return ret;
59 }
60
61 /**
62 * @brief Write generic device register
63 *
64 * @param ctx read / write interface definitions(ptr)
65 * @param reg register to write
66 * @param data pointer to data to write in register reg(ptr)
67 * @param len number of consecutive register to write
68 * @retval interface status (MANDATORY: return 0 -> no Error)
69 *
70 */
iis2mdc_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)71 int32_t __weak iis2mdc_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
72 uint8_t *data,
73 uint16_t len)
74 {
75 int32_t ret;
76
77 if (ctx == NULL) return -1;
78
79 ret = ctx->write_reg(ctx->handle, reg, data, len);
80
81 return ret;
82 }
83
84 /**
85 * @}
86 *
87 */
88
89 /**
90 * @defgroup IIS2MDC_Sensitivity
91 * @brief These functions convert raw-data into engineering units.
92 * @{
93 *
94 */
95
iis2mdc_from_lsb_to_mgauss(int16_t lsb)96 float_t iis2mdc_from_lsb_to_mgauss(int16_t lsb)
97 {
98 return ((float_t)lsb) * 1.5f;
99 }
100
iis2mdc_from_lsb_to_celsius(int16_t lsb)101 float_t iis2mdc_from_lsb_to_celsius(int16_t lsb)
102 {
103 return (((float_t)lsb / 8.0f) + 25.0f);
104 }
105
106 /**
107 * @}
108 *
109 */
110
111 /**
112 * @defgroup IIS2MDC_data_generation.
113 * @brief This section group all the functions concerning
114 * data generation.
115 * @{
116 *
117 */
118
119 /**
120 * @brief These registers comprise a 3 group of 16-bit number and represent
121 * hard-iron offset in order to compensate environmental effects.
122 * Data format is the same of output data raw: two's complement with
123 * 1LSb = 1.5mG.
124 * These values act on the magnetic output data value in order to
125 * delete the environmental offset.[set]
126 *
127 * @param ctx read / write interface definitions
128 * @param buff buffer that contains data to write
129 * @retval interface status (MANDATORY: return 0 -> no Error)
130 *
131 */
iis2mdc_mag_user_offset_set(const stmdev_ctx_t * ctx,int16_t * val)132 int32_t iis2mdc_mag_user_offset_set(const stmdev_ctx_t *ctx, int16_t *val)
133 {
134 uint8_t buff[6];
135 int32_t ret;
136
137 buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
138 buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
139 buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
140 buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
141 buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
142 buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
143 ret = iis2mdc_write_reg(ctx, IIS2MDC_OFFSET_X_REG_L, buff, 6);
144
145 return ret;
146 }
147
148 /**
149 * @brief These registers comprise a 3 group of 16-bit number and represent
150 * hard-iron offset in order to compensate environmental effects.
151 * Data format is the same of output data raw: two's complement with
152 * 1LSb = 1.5mG.
153 * These values act on the magnetic output data value in order to
154 * delete the environmental offset.[get]
155 *
156 * @param ctx read / write interface definitions
157 * @param buff buffer that stores data read
158 * @retval interface status (MANDATORY: return 0 -> no Error)
159 *
160 */
iis2mdc_mag_user_offset_get(const stmdev_ctx_t * ctx,int16_t * val)161 int32_t iis2mdc_mag_user_offset_get(const stmdev_ctx_t *ctx, int16_t *val)
162 {
163 uint8_t buff[6];
164 int32_t ret;
165
166 ret = iis2mdc_read_reg(ctx, IIS2MDC_OFFSET_X_REG_L, buff, 6);
167 val[0] = (int16_t)buff[1];
168 val[0] = (val[0] * 256) + (int16_t)buff[0];
169 val[1] = (int16_t)buff[3];
170 val[1] = (val[1] * 256) + (int16_t)buff[2];
171 val[2] = (int16_t)buff[5];
172 val[2] = (val[2] * 256) + (int16_t)buff[4];
173
174 return ret;
175 }
176
177 /**
178 * @brief Operating mode selection.[set]
179 *
180 * @param ctx read / write interface definitions
181 * @param val change the values of md in reg CFG_REG_A
182 * @retval interface status (MANDATORY: return 0 -> no Error)
183 *
184 */
iis2mdc_operating_mode_set(const stmdev_ctx_t * ctx,iis2mdc_md_t val)185 int32_t iis2mdc_operating_mode_set(const stmdev_ctx_t *ctx,
186 iis2mdc_md_t val)
187 {
188 iis2mdc_cfg_reg_a_t reg;
189 int32_t ret;
190
191 ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t *) ®, 1);
192
193 if (ret == 0)
194 {
195 reg.md = (uint8_t)val;
196 ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t *) ®, 1);
197 }
198
199 return ret;
200 }
201
202 /**
203 * @brief Operating mode selection.[get]
204 *
205 * @param ctx read / write interface definitions
206 * @param val Get the values of md in reg CFG_REG_A
207 * @retval interface status (MANDATORY: return 0 -> no Error)
208 *
209 */
iis2mdc_operating_mode_get(const stmdev_ctx_t * ctx,iis2mdc_md_t * val)210 int32_t iis2mdc_operating_mode_get(const stmdev_ctx_t *ctx,
211 iis2mdc_md_t *val)
212 {
213 iis2mdc_cfg_reg_a_t reg;
214 int32_t ret;
215
216 ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t *) ®, 1);
217
218 switch (reg.md)
219 {
220 case IIS2MDC_CONTINUOUS_MODE:
221 *val = IIS2MDC_CONTINUOUS_MODE;
222 break;
223
224 case IIS2MDC_SINGLE_TRIGGER:
225 *val = IIS2MDC_SINGLE_TRIGGER;
226 break;
227
228 case IIS2MDC_POWER_DOWN:
229 *val = IIS2MDC_POWER_DOWN;
230 break;
231
232 default:
233 *val = IIS2MDC_CONTINUOUS_MODE;
234 break;
235 }
236
237 return ret;
238 }
239
240 /**
241 * @brief Output data rate selection.[set]
242 *
243 * @param ctx read / write interface definitions
244 * @param val change the values of odr in reg CFG_REG_A
245 * @retval interface status (MANDATORY: return 0 -> no Error)
246 *
247 */
iis2mdc_data_rate_set(const stmdev_ctx_t * ctx,iis2mdc_odr_t val)248 int32_t iis2mdc_data_rate_set(const stmdev_ctx_t *ctx, iis2mdc_odr_t val)
249 {
250 iis2mdc_cfg_reg_a_t reg;
251 int32_t ret;
252
253 ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t *) ®, 1);
254
255 if (ret == 0)
256 {
257 reg.odr = (uint8_t)val;
258 ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t *) ®, 1);
259 }
260
261 return ret;
262 }
263
264 /**
265 * @brief Output data rate selection.[get]
266 *
267 * @param ctx read / write interface definitions
268 * @param val Get the values of odr in reg CFG_REG_A
269 * @retval interface status (MANDATORY: return 0 -> no Error)
270 *
271 */
iis2mdc_data_rate_get(const stmdev_ctx_t * ctx,iis2mdc_odr_t * val)272 int32_t iis2mdc_data_rate_get(const stmdev_ctx_t *ctx, iis2mdc_odr_t *val)
273 {
274 iis2mdc_cfg_reg_a_t reg;
275 int32_t ret;
276
277 ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t *) ®, 1);
278
279 switch (reg.odr)
280 {
281 case IIS2MDC_ODR_10Hz:
282 *val = IIS2MDC_ODR_10Hz;
283 break;
284
285 case IIS2MDC_ODR_20Hz:
286 *val = IIS2MDC_ODR_20Hz;
287 break;
288
289 case IIS2MDC_ODR_50Hz:
290 *val = IIS2MDC_ODR_50Hz;
291 break;
292
293 case IIS2MDC_ODR_100Hz:
294 *val = IIS2MDC_ODR_100Hz;
295 break;
296
297 default:
298 *val = IIS2MDC_ODR_10Hz;
299 break;
300 }
301
302 return ret;
303 }
304
305 /**
306 * @brief Enables high-resolution/low-power mode.[set]
307 *
308 * @param ctx read / write interface definitions
309 * @param val change the values of lp in reg CFG_REG_A
310 * @retval interface status (MANDATORY: return 0 -> no Error)
311 *
312 */
iis2mdc_power_mode_set(const stmdev_ctx_t * ctx,iis2mdc_lp_t val)313 int32_t iis2mdc_power_mode_set(const stmdev_ctx_t *ctx, iis2mdc_lp_t val)
314 {
315 iis2mdc_cfg_reg_a_t reg;
316 int32_t ret;
317
318 ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t *) ®, 1);
319
320 if (ret == 0)
321 {
322 reg.lp = (uint8_t)val;
323 ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t *) ®, 1);
324 }
325
326 return ret;
327 }
328
329 /**
330 * @brief Enables high-resolution/low-power mode.[get]
331 *
332 * @param ctx read / write interface definitions
333 * @param val Get the values of lp in reg CFG_REG_A
334 * @retval interface status (MANDATORY: return 0 -> no Error)
335 *
336 */
iis2mdc_power_mode_get(const stmdev_ctx_t * ctx,iis2mdc_lp_t * val)337 int32_t iis2mdc_power_mode_get(const stmdev_ctx_t *ctx, iis2mdc_lp_t *val)
338 {
339 iis2mdc_cfg_reg_a_t reg;
340 int32_t ret;
341
342 ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t *) ®, 1);
343
344 switch (reg.lp)
345 {
346 case IIS2MDC_HIGH_RESOLUTION:
347 *val = IIS2MDC_HIGH_RESOLUTION;
348 break;
349
350 case IIS2MDC_LOW_POWER:
351 *val = IIS2MDC_LOW_POWER;
352 break;
353
354 default:
355 *val = IIS2MDC_HIGH_RESOLUTION;
356 break;
357 }
358
359 return ret;
360 }
361
362 /**
363 * @brief Enables the magnetometer temperature compensation.[set]
364 *
365 * @param ctx read / write interface definitions
366 * @param val change the values of comp_temp_en in reg CFG_REG_A
367 * @retval interface status (MANDATORY: return 0 -> no Error)
368 *
369 */
iis2mdc_offset_temp_comp_set(const stmdev_ctx_t * ctx,uint8_t val)370 int32_t iis2mdc_offset_temp_comp_set(const stmdev_ctx_t *ctx, uint8_t val)
371 {
372 iis2mdc_cfg_reg_a_t reg;
373 int32_t ret;
374
375 ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t *) ®, 1);
376
377 if (ret == 0)
378 {
379 reg.comp_temp_en = val;
380 ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t *) ®, 1);
381 }
382
383 return ret;
384 }
385
386 /**
387 * @brief Enables the magnetometer temperature compensation.[get]
388 *
389 * @param ctx read / write interface definitions
390 * @param val change the values of comp_temp_en in reg CFG_REG_A
391 * @retval interface status (MANDATORY: return 0 -> no Error)
392 *
393 */
iis2mdc_offset_temp_comp_get(const stmdev_ctx_t * ctx,uint8_t * val)394 int32_t iis2mdc_offset_temp_comp_get(const stmdev_ctx_t *ctx, uint8_t *val)
395 {
396 iis2mdc_cfg_reg_a_t reg;
397 int32_t ret;
398
399 ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t *) ®, 1);
400 *val = reg.comp_temp_en;
401
402 return ret;
403 }
404
405 /**
406 * @brief Low-pass bandwidth selection.[set]
407 *
408 * @param ctx read / write interface definitions
409 * @param val change the values of lpf in reg CFG_REG_B
410 * @retval interface status (MANDATORY: return 0 -> no Error)
411 *
412 */
iis2mdc_low_pass_bandwidth_set(const stmdev_ctx_t * ctx,iis2mdc_lpf_t val)413 int32_t iis2mdc_low_pass_bandwidth_set(const stmdev_ctx_t *ctx,
414 iis2mdc_lpf_t val)
415 {
416 iis2mdc_cfg_reg_b_t reg;
417 int32_t ret;
418
419 ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_B, (uint8_t *) ®, 1);
420
421 if (ret == 0)
422 {
423 reg.lpf = (uint8_t)val;
424 ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_B, (uint8_t *) ®, 1);
425 }
426
427 return ret;
428 }
429
430 /**
431 * @brief Low-pass bandwidth selection.[get]
432 *
433 * @param ctx read / write interface definitions
434 * @param val Get the values of lpf in reg CFG_REG_B
435 * @retval interface status (MANDATORY: return 0 -> no Error)
436 *
437 */
iis2mdc_low_pass_bandwidth_get(const stmdev_ctx_t * ctx,iis2mdc_lpf_t * val)438 int32_t iis2mdc_low_pass_bandwidth_get(const stmdev_ctx_t *ctx,
439 iis2mdc_lpf_t *val)
440 {
441 iis2mdc_cfg_reg_b_t reg;
442 int32_t ret;
443
444 ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_B, (uint8_t *) ®, 1);
445
446 switch (reg.lpf)
447 {
448 case IIS2MDC_ODR_DIV_2:
449 *val = IIS2MDC_ODR_DIV_2;
450 break;
451
452 case IIS2MDC_ODR_DIV_4:
453 *val = IIS2MDC_ODR_DIV_4;
454 break;
455
456 default:
457 *val = IIS2MDC_ODR_DIV_2;
458 break;
459 }
460
461 return ret;
462 }
463
464 /**
465 * @brief Reset puse mode.[set]
466 *
467 * @param ctx read / write interface definitions
468 * @param val change the values of set_rst in
469 * reg CFG_REG_B
470 * @retval interface status (MANDATORY: return 0 -> no Error)
471 *
472 */
iis2mdc_set_rst_mode_set(const stmdev_ctx_t * ctx,iis2mdc_set_rst_t val)473 int32_t iis2mdc_set_rst_mode_set(const stmdev_ctx_t *ctx,
474 iis2mdc_set_rst_t val)
475 {
476 iis2mdc_cfg_reg_b_t reg;
477 int32_t ret;
478
479 ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_B, (uint8_t *) ®, 1);
480
481 if (ret == 0)
482 {
483 reg.set_rst = (uint8_t)val;
484 ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_B, (uint8_t *) ®, 1);
485 }
486
487 return ret;
488 }
489
490 /**
491 * @brief Reset puse mode.[get]
492 *
493 * @param ctx read / write interface definitions
494 * @param val Get the values of set_rst in reg CFG_REG_B
495 * @retval interface status (MANDATORY: return 0 -> no Error)
496 *
497 */
iis2mdc_set_rst_mode_get(const stmdev_ctx_t * ctx,iis2mdc_set_rst_t * val)498 int32_t iis2mdc_set_rst_mode_get(const stmdev_ctx_t *ctx,
499 iis2mdc_set_rst_t *val)
500 {
501 iis2mdc_cfg_reg_b_t reg;
502 int32_t ret;
503
504 ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_B, (uint8_t *) ®, 1);
505
506 switch (reg.set_rst)
507 {
508 case IIS2MDC_SET_SENS_ODR_DIV_63:
509 *val = IIS2MDC_SET_SENS_ODR_DIV_63;
510 break;
511
512 case IIS2MDC_SENS_OFF_CANC_EVERY_ODR:
513 *val = IIS2MDC_SENS_OFF_CANC_EVERY_ODR;
514 break;
515
516 case IIS2MDC_SET_SENS_ONLY_AT_POWER_ON:
517 *val = IIS2MDC_SET_SENS_ONLY_AT_POWER_ON;
518 break;
519
520 default:
521 *val = IIS2MDC_SET_SENS_ODR_DIV_63;
522 break;
523 }
524
525 return ret;
526 }
527
528 /**
529 * @brief Enables offset cancellation in single measurement mode.
530 * The OFF_CANC bit must be set to 1 when enabling offset
531 * cancellation in single measurement mode this means a
532 * call function "set_rst_mode(SENS_OFF_CANC_EVERY_ODR)"
533 * is need.[set]
534 *
535 * @param ctx read / write interface definitions
536 * @param val change the values of off_canc_one_shot in
537 * reg CFG_REG_B
538 * @retval interface status (MANDATORY: return 0 -> no Error)
539 *
540 */
iis2mdc_set_rst_sensor_single_set(const stmdev_ctx_t * ctx,uint8_t val)541 int32_t iis2mdc_set_rst_sensor_single_set(const stmdev_ctx_t *ctx,
542 uint8_t val)
543 {
544 iis2mdc_cfg_reg_b_t reg;
545 int32_t ret;
546
547 ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_B, (uint8_t *) ®, 1);
548
549 if (ret == 0)
550 {
551 reg.off_canc_one_shot = val;
552 ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_B, (uint8_t *) ®, 1);
553 }
554
555 return ret;
556 }
557
558 /**
559 * @brief Enables offset cancellation in single measurement mode.
560 * The OFF_CANC bit must be set to 1 when enabling offset
561 * cancellation in single measurement mode this means a
562 * call function "set_rst_mode(SENS_OFF_CANC_EVERY_ODR)"
563 * is need.[get]
564 *
565 * @param ctx read / write interface definitions
566 * @param val change the values of off_canc_one_shot in reg CFG_REG_B
567 * @retval interface status (MANDATORY: return 0 -> no Error)
568 *
569 */
iis2mdc_set_rst_sensor_single_get(const stmdev_ctx_t * ctx,uint8_t * val)570 int32_t iis2mdc_set_rst_sensor_single_get(const stmdev_ctx_t *ctx,
571 uint8_t *val)
572 {
573 iis2mdc_cfg_reg_b_t reg;
574 int32_t ret;
575
576 ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_B, (uint8_t *) ®, 1);
577 *val = reg.off_canc_one_shot;
578
579 return ret;
580 }
581
582 /**
583 * @brief Block data update.[set]
584 *
585 * @param ctx read / write interface definitions
586 * @param val change the values of bdu in reg CFG_REG_C
587 * @retval interface status (MANDATORY: return 0 -> no Error)
588 *
589 */
iis2mdc_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)590 int32_t iis2mdc_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val)
591 {
592 iis2mdc_cfg_reg_c_t reg;
593 int32_t ret;
594
595 ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t *) ®, 1);
596
597 if (ret == 0)
598 {
599 reg.bdu = val;
600 ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t *) ®, 1);
601 }
602
603 return ret;
604 }
605
606 /**
607 * @brief Block data update.[get]
608 *
609 * @param ctx read / write interface definitions
610 * @param val change the values of bdu in reg CFG_REG_C
611 * @retval interface status (MANDATORY: return 0 -> no Error)
612 *
613 */
iis2mdc_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)614 int32_t iis2mdc_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val)
615 {
616 iis2mdc_cfg_reg_c_t reg;
617 int32_t ret;
618
619 ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t *) ®, 1);
620 *val = reg.bdu;
621
622 return ret;
623 }
624
625 /**
626 * @brief Magnetic set of data available.[get]
627 *
628 * @param ctx read / write interface definitions
629 * @param val change the values of zyxda in reg STATUS_REG
630 * @retval interface status (MANDATORY: return 0 -> no Error)
631 *
632 */
iis2mdc_mag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)633 int32_t iis2mdc_mag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val)
634 {
635 iis2mdc_status_reg_t reg;
636 int32_t ret;
637
638 ret = iis2mdc_read_reg(ctx, IIS2MDC_STATUS_REG, (uint8_t *) ®, 1);
639 *val = reg.zyxda;
640
641 return ret;
642 }
643
644 /**
645 * @brief Magnetic set of data overrun.[get]
646 *
647 * @param ctx read / write interface definitions
648 * @param val change the values of zyxor in reg STATUS_REG
649 * @retval interface status (MANDATORY: return 0 -> no Error)
650 *
651 */
iis2mdc_mag_data_ovr_get(const stmdev_ctx_t * ctx,uint8_t * val)652 int32_t iis2mdc_mag_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val)
653 {
654 iis2mdc_status_reg_t reg;
655 int32_t ret;
656
657 ret = iis2mdc_read_reg(ctx, IIS2MDC_STATUS_REG, (uint8_t *) ®, 1);
658 *val = reg.zyxor;
659
660 return ret;
661 }
662
663 /**
664 * @brief Magnetic output value.[get]
665 *
666 * @param ctx read / write interface definitions
667 * @param buff buffer that stores data read
668 * @retval interface status (MANDATORY: return 0 -> no Error)
669 *
670 */
iis2mdc_magnetic_raw_get(const stmdev_ctx_t * ctx,int16_t * val)671 int32_t iis2mdc_magnetic_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
672 {
673 uint8_t buff[6];
674 int32_t ret;
675
676 ret = iis2mdc_read_reg(ctx, IIS2MDC_OUTX_L_REG, buff, 6);
677 val[0] = (int16_t)buff[1];
678 val[0] = (val[0] * 256) + (int16_t)buff[0];
679 val[1] = (int16_t)buff[3];
680 val[1] = (val[1] * 256) + (int16_t)buff[2];
681 val[2] = (int16_t)buff[5];
682 val[2] = (val[2] * 256) + (int16_t)buff[4];
683
684 return ret;
685 }
686
687 /**
688 * @brief Temperature output value.[get]
689 *
690 * @param ctx read / write interface definitions
691 * @param buff buffer that stores data read
692 * @retval interface status (MANDATORY: return 0 -> no Error)
693 *
694 */
iis2mdc_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * val)695 int32_t iis2mdc_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
696 {
697 uint8_t buff[2];
698 int32_t ret;
699
700 ret = iis2mdc_read_reg(ctx, IIS2MDC_TEMP_OUT_L_REG, buff, 2);
701 *val = (int16_t)buff[1];
702 *val = (*val * 256) + (int16_t)buff[0];
703
704 return ret;
705 }
706
707 /**
708 * @}
709 *
710 */
711
712 /**
713 * @defgroup IIS2MDC_common
714 * @brief This section group common useful functions
715 * @{
716 *
717 */
718
719 /**
720 * @brief Device Who am I.[get]
721 *
722 * @param ctx read / write interface definitions
723 * @param buff buffer that stores data read
724 * @retval interface status (MANDATORY: return 0 -> no Error)
725 *
726 */
iis2mdc_device_id_get(const stmdev_ctx_t * ctx,uint8_t * buff)727 int32_t iis2mdc_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
728 {
729 int32_t ret;
730
731 ret = iis2mdc_read_reg(ctx, IIS2MDC_WHO_AM_I, buff, 1);
732
733 return ret;
734 }
735
736 /**
737 * @brief Software reset. Restore the default values in user
738 * registers.[set]
739 *
740 * @param ctx read / write interface definitions
741 * @param val change the values of soft_rst in reg CFG_REG_A
742 * @retval interface status (MANDATORY: return 0 -> no Error)
743 *
744 */
iis2mdc_reset_set(const stmdev_ctx_t * ctx,uint8_t val)745 int32_t iis2mdc_reset_set(const stmdev_ctx_t *ctx, uint8_t val)
746 {
747 iis2mdc_cfg_reg_a_t reg;
748 int32_t ret;
749
750 ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t *) ®, 1);
751
752 if (ret == 0)
753 {
754 reg.soft_rst = val;
755 ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t *) ®, 1);
756 }
757
758 return ret;
759 }
760
761 /**
762 * @brief Software reset. Restore the default values in user registers.[get]
763 *
764 * @param ctx read / write interface definitions
765 * @param val change the values of soft_rst in reg CFG_REG_A
766 * @retval interface status (MANDATORY: return 0 -> no Error)
767 *
768 */
iis2mdc_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)769 int32_t iis2mdc_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
770 {
771 iis2mdc_cfg_reg_a_t reg;
772 int32_t ret;
773
774 ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t *) ®, 1);
775 *val = reg.soft_rst;
776
777 return ret;
778 }
779
780 /**
781 * @brief Reboot memory content. Reload the calibration parameters.[set]
782 *
783 * @param ctx read / write interface definitions
784 * @param val change the values of reboot in reg CFG_REG_A
785 * @retval interface status (MANDATORY: return 0 -> no Error)
786 *
787 */
iis2mdc_boot_set(const stmdev_ctx_t * ctx,uint8_t val)788 int32_t iis2mdc_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
789 {
790 iis2mdc_cfg_reg_a_t reg;
791 int32_t ret;
792
793 ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t *) ®, 1);
794
795 if (ret == 0)
796 {
797 reg.reboot = val;
798 ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t *) ®, 1);
799 }
800
801 return ret;
802 }
803
804 /**
805 * @brief Reboot memory content. Reload the calibration parameters.[get]
806 *
807 * @param ctx read / write interface definitions
808 * @param val change the values of reboot in reg CFG_REG_A
809 * @retval interface status (MANDATORY: return 0 -> no Error)
810 *
811 */
iis2mdc_boot_get(const stmdev_ctx_t * ctx,uint8_t * val)812 int32_t iis2mdc_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
813 {
814 iis2mdc_cfg_reg_a_t reg;
815 int32_t ret;
816
817 ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t *) ®, 1);
818 *val = reg.reboot;
819
820 return ret;
821 }
822
823 /**
824 * @brief Selftest.[set]
825 *
826 * @param ctx read / write interface definitions
827 * @param val change the values of self_test in reg CFG_REG_C
828 * @retval interface status (MANDATORY: return 0 -> no Error)
829 *
830 */
iis2mdc_self_test_set(const stmdev_ctx_t * ctx,uint8_t val)831 int32_t iis2mdc_self_test_set(const stmdev_ctx_t *ctx, uint8_t val)
832 {
833 iis2mdc_cfg_reg_c_t reg;
834 int32_t ret;
835
836 ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t *) ®, 1);
837
838 if (ret == 0)
839 {
840 reg.self_test = val;
841 ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t *) ®, 1);
842 }
843
844 return ret;
845 }
846
847 /**
848 * @brief Selftest.[get]
849 *
850 * @param ctx read / write interface definitions
851 * @param val change the values of self_test in reg CFG_REG_C
852 * @retval interface status (MANDATORY: return 0 -> no Error)
853 *
854 */
iis2mdc_self_test_get(const stmdev_ctx_t * ctx,uint8_t * val)855 int32_t iis2mdc_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val)
856 {
857 iis2mdc_cfg_reg_c_t reg;
858 int32_t ret;
859
860 ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t *) ®, 1);
861 *val = reg.self_test;
862
863 return ret;
864 }
865
866 /**
867 * @brief Big/Little Endian data selection.[set]
868 *
869 * @param ctx read / write interface definitions
870 * @param val change the values of ble in reg CFG_REG_C
871 * @retval interface status (MANDATORY: return 0 -> no Error)
872 *
873 */
iis2mdc_data_format_set(const stmdev_ctx_t * ctx,iis2mdc_ble_t val)874 int32_t iis2mdc_data_format_set(const stmdev_ctx_t *ctx, iis2mdc_ble_t val)
875 {
876 iis2mdc_cfg_reg_c_t reg;
877 int32_t ret;
878
879 ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t *) ®, 1);
880
881 if (ret == 0)
882 {
883 reg.ble = (uint8_t)val;
884 ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t *) ®, 1);
885 }
886
887 return ret;
888 }
889
890 /**
891 * @brief Big/Little Endian data selection.[get]
892 *
893 * @param ctx read / write interface definitions
894 * @param val Get the values of ble in reg CFG_REG_C
895 * @retval interface status (MANDATORY: return 0 -> no Error)
896 *
897 */
iis2mdc_data_format_get(const stmdev_ctx_t * ctx,iis2mdc_ble_t * val)898 int32_t iis2mdc_data_format_get(const stmdev_ctx_t *ctx, iis2mdc_ble_t *val)
899 {
900 iis2mdc_cfg_reg_c_t reg;
901 int32_t ret;
902
903 ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t *) ®, 1);
904
905 switch (reg.ble)
906 {
907 case IIS2MDC_LSB_AT_LOW_ADD:
908 *val = IIS2MDC_LSB_AT_LOW_ADD;
909 break;
910
911 case IIS2MDC_MSB_AT_LOW_ADD:
912 *val = IIS2MDC_MSB_AT_LOW_ADD;
913 break;
914
915 default:
916 *val = IIS2MDC_LSB_AT_LOW_ADD;
917 break;
918 }
919
920 return ret;
921 }
922
923 /**
924 * @brief Info about device status.[get]
925 *
926 * @param ctx read / write interface definitions
927 * @param val registers STATUS_REG
928 * @retval interface status (MANDATORY: return 0 -> no Error)
929 *
930 */
iis2mdc_status_get(const stmdev_ctx_t * ctx,iis2mdc_status_reg_t * val)931 int32_t iis2mdc_status_get(const stmdev_ctx_t *ctx,
932 iis2mdc_status_reg_t *val)
933 {
934 int32_t ret;
935
936 ret = iis2mdc_read_reg(ctx, IIS2MDC_STATUS_REG, (uint8_t *) val, 1);
937
938 return ret;
939 }
940
941 /**
942 * @}
943 *
944 */
945
946 /**
947 * @defgroup IIS2MDC_interrupts
948 * @brief This section group all the functions that manage
949 * interrupts.
950 * @{
951 *
952 */
953
954 /**
955 * @brief The interrupt block recognition checks data after/before the
956 * hard-iron correction to discover the interrupt.[set]
957 *
958 * @param ctx read / write interface definitions
959 * @param val change the values of int_on_dataoff in
960 * reg CFG_REG_B
961 * @retval interface status (MANDATORY: return 0 -> no Error)
962 *
963 */
iis2mdc_offset_int_conf_set(const stmdev_ctx_t * ctx,iis2mdc_int_on_dataoff_t val)964 int32_t iis2mdc_offset_int_conf_set(const stmdev_ctx_t *ctx,
965 iis2mdc_int_on_dataoff_t val)
966 {
967 iis2mdc_cfg_reg_b_t reg;
968 int32_t ret;
969
970 ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_B, (uint8_t *) ®, 1);
971
972 if (ret == 0)
973 {
974 reg.int_on_dataoff = (uint8_t)val;
975 ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_B, (uint8_t *) ®, 1);
976 }
977
978 return ret;
979 }
980
981 /**
982 * @brief The interrupt block recognition checks data after/before the
983 * hard-iron correction to discover the interrupt.[get]
984 *
985 * @param ctx read / write interface definitions
986 * @param val Get the values of int_on_dataoff in
987 * reg CFG_REG_B
988 * @retval interface status (MANDATORY: return 0 -> no Error)
989 *
990 */
iis2mdc_offset_int_conf_get(const stmdev_ctx_t * ctx,iis2mdc_int_on_dataoff_t * val)991 int32_t iis2mdc_offset_int_conf_get(const stmdev_ctx_t *ctx,
992 iis2mdc_int_on_dataoff_t *val)
993 {
994 iis2mdc_cfg_reg_b_t reg;
995 int32_t ret;
996
997 ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_B, (uint8_t *) ®, 1);
998
999 switch (reg.int_on_dataoff)
1000 {
1001 case IIS2MDC_CHECK_BEFORE:
1002 *val = IIS2MDC_CHECK_BEFORE;
1003 break;
1004
1005 case IIS2MDC_CHECK_AFTER:
1006 *val = IIS2MDC_CHECK_AFTER;
1007 break;
1008
1009 default:
1010 *val = IIS2MDC_CHECK_BEFORE;
1011 break;
1012 }
1013
1014 return ret;
1015 }
1016
1017 /**
1018 * @brief Data-ready signal on INT_DRDY pin.[set]
1019 *
1020 * @param ctx read / write interface definitions
1021 * @param val change the values of drdy_on_pin in reg CFG_REG_C
1022 * @retval interface status (MANDATORY: return 0 -> no Error)
1023 *
1024 */
iis2mdc_drdy_on_pin_set(const stmdev_ctx_t * ctx,uint8_t val)1025 int32_t iis2mdc_drdy_on_pin_set(const stmdev_ctx_t *ctx, uint8_t val)
1026 {
1027 iis2mdc_cfg_reg_c_t reg;
1028 int32_t ret;
1029
1030 ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t *) ®, 1);
1031
1032 if (ret == 0)
1033 {
1034 reg.drdy_on_pin = val;
1035 ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t *) ®, 1);
1036 }
1037
1038 return ret;
1039 }
1040
1041 /**
1042 * @brief Data-ready signal on INT_DRDY pin.[get]
1043 *
1044 * @param ctx read / write interface definitions
1045 * @param val change the values of drdy_on_pin in reg CFG_REG_C
1046 * @retval interface status (MANDATORY: return 0 -> no Error)
1047 *
1048 */
iis2mdc_drdy_on_pin_get(const stmdev_ctx_t * ctx,uint8_t * val)1049 int32_t iis2mdc_drdy_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val)
1050 {
1051 iis2mdc_cfg_reg_c_t reg;
1052 int32_t ret;
1053
1054 ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t *) ®, 1);
1055 *val = reg.drdy_on_pin;
1056
1057 return ret;
1058 }
1059
1060 /**
1061 * @brief Interrupt signal on INT_DRDY pin.[set]
1062 *
1063 * @param ctx read / write interface definitions
1064 * @param val change the values of int_on_pin in reg CFG_REG_C
1065 * @retval interface status (MANDATORY: return 0 -> no Error)
1066 *
1067 */
iis2mdc_int_on_pin_set(const stmdev_ctx_t * ctx,uint8_t val)1068 int32_t iis2mdc_int_on_pin_set(const stmdev_ctx_t *ctx, uint8_t val)
1069 {
1070 iis2mdc_cfg_reg_c_t reg;
1071 int32_t ret;
1072
1073 ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t *) ®, 1);
1074
1075 if (ret == 0)
1076 {
1077 reg.int_on_pin = val;
1078 ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t *) ®, 1);
1079 }
1080
1081 return ret;
1082 }
1083
1084 /**
1085 * @brief Interrupt signal on INT_DRDY pin.[get]
1086 *
1087 * @param ctx read / write interface definitions
1088 * @param val change the values of int_on_pin in reg CFG_REG_C
1089 * @retval interface status (MANDATORY: return 0 -> no Error)
1090 *
1091 */
iis2mdc_int_on_pin_get(const stmdev_ctx_t * ctx,uint8_t * val)1092 int32_t iis2mdc_int_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val)
1093 {
1094 iis2mdc_cfg_reg_c_t reg;
1095 int32_t ret;
1096
1097 ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t *) ®, 1);
1098 *val = reg.int_on_pin;
1099
1100 return ret;
1101 }
1102
1103 /**
1104 * @brief Interrupt generator configuration register.[set]
1105 *
1106 * @param ctx read / write interface definitions
1107 * @param val registers INT_CRTL_REG
1108 * @retval interface status (MANDATORY: return 0 -> no Error)
1109 *
1110 */
iis2mdc_int_gen_conf_set(const stmdev_ctx_t * ctx,iis2mdc_int_crtl_reg_t * val)1111 int32_t iis2mdc_int_gen_conf_set(const stmdev_ctx_t *ctx,
1112 iis2mdc_int_crtl_reg_t *val)
1113 {
1114 int32_t ret;
1115
1116 ret = iis2mdc_write_reg(ctx, IIS2MDC_INT_CRTL_REG, (uint8_t *) val, 1);
1117
1118 return ret;
1119 }
1120
1121 /**
1122 * @brief Interrupt generator configuration register.[get]
1123 *
1124 * @param ctx read / write interface definitions
1125 * @param val registers INT_CRTL_REG
1126 * @retval interface status (MANDATORY: return 0 -> no Error)
1127 *
1128 */
iis2mdc_int_gen_conf_get(const stmdev_ctx_t * ctx,iis2mdc_int_crtl_reg_t * val)1129 int32_t iis2mdc_int_gen_conf_get(const stmdev_ctx_t *ctx,
1130 iis2mdc_int_crtl_reg_t *val)
1131 {
1132 int32_t ret;
1133
1134 ret = iis2mdc_read_reg(ctx, IIS2MDC_INT_CRTL_REG, (uint8_t *) val, 1);
1135
1136 return ret;
1137 }
1138
1139 /**
1140 * @brief Interrupt generator source register.[get]
1141 *
1142 * @param ctx read / write interface definitions
1143 * @param val registers INT_SOURCE_REG
1144 * @retval interface status (MANDATORY: return 0 -> no Error)
1145 *
1146 */
iis2mdc_int_gen_source_get(const stmdev_ctx_t * ctx,iis2mdc_int_source_reg_t * val)1147 int32_t iis2mdc_int_gen_source_get(const stmdev_ctx_t *ctx,
1148 iis2mdc_int_source_reg_t *val)
1149 {
1150 int32_t ret;
1151
1152 ret = iis2mdc_read_reg(ctx, IIS2MDC_INT_SOURCE_REG, (uint8_t *) val, 1);
1153
1154 return ret;
1155 }
1156
1157 /**
1158 * @brief User-defined threshold value for xl interrupt event on generator.
1159 * Data format is the same of output data raw:
1160 * two's complement with 1LSb = 1.5mG.[set]
1161 *
1162 * @param ctx read / write interface definitions
1163 * @param buff buffer that contains data to write
1164 * @retval interface status (MANDATORY: return 0 -> no Error)
1165 *
1166 */
iis2mdc_int_gen_threshold_set(const stmdev_ctx_t * ctx,int16_t val)1167 int32_t iis2mdc_int_gen_threshold_set(const stmdev_ctx_t *ctx, int16_t val)
1168 {
1169 uint8_t buff[2];
1170 int32_t ret;
1171
1172 buff[1] = (uint8_t)((uint16_t)val / 256U);
1173 buff[0] = (uint8_t)((uint16_t)val - (buff[1] * 256U));
1174 ret = iis2mdc_write_reg(ctx, IIS2MDC_INT_THS_L_REG, buff, 2);
1175
1176 return ret;
1177 }
1178
1179 /**
1180 * @brief User-defined threshold value for xl interrupt event on generator.
1181 * Data format is the same of output data raw:
1182 * two's complement with 1LSb = 1.5mG.[get]
1183 *
1184 * @param ctx read / write interface definitions
1185 * @param buff buffer that stores data read
1186 * @retval interface status (MANDATORY: return 0 -> no Error)
1187 *
1188 */
iis2mdc_int_gen_threshold_get(const stmdev_ctx_t * ctx,int16_t * val)1189 int32_t iis2mdc_int_gen_threshold_get(const stmdev_ctx_t *ctx, int16_t *val)
1190 {
1191 uint8_t buff[2];
1192 int32_t ret;
1193
1194 ret = iis2mdc_read_reg(ctx, IIS2MDC_INT_THS_L_REG, buff, 2);
1195 *val = (int16_t)buff[1];
1196 *val = (*val * 256) + (int16_t)buff[0];
1197
1198 return ret;
1199 }
1200
1201 /**
1202 * @}
1203 *
1204 */
1205
1206 /**
1207 * @defgroup IIS2MDC_serial_interface
1208 * @brief This section group all the functions concerning serial
1209 * interface management
1210 * @{
1211 *
1212 */
1213
1214 /**
1215 * @brief Enable/Disable I2C interface.[set]
1216 *
1217 * @param ctx read / write interface definitions
1218 * @param val change the values of i2c_dis in reg CFG_REG_C
1219 * @retval interface status (MANDATORY: return 0 -> no Error)
1220 *
1221 */
iis2mdc_i2c_interface_set(const stmdev_ctx_t * ctx,iis2mdc_i2c_dis_t val)1222 int32_t iis2mdc_i2c_interface_set(const stmdev_ctx_t *ctx,
1223 iis2mdc_i2c_dis_t val)
1224 {
1225 iis2mdc_cfg_reg_c_t reg;
1226 int32_t ret;
1227
1228 ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t *) ®, 1);
1229
1230 if (ret == 0)
1231 {
1232 reg.i2c_dis = (uint8_t)val;
1233 ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t *) ®, 1);
1234 }
1235
1236 return ret;
1237 }
1238
1239 /**
1240 * @brief Enable/Disable I2C interface.[get]
1241 *
1242 * @param ctx read / write interface definitions
1243 * @param val Get the values of i2c_dis in reg CFG_REG_C
1244 * @retval interface status (MANDATORY: return 0 -> no Error)
1245 *
1246 */
iis2mdc_i2c_interface_get(const stmdev_ctx_t * ctx,iis2mdc_i2c_dis_t * val)1247 int32_t iis2mdc_i2c_interface_get(const stmdev_ctx_t *ctx,
1248 iis2mdc_i2c_dis_t *val)
1249 {
1250 iis2mdc_cfg_reg_c_t reg;
1251 int32_t ret;
1252
1253 ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t *) ®, 1);
1254
1255 switch (reg.i2c_dis)
1256 {
1257 case IIS2MDC_I2C_ENABLE:
1258 *val = IIS2MDC_I2C_ENABLE;
1259 break;
1260
1261 case IIS2MDC_I2C_DISABLE:
1262 *val = IIS2MDC_I2C_DISABLE;
1263 break;
1264
1265 default:
1266 *val = IIS2MDC_I2C_ENABLE;
1267 break;
1268 }
1269
1270 return ret;
1271 }
1272
1273 /**
1274 * @}
1275 *
1276 */
1277
1278 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1279
