1 /**
2 ******************************************************************************
3 * @file iis2dlpc_reg.c
4 * @author Sensors Software Solution Team
5 * @brief IIS2DLPC driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "iis2dlpc_reg.h"
21
22 /**
23 * @defgroup IIS2DLPC
24 * @brief This file provides a set of functions needed to drive the
25 * iis2dlpc enanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup IIS2DLPC_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
iis2dlpc_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak iis2dlpc_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 if (ctx == NULL) return -1;
56
57 ret = ctx->read_reg(ctx->handle, reg, data, len);
58
59 return ret;
60 }
61
62 /**
63 * @brief Write generic device register
64 *
65 * @param ctx read / write interface definitions(ptr)
66 * @param reg register to write
67 * @param data pointer to data to write in register reg(ptr)
68 * @param len number of consecutive register to write
69 * @retval interface status (MANDATORY: return 0 -> no Error)
70 *
71 */
iis2dlpc_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)72 int32_t __weak iis2dlpc_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
73 uint8_t *data,
74 uint16_t len)
75 {
76 int32_t ret;
77
78 if (ctx == NULL) return -1;
79
80 ret = ctx->write_reg(ctx->handle, reg, data, len);
81
82 return ret;
83 }
84
85 /**
86 * @}
87 *
88 */
89
90 /**
91 * @defgroup IIS2DLPC_Sensitivity
92 * @brief These functions convert raw-data into engineering units.
93 * @{
94 *
95 */
96
iis2dlpc_from_fs2_to_mg(int16_t lsb)97 float_t iis2dlpc_from_fs2_to_mg(int16_t lsb)
98 {
99 return ((float_t)lsb) * 0.061f;
100 }
101
iis2dlpc_from_fs4_to_mg(int16_t lsb)102 float_t iis2dlpc_from_fs4_to_mg(int16_t lsb)
103 {
104 return ((float_t)lsb) * 0.122f;
105 }
106
iis2dlpc_from_fs8_to_mg(int16_t lsb)107 float_t iis2dlpc_from_fs8_to_mg(int16_t lsb)
108 {
109 return ((float_t)lsb) * 0.244f;
110 }
111
iis2dlpc_from_fs16_to_mg(int16_t lsb)112 float_t iis2dlpc_from_fs16_to_mg(int16_t lsb)
113 {
114 return ((float_t)lsb) * 0.488f;
115 }
116
iis2dlpc_from_fs2_lp1_to_mg(int16_t lsb)117 float_t iis2dlpc_from_fs2_lp1_to_mg(int16_t lsb)
118 {
119 return ((float_t)lsb) * 0.061f;
120 }
121
iis2dlpc_from_fs4_lp1_to_mg(int16_t lsb)122 float_t iis2dlpc_from_fs4_lp1_to_mg(int16_t lsb)
123 {
124 return ((float_t)lsb) * 0.122f;
125 }
126
iis2dlpc_from_fs8_lp1_to_mg(int16_t lsb)127 float_t iis2dlpc_from_fs8_lp1_to_mg(int16_t lsb)
128 {
129 return ((float_t)lsb) * 0.244f;
130 }
131
iis2dlpc_from_fs16_lp1_to_mg(int16_t lsb)132 float_t iis2dlpc_from_fs16_lp1_to_mg(int16_t lsb)
133 {
134 return ((float_t)lsb) * 0.488f;
135 }
136
iis2dlpc_from_lsb_to_celsius(int16_t lsb)137 float_t iis2dlpc_from_lsb_to_celsius(int16_t lsb)
138 {
139 return (((float_t)lsb / 256.0f) + 25.0f);
140 }
141
142 /**
143 * @}
144 *
145 */
146
147 /**
148 * @defgroup IIS2DLPC_Data_Generation
149 * @brief This section groups all the functions concerning
150 * data generation
151 * @{
152 *
153 */
154
155 /**
156 * @brief Select accelerometer operating modes.[set]
157 *
158 * @param ctx read / write interface definitions
159 * @param val change the values of mode / lp_mode in reg CTRL1
160 * and low_noise in reg CTRL6
161 * @retval interface status (MANDATORY: return 0 -> no Error)
162 *
163 */
iis2dlpc_power_mode_set(const stmdev_ctx_t * ctx,iis2dlpc_mode_t val)164 int32_t iis2dlpc_power_mode_set(const stmdev_ctx_t *ctx,
165 iis2dlpc_mode_t val)
166 {
167 iis2dlpc_ctrl1_t ctrl1;
168 iis2dlpc_ctrl6_t ctrl6;
169 int32_t ret;
170
171 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL1, (uint8_t *) &ctrl1, 1);
172
173 if (ret == 0)
174 {
175 ctrl1.mode = ((uint8_t) val & 0x0CU) >> 2;
176 ctrl1.lp_mode = (uint8_t) val & 0x03U ;
177 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL1, (uint8_t *) &ctrl1, 1);
178 }
179
180 if (ret == 0)
181 {
182 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6, (uint8_t *) &ctrl6, 1);
183 }
184
185 if (ret == 0)
186 {
187 ctrl6.low_noise = ((uint8_t) val & 0x10U) >> 4;
188 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL6, (uint8_t *) &ctrl6, 1);
189 }
190
191 else
192 {
193 ret = ret;
194 }
195
196 return ret;
197 }
198
199 /**
200 * @brief Select accelerometer operating modes.[get]
201 *
202 * @param ctx read / write interface definitions
203 * @param val change the values of mode / lp_mode in reg CTRL1
204 * and low_noise in reg CTRL6
205 * @retval interface status (MANDATORY: return 0 -> no Error)
206 *
207 */
iis2dlpc_power_mode_get(const stmdev_ctx_t * ctx,iis2dlpc_mode_t * val)208 int32_t iis2dlpc_power_mode_get(const stmdev_ctx_t *ctx,
209 iis2dlpc_mode_t *val)
210 {
211 iis2dlpc_ctrl1_t ctrl1;
212 iis2dlpc_ctrl6_t ctrl6;
213 int32_t ret;
214
215 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL1, (uint8_t *) &ctrl1, 1);
216
217 if (ret == 0)
218 {
219 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6, (uint8_t *) &ctrl6, 1);
220
221 switch (((ctrl6.low_noise << 4) + (ctrl1.mode << 2) +
222 ctrl1.lp_mode))
223 {
224 case IIS2DLPC_HIGH_PERFORMANCE:
225 *val = IIS2DLPC_HIGH_PERFORMANCE;
226 break;
227
228 case IIS2DLPC_CONT_LOW_PWR_4:
229 *val = IIS2DLPC_CONT_LOW_PWR_4;
230 break;
231
232 case IIS2DLPC_CONT_LOW_PWR_3:
233 *val = IIS2DLPC_CONT_LOW_PWR_3;
234 break;
235
236 case IIS2DLPC_CONT_LOW_PWR_2:
237 *val = IIS2DLPC_CONT_LOW_PWR_2;
238 break;
239
240 case IIS2DLPC_CONT_LOW_PWR_12bit:
241 *val = IIS2DLPC_CONT_LOW_PWR_12bit;
242 break;
243
244 case IIS2DLPC_SINGLE_LOW_PWR_4:
245 *val = IIS2DLPC_SINGLE_LOW_PWR_4;
246 break;
247
248 case IIS2DLPC_SINGLE_LOW_PWR_3:
249 *val = IIS2DLPC_SINGLE_LOW_PWR_3;
250 break;
251
252 case IIS2DLPC_SINGLE_LOW_PWR_2:
253 *val = IIS2DLPC_SINGLE_LOW_PWR_2;
254 break;
255
256 case IIS2DLPC_SINGLE_LOW_PWR_12bit:
257 *val = IIS2DLPC_SINGLE_LOW_PWR_12bit;
258 break;
259
260 case IIS2DLPC_HIGH_PERFORMANCE_LOW_NOISE:
261 *val = IIS2DLPC_HIGH_PERFORMANCE_LOW_NOISE;
262 break;
263
264 case IIS2DLPC_CONT_LOW_PWR_LOW_NOISE_4:
265 *val = IIS2DLPC_CONT_LOW_PWR_LOW_NOISE_4;
266 break;
267
268 case IIS2DLPC_CONT_LOW_PWR_LOW_NOISE_3:
269 *val = IIS2DLPC_CONT_LOW_PWR_LOW_NOISE_3;
270 break;
271
272 case IIS2DLPC_CONT_LOW_PWR_LOW_NOISE_2:
273 *val = IIS2DLPC_CONT_LOW_PWR_LOW_NOISE_2;
274 break;
275
276 case IIS2DLPC_CONT_LOW_PWR_LOW_NOISE_12bit:
277 *val = IIS2DLPC_CONT_LOW_PWR_LOW_NOISE_12bit;
278 break;
279
280 case IIS2DLPC_SINGLE_LOW_PWR_LOW_NOISE_4:
281 *val = IIS2DLPC_SINGLE_LOW_PWR_LOW_NOISE_4;
282 break;
283
284 case IIS2DLPC_SINGLE_LOW_PWR_LOW_NOISE_3:
285 *val = IIS2DLPC_SINGLE_LOW_PWR_LOW_NOISE_3;
286 break;
287
288 case IIS2DLPC_SINGLE_LOW_PWR_LOW_NOISE_2:
289 *val = IIS2DLPC_SINGLE_LOW_PWR_LOW_NOISE_2;
290 break;
291
292 case IIS2DLPC_SINGLE_LOW_LOW_NOISE_PWR_12bit:
293 *val = IIS2DLPC_SINGLE_LOW_LOW_NOISE_PWR_12bit;
294 break;
295
296 default:
297 *val = IIS2DLPC_HIGH_PERFORMANCE;
298 break;
299 }
300 }
301
302 return ret;
303 }
304
305 /**
306 * @brief Accelerometer data rate selection.[set]
307 *
308 * @param ctx read / write interface definitions
309 * @param val change the values of odr in reg CTRL1
310 * @retval interface status (MANDATORY: return 0 -> no Error)
311 *
312 */
iis2dlpc_data_rate_set(const stmdev_ctx_t * ctx,iis2dlpc_odr_t val)313 int32_t iis2dlpc_data_rate_set(const stmdev_ctx_t *ctx, iis2dlpc_odr_t val)
314 {
315 iis2dlpc_ctrl1_t ctrl1;
316 iis2dlpc_ctrl3_t ctrl3;
317 int32_t ret;
318
319 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL1, (uint8_t *) &ctrl1, 1);
320
321 if (ret == 0)
322 {
323 ctrl1.odr = (uint8_t) val;
324 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL1, (uint8_t *) &ctrl1, 1);
325 }
326
327 if (ret == 0)
328 {
329 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3, (uint8_t *) &ctrl3, 1);
330 }
331
332 if (ret == 0)
333 {
334 ctrl3.slp_mode = ((uint8_t) val & 0x30U) >> 4;
335 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL3, (uint8_t *) &ctrl3, 1);
336 }
337
338 else
339 {
340 ret = ret;
341 }
342
343 return ret;
344 }
345
346 /**
347 * @brief Accelerometer data rate selection.[get]
348 *
349 * @param ctx read / write interface definitions
350 * @param val Get the values of odr in reg CTRL1
351 * @retval interface status (MANDATORY: return 0 -> no Error)
352 *
353 */
iis2dlpc_data_rate_get(const stmdev_ctx_t * ctx,iis2dlpc_odr_t * val)354 int32_t iis2dlpc_data_rate_get(const stmdev_ctx_t *ctx, iis2dlpc_odr_t *val)
355 {
356 iis2dlpc_ctrl1_t ctrl1;
357 iis2dlpc_ctrl3_t ctrl3;
358 int32_t ret;
359
360 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL1, (uint8_t *) &ctrl1, 1);
361
362 if (ret == 0)
363 {
364 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3, (uint8_t *) &ctrl3, 1);
365
366 switch ((ctrl3.slp_mode << 4) + ctrl1.odr)
367 {
368 case IIS2DLPC_XL_ODR_OFF:
369 *val = IIS2DLPC_XL_ODR_OFF;
370 break;
371
372 case IIS2DLPC_XL_ODR_1Hz6_LP_ONLY:
373 *val = IIS2DLPC_XL_ODR_1Hz6_LP_ONLY;
374 break;
375
376 case IIS2DLPC_XL_ODR_12Hz5:
377 *val = IIS2DLPC_XL_ODR_12Hz5;
378 break;
379
380 case IIS2DLPC_XL_ODR_25Hz:
381 *val = IIS2DLPC_XL_ODR_25Hz;
382 break;
383
384 case IIS2DLPC_XL_ODR_50Hz:
385 *val = IIS2DLPC_XL_ODR_50Hz;
386 break;
387
388 case IIS2DLPC_XL_ODR_100Hz:
389 *val = IIS2DLPC_XL_ODR_100Hz;
390 break;
391
392 case IIS2DLPC_XL_ODR_200Hz:
393 *val = IIS2DLPC_XL_ODR_200Hz;
394 break;
395
396 case IIS2DLPC_XL_ODR_400Hz:
397 *val = IIS2DLPC_XL_ODR_400Hz;
398 break;
399
400 case IIS2DLPC_XL_ODR_800Hz:
401 *val = IIS2DLPC_XL_ODR_800Hz;
402 break;
403
404 case IIS2DLPC_XL_ODR_1k6Hz:
405 *val = IIS2DLPC_XL_ODR_1k6Hz;
406 break;
407
408 case IIS2DLPC_XL_SET_SW_TRIG:
409 *val = IIS2DLPC_XL_SET_SW_TRIG;
410 break;
411
412 case IIS2DLPC_XL_SET_PIN_TRIG:
413 *val = IIS2DLPC_XL_SET_PIN_TRIG;
414 break;
415
416 default:
417 *val = IIS2DLPC_XL_ODR_OFF;
418 break;
419 }
420 }
421
422 return ret;
423 }
424
425 /**
426 * @brief Block data update.[set]
427 *
428 * @param ctx read / write interface definitions
429 * @param val change the values of bdu in reg CTRL2
430 * @retval interface status (MANDATORY: return 0 -> no Error)
431 *
432 */
iis2dlpc_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)433 int32_t iis2dlpc_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val)
434 {
435 iis2dlpc_ctrl2_t reg;
436 int32_t ret;
437
438 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1);
439
440 if (ret == 0)
441 {
442 reg.bdu = val;
443 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1);
444 }
445
446 return ret;
447 }
448
449 /**
450 * @brief Block data update.[get]
451 *
452 * @param ctx read / write interface definitions
453 * @param val change the values of bdu in reg CTRL2
454 * @retval interface status (MANDATORY: return 0 -> no Error)
455 *
456 */
iis2dlpc_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)457 int32_t iis2dlpc_block_data_update_get(const stmdev_ctx_t *ctx,
458 uint8_t *val)
459 {
460 iis2dlpc_ctrl2_t reg;
461 int32_t ret;
462
463 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1);
464 *val = reg.bdu;
465
466 return ret;
467 }
468
469 /**
470 * @brief Accelerometer full-scale selection.[set]
471 *
472 * @param ctx read / write interface definitions
473 * @param val change the values of fs in reg CTRL6
474 * @retval interface status (MANDATORY: return 0 -> no Error)
475 *
476 */
iis2dlpc_full_scale_set(const stmdev_ctx_t * ctx,iis2dlpc_fs_t val)477 int32_t iis2dlpc_full_scale_set(const stmdev_ctx_t *ctx, iis2dlpc_fs_t val)
478 {
479 iis2dlpc_ctrl6_t reg;
480 int32_t ret;
481
482 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6, (uint8_t *) ®, 1);
483
484 if (ret == 0)
485 {
486 reg.fs = (uint8_t) val;
487 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL6, (uint8_t *) ®, 1);
488 }
489
490 return ret;
491 }
492
493 /**
494 * @brief Accelerometer full-scale selection.[get]
495 *
496 * @param ctx read / write interface definitions
497 * @param val Get the values of fs in reg CTRL6
498 * @retval interface status (MANDATORY: return 0 -> no Error)
499 *
500 */
iis2dlpc_full_scale_get(const stmdev_ctx_t * ctx,iis2dlpc_fs_t * val)501 int32_t iis2dlpc_full_scale_get(const stmdev_ctx_t *ctx, iis2dlpc_fs_t *val)
502 {
503 iis2dlpc_ctrl6_t reg;
504 int32_t ret;
505
506 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6, (uint8_t *) ®, 1);
507
508 switch (reg.fs)
509 {
510 case IIS2DLPC_2g:
511 *val = IIS2DLPC_2g;
512 break;
513
514 case IIS2DLPC_4g:
515 *val = IIS2DLPC_4g;
516 break;
517
518 case IIS2DLPC_8g:
519 *val = IIS2DLPC_8g;
520 break;
521
522 case IIS2DLPC_16g:
523 *val = IIS2DLPC_16g;
524 break;
525
526 default:
527 *val = IIS2DLPC_2g;
528 break;
529 }
530
531 return ret;
532 }
533
534 /**
535 * @brief The STATUS_REG register of the device.[get]
536 *
537 * @param ctx read / write interface definitions
538 * @param val union of registers from STATUS to
539 * @retval interface status (MANDATORY: return 0 -> no Error)
540 *
541 */
iis2dlpc_status_reg_get(const stmdev_ctx_t * ctx,iis2dlpc_status_t * val)542 int32_t iis2dlpc_status_reg_get(const stmdev_ctx_t *ctx,
543 iis2dlpc_status_t *val)
544 {
545 int32_t ret;
546
547 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_STATUS, (uint8_t *) val, 1);
548
549 return ret;
550 }
551
552 /**
553 * @brief Accelerometer new data available.[get]
554 *
555 * @param ctx read / write interface definitions
556 * @param val change the values of drdy in reg STATUS
557 * @retval interface status (MANDATORY: return 0 -> no Error)
558 *
559 */
iis2dlpc_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)560 int32_t iis2dlpc_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val)
561 {
562 iis2dlpc_status_t reg;
563 int32_t ret;
564
565 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_STATUS, (uint8_t *) ®, 1);
566 *val = reg.drdy;
567
568 return ret;
569 }
570 /**
571 * @brief Read all the interrupt/status flag of the device.[get]
572 *
573 * @param ctx read / write interface definitions
574 * @param val registers STATUS_DUP, WAKE_UP_SRC,
575 * TAP_SRC, SIXD_SRC, ALL_INT_SRC
576 * @retval interface status (MANDATORY: return 0 -> no Error)
577 *
578 */
iis2dlpc_all_sources_get(const stmdev_ctx_t * ctx,iis2dlpc_all_sources_t * val)579 int32_t iis2dlpc_all_sources_get(const stmdev_ctx_t *ctx,
580 iis2dlpc_all_sources_t *val)
581 {
582 int32_t ret;
583
584 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_STATUS_DUP, (uint8_t *) val, 5);
585
586 return ret;
587 }
588
589 /**
590 * @brief Accelerometer X-axis user offset correction expressed in two’s
591 * complement, weight depends on bit USR_OFF_W. The value must be
592 * in the range [-127 127].[set]
593 *
594 * @param ctx read / write interface definitions
595 * @param buff buffer that contains data to write
596 * @retval interface status (MANDATORY: return 0 -> no Error)
597 *
598 */
iis2dlpc_usr_offset_x_set(const stmdev_ctx_t * ctx,uint8_t * buff)599 int32_t iis2dlpc_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff)
600 {
601 int32_t ret;
602
603 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_X_OFS_USR, buff, 1);
604
605 return ret;
606 }
607
608 /**
609 * @brief Accelerometer X-axis user offset correction expressed in two’s
610 * complement, weight depends on bit USR_OFF_W. The value must be
611 * in the range [-127 127].[get]
612 *
613 * @param ctx read / write interface definitions
614 * @param buff buffer that stores data read
615 * @retval interface status (MANDATORY: return 0 -> no Error)
616 *
617 */
iis2dlpc_usr_offset_x_get(const stmdev_ctx_t * ctx,uint8_t * buff)618 int32_t iis2dlpc_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff)
619 {
620 int32_t ret;
621
622 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_X_OFS_USR, buff, 1);
623
624 return ret;
625 }
626
627 /**
628 * @brief Accelerometer Y-axis user offset correction expressed in two’s
629 * complement, weight depends on bit USR_OFF_W. The value must be
630 * in the range [-127 127].[set]
631 *
632 * @param ctx read / write interface definitions
633 * @param buff buffer that contains data to write
634 * @retval interface status (MANDATORY: return 0 -> no Error)
635 *
636 */
iis2dlpc_usr_offset_y_set(const stmdev_ctx_t * ctx,uint8_t * buff)637 int32_t iis2dlpc_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff)
638 {
639 int32_t ret;
640
641 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_Y_OFS_USR, buff, 1);
642
643 return ret;
644 }
645
646 /**
647 * @brief Accelerometer Y-axis user offset correction expressed in two’s
648 * complement, weight depends on bit USR_OFF_W. The value must be
649 * in the range [-127 127].[get]
650 *
651 * @param ctx read / write interface definitions
652 * @param buff buffer that stores data read
653 * @retval interface status (MANDATORY: return 0 -> no Error)
654 *
655 */
iis2dlpc_usr_offset_y_get(const stmdev_ctx_t * ctx,uint8_t * buff)656 int32_t iis2dlpc_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff)
657 {
658 int32_t ret;
659
660 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_Y_OFS_USR, buff, 1);
661
662 return ret;
663 }
664
665 /**
666 * @brief Accelerometer Z-axis user offset correction expressed in two’s
667 * complement, weight depends on bit USR_OFF_W. The value must be
668 * in the range [-127 127].[set]
669 *
670 * @param ctx read / write interface definitions
671 * @param buff buffer that contains data to write
672 * @retval interface status (MANDATORY: return 0 -> no Error)
673 *
674 */
iis2dlpc_usr_offset_z_set(const stmdev_ctx_t * ctx,uint8_t * buff)675 int32_t iis2dlpc_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff)
676 {
677 int32_t ret;
678
679 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_Z_OFS_USR, buff, 1);
680
681 return ret;
682 }
683
684 /**
685 * @brief Accelerometer Z-axis user offset correction expressed in two’s
686 * complement, weight depends on bit USR_OFF_W. The value must be
687 * in the range [-127 127].[get]
688 *
689 * @param ctx read / write interface definitions
690 * @param buff buffer that stores data read
691 * @retval interface status (MANDATORY: return 0 -> no Error)
692 *
693 */
iis2dlpc_usr_offset_z_get(const stmdev_ctx_t * ctx,uint8_t * buff)694 int32_t iis2dlpc_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff)
695 {
696 int32_t ret;
697
698 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_Z_OFS_USR, buff, 1);
699
700 return ret;
701 }
702
703 /**
704 * @brief Weight of XL user offset bits of registers X_OFS_USR,
705 * Y_OFS_USR, Z_OFS_USR.[set]
706 *
707 * @param ctx read / write interface definitions
708 * @param val change the values of usr_off_w in
709 * reg CTRL_REG7
710 * @retval interface status (MANDATORY: return 0 -> no Error)
711 *
712 */
iis2dlpc_offset_weight_set(const stmdev_ctx_t * ctx,iis2dlpc_usr_off_w_t val)713 int32_t iis2dlpc_offset_weight_set(const stmdev_ctx_t *ctx,
714 iis2dlpc_usr_off_w_t val)
715 {
716 iis2dlpc_ctrl7_t reg;
717 int32_t ret;
718
719 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1);
720
721 if (ret == 0)
722 {
723 reg.usr_off_w = (uint8_t) val;
724 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1);
725 }
726
727 return ret;
728 }
729
730 /**
731 * @brief Weight of XL user offset bits of registers X_OFS_USR,
732 * Y_OFS_USR, Z_OFS_USR.[get]
733 *
734 * @param ctx read / write interface definitions
735 * @param val Get the values of usr_off_w in reg CTRL_REG7
736 * @retval interface status (MANDATORY: return 0 -> no Error)
737 *
738 */
iis2dlpc_offset_weight_get(const stmdev_ctx_t * ctx,iis2dlpc_usr_off_w_t * val)739 int32_t iis2dlpc_offset_weight_get(const stmdev_ctx_t *ctx,
740 iis2dlpc_usr_off_w_t *val)
741 {
742 iis2dlpc_ctrl7_t reg;
743 int32_t ret;
744
745 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1);
746
747 switch (reg.usr_off_w)
748 {
749 case IIS2DLPC_LSb_977ug:
750 *val = IIS2DLPC_LSb_977ug;
751 break;
752
753 case IIS2DLPC_LSb_15mg6:
754 *val = IIS2DLPC_LSb_15mg6;
755 break;
756
757 default:
758 *val = IIS2DLPC_LSb_977ug;
759 break;
760 }
761
762 return ret;
763 }
764
765 /**
766 * @}
767 *
768 */
769
770 /**
771 * @defgroup IIS2DLPC_Data_Output
772 * @brief This section groups all the data output functions.
773 * @{
774 *
775 */
776
777 /**
778 * @brief Temperature data output register (r). L and H registers
779 * together express a 16-bit word in two’s complement.[get]
780 *
781 * @param ctx read / write interface definitions
782 * @param buff buffer that stores data read
783 * @retval interface status (MANDATORY: return 0 -> no Error)
784 *
785 */
iis2dlpc_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * val)786 int32_t iis2dlpc_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
787 {
788 uint8_t buff[2];
789 int32_t ret;
790
791 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_OUT_T_L, buff, 2);
792 *val = (int16_t)buff[1];
793 *val = (*val * 256) + (int16_t)buff[0];
794
795 return ret;
796 }
797
798 /**
799 * @brief Linear acceleration output register. The value is expressed as
800 * a 16-bit word in two’s complement.[get]
801 *
802 * @param ctx read / write interface definitions
803 * @param buff buffer that stores data read
804 * @retval interface status (MANDATORY: return 0 -> no Error)
805 *
806 */
iis2dlpc_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)807 int32_t iis2dlpc_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
808 {
809 uint8_t buff[6];
810 int32_t ret;
811
812 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_OUT_X_L, buff, 6);
813 val[0] = (int16_t)buff[1];
814 val[0] = (val[0] * 256) + (int16_t)buff[0];
815 val[1] = (int16_t)buff[3];
816 val[1] = (val[1] * 256) + (int16_t)buff[2];
817 val[2] = (int16_t)buff[5];
818 val[2] = (val[2] * 256) + (int16_t)buff[4];
819
820 return ret;
821 }
822
823 /**
824 * @}
825 *
826 */
827
828 /**
829 * @defgroup IIS2DLPC_Common
830 * @brief This section groups common useful functions.
831 * @{
832 *
833 */
834
835 /**
836 * @brief Device Who am I.[get]
837 *
838 * @param ctx read / write interface definitions
839 * @param buff buffer that stores data read
840 * @retval interface status (MANDATORY: return 0 -> no Error)
841 *
842 */
iis2dlpc_device_id_get(const stmdev_ctx_t * ctx,uint8_t * buff)843 int32_t iis2dlpc_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
844 {
845 int32_t ret;
846
847 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WHO_AM_I, buff, 1);
848
849 return ret;
850 }
851
852 /**
853 * @brief Register address automatically incremented during multiple byte
854 * access with a serial interface.[set]
855 *
856 * @param ctx read / write interface definitions
857 * @param val change the values of if_add_inc in reg CTRL2
858 * @retval interface status (MANDATORY: return 0 -> no Error)
859 *
860 */
iis2dlpc_auto_increment_set(const stmdev_ctx_t * ctx,uint8_t val)861 int32_t iis2dlpc_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val)
862 {
863 iis2dlpc_ctrl2_t reg;
864 int32_t ret;
865
866 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1);
867
868 if (ret == 0)
869 {
870 reg.if_add_inc = val;
871 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1);
872 }
873
874 return ret;
875 }
876
877 /**
878 * @brief Register address automatically incremented during multiple
879 * byte access with a serial interface.[get]
880 *
881 * @param ctx read / write interface definitions
882 * @param val change the values of if_add_inc in reg CTRL2
883 * @retval interface status (MANDATORY: return 0 -> no Error)
884 *
885 */
iis2dlpc_auto_increment_get(const stmdev_ctx_t * ctx,uint8_t * val)886 int32_t iis2dlpc_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val)
887 {
888 iis2dlpc_ctrl2_t reg;
889 int32_t ret;
890
891 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1);
892 *val = reg.if_add_inc;
893
894 return ret;
895 }
896
897 /**
898 * @brief Software reset. Restore the default values in user registers.[set]
899 *
900 * @param ctx read / write interface definitions
901 * @param val change the values of soft_reset in reg CTRL2
902 * @retval interface status (MANDATORY: return 0 -> no Error)
903 *
904 */
iis2dlpc_reset_set(const stmdev_ctx_t * ctx,uint8_t val)905 int32_t iis2dlpc_reset_set(const stmdev_ctx_t *ctx, uint8_t val)
906 {
907 iis2dlpc_ctrl2_t reg;
908 int32_t ret;
909
910 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1);
911
912 if (ret == 0)
913 {
914 reg.soft_reset = val;
915 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1);
916 }
917
918 return ret;
919 }
920
921 /**
922 * @brief Software reset. Restore the default values in user registers.[get]
923 *
924 * @param ctx read / write interface definitions
925 * @param val change the values of soft_reset in reg CTRL2
926 * @retval interface status (MANDATORY: return 0 -> no Error)
927 *
928 */
iis2dlpc_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)929 int32_t iis2dlpc_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
930 {
931 iis2dlpc_ctrl2_t reg;
932 int32_t ret;
933
934 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1);
935 *val = reg.soft_reset;
936
937 return ret;
938 }
939
940 /**
941 * @brief Reboot memory content. Reload the calibration parameters.[set]
942 *
943 * @param ctx read / write interface definitions
944 * @param val change the values of boot in reg CTRL2
945 * @retval interface status (MANDATORY: return 0 -> no Error)
946 *
947 */
iis2dlpc_boot_set(const stmdev_ctx_t * ctx,uint8_t val)948 int32_t iis2dlpc_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
949 {
950 iis2dlpc_ctrl2_t reg;
951 int32_t ret;
952
953 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1);
954
955 if (ret == 0)
956 {
957 reg.boot = val;
958 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1);
959 }
960
961 return ret;
962 }
963
964 /**
965 * @brief Reboot memory content. Reload the calibration parameters.[get]
966 *
967 * @param ctx read / write interface definitions
968 * @param val change the values of boot in reg CTRL2
969 * @retval interface status (MANDATORY: return 0 -> no Error)
970 *
971 */
iis2dlpc_boot_get(const stmdev_ctx_t * ctx,uint8_t * val)972 int32_t iis2dlpc_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
973 {
974 iis2dlpc_ctrl2_t reg;
975 int32_t ret;
976
977 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1);
978 *val = reg.boot;
979
980 return ret;
981 }
982
983 /**
984 * @brief Sensor self-test enable.[set]
985 *
986 * @param ctx read / write interface definitions
987 * @param val change the values of st in reg CTRL3
988 * @retval interface status (MANDATORY: return 0 -> no Error)
989 *
990 */
iis2dlpc_self_test_set(const stmdev_ctx_t * ctx,iis2dlpc_st_t val)991 int32_t iis2dlpc_self_test_set(const stmdev_ctx_t *ctx, iis2dlpc_st_t val)
992 {
993 iis2dlpc_ctrl3_t reg;
994 int32_t ret;
995
996 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3, (uint8_t *) ®, 1);
997
998 if (ret == 0)
999 {
1000 reg.st = (uint8_t) val;
1001 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL3, (uint8_t *) ®, 1);
1002 }
1003
1004 return ret;
1005 }
1006
1007 /**
1008 * @brief Sensor self-test enable.[get]
1009 *
1010 * @param ctx read / write interface definitions
1011 * @param val Get the values of st in reg CTRL3
1012 * @retval interface status (MANDATORY: return 0 -> no Error)
1013 *
1014 */
iis2dlpc_self_test_get(const stmdev_ctx_t * ctx,iis2dlpc_st_t * val)1015 int32_t iis2dlpc_self_test_get(const stmdev_ctx_t *ctx, iis2dlpc_st_t *val)
1016 {
1017 iis2dlpc_ctrl3_t reg;
1018 int32_t ret;
1019
1020 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3, (uint8_t *) ®, 1);
1021
1022 switch (reg.st)
1023 {
1024 case IIS2DLPC_XL_ST_DISABLE:
1025 *val = IIS2DLPC_XL_ST_DISABLE;
1026 break;
1027
1028 case IIS2DLPC_XL_ST_POSITIVE:
1029 *val = IIS2DLPC_XL_ST_POSITIVE;
1030 break;
1031
1032 case IIS2DLPC_XL_ST_NEGATIVE:
1033 *val = IIS2DLPC_XL_ST_NEGATIVE;
1034 break;
1035
1036 default:
1037 *val = IIS2DLPC_XL_ST_DISABLE;
1038 break;
1039 }
1040
1041 return ret;
1042 }
1043
1044 /**
1045 * @brief Data-ready pulsed / letched mode.[set]
1046 *
1047 * @param ctx read / write interface definitions
1048 * @param val change the values of drdy_pulsed in reg CTRL_REG7
1049 * @retval interface status (MANDATORY: return 0 -> no Error)
1050 *
1051 */
iis2dlpc_data_ready_mode_set(const stmdev_ctx_t * ctx,iis2dlpc_drdy_pulsed_t val)1052 int32_t iis2dlpc_data_ready_mode_set(const stmdev_ctx_t *ctx,
1053 iis2dlpc_drdy_pulsed_t val)
1054 {
1055 iis2dlpc_ctrl7_t reg;
1056 int32_t ret;
1057
1058 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1);
1059
1060 if (ret == 0)
1061 {
1062 reg.drdy_pulsed = (uint8_t) val;
1063 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1);
1064 }
1065
1066 return ret;
1067 }
1068
1069 /**
1070 * @brief Data-ready pulsed / letched mode.[get]
1071 *
1072 * @param ctx read / write interface definitions
1073 * @param val Get the values of drdy_pulsed in reg CTRL_REG7
1074 * @retval interface status (MANDATORY: return 0 -> no Error)
1075 *
1076 */
iis2dlpc_data_ready_mode_get(const stmdev_ctx_t * ctx,iis2dlpc_drdy_pulsed_t * val)1077 int32_t iis2dlpc_data_ready_mode_get(const stmdev_ctx_t *ctx,
1078 iis2dlpc_drdy_pulsed_t *val)
1079 {
1080 iis2dlpc_ctrl7_t reg;
1081 int32_t ret;
1082
1083 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1);
1084
1085 switch (reg.drdy_pulsed)
1086 {
1087 case IIS2DLPC_DRDY_LATCHED:
1088 *val = IIS2DLPC_DRDY_LATCHED;
1089 break;
1090
1091 case IIS2DLPC_DRDY_PULSED:
1092 *val = IIS2DLPC_DRDY_PULSED;
1093 break;
1094
1095 default:
1096 *val = IIS2DLPC_DRDY_LATCHED;
1097 break;
1098 }
1099
1100 return ret;
1101 }
1102
1103 /**
1104 * @}
1105 *
1106 */
1107
1108 /**
1109 * @defgroup IIS2DLPC_Filters
1110 * @brief This section group all the functions concerning the filters
1111 * configuration.
1112 * @{
1113 *
1114 */
1115
1116 /**
1117 * @brief Accelerometer filtering path for outputs.[set]
1118 *
1119 * @param ctx read / write interface definitions
1120 * @param val change the values of fds in reg CTRL6
1121 * @retval interface status (MANDATORY: return 0 -> no Error)
1122 *
1123 */
iis2dlpc_filter_path_set(const stmdev_ctx_t * ctx,iis2dlpc_fds_t val)1124 int32_t iis2dlpc_filter_path_set(const stmdev_ctx_t *ctx,
1125 iis2dlpc_fds_t val)
1126 {
1127 iis2dlpc_ctrl6_t ctrl6;
1128 iis2dlpc_ctrl7_t ctrl_reg7;
1129 int32_t ret;
1130
1131 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6, (uint8_t *) &ctrl6, 1);
1132
1133 if (ret == 0)
1134 {
1135 ctrl6.fds = ((uint8_t) val & 0x10U) >> 4;
1136 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL6, (uint8_t *) &ctrl6, 1);
1137 }
1138
1139 if (ret == 0)
1140 {
1141 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) &ctrl_reg7, 1);
1142 }
1143
1144 if (ret == 0)
1145 {
1146 ctrl_reg7.usr_off_on_out = (uint8_t) val & 0x01U;
1147 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) &ctrl_reg7, 1);
1148 }
1149
1150 else
1151 {
1152 ret = ret;
1153 }
1154
1155 return ret;
1156 }
1157
1158 /**
1159 * @brief Accelerometer filtering path for outputs.[get]
1160 *
1161 * @param ctx read / write interface definitions
1162 * @param val Get the values of fds in reg CTRL6
1163 * @retval interface status (MANDATORY: return 0 -> no Error)
1164 *
1165 */
iis2dlpc_filter_path_get(const stmdev_ctx_t * ctx,iis2dlpc_fds_t * val)1166 int32_t iis2dlpc_filter_path_get(const stmdev_ctx_t *ctx,
1167 iis2dlpc_fds_t *val)
1168 {
1169 iis2dlpc_ctrl6_t ctrl6;
1170 iis2dlpc_ctrl7_t ctrl_reg7;
1171 int32_t ret;
1172
1173 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6, (uint8_t *) &ctrl6, 1);
1174
1175 if (ret == 0)
1176 {
1177 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) &ctrl_reg7, 1);
1178
1179 switch ((ctrl6.fds << 4) + ctrl_reg7.usr_off_on_out)
1180 {
1181 case IIS2DLPC_LPF_ON_OUT:
1182 *val = IIS2DLPC_LPF_ON_OUT;
1183 break;
1184
1185 case IIS2DLPC_USER_OFFSET_ON_OUT:
1186 *val = IIS2DLPC_USER_OFFSET_ON_OUT;
1187 break;
1188
1189 case IIS2DLPC_HIGH_PASS_ON_OUT:
1190 *val = IIS2DLPC_HIGH_PASS_ON_OUT;
1191 break;
1192
1193 default:
1194 *val = IIS2DLPC_LPF_ON_OUT;
1195 break;
1196 }
1197 }
1198
1199 return ret;
1200 }
1201
1202 /**
1203 * @brief Accelerometer cutoff filter frequency. Valid for low and high
1204 * pass filter.[set]
1205 *
1206 * @param ctx read / write interface definitions
1207 * @param val change the values of bw_filt in reg CTRL6
1208 * @retval interface status (MANDATORY: return 0 -> no Error)
1209 *
1210 */
iis2dlpc_filter_bandwidth_set(const stmdev_ctx_t * ctx,iis2dlpc_bw_filt_t val)1211 int32_t iis2dlpc_filter_bandwidth_set(const stmdev_ctx_t *ctx,
1212 iis2dlpc_bw_filt_t val)
1213 {
1214 iis2dlpc_ctrl6_t reg;
1215 int32_t ret;
1216
1217 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6, (uint8_t *) ®, 1);
1218
1219 if (ret == 0)
1220 {
1221 reg.bw_filt = (uint8_t) val;
1222 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL6, (uint8_t *) ®, 1);
1223 }
1224
1225 return ret;
1226 }
1227
1228 /**
1229 * @brief Accelerometer cutoff filter frequency. Valid for low and
1230 * high pass filter.[get]
1231 *
1232 * @param ctx read / write interface definitions
1233 * @param val Get the values of bw_filt in reg CTRL6
1234 * @retval interface status (MANDATORY: return 0 -> no Error)
1235 *
1236 */
iis2dlpc_filter_bandwidth_get(const stmdev_ctx_t * ctx,iis2dlpc_bw_filt_t * val)1237 int32_t iis2dlpc_filter_bandwidth_get(const stmdev_ctx_t *ctx,
1238 iis2dlpc_bw_filt_t *val)
1239 {
1240 iis2dlpc_ctrl6_t reg;
1241 int32_t ret;
1242
1243 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6, (uint8_t *) ®, 1);
1244
1245 switch (reg.bw_filt)
1246 {
1247 case IIS2DLPC_ODR_DIV_2:
1248 *val = IIS2DLPC_ODR_DIV_2;
1249 break;
1250
1251 case IIS2DLPC_ODR_DIV_4:
1252 *val = IIS2DLPC_ODR_DIV_4;
1253 break;
1254
1255 case IIS2DLPC_ODR_DIV_10:
1256 *val = IIS2DLPC_ODR_DIV_10;
1257 break;
1258
1259 case IIS2DLPC_ODR_DIV_20:
1260 *val = IIS2DLPC_ODR_DIV_20;
1261 break;
1262
1263 default:
1264 *val = IIS2DLPC_ODR_DIV_2;
1265 break;
1266 }
1267
1268 return ret;
1269 }
1270
1271 /**
1272 * @brief Enable HP filter reference mode.[set]
1273 *
1274 * @param ctx read / write interface definitions
1275 * @param val change the values of hp_ref_mode in reg CTRL_REG7
1276 * @retval interface status (MANDATORY: return 0 -> no Error)
1277 *
1278 */
iis2dlpc_reference_mode_set(const stmdev_ctx_t * ctx,uint8_t val)1279 int32_t iis2dlpc_reference_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
1280 {
1281 iis2dlpc_ctrl7_t reg;
1282 int32_t ret;
1283
1284 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1);
1285
1286 if (ret == 0)
1287 {
1288 reg.hp_ref_mode = val;
1289 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1);
1290 }
1291
1292 return ret;
1293 }
1294
1295 /**
1296 * @brief Enable HP filter reference mode.[get]
1297 *
1298 * @param ctx read / write interface definitions
1299 * @param val change the values of hp_ref_mode in reg CTRL_REG7
1300 * @retval interface status (MANDATORY: return 0 -> no Error)
1301 *
1302 */
iis2dlpc_reference_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)1303 int32_t iis2dlpc_reference_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
1304 {
1305 iis2dlpc_ctrl7_t reg;
1306 int32_t ret;
1307
1308 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1);
1309 *val = reg.hp_ref_mode;
1310
1311 return ret;
1312 }
1313
1314 /**
1315 * @}
1316 *
1317 */
1318
1319 /**
1320 * @defgroup IIS2DLPC_Serial_Interface
1321 * @brief This section groups all the functions concerning main serial
1322 * interface management (not auxiliary)
1323 * @{
1324 *
1325 */
1326
1327 /**
1328 * @brief SPI Serial Interface Mode selection.[set]
1329 *
1330 * @param ctx read / write interface definitions
1331 * @param val change the values of sim in reg CTRL2
1332 * @retval interface status (MANDATORY: return 0 -> no Error)
1333 *
1334 */
iis2dlpc_spi_mode_set(const stmdev_ctx_t * ctx,iis2dlpc_sim_t val)1335 int32_t iis2dlpc_spi_mode_set(const stmdev_ctx_t *ctx, iis2dlpc_sim_t val)
1336 {
1337 iis2dlpc_ctrl2_t reg;
1338 int32_t ret;
1339
1340 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1);
1341
1342 if (ret == 0)
1343 {
1344 reg.sim = (uint8_t) val;
1345 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1);
1346 }
1347
1348 return ret;
1349 }
1350
1351 /**
1352 * @brief SPI Serial Interface Mode selection.[get]
1353 *
1354 * @param ctx read / write interface definitions
1355 * @param val Get the values of sim in reg CTRL2
1356 * @retval interface status (MANDATORY: return 0 -> no Error)
1357 *
1358 */
iis2dlpc_spi_mode_get(const stmdev_ctx_t * ctx,iis2dlpc_sim_t * val)1359 int32_t iis2dlpc_spi_mode_get(const stmdev_ctx_t *ctx, iis2dlpc_sim_t *val)
1360 {
1361 iis2dlpc_ctrl2_t reg;
1362 int32_t ret;
1363
1364 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1);
1365
1366 switch (reg.sim)
1367 {
1368 case IIS2DLPC_SPI_4_WIRE:
1369 *val = IIS2DLPC_SPI_4_WIRE;
1370 break;
1371
1372 case IIS2DLPC_SPI_3_WIRE:
1373 *val = IIS2DLPC_SPI_3_WIRE;
1374 break;
1375
1376 default:
1377 *val = IIS2DLPC_SPI_4_WIRE;
1378 break;
1379 }
1380
1381 return ret;
1382 }
1383
1384 /**
1385 * @brief Disable / Enable I2C interface.[set]
1386 *
1387 * @param ctx read / write interface definitions
1388 * @param val change the values of i2c_disable in
1389 * reg CTRL2
1390 * @retval interface status (MANDATORY: return 0 -> no Error)
1391 *
1392 */
iis2dlpc_i2c_interface_set(const stmdev_ctx_t * ctx,iis2dlpc_i2c_disable_t val)1393 int32_t iis2dlpc_i2c_interface_set(const stmdev_ctx_t *ctx,
1394 iis2dlpc_i2c_disable_t val)
1395 {
1396 iis2dlpc_ctrl2_t reg;
1397 int32_t ret;
1398
1399 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1);
1400
1401 if (ret == 0)
1402 {
1403 reg.i2c_disable = (uint8_t) val;
1404 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1);
1405 }
1406
1407 return ret;
1408 }
1409
1410 /**
1411 * @brief Disable / Enable I2C interface.[get]
1412 *
1413 * @param ctx read / write interface definitions
1414 * @param val Get the values of i2c_disable in reg CTRL2
1415 * @retval interface status (MANDATORY: return 0 -> no Error)
1416 *
1417 */
iis2dlpc_i2c_interface_get(const stmdev_ctx_t * ctx,iis2dlpc_i2c_disable_t * val)1418 int32_t iis2dlpc_i2c_interface_get(const stmdev_ctx_t *ctx,
1419 iis2dlpc_i2c_disable_t *val)
1420 {
1421 iis2dlpc_ctrl2_t reg;
1422 int32_t ret;
1423
1424 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1);
1425
1426 switch (reg.i2c_disable)
1427 {
1428 case IIS2DLPC_I2C_ENABLE:
1429 *val = IIS2DLPC_I2C_ENABLE;
1430 break;
1431
1432 case IIS2DLPC_I2C_DISABLE:
1433 *val = IIS2DLPC_I2C_DISABLE;
1434 break;
1435
1436 default:
1437 *val = IIS2DLPC_I2C_ENABLE;
1438 break;
1439 }
1440
1441 return ret;
1442 }
1443
1444 /**
1445 * @brief Disconnect CS pull-up.[set]
1446 *
1447 * @param ctx read / write interface definitions
1448 * @param val change the values of cs_pu_disc in reg CTRL2
1449 * @retval interface status (MANDATORY: return 0 -> no Error)
1450 *
1451 */
iis2dlpc_cs_mode_set(const stmdev_ctx_t * ctx,iis2dlpc_cs_pu_disc_t val)1452 int32_t iis2dlpc_cs_mode_set(const stmdev_ctx_t *ctx,
1453 iis2dlpc_cs_pu_disc_t val)
1454 {
1455 iis2dlpc_ctrl2_t reg;
1456 int32_t ret;
1457
1458 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1);
1459
1460 if (ret == 0)
1461 {
1462 reg.cs_pu_disc = (uint8_t) val;
1463 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1);
1464 }
1465
1466 return ret;
1467 }
1468
1469 /**
1470 * @brief Disconnect CS pull-up.[get]
1471 *
1472 * @param ctx read / write interface definitions
1473 * @param val Get the values of cs_pu_disc in reg CTRL2
1474 * @retval interface status (MANDATORY: return 0 -> no Error)
1475 *
1476 */
iis2dlpc_cs_mode_get(const stmdev_ctx_t * ctx,iis2dlpc_cs_pu_disc_t * val)1477 int32_t iis2dlpc_cs_mode_get(const stmdev_ctx_t *ctx,
1478 iis2dlpc_cs_pu_disc_t *val)
1479 {
1480 iis2dlpc_ctrl2_t reg;
1481 int32_t ret;
1482
1483 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1);
1484
1485 switch (reg.cs_pu_disc)
1486 {
1487 case IIS2DLPC_PULL_UP_CONNECT:
1488 *val = IIS2DLPC_PULL_UP_CONNECT;
1489 break;
1490
1491 case IIS2DLPC_PULL_UP_DISCONNECT:
1492 *val = IIS2DLPC_PULL_UP_DISCONNECT;
1493 break;
1494
1495 default:
1496 *val = IIS2DLPC_PULL_UP_CONNECT;
1497 break;
1498 }
1499
1500 return ret;
1501 }
1502
1503 /**
1504 * @}
1505 *
1506 */
1507
1508 /**
1509 * @defgroup IIS2DLPC_Interrupt_Pins
1510 * @brief This section groups all the functions that manage interrupt pins
1511 * @{
1512 *
1513 */
1514
1515 /**
1516 * @brief Interrupt active-high/low.[set]
1517 *
1518 * @param ctx read / write interface definitions
1519 * @param val change the values of h_lactive in reg CTRL3
1520 * @retval interface status (MANDATORY: return 0 -> no Error)
1521 *
1522 */
iis2dlpc_pin_polarity_set(const stmdev_ctx_t * ctx,iis2dlpc_h_lactive_t val)1523 int32_t iis2dlpc_pin_polarity_set(const stmdev_ctx_t *ctx,
1524 iis2dlpc_h_lactive_t val)
1525 {
1526 iis2dlpc_ctrl3_t reg;
1527 int32_t ret;
1528
1529 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3, (uint8_t *) ®, 1);
1530
1531 if (ret == 0)
1532 {
1533 reg.h_lactive = (uint8_t) val;
1534 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL3, (uint8_t *) ®, 1);
1535 }
1536
1537 return ret;
1538 }
1539
1540 /**
1541 * @brief Interrupt active-high/low.[get]
1542 *
1543 * @param ctx read / write interface definitions
1544 * @param val Get the values of h_lactive in reg CTRL3
1545 * @retval interface status (MANDATORY: return 0 -> no Error)
1546 *
1547 */
iis2dlpc_pin_polarity_get(const stmdev_ctx_t * ctx,iis2dlpc_h_lactive_t * val)1548 int32_t iis2dlpc_pin_polarity_get(const stmdev_ctx_t *ctx,
1549 iis2dlpc_h_lactive_t *val)
1550 {
1551 iis2dlpc_ctrl3_t reg;
1552 int32_t ret;
1553
1554 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3, (uint8_t *) ®, 1);
1555
1556 switch (reg.h_lactive)
1557 {
1558 case IIS2DLPC_ACTIVE_HIGH:
1559 *val = IIS2DLPC_ACTIVE_HIGH;
1560 break;
1561
1562 case IIS2DLPC_ACTIVE_LOW:
1563 *val = IIS2DLPC_ACTIVE_LOW;
1564 break;
1565
1566 default:
1567 *val = IIS2DLPC_ACTIVE_HIGH;
1568 break;
1569 }
1570
1571 return ret;
1572 }
1573
1574 /**
1575 * @brief Latched/pulsed interrupt.[set]
1576 *
1577 * @param ctx read / write interface definitions
1578 * @param val change the values of lir in reg CTRL3
1579 * @retval interface status (MANDATORY: return 0 -> no Error)
1580 *
1581 */
iis2dlpc_int_notification_set(const stmdev_ctx_t * ctx,iis2dlpc_lir_t val)1582 int32_t iis2dlpc_int_notification_set(const stmdev_ctx_t *ctx,
1583 iis2dlpc_lir_t val)
1584 {
1585 iis2dlpc_ctrl3_t reg;
1586 int32_t ret;
1587
1588 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3, (uint8_t *) ®, 1);
1589
1590 if (ret == 0)
1591 {
1592 reg.lir = (uint8_t) val;
1593 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL3, (uint8_t *) ®, 1);
1594 }
1595
1596 return ret;
1597 }
1598
1599 /**
1600 * @brief Latched/pulsed interrupt.[get]
1601 *
1602 * @param ctx read / write interface definitions
1603 * @param val Get the values of lir in reg CTRL3
1604 * @retval interface status (MANDATORY: return 0 -> no Error)
1605 *
1606 */
iis2dlpc_int_notification_get(const stmdev_ctx_t * ctx,iis2dlpc_lir_t * val)1607 int32_t iis2dlpc_int_notification_get(const stmdev_ctx_t *ctx,
1608 iis2dlpc_lir_t *val)
1609 {
1610 iis2dlpc_ctrl3_t reg;
1611 int32_t ret;
1612
1613 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3, (uint8_t *) ®, 1);
1614
1615 switch (reg.lir)
1616 {
1617 case IIS2DLPC_INT_PULSED:
1618 *val = IIS2DLPC_INT_PULSED;
1619 break;
1620
1621 case IIS2DLPC_INT_LATCHED:
1622 *val = IIS2DLPC_INT_LATCHED;
1623 break;
1624
1625 default:
1626 *val = IIS2DLPC_INT_PULSED;
1627 break;
1628 }
1629
1630 return ret;
1631 }
1632
1633 /**
1634 * @brief Push-pull/open drain selection on interrupt pads.[set]
1635 *
1636 * @param ctx read / write interface definitions
1637 * @param val change the values of pp_od in reg CTRL3
1638 * @retval interface status (MANDATORY: return 0 -> no Error)
1639 *
1640 */
iis2dlpc_pin_mode_set(const stmdev_ctx_t * ctx,iis2dlpc_pp_od_t val)1641 int32_t iis2dlpc_pin_mode_set(const stmdev_ctx_t *ctx, iis2dlpc_pp_od_t val)
1642 {
1643 iis2dlpc_ctrl3_t reg;
1644 int32_t ret;
1645
1646 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3, (uint8_t *) ®, 1);
1647
1648 if (ret == 0)
1649 {
1650 reg.pp_od = (uint8_t) val;
1651 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL3, (uint8_t *) ®, 1);
1652 }
1653
1654 return ret;
1655 }
1656
1657 /**
1658 * @brief Push-pull/open drain selection on interrupt pads.[get]
1659 *
1660 * @param ctx read / write interface definitions
1661 * @param val Get the values of pp_od in reg CTRL3
1662 * @retval interface status (MANDATORY: return 0 -> no Error)
1663 *
1664 */
iis2dlpc_pin_mode_get(const stmdev_ctx_t * ctx,iis2dlpc_pp_od_t * val)1665 int32_t iis2dlpc_pin_mode_get(const stmdev_ctx_t *ctx,
1666 iis2dlpc_pp_od_t *val)
1667 {
1668 iis2dlpc_ctrl3_t reg;
1669 int32_t ret;
1670
1671 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3, (uint8_t *) ®, 1);
1672
1673 switch (reg.pp_od)
1674 {
1675 case IIS2DLPC_PUSH_PULL:
1676 *val = IIS2DLPC_PUSH_PULL;
1677 break;
1678
1679 case IIS2DLPC_OPEN_DRAIN:
1680 *val = IIS2DLPC_OPEN_DRAIN;
1681 break;
1682
1683 default:
1684 *val = IIS2DLPC_PUSH_PULL;
1685 break;
1686 }
1687
1688 return ret;
1689 }
1690
1691 /**
1692 * @brief Select the signal that need to route on int1 pad.[set]
1693 *
1694 * @param ctx read / write interface definitions
1695 * @param val register CTRL4_INT1_PAD_CTRL.
1696 * @retval interface status (MANDATORY: return 0 -> no Error)
1697 *
1698 */
iis2dlpc_pin_int1_route_set(const stmdev_ctx_t * ctx,iis2dlpc_ctrl4_int1_pad_ctrl_t * val)1699 int32_t iis2dlpc_pin_int1_route_set(const stmdev_ctx_t *ctx,
1700 iis2dlpc_ctrl4_int1_pad_ctrl_t *val)
1701 {
1702 iis2dlpc_ctrl5_int2_pad_ctrl_t ctrl5_int2_pad_ctrl;
1703 iis2dlpc_ctrl7_t reg;
1704 int32_t ret;
1705
1706 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL5_INT2_PAD_CTRL,
1707 (uint8_t *) &ctrl5_int2_pad_ctrl, 1);
1708
1709 if (ret == 0)
1710 {
1711 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1);
1712 }
1713
1714 if (ret == 0)
1715 {
1716 if ((ctrl5_int2_pad_ctrl.int2_sleep_state
1717 | ctrl5_int2_pad_ctrl.int2_sleep_chg
1718 | val->int1_tap
1719 | val->int1_ff
1720 | val->int1_wu
1721 | val->int1_single_tap
1722 | val->int1_6d) != PROPERTY_DISABLE)
1723 {
1724 reg.interrupts_enable = PROPERTY_ENABLE;
1725 }
1726
1727 else
1728 {
1729 reg.interrupts_enable = PROPERTY_DISABLE;
1730 }
1731
1732 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL4_INT1_PAD_CTRL,
1733 (uint8_t *) val, 1);
1734 }
1735
1736 if (ret == 0)
1737 {
1738 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1);
1739 }
1740
1741 else
1742 {
1743 ret = ret;
1744 }
1745
1746 return ret;
1747 }
1748
1749 /**
1750 * @brief Select the signal that need to route on int1 pad.[get]
1751 *
1752 * @param ctx read / write interface definitions
1753 * @param val register CTRL4_INT1_PAD_CTRL.
1754 * @retval interface status (MANDATORY: return 0 -> no Error)
1755 *
1756 */
iis2dlpc_pin_int1_route_get(const stmdev_ctx_t * ctx,iis2dlpc_ctrl4_int1_pad_ctrl_t * val)1757 int32_t iis2dlpc_pin_int1_route_get(const stmdev_ctx_t *ctx,
1758 iis2dlpc_ctrl4_int1_pad_ctrl_t *val)
1759 {
1760 int32_t ret;
1761
1762 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL4_INT1_PAD_CTRL,
1763 (uint8_t *) val, 1);
1764
1765 return ret;
1766 }
1767
1768 /**
1769 * @brief Select the signal that need to route on int2 pad.[set]
1770 *
1771 * @param ctx read / write interface definitions
1772 * @param val register CTRL5_INT2_PAD_CTRL.
1773 * @retval interface status (MANDATORY: return 0 -> no Error)
1774 *
1775 */
iis2dlpc_pin_int2_route_set(const stmdev_ctx_t * ctx,iis2dlpc_ctrl5_int2_pad_ctrl_t * val)1776 int32_t iis2dlpc_pin_int2_route_set(const stmdev_ctx_t *ctx,
1777 iis2dlpc_ctrl5_int2_pad_ctrl_t *val)
1778 {
1779 iis2dlpc_ctrl7_t ctrl_reg7;
1780 iis2dlpc_ctrl4_int1_pad_ctrl_t ctrl4_int1_pad;
1781 int32_t ret;
1782
1783 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL4_INT1_PAD_CTRL,
1784 (uint8_t *)&ctrl4_int1_pad, 1);
1785
1786 if (ret == 0)
1787 {
1788 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) &ctrl_reg7, 1);
1789 }
1790
1791 if (ret == 0)
1792 {
1793 if ((val->int2_sleep_state
1794 | val->int2_sleep_chg
1795 | ctrl4_int1_pad.int1_tap
1796 | ctrl4_int1_pad.int1_ff
1797 | ctrl4_int1_pad.int1_wu
1798 | ctrl4_int1_pad.int1_single_tap
1799 | ctrl4_int1_pad.int1_6d) != PROPERTY_DISABLE)
1800 {
1801 ctrl_reg7.interrupts_enable = PROPERTY_ENABLE;
1802 }
1803
1804 else
1805 {
1806 ctrl_reg7.interrupts_enable = PROPERTY_DISABLE;
1807 }
1808
1809 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL5_INT2_PAD_CTRL,
1810 (uint8_t *) val, 1);
1811 }
1812
1813 if (ret == 0)
1814 {
1815 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) &ctrl_reg7, 1);
1816 }
1817
1818 else
1819 {
1820 ret = ret;
1821 }
1822
1823 return ret;
1824 }
1825
1826 /**
1827 * @brief Select the signal that need to route on int2 pad.[get]
1828 *
1829 * @param ctx read / write interface definitions
1830 * @param val register CTRL5_INT2_PAD_CTRL
1831 * @retval interface status (MANDATORY: return 0 -> no Error)
1832 *
1833 */
iis2dlpc_pin_int2_route_get(const stmdev_ctx_t * ctx,iis2dlpc_ctrl5_int2_pad_ctrl_t * val)1834 int32_t iis2dlpc_pin_int2_route_get(const stmdev_ctx_t *ctx,
1835 iis2dlpc_ctrl5_int2_pad_ctrl_t *val)
1836 {
1837 int32_t ret;
1838
1839 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL5_INT2_PAD_CTRL,
1840 (uint8_t *) val, 1);
1841
1842 return ret;
1843 }
1844 /**
1845 * @brief All interrupt signals become available on INT1 pin.[set]
1846 *
1847 * @param ctx read / write interface definitions
1848 * @param val change the values of int2_on_int1 in reg CTRL_REG7
1849 * @retval interface status (MANDATORY: return 0 -> no Error)
1850 *
1851 */
iis2dlpc_all_on_int1_set(const stmdev_ctx_t * ctx,uint8_t val)1852 int32_t iis2dlpc_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val)
1853 {
1854 iis2dlpc_ctrl7_t reg;
1855 int32_t ret;
1856
1857 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1);
1858
1859 if (ret == 0)
1860 {
1861 reg.int2_on_int1 = val;
1862 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1);
1863 }
1864
1865 return ret;
1866 }
1867
1868 /**
1869 * @brief All interrupt signals become available on INT1 pin.[get]
1870 *
1871 * @param ctx read / write interface definitions
1872 * @param val change the values of int2_on_int1 in reg CTRL_REG7
1873 * @retval interface status (MANDATORY: return 0 -> no Error)
1874 *
1875 */
iis2dlpc_all_on_int1_get(const stmdev_ctx_t * ctx,uint8_t * val)1876 int32_t iis2dlpc_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val)
1877 {
1878 iis2dlpc_ctrl7_t reg;
1879 int32_t ret;
1880
1881 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1);
1882 *val = reg.int2_on_int1;
1883
1884 return ret;
1885 }
1886
1887 /**
1888 * @}
1889 *
1890 */
1891
1892 /**
1893 * @defgroup IIS2DLPC_Wake_Up_Event
1894 * @brief This section groups all the functions that manage the Wake
1895 * Up event generation.
1896 * @{
1897 *
1898 */
1899
1900 /**
1901 * @brief Threshold for wakeup.1 LSB = FS_XL / 64.[set]
1902 *
1903 * @param ctx read / write interface definitions
1904 * @param val change the values of wk_ths in reg WAKE_UP_THS
1905 * @retval interface status (MANDATORY: return 0 -> no Error)
1906 *
1907 */
iis2dlpc_wkup_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)1908 int32_t iis2dlpc_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
1909 {
1910 iis2dlpc_wake_up_ths_t reg;
1911 int32_t ret;
1912
1913 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_THS, (uint8_t *) ®, 1);
1914
1915 if (ret == 0)
1916 {
1917 reg.wk_ths = val;
1918 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_WAKE_UP_THS, (uint8_t *) ®, 1);
1919 }
1920
1921 return ret;
1922 }
1923
1924 /**
1925 * @brief Threshold for wakeup.1 LSB = FS_XL / 64.[get]
1926 *
1927 * @param ctx read / write interface definitions
1928 * @param val change the values of wk_ths in reg WAKE_UP_THS
1929 * @retval interface status (MANDATORY: return 0 -> no Error)
1930 *
1931 */
iis2dlpc_wkup_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)1932 int32_t iis2dlpc_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
1933 {
1934 iis2dlpc_wake_up_ths_t reg;
1935 int32_t ret;
1936
1937 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_THS, (uint8_t *) ®, 1);
1938 *val = reg.wk_ths;
1939
1940 return ret;
1941 }
1942
1943 /**
1944 * @brief Wake up duration event.1LSb = 1 / ODR.[set]
1945 *
1946 * @param ctx read / write interface definitions
1947 * @param val change the values of wake_dur in reg WAKE_UP_DUR
1948 * @retval interface status (MANDATORY: return 0 -> no Error)
1949 *
1950 */
iis2dlpc_wkup_dur_set(const stmdev_ctx_t * ctx,uint8_t val)1951 int32_t iis2dlpc_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
1952 {
1953 iis2dlpc_wake_up_dur_t reg;
1954 int32_t ret;
1955
1956 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR, (uint8_t *) ®, 1);
1957
1958 if (ret == 0)
1959 {
1960 reg.wake_dur = val;
1961 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_WAKE_UP_DUR, (uint8_t *) ®, 1);
1962 }
1963
1964 return ret;
1965 }
1966
1967 /**
1968 * @brief Wake up duration event.1LSb = 1 / ODR.[get]
1969 *
1970 * @param ctx read / write interface definitions
1971 * @param val change the values of wake_dur in reg WAKE_UP_DUR
1972 * @retval interface status (MANDATORY: return 0 -> no Error)
1973 *
1974 */
iis2dlpc_wkup_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)1975 int32_t iis2dlpc_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
1976 {
1977 iis2dlpc_wake_up_dur_t reg;
1978 int32_t ret;
1979
1980 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR, (uint8_t *) ®, 1);
1981 *val = reg.wake_dur;
1982
1983 return ret;
1984 }
1985
1986 /**
1987 * @brief Data sent to wake-up interrupt function.[set]
1988 *
1989 * @param ctx read / write interface definitions
1990 * @param val change the values of usr_off_on_wu in reg CTRL_REG7
1991 * @retval interface status (MANDATORY: return 0 -> no Error)
1992 *
1993 */
iis2dlpc_wkup_feed_data_set(const stmdev_ctx_t * ctx,iis2dlpc_usr_off_on_wu_t val)1994 int32_t iis2dlpc_wkup_feed_data_set(const stmdev_ctx_t *ctx,
1995 iis2dlpc_usr_off_on_wu_t val)
1996 {
1997 iis2dlpc_ctrl7_t reg;
1998 int32_t ret;
1999
2000 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1);
2001
2002 if (ret == 0)
2003 {
2004 reg.usr_off_on_wu = (uint8_t) val;
2005 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1);
2006 }
2007
2008 return ret;
2009 }
2010
2011 /**
2012 * @brief Data sent to wake-up interrupt function.[get]
2013 *
2014 * @param ctx read / write interface definitions
2015 * @param val Get the values of usr_off_on_wu in reg CTRL_REG7
2016 * @retval interface status (MANDATORY: return 0 -> no Error)
2017 *
2018 */
iis2dlpc_wkup_feed_data_get(const stmdev_ctx_t * ctx,iis2dlpc_usr_off_on_wu_t * val)2019 int32_t iis2dlpc_wkup_feed_data_get(const stmdev_ctx_t *ctx,
2020 iis2dlpc_usr_off_on_wu_t *val)
2021 {
2022 iis2dlpc_ctrl7_t reg;
2023 int32_t ret;
2024
2025 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1);
2026
2027 switch (reg.usr_off_on_wu)
2028 {
2029 case IIS2DLPC_HP_FEED:
2030 *val = IIS2DLPC_HP_FEED;
2031 break;
2032
2033 case IIS2DLPC_USER_OFFSET_FEED:
2034 *val = IIS2DLPC_USER_OFFSET_FEED;
2035 break;
2036
2037 default:
2038 *val = IIS2DLPC_HP_FEED;
2039 break;
2040 }
2041
2042 return ret;
2043 }
2044
2045 /**
2046 * @}
2047 *
2048 */
2049
2050 /**
2051 * @defgroup IIS2DLPC_Activity/Inactivity_Detection
2052 * @brief This section groups all the functions concerning
2053 * activity/inactivity detection.
2054 * @{
2055 *
2056 */
2057
2058 /**
2059 * @brief Config activity / inactivity or
2060 * stationary / motion detection.[set]
2061 *
2062 * @param ctx read / write interface definitions
2063 * @param val change the values of sleep_on / stationary in
2064 * reg WAKE_UP_THS / WAKE_UP_DUR
2065 * @retval interface status (MANDATORY: return 0 -> no Error)
2066 *
2067 */
iis2dlpc_act_mode_set(const stmdev_ctx_t * ctx,iis2dlpc_sleep_on_t val)2068 int32_t iis2dlpc_act_mode_set(const stmdev_ctx_t *ctx,
2069 iis2dlpc_sleep_on_t val)
2070 {
2071 iis2dlpc_wake_up_ths_t wake_up_ths;
2072 iis2dlpc_wake_up_dur_t wake_up_dur;
2073 int32_t ret;
2074
2075 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_THS,
2076 (uint8_t *) &wake_up_ths, 1);
2077
2078 if (ret == 0)
2079 {
2080 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR,
2081 (uint8_t *) &wake_up_dur, 1);
2082 }
2083
2084 if (ret == 0)
2085 {
2086 wake_up_ths.sleep_on = (uint8_t) val & 0x01U;
2087 wake_up_dur.stationary = ((uint8_t)val & 0x02U) >> 1;
2088 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_WAKE_UP_THS,
2089 (uint8_t *) &wake_up_ths, 2);
2090 }
2091
2092 else
2093 {
2094 ret = ret;
2095 }
2096
2097 return ret;
2098 }
2099
2100 /**
2101 * @brief Config activity / inactivity or
2102 * stationary / motion detection. [get]
2103 *
2104 * @param ctx read / write interface definitions
2105 * @param val Get the values of sleep_on in reg WAKE_UP_THS
2106 * @retval interface status (MANDATORY: return 0 -> no Error)
2107 *
2108 */
iis2dlpc_act_mode_get(const stmdev_ctx_t * ctx,iis2dlpc_sleep_on_t * val)2109 int32_t iis2dlpc_act_mode_get(const stmdev_ctx_t *ctx,
2110 iis2dlpc_sleep_on_t *val)
2111 {
2112 iis2dlpc_wake_up_ths_t wake_up_ths;
2113 iis2dlpc_wake_up_dur_t wake_up_dur;;
2114 int32_t ret;
2115
2116 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_THS,
2117 (uint8_t *) &wake_up_ths, 1);
2118
2119 if (ret == 0)
2120 {
2121 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR,
2122 (uint8_t *) &wake_up_dur, 1);
2123
2124 switch ((wake_up_dur.stationary << 1) + wake_up_ths.sleep_on)
2125 {
2126 case IIS2DLPC_NO_DETECTION:
2127 *val = IIS2DLPC_NO_DETECTION;
2128 break;
2129
2130 case IIS2DLPC_DETECT_ACT_INACT:
2131 *val = IIS2DLPC_DETECT_ACT_INACT;
2132 break;
2133
2134 case IIS2DLPC_DETECT_STAT_MOTION:
2135 *val = IIS2DLPC_DETECT_STAT_MOTION;
2136 break;
2137
2138 default:
2139 *val = IIS2DLPC_NO_DETECTION;
2140 break;
2141 }
2142 }
2143
2144 return ret;
2145 }
2146
2147 /**
2148 * @brief Duration to go in sleep mode (1 LSb = 512 / ODR).[set]
2149 *
2150 * @param ctx read / write interface definitions
2151 * @param val change the values of sleep_dur in reg WAKE_UP_DUR
2152 * @retval interface status (MANDATORY: return 0 -> no Error)
2153 *
2154 */
iis2dlpc_act_sleep_dur_set(const stmdev_ctx_t * ctx,uint8_t val)2155 int32_t iis2dlpc_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
2156 {
2157 iis2dlpc_wake_up_dur_t reg;
2158 int32_t ret;
2159
2160 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR, (uint8_t *) ®, 1);
2161
2162 if (ret == 0)
2163 {
2164 reg.sleep_dur = val;
2165 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_WAKE_UP_DUR, (uint8_t *) ®, 1);
2166 }
2167
2168 return ret;
2169 }
2170
2171 /**
2172 * @brief Duration to go in sleep mode (1 LSb = 512 / ODR).[get]
2173 *
2174 * @param ctx read / write interface definitions
2175 * @param val change the values of sleep_dur in reg WAKE_UP_DUR
2176 * @retval interface status (MANDATORY: return 0 -> no Error)
2177 *
2178 */
iis2dlpc_act_sleep_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)2179 int32_t iis2dlpc_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
2180 {
2181 iis2dlpc_wake_up_dur_t reg;
2182 int32_t ret;
2183
2184 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR, (uint8_t *) ®, 1);
2185 *val = reg.sleep_dur;
2186
2187 return ret;
2188 }
2189
2190 /**
2191 * @}
2192 *
2193 */
2194
2195 /**
2196 * @defgroup IIS2DLPC_Tap_Generator
2197 * @brief This section groups all the functions that manage the tap
2198 * and double tap event generation.
2199 * @{
2200 *
2201 */
2202
2203 /**
2204 * @brief Threshold for tap recognition.[set]
2205 *
2206 * @param ctx read / write interface definitions
2207 * @param val change the values of tap_thsx in reg TAP_THS_X
2208 * @retval interface status (MANDATORY: return 0 -> no Error)
2209 *
2210 */
iis2dlpc_tap_threshold_x_set(const stmdev_ctx_t * ctx,uint8_t val)2211 int32_t iis2dlpc_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val)
2212 {
2213 iis2dlpc_tap_ths_x_t reg;
2214 int32_t ret;
2215
2216 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_X, (uint8_t *) ®, 1);
2217
2218 if (ret == 0)
2219 {
2220 reg.tap_thsx = val;
2221 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_X, (uint8_t *) ®, 1);
2222 }
2223
2224 return ret;
2225 }
2226
2227 /**
2228 * @brief Threshold for tap recognition.[get]
2229 *
2230 * @param ctx read / write interface definitions
2231 * @param val change the values of tap_thsx in reg TAP_THS_X
2232 * @retval interface status (MANDATORY: return 0 -> no Error)
2233 *
2234 */
iis2dlpc_tap_threshold_x_get(const stmdev_ctx_t * ctx,uint8_t * val)2235 int32_t iis2dlpc_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val)
2236 {
2237 iis2dlpc_tap_ths_x_t reg;
2238 int32_t ret;
2239
2240 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_X, (uint8_t *) ®, 1);
2241 *val = reg.tap_thsx;
2242
2243 return ret;
2244 }
2245
2246 /**
2247 * @brief Threshold for tap recognition.[set]
2248 *
2249 * @param ctx read / write interface definitions
2250 * @param val change the values of tap_thsy in reg TAP_THS_Y
2251 * @retval interface status (MANDATORY: return 0 -> no Error)
2252 *
2253 */
iis2dlpc_tap_threshold_y_set(const stmdev_ctx_t * ctx,uint8_t val)2254 int32_t iis2dlpc_tap_threshold_y_set(const stmdev_ctx_t *ctx, uint8_t val)
2255 {
2256 iis2dlpc_tap_ths_y_t reg;
2257 int32_t ret;
2258
2259 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Y, (uint8_t *) ®, 1);
2260
2261 if (ret == 0)
2262 {
2263 reg.tap_thsy = val;
2264 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_Y, (uint8_t *) ®, 1);
2265 }
2266
2267 return ret;
2268 }
2269
2270 /**
2271 * @brief Threshold for tap recognition.[get]
2272 *
2273 * @param ctx read / write interface definitions
2274 * @param val change the values of tap_thsy in reg TAP_THS_Y
2275 * @retval interface status (MANDATORY: return 0 -> no Error)
2276 *
2277 */
iis2dlpc_tap_threshold_y_get(const stmdev_ctx_t * ctx,uint8_t * val)2278 int32_t iis2dlpc_tap_threshold_y_get(const stmdev_ctx_t *ctx, uint8_t *val)
2279 {
2280 iis2dlpc_tap_ths_y_t reg;
2281 int32_t ret;
2282
2283 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Y, (uint8_t *) ®, 1);
2284 *val = reg.tap_thsy;
2285
2286 return ret;
2287 }
2288
2289 /**
2290 * @brief Selection of axis priority for TAP detection.[set]
2291 *
2292 * @param ctx read / write interface definitions
2293 * @param val change the values of tap_prior in reg TAP_THS_Y
2294 * @retval interface status (MANDATORY: return 0 -> no Error)
2295 *
2296 */
iis2dlpc_tap_axis_priority_set(const stmdev_ctx_t * ctx,iis2dlpc_tap_prior_t val)2297 int32_t iis2dlpc_tap_axis_priority_set(const stmdev_ctx_t *ctx,
2298 iis2dlpc_tap_prior_t val)
2299 {
2300 iis2dlpc_tap_ths_y_t reg;
2301 int32_t ret;
2302
2303 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Y, (uint8_t *) ®, 1);
2304
2305 if (ret == 0)
2306 {
2307 reg.tap_prior = (uint8_t) val;
2308 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_Y, (uint8_t *) ®, 1);
2309 }
2310
2311 return ret;
2312 }
2313
2314 /**
2315 * @brief Selection of axis priority for TAP detection.[get]
2316 *
2317 * @param ctx read / write interface definitions
2318 * @param val Get the values of tap_prior in reg TAP_THS_Y
2319 * @retval interface status (MANDATORY: return 0 -> no Error)
2320 *
2321 */
iis2dlpc_tap_axis_priority_get(const stmdev_ctx_t * ctx,iis2dlpc_tap_prior_t * val)2322 int32_t iis2dlpc_tap_axis_priority_get(const stmdev_ctx_t *ctx,
2323 iis2dlpc_tap_prior_t *val)
2324 {
2325 iis2dlpc_tap_ths_y_t reg;
2326 int32_t ret;
2327
2328 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Y, (uint8_t *) ®, 1);
2329
2330 switch (reg.tap_prior)
2331 {
2332 case IIS2DLPC_XYZ:
2333 *val = IIS2DLPC_XYZ;
2334 break;
2335
2336 case IIS2DLPC_YXZ:
2337 *val = IIS2DLPC_YXZ;
2338 break;
2339
2340 case IIS2DLPC_XZY:
2341 *val = IIS2DLPC_XZY;
2342 break;
2343
2344 case IIS2DLPC_ZYX:
2345 *val = IIS2DLPC_ZYX;
2346 break;
2347
2348 case IIS2DLPC_YZX:
2349 *val = IIS2DLPC_YZX;
2350 break;
2351
2352 case IIS2DLPC_ZXY:
2353 *val = IIS2DLPC_ZXY;
2354 break;
2355
2356 default:
2357 *val = IIS2DLPC_XYZ;
2358 break;
2359 }
2360
2361 return ret;
2362 }
2363
2364 /**
2365 * @brief Threshold for tap recognition.[set]
2366 *
2367 * @param ctx read / write interface definitions
2368 * @param val change the values of tap_thsz in reg TAP_THS_Z
2369 * @retval interface status (MANDATORY: return 0 -> no Error)
2370 *
2371 */
iis2dlpc_tap_threshold_z_set(const stmdev_ctx_t * ctx,uint8_t val)2372 int32_t iis2dlpc_tap_threshold_z_set(const stmdev_ctx_t *ctx, uint8_t val)
2373 {
2374 iis2dlpc_tap_ths_z_t reg;
2375 int32_t ret;
2376
2377 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z, (uint8_t *) ®, 1);
2378
2379 if (ret == 0)
2380 {
2381 reg.tap_thsz = val;
2382 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_Z, (uint8_t *) ®, 1);
2383 }
2384
2385 return ret;
2386 }
2387
2388 /**
2389 * @brief Threshold for tap recognition.[get]
2390 *
2391 * @param ctx read / write interface definitions
2392 * @param val change the values of tap_thsz in reg TAP_THS_Z
2393 * @retval interface status (MANDATORY: return 0 -> no Error)
2394 *
2395 */
iis2dlpc_tap_threshold_z_get(const stmdev_ctx_t * ctx,uint8_t * val)2396 int32_t iis2dlpc_tap_threshold_z_get(const stmdev_ctx_t *ctx, uint8_t *val)
2397 {
2398 iis2dlpc_tap_ths_z_t reg;
2399 int32_t ret;
2400
2401 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z, (uint8_t *) ®, 1);
2402 *val = reg.tap_thsz;
2403
2404 return ret;
2405 }
2406
2407 /**
2408 * @brief Enable Z direction in tap recognition.[set]
2409 *
2410 * @param ctx read / write interface definitions
2411 * @param val change the values of tap_z_en in reg TAP_THS_Z
2412 * @retval interface status (MANDATORY: return 0 -> no Error)
2413 *
2414 */
iis2dlpc_tap_detection_on_z_set(const stmdev_ctx_t * ctx,uint8_t val)2415 int32_t iis2dlpc_tap_detection_on_z_set(const stmdev_ctx_t *ctx,
2416 uint8_t val)
2417 {
2418 iis2dlpc_tap_ths_z_t reg;
2419 int32_t ret;
2420
2421 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z, (uint8_t *) ®, 1);
2422
2423 if (ret == 0)
2424 {
2425 reg.tap_z_en = val;
2426 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_Z, (uint8_t *) ®, 1);
2427 }
2428
2429 return ret;
2430 }
2431
2432 /**
2433 * @brief Enable Z direction in tap recognition.[get]
2434 *
2435 * @param ctx read / write interface definitions
2436 * @param val change the values of tap_z_en in reg TAP_THS_Z
2437 * @retval interface status (MANDATORY: return 0 -> no Error)
2438 *
2439 */
iis2dlpc_tap_detection_on_z_get(const stmdev_ctx_t * ctx,uint8_t * val)2440 int32_t iis2dlpc_tap_detection_on_z_get(const stmdev_ctx_t *ctx,
2441 uint8_t *val)
2442 {
2443 iis2dlpc_tap_ths_z_t reg;
2444 int32_t ret;
2445
2446 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z, (uint8_t *) ®, 1);
2447 *val = reg.tap_z_en;
2448
2449 return ret;
2450 }
2451
2452 /**
2453 * @brief Enable Y direction in tap recognition.[set]
2454 *
2455 * @param ctx read / write interface definitions
2456 * @param val change the values of tap_y_en in reg TAP_THS_Z
2457 * @retval interface status (MANDATORY: return 0 -> no Error)
2458 *
2459 */
iis2dlpc_tap_detection_on_y_set(const stmdev_ctx_t * ctx,uint8_t val)2460 int32_t iis2dlpc_tap_detection_on_y_set(const stmdev_ctx_t *ctx,
2461 uint8_t val)
2462 {
2463 iis2dlpc_tap_ths_z_t reg;
2464 int32_t ret;
2465
2466 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z, (uint8_t *) ®, 1);
2467
2468 if (ret == 0)
2469 {
2470 reg.tap_y_en = val;
2471 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_Z, (uint8_t *) ®, 1);
2472 }
2473
2474 return ret;
2475 }
2476
2477 /**
2478 * @brief Enable Y direction in tap recognition.[get]
2479 *
2480 * @param ctx read / write interface definitions
2481 * @param val change the values of tap_y_en in reg TAP_THS_Z
2482 * @retval interface status (MANDATORY: return 0 -> no Error)
2483 *
2484 */
iis2dlpc_tap_detection_on_y_get(const stmdev_ctx_t * ctx,uint8_t * val)2485 int32_t iis2dlpc_tap_detection_on_y_get(const stmdev_ctx_t *ctx,
2486 uint8_t *val)
2487 {
2488 iis2dlpc_tap_ths_z_t reg;
2489 int32_t ret;
2490
2491 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z, (uint8_t *) ®, 1);
2492 *val = reg.tap_y_en;
2493
2494 return ret;
2495 }
2496
2497 /**
2498 * @brief Enable X direction in tap recognition.[set]
2499 *
2500 * @param ctx read / write interface definitions
2501 * @param val change the values of tap_x_en in reg TAP_THS_Z
2502 * @retval interface status (MANDATORY: return 0 -> no Error)
2503 *
2504 */
iis2dlpc_tap_detection_on_x_set(const stmdev_ctx_t * ctx,uint8_t val)2505 int32_t iis2dlpc_tap_detection_on_x_set(const stmdev_ctx_t *ctx,
2506 uint8_t val)
2507 {
2508 iis2dlpc_tap_ths_z_t reg;
2509 int32_t ret;
2510
2511 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z, (uint8_t *) ®, 1);
2512
2513 if (ret == 0)
2514 {
2515 reg.tap_x_en = val;
2516 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_Z, (uint8_t *) ®, 1);
2517 }
2518
2519 return ret;
2520 }
2521
2522 /**
2523 * @brief Enable X direction in tap recognition.[get]
2524 *
2525 * @param ctx read / write interface definitions
2526 * @param val change the values of tap_x_en in reg TAP_THS_Z
2527 * @retval interface status (MANDATORY: return 0 -> no Error)
2528 *
2529 */
iis2dlpc_tap_detection_on_x_get(const stmdev_ctx_t * ctx,uint8_t * val)2530 int32_t iis2dlpc_tap_detection_on_x_get(const stmdev_ctx_t *ctx,
2531 uint8_t *val)
2532 {
2533 iis2dlpc_tap_ths_z_t reg;
2534 int32_t ret;
2535
2536 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z, (uint8_t *) ®, 1);
2537 *val = reg.tap_x_en;
2538
2539 return ret;
2540 }
2541
2542 /**
2543 * @brief Maximum duration is the maximum time of an overthreshold signal
2544 * detection to be recognized as a tap event. The default value
2545 * of these bits is 00b which corresponds to 4*ODR_XL time.
2546 * If the SHOCK[1:0] bits are set to a different value, 1LSB
2547 * corresponds to 8*ODR_XL time.[set]
2548 *
2549 * @param ctx read / write interface definitions
2550 * @param val change the values of shock in reg INT_DUR
2551 * @retval interface status (MANDATORY: return 0 -> no Error)
2552 *
2553 */
iis2dlpc_tap_shock_set(const stmdev_ctx_t * ctx,uint8_t val)2554 int32_t iis2dlpc_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val)
2555 {
2556 iis2dlpc_int_dur_t reg;
2557 int32_t ret;
2558
2559 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_INT_DUR, (uint8_t *) ®, 1);
2560
2561 if (ret == 0)
2562 {
2563 reg.shock = val;
2564 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_INT_DUR, (uint8_t *) ®, 1);
2565 }
2566
2567 return ret;
2568 }
2569
2570 /**
2571 * @brief Maximum duration is the maximum time of an overthreshold signal
2572 * detection to be recognized as a tap event. The default value
2573 * of these bits is 00b which corresponds to 4*ODR_XL time.
2574 * If the SHOCK[1:0] bits are set to a different value, 1LSB
2575 * corresponds to 8*ODR_XL time.[get]
2576 *
2577 * @param ctx read / write interface definitions
2578 * @param val change the values of shock in reg INT_DUR
2579 * @retval interface status (MANDATORY: return 0 -> no Error)
2580 *
2581 */
iis2dlpc_tap_shock_get(const stmdev_ctx_t * ctx,uint8_t * val)2582 int32_t iis2dlpc_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val)
2583 {
2584 iis2dlpc_int_dur_t reg;
2585 int32_t ret;
2586
2587 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_INT_DUR, (uint8_t *) ®, 1);
2588 *val = reg.shock;
2589
2590 return ret;
2591 }
2592
2593 /**
2594 * @brief Quiet time is the time after the first detected tap in which
2595 * there must not be any overthreshold event.
2596 * The default value of these bits is 00b which corresponds
2597 * to 2*ODR_XL time. If the QUIET[1:0] bits are set to a different
2598 * value, 1LSB corresponds to 4*ODR_XL time.[set]
2599 *
2600 * @param ctx read / write interface definitions
2601 * @param val change the values of quiet in reg INT_DUR
2602 * @retval interface status (MANDATORY: return 0 -> no Error)
2603 *
2604 */
iis2dlpc_tap_quiet_set(const stmdev_ctx_t * ctx,uint8_t val)2605 int32_t iis2dlpc_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val)
2606 {
2607 iis2dlpc_int_dur_t reg;
2608 int32_t ret;
2609
2610 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_INT_DUR, (uint8_t *) ®, 1);
2611
2612 if (ret == 0)
2613 {
2614 reg.quiet = val;
2615 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_INT_DUR, (uint8_t *) ®, 1);
2616 }
2617
2618 return ret;
2619 }
2620
2621 /**
2622 * @brief Quiet time is the time after the first detected tap in which
2623 * there must not be any overthreshold event.
2624 * The default value of these bits is 00b which corresponds
2625 * to 2*ODR_XL time. If the QUIET[1:0] bits are set to a different
2626 * value, 1LSB corresponds to 4*ODR_XL time.[get]
2627 *
2628 * @param ctx read / write interface definitions
2629 * @param val change the values of quiet in reg INT_DUR
2630 * @retval interface status (MANDATORY: return 0 -> no Error)
2631 *
2632 */
iis2dlpc_tap_quiet_get(const stmdev_ctx_t * ctx,uint8_t * val)2633 int32_t iis2dlpc_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val)
2634 {
2635 iis2dlpc_int_dur_t reg;
2636 int32_t ret;
2637
2638 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_INT_DUR, (uint8_t *) ®, 1);
2639 *val = reg.quiet;
2640
2641 return ret;
2642 }
2643
2644 /**
2645 * @brief When double tap recognition is enabled, this register expresses
2646 * the maximum time between two consecutive detected taps to
2647 * determine a double tap event.
2648 * The default value of these bits is 0000b which corresponds
2649 * to 16*ODR_XL time. If the DUR[3:0] bits are set to a different
2650 * value, 1LSB corresponds to 32*ODR_XL time.[set]
2651 *
2652 * @param ctx read / write interface definitions
2653 * @param val change the values of latency in reg INT_DUR
2654 * @retval interface status (MANDATORY: return 0 -> no Error)
2655 *
2656 */
iis2dlpc_tap_dur_set(const stmdev_ctx_t * ctx,uint8_t val)2657 int32_t iis2dlpc_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
2658 {
2659 iis2dlpc_int_dur_t reg;
2660 int32_t ret;
2661
2662 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_INT_DUR, (uint8_t *) ®, 1);
2663
2664 if (ret == 0)
2665 {
2666 reg.latency = val;
2667 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_INT_DUR, (uint8_t *) ®, 1);
2668 }
2669
2670 return ret;
2671 }
2672
2673 /**
2674 * @brief When double tap recognition is enabled, this register expresses
2675 * the maximum time between two consecutive detected taps to
2676 * determine a double tap event.
2677 * The default value of these bits is 0000b which corresponds
2678 * to 16*ODR_XL time. If the DUR[3:0] bits are set to a different
2679 * value, 1LSB corresponds to 32*ODR_XL time.[get]
2680 *
2681 * @param ctx read / write interface definitions
2682 * @param val change the values of latency in reg INT_DUR
2683 * @retval interface status (MANDATORY: return 0 -> no Error)
2684 *
2685 */
iis2dlpc_tap_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)2686 int32_t iis2dlpc_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
2687 {
2688 iis2dlpc_int_dur_t reg;
2689 int32_t ret;
2690
2691 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_INT_DUR, (uint8_t *) ®, 1);
2692 *val = reg.latency;
2693
2694 return ret;
2695 }
2696
2697 /**
2698 * @brief Single/double-tap event enable.[set]
2699 *
2700 * @param ctx read / write interface definitions
2701 * @param val change the values of single_double_tap in reg WAKE_UP_THS
2702 * @retval interface status (MANDATORY: return 0 -> no Error)
2703 *
2704 */
iis2dlpc_tap_mode_set(const stmdev_ctx_t * ctx,iis2dlpc_single_double_tap_t val)2705 int32_t iis2dlpc_tap_mode_set(const stmdev_ctx_t *ctx,
2706 iis2dlpc_single_double_tap_t val)
2707 {
2708 iis2dlpc_wake_up_ths_t reg;
2709 int32_t ret;
2710
2711 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_THS, (uint8_t *) ®, 1);
2712
2713 if (ret == 0)
2714 {
2715 reg.single_double_tap = (uint8_t) val;
2716 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_WAKE_UP_THS, (uint8_t *) ®, 1);
2717 }
2718
2719 return ret;
2720 }
2721
2722 /**
2723 * @brief Single/double-tap event enable.[get]
2724 *
2725 * @param ctx read / write interface definitions
2726 * @param val Get the values of single_double_tap in reg WAKE_UP_THS
2727 * @retval interface status (MANDATORY: return 0 -> no Error)
2728 *
2729 */
iis2dlpc_tap_mode_get(const stmdev_ctx_t * ctx,iis2dlpc_single_double_tap_t * val)2730 int32_t iis2dlpc_tap_mode_get(const stmdev_ctx_t *ctx,
2731 iis2dlpc_single_double_tap_t *val)
2732 {
2733 iis2dlpc_wake_up_ths_t reg;
2734 int32_t ret;
2735
2736 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_THS, (uint8_t *) ®, 1);
2737
2738 switch (reg.single_double_tap)
2739 {
2740 case IIS2DLPC_ONLY_SINGLE:
2741 *val = IIS2DLPC_ONLY_SINGLE;
2742 break;
2743
2744 case IIS2DLPC_BOTH_SINGLE_DOUBLE:
2745 *val = IIS2DLPC_BOTH_SINGLE_DOUBLE;
2746 break;
2747
2748 default:
2749 *val = IIS2DLPC_ONLY_SINGLE;
2750 break;
2751 }
2752
2753 return ret;
2754 }
2755
2756 /**
2757 * @brief Read the tap / double tap source register.[get]
2758 *
2759 * @param ctx read / write interface definitions
2760 * @param iis2dlpc_tap_src: union of registers from TAP_SRC to
2761 * @retval interface status (MANDATORY: return 0 -> no Error)
2762 *
2763 */
iis2dlpc_tap_src_get(const stmdev_ctx_t * ctx,iis2dlpc_tap_src_t * val)2764 int32_t iis2dlpc_tap_src_get(const stmdev_ctx_t *ctx,
2765 iis2dlpc_tap_src_t *val)
2766 {
2767 int32_t ret;
2768
2769 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_SRC, (uint8_t *) val, 1);
2770
2771 return ret;
2772 }
2773
2774 /**
2775 * @}
2776 *
2777 */
2778
2779 /**
2780 * @defgroup IIS2DLPC_Six_Position_Detection(6D/4D)
2781 * @brief This section groups all the functions concerning six
2782 * position detection (6D).
2783 * @{
2784 *
2785 */
2786
2787 /**
2788 * @brief Threshold for 4D/6D function.[set]
2789 *
2790 * @param ctx read / write interface definitions
2791 * @param val change the values of 6d_ths in reg TAP_THS_X
2792 * @retval interface status (MANDATORY: return 0 -> no Error)
2793 *
2794 */
iis2dlpc_6d_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)2795 int32_t iis2dlpc_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
2796 {
2797 iis2dlpc_tap_ths_x_t reg;
2798 int32_t ret;
2799
2800 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_X, (uint8_t *) ®, 1);
2801
2802 if (ret == 0)
2803 {
2804 reg._6d_ths = val;
2805 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_X, (uint8_t *) ®, 1);
2806 }
2807
2808 return ret;
2809 }
2810
2811 /**
2812 * @brief Threshold for 4D/6D function.[get]
2813 *
2814 * @param ctx read / write interface definitions
2815 * @param val change the values of 6d_ths in reg TAP_THS_X
2816 * @retval interface status (MANDATORY: return 0 -> no Error)
2817 *
2818 */
iis2dlpc_6d_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)2819 int32_t iis2dlpc_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
2820 {
2821 iis2dlpc_tap_ths_x_t reg;
2822 int32_t ret;
2823
2824 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_X, (uint8_t *) ®, 1);
2825 *val = reg._6d_ths;
2826
2827 return ret;
2828 }
2829
2830 /**
2831 * @brief 4D orientation detection enable.[set]
2832 *
2833 * @param ctx read / write interface definitions
2834 * @param val change the values of 4d_en in reg TAP_THS_X
2835 * @retval interface status (MANDATORY: return 0 -> no Error)
2836 *
2837 */
iis2dlpc_4d_mode_set(const stmdev_ctx_t * ctx,uint8_t val)2838 int32_t iis2dlpc_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
2839 {
2840 iis2dlpc_tap_ths_x_t reg;
2841 int32_t ret;
2842
2843 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_X, (uint8_t *) ®, 1);
2844
2845 if (ret == 0)
2846 {
2847 reg._4d_en = val;
2848 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_X, (uint8_t *) ®, 1);
2849 }
2850
2851 return ret;
2852 }
2853
2854 /**
2855 * @brief 4D orientation detection enable.[get]
2856 *
2857 * @param ctx read / write interface definitions
2858 * @param val change the values of 4d_en in reg TAP_THS_X
2859 * @retval interface status (MANDATORY: return 0 -> no Error)
2860 *
2861 */
iis2dlpc_4d_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)2862 int32_t iis2dlpc_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
2863 {
2864 iis2dlpc_tap_ths_x_t reg;
2865 int32_t ret;
2866
2867 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_X, (uint8_t *) ®, 1);
2868 *val = reg._4d_en;
2869
2870 return ret;
2871 }
2872
2873 /**
2874 * @brief Read the 6D tap source register.[get]
2875 *
2876 * @param ctx read / write interface definitions
2877 * @param val union of registers from SIXD_SRC
2878 * @retval interface status (MANDATORY: return 0 -> no Error)
2879 *
2880 */
iis2dlpc_6d_src_get(const stmdev_ctx_t * ctx,iis2dlpc_sixd_src_t * val)2881 int32_t iis2dlpc_6d_src_get(const stmdev_ctx_t *ctx,
2882 iis2dlpc_sixd_src_t *val)
2883 {
2884 int32_t ret;
2885
2886 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_SIXD_SRC, (uint8_t *) val, 1);
2887
2888 return ret;
2889 }
2890 /**
2891 * @brief Data sent to 6D interrupt function.[set]
2892 *
2893 * @param ctx read / write interface definitions
2894 * @param val change the values of lpass_on6d in reg CTRL_REG7
2895 * @retval interface status (MANDATORY: return 0 -> no Error)
2896 *
2897 */
iis2dlpc_6d_feed_data_set(const stmdev_ctx_t * ctx,iis2dlpc_lpass_on6d_t val)2898 int32_t iis2dlpc_6d_feed_data_set(const stmdev_ctx_t *ctx,
2899 iis2dlpc_lpass_on6d_t val)
2900 {
2901 iis2dlpc_ctrl7_t reg;
2902 int32_t ret;
2903
2904 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1);
2905
2906 if (ret == 0)
2907 {
2908 reg.lpass_on6d = (uint8_t) val;
2909 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1);
2910 }
2911
2912 return ret;
2913 }
2914
2915 /**
2916 * @brief Data sent to 6D interrupt function.[get]
2917 *
2918 * @param ctx read / write interface definitions
2919 * @param val Get the values of lpass_on6d in reg CTRL_REG7
2920 * @retval interface status (MANDATORY: return 0 -> no Error)
2921 *
2922 */
iis2dlpc_6d_feed_data_get(const stmdev_ctx_t * ctx,iis2dlpc_lpass_on6d_t * val)2923 int32_t iis2dlpc_6d_feed_data_get(const stmdev_ctx_t *ctx,
2924 iis2dlpc_lpass_on6d_t *val)
2925 {
2926 iis2dlpc_ctrl7_t reg;
2927 int32_t ret;
2928
2929 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1);
2930
2931 switch (reg.lpass_on6d)
2932 {
2933 case IIS2DLPC_ODR_DIV_2_FEED:
2934 *val = IIS2DLPC_ODR_DIV_2_FEED;
2935 break;
2936
2937 case IIS2DLPC_LPF2_FEED:
2938 *val = IIS2DLPC_LPF2_FEED;
2939 break;
2940
2941 default:
2942 *val = IIS2DLPC_ODR_DIV_2_FEED;
2943 break;
2944 }
2945
2946 return ret;
2947 }
2948
2949 /**
2950 * @}
2951 *
2952 */
2953
2954 /**
2955 * @defgroup IIS2DLPC_Free_Fall
2956 * @brief This section group all the functions concerning
2957 * the free fall detection.
2958 * @{
2959 *
2960 */
2961
2962 /**
2963 * @brief Wake up duration event(1LSb = 1 / ODR).[set]
2964 *
2965 * @param ctx read / write interface definitions
2966 * @param val change the values of ff_dur in reg
2967 * WAKE_UP_DUR /F REE_FALL
2968 * @retval interface status (MANDATORY: return 0 -> no Error)
2969 *
2970 */
iis2dlpc_ff_dur_set(const stmdev_ctx_t * ctx,uint8_t val)2971 int32_t iis2dlpc_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
2972 {
2973 iis2dlpc_wake_up_dur_t wake_up_dur;
2974 iis2dlpc_free_fall_t free_fall;
2975 int32_t ret;
2976
2977 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR,
2978 (uint8_t *) &wake_up_dur, 1);
2979
2980 if (ret == 0)
2981 {
2982 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FREE_FALL,
2983 (uint8_t *) &free_fall, 1);
2984 }
2985
2986 if (ret == 0)
2987 {
2988 wake_up_dur.ff_dur = ((uint8_t) val & 0x20U) >> 5;
2989 free_fall.ff_dur = (uint8_t) val & 0x1FU;
2990 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_WAKE_UP_DUR,
2991 (uint8_t *) &wake_up_dur, 1);
2992 }
2993
2994 if (ret == 0)
2995 {
2996 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_FREE_FALL,
2997 (uint8_t *) &free_fall, 1);
2998 }
2999
3000 return ret;
3001 }
3002
3003 /**
3004 * @brief Wake up duration event(1LSb = 1 / ODR).[get]
3005 *
3006 * @param ctx read / write interface definitions
3007 * @param val change the values of ff_dur in
3008 * reg WAKE_UP_DUR /F REE_FALL
3009 * @retval interface status (MANDATORY: return 0 -> no Error)
3010 *
3011 */
iis2dlpc_ff_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)3012 int32_t iis2dlpc_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
3013 {
3014 iis2dlpc_wake_up_dur_t wake_up_dur;
3015 iis2dlpc_free_fall_t free_fall;
3016 int32_t ret;
3017
3018 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR,
3019 (uint8_t *) &wake_up_dur, 1);
3020
3021 if (ret == 0)
3022 {
3023 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FREE_FALL,
3024 (uint8_t *) &free_fall, 1);
3025 *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
3026 }
3027
3028 return ret;
3029 }
3030
3031 /**
3032 * @brief Free fall threshold setting.[set]
3033 *
3034 * @param ctx read / write interface definitions
3035 * @param val change the values of ff_ths in reg FREE_FALL
3036 * @retval interface status (MANDATORY: return 0 -> no Error)
3037 *
3038 */
iis2dlpc_ff_threshold_set(const stmdev_ctx_t * ctx,iis2dlpc_ff_ths_t val)3039 int32_t iis2dlpc_ff_threshold_set(const stmdev_ctx_t *ctx,
3040 iis2dlpc_ff_ths_t val)
3041 {
3042 iis2dlpc_free_fall_t reg;
3043 int32_t ret;
3044
3045 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FREE_FALL, (uint8_t *) ®, 1);
3046
3047 if (ret == 0)
3048 {
3049 reg.ff_ths = (uint8_t) val;
3050 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_FREE_FALL, (uint8_t *) ®, 1);
3051 }
3052
3053 return ret;
3054 }
3055
3056 /**
3057 * @brief Free fall threshold setting.[get]
3058 *
3059 * @param ctx read / write interface definitions
3060 * @param val Get the values of ff_ths in reg FREE_FALL
3061 * @retval interface status (MANDATORY: return 0 -> no Error)
3062 *
3063 */
iis2dlpc_ff_threshold_get(const stmdev_ctx_t * ctx,iis2dlpc_ff_ths_t * val)3064 int32_t iis2dlpc_ff_threshold_get(const stmdev_ctx_t *ctx,
3065 iis2dlpc_ff_ths_t *val)
3066 {
3067 iis2dlpc_free_fall_t reg;
3068 int32_t ret;
3069
3070 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FREE_FALL, (uint8_t *) ®, 1);
3071
3072 switch (reg.ff_ths)
3073 {
3074 case IIS2DLPC_FF_TSH_5LSb_FS2g:
3075 *val = IIS2DLPC_FF_TSH_5LSb_FS2g;
3076 break;
3077
3078 case IIS2DLPC_FF_TSH_7LSb_FS2g:
3079 *val = IIS2DLPC_FF_TSH_7LSb_FS2g;
3080 break;
3081
3082 case IIS2DLPC_FF_TSH_8LSb_FS2g:
3083 *val = IIS2DLPC_FF_TSH_8LSb_FS2g;
3084 break;
3085
3086 case IIS2DLPC_FF_TSH_10LSb_FS2g:
3087 *val = IIS2DLPC_FF_TSH_10LSb_FS2g;
3088 break;
3089
3090 case IIS2DLPC_FF_TSH_11LSb_FS2g:
3091 *val = IIS2DLPC_FF_TSH_11LSb_FS2g;
3092 break;
3093
3094 case IIS2DLPC_FF_TSH_13LSb_FS2g:
3095 *val = IIS2DLPC_FF_TSH_13LSb_FS2g;
3096 break;
3097
3098 case IIS2DLPC_FF_TSH_15LSb_FS2g:
3099 *val = IIS2DLPC_FF_TSH_15LSb_FS2g;
3100 break;
3101
3102 case IIS2DLPC_FF_TSH_16LSb_FS2g:
3103 *val = IIS2DLPC_FF_TSH_16LSb_FS2g;
3104 break;
3105
3106 default:
3107 *val = IIS2DLPC_FF_TSH_5LSb_FS2g;
3108 break;
3109 }
3110
3111 return ret;
3112 }
3113
3114 /**
3115 * @}
3116 *
3117 */
3118
3119 /**
3120 * @defgroup IIS2DLPC_Fifo
3121 * @brief This section group all the functions concerning the fifo usage
3122 * @{
3123 *
3124 */
3125
3126 /**
3127 * @brief FIFO watermark level selection.[set]
3128 *
3129 * @param ctx read / write interface definitions
3130 * @param val change the values of fth in reg FIFO_CTRL
3131 * @retval interface status (MANDATORY: return 0 -> no Error)
3132 *
3133 */
iis2dlpc_fifo_watermark_set(const stmdev_ctx_t * ctx,uint8_t val)3134 int32_t iis2dlpc_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val)
3135 {
3136 iis2dlpc_fifo_ctrl_t reg;
3137 int32_t ret;
3138
3139 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_CTRL, (uint8_t *) ®, 1);
3140
3141 if (ret == 0)
3142 {
3143 reg.fth = val;
3144 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_FIFO_CTRL, (uint8_t *) ®, 1);
3145 }
3146
3147 return ret;
3148 }
3149
3150 /**
3151 * @brief FIFO watermark level selection.[get]
3152 *
3153 * @param ctx read / write interface definitions
3154 * @param val change the values of fth in reg FIFO_CTRL
3155 * @retval interface status (MANDATORY: return 0 -> no Error)
3156 *
3157 */
iis2dlpc_fifo_watermark_get(const stmdev_ctx_t * ctx,uint8_t * val)3158 int32_t iis2dlpc_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val)
3159 {
3160 iis2dlpc_fifo_ctrl_t reg;
3161 int32_t ret;
3162
3163 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_CTRL, (uint8_t *) ®, 1);
3164 *val = reg.fth;
3165
3166 return ret;
3167 }
3168
3169 /**
3170 * @brief FIFO mode selection.[set]
3171 *
3172 * @param ctx read / write interface definitions
3173 * @param val change the values of fmode in reg FIFO_CTRL
3174 * @retval interface status (MANDATORY: return 0 -> no Error)
3175 *
3176 */
iis2dlpc_fifo_mode_set(const stmdev_ctx_t * ctx,iis2dlpc_fmode_t val)3177 int32_t iis2dlpc_fifo_mode_set(const stmdev_ctx_t *ctx,
3178 iis2dlpc_fmode_t val)
3179 {
3180 iis2dlpc_fifo_ctrl_t reg;
3181 int32_t ret;
3182
3183 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_CTRL, (uint8_t *) ®, 1);
3184
3185 if (ret == 0)
3186 {
3187 reg.fmode = (uint8_t) val;
3188 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_FIFO_CTRL, (uint8_t *) ®, 1);
3189 }
3190
3191 return ret;
3192 }
3193
3194 /**
3195 * @brief FIFO mode selection.[get]
3196 *
3197 * @param ctx read / write interface definitions
3198 * @param val Get the values of fmode in reg FIFO_CTRL
3199 * @retval interface status (MANDATORY: return 0 -> no Error)
3200 *
3201 */
iis2dlpc_fifo_mode_get(const stmdev_ctx_t * ctx,iis2dlpc_fmode_t * val)3202 int32_t iis2dlpc_fifo_mode_get(const stmdev_ctx_t *ctx,
3203 iis2dlpc_fmode_t *val)
3204 {
3205 iis2dlpc_fifo_ctrl_t reg;
3206 int32_t ret;
3207
3208 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_CTRL, (uint8_t *) ®, 1);
3209
3210 switch (reg.fmode)
3211 {
3212 case IIS2DLPC_BYPASS_MODE:
3213 *val = IIS2DLPC_BYPASS_MODE;
3214 break;
3215
3216 case IIS2DLPC_FIFO_MODE:
3217 *val = IIS2DLPC_FIFO_MODE;
3218 break;
3219
3220 case IIS2DLPC_STREAM_TO_FIFO_MODE:
3221 *val = IIS2DLPC_STREAM_TO_FIFO_MODE;
3222 break;
3223
3224 case IIS2DLPC_BYPASS_TO_STREAM_MODE:
3225 *val = IIS2DLPC_BYPASS_TO_STREAM_MODE;
3226 break;
3227
3228 case IIS2DLPC_STREAM_MODE:
3229 *val = IIS2DLPC_STREAM_MODE;
3230 break;
3231
3232 default:
3233 *val = IIS2DLPC_BYPASS_MODE;
3234 break;
3235 }
3236
3237 return ret;
3238 }
3239
3240 /**
3241 * @brief Number of unread samples stored in FIFO.[get]
3242 *
3243 * @param ctx read / write interface definitions
3244 * @param val change the values of diff in reg FIFO_SAMPLES
3245 * @retval interface status (MANDATORY: return 0 -> no Error)
3246 *
3247 */
iis2dlpc_fifo_data_level_get(const stmdev_ctx_t * ctx,uint8_t * val)3248 int32_t iis2dlpc_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val)
3249 {
3250 iis2dlpc_fifo_samples_t reg;
3251 int32_t ret;
3252
3253 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_SAMPLES, (uint8_t *) ®, 1);
3254 *val = reg.diff;
3255
3256 return ret;
3257 }
3258 /**
3259 * @brief FIFO overrun status.[get]
3260 *
3261 * @param ctx read / write interface definitions
3262 * @param val change the values of fifo_ovr in reg FIFO_SAMPLES
3263 * @retval interface status (MANDATORY: return 0 -> no Error)
3264 *
3265 */
iis2dlpc_fifo_ovr_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)3266 int32_t iis2dlpc_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
3267 {
3268 iis2dlpc_fifo_samples_t reg;
3269 int32_t ret;
3270
3271 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_SAMPLES, (uint8_t *) ®, 1);
3272 *val = reg.fifo_ovr;
3273
3274 return ret;
3275 }
3276 /**
3277 * @brief FIFO threshold status flag.[get]
3278 *
3279 * @param ctx read / write interface definitions
3280 * @param val change the values of fifo_fth in reg FIFO_SAMPLES
3281 * @retval interface status (MANDATORY: return 0 -> no Error)
3282 *
3283 */
iis2dlpc_fifo_wtm_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)3284 int32_t iis2dlpc_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
3285 {
3286 iis2dlpc_fifo_samples_t reg;
3287 int32_t ret;
3288
3289 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_SAMPLES, (uint8_t *) ®, 1);
3290 *val = reg.fifo_fth;
3291
3292 return ret;
3293 }
3294 /**
3295 * @}
3296 *
3297 */
3298
3299 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
3300
