1 /**
2 ******************************************************************************
3 * @file iis2dh_reg.c
4 * @author Sensors Software Solution Team
5 * @brief IIS2DH driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "iis2dh_reg.h"
21
22 /**
23 * @defgroup IIS2DH
24 * @brief This file provides a set of functions needed to drive the
25 * iis2dh enanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup IIS2DH_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
iis2dh_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak iis2dh_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
50 uint16_t len)
51 {
52 int32_t ret;
53
54 if (ctx == NULL) return -1;
55
56 ret = ctx->read_reg(ctx->handle, reg, data, len);
57
58 return ret;
59 }
60
61 /**
62 * @brief Write generic device register
63 *
64 * @param ctx read / write interface definitions(ptr)
65 * @param reg register to write
66 * @param data pointer to data to write in register reg(ptr)
67 * @param len number of consecutive register to write
68 * @retval interface status (MANDATORY: return 0 -> no Error)
69 *
70 */
iis2dh_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)71 int32_t __weak iis2dh_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
72 uint8_t *data,
73 uint16_t len)
74 {
75 int32_t ret;
76
77 if (ctx == NULL) return -1;
78
79 ret = ctx->write_reg(ctx->handle, reg, data, len);
80
81 return ret;
82 }
83
84 /**
85 * @}
86 *
87 */
88
89 /**
90 * @defgroup IIS2DH_Sensitivity
91 * @brief These functions convert raw-data into engineering units.
92 * @{
93 *
94 */
95
iis2dh_from_fs2_hr_to_mg(int16_t lsb)96 float_t iis2dh_from_fs2_hr_to_mg(int16_t lsb)
97 {
98 return ((float_t)lsb / 16.0f) * 0.98f;
99 }
100
iis2dh_from_fs4_hr_to_mg(int16_t lsb)101 float_t iis2dh_from_fs4_hr_to_mg(int16_t lsb)
102 {
103 return ((float_t)lsb / 16.0f) * 1.95f;
104 }
105
iis2dh_from_fs8_hr_to_mg(int16_t lsb)106 float_t iis2dh_from_fs8_hr_to_mg(int16_t lsb)
107 {
108 return ((float_t)lsb / 16.0f) * 3.91f;
109 }
110
iis2dh_from_fs16_hr_to_mg(int16_t lsb)111 float_t iis2dh_from_fs16_hr_to_mg(int16_t lsb)
112 {
113 return ((float_t)lsb / 16.0f) * 11.72f;
114 }
115
iis2dh_from_lsb_hr_to_celsius(int16_t lsb)116 float_t iis2dh_from_lsb_hr_to_celsius(int16_t lsb)
117 {
118 return (((float_t)lsb / 64.0f) / 4.0f) + 25.0f;
119 }
120
iis2dh_from_fs2_nm_to_mg(int16_t lsb)121 float_t iis2dh_from_fs2_nm_to_mg(int16_t lsb)
122 {
123 return ((float_t)lsb / 64.0f) * 3.91f;
124 }
125
iis2dh_from_fs4_nm_to_mg(int16_t lsb)126 float_t iis2dh_from_fs4_nm_to_mg(int16_t lsb)
127 {
128 return ((float_t)lsb / 64.0f) * 7.81f;
129 }
130
iis2dh_from_fs8_nm_to_mg(int16_t lsb)131 float_t iis2dh_from_fs8_nm_to_mg(int16_t lsb)
132 {
133 return ((float_t)lsb / 64.0f) * 15.63f;
134 }
135
iis2dh_from_fs16_nm_to_mg(int16_t lsb)136 float_t iis2dh_from_fs16_nm_to_mg(int16_t lsb)
137 {
138 return ((float_t)lsb / 64.0f) * 46.95f;
139 }
140
iis2dh_from_lsb_nm_to_celsius(int16_t lsb)141 float_t iis2dh_from_lsb_nm_to_celsius(int16_t lsb)
142 {
143 return (((float_t)lsb / 64.0f) / 4.0f) + 25.0f;
144 }
145
iis2dh_from_fs2_lp_to_mg(int16_t lsb)146 float_t iis2dh_from_fs2_lp_to_mg(int16_t lsb)
147 {
148 return ((float_t)lsb / 256.0f) * 15.63f;
149 }
150
iis2dh_from_fs4_lp_to_mg(int16_t lsb)151 float_t iis2dh_from_fs4_lp_to_mg(int16_t lsb)
152 {
153 return ((float_t)lsb / 256.0f) * 31.25f;
154 }
155
iis2dh_from_fs8_lp_to_mg(int16_t lsb)156 float_t iis2dh_from_fs8_lp_to_mg(int16_t lsb)
157 {
158 return ((float_t)lsb / 256.0f) * 62.5f;
159 }
160
iis2dh_from_fs16_lp_to_mg(int16_t lsb)161 float_t iis2dh_from_fs16_lp_to_mg(int16_t lsb)
162 {
163 return ((float_t)lsb / 256.0f) * 188.68f;
164 }
165
iis2dh_from_lsb_lp_to_celsius(int16_t lsb)166 float_t iis2dh_from_lsb_lp_to_celsius(int16_t lsb)
167 {
168 return (((float_t)lsb / 256.0f) * 1.0f) + 25.0f;
169 }
170
171 /**
172 * @}
173 *
174 */
175
176 /**
177 * @defgroup IIS2DH_Data_generation
178 * @brief This section group all the functions concerning data generation.
179 * @{
180 *
181 */
182
183 /**
184 * @brief Temperature status register.[get]
185 *
186 * @param ctx read / write interface definitions
187 * @param buff buffer that stores data read
188 * @retval interface status (MANDATORY: return 0 -> no Error)
189 *
190 */
iis2dh_temp_status_reg_get(const stmdev_ctx_t * ctx,uint8_t * buff)191 int32_t iis2dh_temp_status_reg_get(const stmdev_ctx_t *ctx, uint8_t *buff)
192 {
193 int32_t ret;
194
195 ret = iis2dh_read_reg(ctx, IIS2DH_STATUS_REG_AUX, buff, 1);
196
197 return ret;
198 }
199 /**
200 * @brief Temperature data available.[get]
201 *
202 * @param ctx read / write interface definitions
203 * @param val change the values of tda in reg STATUS_REG_AUX
204 * @retval interface status (MANDATORY: return 0 -> no Error)
205 *
206 */
iis2dh_temp_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)207 int32_t iis2dh_temp_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val)
208 {
209 iis2dh_status_reg_aux_t status_reg_aux;
210 int32_t ret;
211
212 ret = iis2dh_read_reg(ctx, IIS2DH_STATUS_REG_AUX,
213 (uint8_t *)&status_reg_aux, 1);
214 *val = status_reg_aux.tda;
215
216 return ret;
217 }
218 /**
219 * @brief Temperature data overrun.[get]
220 *
221 * @param ctx read / write interface definitions
222 * @param val change the values of tor in reg STATUS_REG_AUX
223 * @retval interface status (MANDATORY: return 0 -> no Error)
224 *
225 */
iis2dh_temp_data_ovr_get(const stmdev_ctx_t * ctx,uint8_t * val)226 int32_t iis2dh_temp_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val)
227 {
228 iis2dh_status_reg_aux_t status_reg_aux;
229 int32_t ret;
230
231 ret = iis2dh_read_reg(ctx, IIS2DH_STATUS_REG_AUX,
232 (uint8_t *)&status_reg_aux, 1);
233 *val = status_reg_aux.tor;
234
235 return ret;
236 }
237 /**
238 * @brief Temperature output value.[get]
239 *
240 * @param ctx read / write interface definitions
241 * @param buff buffer that stores data read
242 * @retval interface status (MANDATORY: return 0 -> no Error)
243 *
244 */
iis2dh_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * val)245 int32_t iis2dh_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
246 {
247 uint8_t buff[2];
248 int32_t ret;
249
250 ret = iis2dh_read_reg(ctx, IIS2DH_OUT_TEMP_L, buff, 2);
251 *val = (int16_t)buff[1];
252 *val = (*val * 256) + (int16_t)buff[0];
253
254 return ret;
255 }
256 /**
257 * @brief Temperature sensor enable.[set]
258 *
259 * @param ctx read / write interface definitions
260 * @param val change the values of temp_en in reg TEMP_CFG_REG
261 * @retval interface status (MANDATORY: return 0 -> no Error)
262 *
263 */
iis2dh_temperature_meas_set(const stmdev_ctx_t * ctx,iis2dh_temp_en_t val)264 int32_t iis2dh_temperature_meas_set(const stmdev_ctx_t *ctx,
265 iis2dh_temp_en_t val)
266 {
267 iis2dh_temp_cfg_reg_t temp_cfg_reg;
268 int32_t ret;
269
270 ret = iis2dh_read_reg(ctx, IIS2DH_TEMP_CFG_REG,
271 (uint8_t *)&temp_cfg_reg, 1);
272
273 if (ret == 0)
274 {
275 temp_cfg_reg.temp_en = (uint8_t) val;
276 ret = iis2dh_write_reg(ctx, IIS2DH_TEMP_CFG_REG,
277 (uint8_t *)&temp_cfg_reg, 1);
278 }
279
280 return ret;
281 }
282
283 /**
284 * @brief Temperature sensor enable.[get]
285 *
286 * @param ctx read / write interface definitions
287 * @param val get the values of temp_en in reg TEMP_CFG_REG
288 * @retval interface status (MANDATORY: return 0 -> no Error)
289 *
290 */
iis2dh_temperature_meas_get(const stmdev_ctx_t * ctx,iis2dh_temp_en_t * val)291 int32_t iis2dh_temperature_meas_get(const stmdev_ctx_t *ctx,
292 iis2dh_temp_en_t *val)
293 {
294 iis2dh_temp_cfg_reg_t temp_cfg_reg;
295 int32_t ret;
296
297 ret = iis2dh_read_reg(ctx, IIS2DH_TEMP_CFG_REG,
298 (uint8_t *)&temp_cfg_reg, 1);
299
300 switch (temp_cfg_reg.temp_en)
301 {
302 case IIS2DH_TEMP_DISABLE:
303 *val = IIS2DH_TEMP_DISABLE;
304 break;
305
306 case IIS2DH_TEMP_ENABLE:
307 *val = IIS2DH_TEMP_ENABLE;
308 break;
309
310 default:
311 *val = IIS2DH_TEMP_DISABLE;
312 break;
313 }
314
315 return ret;
316 }
317
318 /**
319 * @brief Operating mode selection.[set]
320 *
321 * @param ctx read / write interface definitions
322 * @param val change the values of lpen in reg CTRL_REG1
323 * and HR in reg CTRL_REG4
324 * @retval interface status (MANDATORY: return 0 -> no Error)
325 *
326 */
iis2dh_operating_mode_set(const stmdev_ctx_t * ctx,iis2dh_op_md_t val)327 int32_t iis2dh_operating_mode_set(const stmdev_ctx_t *ctx,
328 iis2dh_op_md_t val)
329 {
330 iis2dh_ctrl_reg1_t ctrl_reg1;
331 iis2dh_ctrl_reg4_t ctrl_reg4;
332 int32_t ret;
333
334 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
335
336 if (ret == 0)
337 {
338 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
339 }
340
341 if (ret == 0)
342 {
343 if (val == IIS2DH_HR_12bit)
344 {
345 ctrl_reg1.lpen = 0;
346 ctrl_reg4.hr = 1;
347 }
348
349 if (val == IIS2DH_NM_10bit)
350 {
351 ctrl_reg1.lpen = 0;
352 ctrl_reg4.hr = 0;
353 }
354
355 if (val == IIS2DH_LP_8bit)
356 {
357 ctrl_reg1.lpen = 1;
358 ctrl_reg4.hr = 0;
359 }
360
361 ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
362 }
363
364 if (ret == 0)
365 {
366 ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
367 }
368
369 return ret;
370 }
371
372 /**
373 * @brief Operating mode selection.[get]
374 *
375 * @param ctx read / write interface definitions
376 * @param val change the values of lpen in reg CTRL_REG1
377 * @retval interface status (MANDATORY: return 0 -> no Error)
378 *
379 */
iis2dh_operating_mode_get(const stmdev_ctx_t * ctx,iis2dh_op_md_t * val)380 int32_t iis2dh_operating_mode_get(const stmdev_ctx_t *ctx,
381 iis2dh_op_md_t *val)
382 {
383 iis2dh_ctrl_reg1_t ctrl_reg1;
384 iis2dh_ctrl_reg4_t ctrl_reg4;
385 int32_t ret;
386
387 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
388
389 if (ret == 0)
390 {
391 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
392
393 if (ctrl_reg1.lpen == PROPERTY_ENABLE)
394 {
395 *val = IIS2DH_LP_8bit;
396 }
397
398 else if (ctrl_reg4.hr == PROPERTY_ENABLE)
399 {
400 *val = IIS2DH_HR_12bit;
401 }
402
403 else
404 {
405 *val = IIS2DH_NM_10bit;
406 }
407 }
408
409 return ret;
410 }
411
412 /**
413 * @brief Output data rate selection.[set]
414 *
415 * @param ctx read / write interface definitions
416 * @param val change the values of odr in reg CTRL_REG1
417 * @retval interface status (MANDATORY: return 0 -> no Error)
418 *
419 */
iis2dh_data_rate_set(const stmdev_ctx_t * ctx,iis2dh_odr_t val)420 int32_t iis2dh_data_rate_set(const stmdev_ctx_t *ctx, iis2dh_odr_t val)
421 {
422 iis2dh_ctrl_reg1_t ctrl_reg1;
423 int32_t ret;
424
425 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
426
427 if (ret == 0)
428 {
429 ctrl_reg1.odr = (uint8_t)val;
430 ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
431 }
432
433 return ret;
434 }
435
436 /**
437 * @brief Output data rate selection.[get]
438 *
439 * @param ctx read / write interface definitions
440 * @param val get the values of odr in reg CTRL_REG1
441 * @retval interface status (MANDATORY: return 0 -> no Error)
442 *
443 */
iis2dh_data_rate_get(const stmdev_ctx_t * ctx,iis2dh_odr_t * val)444 int32_t iis2dh_data_rate_get(const stmdev_ctx_t *ctx, iis2dh_odr_t *val)
445 {
446 iis2dh_ctrl_reg1_t ctrl_reg1;
447 int32_t ret;
448
449 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
450
451 switch (ctrl_reg1.odr)
452 {
453 case IIS2DH_POWER_DOWN:
454 *val = IIS2DH_POWER_DOWN;
455 break;
456
457 case IIS2DH_ODR_1Hz:
458 *val = IIS2DH_ODR_1Hz;
459 break;
460
461 case IIS2DH_ODR_10Hz:
462 *val = IIS2DH_ODR_10Hz;
463 break;
464
465 case IIS2DH_ODR_25Hz:
466 *val = IIS2DH_ODR_25Hz;
467 break;
468
469 case IIS2DH_ODR_50Hz:
470 *val = IIS2DH_ODR_50Hz;
471 break;
472
473 case IIS2DH_ODR_100Hz:
474 *val = IIS2DH_ODR_100Hz;
475 break;
476
477 case IIS2DH_ODR_200Hz:
478 *val = IIS2DH_ODR_200Hz;
479 break;
480
481 case IIS2DH_ODR_400Hz:
482 *val = IIS2DH_ODR_400Hz;
483 break;
484
485 case IIS2DH_ODR_1kHz620_LP:
486 *val = IIS2DH_ODR_1kHz620_LP;
487 break;
488
489 case IIS2DH_ODR_5kHz376_LP_1kHz344_NM_HP:
490 *val = IIS2DH_ODR_5kHz376_LP_1kHz344_NM_HP;
491 break;
492
493 default:
494 *val = IIS2DH_POWER_DOWN;
495 break;
496 }
497
498 return ret;
499 }
500
501 /**
502 * @brief High pass data from internal filter sent to output register
503 * and FIFO.
504 *
505 * @param ctx read / write interface definitions
506 * @param val change the values of fds in reg CTRL_REG2
507 * @retval interface status (MANDATORY: return 0 -> no Error)
508 *
509 */
iis2dh_high_pass_on_outputs_set(const stmdev_ctx_t * ctx,uint8_t val)510 int32_t iis2dh_high_pass_on_outputs_set(const stmdev_ctx_t *ctx,
511 uint8_t val)
512 {
513 iis2dh_ctrl_reg2_t ctrl_reg2;
514 int32_t ret;
515
516 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
517
518 if (ret == 0)
519 {
520 ctrl_reg2.fds = val;
521 ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
522 }
523
524 return ret;
525 }
526
527 /**
528 * @brief High pass data from internal filter sent to output register
529 * and FIFO.[get]
530 *
531 * @param ctx read / write interface definitions
532 * @param val change the values of fds in reg CTRL_REG2
533 * @retval interface status (MANDATORY: return 0 -> no Error)
534 *
535 */
iis2dh_high_pass_on_outputs_get(const stmdev_ctx_t * ctx,uint8_t * val)536 int32_t iis2dh_high_pass_on_outputs_get(const stmdev_ctx_t *ctx,
537 uint8_t *val)
538 {
539 iis2dh_ctrl_reg2_t ctrl_reg2;
540 int32_t ret;
541
542 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
543 *val = (uint8_t)ctrl_reg2.fds;
544
545 return ret;
546 }
547
548 /**
549 * @brief High-pass filter cutoff frequency selection.[set]
550 *
551 * HPCF[2:1]\ft @1Hz @10Hz @25Hz @50Hz @100Hz @200Hz @400Hz @1kHz6 ft@5kHz
552 * AGGRESSIVE 0.02Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 8Hz 32Hz 100Hz
553 * STRONG 0.008Hz 0.08Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 16Hz 50Hz
554 * MEDIUM 0.004Hz 0.04Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 2Hz 8Hz 25Hz
555 * LIGHT 0.002Hz 0.02Hz 0.05Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 4Hz 12Hz
556 *
557 * @param ctx read / write interface definitions
558 * @param val change the values of hpcf in reg CTRL_REG2
559 * @retval interface status (MANDATORY: return 0 -> no Error)
560 *
561 */
iis2dh_high_pass_bandwidth_set(const stmdev_ctx_t * ctx,iis2dh_hpcf_t val)562 int32_t iis2dh_high_pass_bandwidth_set(const stmdev_ctx_t *ctx,
563 iis2dh_hpcf_t val)
564 {
565 iis2dh_ctrl_reg2_t ctrl_reg2;
566 int32_t ret;
567
568 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
569
570 if (ret == 0)
571 {
572 ctrl_reg2.hpcf = (uint8_t)val;
573 ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
574 }
575
576 return ret;
577 }
578
579 /**
580 * @brief High-pass filter cutoff frequency selection.[get]
581 *
582 * HPCF[2:1]\ft @1Hz @10Hz @25Hz @50Hz @100Hz @200Hz @400Hz @1kHz6 ft@5kHz
583 * AGGRESSIVE 0.02Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 8Hz 32Hz 100Hz
584 * STRONG 0.008Hz 0.08Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 16Hz 50Hz
585 * MEDIUM 0.004Hz 0.04Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 2Hz 8Hz 25Hz
586 * LIGHT 0.002Hz 0.02Hz 0.05Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 4Hz 12Hz
587 *
588 * @param ctx read / write interface definitions
589 * @param val get the values of hpcf in reg CTRL_REG2
590 * @retval interface status (MANDATORY: return 0 -> no Error)
591 *
592 */
iis2dh_high_pass_bandwidth_get(const stmdev_ctx_t * ctx,iis2dh_hpcf_t * val)593 int32_t iis2dh_high_pass_bandwidth_get(const stmdev_ctx_t *ctx,
594 iis2dh_hpcf_t *val)
595 {
596 iis2dh_ctrl_reg2_t ctrl_reg2;
597 int32_t ret;
598
599 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
600
601 switch (ctrl_reg2.hpcf)
602 {
603 case IIS2DH_AGGRESSIVE:
604 *val = IIS2DH_AGGRESSIVE;
605 break;
606
607 case IIS2DH_STRONG:
608 *val = IIS2DH_STRONG;
609 break;
610
611 case IIS2DH_MEDIUM:
612 *val = IIS2DH_MEDIUM;
613 break;
614
615 case IIS2DH_LIGHT:
616 *val = IIS2DH_LIGHT;
617 break;
618
619 default:
620 *val = IIS2DH_LIGHT;
621 break;
622 }
623
624 return ret;
625 }
626
627 /**
628 * @brief High-pass filter mode selection.[set]
629 *
630 * @param ctx read / write interface definitions
631 * @param val change the values of hpm in reg CTRL_REG2
632 * @retval interface status (MANDATORY: return 0 -> no Error)
633 *
634 */
iis2dh_high_pass_mode_set(const stmdev_ctx_t * ctx,iis2dh_hpm_t val)635 int32_t iis2dh_high_pass_mode_set(const stmdev_ctx_t *ctx, iis2dh_hpm_t val)
636 {
637 iis2dh_ctrl_reg2_t ctrl_reg2;
638 int32_t ret;
639
640 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
641
642 if (ret == 0)
643 {
644 ctrl_reg2.hpm = (uint8_t)val;
645 ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
646 }
647
648 return ret;
649 }
650
651 /**
652 * @brief High-pass filter mode selection.[get]
653 *
654 * @param ctx read / write interface definitions
655 * @param val get the values of hpm in reg CTRL_REG2
656 * @retval interface status (MANDATORY: return 0 -> no Error)
657 *
658 */
iis2dh_high_pass_mode_get(const stmdev_ctx_t * ctx,iis2dh_hpm_t * val)659 int32_t iis2dh_high_pass_mode_get(const stmdev_ctx_t *ctx,
660 iis2dh_hpm_t *val)
661 {
662 iis2dh_ctrl_reg2_t ctrl_reg2;
663 int32_t ret;
664
665 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
666
667 switch (ctrl_reg2.hpm)
668 {
669 case IIS2DH_NORMAL_WITH_RST:
670 *val = IIS2DH_NORMAL_WITH_RST;
671 break;
672
673 case IIS2DH_REFERENCE_MODE:
674 *val = IIS2DH_REFERENCE_MODE;
675 break;
676
677 case IIS2DH_NORMAL:
678 *val = IIS2DH_NORMAL;
679 break;
680
681 case IIS2DH_AUTORST_ON_INT:
682 *val = IIS2DH_AUTORST_ON_INT;
683 break;
684
685 default:
686 *val = IIS2DH_NORMAL_WITH_RST;
687 break;
688 }
689
690 return ret;
691 }
692
693 /**
694 * @brief Full-scale configuration.[set]
695 *
696 * @param ctx read / write interface definitions
697 * @param val change the values of fs in reg CTRL_REG4
698 * @retval interface status (MANDATORY: return 0 -> no Error)
699 *
700 */
iis2dh_full_scale_set(const stmdev_ctx_t * ctx,iis2dh_fs_t val)701 int32_t iis2dh_full_scale_set(const stmdev_ctx_t *ctx, iis2dh_fs_t val)
702 {
703 iis2dh_ctrl_reg4_t ctrl_reg4;
704 int32_t ret;
705
706 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
707
708 if (ret == 0)
709 {
710 ctrl_reg4.fs = (uint8_t)val;
711 ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
712 }
713
714 return ret;
715 }
716
717 /**
718 * @brief Full-scale configuration.[get]
719 *
720 * @param ctx read / write interface definitions
721 * @param val get the values of fs in reg CTRL_REG4
722 * @retval interface status (MANDATORY: return 0 -> no Error)
723 *
724 */
iis2dh_full_scale_get(const stmdev_ctx_t * ctx,iis2dh_fs_t * val)725 int32_t iis2dh_full_scale_get(const stmdev_ctx_t *ctx, iis2dh_fs_t *val)
726 {
727 iis2dh_ctrl_reg4_t ctrl_reg4;
728 int32_t ret;
729
730 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
731
732 switch (ctrl_reg4.fs)
733 {
734 case IIS2DH_2g:
735 *val = IIS2DH_2g;
736 break;
737
738 case IIS2DH_4g:
739 *val = IIS2DH_4g;
740 break;
741
742 case IIS2DH_8g:
743 *val = IIS2DH_8g;
744 break;
745
746 case IIS2DH_16g:
747 *val = IIS2DH_16g;
748 break;
749
750 default:
751 *val = IIS2DH_2g;
752 break;
753 }
754
755 return ret;
756 }
757
758 /**
759 * @brief Block Data Update.[set]
760 *
761 * @param ctx read / write interface definitions
762 * @param val change the values of bdu in reg CTRL_REG4
763 * @retval interface status (MANDATORY: return 0 -> no Error)
764 *
765 */
iis2dh_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)766 int32_t iis2dh_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val)
767 {
768 iis2dh_ctrl_reg4_t ctrl_reg4;
769 int32_t ret;
770
771 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
772
773 if (ret == 0)
774 {
775 ctrl_reg4.bdu = val;
776 ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
777 }
778
779 return ret;
780 }
781
782 /**
783 * @brief Block Data Update.[get]
784 *
785 * @param ctx read / write interface definitions
786 * @param val change the values of bdu in reg CTRL_REG4
787 * @retval interface status (MANDATORY: return 0 -> no Error)
788 *
789 */
iis2dh_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)790 int32_t iis2dh_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val)
791 {
792 iis2dh_ctrl_reg4_t ctrl_reg4;
793 int32_t ret;
794
795 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
796 *val = (uint8_t)ctrl_reg4.bdu;
797
798 return ret;
799 }
800
801 /**
802 * @brief Reference value for interrupt generation.[set]
803 * LSB = ~16@2g / ~31@4g / ~63@8g / ~127@16g
804 *
805 * @param ctx read / write interface definitions
806 * @param buff buffer that contains data to write
807 * @retval interface status (MANDATORY: return 0 -> no Error)
808 *
809 */
iis2dh_filter_reference_set(const stmdev_ctx_t * ctx,uint8_t * buff)810 int32_t iis2dh_filter_reference_set(const stmdev_ctx_t *ctx, uint8_t *buff)
811 {
812 int32_t ret;
813
814 ret = iis2dh_write_reg(ctx, IIS2DH_REFERENCE, buff, 1);
815
816 return ret;
817 }
818
819 /**
820 * @brief Reference value for interrupt generation.[get]
821 * LSB = ~16@2g / ~31@4g / ~63@8g / ~127@16g
822 *
823 * @param ctx read / write interface definitions
824 * @param buff buffer that stores data read
825 * @retval interface status (MANDATORY: return 0 -> no Error)
826 *
827 */
iis2dh_filter_reference_get(const stmdev_ctx_t * ctx,uint8_t * buff)828 int32_t iis2dh_filter_reference_get(const stmdev_ctx_t *ctx, uint8_t *buff)
829 {
830 int32_t ret;
831
832 ret = iis2dh_read_reg(ctx, IIS2DH_REFERENCE, buff, 1);
833
834 return ret;
835 }
836 /**
837 * @brief Acceleration set of data available.[get]
838 *
839 * @param ctx read / write interface definitions
840 * @param val change the values of zyxda in reg STATUS_REG
841 * @retval interface status (MANDATORY: return 0 -> no Error)
842 *
843 */
iis2dh_xl_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)844 int32_t iis2dh_xl_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val)
845 {
846 iis2dh_status_reg_t status_reg;
847 int32_t ret;
848
849 ret = iis2dh_read_reg(ctx, IIS2DH_STATUS_REG, (uint8_t *)&status_reg, 1);
850 *val = status_reg.zyxda;
851
852 return ret;
853 }
854 /**
855 * @brief Acceleration set of data overrun.[get]
856 *
857 * @param ctx read / write interface definitions
858 * @param val change the values of zyxor in reg STATUS_REG
859 * @retval interface status (MANDATORY: return 0 -> no Error)
860 *
861 */
iis2dh_xl_data_ovr_get(const stmdev_ctx_t * ctx,uint8_t * val)862 int32_t iis2dh_xl_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val)
863 {
864 iis2dh_status_reg_t status_reg;
865 int32_t ret;
866
867 ret = iis2dh_read_reg(ctx, IIS2DH_STATUS_REG, (uint8_t *)&status_reg, 1);
868 *val = status_reg.zyxor;
869
870 return ret;
871 }
872 /**
873 * @brief Acceleration output value.[get]
874 *
875 * @param ctx read / write interface definitions
876 * @param buff buffer that stores data read
877 * @retval interface status (MANDATORY: return 0 -> no Error)
878 *
879 */
iis2dh_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)880 int32_t iis2dh_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
881 {
882 uint8_t buff[6];
883 int32_t ret;
884
885 ret = iis2dh_read_reg(ctx, IIS2DH_OUT_X_L, buff, 6);
886 val[0] = (int16_t)buff[1];
887 val[0] = (val[0] * 256) + (int16_t)buff[0];
888 val[1] = (int16_t)buff[3];
889 val[1] = (val[1] * 256) + (int16_t)buff[2];
890 val[2] = (int16_t)buff[5];
891 val[2] = (val[2] * 256) + (int16_t)buff[4];
892
893 return ret;
894 }
895 /**
896 * @}
897 *
898 */
899
900 /**
901 * @defgroup IIS2DH_Common
902 * @brief This section group common useful functions
903 * @{
904 *
905 */
906
907 /**
908 * @brief DeviceWhoamI .[get]
909 *
910 * @param ctx read / write interface definitions
911 * @param buff buffer that stores data read
912 * @retval interface status (MANDATORY: return 0 -> no Error)
913 *
914 */
iis2dh_device_id_get(const stmdev_ctx_t * ctx,uint8_t * buff)915 int32_t iis2dh_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
916 {
917 int32_t ret;
918
919 ret = iis2dh_read_reg(ctx, IIS2DH_WHO_AM_I, buff, 1);
920
921 return ret;
922 }
923 /**
924 * @brief Self Test.[set]
925 *
926 * @param ctx read / write interface definitions
927 * @param val change the values of st in reg CTRL_REG4
928 * @retval interface status (MANDATORY: return 0 -> no Error)
929 *
930 */
iis2dh_self_test_set(const stmdev_ctx_t * ctx,iis2dh_st_t val)931 int32_t iis2dh_self_test_set(const stmdev_ctx_t *ctx, iis2dh_st_t val)
932 {
933 iis2dh_ctrl_reg4_t ctrl_reg4;
934 int32_t ret;
935
936 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
937
938 if (ret == 0)
939 {
940 ctrl_reg4.st = (uint8_t)val;
941 ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
942 }
943
944 return ret;
945 }
946
947 /**
948 * @brief Self Test.[get]
949 *
950 * @param ctx read / write interface definitions
951 * @param val Get the values of st in reg CTRL_REG4
952 * @retval interface status (MANDATORY: return 0 -> no Error)
953 *
954 */
iis2dh_self_test_get(const stmdev_ctx_t * ctx,iis2dh_st_t * val)955 int32_t iis2dh_self_test_get(const stmdev_ctx_t *ctx, iis2dh_st_t *val)
956 {
957 iis2dh_ctrl_reg4_t ctrl_reg4;
958 int32_t ret;
959
960 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
961
962 switch (ctrl_reg4.st)
963 {
964 case IIS2DH_ST_DISABLE:
965 *val = IIS2DH_ST_DISABLE;
966 break;
967
968 case IIS2DH_ST_POSITIVE:
969 *val = IIS2DH_ST_POSITIVE;
970 break;
971
972 case IIS2DH_ST_NEGATIVE:
973 *val = IIS2DH_ST_NEGATIVE;
974 break;
975
976 default:
977 *val = IIS2DH_ST_DISABLE;
978 break;
979 }
980
981 return ret;
982 }
983
984 /**
985 * @brief Big/Little Endian data selection.[set]
986 *
987 * @param ctx read / write interface definitions
988 * @param val change the values of ble in reg CTRL_REG4
989 * @retval interface status (MANDATORY: return 0 -> no Error)
990 *
991 */
iis2dh_data_format_set(const stmdev_ctx_t * ctx,iis2dh_ble_t val)992 int32_t iis2dh_data_format_set(const stmdev_ctx_t *ctx, iis2dh_ble_t val)
993 {
994 iis2dh_ctrl_reg4_t ctrl_reg4;
995 int32_t ret;
996
997 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
998
999 if (ret == 0)
1000 {
1001 ctrl_reg4.ble = (uint8_t)val;
1002 ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
1003 }
1004
1005 return ret;
1006 }
1007
1008 /**
1009 * @brief Big/Little Endian data selection.[get]
1010 *
1011 * @param ctx read / write interface definitions
1012 * @param val get the values of ble in reg CTRL_REG4
1013 * @retval interface status (MANDATORY: return 0 -> no Error)
1014 *
1015 */
iis2dh_data_format_get(const stmdev_ctx_t * ctx,iis2dh_ble_t * val)1016 int32_t iis2dh_data_format_get(const stmdev_ctx_t *ctx, iis2dh_ble_t *val)
1017 {
1018 iis2dh_ctrl_reg4_t ctrl_reg4;
1019 int32_t ret;
1020
1021 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
1022
1023 switch (ctrl_reg4.ble)
1024 {
1025 case IIS2DH_LSB_AT_LOW_ADD:
1026 *val = IIS2DH_LSB_AT_LOW_ADD;
1027 break;
1028
1029 case IIS2DH_MSB_AT_LOW_ADD:
1030 *val = IIS2DH_MSB_AT_LOW_ADD;
1031 break;
1032
1033 default:
1034 *val = IIS2DH_LSB_AT_LOW_ADD;
1035 break;
1036 }
1037
1038 return ret;
1039 }
1040
1041 /**
1042 * @brief Reboot memory content. Reload the calibration parameters.[set]
1043 *
1044 * @param ctx read / write interface definitions
1045 * @param val change the values of boot in reg CTRL_REG5
1046 * @retval interface status (MANDATORY: return 0 -> no Error)
1047 *
1048 */
iis2dh_boot_set(const stmdev_ctx_t * ctx,uint8_t val)1049 int32_t iis2dh_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
1050 {
1051 iis2dh_ctrl_reg5_t ctrl_reg5;
1052 int32_t ret;
1053
1054 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1055
1056 if (ret == 0)
1057 {
1058 ctrl_reg5.boot = val;
1059 ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1060 }
1061
1062 return ret;
1063 }
1064
1065 /**
1066 * @brief Reboot memory content. Reload the calibration parameters.[get]
1067 *
1068 * @param ctx read / write interface definitions
1069 * @param val change the values of boot in reg CTRL_REG5
1070 * @retval interface status (MANDATORY: return 0 -> no Error)
1071 *
1072 */
iis2dh_boot_get(const stmdev_ctx_t * ctx,uint8_t * val)1073 int32_t iis2dh_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
1074 {
1075 iis2dh_ctrl_reg5_t ctrl_reg5;
1076 int32_t ret;
1077
1078 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1079 *val = (uint8_t)ctrl_reg5.boot;
1080
1081 return ret;
1082 }
1083
1084 /**
1085 * @brief count the interrupt occurrencies.[get]
1086 *
1087 * @param ctx read / write interface definitions
1088 * @param val registers INT_COUNTER_REG
1089 * @retval interface status (MANDATORY: return 0 -> no Error)
1090 *
1091 */
iis2dh_int_occurrencies_get(const stmdev_ctx_t * ctx,uint8_t * val)1092 int32_t iis2dh_int_occurrencies_get(const stmdev_ctx_t *ctx, uint8_t *val)
1093 {
1094 int32_t ret;
1095
1096 ret = iis2dh_read_reg(ctx, IIS2DH_INT_COUNTER_REG, (uint8_t *) val, 1);
1097
1098 return ret;
1099 }
1100
1101 /**
1102 * @brief Info about device status.[get]
1103 *
1104 * @param ctx read / write interface definitions
1105 * @param val register STATUS_REG
1106 * @retval interface status (MANDATORY: return 0 -> no Error)
1107 *
1108 */
iis2dh_status_get(const stmdev_ctx_t * ctx,iis2dh_status_reg_t * val)1109 int32_t iis2dh_status_get(const stmdev_ctx_t *ctx, iis2dh_status_reg_t *val)
1110 {
1111 int32_t ret;
1112
1113 ret = iis2dh_read_reg(ctx, IIS2DH_STATUS_REG, (uint8_t *) val, 1);
1114
1115 return ret;
1116 }
1117 /**
1118 * @}
1119 *
1120 */
1121
1122 /**
1123 * @defgroup IIS2DH_Interrupts_generator_1
1124 * @brief This section group all the functions that manage the first
1125 * interrupts generator
1126 * @{
1127 *
1128 */
1129
1130 /**
1131 * @brief Interrupt generator 1 configuration register.[set]
1132 *
1133 * @param ctx read / write interface definitions
1134 * @param val register INT1_CFG
1135 * @retval interface status (MANDATORY: return 0 -> no Error)
1136 *
1137 */
iis2dh_int1_gen_conf_set(const stmdev_ctx_t * ctx,iis2dh_int1_cfg_t * val)1138 int32_t iis2dh_int1_gen_conf_set(const stmdev_ctx_t *ctx,
1139 iis2dh_int1_cfg_t *val)
1140 {
1141 int32_t ret;
1142
1143 ret = iis2dh_write_reg(ctx, IIS2DH_INT1_CFG, (uint8_t *) val, 1);
1144
1145 return ret;
1146 }
1147
1148 /**
1149 * @brief Interrupt generator 1 configuration register.[get]
1150 *
1151 * @param ctx read / write interface definitions
1152 * @param val register INT1_CFG
1153 * @retval interface status (MANDATORY: return 0 -> no Error)
1154 *
1155 */
iis2dh_int1_gen_conf_get(const stmdev_ctx_t * ctx,iis2dh_int1_cfg_t * val)1156 int32_t iis2dh_int1_gen_conf_get(const stmdev_ctx_t *ctx,
1157 iis2dh_int1_cfg_t *val)
1158 {
1159 int32_t ret;
1160
1161 ret = iis2dh_read_reg(ctx, IIS2DH_INT1_CFG, (uint8_t *) val, 1);
1162
1163 return ret;
1164 }
1165
1166 /**
1167 * @brief Interrupt generator 1 source register.[get]
1168 *
1169 * @param ctx read / write interface definitions
1170 * @param val Registers INT1_SRC
1171 * @retval interface status (MANDATORY: return 0 -> no Error)
1172 *
1173 */
iis2dh_int1_gen_source_get(const stmdev_ctx_t * ctx,iis2dh_int1_src_t * val)1174 int32_t iis2dh_int1_gen_source_get(const stmdev_ctx_t *ctx,
1175 iis2dh_int1_src_t *val)
1176 {
1177 int32_t ret;
1178
1179 ret = iis2dh_read_reg(ctx, IIS2DH_INT1_SRC, (uint8_t *) val, 1);
1180
1181 return ret;
1182 }
1183 /**
1184 * @brief User-defined threshold value for xl interrupt event on
1185 * generator 1.[set]
1186 * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
1187 *
1188 * @param ctx read / write interface definitions
1189 * @param val change the values of ths in reg INT1_THS
1190 * @retval interface status (MANDATORY: return 0 -> no Error)
1191 *
1192 */
iis2dh_int1_gen_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)1193 int32_t iis2dh_int1_gen_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
1194 {
1195 iis2dh_int1_ths_t int1_ths;
1196 int32_t ret;
1197
1198 ret = iis2dh_read_reg(ctx, IIS2DH_INT1_THS, (uint8_t *)&int1_ths, 1);
1199
1200 if (ret == 0)
1201 {
1202 int1_ths.ths = val;
1203 ret = iis2dh_write_reg(ctx, IIS2DH_INT1_THS, (uint8_t *)&int1_ths, 1);
1204 }
1205
1206 return ret;
1207 }
1208
1209 /**
1210 * @brief User-defined threshold value for xl interrupt event on
1211 * generator 1.[get]
1212 * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
1213 *
1214 * @param ctx read / write interface definitions
1215 * @param val change the values of ths in reg INT1_THS
1216 * @retval interface status (MANDATORY: return 0 -> no Error)
1217 *
1218 */
iis2dh_int1_gen_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)1219 int32_t iis2dh_int1_gen_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
1220 {
1221 iis2dh_int1_ths_t int1_ths;
1222 int32_t ret;
1223
1224 ret = iis2dh_read_reg(ctx, IIS2DH_INT1_THS, (uint8_t *)&int1_ths, 1);
1225 *val = (uint8_t)int1_ths.ths;
1226
1227 return ret;
1228 }
1229
1230 /**
1231 * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be
1232 * recognized.[set]
1233 *
1234 * @param ctx read / write interface definitions
1235 * @param val change the values of d in reg INT1_DURATION
1236 * @retval interface status (MANDATORY: return 0 -> no Error)
1237 *
1238 */
iis2dh_int1_gen_duration_set(const stmdev_ctx_t * ctx,uint8_t val)1239 int32_t iis2dh_int1_gen_duration_set(const stmdev_ctx_t *ctx, uint8_t val)
1240 {
1241 iis2dh_int1_duration_t int1_duration;
1242 int32_t ret;
1243
1244 ret = iis2dh_read_reg(ctx, IIS2DH_INT1_DURATION,
1245 (uint8_t *)&int1_duration, 1);
1246
1247 if (ret == 0)
1248 {
1249 int1_duration.d = val;
1250 ret = iis2dh_write_reg(ctx, IIS2DH_INT1_DURATION,
1251 (uint8_t *)&int1_duration, 1);
1252 }
1253
1254 return ret;
1255 }
1256
1257 /**
1258 * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be
1259 * recognized.[get]
1260 *
1261 * @param ctx read / write interface definitions
1262 * @param val change the values of d in reg INT1_DURATION
1263 * @retval interface status (MANDATORY: return 0 -> no Error)
1264 *
1265 */
iis2dh_int1_gen_duration_get(const stmdev_ctx_t * ctx,uint8_t * val)1266 int32_t iis2dh_int1_gen_duration_get(const stmdev_ctx_t *ctx, uint8_t *val)
1267 {
1268 iis2dh_int1_duration_t int1_duration;
1269 int32_t ret;
1270
1271 ret = iis2dh_read_reg(ctx, IIS2DH_INT1_DURATION,
1272 (uint8_t *)&int1_duration, 1);
1273 *val = (uint8_t)int1_duration.d;
1274
1275 return ret;
1276 }
1277
1278 /**
1279 * @}
1280 *
1281 */
1282
1283 /**
1284 * @defgroup IIS2DH_Interrupts_generator_2
1285 * @brief This section group all the functions that manage the second
1286 * interrupts generator
1287 * @{
1288 *
1289 */
1290
1291 /**
1292 * @brief Interrupt generator 2 configuration register.[set]
1293 *
1294 * @param ctx read / write interface definitions
1295 * @param val registers INT2_CFG
1296 * @retval interface status (MANDATORY: return 0 -> no Error)
1297 *
1298 */
iis2dh_int2_gen_conf_set(const stmdev_ctx_t * ctx,iis2dh_int2_cfg_t * val)1299 int32_t iis2dh_int2_gen_conf_set(const stmdev_ctx_t *ctx,
1300 iis2dh_int2_cfg_t *val)
1301 {
1302 int32_t ret;
1303
1304 ret = iis2dh_write_reg(ctx, IIS2DH_INT2_CFG, (uint8_t *) val, 1);
1305
1306 return ret;
1307 }
1308
1309 /**
1310 * @brief Interrupt generator 2 configuration register.[get]
1311 *
1312 * @param ctx read / write interface definitions
1313 * @param val registers INT2_CFG
1314 * @retval interface status (MANDATORY: return 0 -> no Error)
1315 *
1316 */
iis2dh_int2_gen_conf_get(const stmdev_ctx_t * ctx,iis2dh_int2_cfg_t * val)1317 int32_t iis2dh_int2_gen_conf_get(const stmdev_ctx_t *ctx,
1318 iis2dh_int2_cfg_t *val)
1319 {
1320 int32_t ret;
1321
1322 ret = iis2dh_read_reg(ctx, IIS2DH_INT2_CFG, (uint8_t *) val, 1);
1323
1324 return ret;
1325 }
1326 /**
1327 * @brief Interrupt generator 2 source register.[get]
1328 *
1329 * @param ctx read / write interface definitions
1330 * @param val registers INT2_SRC
1331 * @retval interface status (MANDATORY: return 0 -> no Error)
1332 *
1333 */
iis2dh_int2_gen_source_get(const stmdev_ctx_t * ctx,iis2dh_int2_src_t * val)1334 int32_t iis2dh_int2_gen_source_get(const stmdev_ctx_t *ctx,
1335 iis2dh_int2_src_t *val)
1336 {
1337 int32_t ret;
1338
1339 ret = iis2dh_read_reg(ctx, IIS2DH_INT2_SRC, (uint8_t *) val, 1);
1340
1341 return ret;
1342 }
1343 /**
1344 * @brief User-defined threshold value for xl interrupt event on
1345 * generator 2.[set]
1346 * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
1347 *
1348 * @param ctx read / write interface definitions
1349 * @param val change the values of ths in reg INT2_THS
1350 * @retval interface status (MANDATORY: return 0 -> no Error)
1351 *
1352 */
iis2dh_int2_gen_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)1353 int32_t iis2dh_int2_gen_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
1354 {
1355 iis2dh_int2_ths_t int2_ths;
1356 int32_t ret;
1357
1358 ret = iis2dh_read_reg(ctx, IIS2DH_INT2_THS, (uint8_t *)&int2_ths, 1);
1359
1360 if (ret == 0)
1361 {
1362 int2_ths.ths = val;
1363 ret = iis2dh_write_reg(ctx, IIS2DH_INT2_THS, (uint8_t *)&int2_ths, 1);
1364 }
1365
1366 return ret;
1367 }
1368
1369 /**
1370 * @brief User-defined threshold value for xl interrupt event on
1371 * generator 2.[get]
1372 * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
1373 *
1374 * @param ctx read / write interface definitions
1375 * @param val change the values of ths in reg INT2_THS
1376 * @retval interface status (MANDATORY: return 0 -> no Error)
1377 *
1378 */
iis2dh_int2_gen_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)1379 int32_t iis2dh_int2_gen_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
1380 {
1381 iis2dh_int2_ths_t int2_ths;
1382 int32_t ret;
1383
1384 ret = iis2dh_read_reg(ctx, IIS2DH_INT2_THS, (uint8_t *)&int2_ths, 1);
1385 *val = (uint8_t)int2_ths.ths;
1386
1387 return ret;
1388 }
1389
1390 /**
1391 * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be
1392 * recognized .[set]
1393 *
1394 * @param ctx read / write interface definitions
1395 * @param val change the values of d in reg INT2_DURATION
1396 * @retval interface status (MANDATORY: return 0 -> no Error)
1397 *
1398 */
iis2dh_int2_gen_duration_set(const stmdev_ctx_t * ctx,uint8_t val)1399 int32_t iis2dh_int2_gen_duration_set(const stmdev_ctx_t *ctx, uint8_t val)
1400 {
1401 iis2dh_int2_duration_t int2_duration;
1402 int32_t ret;
1403
1404 ret = iis2dh_read_reg(ctx, IIS2DH_INT2_DURATION,
1405 (uint8_t *)&int2_duration, 1);
1406
1407 if (ret == 0)
1408 {
1409 int2_duration.d = val;
1410 ret = iis2dh_write_reg(ctx, IIS2DH_INT2_DURATION,
1411 (uint8_t *)&int2_duration, 1);
1412 }
1413
1414 return ret;
1415 }
1416
1417 /**
1418 * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be
1419 * recognized.[get]
1420 *
1421 * @param ctx read / write interface definitions
1422 * @param val change the values of d in reg INT2_DURATION
1423 * @retval interface status (MANDATORY: return 0 -> no Error)
1424 *
1425 */
iis2dh_int2_gen_duration_get(const stmdev_ctx_t * ctx,uint8_t * val)1426 int32_t iis2dh_int2_gen_duration_get(const stmdev_ctx_t *ctx, uint8_t *val)
1427 {
1428 iis2dh_int2_duration_t int2_duration;
1429 int32_t ret;
1430
1431 ret = iis2dh_read_reg(ctx, IIS2DH_INT2_DURATION,
1432 (uint8_t *)&int2_duration, 1);
1433 *val = (uint8_t)int2_duration.d;
1434
1435 return ret;
1436 }
1437
1438 /**
1439 * @}
1440 *
1441 */
1442
1443 /**
1444 * @defgroup IIS2DH_Interrupt_pins
1445 * @brief This section group all the functions that manage interrupt pins
1446 * @{
1447 *
1448 */
1449
1450 /**
1451 * @brief High-pass filter on interrupts/tap generator.[set]
1452 *
1453 * @param ctx read / write interface definitions
1454 * @param val change the values of hp in reg CTRL_REG2
1455 * @retval interface status (MANDATORY: return 0 -> no Error)
1456 *
1457 */
iis2dh_high_pass_int_conf_set(const stmdev_ctx_t * ctx,iis2dh_hp_t val)1458 int32_t iis2dh_high_pass_int_conf_set(const stmdev_ctx_t *ctx,
1459 iis2dh_hp_t val)
1460 {
1461 iis2dh_ctrl_reg2_t ctrl_reg2;
1462 int32_t ret;
1463
1464 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
1465
1466 if (ret == 0)
1467 {
1468 ctrl_reg2.hp = (uint8_t)val;
1469 ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
1470 }
1471
1472 return ret;
1473 }
1474
1475 /**
1476 * @brief High-pass filter on interrupts/tap generator.[get]
1477 *
1478 * @param ctx read / write interface definitions
1479 * @param val Get the values of hp in reg CTRL_REG2
1480 * @retval interface status (MANDATORY: return 0 -> no Error)
1481 *
1482 */
iis2dh_high_pass_int_conf_get(const stmdev_ctx_t * ctx,iis2dh_hp_t * val)1483 int32_t iis2dh_high_pass_int_conf_get(const stmdev_ctx_t *ctx,
1484 iis2dh_hp_t *val)
1485 {
1486 iis2dh_ctrl_reg2_t ctrl_reg2;
1487 int32_t ret;
1488
1489 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
1490
1491 switch (ctrl_reg2.hp)
1492 {
1493 case IIS2DH_DISC_FROM_INT_GENERATOR:
1494 *val = IIS2DH_DISC_FROM_INT_GENERATOR;
1495 break;
1496
1497 case IIS2DH_ON_INT1_GEN:
1498 *val = IIS2DH_ON_INT1_GEN;
1499 break;
1500
1501 case IIS2DH_ON_INT2_GEN:
1502 *val = IIS2DH_ON_INT2_GEN;
1503 break;
1504
1505 case IIS2DH_ON_TAP_GEN:
1506 *val = IIS2DH_ON_TAP_GEN;
1507 break;
1508
1509 case IIS2DH_ON_INT1_INT2_GEN:
1510 *val = IIS2DH_ON_INT1_INT2_GEN;
1511 break;
1512
1513 case IIS2DH_ON_INT1_TAP_GEN:
1514 *val = IIS2DH_ON_INT1_TAP_GEN;
1515 break;
1516
1517 case IIS2DH_ON_INT2_TAP_GEN:
1518 *val = IIS2DH_ON_INT2_TAP_GEN;
1519 break;
1520
1521 case IIS2DH_ON_INT1_INT2_TAP_GEN:
1522 *val = IIS2DH_ON_INT1_INT2_TAP_GEN;
1523 break;
1524
1525 default:
1526 *val = IIS2DH_DISC_FROM_INT_GENERATOR;
1527 break;
1528 }
1529
1530 return ret;
1531 }
1532
1533 /**
1534 * @brief Int1 pin routing configuration register.[set]
1535 *
1536 * @param ctx read / write interface definitions
1537 * @param val registers CTRL_REG3
1538 * @retval interface status (MANDATORY: return 0 -> no Error)
1539 *
1540 */
iis2dh_pin_int1_config_set(const stmdev_ctx_t * ctx,iis2dh_ctrl_reg3_t * val)1541 int32_t iis2dh_pin_int1_config_set(const stmdev_ctx_t *ctx,
1542 iis2dh_ctrl_reg3_t *val)
1543 {
1544 int32_t ret;
1545
1546 ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG3, (uint8_t *) val, 1);
1547
1548 return ret;
1549 }
1550
1551 /**
1552 * @brief Int1 pin routing configuration register.[get]
1553 *
1554 * @param ctx read / write interface definitions
1555 * @param val registers CTRL_REG3
1556 * @retval interface status (MANDATORY: return 0 -> no Error)
1557 *
1558 */
iis2dh_pin_int1_config_get(const stmdev_ctx_t * ctx,iis2dh_ctrl_reg3_t * val)1559 int32_t iis2dh_pin_int1_config_get(const stmdev_ctx_t *ctx,
1560 iis2dh_ctrl_reg3_t *val)
1561 {
1562 int32_t ret;
1563
1564 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG3, (uint8_t *) val, 1);
1565
1566 return ret;
1567 }
1568 /**
1569 * @brief int2_pin_detect_4d: [set] 4D enable: 4D detection is enabled
1570 * on INT2 pin when 6D bit on
1571 * INT2_CFG (34h) is set to 1.
1572 *
1573 * @param ctx read / write interface definitions
1574 * @param val change the values of d4d_int2 in reg CTRL_REG5
1575 * @retval interface status (MANDATORY: return 0 -> no Error)
1576 *
1577 */
iis2dh_int2_pin_detect_4d_set(const stmdev_ctx_t * ctx,uint8_t val)1578 int32_t iis2dh_int2_pin_detect_4d_set(const stmdev_ctx_t *ctx, uint8_t val)
1579 {
1580 iis2dh_ctrl_reg5_t ctrl_reg5;
1581 int32_t ret;
1582
1583 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1584
1585 if (ret == 0)
1586 {
1587 ctrl_reg5.d4d_int2 = val;
1588 ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1589 }
1590
1591 return ret;
1592 }
1593
1594 /**
1595 * @brief 4D enable: 4D detection is enabled on INT2 pin when 6D bit on
1596 * INT2_CFG (34h) is set to 1.[get]
1597 *
1598 * @param ctx read / write interface definitions
1599 * @param val change the values of d4d_int2 in reg CTRL_REG5
1600 * @retval interface status (MANDATORY: return 0 -> no Error)
1601 *
1602 */
iis2dh_int2_pin_detect_4d_get(const stmdev_ctx_t * ctx,uint8_t * val)1603 int32_t iis2dh_int2_pin_detect_4d_get(const stmdev_ctx_t *ctx, uint8_t *val)
1604 {
1605 iis2dh_ctrl_reg5_t ctrl_reg5;
1606 int32_t ret;
1607
1608 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1609 *val = (uint8_t)ctrl_reg5.d4d_int2;
1610
1611 return ret;
1612 }
1613
1614 /**
1615 * @brief Latch interrupt request on INT2_SRC (35h) register, with
1616 * INT2_SRC (35h) register cleared by reading INT2_SRC(35h)
1617 * itself.[set]
1618 *
1619 * @param ctx read / write interface definitions
1620 * @param val change the values of lir_int2 in reg CTRL_REG5
1621 * @retval interface status (MANDATORY: return 0 -> no Error)
1622 *
1623 */
iis2dh_int2_pin_notification_mode_set(const stmdev_ctx_t * ctx,iis2dh_lir_int2_t val)1624 int32_t iis2dh_int2_pin_notification_mode_set(const stmdev_ctx_t *ctx,
1625 iis2dh_lir_int2_t val)
1626 {
1627 iis2dh_ctrl_reg5_t ctrl_reg5;
1628 int32_t ret;
1629
1630 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1631
1632 if (ret == 0)
1633 {
1634 ctrl_reg5.lir_int2 = (uint8_t)val;
1635 ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1636 }
1637
1638 return ret;
1639 }
1640
1641 /**
1642 * @brief Latch interrupt request on INT2_SRC (35h) register, with
1643 * INT2_SRC (35h) register cleared by reading INT2_SRC(35h)
1644 * itself.[get]
1645 *
1646 * @param ctx read / write interface definitions
1647 * @param val Get the values of lir_int2 in reg CTRL_REG5
1648 * @retval interface status (MANDATORY: return 0 -> no Error)
1649 *
1650 */
iis2dh_int2_pin_notification_mode_get(const stmdev_ctx_t * ctx,iis2dh_lir_int2_t * val)1651 int32_t iis2dh_int2_pin_notification_mode_get(const stmdev_ctx_t *ctx,
1652 iis2dh_lir_int2_t *val)
1653 {
1654 iis2dh_ctrl_reg5_t ctrl_reg5;
1655 int32_t ret;
1656
1657 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1658
1659 switch (ctrl_reg5.lir_int2)
1660 {
1661 case IIS2DH_INT2_PULSED:
1662 *val = IIS2DH_INT2_PULSED;
1663 break;
1664
1665 case IIS2DH_INT2_LATCHED:
1666 *val = IIS2DH_INT2_LATCHED;
1667 break;
1668
1669 default:
1670 *val = IIS2DH_INT2_PULSED;
1671 break;
1672 }
1673
1674 return ret;
1675 }
1676
1677 /**
1678 * @brief 4D enable: 4D detection is enabled on INT1 pin when 6D bit
1679 * on INT1_CFG(30h) is set to 1.[set]
1680 *
1681 * @param ctx read / write interface definitions
1682 * @param val change the values of d4d_int1 in reg CTRL_REG5
1683 * @retval interface status (MANDATORY: return 0 -> no Error)
1684 *
1685 */
iis2dh_int1_pin_detect_4d_set(const stmdev_ctx_t * ctx,uint8_t val)1686 int32_t iis2dh_int1_pin_detect_4d_set(const stmdev_ctx_t *ctx, uint8_t val)
1687 {
1688 iis2dh_ctrl_reg5_t ctrl_reg5;
1689 int32_t ret;
1690
1691 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1692
1693 if (ret == 0)
1694 {
1695 ctrl_reg5.d4d_int1 = val;
1696 ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1697 }
1698
1699 return ret;
1700 }
1701
1702 /**
1703 * @brief 4D enable: 4D detection is enabled on INT1 pin when 6D bit on
1704 * INT1_CFG(30h) is set to 1.[get]
1705 *
1706 * @param ctx read / write interface definitions
1707 * @param val change the values of d4d_int1 in reg CTRL_REG5
1708 * @retval interface status (MANDATORY: return 0 -> no Error)
1709 *
1710 */
iis2dh_int1_pin_detect_4d_get(const stmdev_ctx_t * ctx,uint8_t * val)1711 int32_t iis2dh_int1_pin_detect_4d_get(const stmdev_ctx_t *ctx, uint8_t *val)
1712 {
1713 iis2dh_ctrl_reg5_t ctrl_reg5;
1714 int32_t ret;
1715
1716 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1717 *val = (uint8_t)ctrl_reg5.d4d_int1;
1718
1719 return ret;
1720 }
1721
1722 /**
1723 * @brief Latch interrupt request on INT1_SRC (31h), with INT1_SRC(31h)
1724 * register cleared by reading INT1_SRC (31h) itself.[set]
1725 *
1726 * @param ctx read / write interface definitions
1727 * @param val change the values of lir_int1 in reg CTRL_REG5
1728 * @retval interface status (MANDATORY: return 0 -> no Error)
1729 *
1730 */
iis2dh_int1_pin_notification_mode_set(const stmdev_ctx_t * ctx,iis2dh_lir_int1_t val)1731 int32_t iis2dh_int1_pin_notification_mode_set(const stmdev_ctx_t *ctx,
1732 iis2dh_lir_int1_t val)
1733 {
1734 iis2dh_ctrl_reg5_t ctrl_reg5;
1735 int32_t ret;
1736
1737 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1738
1739 if (ret == 0)
1740 {
1741 ctrl_reg5.lir_int1 = (uint8_t)val;
1742 ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1743 }
1744
1745 return ret;
1746 }
1747
1748 /**
1749 * @brief Latch interrupt request on INT1_SRC (31h), with INT1_SRC(31h)
1750 * register cleared by reading INT1_SRC (31h) itself.[get]
1751 *
1752 * @param ctx read / write interface definitions
1753 * @param val Get the values of lir_int1 in reg CTRL_REG5
1754 * @retval interface status (MANDATORY: return 0 -> no Error)
1755 *
1756 */
iis2dh_int1_pin_notification_mode_get(const stmdev_ctx_t * ctx,iis2dh_lir_int1_t * val)1757 int32_t iis2dh_int1_pin_notification_mode_get(const stmdev_ctx_t *ctx,
1758 iis2dh_lir_int1_t *val)
1759 {
1760 iis2dh_ctrl_reg5_t ctrl_reg5;
1761 int32_t ret;
1762
1763 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1764
1765 switch (ctrl_reg5.lir_int1)
1766 {
1767 case IIS2DH_INT1_PULSED:
1768 *val = IIS2DH_INT1_PULSED;
1769 break;
1770
1771 case IIS2DH_INT1_LATCHED:
1772 *val = IIS2DH_INT1_LATCHED;
1773 break;
1774
1775 default:
1776 *val = IIS2DH_INT1_PULSED;
1777 break;
1778 }
1779
1780 return ret;
1781 }
1782
1783 /**
1784 * @brief Int2 pin routing configuration register.[set]
1785 *
1786 * @param ctx read / write interface definitions
1787 * @param val registers CTRL_REG6
1788 * @retval interface status (MANDATORY: return 0 -> no Error)
1789 *
1790 */
iis2dh_pin_int2_config_set(const stmdev_ctx_t * ctx,iis2dh_ctrl_reg6_t * val)1791 int32_t iis2dh_pin_int2_config_set(const stmdev_ctx_t *ctx,
1792 iis2dh_ctrl_reg6_t *val)
1793 {
1794 int32_t ret;
1795
1796 ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG6, (uint8_t *) val, 1);
1797
1798 return ret;
1799 }
1800
1801 /**
1802 * @brief Int2 pin routing configuration register.[get]
1803 *
1804 * @param ctx read / write interface definitions
1805 * @param val registers CTRL_REG6
1806 * @retval interface status (MANDATORY: return 0 -> no Error)
1807 *
1808 */
iis2dh_pin_int2_config_get(const stmdev_ctx_t * ctx,iis2dh_ctrl_reg6_t * val)1809 int32_t iis2dh_pin_int2_config_get(const stmdev_ctx_t *ctx,
1810 iis2dh_ctrl_reg6_t *val)
1811 {
1812 int32_t ret;
1813
1814 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG6, (uint8_t *) val, 1);
1815
1816 return ret;
1817 }
1818
1819 /**
1820 * @}
1821 *
1822 */
1823
1824 /**
1825 * @defgroup IIS2DH_Fifo
1826 * @brief This section group all the functions concerning the fifo usage
1827 * @{
1828 *
1829 */
1830
1831 /**
1832 * @brief FIFO enable.[set]
1833 *
1834 * @param ctx read / write interface definitions
1835 * @param val change the values of fifo_en in reg CTRL_REG5
1836 * @retval interface status (MANDATORY: return 0 -> no Error)
1837 *
1838 */
iis2dh_fifo_set(const stmdev_ctx_t * ctx,uint8_t val)1839 int32_t iis2dh_fifo_set(const stmdev_ctx_t *ctx, uint8_t val)
1840 {
1841 iis2dh_ctrl_reg5_t ctrl_reg5;
1842 int32_t ret;
1843
1844 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1845
1846 if (ret == 0)
1847 {
1848 ctrl_reg5.fifo_en = val;
1849 ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1850 }
1851
1852 return ret;
1853 }
1854
1855 /**
1856 * @brief FIFO enable.[get]
1857 *
1858 * @param ctx read / write interface definitions
1859 * @param val change the values of fifo_en in reg CTRL_REG5
1860 * @retval interface status (MANDATORY: return 0 -> no Error)
1861 *
1862 */
iis2dh_fifo_get(const stmdev_ctx_t * ctx,uint8_t * val)1863 int32_t iis2dh_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val)
1864 {
1865 iis2dh_ctrl_reg5_t ctrl_reg5;
1866 int32_t ret;
1867
1868 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1869 *val = (uint8_t)ctrl_reg5.fifo_en;
1870
1871 return ret;
1872 }
1873
1874 /**
1875 * @brief FIFO watermark level selection.[set]
1876 *
1877 * @param ctx read / write interface definitions
1878 * @param val change the values of fth in reg FIFO_CTRL_REG
1879 * @retval interface status (MANDATORY: return 0 -> no Error)
1880 *
1881 */
iis2dh_fifo_watermark_set(const stmdev_ctx_t * ctx,uint8_t val)1882 int32_t iis2dh_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val)
1883 {
1884 iis2dh_fifo_ctrl_reg_t fifo_ctrl_reg;
1885 int32_t ret;
1886
1887 ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_CTRL_REG,
1888 (uint8_t *)&fifo_ctrl_reg, 1);
1889
1890 if (ret == 0)
1891 {
1892 fifo_ctrl_reg.fth = val;
1893 ret = iis2dh_write_reg(ctx, IIS2DH_FIFO_CTRL_REG,
1894 (uint8_t *)&fifo_ctrl_reg, 1);
1895 }
1896
1897 return ret;
1898 }
1899
1900 /**
1901 * @brief FIFO watermark level selection.[get]
1902 *
1903 * @param ctx read / write interface definitions
1904 * @param val change the values of fth in reg FIFO_CTRL_REG
1905 * @retval interface status (MANDATORY: return 0 -> no Error)
1906 *
1907 */
iis2dh_fifo_watermark_get(const stmdev_ctx_t * ctx,uint8_t * val)1908 int32_t iis2dh_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val)
1909 {
1910 iis2dh_fifo_ctrl_reg_t fifo_ctrl_reg;
1911 int32_t ret;
1912
1913 ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_CTRL_REG,
1914 (uint8_t *)&fifo_ctrl_reg, 1);
1915 *val = (uint8_t)fifo_ctrl_reg.fth;
1916
1917 return ret;
1918 }
1919
1920 /**
1921 * @brief Trigger FIFO selection.[set]
1922 *
1923 * @param ctx read / write interface definitions
1924 * @param val change the values of tr in reg FIFO_CTRL_REG
1925 * @retval interface status (MANDATORY: return 0 -> no Error)
1926 *
1927 */
iis2dh_fifo_trigger_event_set(const stmdev_ctx_t * ctx,iis2dh_tr_t val)1928 int32_t iis2dh_fifo_trigger_event_set(const stmdev_ctx_t *ctx,
1929 iis2dh_tr_t val)
1930 {
1931 iis2dh_fifo_ctrl_reg_t fifo_ctrl_reg;
1932 int32_t ret;
1933
1934 ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_CTRL_REG,
1935 (uint8_t *)&fifo_ctrl_reg, 1);
1936
1937 if (ret == 0)
1938 {
1939 fifo_ctrl_reg.tr = (uint8_t)val;
1940 ret = iis2dh_write_reg(ctx, IIS2DH_FIFO_CTRL_REG,
1941 (uint8_t *)&fifo_ctrl_reg, 1);
1942 }
1943
1944 return ret;
1945 }
1946
1947 /**
1948 * @brief Trigger FIFO selection.[get]
1949 *
1950 * @param ctx read / write interface definitions
1951 * @param val Get the values of tr in reg FIFO_CTRL_REG
1952 * @retval interface status (MANDATORY: return 0 -> no Error)
1953 *
1954 */
iis2dh_fifo_trigger_event_get(const stmdev_ctx_t * ctx,iis2dh_tr_t * val)1955 int32_t iis2dh_fifo_trigger_event_get(const stmdev_ctx_t *ctx,
1956 iis2dh_tr_t *val)
1957 {
1958 iis2dh_fifo_ctrl_reg_t fifo_ctrl_reg;
1959 int32_t ret;
1960
1961 ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_CTRL_REG,
1962 (uint8_t *)&fifo_ctrl_reg, 1);
1963
1964 switch (fifo_ctrl_reg.tr)
1965 {
1966 case IIS2DH_INT1_GEN:
1967 *val = IIS2DH_INT1_GEN;
1968 break;
1969
1970 case IIS2DH_INT2_GEN:
1971 *val = IIS2DH_INT2_GEN;
1972 break;
1973
1974 default:
1975 *val = IIS2DH_INT1_GEN;
1976 break;
1977 }
1978
1979 return ret;
1980 }
1981
1982 /**
1983 * @brief FIFO mode selection.[set]
1984 *
1985 * @param ctx read / write interface definitions
1986 * @param val change the values of fm in reg FIFO_CTRL_REG
1987 * @retval interface status (MANDATORY: return 0 -> no Error)
1988 *
1989 */
iis2dh_fifo_mode_set(const stmdev_ctx_t * ctx,iis2dh_fm_t val)1990 int32_t iis2dh_fifo_mode_set(const stmdev_ctx_t *ctx, iis2dh_fm_t val)
1991 {
1992 iis2dh_fifo_ctrl_reg_t fifo_ctrl_reg;
1993 int32_t ret;
1994
1995 ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_CTRL_REG,
1996 (uint8_t *)&fifo_ctrl_reg, 1);
1997
1998 if (ret == 0)
1999 {
2000 fifo_ctrl_reg.fm = (uint8_t)val;
2001 ret = iis2dh_write_reg(ctx, IIS2DH_FIFO_CTRL_REG,
2002 (uint8_t *)&fifo_ctrl_reg, 1);
2003 }
2004
2005 return ret;
2006 }
2007
2008 /**
2009 * @brief FIFO mode selection.[get]
2010 *
2011 * @param ctx read / write interface definitions
2012 * @param val Get the values of fm in reg FIFO_CTRL_REG
2013 * @retval interface status (MANDATORY: return 0 -> no Error)
2014 *
2015 */
iis2dh_fifo_mode_get(const stmdev_ctx_t * ctx,iis2dh_fm_t * val)2016 int32_t iis2dh_fifo_mode_get(const stmdev_ctx_t *ctx, iis2dh_fm_t *val)
2017 {
2018 iis2dh_fifo_ctrl_reg_t fifo_ctrl_reg;
2019 int32_t ret;
2020
2021 ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_CTRL_REG,
2022 (uint8_t *)&fifo_ctrl_reg, 1);
2023
2024 switch (fifo_ctrl_reg.fm)
2025 {
2026 case IIS2DH_BYPASS_MODE:
2027 *val = IIS2DH_BYPASS_MODE;
2028 break;
2029
2030 case IIS2DH_FIFO_MODE:
2031 *val = IIS2DH_FIFO_MODE;
2032 break;
2033
2034 case IIS2DH_DYNAMIC_STREAM_MODE:
2035 *val = IIS2DH_DYNAMIC_STREAM_MODE;
2036 break;
2037
2038 case IIS2DH_STREAM_TO_FIFO_MODE:
2039 *val = IIS2DH_STREAM_TO_FIFO_MODE;
2040 break;
2041
2042 default:
2043 *val = IIS2DH_BYPASS_MODE;
2044 break;
2045 }
2046
2047 return ret;
2048 }
2049
2050 /**
2051 * @brief FIFO status register.[get]
2052 *
2053 * @param ctx read / write interface definitions
2054 * @param val registers FIFO_SRC_REG
2055 * @retval interface status (MANDATORY: return 0 -> no Error)
2056 *
2057 */
iis2dh_fifo_status_get(const stmdev_ctx_t * ctx,iis2dh_fifo_src_reg_t * val)2058 int32_t iis2dh_fifo_status_get(const stmdev_ctx_t *ctx,
2059 iis2dh_fifo_src_reg_t *val)
2060 {
2061 int32_t ret;
2062
2063 ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_SRC_REG, (uint8_t *) val, 1);
2064
2065 return ret;
2066 }
2067 /**
2068 * @brief FIFO stored data level.[get]
2069 *
2070 * @param ctx read / write interface definitions
2071 * @param val change the values of fss in reg FIFO_SRC_REG
2072 * @retval interface status (MANDATORY: return 0 -> no Error)
2073 *
2074 */
iis2dh_fifo_data_level_get(const stmdev_ctx_t * ctx,uint8_t * val)2075 int32_t iis2dh_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val)
2076 {
2077 iis2dh_fifo_src_reg_t fifo_src_reg;
2078 int32_t ret;
2079
2080 ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_SRC_REG,
2081 (uint8_t *)&fifo_src_reg, 1);
2082 *val = (uint8_t)fifo_src_reg.fss;
2083
2084 return ret;
2085 }
2086 /**
2087 * @brief Empty FIFO status flag.[get]
2088 *
2089 * @param ctx read / write interface definitions
2090 * @param val change the values of empty in reg FIFO_SRC_REG
2091 * @retval interface status (MANDATORY: return 0 -> no Error)
2092 *
2093 */
iis2dh_fifo_empty_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)2094 int32_t iis2dh_fifo_empty_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
2095 {
2096 iis2dh_fifo_src_reg_t fifo_src_reg;
2097 int32_t ret;
2098
2099 ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_SRC_REG,
2100 (uint8_t *)&fifo_src_reg, 1);
2101 *val = (uint8_t)fifo_src_reg.empty;
2102
2103 return ret;
2104 }
2105 /**
2106 * @brief FIFO overrun status flag.[get]
2107 *
2108 * @param ctx read / write interface definitions
2109 * @param val change the values of ovrn_fifo in reg FIFO_SRC_REG
2110 * @retval interface status (MANDATORY: return 0 -> no Error)
2111 *
2112 */
iis2dh_fifo_ovr_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)2113 int32_t iis2dh_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
2114 {
2115 iis2dh_fifo_src_reg_t fifo_src_reg;
2116 int32_t ret;
2117
2118 ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_SRC_REG,
2119 (uint8_t *)&fifo_src_reg, 1);
2120 *val = (uint8_t)fifo_src_reg.ovrn_fifo;
2121
2122 return ret;
2123 }
2124 /**
2125 * @brief FIFO watermark status.[get]
2126 *
2127 * @param ctx read / write interface definitions
2128 * @param val change the values of wtm in reg FIFO_SRC_REG
2129 * @retval interface status (MANDATORY: return 0 -> no Error)
2130 *
2131 */
iis2dh_fifo_fth_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)2132 int32_t iis2dh_fifo_fth_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
2133 {
2134 iis2dh_fifo_src_reg_t fifo_src_reg;
2135 int32_t ret;
2136
2137 ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_SRC_REG,
2138 (uint8_t *)&fifo_src_reg, 1);
2139 *val = (uint8_t)fifo_src_reg.wtm;
2140
2141 return ret;
2142 }
2143 /**
2144 * @}
2145 *
2146 */
2147
2148 /**
2149 * @defgroup IIS2DH_Tap_generator
2150 * @brief This section group all the functions that manage the tap and
2151 * double tap event generation
2152 * @{
2153 *
2154 */
2155
2156 /**
2157 * @brief Tap/Double Tap generator configuration register.[set]
2158 *
2159 * @param ctx read / write interface definitions
2160 * @param val registers CLICK_CFG
2161 * @retval interface status (MANDATORY: return 0 -> no Error)
2162 *
2163 */
iis2dh_tap_conf_set(const stmdev_ctx_t * ctx,iis2dh_click_cfg_t * val)2164 int32_t iis2dh_tap_conf_set(const stmdev_ctx_t *ctx,
2165 iis2dh_click_cfg_t *val)
2166 {
2167 int32_t ret;
2168
2169 ret = iis2dh_write_reg(ctx, IIS2DH_CLICK_CFG, (uint8_t *) val, 1);
2170
2171 return ret;
2172 }
2173
2174 /**
2175 * @brief Tap/Double Tap generator configuration register.[get]
2176 *
2177 * @param ctx read / write interface definitions
2178 * @param val registers CLICK_CFG
2179 * @retval interface status (MANDATORY: return 0 -> no Error)
2180 *
2181 */
iis2dh_tap_conf_get(const stmdev_ctx_t * ctx,iis2dh_click_cfg_t * val)2182 int32_t iis2dh_tap_conf_get(const stmdev_ctx_t *ctx,
2183 iis2dh_click_cfg_t *val)
2184 {
2185 int32_t ret;
2186
2187 ret = iis2dh_read_reg(ctx, IIS2DH_CLICK_CFG, (uint8_t *) val, 1);
2188
2189 return ret;
2190 }
2191 /**
2192 * @brief Tap/Double Tap generator source register.[get]
2193 *
2194 * @param ctx read / write interface definitions
2195 * @param val registers CLICK_SRC
2196 * @retval interface status (MANDATORY: return 0 -> no Error)
2197 *
2198 */
iis2dh_tap_source_get(const stmdev_ctx_t * ctx,iis2dh_click_src_t * val)2199 int32_t iis2dh_tap_source_get(const stmdev_ctx_t *ctx,
2200 iis2dh_click_src_t *val)
2201 {
2202 int32_t ret;
2203
2204 ret = iis2dh_read_reg(ctx, IIS2DH_CLICK_SRC, (uint8_t *) val, 1);
2205
2206 return ret;
2207 }
2208 /**
2209 * @brief User-defined threshold value for Tap/Double Tap event.[set]
2210 * 1 LSB = full scale/128
2211 *
2212 * @param ctx read / write interface definitions
2213 * @param val change the values of ths in reg CLICK_THS
2214 * @retval interface status (MANDATORY: return 0 -> no Error)
2215 *
2216 */
iis2dh_tap_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)2217 int32_t iis2dh_tap_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
2218 {
2219 iis2dh_click_ths_t click_ths;
2220 int32_t ret;
2221
2222 ret = iis2dh_read_reg(ctx, IIS2DH_CLICK_THS, (uint8_t *)&click_ths, 1);
2223
2224 if (ret == 0)
2225 {
2226 click_ths.ths = val;
2227 ret = iis2dh_write_reg(ctx, IIS2DH_CLICK_THS, (uint8_t *)&click_ths, 1);
2228 }
2229
2230 return ret;
2231 }
2232
2233 /**
2234 * @brief User-defined threshold value for Tap/Double Tap event.[get]
2235 * 1 LSB = full scale/128
2236 *
2237 * @param ctx read / write interface definitions
2238 * @param val change the values of ths in reg CLICK_THS
2239 * @retval interface status (MANDATORY: return 0 -> no Error)
2240 *
2241 */
iis2dh_tap_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)2242 int32_t iis2dh_tap_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
2243 {
2244 iis2dh_click_ths_t click_ths;
2245 int32_t ret;
2246
2247 ret = iis2dh_read_reg(ctx, IIS2DH_CLICK_THS, (uint8_t *)&click_ths, 1);
2248 *val = (uint8_t)click_ths.ths;
2249
2250 return ret;
2251 }
2252
2253 /**
2254 * @brief The maximum time (1 LSB = 1/ODR) interval that can elapse
2255 * between the start of the click-detection procedure and when the
2256 * acceleration falls back below the threshold.[set]
2257 *
2258 * @param ctx read / write interface definitions
2259 * @param val change the values of tli in reg TIME_LIMIT
2260 * @retval interface status (MANDATORY: return 0 -> no Error)
2261 *
2262 */
iis2dh_shock_dur_set(const stmdev_ctx_t * ctx,uint8_t val)2263 int32_t iis2dh_shock_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
2264 {
2265 iis2dh_time_limit_t time_limit;
2266 int32_t ret;
2267
2268 ret = iis2dh_read_reg(ctx, IIS2DH_TIME_LIMIT, (uint8_t *)&time_limit, 1);
2269
2270 if (ret == 0)
2271 {
2272 time_limit.tli = val;
2273 ret = iis2dh_write_reg(ctx, IIS2DH_TIME_LIMIT, (uint8_t *)&time_limit, 1);
2274 }
2275
2276 return ret;
2277 }
2278
2279 /**
2280 * @brief The maximum time (1 LSB = 1/ODR) interval that can elapse between
2281 * the start of the click-detection procedure and when the
2282 * acceleration falls back below the threshold.[get]
2283 *
2284 * @param ctx read / write interface definitions
2285 * @param val change the values of tli in reg TIME_LIMIT
2286 * @retval interface status (MANDATORY: return 0 -> no Error)
2287 *
2288 */
iis2dh_shock_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)2289 int32_t iis2dh_shock_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
2290 {
2291 iis2dh_time_limit_t time_limit;
2292 int32_t ret;
2293
2294 ret = iis2dh_read_reg(ctx, IIS2DH_TIME_LIMIT, (uint8_t *)&time_limit, 1);
2295 *val = (uint8_t)time_limit.tli;
2296
2297 return ret;
2298 }
2299
2300 /**
2301 * @brief The time (1 LSB = 1/ODR) interval that starts after the first
2302 * click detection where the click-detection procedure is
2303 * disabled, in cases where the device is configured for
2304 * double-click detection.[set]
2305 *
2306 * @param ctx read / write interface definitions
2307 * @param val change the values of tla in reg TIME_LATENCY
2308 * @retval interface status (MANDATORY: return 0 -> no Error)
2309 *
2310 */
iis2dh_quiet_dur_set(const stmdev_ctx_t * ctx,uint8_t val)2311 int32_t iis2dh_quiet_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
2312 {
2313 iis2dh_time_latency_t time_latency;
2314 int32_t ret;
2315
2316 ret = iis2dh_read_reg(ctx, IIS2DH_TIME_LATENCY,
2317 (uint8_t *)&time_latency, 1);
2318
2319 if (ret == 0)
2320 {
2321 time_latency.tla = val;
2322 ret = iis2dh_write_reg(ctx, IIS2DH_TIME_LATENCY,
2323 (uint8_t *)&time_latency, 1);
2324 }
2325
2326 return ret;
2327 }
2328
2329 /**
2330 * @brief The time (1 LSB = 1/ODR) interval that starts after the first
2331 * click detection where the click-detection procedure is
2332 * disabled, in cases where the device is configured for
2333 * double-click detection.[get]
2334 *
2335 * @param ctx read / write interface definitions
2336 * @param val change the values of tla in reg TIME_LATENCY
2337 * @retval interface status (MANDATORY: return 0 -> no Error)
2338 *
2339 */
iis2dh_quiet_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)2340 int32_t iis2dh_quiet_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
2341 {
2342 iis2dh_time_latency_t time_latency;
2343 int32_t ret;
2344
2345 ret = iis2dh_read_reg(ctx, IIS2DH_TIME_LATENCY,
2346 (uint8_t *)&time_latency, 1);
2347 *val = (uint8_t)time_latency.tla;
2348
2349 return ret;
2350 }
2351
2352 /**
2353 * @brief The maximum interval of time (1 LSB = 1/ODR) that can elapse
2354 * after the end of the latency interval in which the click-detection
2355 * procedure can start, in cases where the device is configured
2356 * for double-click detection.[set]
2357 *
2358 * @param ctx read / write interface definitions
2359 * @param val change the values of tw in reg TIME_WINDOW
2360 * @retval interface status (MANDATORY: return 0 -> no Error)
2361 *
2362 */
iis2dh_double_tap_timeout_set(const stmdev_ctx_t * ctx,uint8_t val)2363 int32_t iis2dh_double_tap_timeout_set(const stmdev_ctx_t *ctx, uint8_t val)
2364 {
2365 iis2dh_time_window_t time_window;
2366 int32_t ret;
2367
2368 ret = iis2dh_read_reg(ctx, IIS2DH_TIME_WINDOW,
2369 (uint8_t *)&time_window, 1);
2370
2371 if (ret == 0)
2372 {
2373 time_window.tw = val;
2374 ret = iis2dh_write_reg(ctx, IIS2DH_TIME_WINDOW,
2375 (uint8_t *)&time_window, 1);
2376 }
2377
2378 return ret;
2379 }
2380
2381 /**
2382 * @brief The maximum interval of time (1 LSB = 1/ODR) that can elapse
2383 * after the end of the latency interval in which the
2384 * click-detection procedure can start, in cases where the device
2385 * is configured for double-click detection.[get]
2386 *
2387 * @param ctx read / write interface definitions
2388 * @param val change the values of tw in reg TIME_WINDOW
2389 * @retval interface status (MANDATORY: return 0 -> no Error)
2390 *
2391 */
iis2dh_double_tap_timeout_get(const stmdev_ctx_t * ctx,uint8_t * val)2392 int32_t iis2dh_double_tap_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val)
2393 {
2394 iis2dh_time_window_t time_window;
2395 int32_t ret;
2396
2397 ret = iis2dh_read_reg(ctx, IIS2DH_TIME_WINDOW,
2398 (uint8_t *)&time_window, 1);
2399 *val = (uint8_t)time_window.tw;
2400
2401 return ret;
2402 }
2403
2404 /**
2405 * @}
2406 *
2407 */
2408
2409 /**
2410 * @defgroup IIS2DH_Activity_inactivity
2411 * @brief This section group all the functions concerning activity
2412 * inactivity functionality
2413 * @{
2414 *
2415 */
2416
2417 /**
2418 * @brief Sleep-to-wake, return-to-sleep activation threshold in
2419 * low-power mode.[set]
2420 * 1 LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
2421 *
2422 * @param ctx read / write interface definitions
2423 * @param val change the values of acth in reg ACT_THS
2424 * @retval interface status (MANDATORY: return 0 -> no Error)
2425 *
2426 */
iis2dh_act_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)2427 int32_t iis2dh_act_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
2428 {
2429 iis2dh_act_ths_t act_ths;
2430 int32_t ret;
2431
2432 ret = iis2dh_read_reg(ctx, IIS2DH_ACT_THS, (uint8_t *)&act_ths, 1);
2433
2434 if (ret == 0)
2435 {
2436 act_ths.acth = val;
2437 ret = iis2dh_write_reg(ctx, IIS2DH_ACT_THS, (uint8_t *)&act_ths, 1);
2438 }
2439
2440 return ret;
2441 }
2442
2443 /**
2444 * @brief Sleep-to-wake, return-to-sleep activation threshold in low-power
2445 * mode.[get]
2446 * 1 LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
2447 *
2448 * @param ctx read / write interface definitions
2449 * @param val change the values of acth in reg ACT_THS
2450 * @retval interface status (MANDATORY: return 0 -> no Error)
2451 *
2452 */
iis2dh_act_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)2453 int32_t iis2dh_act_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
2454 {
2455 iis2dh_act_ths_t act_ths;
2456 int32_t ret;
2457
2458 ret = iis2dh_read_reg(ctx, IIS2DH_ACT_THS, (uint8_t *)&act_ths, 1);
2459 *val = (uint8_t)act_ths.acth;
2460
2461 return ret;
2462 }
2463
2464 /**
2465 * @brief Sleep-to-wake, return-to-sleep.[set]
2466 * duration = (8*1[LSb]+1)/ODR
2467 *
2468 * @param ctx read / write interface definitions
2469 * @param val change the values of actd in reg ACT_DUR
2470 * @retval interface status (MANDATORY: return 0 -> no Error)
2471 *
2472 */
iis2dh_act_timeout_set(const stmdev_ctx_t * ctx,uint8_t val)2473 int32_t iis2dh_act_timeout_set(const stmdev_ctx_t *ctx, uint8_t val)
2474 {
2475 iis2dh_act_dur_t act_dur;
2476 int32_t ret;
2477
2478 ret = iis2dh_read_reg(ctx, IIS2DH_ACT_DUR, (uint8_t *)&act_dur, 1);
2479
2480 if (ret == 0)
2481 {
2482 act_dur.actd = val;
2483 ret = iis2dh_write_reg(ctx, IIS2DH_ACT_DUR, (uint8_t *)&act_dur, 1);
2484 }
2485
2486 return ret;
2487 }
2488
2489 /**
2490 * @brief Sleep-to-wake, return-to-sleep.[get]
2491 * duration = (8*1[LSb]+1)/ODR
2492 *
2493 * @param ctx read / write interface definitions
2494 * @param val change the values of actd in reg ACT_DUR
2495 * @retval interface status (MANDATORY: return 0 -> no Error)
2496 *
2497 */
iis2dh_act_timeout_get(const stmdev_ctx_t * ctx,uint8_t * val)2498 int32_t iis2dh_act_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val)
2499 {
2500 iis2dh_act_dur_t act_dur;
2501 int32_t ret;
2502
2503 ret = iis2dh_read_reg(ctx, IIS2DH_ACT_DUR, (uint8_t *)&act_dur, 1);
2504 *val = (uint8_t)act_dur.actd;
2505
2506 return ret;
2507 }
2508
2509 /**
2510 * @}
2511 *
2512 */
2513
2514 /**
2515 * @defgroup IIS2DH_Serial_interface
2516 * @brief This section group all the functions concerning serial
2517 * interface management
2518 * @{
2519 *
2520 */
2521
2522 /**
2523 * @brief SPI Serial Interface Mode selection.[set]
2524 *
2525 * @param ctx read / write interface definitions
2526 * @param val change the values of sim in reg CTRL_REG4
2527 * @retval interface status (MANDATORY: return 0 -> no Error)
2528 *
2529 */
iis2dh_spi_mode_set(const stmdev_ctx_t * ctx,iis2dh_sim_t val)2530 int32_t iis2dh_spi_mode_set(const stmdev_ctx_t *ctx, iis2dh_sim_t val)
2531 {
2532 iis2dh_ctrl_reg4_t ctrl_reg4;
2533 int32_t ret;
2534
2535 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
2536
2537 if (ret == 0)
2538 {
2539 ctrl_reg4.sim = (uint8_t)val;
2540 ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
2541 }
2542
2543 return ret;
2544 }
2545
2546 /**
2547 * @brief SPI Serial Interface Mode selection.[get]
2548 *
2549 * @param ctx read / write interface definitions
2550 * @param val Get the values of sim in reg CTRL_REG4
2551 * @retval interface status (MANDATORY: return 0 -> no Error)
2552 *
2553 */
iis2dh_spi_mode_get(const stmdev_ctx_t * ctx,iis2dh_sim_t * val)2554 int32_t iis2dh_spi_mode_get(const stmdev_ctx_t *ctx, iis2dh_sim_t *val)
2555 {
2556 iis2dh_ctrl_reg4_t ctrl_reg4;
2557 int32_t ret;
2558
2559 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
2560
2561 switch (ctrl_reg4.sim)
2562 {
2563 case IIS2DH_SPI_4_WIRE:
2564 *val = IIS2DH_SPI_4_WIRE;
2565 break;
2566
2567 case IIS2DH_SPI_3_WIRE:
2568 *val = IIS2DH_SPI_3_WIRE;
2569 break;
2570
2571 default:
2572 *val = IIS2DH_SPI_4_WIRE;
2573 break;
2574 }
2575
2576 return ret;
2577 }
2578
2579 /**
2580 * @}
2581 *
2582 */
2583
2584 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2585
