1 /**
2 ******************************************************************************
3 * @file ais2ih_reg.c
4 * @author Sensors Software Solution Team
5 * @brief AIS2IH driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "ais2ih_reg.h"
21
22 /**
23 * @defgroup AIS2IH
24 * @brief This file provides a set of functions needed to drive the
25 * ais2ih enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup AIS2IH_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
ais2ih_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak ais2ih_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
50 uint16_t len)
51 {
52 int32_t ret;
53
54 if (ctx == NULL) return -1;
55
56 ret = ctx->read_reg(ctx->handle, reg, data, len);
57
58 return ret;
59 }
60
61 /**
62 * @brief Write generic device register
63 *
64 * @param ctx read / write interface definitions(ptr)
65 * @param reg register to write
66 * @param data pointer to data to write in register reg(ptr)
67 * @param len number of consecutive register to write
68 * @retval interface status (MANDATORY: return 0 -> no Error)
69 *
70 */
ais2ih_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)71 int32_t __weak ais2ih_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
72 uint8_t *data,
73 uint16_t len)
74 {
75 int32_t ret;
76
77 if (ctx == NULL) return -1;
78
79 ret = ctx->write_reg(ctx->handle, reg, data, len);
80
81 return ret;
82 }
83
84 /**
85 * @}
86 *
87 */
88
89 /**
90 * @defgroup AIS2IH_Sensitivity
91 * @brief These functions convert raw-data into engineering units.
92 * @{
93 *
94 */
95
ais2ih_from_fs2_to_mg(int16_t lsb)96 float_t ais2ih_from_fs2_to_mg(int16_t lsb)
97 {
98 return ((float_t)lsb) * 0.061f;
99 }
100
ais2ih_from_fs4_to_mg(int16_t lsb)101 float_t ais2ih_from_fs4_to_mg(int16_t lsb)
102 {
103 return ((float_t)lsb) * 0.122f;
104 }
105
ais2ih_from_fs8_to_mg(int16_t lsb)106 float_t ais2ih_from_fs8_to_mg(int16_t lsb)
107 {
108 return ((float_t)lsb) * 0.244f;
109 }
110
ais2ih_from_fs16_to_mg(int16_t lsb)111 float_t ais2ih_from_fs16_to_mg(int16_t lsb)
112 {
113 return ((float_t)lsb) * 0.488f;
114 }
115
ais2ih_from_fs2_lp1_to_mg(int16_t lsb)116 float_t ais2ih_from_fs2_lp1_to_mg(int16_t lsb)
117 {
118 return ((float_t)lsb) * 0.061f;
119 }
120
ais2ih_from_fs4_lp1_to_mg(int16_t lsb)121 float_t ais2ih_from_fs4_lp1_to_mg(int16_t lsb)
122 {
123 return ((float_t)lsb) * 0.122f;
124 }
125
ais2ih_from_fs8_lp1_to_mg(int16_t lsb)126 float_t ais2ih_from_fs8_lp1_to_mg(int16_t lsb)
127 {
128 return ((float_t)lsb) * 0.244f;
129 }
130
ais2ih_from_fs16_lp1_to_mg(int16_t lsb)131 float_t ais2ih_from_fs16_lp1_to_mg(int16_t lsb)
132 {
133 return ((float_t)lsb) * 0.488f;
134 }
135
ais2ih_from_lsb_to_celsius(int16_t lsb)136 float_t ais2ih_from_lsb_to_celsius(int16_t lsb)
137 {
138 return (((float_t)lsb / 256.0f) + 25.0f);
139 }
140
141 /**
142 * @}
143 *
144 */
145
146 /**
147 * @defgroup AIS2IH_Data_Generation
148 * @brief This section groups all the functions concerning
149 * data generation
150 * @{
151 *
152 */
153
154 /**
155 * @brief Select accelerometer operating modes.[set]
156 *
157 * @param ctx read / write interface definitions
158 * @param val change the values of mode / lp_mode in reg CTRL1
159 * and low_noise in reg CTRL6
160 * @retval interface status (MANDATORY: return 0 -> no Error)
161 *
162 */
ais2ih_power_mode_set(const stmdev_ctx_t * ctx,ais2ih_mode_t val)163 int32_t ais2ih_power_mode_set(const stmdev_ctx_t *ctx, ais2ih_mode_t val)
164 {
165 ais2ih_ctrl1_t ctrl1;
166 ais2ih_ctrl6_t ctrl6;
167 int32_t ret;
168
169 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL1, (uint8_t *) &ctrl1, 1);
170
171 if (ret == 0)
172 {
173 ctrl1.mode = ((uint8_t) val & 0x0CU) >> 2;
174 ctrl1.lp_mode = (uint8_t) val & 0x03U ;
175 ret = ais2ih_write_reg(ctx, AIS2IH_CTRL1, (uint8_t *) &ctrl1, 1);
176 }
177
178 if (ret == 0)
179 {
180 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL6, (uint8_t *) &ctrl6, 1);
181 }
182
183 if (ret == 0)
184 {
185 ctrl6.low_noise = ((uint8_t) val & 0x10U) >> 4;
186 ret = ais2ih_write_reg(ctx, AIS2IH_CTRL6, (uint8_t *) &ctrl6, 1);
187 }
188
189 return ret;
190 }
191
192 /**
193 * @brief Select accelerometer operating modes.[get]
194 *
195 * @param ctx read / write interface definitions
196 * @param val change the values of mode / lp_mode in reg CTRL1
197 * and low_noise in reg CTRL6
198 * @retval interface status (MANDATORY: return 0 -> no Error)
199 *
200 */
ais2ih_power_mode_get(const stmdev_ctx_t * ctx,ais2ih_mode_t * val)201 int32_t ais2ih_power_mode_get(const stmdev_ctx_t *ctx, ais2ih_mode_t *val)
202 {
203 ais2ih_ctrl1_t ctrl1;
204 ais2ih_ctrl6_t ctrl6;
205 int32_t ret;
206
207 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL1, (uint8_t *) &ctrl1, 1);
208
209 if (ret == 0)
210 {
211 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL6, (uint8_t *) &ctrl6, 1);
212
213 switch (((ctrl6.low_noise << 4) + (ctrl1.mode << 2) +
214 ctrl1.lp_mode))
215 {
216 case AIS2IH_HIGH_PERFORMANCE:
217 *val = AIS2IH_HIGH_PERFORMANCE;
218 break;
219
220 case AIS2IH_CONT_LOW_PWR_4:
221 *val = AIS2IH_CONT_LOW_PWR_4;
222 break;
223
224 case AIS2IH_CONT_LOW_PWR_3:
225 *val = AIS2IH_CONT_LOW_PWR_3;
226 break;
227
228 case AIS2IH_CONT_LOW_PWR_2:
229 *val = AIS2IH_CONT_LOW_PWR_2;
230 break;
231
232 case AIS2IH_CONT_LOW_PWR_12bit:
233 *val = AIS2IH_CONT_LOW_PWR_12bit;
234 break;
235
236 case AIS2IH_SINGLE_LOW_PWR_4:
237 *val = AIS2IH_SINGLE_LOW_PWR_4;
238 break;
239
240 case AIS2IH_SINGLE_LOW_PWR_3:
241 *val = AIS2IH_SINGLE_LOW_PWR_3;
242 break;
243
244 case AIS2IH_SINGLE_LOW_PWR_2:
245 *val = AIS2IH_SINGLE_LOW_PWR_2;
246 break;
247
248 case AIS2IH_SINGLE_LOW_PWR_12bit:
249 *val = AIS2IH_SINGLE_LOW_PWR_12bit;
250 break;
251
252 case AIS2IH_HIGH_PERFORMANCE_LOW_NOISE:
253 *val = AIS2IH_HIGH_PERFORMANCE_LOW_NOISE;
254 break;
255
256 case AIS2IH_CONT_LOW_PWR_LOW_NOISE_4:
257 *val = AIS2IH_CONT_LOW_PWR_LOW_NOISE_4;
258 break;
259
260 case AIS2IH_CONT_LOW_PWR_LOW_NOISE_3:
261 *val = AIS2IH_CONT_LOW_PWR_LOW_NOISE_3;
262 break;
263
264 case AIS2IH_CONT_LOW_PWR_LOW_NOISE_2:
265 *val = AIS2IH_CONT_LOW_PWR_LOW_NOISE_2;
266 break;
267
268 case AIS2IH_CONT_LOW_PWR_LOW_NOISE_12bit:
269 *val = AIS2IH_CONT_LOW_PWR_LOW_NOISE_12bit;
270 break;
271
272 case AIS2IH_SINGLE_LOW_PWR_LOW_NOISE_4:
273 *val = AIS2IH_SINGLE_LOW_PWR_LOW_NOISE_4;
274 break;
275
276 case AIS2IH_SINGLE_LOW_PWR_LOW_NOISE_3:
277 *val = AIS2IH_SINGLE_LOW_PWR_LOW_NOISE_3;
278 break;
279
280 case AIS2IH_SINGLE_LOW_PWR_LOW_NOISE_2:
281 *val = AIS2IH_SINGLE_LOW_PWR_LOW_NOISE_2;
282 break;
283
284 case AIS2IH_SINGLE_LOW_LOW_NOISE_PWR_12bit:
285 *val = AIS2IH_SINGLE_LOW_LOW_NOISE_PWR_12bit;
286 break;
287
288 default:
289 *val = AIS2IH_HIGH_PERFORMANCE;
290 break;
291 }
292 }
293
294 return ret;
295 }
296
297 /**
298 * @brief Accelerometer data rate selection.[set]
299 *
300 * @param ctx read / write interface definitions
301 * @param val change the values of odr in reg CTRL1
302 * @retval interface status (MANDATORY: return 0 -> no Error)
303 *
304 */
ais2ih_data_rate_set(const stmdev_ctx_t * ctx,ais2ih_odr_t val)305 int32_t ais2ih_data_rate_set(const stmdev_ctx_t *ctx, ais2ih_odr_t val)
306 {
307 ais2ih_ctrl1_t ctrl1;
308 ais2ih_ctrl3_t ctrl3;
309 int32_t ret;
310
311 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL1, (uint8_t *) &ctrl1, 1);
312
313 if (ret == 0)
314 {
315 ctrl1.odr = (uint8_t) val;
316 ret = ais2ih_write_reg(ctx, AIS2IH_CTRL1, (uint8_t *) &ctrl1, 1);
317 }
318
319 if (ret == 0)
320 {
321 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL3, (uint8_t *) &ctrl3, 1);
322 }
323
324 if (ret == 0)
325 {
326 ctrl3.slp_mode = ((uint8_t) val & 0x30U) >> 4;
327 ret = ais2ih_write_reg(ctx, AIS2IH_CTRL3, (uint8_t *) &ctrl3, 1);
328 }
329
330 return ret;
331 }
332
333 /**
334 * @brief Accelerometer data rate selection.[get]
335 *
336 * @param ctx read / write interface definitions
337 * @param val Get the values of odr in reg CTRL1
338 * @retval interface status (MANDATORY: return 0 -> no Error)
339 *
340 */
ais2ih_data_rate_get(const stmdev_ctx_t * ctx,ais2ih_odr_t * val)341 int32_t ais2ih_data_rate_get(const stmdev_ctx_t *ctx, ais2ih_odr_t *val)
342 {
343 ais2ih_ctrl1_t ctrl1;
344 ais2ih_ctrl3_t ctrl3;
345 int32_t ret;
346
347 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL1, (uint8_t *) &ctrl1, 1);
348
349 if (ret == 0)
350 {
351 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL3, (uint8_t *) &ctrl3, 1);
352
353 switch ((ctrl3.slp_mode << 4) + ctrl1.odr)
354 {
355 case AIS2IH_XL_ODR_OFF:
356 *val = AIS2IH_XL_ODR_OFF;
357 break;
358
359 case AIS2IH_XL_ODR_1Hz6_LP_ONLY:
360 *val = AIS2IH_XL_ODR_1Hz6_LP_ONLY;
361 break;
362
363 case AIS2IH_XL_ODR_12Hz5:
364 *val = AIS2IH_XL_ODR_12Hz5;
365 break;
366
367 case AIS2IH_XL_ODR_25Hz:
368 *val = AIS2IH_XL_ODR_25Hz;
369 break;
370
371 case AIS2IH_XL_ODR_50Hz:
372 *val = AIS2IH_XL_ODR_50Hz;
373 break;
374
375 case AIS2IH_XL_ODR_100Hz:
376 *val = AIS2IH_XL_ODR_100Hz;
377 break;
378
379 case AIS2IH_XL_ODR_200Hz:
380 *val = AIS2IH_XL_ODR_200Hz;
381 break;
382
383 case AIS2IH_XL_ODR_400Hz:
384 *val = AIS2IH_XL_ODR_400Hz;
385 break;
386
387 case AIS2IH_XL_ODR_800Hz:
388 *val = AIS2IH_XL_ODR_800Hz;
389 break;
390
391 case AIS2IH_XL_ODR_1k6Hz:
392 *val = AIS2IH_XL_ODR_1k6Hz;
393 break;
394
395 case AIS2IH_XL_SET_SW_TRIG:
396 *val = AIS2IH_XL_SET_SW_TRIG;
397 break;
398
399 case AIS2IH_XL_SET_PIN_TRIG:
400 *val = AIS2IH_XL_SET_PIN_TRIG;
401 break;
402
403 default:
404 *val = AIS2IH_XL_ODR_OFF;
405 break;
406 }
407 }
408
409 return ret;
410 }
411
412 /**
413 * @brief Block data update.[set]
414 *
415 * @param ctx read / write interface definitions
416 * @param val change the values of bdu in reg CTRL2
417 * @retval interface status (MANDATORY: return 0 -> no Error)
418 *
419 */
ais2ih_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)420 int32_t ais2ih_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val)
421 {
422 ais2ih_ctrl2_t reg;
423 int32_t ret;
424
425 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1);
426
427 if (ret == 0)
428 {
429 reg.bdu = val;
430 ret = ais2ih_write_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1);
431 }
432
433 return ret;
434 }
435
436 /**
437 * @brief Block data update.[get]
438 *
439 * @param ctx read / write interface definitions
440 * @param val change the values of bdu in reg CTRL2
441 * @retval interface status (MANDATORY: return 0 -> no Error)
442 *
443 */
ais2ih_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)444 int32_t ais2ih_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val)
445 {
446 ais2ih_ctrl2_t reg;
447 int32_t ret;
448
449 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1);
450 *val = reg.bdu;
451
452 return ret;
453 }
454
455 /**
456 * @brief Accelerometer full-scale selection.[set]
457 *
458 * @param ctx read / write interface definitions
459 * @param val change the values of fs in reg CTRL6
460 * @retval interface status (MANDATORY: return 0 -> no Error)
461 *
462 */
ais2ih_full_scale_set(const stmdev_ctx_t * ctx,ais2ih_fs_t val)463 int32_t ais2ih_full_scale_set(const stmdev_ctx_t *ctx, ais2ih_fs_t val)
464 {
465 ais2ih_ctrl6_t reg;
466 int32_t ret;
467
468 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL6, (uint8_t *) ®, 1);
469
470 if (ret == 0)
471 {
472 reg.fs = (uint8_t) val;
473 ret = ais2ih_write_reg(ctx, AIS2IH_CTRL6, (uint8_t *) ®, 1);
474 }
475
476 return ret;
477 }
478
479 /**
480 * @brief Accelerometer full-scale selection.[get]
481 *
482 * @param ctx read / write interface definitions
483 * @param val Get the values of fs in reg CTRL6
484 * @retval interface status (MANDATORY: return 0 -> no Error)
485 *
486 */
ais2ih_full_scale_get(const stmdev_ctx_t * ctx,ais2ih_fs_t * val)487 int32_t ais2ih_full_scale_get(const stmdev_ctx_t *ctx, ais2ih_fs_t *val)
488 {
489 ais2ih_ctrl6_t reg;
490 int32_t ret;
491
492 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL6, (uint8_t *) ®, 1);
493
494 switch (reg.fs)
495 {
496 case AIS2IH_2g:
497 *val = AIS2IH_2g;
498 break;
499
500 case AIS2IH_4g:
501 *val = AIS2IH_4g;
502 break;
503
504 case AIS2IH_8g:
505 *val = AIS2IH_8g;
506 break;
507
508 case AIS2IH_16g:
509 *val = AIS2IH_16g;
510 break;
511
512 default:
513 *val = AIS2IH_2g;
514 break;
515 }
516
517 return ret;
518 }
519
520 /**
521 * @brief The STATUS_REG register of the device.[get]
522 *
523 * @param ctx read / write interface definitions
524 * @param val union of registers from STATUS to
525 * @retval interface status (MANDATORY: return 0 -> no Error)
526 *
527 */
ais2ih_status_reg_get(const stmdev_ctx_t * ctx,ais2ih_status_t * val)528 int32_t ais2ih_status_reg_get(const stmdev_ctx_t *ctx, ais2ih_status_t *val)
529 {
530 int32_t ret;
531
532 ret = ais2ih_read_reg(ctx, AIS2IH_STATUS, (uint8_t *) val, 1);
533
534 return ret;
535 }
536
537 /**
538 * @brief Accelerometer new data available.[get]
539 *
540 * @param ctx read / write interface definitions
541 * @param val change the values of drdy in reg STATUS
542 * @retval interface status (MANDATORY: return 0 -> no Error)
543 *
544 */
ais2ih_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)545 int32_t ais2ih_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val)
546 {
547 ais2ih_status_t reg;
548 int32_t ret;
549
550 ret = ais2ih_read_reg(ctx, AIS2IH_STATUS, (uint8_t *) ®, 1);
551 *val = reg.drdy;
552
553 return ret;
554 }
555 /**
556 * @brief Read all the interrupt/status flag of the device.[get]
557 *
558 * @param ctx read / write interface definitions
559 * @param val registers STATUS_DUP, WAKE_UP_SRC,
560 * TAP_SRC, SIXD_SRC, ALL_INT_SRC
561 * @retval interface status (MANDATORY: return 0 -> no Error)
562 *
563 */
ais2ih_all_sources_get(const stmdev_ctx_t * ctx,ais2ih_all_sources_t * val)564 int32_t ais2ih_all_sources_get(const stmdev_ctx_t *ctx,
565 ais2ih_all_sources_t *val)
566 {
567 int32_t ret;
568
569 ret = ais2ih_read_reg(ctx, AIS2IH_STATUS_DUP, (uint8_t *) val, 5);
570
571 return ret;
572 }
573
574 /**
575 * @brief Accelerometer X-axis user offset correction expressed in two’s
576 * complement, weight depends on bit USR_OFF_W. The value must be
577 * in the range [-127 127].[set]
578 *
579 * @param ctx read / write interface definitions
580 * @param buff buffer that contains data to write
581 * @retval interface status (MANDATORY: return 0 -> no Error)
582 *
583 */
ais2ih_usr_offset_x_set(const stmdev_ctx_t * ctx,uint8_t * buff)584 int32_t ais2ih_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff)
585 {
586 int32_t ret;
587
588 ret = ais2ih_write_reg(ctx, AIS2IH_X_OFS_USR, buff, 1);
589
590 return ret;
591 }
592
593 /**
594 * @brief Accelerometer X-axis user offset correction expressed in two’s
595 * complement, weight depends on bit USR_OFF_W. The value must be
596 * in the range [-127 127].[get]
597 *
598 * @param ctx read / write interface definitions
599 * @param buff buffer that stores data read
600 * @retval interface status (MANDATORY: return 0 -> no Error)
601 *
602 */
ais2ih_usr_offset_x_get(const stmdev_ctx_t * ctx,uint8_t * buff)603 int32_t ais2ih_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff)
604 {
605 int32_t ret;
606
607 ret = ais2ih_read_reg(ctx, AIS2IH_X_OFS_USR, buff, 1);
608
609 return ret;
610 }
611
612 /**
613 * @brief Accelerometer Y-axis user offset correction expressed in two’s
614 * complement, weight depends on bit USR_OFF_W. The value must be
615 * in the range [-127 127].[set]
616 *
617 * @param ctx read / write interface definitions
618 * @param buff buffer that contains data to write
619 * @retval interface status (MANDATORY: return 0 -> no Error)
620 *
621 */
ais2ih_usr_offset_y_set(const stmdev_ctx_t * ctx,uint8_t * buff)622 int32_t ais2ih_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff)
623 {
624 int32_t ret;
625
626 ret = ais2ih_write_reg(ctx, AIS2IH_Y_OFS_USR, buff, 1);
627
628 return ret;
629 }
630
631 /**
632 * @brief Accelerometer Y-axis user offset correction expressed in two’s
633 * complement, weight depends on bit USR_OFF_W. The value must be
634 * in the range [-127 127].[get]
635 *
636 * @param ctx read / write interface definitions
637 * @param buff buffer that stores data read
638 * @retval interface status (MANDATORY: return 0 -> no Error)
639 *
640 */
ais2ih_usr_offset_y_get(const stmdev_ctx_t * ctx,uint8_t * buff)641 int32_t ais2ih_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff)
642 {
643 int32_t ret;
644
645 ret = ais2ih_read_reg(ctx, AIS2IH_Y_OFS_USR, buff, 1);
646
647 return ret;
648 }
649
650 /**
651 * @brief Accelerometer Z-axis user offset correction expressed in two’s
652 * complement, weight depends on bit USR_OFF_W. The value must be
653 * in the range [-127 127].[set]
654 *
655 * @param ctx read / write interface definitions
656 * @param buff buffer that contains data to write
657 * @retval interface status (MANDATORY: return 0 -> no Error)
658 *
659 */
ais2ih_usr_offset_z_set(const stmdev_ctx_t * ctx,uint8_t * buff)660 int32_t ais2ih_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff)
661 {
662 int32_t ret;
663
664 ret = ais2ih_write_reg(ctx, AIS2IH_Z_OFS_USR, buff, 1);
665
666 return ret;
667 }
668
669 /**
670 * @brief Accelerometer Z-axis user offset correction expressed in two’s
671 * complement, weight depends on bit USR_OFF_W. The value must be
672 * in the range [-127 127].[get]
673 *
674 * @param ctx read / write interface definitions
675 * @param buff buffer that stores data read
676 * @retval interface status (MANDATORY: return 0 -> no Error)
677 *
678 */
ais2ih_usr_offset_z_get(const stmdev_ctx_t * ctx,uint8_t * buff)679 int32_t ais2ih_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff)
680 {
681 int32_t ret;
682
683 ret = ais2ih_read_reg(ctx, AIS2IH_Z_OFS_USR, buff, 1);
684
685 return ret;
686 }
687
688 /**
689 * @brief Weight of XL user offset bits of registers X_OFS_USR,
690 * Y_OFS_USR, Z_OFS_USR.[set]
691 *
692 * @param ctx read / write interface definitions
693 * @param val change the values of usr_off_w in
694 * reg CTRL_REG7
695 * @retval interface status (MANDATORY: return 0 -> no Error)
696 *
697 */
ais2ih_offset_weight_set(const stmdev_ctx_t * ctx,ais2ih_usr_off_w_t val)698 int32_t ais2ih_offset_weight_set(const stmdev_ctx_t *ctx,
699 ais2ih_usr_off_w_t val)
700 {
701 ais2ih_ctrl_reg7_t reg;
702 int32_t ret;
703
704 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1);
705
706 if (ret == 0)
707 {
708 reg.usr_off_w = (uint8_t) val;
709 ret = ais2ih_write_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1);
710 }
711
712 return ret;
713 }
714
715 /**
716 * @brief Weight of XL user offset bits of registers X_OFS_USR,
717 * Y_OFS_USR, Z_OFS_USR.[get]
718 *
719 * @param ctx read / write interface definitions
720 * @param val Get the values of usr_off_w in reg CTRL_REG7
721 * @retval interface status (MANDATORY: return 0 -> no Error)
722 *
723 */
ais2ih_offset_weight_get(const stmdev_ctx_t * ctx,ais2ih_usr_off_w_t * val)724 int32_t ais2ih_offset_weight_get(const stmdev_ctx_t *ctx,
725 ais2ih_usr_off_w_t *val)
726 {
727 ais2ih_ctrl_reg7_t reg;
728 int32_t ret;
729
730 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1);
731
732 switch (reg.usr_off_w)
733 {
734 case AIS2IH_LSb_977ug:
735 *val = AIS2IH_LSb_977ug;
736 break;
737
738 case AIS2IH_LSb_15mg6:
739 *val = AIS2IH_LSb_15mg6;
740 break;
741
742 default:
743 *val = AIS2IH_LSb_977ug;
744 break;
745 }
746
747 return ret;
748 }
749
750 /**
751 * @}
752 *
753 */
754
755 /**
756 * @defgroup AIS2IH_Data_Output
757 * @brief This section groups all the data output functions.
758 * @{
759 *
760 */
761
762 /**
763 * @brief Temperature data output register (r). L and H registers
764 * together express a 16-bit word in two’s complement.[get]
765 *
766 * @param ctx read / write interface definitions
767 * @param val buffer that stores data read
768 * @retval interface status (MANDATORY: return 0 -> no Error)
769 *
770 */
ais2ih_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * val)771 int32_t ais2ih_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
772 {
773 uint8_t buff[2];
774 int32_t ret;
775
776 ret = ais2ih_read_reg(ctx, AIS2IH_OUT_T_L, buff, 2);
777 *val = (int16_t)buff[1];
778 *val = (*val * 256) + (int16_t)buff[0];
779
780 return ret;
781 }
782
783 /**
784 * @brief Linear acceleration output register. The value is expressed as
785 * a 16-bit word in two’s complement.[get]
786 *
787 * @param ctx read / write interface definitions
788 * @param val buffer that stores data read
789 * @retval interface status (MANDATORY: return 0 -> no Error)
790 *
791 */
ais2ih_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)792 int32_t ais2ih_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
793 {
794 uint8_t buff[6];
795 int32_t ret;
796
797 ret = ais2ih_read_reg(ctx, AIS2IH_OUT_X_L, buff, 6);
798 val[0] = (int16_t)buff[1];
799 val[0] = (val[0] * 256) + (int16_t)buff[0];
800 val[1] = (int16_t)buff[3];
801 val[1] = (val[1] * 256) + (int16_t)buff[2];
802 val[2] = (int16_t)buff[5];
803 val[2] = (val[2] * 256) + (int16_t)buff[4];
804
805 return ret;
806 }
807
808 /**
809 * @}
810 *
811 */
812
813 /**
814 * @defgroup AIS2IH_Common
815 * @brief This section groups common useful functions.
816 * @{
817 *
818 */
819
820 /**
821 * @brief Device Who am I.[get]
822 *
823 * @param ctx read / write interface definitions
824 * @param buff buffer that stores data read
825 * @retval interface status (MANDATORY: return 0 -> no Error)
826 *
827 */
ais2ih_device_id_get(const stmdev_ctx_t * ctx,uint8_t * buff)828 int32_t ais2ih_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
829 {
830 int32_t ret;
831
832 ret = ais2ih_read_reg(ctx, AIS2IH_WHO_AM_I, buff, 1);
833
834 return ret;
835 }
836
837 /**
838 * @brief Register address automatically incremented during multiple byte
839 * access with a serial interface.[set]
840 *
841 * @param ctx read / write interface definitions
842 * @param val change the values of if_add_inc in reg CTRL2
843 * @retval interface status (MANDATORY: return 0 -> no Error)
844 *
845 */
ais2ih_auto_increment_set(const stmdev_ctx_t * ctx,uint8_t val)846 int32_t ais2ih_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val)
847 {
848 ais2ih_ctrl2_t reg;
849 int32_t ret;
850
851 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1);
852
853 if (ret == 0)
854 {
855 reg.if_add_inc = val;
856 ret = ais2ih_write_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1);
857 }
858
859 return ret;
860 }
861
862 /**
863 * @brief Register address automatically incremented during multiple
864 * byte access with a serial interface.[get]
865 *
866 * @param ctx read / write interface definitions
867 * @param val change the values of if_add_inc in reg CTRL2
868 * @retval interface status (MANDATORY: return 0 -> no Error)
869 *
870 */
ais2ih_auto_increment_get(const stmdev_ctx_t * ctx,uint8_t * val)871 int32_t ais2ih_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val)
872 {
873 ais2ih_ctrl2_t reg;
874 int32_t ret;
875
876 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1);
877 *val = reg.if_add_inc;
878
879 return ret;
880 }
881
882 /**
883 * @brief Software reset. Restore the default values in user registers.[set]
884 *
885 * @param ctx read / write interface definitions
886 * @param val change the values of soft_reset in reg CTRL2
887 * @retval interface status (MANDATORY: return 0 -> no Error)
888 *
889 */
ais2ih_reset_set(const stmdev_ctx_t * ctx,uint8_t val)890 int32_t ais2ih_reset_set(const stmdev_ctx_t *ctx, uint8_t val)
891 {
892 ais2ih_ctrl2_t reg;
893 int32_t ret;
894
895 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1);
896
897 if (ret == 0)
898 {
899 reg.soft_reset = val;
900 ret = ais2ih_write_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1);
901 }
902
903 return ret;
904 }
905
906 /**
907 * @brief Software reset. Restore the default values in user registers.[get]
908 *
909 * @param ctx read / write interface definitions
910 * @param val change the values of soft_reset in reg CTRL2
911 * @retval interface status (MANDATORY: return 0 -> no Error)
912 *
913 */
ais2ih_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)914 int32_t ais2ih_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
915 {
916 ais2ih_ctrl2_t reg;
917 int32_t ret;
918
919 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1);
920 *val = reg.soft_reset;
921
922 return ret;
923 }
924
925 /**
926 * @brief Reboot memory content. Reload the calibration parameters.[set]
927 *
928 * @param ctx read / write interface definitions
929 * @param val change the values of boot in reg CTRL2
930 * @retval interface status (MANDATORY: return 0 -> no Error)
931 *
932 */
ais2ih_boot_set(const stmdev_ctx_t * ctx,uint8_t val)933 int32_t ais2ih_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
934 {
935 ais2ih_ctrl2_t reg;
936 int32_t ret;
937
938 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1);
939
940 if (ret == 0)
941 {
942 reg.boot = val;
943 ret = ais2ih_write_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1);
944 }
945
946 return ret;
947 }
948
949 /**
950 * @brief Reboot memory content. Reload the calibration parameters.[get]
951 *
952 * @param ctx read / write interface definitions
953 * @param val change the values of boot in reg CTRL2
954 * @retval interface status (MANDATORY: return 0 -> no Error)
955 *
956 */
ais2ih_boot_get(const stmdev_ctx_t * ctx,uint8_t * val)957 int32_t ais2ih_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
958 {
959 ais2ih_ctrl2_t reg;
960 int32_t ret;
961
962 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1);
963 *val = reg.boot;
964
965 return ret;
966 }
967
968 /**
969 * @brief Sensor self-test enable.[set]
970 *
971 * @param ctx read / write interface definitions
972 * @param val change the values of st in reg CTRL3
973 * @retval interface status (MANDATORY: return 0 -> no Error)
974 *
975 */
ais2ih_self_test_set(const stmdev_ctx_t * ctx,ais2ih_st_t val)976 int32_t ais2ih_self_test_set(const stmdev_ctx_t *ctx, ais2ih_st_t val)
977 {
978 ais2ih_ctrl3_t reg;
979 int32_t ret;
980
981 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL3, (uint8_t *) ®, 1);
982
983 if (ret == 0)
984 {
985 reg.st = (uint8_t) val;
986 ret = ais2ih_write_reg(ctx, AIS2IH_CTRL3, (uint8_t *) ®, 1);
987 }
988
989 return ret;
990 }
991
992 /**
993 * @brief Sensor self-test enable.[get]
994 *
995 * @param ctx read / write interface definitions
996 * @param val Get the values of st in reg CTRL3
997 * @retval interface status (MANDATORY: return 0 -> no Error)
998 *
999 */
ais2ih_self_test_get(const stmdev_ctx_t * ctx,ais2ih_st_t * val)1000 int32_t ais2ih_self_test_get(const stmdev_ctx_t *ctx, ais2ih_st_t *val)
1001 {
1002 ais2ih_ctrl3_t reg;
1003 int32_t ret;
1004
1005 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL3, (uint8_t *) ®, 1);
1006
1007 switch (reg.st)
1008 {
1009 case AIS2IH_XL_ST_DISABLE:
1010 *val = AIS2IH_XL_ST_DISABLE;
1011 break;
1012
1013 case AIS2IH_XL_ST_POSITIVE:
1014 *val = AIS2IH_XL_ST_POSITIVE;
1015 break;
1016
1017 case AIS2IH_XL_ST_NEGATIVE:
1018 *val = AIS2IH_XL_ST_NEGATIVE;
1019 break;
1020
1021 default:
1022 *val = AIS2IH_XL_ST_DISABLE;
1023 break;
1024 }
1025
1026 return ret;
1027 }
1028
1029 /**
1030 * @brief Data-ready pulsed / letched mode.[set]
1031 *
1032 * @param ctx read / write interface definitions
1033 * @param val change the values of drdy_pulsed in reg CTRL_REG7
1034 * @retval interface status (MANDATORY: return 0 -> no Error)
1035 *
1036 */
ais2ih_data_ready_mode_set(const stmdev_ctx_t * ctx,ais2ih_drdy_pulsed_t val)1037 int32_t ais2ih_data_ready_mode_set(const stmdev_ctx_t *ctx,
1038 ais2ih_drdy_pulsed_t val)
1039 {
1040 ais2ih_ctrl_reg7_t reg;
1041 int32_t ret;
1042
1043 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1);
1044
1045 if (ret == 0)
1046 {
1047 reg.drdy_pulsed = (uint8_t) val;
1048 ret = ais2ih_write_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1);
1049 }
1050
1051 return ret;
1052 }
1053
1054 /**
1055 * @brief Data-ready pulsed / letched mode.[get]
1056 *
1057 * @param ctx read / write interface definitions
1058 * @param val Get the values of drdy_pulsed in reg CTRL_REG7
1059 * @retval interface status (MANDATORY: return 0 -> no Error)
1060 *
1061 */
ais2ih_data_ready_mode_get(const stmdev_ctx_t * ctx,ais2ih_drdy_pulsed_t * val)1062 int32_t ais2ih_data_ready_mode_get(const stmdev_ctx_t *ctx,
1063 ais2ih_drdy_pulsed_t *val)
1064 {
1065 ais2ih_ctrl_reg7_t reg;
1066 int32_t ret;
1067
1068 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1);
1069
1070 switch (reg.drdy_pulsed)
1071 {
1072 case AIS2IH_DRDY_LATCHED:
1073 *val = AIS2IH_DRDY_LATCHED;
1074 break;
1075
1076 case AIS2IH_DRDY_PULSED:
1077 *val = AIS2IH_DRDY_PULSED;
1078 break;
1079
1080 default:
1081 *val = AIS2IH_DRDY_LATCHED;
1082 break;
1083 }
1084
1085 return ret;
1086 }
1087
1088 /**
1089 * @}
1090 *
1091 */
1092
1093 /**
1094 * @defgroup AIS2IH_Filters
1095 * @brief This section group all the functions concerning the filters
1096 * configuration.
1097 * @{
1098 *
1099 */
1100
1101 /**
1102 * @brief Accelerometer filtering path for outputs.[set]
1103 *
1104 * @param ctx read / write interface definitions
1105 * @param val change the values of fds in reg CTRL6
1106 * @retval interface status (MANDATORY: return 0 -> no Error)
1107 *
1108 */
ais2ih_filter_path_set(const stmdev_ctx_t * ctx,ais2ih_fds_t val)1109 int32_t ais2ih_filter_path_set(const stmdev_ctx_t *ctx, ais2ih_fds_t val)
1110 {
1111 ais2ih_ctrl6_t ctrl6;
1112 ais2ih_ctrl_reg7_t ctrl_reg7;
1113 int32_t ret;
1114
1115 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL6, (uint8_t *) &ctrl6, 1);
1116
1117 if (ret == 0)
1118 {
1119 ctrl6.fds = ((uint8_t) val & 0x10U) >> 4;
1120 ret = ais2ih_write_reg(ctx, AIS2IH_CTRL6, (uint8_t *) &ctrl6, 1);
1121 }
1122
1123 if (ret == 0)
1124 {
1125 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) &ctrl_reg7, 1);
1126 }
1127
1128 if (ret == 0)
1129 {
1130 ctrl_reg7.usr_off_on_out = (uint8_t) val & 0x01U;
1131 ret = ais2ih_write_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) &ctrl_reg7, 1);
1132 }
1133
1134 return ret;
1135 }
1136
1137 /**
1138 * @brief Accelerometer filtering path for outputs.[get]
1139 *
1140 * @param ctx read / write interface definitions
1141 * @param val Get the values of fds in reg CTRL6
1142 * @retval interface status (MANDATORY: return 0 -> no Error)
1143 *
1144 */
ais2ih_filter_path_get(const stmdev_ctx_t * ctx,ais2ih_fds_t * val)1145 int32_t ais2ih_filter_path_get(const stmdev_ctx_t *ctx, ais2ih_fds_t *val)
1146 {
1147 ais2ih_ctrl6_t ctrl6;
1148 ais2ih_ctrl_reg7_t ctrl_reg7;
1149 int32_t ret;
1150
1151 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL6, (uint8_t *) &ctrl6, 1);
1152
1153 if (ret == 0)
1154 {
1155 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) &ctrl_reg7, 1);
1156
1157 switch ((ctrl6.fds << 4) + ctrl_reg7.usr_off_on_out)
1158 {
1159 case AIS2IH_LPF_ON_OUT:
1160 *val = AIS2IH_LPF_ON_OUT;
1161 break;
1162
1163 case AIS2IH_USER_OFFSET_ON_OUT:
1164 *val = AIS2IH_USER_OFFSET_ON_OUT;
1165 break;
1166
1167 case AIS2IH_HIGH_PASS_ON_OUT:
1168 *val = AIS2IH_HIGH_PASS_ON_OUT;
1169 break;
1170
1171 default:
1172 *val = AIS2IH_LPF_ON_OUT;
1173 break;
1174 }
1175 }
1176
1177 return ret;
1178 }
1179
1180 /**
1181 * @brief Accelerometer cutoff filter frequency. Valid for low and high
1182 * pass filter.[set]
1183 *
1184 * @param ctx read / write interface definitions
1185 * @param val change the values of bw_filt in reg CTRL6
1186 * @retval interface status (MANDATORY: return 0 -> no Error)
1187 *
1188 */
ais2ih_filter_bandwidth_set(const stmdev_ctx_t * ctx,ais2ih_bw_filt_t val)1189 int32_t ais2ih_filter_bandwidth_set(const stmdev_ctx_t *ctx,
1190 ais2ih_bw_filt_t val)
1191 {
1192 ais2ih_ctrl6_t reg;
1193 int32_t ret;
1194
1195 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL6, (uint8_t *) ®, 1);
1196
1197 if (ret == 0)
1198 {
1199 reg.bw_filt = (uint8_t) val;
1200 ret = ais2ih_write_reg(ctx, AIS2IH_CTRL6, (uint8_t *) ®, 1);
1201 }
1202
1203 return ret;
1204 }
1205
1206 /**
1207 * @brief Accelerometer cutoff filter frequency. Valid for low and
1208 * high pass filter.[get]
1209 *
1210 * @param ctx read / write interface definitions
1211 * @param val Get the values of bw_filt in reg CTRL6
1212 * @retval interface status (MANDATORY: return 0 -> no Error)
1213 *
1214 */
ais2ih_filter_bandwidth_get(const stmdev_ctx_t * ctx,ais2ih_bw_filt_t * val)1215 int32_t ais2ih_filter_bandwidth_get(const stmdev_ctx_t *ctx,
1216 ais2ih_bw_filt_t *val)
1217 {
1218 ais2ih_ctrl6_t reg;
1219 int32_t ret;
1220
1221 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL6, (uint8_t *) ®, 1);
1222
1223 switch (reg.bw_filt)
1224 {
1225 case AIS2IH_ODR_DIV_2:
1226 *val = AIS2IH_ODR_DIV_2;
1227 break;
1228
1229 case AIS2IH_ODR_DIV_4:
1230 *val = AIS2IH_ODR_DIV_4;
1231 break;
1232
1233 case AIS2IH_ODR_DIV_10:
1234 *val = AIS2IH_ODR_DIV_10;
1235 break;
1236
1237 case AIS2IH_ODR_DIV_20:
1238 *val = AIS2IH_ODR_DIV_20;
1239 break;
1240
1241 default:
1242 *val = AIS2IH_ODR_DIV_2;
1243 break;
1244 }
1245
1246 return ret;
1247 }
1248
1249 /**
1250 * @brief Enable HP filter reference mode.[set]
1251 *
1252 * @param ctx read / write interface definitions
1253 * @param val change the values of hp_ref_mode in reg CTRL_REG7
1254 * @retval interface status (MANDATORY: return 0 -> no Error)
1255 *
1256 */
ais2ih_reference_mode_set(const stmdev_ctx_t * ctx,uint8_t val)1257 int32_t ais2ih_reference_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
1258 {
1259 ais2ih_ctrl_reg7_t reg;
1260 int32_t ret;
1261
1262 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1);
1263
1264 if (ret == 0)
1265 {
1266 reg.hp_ref_mode = val;
1267 ret = ais2ih_write_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1);
1268 }
1269
1270 return ret;
1271 }
1272
1273 /**
1274 * @brief Enable HP filter reference mode.[get]
1275 *
1276 * @param ctx read / write interface definitions
1277 * @param val change the values of hp_ref_mode in reg CTRL_REG7
1278 * @retval interface status (MANDATORY: return 0 -> no Error)
1279 *
1280 */
ais2ih_reference_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)1281 int32_t ais2ih_reference_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
1282 {
1283 ais2ih_ctrl_reg7_t reg;
1284 int32_t ret;
1285
1286 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1);
1287 *val = reg.hp_ref_mode;
1288
1289 return ret;
1290 }
1291
1292 /**
1293 * @}
1294 *
1295 */
1296
1297 /**
1298 * @defgroup AIS2IH_Serial_Interface
1299 * @brief This section groups all the functions concerning main serial
1300 * interface management (not auxiliary)
1301 * @{
1302 *
1303 */
1304
1305 /**
1306 * @brief SPI Serial Interface Mode selection.[set]
1307 *
1308 * @param ctx read / write interface definitions
1309 * @param val change the values of sim in reg CTRL2
1310 * @retval interface status (MANDATORY: return 0 -> no Error)
1311 *
1312 */
ais2ih_spi_mode_set(const stmdev_ctx_t * ctx,ais2ih_sim_t val)1313 int32_t ais2ih_spi_mode_set(const stmdev_ctx_t *ctx, ais2ih_sim_t val)
1314 {
1315 ais2ih_ctrl2_t reg;
1316 int32_t ret;
1317
1318 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1);
1319
1320 if (ret == 0)
1321 {
1322 reg.sim = (uint8_t) val;
1323 ret = ais2ih_write_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1);
1324 }
1325
1326 return ret;
1327 }
1328
1329 /**
1330 * @brief SPI Serial Interface Mode selection.[get]
1331 *
1332 * @param ctx read / write interface definitions
1333 * @param val Get the values of sim in reg CTRL2
1334 * @retval interface status (MANDATORY: return 0 -> no Error)
1335 *
1336 */
ais2ih_spi_mode_get(const stmdev_ctx_t * ctx,ais2ih_sim_t * val)1337 int32_t ais2ih_spi_mode_get(const stmdev_ctx_t *ctx, ais2ih_sim_t *val)
1338 {
1339 ais2ih_ctrl2_t reg;
1340 int32_t ret;
1341
1342 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1);
1343
1344 switch (reg.sim)
1345 {
1346 case AIS2IH_SPI_4_WIRE:
1347 *val = AIS2IH_SPI_4_WIRE;
1348 break;
1349
1350 case AIS2IH_SPI_3_WIRE:
1351 *val = AIS2IH_SPI_3_WIRE;
1352 break;
1353
1354 default:
1355 *val = AIS2IH_SPI_4_WIRE;
1356 break;
1357 }
1358
1359 return ret;
1360 }
1361
1362 /**
1363 * @brief Disable / Enable I2C interface.[set]
1364 *
1365 * @param ctx read / write interface definitions
1366 * @param val change the values of i2c_disable in
1367 * reg CTRL2
1368 * @retval interface status (MANDATORY: return 0 -> no Error)
1369 *
1370 */
ais2ih_i2c_interface_set(const stmdev_ctx_t * ctx,ais2ih_i2c_disable_t val)1371 int32_t ais2ih_i2c_interface_set(const stmdev_ctx_t *ctx,
1372 ais2ih_i2c_disable_t val)
1373 {
1374 ais2ih_ctrl2_t reg;
1375 int32_t ret;
1376
1377 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1);
1378
1379 if (ret == 0)
1380 {
1381 reg.i2c_disable = (uint8_t) val;
1382 ret = ais2ih_write_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1);
1383 }
1384
1385 return ret;
1386 }
1387
1388 /**
1389 * @brief Disable / Enable I2C interface.[get]
1390 *
1391 * @param ctx read / write interface definitions
1392 * @param val Get the values of i2c_disable in reg CTRL2
1393 * @retval interface status (MANDATORY: return 0 -> no Error)
1394 *
1395 */
ais2ih_i2c_interface_get(const stmdev_ctx_t * ctx,ais2ih_i2c_disable_t * val)1396 int32_t ais2ih_i2c_interface_get(const stmdev_ctx_t *ctx,
1397 ais2ih_i2c_disable_t *val)
1398 {
1399 ais2ih_ctrl2_t reg;
1400 int32_t ret;
1401
1402 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1);
1403
1404 switch (reg.i2c_disable)
1405 {
1406 case AIS2IH_I2C_ENABLE:
1407 *val = AIS2IH_I2C_ENABLE;
1408 break;
1409
1410 case AIS2IH_I2C_DISABLE:
1411 *val = AIS2IH_I2C_DISABLE;
1412 break;
1413
1414 default:
1415 *val = AIS2IH_I2C_ENABLE;
1416 break;
1417 }
1418
1419 return ret;
1420 }
1421
1422 /**
1423 * @brief Disconnect CS pull-up.[set]
1424 *
1425 * @param ctx read / write interface definitions
1426 * @param val change the values of cs_pu_disc in reg CTRL2
1427 * @retval interface status (MANDATORY: return 0 -> no Error)
1428 *
1429 */
ais2ih_cs_mode_set(const stmdev_ctx_t * ctx,ais2ih_cs_pu_disc_t val)1430 int32_t ais2ih_cs_mode_set(const stmdev_ctx_t *ctx, ais2ih_cs_pu_disc_t val)
1431 {
1432 ais2ih_ctrl2_t reg;
1433 int32_t ret;
1434
1435 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1);
1436
1437 if (ret == 0)
1438 {
1439 reg.cs_pu_disc = (uint8_t) val;
1440 ret = ais2ih_write_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1);
1441 }
1442
1443 return ret;
1444 }
1445
1446 /**
1447 * @brief Disconnect CS pull-up.[get]
1448 *
1449 * @param ctx read / write interface definitions
1450 * @param val Get the values of cs_pu_disc in reg CTRL2
1451 * @retval interface status (MANDATORY: return 0 -> no Error)
1452 *
1453 */
ais2ih_cs_mode_get(const stmdev_ctx_t * ctx,ais2ih_cs_pu_disc_t * val)1454 int32_t ais2ih_cs_mode_get(const stmdev_ctx_t *ctx,
1455 ais2ih_cs_pu_disc_t *val)
1456 {
1457 ais2ih_ctrl2_t reg;
1458 int32_t ret;
1459
1460 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1);
1461
1462 switch (reg.cs_pu_disc)
1463 {
1464 case AIS2IH_PULL_UP_CONNECT:
1465 *val = AIS2IH_PULL_UP_CONNECT;
1466 break;
1467
1468 case AIS2IH_PULL_UP_DISCONNECT:
1469 *val = AIS2IH_PULL_UP_DISCONNECT;
1470 break;
1471
1472 default:
1473 *val = AIS2IH_PULL_UP_CONNECT;
1474 break;
1475 }
1476
1477 return ret;
1478 }
1479
1480 /**
1481 * @}
1482 *
1483 */
1484
1485 /**
1486 * @defgroup AIS2IH_Interrupt_Pins
1487 * @brief This section groups all the functions that manage interrupt pins
1488 * @{
1489 *
1490 */
1491
1492 /**
1493 * @brief Interrupt active-high/low.[set]
1494 *
1495 * @param ctx read / write interface definitions
1496 * @param val change the values of h_lactive in reg CTRL3
1497 * @retval interface status (MANDATORY: return 0 -> no Error)
1498 *
1499 */
ais2ih_pin_polarity_set(const stmdev_ctx_t * ctx,ais2ih_h_lactive_t val)1500 int32_t ais2ih_pin_polarity_set(const stmdev_ctx_t *ctx,
1501 ais2ih_h_lactive_t val)
1502 {
1503 ais2ih_ctrl3_t reg;
1504 int32_t ret;
1505
1506 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL3, (uint8_t *) ®, 1);
1507
1508 if (ret == 0)
1509 {
1510 reg.h_lactive = (uint8_t) val;
1511 ret = ais2ih_write_reg(ctx, AIS2IH_CTRL3, (uint8_t *) ®, 1);
1512 }
1513
1514 return ret;
1515 }
1516
1517 /**
1518 * @brief Interrupt active-high/low.[get]
1519 *
1520 * @param ctx read / write interface definitions
1521 * @param val Get the values of h_lactive in reg CTRL3
1522 * @retval interface status (MANDATORY: return 0 -> no Error)
1523 *
1524 */
ais2ih_pin_polarity_get(const stmdev_ctx_t * ctx,ais2ih_h_lactive_t * val)1525 int32_t ais2ih_pin_polarity_get(const stmdev_ctx_t *ctx,
1526 ais2ih_h_lactive_t *val)
1527 {
1528 ais2ih_ctrl3_t reg;
1529 int32_t ret;
1530
1531 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL3, (uint8_t *) ®, 1);
1532
1533 switch (reg.h_lactive)
1534 {
1535 case AIS2IH_ACTIVE_HIGH:
1536 *val = AIS2IH_ACTIVE_HIGH;
1537 break;
1538
1539 case AIS2IH_ACTIVE_LOW:
1540 *val = AIS2IH_ACTIVE_LOW;
1541 break;
1542
1543 default:
1544 *val = AIS2IH_ACTIVE_HIGH;
1545 break;
1546 }
1547
1548 return ret;
1549 }
1550
1551 /**
1552 * @brief Latched/pulsed interrupt.[set]
1553 *
1554 * @param ctx read / write interface definitions
1555 * @param val change the values of lir in reg CTRL3
1556 * @retval interface status (MANDATORY: return 0 -> no Error)
1557 *
1558 */
ais2ih_int_notification_set(const stmdev_ctx_t * ctx,ais2ih_lir_t val)1559 int32_t ais2ih_int_notification_set(const stmdev_ctx_t *ctx,
1560 ais2ih_lir_t val)
1561 {
1562 ais2ih_ctrl3_t reg;
1563 int32_t ret;
1564
1565 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL3, (uint8_t *) ®, 1);
1566
1567 if (ret == 0)
1568 {
1569 reg.lir = (uint8_t) val;
1570 ret = ais2ih_write_reg(ctx, AIS2IH_CTRL3, (uint8_t *) ®, 1);
1571 }
1572
1573 return ret;
1574 }
1575
1576 /**
1577 * @brief Latched/pulsed interrupt.[get]
1578 *
1579 * @param ctx read / write interface definitions
1580 * @param val Get the values of lir in reg CTRL3
1581 * @retval interface status (MANDATORY: return 0 -> no Error)
1582 *
1583 */
ais2ih_int_notification_get(const stmdev_ctx_t * ctx,ais2ih_lir_t * val)1584 int32_t ais2ih_int_notification_get(const stmdev_ctx_t *ctx,
1585 ais2ih_lir_t *val)
1586 {
1587 ais2ih_ctrl3_t reg;
1588 int32_t ret;
1589
1590 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL3, (uint8_t *) ®, 1);
1591
1592 switch (reg.lir)
1593 {
1594 case AIS2IH_INT_PULSED:
1595 *val = AIS2IH_INT_PULSED;
1596 break;
1597
1598 case AIS2IH_INT_LATCHED:
1599 *val = AIS2IH_INT_LATCHED;
1600 break;
1601
1602 default:
1603 *val = AIS2IH_INT_PULSED;
1604 break;
1605 }
1606
1607 return ret;
1608 }
1609
1610 /**
1611 * @brief Push-pull/open drain selection on interrupt pads.[set]
1612 *
1613 * @param ctx read / write interface definitions
1614 * @param val change the values of pp_od in reg CTRL3
1615 * @retval interface status (MANDATORY: return 0 -> no Error)
1616 *
1617 */
ais2ih_pin_mode_set(const stmdev_ctx_t * ctx,ais2ih_pp_od_t val)1618 int32_t ais2ih_pin_mode_set(const stmdev_ctx_t *ctx, ais2ih_pp_od_t val)
1619 {
1620 ais2ih_ctrl3_t reg;
1621 int32_t ret;
1622
1623 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL3, (uint8_t *) ®, 1);
1624
1625 if (ret == 0)
1626 {
1627 reg.pp_od = (uint8_t) val;
1628 ret = ais2ih_write_reg(ctx, AIS2IH_CTRL3, (uint8_t *) ®, 1);
1629 }
1630
1631 return ret;
1632 }
1633
1634 /**
1635 * @brief Push-pull/open drain selection on interrupt pads.[get]
1636 *
1637 * @param ctx read / write interface definitions
1638 * @param val Get the values of pp_od in reg CTRL3
1639 * @retval interface status (MANDATORY: return 0 -> no Error)
1640 *
1641 */
ais2ih_pin_mode_get(const stmdev_ctx_t * ctx,ais2ih_pp_od_t * val)1642 int32_t ais2ih_pin_mode_get(const stmdev_ctx_t *ctx, ais2ih_pp_od_t *val)
1643 {
1644 ais2ih_ctrl3_t reg;
1645 int32_t ret;
1646
1647 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL3, (uint8_t *) ®, 1);
1648
1649 switch (reg.pp_od)
1650 {
1651 case AIS2IH_PUSH_PULL:
1652 *val = AIS2IH_PUSH_PULL;
1653 break;
1654
1655 case AIS2IH_OPEN_DRAIN:
1656 *val = AIS2IH_OPEN_DRAIN;
1657 break;
1658
1659 default:
1660 *val = AIS2IH_PUSH_PULL;
1661 break;
1662 }
1663
1664 return ret;
1665 }
1666
1667 /**
1668 * @brief Select the signal that need to route on int1 pad.[set]
1669 *
1670 * @param ctx read / write interface definitions
1671 * @param val register CTRL4_INT1_PAD_CTRL.
1672 * @retval interface status (MANDATORY: return 0 -> no Error)
1673 *
1674 */
ais2ih_pin_int1_route_set(const stmdev_ctx_t * ctx,ais2ih_ctrl4_int1_pad_ctrl_t * val)1675 int32_t ais2ih_pin_int1_route_set(const stmdev_ctx_t *ctx,
1676 ais2ih_ctrl4_int1_pad_ctrl_t *val)
1677 {
1678 ais2ih_ctrl5_int2_pad_ctrl_t ctrl5_int2_pad_ctrl;
1679 ais2ih_ctrl_reg7_t reg;
1680 int32_t ret;
1681
1682 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL5_INT2_PAD_CTRL,
1683 (uint8_t *)&ctrl5_int2_pad_ctrl, 1);
1684
1685 if (ret == 0)
1686 {
1687 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1);
1688 }
1689
1690 if (ret == 0)
1691 {
1692 if ((val->int1_tap |
1693 val->int1_ff |
1694 val->int1_wu |
1695 val->int1_single_tap |
1696 val->int1_6d |
1697 ctrl5_int2_pad_ctrl.int2_sleep_state |
1698 ctrl5_int2_pad_ctrl.int2_sleep_chg) != PROPERTY_DISABLE)
1699 {
1700 reg.interrupts_enable = PROPERTY_ENABLE;
1701 }
1702
1703 else
1704 {
1705 reg.interrupts_enable = PROPERTY_DISABLE;
1706 }
1707
1708 ret = ais2ih_write_reg(ctx, AIS2IH_CTRL4_INT1_PAD_CTRL,
1709 (uint8_t *) val, 1);
1710 }
1711
1712 if (ret == 0)
1713 {
1714 ret = ais2ih_write_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1);
1715 }
1716
1717 return ret;
1718 }
1719
1720 /**
1721 * @brief Select the signal that need to route on int1 pad.[get]
1722 *
1723 * @param ctx read / write interface definitions
1724 * @param val register CTRL4_INT1_PAD_CTRL.
1725 * @retval interface status (MANDATORY: return 0 -> no Error)
1726 *
1727 */
ais2ih_pin_int1_route_get(const stmdev_ctx_t * ctx,ais2ih_ctrl4_int1_pad_ctrl_t * val)1728 int32_t ais2ih_pin_int1_route_get(const stmdev_ctx_t *ctx,
1729 ais2ih_ctrl4_int1_pad_ctrl_t *val)
1730 {
1731 int32_t ret;
1732
1733 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL4_INT1_PAD_CTRL,
1734 (uint8_t *) val, 1);
1735
1736 return ret;
1737 }
1738
1739 /**
1740 * @brief Select the signal that need to route on int2 pad.[set]
1741 *
1742 * @param ctx read / write interface definitions
1743 * @param val register CTRL5_INT2_PAD_CTRL.
1744 * @retval interface status (MANDATORY: return 0 -> no Error)
1745 *
1746 */
ais2ih_pin_int2_route_set(const stmdev_ctx_t * ctx,ais2ih_ctrl5_int2_pad_ctrl_t * val)1747 int32_t ais2ih_pin_int2_route_set(const stmdev_ctx_t *ctx,
1748 ais2ih_ctrl5_int2_pad_ctrl_t *val)
1749 {
1750 ais2ih_ctrl4_int1_pad_ctrl_t ctrl4_int1_pad_ctrl;
1751 ais2ih_ctrl_reg7_t reg;
1752 int32_t ret;
1753
1754 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL4_INT1_PAD_CTRL,
1755 (uint8_t *) &ctrl4_int1_pad_ctrl, 1);
1756
1757 if (ret == 0)
1758 {
1759 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1);
1760 }
1761
1762 if (ret == 0)
1763 {
1764 if ((ctrl4_int1_pad_ctrl.int1_tap |
1765 ctrl4_int1_pad_ctrl.int1_ff |
1766 ctrl4_int1_pad_ctrl.int1_wu |
1767 ctrl4_int1_pad_ctrl.int1_single_tap |
1768 ctrl4_int1_pad_ctrl.int1_6d |
1769 val->int2_sleep_state | val->int2_sleep_chg) != PROPERTY_DISABLE)
1770 {
1771 reg.interrupts_enable = PROPERTY_ENABLE;
1772 }
1773
1774 else
1775 {
1776 reg.interrupts_enable = PROPERTY_DISABLE;
1777 }
1778
1779 ret = ais2ih_write_reg(ctx, AIS2IH_CTRL5_INT2_PAD_CTRL,
1780 (uint8_t *) val, 1);
1781 }
1782
1783 if (ret == 0)
1784 {
1785 ret = ais2ih_write_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1);
1786 }
1787
1788 return ret;
1789 }
1790
1791 /**
1792 * @brief Select the signal that need to route on int2 pad.[get]
1793 *
1794 * @param ctx read / write interface definitions
1795 * @param val register CTRL5_INT2_PAD_CTRL
1796 * @retval interface status (MANDATORY: return 0 -> no Error)
1797 *
1798 */
ais2ih_pin_int2_route_get(const stmdev_ctx_t * ctx,ais2ih_ctrl5_int2_pad_ctrl_t * val)1799 int32_t ais2ih_pin_int2_route_get(const stmdev_ctx_t *ctx,
1800 ais2ih_ctrl5_int2_pad_ctrl_t *val)
1801 {
1802 int32_t ret;
1803
1804 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL5_INT2_PAD_CTRL,
1805 (uint8_t *) val, 1);
1806
1807 return ret;
1808 }
1809 /**
1810 * @brief All interrupt signals become available on INT1 pin.[set]
1811 *
1812 * @param ctx read / write interface definitions
1813 * @param val change the values of int2_on_int1 in reg CTRL_REG7
1814 * @retval interface status (MANDATORY: return 0 -> no Error)
1815 *
1816 */
ais2ih_all_on_int1_set(const stmdev_ctx_t * ctx,uint8_t val)1817 int32_t ais2ih_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val)
1818 {
1819 ais2ih_ctrl_reg7_t reg;
1820 int32_t ret;
1821
1822 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1);
1823
1824 if (ret == 0)
1825 {
1826 reg.int2_on_int1 = val;
1827 ret = ais2ih_write_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1);
1828 }
1829
1830 return ret;
1831 }
1832
1833 /**
1834 * @brief All interrupt signals become available on INT1 pin.[get]
1835 *
1836 * @param ctx read / write interface definitions
1837 * @param val change the values of int2_on_int1 in reg CTRL_REG7
1838 * @retval interface status (MANDATORY: return 0 -> no Error)
1839 *
1840 */
ais2ih_all_on_int1_get(const stmdev_ctx_t * ctx,uint8_t * val)1841 int32_t ais2ih_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val)
1842 {
1843 ais2ih_ctrl_reg7_t reg;
1844 int32_t ret;
1845
1846 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1);
1847 *val = reg.int2_on_int1;
1848
1849 return ret;
1850 }
1851
1852 /**
1853 * @}
1854 *
1855 */
1856
1857 /**
1858 * @defgroup AIS2IH_Wake_Up_Event
1859 * @brief This section groups all the functions that manage the Wake
1860 * Up event generation.
1861 * @{
1862 *
1863 */
1864
1865 /**
1866 * @brief Threshold for wakeup.1 LSB = FS_XL / 64.[set]
1867 *
1868 * @param ctx read / write interface definitions
1869 * @param val change the values of wk_ths in reg WAKE_UP_THS
1870 * @retval interface status (MANDATORY: return 0 -> no Error)
1871 *
1872 */
ais2ih_wkup_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)1873 int32_t ais2ih_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
1874 {
1875 ais2ih_wake_up_ths_t reg;
1876 int32_t ret;
1877
1878 ret = ais2ih_read_reg(ctx, AIS2IH_WAKE_UP_THS, (uint8_t *) ®, 1);
1879
1880 if (ret == 0)
1881 {
1882 reg.wk_ths = val;
1883 ret = ais2ih_write_reg(ctx, AIS2IH_WAKE_UP_THS, (uint8_t *) ®, 1);
1884 }
1885
1886 return ret;
1887 }
1888
1889 /**
1890 * @brief Threshold for wakeup.1 LSB = FS_XL / 64.[get]
1891 *
1892 * @param ctx read / write interface definitions
1893 * @param val change the values of wk_ths in reg WAKE_UP_THS
1894 * @retval interface status (MANDATORY: return 0 -> no Error)
1895 *
1896 */
ais2ih_wkup_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)1897 int32_t ais2ih_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
1898 {
1899 ais2ih_wake_up_ths_t reg;
1900 int32_t ret;
1901
1902 ret = ais2ih_read_reg(ctx, AIS2IH_WAKE_UP_THS, (uint8_t *) ®, 1);
1903 *val = reg.wk_ths;
1904
1905 return ret;
1906 }
1907
1908 /**
1909 * @brief Wake up duration event.1LSb = 1 / ODR.[set]
1910 *
1911 * @param ctx read / write interface definitions
1912 * @param val change the values of wake_dur in reg WAKE_UP_DUR
1913 * @retval interface status (MANDATORY: return 0 -> no Error)
1914 *
1915 */
ais2ih_wkup_dur_set(const stmdev_ctx_t * ctx,uint8_t val)1916 int32_t ais2ih_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
1917 {
1918 ais2ih_wake_up_dur_t reg;
1919 int32_t ret;
1920
1921 ret = ais2ih_read_reg(ctx, AIS2IH_WAKE_UP_DUR, (uint8_t *) ®, 1);
1922
1923 if (ret == 0)
1924 {
1925 reg.wake_dur = val;
1926 ret = ais2ih_write_reg(ctx, AIS2IH_WAKE_UP_DUR, (uint8_t *) ®, 1);
1927 }
1928
1929 return ret;
1930 }
1931
1932 /**
1933 * @brief Wake up duration event.1LSb = 1 / ODR.[get]
1934 *
1935 * @param ctx read / write interface definitions
1936 * @param val change the values of wake_dur in reg WAKE_UP_DUR
1937 * @retval interface status (MANDATORY: return 0 -> no Error)
1938 *
1939 */
ais2ih_wkup_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)1940 int32_t ais2ih_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
1941 {
1942 ais2ih_wake_up_dur_t reg;
1943 int32_t ret;
1944
1945 ret = ais2ih_read_reg(ctx, AIS2IH_WAKE_UP_DUR, (uint8_t *) ®, 1);
1946 *val = reg.wake_dur;
1947
1948 return ret;
1949 }
1950
1951 /**
1952 * @brief Data sent to wake-up interrupt function.[set]
1953 *
1954 * @param ctx read / write interface definitions
1955 * @param val change the values of usr_off_on_wu in reg CTRL_REG7
1956 * @retval interface status (MANDATORY: return 0 -> no Error)
1957 *
1958 */
ais2ih_wkup_feed_data_set(const stmdev_ctx_t * ctx,ais2ih_usr_off_on_wu_t val)1959 int32_t ais2ih_wkup_feed_data_set(const stmdev_ctx_t *ctx,
1960 ais2ih_usr_off_on_wu_t val)
1961 {
1962 ais2ih_ctrl_reg7_t reg;
1963 int32_t ret;
1964
1965 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1);
1966
1967 if (ret == 0)
1968 {
1969 reg.usr_off_on_wu = (uint8_t) val;
1970 ret = ais2ih_write_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1);
1971 }
1972
1973 return ret;
1974 }
1975
1976 /**
1977 * @brief Data sent to wake-up interrupt function.[get]
1978 *
1979 * @param ctx read / write interface definitions
1980 * @param val Get the values of usr_off_on_wu in reg CTRL_REG7
1981 * @retval interface status (MANDATORY: return 0 -> no Error)
1982 *
1983 */
ais2ih_wkup_feed_data_get(const stmdev_ctx_t * ctx,ais2ih_usr_off_on_wu_t * val)1984 int32_t ais2ih_wkup_feed_data_get(const stmdev_ctx_t *ctx,
1985 ais2ih_usr_off_on_wu_t *val)
1986 {
1987 ais2ih_ctrl_reg7_t reg;
1988 int32_t ret;
1989
1990 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1);
1991
1992 switch (reg.usr_off_on_wu)
1993 {
1994 case AIS2IH_HP_FEED:
1995 *val = AIS2IH_HP_FEED;
1996 break;
1997
1998 case AIS2IH_USER_OFFSET_FEED:
1999 *val = AIS2IH_USER_OFFSET_FEED;
2000 break;
2001
2002 default:
2003 *val = AIS2IH_HP_FEED;
2004 break;
2005 }
2006
2007 return ret;
2008 }
2009
2010 /**
2011 * @}
2012 *
2013 */
2014
2015 /**
2016 * @defgroup AIS2IH_Activity/Inactivity_Detection
2017 * @brief This section groups all the functions concerning
2018 * activity/inactivity detection.
2019 * @{
2020 *
2021 */
2022
2023 /**
2024 * @brief Config activity / inactivity or
2025 * stationary / motion detection.[set]
2026 *
2027 * @param ctx read / write interface definitions
2028 * @param val change the values of sleep_on / stationary in
2029 * reg WAKE_UP_THS / WAKE_UP_DUR
2030 * @retval interface status (MANDATORY: return 0 -> no Error)
2031 *
2032 */
ais2ih_act_mode_set(const stmdev_ctx_t * ctx,ais2ih_sleep_on_t val)2033 int32_t ais2ih_act_mode_set(const stmdev_ctx_t *ctx, ais2ih_sleep_on_t val)
2034 {
2035 ais2ih_wake_up_ths_t wake_up_ths;
2036 ais2ih_wake_up_dur_t wake_up_dur;
2037 int32_t ret;
2038
2039 ret = ais2ih_read_reg(ctx, AIS2IH_WAKE_UP_THS,
2040 (uint8_t *) &wake_up_ths, 1);
2041
2042 if (ret == 0)
2043 {
2044 ret = ais2ih_read_reg(ctx, AIS2IH_WAKE_UP_DUR,
2045 (uint8_t *) &wake_up_dur, 1);
2046 }
2047
2048 if (ret == 0)
2049 {
2050 wake_up_ths.sleep_on = (uint8_t) val & 0x01U;
2051 ret = ais2ih_write_reg(ctx, AIS2IH_WAKE_UP_THS,
2052 (uint8_t *) &wake_up_ths, 1);
2053 }
2054
2055 if (ret == 0)
2056 {
2057 wake_up_dur.stationary = ((uint8_t)val & 0x02U) >> 1;
2058 ret = ais2ih_write_reg(ctx, AIS2IH_WAKE_UP_DUR,
2059 (uint8_t *) &wake_up_dur, 1);
2060 }
2061
2062 return ret;
2063 }
2064
2065 /**
2066 * @brief Config activity / inactivity or
2067 * stationary / motion detection. [get]
2068 *
2069 * @param ctx read / write interface definitions
2070 * @param val Get the values of sleep_on in reg WAKE_UP_THS
2071 * @retval interface status (MANDATORY: return 0 -> no Error)
2072 *
2073 */
ais2ih_act_mode_get(const stmdev_ctx_t * ctx,ais2ih_sleep_on_t * val)2074 int32_t ais2ih_act_mode_get(const stmdev_ctx_t *ctx, ais2ih_sleep_on_t *val)
2075 {
2076 ais2ih_wake_up_ths_t wake_up_ths;
2077 ais2ih_wake_up_dur_t wake_up_dur;;
2078 int32_t ret;
2079
2080 ret = ais2ih_read_reg(ctx, AIS2IH_WAKE_UP_THS,
2081 (uint8_t *) &wake_up_ths, 1);
2082
2083 if (ret == 0)
2084 {
2085 ret = ais2ih_read_reg(ctx, AIS2IH_WAKE_UP_DUR,
2086 (uint8_t *) &wake_up_dur, 1);
2087
2088 switch ((wake_up_dur.stationary << 1) + wake_up_ths.sleep_on)
2089 {
2090 case AIS2IH_NO_DETECTION:
2091 *val = AIS2IH_NO_DETECTION;
2092 break;
2093
2094 case AIS2IH_DETECT_ACT_INACT:
2095 *val = AIS2IH_DETECT_ACT_INACT;
2096 break;
2097
2098 case AIS2IH_DETECT_STAT_MOTION:
2099 *val = AIS2IH_DETECT_STAT_MOTION;
2100 break;
2101
2102 default:
2103 *val = AIS2IH_NO_DETECTION;
2104 break;
2105 }
2106 }
2107
2108 return ret;
2109 }
2110
2111 /**
2112 * @brief Duration to go in sleep mode (1 LSb = 512 / ODR).[set]
2113 *
2114 * @param ctx read / write interface definitions
2115 * @param val change the values of sleep_dur in reg WAKE_UP_DUR
2116 * @retval interface status (MANDATORY: return 0 -> no Error)
2117 *
2118 */
ais2ih_act_sleep_dur_set(const stmdev_ctx_t * ctx,uint8_t val)2119 int32_t ais2ih_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
2120 {
2121 ais2ih_wake_up_dur_t reg;
2122 int32_t ret;
2123
2124 ret = ais2ih_read_reg(ctx, AIS2IH_WAKE_UP_DUR, (uint8_t *) ®, 1);
2125
2126 if (ret == 0)
2127 {
2128 reg.sleep_dur = val;
2129 ret = ais2ih_write_reg(ctx, AIS2IH_WAKE_UP_DUR, (uint8_t *) ®, 1);
2130 }
2131
2132 return ret;
2133 }
2134
2135 /**
2136 * @brief Duration to go in sleep mode (1 LSb = 512 / ODR).[get]
2137 *
2138 * @param ctx read / write interface definitions
2139 * @param val change the values of sleep_dur in reg WAKE_UP_DUR
2140 * @retval interface status (MANDATORY: return 0 -> no Error)
2141 *
2142 */
ais2ih_act_sleep_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)2143 int32_t ais2ih_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
2144 {
2145 ais2ih_wake_up_dur_t reg;
2146 int32_t ret;
2147
2148 ret = ais2ih_read_reg(ctx, AIS2IH_WAKE_UP_DUR, (uint8_t *) ®, 1);
2149 *val = reg.sleep_dur;
2150
2151 return ret;
2152 }
2153
2154 /**
2155 * @}
2156 *
2157 */
2158
2159 /**
2160 * @defgroup AIS2IH_Tap_Generator
2161 * @brief This section groups all the functions that manage the tap
2162 * and double tap event generation.
2163 * @{
2164 *
2165 */
2166
2167 /**
2168 * @brief Threshold for tap recognition.[set]
2169 *
2170 * @param ctx read / write interface definitions
2171 * @param val change the values of tap_thsx in reg TAP_THS_X
2172 * @retval interface status (MANDATORY: return 0 -> no Error)
2173 *
2174 */
ais2ih_tap_threshold_x_set(const stmdev_ctx_t * ctx,uint8_t val)2175 int32_t ais2ih_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val)
2176 {
2177 ais2ih_tap_ths_x_t reg;
2178 int32_t ret;
2179
2180 ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_X, (uint8_t *) ®, 1);
2181
2182 if (ret == 0)
2183 {
2184 reg.tap_thsx = val;
2185 ret = ais2ih_write_reg(ctx, AIS2IH_TAP_THS_X, (uint8_t *) ®, 1);
2186 }
2187
2188 return ret;
2189 }
2190
2191 /**
2192 * @brief Threshold for tap recognition.[get]
2193 *
2194 * @param ctx read / write interface definitions
2195 * @param val change the values of tap_thsx in reg TAP_THS_X
2196 * @retval interface status (MANDATORY: return 0 -> no Error)
2197 *
2198 */
ais2ih_tap_threshold_x_get(const stmdev_ctx_t * ctx,uint8_t * val)2199 int32_t ais2ih_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val)
2200 {
2201 ais2ih_tap_ths_x_t reg;
2202 int32_t ret;
2203
2204 ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_X, (uint8_t *) ®, 1);
2205 *val = reg.tap_thsx;
2206
2207 return ret;
2208 }
2209
2210 /**
2211 * @brief Threshold for tap recognition.[set]
2212 *
2213 * @param ctx read / write interface definitions
2214 * @param val change the values of tap_thsy in reg TAP_THS_Y
2215 * @retval interface status (MANDATORY: return 0 -> no Error)
2216 *
2217 */
ais2ih_tap_threshold_y_set(const stmdev_ctx_t * ctx,uint8_t val)2218 int32_t ais2ih_tap_threshold_y_set(const stmdev_ctx_t *ctx, uint8_t val)
2219 {
2220 ais2ih_tap_ths_y_t reg;
2221 int32_t ret;
2222
2223 ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_Y, (uint8_t *) ®, 1);
2224
2225 if (ret == 0)
2226 {
2227 reg.tap_thsy = val;
2228 ret = ais2ih_write_reg(ctx, AIS2IH_TAP_THS_Y, (uint8_t *) ®, 1);
2229 }
2230
2231 return ret;
2232 }
2233
2234 /**
2235 * @brief Threshold for tap recognition.[get]
2236 *
2237 * @param ctx read / write interface definitions
2238 * @param val change the values of tap_thsy in reg TAP_THS_Y
2239 * @retval interface status (MANDATORY: return 0 -> no Error)
2240 *
2241 */
ais2ih_tap_threshold_y_get(const stmdev_ctx_t * ctx,uint8_t * val)2242 int32_t ais2ih_tap_threshold_y_get(const stmdev_ctx_t *ctx, uint8_t *val)
2243 {
2244 ais2ih_tap_ths_y_t reg;
2245 int32_t ret;
2246
2247 ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_Y, (uint8_t *) ®, 1);
2248 *val = reg.tap_thsy;
2249
2250 return ret;
2251 }
2252
2253 /**
2254 * @brief Selection of axis priority for TAP detection.[set]
2255 *
2256 * @param ctx read / write interface definitions
2257 * @param val change the values of tap_prior in reg TAP_THS_Y
2258 * @retval interface status (MANDATORY: return 0 -> no Error)
2259 *
2260 */
ais2ih_tap_axis_priority_set(const stmdev_ctx_t * ctx,ais2ih_tap_prior_t val)2261 int32_t ais2ih_tap_axis_priority_set(const stmdev_ctx_t *ctx,
2262 ais2ih_tap_prior_t val)
2263 {
2264 ais2ih_tap_ths_y_t reg;
2265 int32_t ret;
2266
2267 ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_Y, (uint8_t *) ®, 1);
2268
2269 if (ret == 0)
2270 {
2271 reg.tap_prior = (uint8_t) val;
2272 ret = ais2ih_write_reg(ctx, AIS2IH_TAP_THS_Y, (uint8_t *) ®, 1);
2273 }
2274
2275 return ret;
2276 }
2277
2278 /**
2279 * @brief Selection of axis priority for TAP detection.[get]
2280 *
2281 * @param ctx read / write interface definitions
2282 * @param val Get the values of tap_prior in reg TAP_THS_Y
2283 * @retval interface status (MANDATORY: return 0 -> no Error)
2284 *
2285 */
ais2ih_tap_axis_priority_get(const stmdev_ctx_t * ctx,ais2ih_tap_prior_t * val)2286 int32_t ais2ih_tap_axis_priority_get(const stmdev_ctx_t *ctx,
2287 ais2ih_tap_prior_t *val)
2288 {
2289 ais2ih_tap_ths_y_t reg;
2290 int32_t ret;
2291
2292 ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_Y, (uint8_t *) ®, 1);
2293
2294 switch (reg.tap_prior)
2295 {
2296 case AIS2IH_XYZ:
2297 *val = AIS2IH_XYZ;
2298 break;
2299
2300 case AIS2IH_YXZ:
2301 *val = AIS2IH_YXZ;
2302 break;
2303
2304 case AIS2IH_XZY:
2305 *val = AIS2IH_XZY;
2306 break;
2307
2308 case AIS2IH_ZYX:
2309 *val = AIS2IH_ZYX;
2310 break;
2311
2312 case AIS2IH_YZX:
2313 *val = AIS2IH_YZX;
2314 break;
2315
2316 case AIS2IH_ZXY:
2317 *val = AIS2IH_ZXY;
2318 break;
2319
2320 default:
2321 *val = AIS2IH_XYZ;
2322 break;
2323 }
2324
2325 return ret;
2326 }
2327
2328 /**
2329 * @brief Threshold for tap recognition.[set]
2330 *
2331 * @param ctx read / write interface definitions
2332 * @param val change the values of tap_thsz in reg TAP_THS_Z
2333 * @retval interface status (MANDATORY: return 0 -> no Error)
2334 *
2335 */
ais2ih_tap_threshold_z_set(const stmdev_ctx_t * ctx,uint8_t val)2336 int32_t ais2ih_tap_threshold_z_set(const stmdev_ctx_t *ctx, uint8_t val)
2337 {
2338 ais2ih_tap_ths_z_t reg;
2339 int32_t ret;
2340
2341 ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_Z, (uint8_t *) ®, 1);
2342
2343 if (ret == 0)
2344 {
2345 reg.tap_thsz = val;
2346 ret = ais2ih_write_reg(ctx, AIS2IH_TAP_THS_Z, (uint8_t *) ®, 1);
2347 }
2348
2349 return ret;
2350 }
2351
2352 /**
2353 * @brief Threshold for tap recognition.[get]
2354 *
2355 * @param ctx read / write interface definitions
2356 * @param val change the values of tap_thsz in reg TAP_THS_Z
2357 * @retval interface status (MANDATORY: return 0 -> no Error)
2358 *
2359 */
ais2ih_tap_threshold_z_get(const stmdev_ctx_t * ctx,uint8_t * val)2360 int32_t ais2ih_tap_threshold_z_get(const stmdev_ctx_t *ctx, uint8_t *val)
2361 {
2362 ais2ih_tap_ths_z_t reg;
2363 int32_t ret;
2364
2365 ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_Z, (uint8_t *) ®, 1);
2366 *val = reg.tap_thsz;
2367
2368 return ret;
2369 }
2370
2371 /**
2372 * @brief Enable Z direction in tap recognition.[set]
2373 *
2374 * @param ctx read / write interface definitions
2375 * @param val change the values of tap_z_en in reg TAP_THS_Z
2376 * @retval interface status (MANDATORY: return 0 -> no Error)
2377 *
2378 */
ais2ih_tap_detection_on_z_set(const stmdev_ctx_t * ctx,uint8_t val)2379 int32_t ais2ih_tap_detection_on_z_set(const stmdev_ctx_t *ctx, uint8_t val)
2380 {
2381 ais2ih_tap_ths_z_t reg;
2382 int32_t ret;
2383
2384 ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_Z, (uint8_t *) ®, 1);
2385
2386 if (ret == 0)
2387 {
2388 reg.tap_z_en = val;
2389 ret = ais2ih_write_reg(ctx, AIS2IH_TAP_THS_Z, (uint8_t *) ®, 1);
2390 }
2391
2392 return ret;
2393 }
2394
2395 /**
2396 * @brief Enable Z direction in tap recognition.[get]
2397 *
2398 * @param ctx read / write interface definitions
2399 * @param val change the values of tap_z_en in reg TAP_THS_Z
2400 * @retval interface status (MANDATORY: return 0 -> no Error)
2401 *
2402 */
ais2ih_tap_detection_on_z_get(const stmdev_ctx_t * ctx,uint8_t * val)2403 int32_t ais2ih_tap_detection_on_z_get(const stmdev_ctx_t *ctx, uint8_t *val)
2404 {
2405 ais2ih_tap_ths_z_t reg;
2406 int32_t ret;
2407
2408 ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_Z, (uint8_t *) ®, 1);
2409 *val = reg.tap_z_en;
2410
2411 return ret;
2412 }
2413
2414 /**
2415 * @brief Enable Y direction in tap recognition.[set]
2416 *
2417 * @param ctx read / write interface definitions
2418 * @param val change the values of tap_y_en in reg TAP_THS_Z
2419 * @retval interface status (MANDATORY: return 0 -> no Error)
2420 *
2421 */
ais2ih_tap_detection_on_y_set(const stmdev_ctx_t * ctx,uint8_t val)2422 int32_t ais2ih_tap_detection_on_y_set(const stmdev_ctx_t *ctx, uint8_t val)
2423 {
2424 ais2ih_tap_ths_z_t reg;
2425 int32_t ret;
2426
2427 ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_Z, (uint8_t *) ®, 1);
2428
2429 if (ret == 0)
2430 {
2431 reg.tap_y_en = val;
2432 ret = ais2ih_write_reg(ctx, AIS2IH_TAP_THS_Z, (uint8_t *) ®, 1);
2433 }
2434
2435 return ret;
2436 }
2437
2438 /**
2439 * @brief Enable Y direction in tap recognition.[get]
2440 *
2441 * @param ctx read / write interface definitions
2442 * @param val change the values of tap_y_en in reg TAP_THS_Z
2443 * @retval interface status (MANDATORY: return 0 -> no Error)
2444 *
2445 */
ais2ih_tap_detection_on_y_get(const stmdev_ctx_t * ctx,uint8_t * val)2446 int32_t ais2ih_tap_detection_on_y_get(const stmdev_ctx_t *ctx, uint8_t *val)
2447 {
2448 ais2ih_tap_ths_z_t reg;
2449 int32_t ret;
2450
2451 ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_Z, (uint8_t *) ®, 1);
2452 *val = reg.tap_y_en;
2453
2454 return ret;
2455 }
2456
2457 /**
2458 * @brief Enable X direction in tap recognition.[set]
2459 *
2460 * @param ctx read / write interface definitions
2461 * @param val change the values of tap_x_en in reg TAP_THS_Z
2462 * @retval interface status (MANDATORY: return 0 -> no Error)
2463 *
2464 */
ais2ih_tap_detection_on_x_set(const stmdev_ctx_t * ctx,uint8_t val)2465 int32_t ais2ih_tap_detection_on_x_set(const stmdev_ctx_t *ctx, uint8_t val)
2466 {
2467 ais2ih_tap_ths_z_t reg;
2468 int32_t ret;
2469
2470 ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_Z, (uint8_t *) ®, 1);
2471
2472 if (ret == 0)
2473 {
2474 reg.tap_x_en = val;
2475 ret = ais2ih_write_reg(ctx, AIS2IH_TAP_THS_Z, (uint8_t *) ®, 1);
2476 }
2477
2478 return ret;
2479 }
2480
2481 /**
2482 * @brief Enable X direction in tap recognition.[get]
2483 *
2484 * @param ctx read / write interface definitions
2485 * @param val change the values of tap_x_en in reg TAP_THS_Z
2486 * @retval interface status (MANDATORY: return 0 -> no Error)
2487 *
2488 */
ais2ih_tap_detection_on_x_get(const stmdev_ctx_t * ctx,uint8_t * val)2489 int32_t ais2ih_tap_detection_on_x_get(const stmdev_ctx_t *ctx, uint8_t *val)
2490 {
2491 ais2ih_tap_ths_z_t reg;
2492 int32_t ret;
2493
2494 ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_Z, (uint8_t *) ®, 1);
2495 *val = reg.tap_x_en;
2496
2497 return ret;
2498 }
2499
2500 /**
2501 * @brief Maximum duration is the maximum time of an overthreshold signal
2502 * detection to be recognized as a tap event. The default value
2503 * of these bits is 00b which corresponds to 4*ODR_XL time.
2504 * If the SHOCK[1:0] bits are set to a different value, 1LSB
2505 * corresponds to 8*ODR_XL time.[set]
2506 *
2507 * @param ctx read / write interface definitions
2508 * @param val change the values of shock in reg INT_DUR
2509 * @retval interface status (MANDATORY: return 0 -> no Error)
2510 *
2511 */
ais2ih_tap_shock_set(const stmdev_ctx_t * ctx,uint8_t val)2512 int32_t ais2ih_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val)
2513 {
2514 ais2ih_int_dur_t reg;
2515 int32_t ret;
2516
2517 ret = ais2ih_read_reg(ctx, AIS2IH_INT_DUR, (uint8_t *) ®, 1);
2518
2519 if (ret == 0)
2520 {
2521 reg.shock = val;
2522 ret = ais2ih_write_reg(ctx, AIS2IH_INT_DUR, (uint8_t *) ®, 1);
2523 }
2524
2525 return ret;
2526 }
2527
2528 /**
2529 * @brief Maximum duration is the maximum time of an overthreshold signal
2530 * detection to be recognized as a tap event. The default value
2531 * of these bits is 00b which corresponds to 4*ODR_XL time.
2532 * If the SHOCK[1:0] bits are set to a different value, 1LSB
2533 * corresponds to 8*ODR_XL time.[get]
2534 *
2535 * @param ctx read / write interface definitions
2536 * @param val change the values of shock in reg INT_DUR
2537 * @retval interface status (MANDATORY: return 0 -> no Error)
2538 *
2539 */
ais2ih_tap_shock_get(const stmdev_ctx_t * ctx,uint8_t * val)2540 int32_t ais2ih_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val)
2541 {
2542 ais2ih_int_dur_t reg;
2543 int32_t ret;
2544
2545 ret = ais2ih_read_reg(ctx, AIS2IH_INT_DUR, (uint8_t *) ®, 1);
2546 *val = reg.shock;
2547
2548 return ret;
2549 }
2550
2551 /**
2552 * @brief Quiet time is the time after the first detected tap in which
2553 * there must not be any overthreshold event.
2554 * The default value of these bits is 00b which corresponds
2555 * to 2*ODR_XL time. If the QUIET[1:0] bits are set to a different
2556 * value, 1LSB corresponds to 4*ODR_XL time.[set]
2557 *
2558 * @param ctx read / write interface definitions
2559 * @param val change the values of quiet in reg INT_DUR
2560 * @retval interface status (MANDATORY: return 0 -> no Error)
2561 *
2562 */
ais2ih_tap_quiet_set(const stmdev_ctx_t * ctx,uint8_t val)2563 int32_t ais2ih_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val)
2564 {
2565 ais2ih_int_dur_t reg;
2566 int32_t ret;
2567
2568 ret = ais2ih_read_reg(ctx, AIS2IH_INT_DUR, (uint8_t *) ®, 1);
2569
2570 if (ret == 0)
2571 {
2572 reg.quiet = val;
2573 ret = ais2ih_write_reg(ctx, AIS2IH_INT_DUR, (uint8_t *) ®, 1);
2574 }
2575
2576 return ret;
2577 }
2578
2579 /**
2580 * @brief Quiet time is the time after the first detected tap in which
2581 * there must not be any overthreshold event.
2582 * The default value of these bits is 00b which corresponds
2583 * to 2*ODR_XL time. If the QUIET[1:0] bits are set to a different
2584 * value, 1LSB corresponds to 4*ODR_XL time.[get]
2585 *
2586 * @param ctx read / write interface definitions
2587 * @param val change the values of quiet in reg INT_DUR
2588 * @retval interface status (MANDATORY: return 0 -> no Error)
2589 *
2590 */
ais2ih_tap_quiet_get(const stmdev_ctx_t * ctx,uint8_t * val)2591 int32_t ais2ih_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val)
2592 {
2593 ais2ih_int_dur_t reg;
2594 int32_t ret;
2595
2596 ret = ais2ih_read_reg(ctx, AIS2IH_INT_DUR, (uint8_t *) ®, 1);
2597 *val = reg.quiet;
2598
2599 return ret;
2600 }
2601
2602 /**
2603 * @brief When double tap recognition is enabled, this register expresses
2604 * the maximum time between two consecutive detected taps to
2605 * determine a double tap event.
2606 * The default value of these bits is 0000b which corresponds
2607 * to 16*ODR_XL time. If the DUR[3:0] bits are set to a different
2608 * value, 1LSB corresponds to 32*ODR_XL time.[set]
2609 *
2610 * @param ctx read / write interface definitions
2611 * @param val change the values of latency in reg INT_DUR
2612 * @retval interface status (MANDATORY: return 0 -> no Error)
2613 *
2614 */
ais2ih_tap_dur_set(const stmdev_ctx_t * ctx,uint8_t val)2615 int32_t ais2ih_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
2616 {
2617 ais2ih_int_dur_t reg;
2618 int32_t ret;
2619
2620 ret = ais2ih_read_reg(ctx, AIS2IH_INT_DUR, (uint8_t *) ®, 1);
2621
2622 if (ret == 0)
2623 {
2624 reg.latency = val;
2625 ret = ais2ih_write_reg(ctx, AIS2IH_INT_DUR, (uint8_t *) ®, 1);
2626 }
2627
2628 return ret;
2629 }
2630
2631 /**
2632 * @brief When double tap recognition is enabled, this register expresses
2633 * the maximum time between two consecutive detected taps to
2634 * determine a double tap event.
2635 * The default value of these bits is 0000b which corresponds
2636 * to 16*ODR_XL time. If the DUR[3:0] bits are set to a different
2637 * value, 1LSB corresponds to 32*ODR_XL time.[get]
2638 *
2639 * @param ctx read / write interface definitions
2640 * @param val change the values of latency in reg INT_DUR
2641 * @retval interface status (MANDATORY: return 0 -> no Error)
2642 *
2643 */
ais2ih_tap_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)2644 int32_t ais2ih_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
2645 {
2646 ais2ih_int_dur_t reg;
2647 int32_t ret;
2648
2649 ret = ais2ih_read_reg(ctx, AIS2IH_INT_DUR, (uint8_t *) ®, 1);
2650 *val = reg.latency;
2651
2652 return ret;
2653 }
2654
2655 /**
2656 * @brief Single/double-tap event enable.[set]
2657 *
2658 * @param ctx read / write interface definitions
2659 * @param val change the values of single_double_tap in reg WAKE_UP_THS
2660 * @retval interface status (MANDATORY: return 0 -> no Error)
2661 *
2662 */
ais2ih_tap_mode_set(const stmdev_ctx_t * ctx,ais2ih_single_double_tap_t val)2663 int32_t ais2ih_tap_mode_set(const stmdev_ctx_t *ctx,
2664 ais2ih_single_double_tap_t val)
2665 {
2666 ais2ih_wake_up_ths_t reg;
2667 int32_t ret;
2668
2669 ret = ais2ih_read_reg(ctx, AIS2IH_WAKE_UP_THS, (uint8_t *) ®, 1);
2670
2671 if (ret == 0)
2672 {
2673 reg.single_double_tap = (uint8_t) val;
2674 ret = ais2ih_write_reg(ctx, AIS2IH_WAKE_UP_THS, (uint8_t *) ®, 1);
2675 }
2676
2677 return ret;
2678 }
2679
2680 /**
2681 * @brief Single/double-tap event enable.[get]
2682 *
2683 * @param ctx read / write interface definitions
2684 * @param val Get the values of single_double_tap in reg WAKE_UP_THS
2685 * @retval interface status (MANDATORY: return 0 -> no Error)
2686 *
2687 */
ais2ih_tap_mode_get(const stmdev_ctx_t * ctx,ais2ih_single_double_tap_t * val)2688 int32_t ais2ih_tap_mode_get(const stmdev_ctx_t *ctx,
2689 ais2ih_single_double_tap_t *val)
2690 {
2691 ais2ih_wake_up_ths_t reg;
2692 int32_t ret;
2693
2694 ret = ais2ih_read_reg(ctx, AIS2IH_WAKE_UP_THS, (uint8_t *) ®, 1);
2695
2696 switch (reg.single_double_tap)
2697 {
2698 case AIS2IH_ONLY_SINGLE:
2699 *val = AIS2IH_ONLY_SINGLE;
2700 break;
2701
2702 case AIS2IH_BOTH_SINGLE_DOUBLE:
2703 *val = AIS2IH_BOTH_SINGLE_DOUBLE;
2704 break;
2705
2706 default:
2707 *val = AIS2IH_ONLY_SINGLE;
2708 break;
2709 }
2710
2711 return ret;
2712 }
2713
2714 /**
2715 * @brief Read the tap / double tap source register.[get]
2716 *
2717 * @param ctx read / write interface definitions
2718 * @param ais2ih_tap_src: union of registers from TAP_SRC to
2719 * @retval interface status (MANDATORY: return 0 -> no Error)
2720 *
2721 */
ais2ih_tap_src_get(const stmdev_ctx_t * ctx,ais2ih_tap_src_t * val)2722 int32_t ais2ih_tap_src_get(const stmdev_ctx_t *ctx, ais2ih_tap_src_t *val)
2723 {
2724 int32_t ret;
2725
2726 ret = ais2ih_read_reg(ctx, AIS2IH_TAP_SRC, (uint8_t *) val, 1);
2727
2728 return ret;
2729 }
2730
2731 /**
2732 * @}
2733 *
2734 */
2735
2736 /**
2737 * @defgroup AIS2IH_Six_Position_Detection(6D/4D)
2738 * @brief This section groups all the functions concerning six
2739 * position detection (6D).
2740 * @{
2741 *
2742 */
2743
2744 /**
2745 * @brief Threshold for 4D/6D function.[set]
2746 *
2747 * @param ctx read / write interface definitions
2748 * @param val change the values of 6d_ths in reg TAP_THS_X
2749 * @retval interface status (MANDATORY: return 0 -> no Error)
2750 *
2751 */
ais2ih_6d_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)2752 int32_t ais2ih_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
2753 {
2754 ais2ih_tap_ths_x_t reg;
2755 int32_t ret;
2756
2757 ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_X, (uint8_t *) ®, 1);
2758
2759 if (ret == 0)
2760 {
2761 reg._6d_ths = val;
2762 ret = ais2ih_write_reg(ctx, AIS2IH_TAP_THS_X, (uint8_t *) ®, 1);
2763 }
2764
2765 return ret;
2766 }
2767
2768 /**
2769 * @brief Threshold for 4D/6D function.[get]
2770 *
2771 * @param ctx read / write interface definitions
2772 * @param val change the values of 6d_ths in reg TAP_THS_X
2773 * @retval interface status (MANDATORY: return 0 -> no Error)
2774 *
2775 */
ais2ih_6d_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)2776 int32_t ais2ih_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
2777 {
2778 ais2ih_tap_ths_x_t reg;
2779 int32_t ret;
2780
2781 ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_X, (uint8_t *) ®, 1);
2782 *val = reg._6d_ths;
2783
2784 return ret;
2785 }
2786
2787 /**
2788 * @brief 4D orientation detection enable.[set]
2789 *
2790 * @param ctx read / write interface definitions
2791 * @param val change the values of 4d_en in reg TAP_THS_X
2792 * @retval interface status (MANDATORY: return 0 -> no Error)
2793 *
2794 */
ais2ih_4d_mode_set(const stmdev_ctx_t * ctx,uint8_t val)2795 int32_t ais2ih_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
2796 {
2797 ais2ih_tap_ths_x_t reg;
2798 int32_t ret;
2799
2800 ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_X, (uint8_t *) ®, 1);
2801
2802 if (ret == 0)
2803 {
2804 reg._4d_en = val;
2805 ret = ais2ih_write_reg(ctx, AIS2IH_TAP_THS_X, (uint8_t *) ®, 1);
2806 }
2807
2808 return ret;
2809 }
2810
2811 /**
2812 * @brief 4D orientation detection enable.[get]
2813 *
2814 * @param ctx read / write interface definitions
2815 * @param val change the values of 4d_en in reg TAP_THS_X
2816 * @retval interface status (MANDATORY: return 0 -> no Error)
2817 *
2818 */
ais2ih_4d_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)2819 int32_t ais2ih_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
2820 {
2821 ais2ih_tap_ths_x_t reg;
2822 int32_t ret;
2823
2824 ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_X, (uint8_t *) ®, 1);
2825 *val = reg._4d_en;
2826
2827 return ret;
2828 }
2829
2830 /**
2831 * @brief Read the 6D tap source register.[get]
2832 *
2833 * @param ctx read / write interface definitions
2834 * @param val union of registers from SIXD_SRC
2835 * @retval interface status (MANDATORY: return 0 -> no Error)
2836 *
2837 */
ais2ih_6d_src_get(const stmdev_ctx_t * ctx,ais2ih_sixd_src_t * val)2838 int32_t ais2ih_6d_src_get(const stmdev_ctx_t *ctx, ais2ih_sixd_src_t *val)
2839 {
2840 int32_t ret;
2841
2842 ret = ais2ih_read_reg(ctx, AIS2IH_SIXD_SRC, (uint8_t *) val, 1);
2843
2844 return ret;
2845 }
2846 /**
2847 * @brief Data sent to 6D interrupt function.[set]
2848 *
2849 * @param ctx read / write interface definitions
2850 * @param val change the values of lpass_on6d in reg CTRL_REG7
2851 * @retval interface status (MANDATORY: return 0 -> no Error)
2852 *
2853 */
ais2ih_6d_feed_data_set(const stmdev_ctx_t * ctx,ais2ih_lpass_on6d_t val)2854 int32_t ais2ih_6d_feed_data_set(const stmdev_ctx_t *ctx,
2855 ais2ih_lpass_on6d_t val)
2856 {
2857 ais2ih_ctrl_reg7_t reg;
2858 int32_t ret;
2859
2860 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1);
2861
2862 if (ret == 0)
2863 {
2864 reg.lpass_on6d = (uint8_t) val;
2865 ret = ais2ih_write_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1);
2866 }
2867
2868 return ret;
2869 }
2870
2871 /**
2872 * @brief Data sent to 6D interrupt function.[get]
2873 *
2874 * @param ctx read / write interface definitions
2875 * @param val Get the values of lpass_on6d in reg CTRL_REG7
2876 * @retval interface status (MANDATORY: return 0 -> no Error)
2877 *
2878 */
ais2ih_6d_feed_data_get(const stmdev_ctx_t * ctx,ais2ih_lpass_on6d_t * val)2879 int32_t ais2ih_6d_feed_data_get(const stmdev_ctx_t *ctx,
2880 ais2ih_lpass_on6d_t *val)
2881 {
2882 ais2ih_ctrl_reg7_t reg;
2883 int32_t ret;
2884
2885 ret = ais2ih_read_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1);
2886
2887 switch (reg.lpass_on6d)
2888 {
2889 case AIS2IH_ODR_DIV_2_FEED:
2890 *val = AIS2IH_ODR_DIV_2_FEED;
2891 break;
2892
2893 case AIS2IH_LPF2_FEED:
2894 *val = AIS2IH_LPF2_FEED;
2895 break;
2896
2897 default:
2898 *val = AIS2IH_ODR_DIV_2_FEED;
2899 break;
2900 }
2901
2902 return ret;
2903 }
2904
2905 /**
2906 * @}
2907 *
2908 */
2909
2910 /**
2911 * @defgroup AIS2IH_Free_Fall
2912 * @brief This section group all the functions concerning
2913 * the free fall detection.
2914 * @{
2915 *
2916 */
2917
2918 /**
2919 * @brief Wake up duration event(1LSb = 1 / ODR).[set]
2920 *
2921 * @param ctx read / write interface definitions
2922 * @param val change the values of ff_dur in reg
2923 * WAKE_UP_DUR /F REE_FALL
2924 * @retval interface status (MANDATORY: return 0 -> no Error)
2925 *
2926 */
ais2ih_ff_dur_set(const stmdev_ctx_t * ctx,uint8_t val)2927 int32_t ais2ih_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
2928 {
2929 ais2ih_wake_up_dur_t wake_up_dur;
2930 ais2ih_free_fall_t free_fall;
2931 int32_t ret;
2932
2933 ret = ais2ih_read_reg(ctx, AIS2IH_WAKE_UP_DUR,
2934 (uint8_t *) &wake_up_dur, 1);
2935
2936 if (ret == 0)
2937 {
2938 ret = ais2ih_read_reg(ctx, AIS2IH_FREE_FALL, (uint8_t *) &free_fall, 1);
2939 }
2940
2941 if (ret == 0)
2942 {
2943 wake_up_dur.ff_dur = ((uint8_t) val & 0x20U) >> 5;
2944 free_fall.ff_dur = (uint8_t) val & 0x1FU;
2945 ret = ais2ih_write_reg(ctx, AIS2IH_WAKE_UP_DUR,
2946 (uint8_t *) &wake_up_dur, 1);
2947 }
2948
2949 if (ret == 0)
2950 {
2951 ret = ais2ih_write_reg(ctx, AIS2IH_FREE_FALL, (uint8_t *) &free_fall, 1);
2952 }
2953
2954 return ret;
2955 }
2956
2957 /**
2958 * @brief Wake up duration event(1LSb = 1 / ODR).[get]
2959 *
2960 * @param ctx read / write interface definitions
2961 * @param val change the values of ff_dur in
2962 * reg WAKE_UP_DUR /F REE_FALL
2963 * @retval interface status (MANDATORY: return 0 -> no Error)
2964 *
2965 */
ais2ih_ff_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)2966 int32_t ais2ih_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
2967 {
2968 ais2ih_wake_up_dur_t wake_up_dur;
2969 ais2ih_free_fall_t free_fall;
2970 int32_t ret;
2971
2972 ret = ais2ih_read_reg(ctx, AIS2IH_WAKE_UP_DUR,
2973 (uint8_t *) &wake_up_dur, 1);
2974
2975 if (ret == 0)
2976 {
2977 ret = ais2ih_read_reg(ctx, AIS2IH_FREE_FALL, (uint8_t *) &free_fall, 1);
2978 *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
2979 }
2980
2981 return ret;
2982 }
2983
2984 /**
2985 * @brief Free fall threshold setting.[set]
2986 *
2987 * @param ctx read / write interface definitions
2988 * @param val change the values of ff_ths in reg FREE_FALL
2989 * @retval interface status (MANDATORY: return 0 -> no Error)
2990 *
2991 */
ais2ih_ff_threshold_set(const stmdev_ctx_t * ctx,ais2ih_ff_ths_t val)2992 int32_t ais2ih_ff_threshold_set(const stmdev_ctx_t *ctx,
2993 ais2ih_ff_ths_t val)
2994 {
2995 ais2ih_free_fall_t reg;
2996 int32_t ret;
2997
2998 ret = ais2ih_read_reg(ctx, AIS2IH_FREE_FALL, (uint8_t *) ®, 1);
2999
3000 if (ret == 0)
3001 {
3002 reg.ff_ths = (uint8_t) val;
3003 ret = ais2ih_write_reg(ctx, AIS2IH_FREE_FALL, (uint8_t *) ®, 1);
3004 }
3005
3006 return ret;
3007 }
3008
3009 /**
3010 * @brief Free fall threshold setting.[get]
3011 *
3012 * @param ctx read / write interface definitions
3013 * @param val Get the values of ff_ths in reg FREE_FALL
3014 * @retval interface status (MANDATORY: return 0 -> no Error)
3015 *
3016 */
ais2ih_ff_threshold_get(const stmdev_ctx_t * ctx,ais2ih_ff_ths_t * val)3017 int32_t ais2ih_ff_threshold_get(const stmdev_ctx_t *ctx,
3018 ais2ih_ff_ths_t *val)
3019 {
3020 ais2ih_free_fall_t reg;
3021 int32_t ret;
3022
3023 ret = ais2ih_read_reg(ctx, AIS2IH_FREE_FALL, (uint8_t *) ®, 1);
3024
3025 switch (reg.ff_ths)
3026 {
3027 case AIS2IH_FF_TSH_5LSb_FS2g:
3028 *val = AIS2IH_FF_TSH_5LSb_FS2g;
3029 break;
3030
3031 case AIS2IH_FF_TSH_7LSb_FS2g:
3032 *val = AIS2IH_FF_TSH_7LSb_FS2g;
3033 break;
3034
3035 case AIS2IH_FF_TSH_8LSb_FS2g:
3036 *val = AIS2IH_FF_TSH_8LSb_FS2g;
3037 break;
3038
3039 case AIS2IH_FF_TSH_10LSb_FS2g:
3040 *val = AIS2IH_FF_TSH_10LSb_FS2g;
3041 break;
3042
3043 case AIS2IH_FF_TSH_11LSb_FS2g:
3044 *val = AIS2IH_FF_TSH_11LSb_FS2g;
3045 break;
3046
3047 case AIS2IH_FF_TSH_13LSb_FS2g:
3048 *val = AIS2IH_FF_TSH_13LSb_FS2g;
3049 break;
3050
3051 case AIS2IH_FF_TSH_15LSb_FS2g:
3052 *val = AIS2IH_FF_TSH_15LSb_FS2g;
3053 break;
3054
3055 case AIS2IH_FF_TSH_16LSb_FS2g:
3056 *val = AIS2IH_FF_TSH_16LSb_FS2g;
3057 break;
3058
3059 default:
3060 *val = AIS2IH_FF_TSH_5LSb_FS2g;
3061 break;
3062 }
3063
3064 return ret;
3065 }
3066
3067 /**
3068 * @}
3069 *
3070 */
3071
3072 /**
3073 * @defgroup AIS2IH_Fifo
3074 * @brief This section group all the functions concerning the fifo usage
3075 * @{
3076 *
3077 */
3078
3079 /**
3080 * @brief FIFO watermark level selection.[set]
3081 *
3082 * @param ctx read / write interface definitions
3083 * @param val change the values of fth in reg FIFO_CTRL
3084 * @retval interface status (MANDATORY: return 0 -> no Error)
3085 *
3086 */
ais2ih_fifo_watermark_set(const stmdev_ctx_t * ctx,uint8_t val)3087 int32_t ais2ih_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val)
3088 {
3089 ais2ih_fifo_ctrl_t reg;
3090 int32_t ret;
3091
3092 ret = ais2ih_read_reg(ctx, AIS2IH_FIFO_CTRL, (uint8_t *) ®, 1);
3093
3094 if (ret == 0)
3095 {
3096 reg.fth = val;
3097 ret = ais2ih_write_reg(ctx, AIS2IH_FIFO_CTRL, (uint8_t *) ®, 1);
3098 }
3099
3100 return ret;
3101 }
3102
3103 /**
3104 * @brief FIFO watermark level selection.[get]
3105 *
3106 * @param ctx read / write interface definitions
3107 * @param val change the values of fth in reg FIFO_CTRL
3108 * @retval interface status (MANDATORY: return 0 -> no Error)
3109 *
3110 */
ais2ih_fifo_watermark_get(const stmdev_ctx_t * ctx,uint8_t * val)3111 int32_t ais2ih_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val)
3112 {
3113 ais2ih_fifo_ctrl_t reg;
3114 int32_t ret;
3115
3116 ret = ais2ih_read_reg(ctx, AIS2IH_FIFO_CTRL, (uint8_t *) ®, 1);
3117 *val = reg.fth;
3118
3119 return ret;
3120 }
3121
3122 /**
3123 * @brief FIFO mode selection.[set]
3124 *
3125 * @param ctx read / write interface definitions
3126 * @param val change the values of fmode in reg FIFO_CTRL
3127 * @retval interface status (MANDATORY: return 0 -> no Error)
3128 *
3129 */
ais2ih_fifo_mode_set(const stmdev_ctx_t * ctx,ais2ih_fmode_t val)3130 int32_t ais2ih_fifo_mode_set(const stmdev_ctx_t *ctx, ais2ih_fmode_t val)
3131 {
3132 ais2ih_fifo_ctrl_t reg;
3133 int32_t ret;
3134
3135 ret = ais2ih_read_reg(ctx, AIS2IH_FIFO_CTRL, (uint8_t *) ®, 1);
3136
3137 if (ret == 0)
3138 {
3139 reg.fmode = (uint8_t) val;
3140 ret = ais2ih_write_reg(ctx, AIS2IH_FIFO_CTRL, (uint8_t *) ®, 1);
3141 }
3142
3143 return ret;
3144 }
3145
3146 /**
3147 * @brief FIFO mode selection.[get]
3148 *
3149 * @param ctx read / write interface definitions
3150 * @param val Get the values of fmode in reg FIFO_CTRL
3151 * @retval interface status (MANDATORY: return 0 -> no Error)
3152 *
3153 */
ais2ih_fifo_mode_get(const stmdev_ctx_t * ctx,ais2ih_fmode_t * val)3154 int32_t ais2ih_fifo_mode_get(const stmdev_ctx_t *ctx, ais2ih_fmode_t *val)
3155 {
3156 ais2ih_fifo_ctrl_t reg;
3157 int32_t ret;
3158
3159 ret = ais2ih_read_reg(ctx, AIS2IH_FIFO_CTRL, (uint8_t *) ®, 1);
3160
3161 switch (reg.fmode)
3162 {
3163 case AIS2IH_BYPASS_MODE:
3164 *val = AIS2IH_BYPASS_MODE;
3165 break;
3166
3167 case AIS2IH_FIFO_MODE:
3168 *val = AIS2IH_FIFO_MODE;
3169 break;
3170
3171 case AIS2IH_STREAM_TO_FIFO_MODE:
3172 *val = AIS2IH_STREAM_TO_FIFO_MODE;
3173 break;
3174
3175 case AIS2IH_BYPASS_TO_STREAM_MODE:
3176 *val = AIS2IH_BYPASS_TO_STREAM_MODE;
3177 break;
3178
3179 case AIS2IH_STREAM_MODE:
3180 *val = AIS2IH_STREAM_MODE;
3181 break;
3182
3183 default:
3184 *val = AIS2IH_BYPASS_MODE;
3185 break;
3186 }
3187
3188 return ret;
3189 }
3190
3191 /**
3192 * @brief Number of unread samples stored in FIFO.[get]
3193 *
3194 * @param ctx read / write interface definitions
3195 * @param val change the values of diff in reg FIFO_SAMPLES
3196 * @retval interface status (MANDATORY: return 0 -> no Error)
3197 *
3198 */
ais2ih_fifo_data_level_get(const stmdev_ctx_t * ctx,uint8_t * val)3199 int32_t ais2ih_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val)
3200 {
3201 ais2ih_fifo_samples_t reg;
3202 int32_t ret;
3203
3204 ret = ais2ih_read_reg(ctx, AIS2IH_FIFO_SAMPLES, (uint8_t *) ®, 1);
3205 *val = reg.diff;
3206
3207 return ret;
3208 }
3209 /**
3210 * @brief FIFO overrun status.[get]
3211 *
3212 * @param ctx read / write interface definitions
3213 * @param val change the values of fifo_ovr in reg FIFO_SAMPLES
3214 * @retval interface status (MANDATORY: return 0 -> no Error)
3215 *
3216 */
ais2ih_fifo_ovr_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)3217 int32_t ais2ih_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
3218 {
3219 ais2ih_fifo_samples_t reg;
3220 int32_t ret;
3221
3222 ret = ais2ih_read_reg(ctx, AIS2IH_FIFO_SAMPLES, (uint8_t *) ®, 1);
3223 *val = reg.fifo_ovr;
3224
3225 return ret;
3226 }
3227 /**
3228 * @brief FIFO threshold status flag.[get]
3229 *
3230 * @param ctx read / write interface definitions
3231 * @param val change the values of fifo_fth in reg FIFO_SAMPLES
3232 * @retval interface status (MANDATORY: return 0 -> no Error)
3233 *
3234 */
ais2ih_fifo_wtm_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)3235 int32_t ais2ih_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
3236 {
3237 ais2ih_fifo_samples_t reg;
3238 int32_t ret;
3239
3240 ret = ais2ih_read_reg(ctx, AIS2IH_FIFO_SAMPLES, (uint8_t *) ®, 1);
3241 *val = reg.fifo_fth;
3242
3243 return ret;
3244 }
3245
3246 /**
3247 * @}
3248 *
3249 */
3250
3251 /**
3252 * @}
3253 *
3254 */
3255
3256 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
3257
