1 /**
2 ******************************************************************************
3 * @file lsm6dsv16x_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LSM6DSV16X driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lsm6dsv16x_reg.h"
21
22 /**
23 * @defgroup LSM6DSV16X
24 * @brief This file provides a set of functions needed to drive the
25 * lsm6dsv16x enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup Interfaces functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx communication interface handler.(ptr)
43 * @param reg first register address to read.
44 * @param data buffer for data read.(ptr)
45 * @param len number of consecutive register to read.
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lsm6dsv16x_read_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lsm6dsv16x_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 ret = ctx->read_reg(ctx->handle, reg, data, len);
56
57 return ret;
58 }
59
60 /**
61 * @brief Write generic device register
62 *
63 * @param ctx communication interface handler.(ptr)
64 * @param reg first register address to write.
65 * @param data the buffer contains data to be written.(ptr)
66 * @param len number of consecutive register to write.
67 * @retval interface status (MANDATORY: return 0 -> no Error)
68 *
69 */
lsm6dsv16x_write_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)70 int32_t __weak lsm6dsv16x_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
71 uint8_t *data,
72 uint16_t len)
73 {
74 int32_t ret;
75
76 ret = ctx->write_reg(ctx->handle, reg, data, len);
77
78 return ret;
79 }
80
81 /**
82 * @}
83 *
84 */
85
86 /**
87 * @defgroup Private functions
88 * @brief Section collect all the utility functions needed by APIs.
89 * @{
90 *
91 */
92
bytecpy(uint8_t * target,uint8_t * source)93 static void bytecpy(uint8_t *target, uint8_t *source)
94 {
95 if ((target != NULL) && (source != NULL))
96 {
97 *target = *source;
98 }
99 }
100
101 /**
102 * @}
103 *
104 */
105
106 /**
107 * @defgroup Sensitivity
108 * @brief These functions convert raw-data into engineering units.
109 * @{
110 *
111 */
lsm6dsv16x_from_sflp_to_mg(int16_t lsb)112 float_t lsm6dsv16x_from_sflp_to_mg(int16_t lsb)
113 {
114 return ((float_t)lsb) * 0.061f;
115 }
116
lsm6dsv16x_from_fs2_to_mg(int16_t lsb)117 float_t lsm6dsv16x_from_fs2_to_mg(int16_t lsb)
118 {
119 return ((float_t)lsb) * 0.061f;
120 }
121
lsm6dsv16x_from_fs4_to_mg(int16_t lsb)122 float_t lsm6dsv16x_from_fs4_to_mg(int16_t lsb)
123 {
124 return ((float_t)lsb) * 0.122f;
125 }
126
lsm6dsv16x_from_fs8_to_mg(int16_t lsb)127 float_t lsm6dsv16x_from_fs8_to_mg(int16_t lsb)
128 {
129 return ((float_t)lsb) * 0.244f;
130 }
131
lsm6dsv16x_from_fs16_to_mg(int16_t lsb)132 float_t lsm6dsv16x_from_fs16_to_mg(int16_t lsb)
133 {
134 return ((float_t)lsb) * 0.488f;
135 }
136
lsm6dsv16x_from_fs125_to_mdps(int16_t lsb)137 float_t lsm6dsv16x_from_fs125_to_mdps(int16_t lsb)
138 {
139 return ((float_t)lsb) * 4.375f;
140 }
141
lsm6dsv16x_from_fs250_to_mdps(int16_t lsb)142 float_t lsm6dsv16x_from_fs250_to_mdps(int16_t lsb)
143 {
144 return ((float_t)lsb) * 8.750f;
145 }
146
lsm6dsv16x_from_fs500_to_mdps(int16_t lsb)147 float_t lsm6dsv16x_from_fs500_to_mdps(int16_t lsb)
148 {
149 return ((float_t)lsb) * 17.50f;
150 }
151
lsm6dsv16x_from_fs1000_to_mdps(int16_t lsb)152 float_t lsm6dsv16x_from_fs1000_to_mdps(int16_t lsb)
153 {
154 return ((float_t)lsb) * 35.0f;
155 }
156
lsm6dsv16x_from_fs2000_to_mdps(int16_t lsb)157 float_t lsm6dsv16x_from_fs2000_to_mdps(int16_t lsb)
158 {
159 return ((float_t)lsb) * 70.0f;
160 }
161
lsm6dsv16x_from_fs4000_to_mdps(int16_t lsb)162 float_t lsm6dsv16x_from_fs4000_to_mdps(int16_t lsb)
163 {
164 return ((float_t)lsb) * 140.0f;
165 }
166
lsm6dsv16x_from_lsb_to_celsius(int16_t lsb)167 float_t lsm6dsv16x_from_lsb_to_celsius(int16_t lsb)
168 {
169 return (((float_t)lsb / 256.0f) + 25.0f);
170 }
171
lsm6dsv16x_from_lsb_to_nsec(uint32_t lsb)172 float_t lsm6dsv16x_from_lsb_to_nsec(uint32_t lsb)
173 {
174 return ((float_t)lsb * 21750.0f);
175 }
176
lsm6dsv16x_from_lsb_to_mv(int16_t lsb)177 float_t lsm6dsv16x_from_lsb_to_mv(int16_t lsb)
178 {
179 return ((float_t)lsb) / 78.0f;
180 }
181
182 /**
183 * @}
184 *
185 */
186
187 /**
188 * @defgroup Accelerometer user offset correction
189 * @brief This section groups all the functions concerning the
190 * usage of Accelerometer user offset correction
191 * @{
192 *
193 */
194
195 /**
196 * @brief Enables accelerometer user offset correction block; it is valid for the low-pass path.[set]
197 *
198 * @param ctx read / write interface definitions
199 * @param val Enables accelerometer user offset correction block; it is valid for the low-pass path.
200 * @retval interface status (MANDATORY: return 0 -> no Error)
201 *
202 */
lsm6dsv16x_xl_offset_on_out_set(stmdev_ctx_t * ctx,uint8_t val)203 int32_t lsm6dsv16x_xl_offset_on_out_set(stmdev_ctx_t *ctx, uint8_t val)
204 {
205 lsm6dsv16x_ctrl9_t ctrl9;
206 int32_t ret;
207
208 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1);
209 if (ret == 0)
210 {
211 ctrl9.usr_off_on_out = val;
212 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1);
213 }
214
215 return ret;
216 }
217
218 /**
219 * @brief Enables accelerometer user offset correction block; it is valid for the low-pass path.[get]
220 *
221 * @param ctx read / write interface definitions
222 * @param val Enables accelerometer user offset correction block; it is valid for the low-pass path.
223 * @retval interface status (MANDATORY: return 0 -> no Error)
224 *
225 */
lsm6dsv16x_xl_offset_on_out_get(stmdev_ctx_t * ctx,uint8_t * val)226 int32_t lsm6dsv16x_xl_offset_on_out_get(stmdev_ctx_t *ctx, uint8_t *val)
227 {
228 lsm6dsv16x_ctrl9_t ctrl9;
229 int32_t ret;
230
231 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1);
232 *val = ctrl9.usr_off_on_out;
233
234 return ret;
235 }
236
237 /**
238 * @brief Accelerometer user offset correction values in mg.[set]
239 *
240 * @param ctx read / write interface definitions
241 * @param val Accelerometer user offset correction values in mg.
242 * @retval interface status (MANDATORY: return 0 -> no Error)
243 *
244 */
lsm6dsv16x_xl_offset_mg_set(stmdev_ctx_t * ctx,lsm6dsv16x_xl_offset_mg_t val)245 int32_t lsm6dsv16x_xl_offset_mg_set(stmdev_ctx_t *ctx,
246 lsm6dsv16x_xl_offset_mg_t val)
247 {
248 lsm6dsv16x_z_ofs_usr_t z_ofs_usr;
249 lsm6dsv16x_y_ofs_usr_t y_ofs_usr;
250 lsm6dsv16x_x_ofs_usr_t x_ofs_usr;
251 lsm6dsv16x_ctrl9_t ctrl9;
252 int32_t ret;
253 float_t tmp;
254
255 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1);
256 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1);
257 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1);
258 if (ret != 0) { return ret; }
259
260
261 if ((val.x_mg < (0.0078125f * 127.0f)) && (val.x_mg > (0.0078125f * -127.0f)) &&
262 (val.y_mg < (0.0078125f * 127.0f)) && (val.y_mg > (0.0078125f * -127.0f)) &&
263 (val.z_mg < (0.0078125f * 127.0f)) && (val.z_mg > (0.0078125f * -127.0f)))
264 {
265 ctrl9.usr_off_w = 0;
266
267 tmp = val.z_mg / 0.0078125f;
268 z_ofs_usr.z_ofs_usr = (uint8_t)tmp;
269
270 tmp = val.y_mg / 0.0078125f;
271 y_ofs_usr.y_ofs_usr = (uint8_t)tmp;
272
273 tmp = val.x_mg / 0.0078125f;
274 x_ofs_usr.x_ofs_usr = (uint8_t)tmp;
275 }
276 else if ((val.x_mg < (0.125f * 127.0f)) && (val.x_mg > (0.125f * -127.0f)) &&
277 (val.y_mg < (0.125f * 127.0f)) && (val.y_mg > (0.125f * -127.0f)) &&
278 (val.z_mg < (0.125f * 127.0f)) && (val.z_mg > (0.125f * -127.0f)))
279 {
280 ctrl9.usr_off_w = 1;
281
282 tmp = val.z_mg / 0.125f;
283 z_ofs_usr.z_ofs_usr = (uint8_t)tmp;
284
285 tmp = val.y_mg / 0.125f;
286 y_ofs_usr.y_ofs_usr = (uint8_t)tmp;
287
288 tmp = val.x_mg / 0.125f;
289 x_ofs_usr.x_ofs_usr = (uint8_t)tmp;
290 }
291 else // out of limit
292 {
293 ctrl9.usr_off_w = 1;
294 z_ofs_usr.z_ofs_usr = 0xFFU;
295 y_ofs_usr.y_ofs_usr = 0xFFU;
296 x_ofs_usr.x_ofs_usr = 0xFFU;
297 }
298
299 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1);
300 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1);
301 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1);
302 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1);
303
304 return ret;
305 }
306
307 /**
308 * @brief Accelerometer user offset correction values in mg.[get]
309 *
310 * @param ctx read / write interface definitions
311 * @param val Accelerometer user offset correction values in mg.
312 * @retval interface status (MANDATORY: return 0 -> no Error)
313 *
314 */
lsm6dsv16x_xl_offset_mg_get(stmdev_ctx_t * ctx,lsm6dsv16x_xl_offset_mg_t * val)315 int32_t lsm6dsv16x_xl_offset_mg_get(stmdev_ctx_t *ctx,
316 lsm6dsv16x_xl_offset_mg_t *val)
317 {
318 lsm6dsv16x_z_ofs_usr_t z_ofs_usr;
319 lsm6dsv16x_y_ofs_usr_t y_ofs_usr;
320 lsm6dsv16x_x_ofs_usr_t x_ofs_usr;
321 lsm6dsv16x_ctrl9_t ctrl9;
322 int32_t ret;
323
324 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1);
325 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1);
326 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1);
327 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1);
328 if (ret != 0) { return ret; }
329
330 if (ctrl9.usr_off_w == PROPERTY_DISABLE)
331 {
332 val->z_mg = ((float_t)z_ofs_usr.z_ofs_usr * 0.0078125f);
333 val->y_mg = ((float_t)y_ofs_usr.y_ofs_usr * 0.0078125f);
334 val->x_mg = ((float_t)x_ofs_usr.x_ofs_usr * 0.0078125f);
335 }
336 else
337 {
338 val->z_mg = ((float_t)z_ofs_usr.z_ofs_usr * 0.125f);
339 val->y_mg = ((float_t)y_ofs_usr.y_ofs_usr * 0.125f);
340 val->x_mg = ((float_t)x_ofs_usr.x_ofs_usr * 0.125f);
341 }
342
343 return ret;
344 }
345
346 /**
347 * @}
348 *
349 */
350
351 /**
352 * @brief Reset of the device.[set]
353 *
354 * @param ctx read / write interface definitions
355 * @param val Reset of the device.
356 * @retval interface status (MANDATORY: return 0 -> no Error)
357 *
358 */
lsm6dsv16x_reset_set(stmdev_ctx_t * ctx,lsm6dsv16x_reset_t val)359 int32_t lsm6dsv16x_reset_set(stmdev_ctx_t *ctx, lsm6dsv16x_reset_t val)
360 {
361 lsm6dsv16x_func_cfg_access_t func_cfg_access;
362 lsm6dsv16x_ctrl3_t ctrl3;
363 int32_t ret;
364
365 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL3, (uint8_t *)&ctrl3, 1);
366 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
367 if (ret != 0) { return ret; }
368
369 ctrl3.boot = ((uint8_t)val & 0x04U) >> 2;
370 ctrl3.sw_reset = ((uint8_t)val & 0x02U) >> 1;
371 func_cfg_access.sw_por = (uint8_t)val & 0x01U;
372
373 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL3, (uint8_t *)&ctrl3, 1);
374 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
375
376 return ret;
377 }
378
379 /**
380 * @brief Global reset of the device.[get]
381 *
382 * @param ctx read / write interface definitions
383 * @param val Global reset of the device.
384 * @retval interface status (MANDATORY: return 0 -> no Error)
385 *
386 */
lsm6dsv16x_reset_get(stmdev_ctx_t * ctx,lsm6dsv16x_reset_t * val)387 int32_t lsm6dsv16x_reset_get(stmdev_ctx_t *ctx, lsm6dsv16x_reset_t *val)
388 {
389 lsm6dsv16x_func_cfg_access_t func_cfg_access;
390 lsm6dsv16x_ctrl3_t ctrl3;
391 int32_t ret;
392
393 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL3, (uint8_t *)&ctrl3, 1);
394 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
395 if (ret != 0) { return ret; }
396
397 switch ((ctrl3.sw_reset << 2) + (ctrl3.boot << 1) + func_cfg_access.sw_por)
398 {
399 case LSM6DSV16X_READY:
400 *val = LSM6DSV16X_READY;
401 break;
402
403 case LSM6DSV16X_GLOBAL_RST:
404 *val = LSM6DSV16X_GLOBAL_RST;
405 break;
406
407 case LSM6DSV16X_RESTORE_CAL_PARAM:
408 *val = LSM6DSV16X_RESTORE_CAL_PARAM;
409 break;
410
411 case LSM6DSV16X_RESTORE_CTRL_REGS:
412 *val = LSM6DSV16X_RESTORE_CTRL_REGS;
413 break;
414
415 default:
416 *val = LSM6DSV16X_GLOBAL_RST;
417 break;
418 }
419
420 return ret;
421 }
422
423 /**
424 * @brief Change memory bank.[set]
425 *
426 * @param ctx read / write interface definitions
427 * @param val MAIN_MEM_BANK, EMBED_FUNC_MEM_BANK,
428 * @retval interface status (MANDATORY: return 0 -> no Error)
429 *
430 */
lsm6dsv16x_mem_bank_set(stmdev_ctx_t * ctx,lsm6dsv16x_mem_bank_t val)431 int32_t lsm6dsv16x_mem_bank_set(stmdev_ctx_t *ctx, lsm6dsv16x_mem_bank_t val)
432 {
433 lsm6dsv16x_func_cfg_access_t func_cfg_access;
434 int32_t ret;
435
436 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
437 if (ret != 0) { return ret; }
438
439 func_cfg_access.shub_reg_access = ((uint8_t)val & 0x02U) >> 1;
440 func_cfg_access.emb_func_reg_access = (uint8_t)val & 0x01U;
441 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
442
443 return ret;
444 }
445
446 /**
447 * @brief Change memory bank.[get]
448 *
449 * @param ctx read / write interface definitions
450 * @param val MAIN_MEM_BANK, SENSOR_HUB_MEM_BANK, EMBED_FUNC_MEM_BANK,
451 * @retval interface status (MANDATORY: return 0 -> no Error)
452 *
453 */
lsm6dsv16x_mem_bank_get(stmdev_ctx_t * ctx,lsm6dsv16x_mem_bank_t * val)454 int32_t lsm6dsv16x_mem_bank_get(stmdev_ctx_t *ctx, lsm6dsv16x_mem_bank_t *val)
455 {
456 lsm6dsv16x_func_cfg_access_t func_cfg_access;
457 int32_t ret;
458
459 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
460 if (ret != 0) { return ret; }
461
462 switch ((func_cfg_access.shub_reg_access << 1) + func_cfg_access.emb_func_reg_access)
463 {
464 case LSM6DSV16X_MAIN_MEM_BANK:
465 *val = LSM6DSV16X_MAIN_MEM_BANK;
466 break;
467
468 case LSM6DSV16X_EMBED_FUNC_MEM_BANK:
469 *val = LSM6DSV16X_EMBED_FUNC_MEM_BANK;
470 break;
471
472 case LSM6DSV16X_SENSOR_HUB_MEM_BANK:
473 *val = LSM6DSV16X_SENSOR_HUB_MEM_BANK;
474 break;
475
476 default:
477 *val = LSM6DSV16X_MAIN_MEM_BANK;
478 break;
479 }
480
481 return ret;
482 }
483
484 /**
485 * @brief Device ID.[get] THis function works also for OIS
486 * (WHO_AM_I and SPI2_WHO_AM_I have same address)
487 *
488 * @param ctx read / write interface definitions
489 * @param val Device ID.
490 * @retval interface status (MANDATORY: return 0 -> no Error)
491 *
492 */
lsm6dsv16x_device_id_get(stmdev_ctx_t * ctx,uint8_t * val)493 int32_t lsm6dsv16x_device_id_get(stmdev_ctx_t *ctx, uint8_t *val)
494 {
495 int32_t ret;
496
497 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WHO_AM_I, val, 1);
498
499 return ret;
500 }
501
502 /**
503 * @brief Accelerometer output data rate (ODR) selection.[set]
504 *
505 * @param ctx read / write interface definitions
506 * @param val lsm6dsv16x_data_rate_t enum
507 * @retval interface status (MANDATORY: return 0 -> no Error)
508 *
509 */
lsm6dsv16x_xl_data_rate_set(stmdev_ctx_t * ctx,lsm6dsv16x_data_rate_t val)510 int32_t lsm6dsv16x_xl_data_rate_set(stmdev_ctx_t *ctx,
511 lsm6dsv16x_data_rate_t val)
512 {
513 lsm6dsv16x_ctrl1_t ctrl1;
514 lsm6dsv16x_haodr_cfg_t haodr;
515 uint8_t sel;
516 int32_t ret;
517
518 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL1, (uint8_t *)&ctrl1, 1);
519 if (ret != 0) { return ret; }
520
521 ctrl1.odr_xl = (uint8_t)val & 0x0Fu;
522 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL1, (uint8_t *)&ctrl1, 1);
523 if (ret != 0) { return ret; }
524
525 sel = ((uint8_t)val >> 4) & 0xFU;
526 if (sel != 0U)
527 {
528 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_HAODR_CFG, (uint8_t *)&haodr, 1);
529 haodr.haodr_sel = sel;
530 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_HAODR_CFG, (uint8_t *)&haodr, 1);
531 }
532
533 return ret;
534 }
535
536 /**
537 * @brief Accelerometer output data rate (ODR) selection.[get]
538 *
539 * @param ctx read / write interface definitions
540 * @param val lsm6dsv16x_data_rate_t enum
541 * @retval interface status (MANDATORY: return 0 -> no Error)
542 *
543 */
lsm6dsv16x_xl_data_rate_get(stmdev_ctx_t * ctx,lsm6dsv16x_data_rate_t * val)544 int32_t lsm6dsv16x_xl_data_rate_get(stmdev_ctx_t *ctx,
545 lsm6dsv16x_data_rate_t *val)
546 {
547 lsm6dsv16x_ctrl1_t ctrl1;
548 lsm6dsv16x_haodr_cfg_t haodr;
549 uint8_t sel;
550 int32_t ret;
551
552 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL1, (uint8_t *)&ctrl1, 1);
553 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_HAODR_CFG, (uint8_t *)&haodr, 1);
554 if (ret != 0) { return ret; }
555
556 sel = haodr.haodr_sel;
557
558 switch (ctrl1.odr_xl)
559 {
560 case LSM6DSV16X_ODR_OFF:
561 *val = LSM6DSV16X_ODR_OFF;
562 break;
563
564 case LSM6DSV16X_ODR_AT_1Hz875:
565 *val = LSM6DSV16X_ODR_AT_1Hz875;
566 break;
567
568 case LSM6DSV16X_ODR_AT_7Hz5:
569 *val = LSM6DSV16X_ODR_AT_7Hz5;
570 break;
571
572 case LSM6DSV16X_ODR_AT_15Hz:
573 switch (sel) {
574 default:
575 case 0:
576 *val = LSM6DSV16X_ODR_AT_15Hz;
577 break;
578 case 1:
579 *val = LSM6DSV16X_ODR_HA01_AT_15Hz625;
580 break;
581 case 2:
582 *val = LSM6DSV16X_ODR_HA02_AT_12Hz5;
583 break;
584 }
585 break;
586
587 case LSM6DSV16X_ODR_AT_30Hz:
588 switch (sel) {
589 default:
590 case 0:
591 *val = LSM6DSV16X_ODR_AT_30Hz;
592 break;
593 case 1:
594 *val = LSM6DSV16X_ODR_HA01_AT_31Hz25;
595 break;
596 case 2:
597 *val = LSM6DSV16X_ODR_HA02_AT_25Hz;
598 break;
599 }
600 break;
601
602 case LSM6DSV16X_ODR_AT_60Hz:
603 switch (sel) {
604 default:
605 case 0:
606 *val = LSM6DSV16X_ODR_AT_60Hz;
607 break;
608 case 1:
609 *val = LSM6DSV16X_ODR_HA01_AT_62Hz5;
610 break;
611 case 2:
612 *val = LSM6DSV16X_ODR_HA02_AT_50Hz;
613 break;
614 }
615 break;
616
617 case LSM6DSV16X_ODR_AT_120Hz:
618 switch (sel) {
619 default:
620 case 0:
621 *val = LSM6DSV16X_ODR_AT_120Hz;
622 break;
623 case 1:
624 *val = LSM6DSV16X_ODR_HA01_AT_125Hz;
625 break;
626 case 2:
627 *val = LSM6DSV16X_ODR_HA02_AT_100Hz;
628 break;
629 }
630 break;
631
632 case LSM6DSV16X_ODR_AT_240Hz:
633 switch (sel) {
634 default:
635 case 0:
636 *val = LSM6DSV16X_ODR_AT_240Hz;
637 break;
638 case 1:
639 *val = LSM6DSV16X_ODR_HA01_AT_250Hz;
640 break;
641 case 2:
642 *val = LSM6DSV16X_ODR_HA02_AT_200Hz;
643 break;
644 }
645 break;
646
647 case LSM6DSV16X_ODR_AT_480Hz:
648 switch (sel) {
649 default:
650 case 0:
651 *val = LSM6DSV16X_ODR_AT_480Hz;
652 break;
653 case 1:
654 *val = LSM6DSV16X_ODR_HA01_AT_500Hz;
655 break;
656 case 2:
657 *val = LSM6DSV16X_ODR_HA02_AT_400Hz;
658 break;
659 }
660 break;
661
662 case LSM6DSV16X_ODR_AT_960Hz:
663 switch (sel) {
664 default:
665 case 0:
666 *val = LSM6DSV16X_ODR_AT_960Hz;
667 break;
668 case 1:
669 *val = LSM6DSV16X_ODR_HA01_AT_1000Hz;
670 break;
671 case 2:
672 *val = LSM6DSV16X_ODR_HA02_AT_800Hz;
673 break;
674 }
675 break;
676
677 case LSM6DSV16X_ODR_AT_1920Hz:
678 switch (sel) {
679 default:
680 case 0:
681 *val = LSM6DSV16X_ODR_AT_1920Hz;
682 break;
683 case 1:
684 *val = LSM6DSV16X_ODR_HA01_AT_2000Hz;
685 break;
686 case 2:
687 *val = LSM6DSV16X_ODR_HA02_AT_1600Hz;
688 break;
689 }
690 break;
691
692 case LSM6DSV16X_ODR_AT_3840Hz:
693 switch (sel) {
694 default:
695 case 0:
696 *val = LSM6DSV16X_ODR_AT_3840Hz;
697 break;
698 case 1:
699 *val = LSM6DSV16X_ODR_HA01_AT_4000Hz;
700 break;
701 case 2:
702 *val = LSM6DSV16X_ODR_HA02_AT_3200Hz;
703 break;
704 }
705 break;
706
707 case LSM6DSV16X_ODR_AT_7680Hz:
708 switch (sel) {
709 default:
710 case 0:
711 *val = LSM6DSV16X_ODR_AT_7680Hz;
712 break;
713 case 1:
714 *val = LSM6DSV16X_ODR_HA01_AT_8000Hz;
715 break;
716 case 2:
717 *val = LSM6DSV16X_ODR_HA02_AT_6400Hz;
718 break;
719 }
720 break;
721
722 default:
723 *val = LSM6DSV16X_ODR_OFF;
724 break;
725 }
726
727 return ret;
728 }
729
730 /**
731 * @brief Accelerometer operating mode selection.[set]
732 *
733 * @param ctx read / write interface definitions
734 * @param val XL_HIGH_PERFORMANCE_MD, XL_HIGH_ACCURACY_ODR_MD, XL_LOW_POWER_2_AVG_MD, XL_LOW_POWER_4_AVG_MD, XL_LOW_POWER_8_AVG_MD, XL_NORMAL_MD,
735 * @retval interface status (MANDATORY: return 0 -> no Error)
736 *
737 */
lsm6dsv16x_xl_mode_set(stmdev_ctx_t * ctx,lsm6dsv16x_xl_mode_t val)738 int32_t lsm6dsv16x_xl_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_xl_mode_t val)
739 {
740 lsm6dsv16x_ctrl1_t ctrl1;
741 int32_t ret;
742
743 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL1, (uint8_t *)&ctrl1, 1);
744
745 if (ret == 0)
746 {
747 ctrl1.op_mode_xl = (uint8_t)val & 0x07U;
748 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL1, (uint8_t *)&ctrl1, 1);
749 }
750
751 return ret;
752 }
753
754 /**
755 * @brief Accelerometer operating mode selection.[get]
756 *
757 * @param ctx read / write interface definitions
758 * @param val XL_HIGH_PERFORMANCE_MD, XL_HIGH_ACCURACY_ODR_MD, XL_LOW_POWER_2_AVG_MD, XL_LOW_POWER_4_AVG_MD, XL_LOW_POWER_8_AVG_MD, XL_NORMAL_MD,
759 * @retval interface status (MANDATORY: return 0 -> no Error)
760 *
761 */
lsm6dsv16x_xl_mode_get(stmdev_ctx_t * ctx,lsm6dsv16x_xl_mode_t * val)762 int32_t lsm6dsv16x_xl_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_xl_mode_t *val)
763 {
764 lsm6dsv16x_ctrl1_t ctrl1;
765 int32_t ret;
766
767 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL1, (uint8_t *)&ctrl1, 1);
768 if (ret != 0) { return ret; }
769
770 switch (ctrl1.op_mode_xl)
771 {
772 case LSM6DSV16X_XL_HIGH_PERFORMANCE_MD:
773 *val = LSM6DSV16X_XL_HIGH_PERFORMANCE_MD;
774 break;
775
776 case LSM6DSV16X_XL_HIGH_ACCURACY_ODR_MD:
777 *val = LSM6DSV16X_XL_HIGH_ACCURACY_ODR_MD;
778 break;
779
780 case LSM6DSV16X_XL_ODR_TRIGGERED_MD:
781 *val = LSM6DSV16X_XL_ODR_TRIGGERED_MD;
782 break;
783
784 case LSM6DSV16X_XL_LOW_POWER_2_AVG_MD:
785 *val = LSM6DSV16X_XL_LOW_POWER_2_AVG_MD;
786 break;
787
788 case LSM6DSV16X_XL_LOW_POWER_4_AVG_MD:
789 *val = LSM6DSV16X_XL_LOW_POWER_4_AVG_MD;
790 break;
791
792 case LSM6DSV16X_XL_LOW_POWER_8_AVG_MD:
793 *val = LSM6DSV16X_XL_LOW_POWER_8_AVG_MD;
794 break;
795
796 case LSM6DSV16X_XL_NORMAL_MD:
797 *val = LSM6DSV16X_XL_NORMAL_MD;
798 break;
799
800 default:
801 *val = LSM6DSV16X_XL_HIGH_PERFORMANCE_MD;
802 break;
803 }
804
805 return ret;
806 }
807
808 /**
809 * @brief Gyroscope output data rate (ODR) selection.[set]
810 *
811 * @param ctx read / write interface definitions
812 * @param val lsm6dsv16x_data_rate_t enum
813 * @retval interface status (MANDATORY: return 0 -> no Error)
814 *
815 */
lsm6dsv16x_gy_data_rate_set(stmdev_ctx_t * ctx,lsm6dsv16x_data_rate_t val)816 int32_t lsm6dsv16x_gy_data_rate_set(stmdev_ctx_t *ctx,
817 lsm6dsv16x_data_rate_t val)
818 {
819 lsm6dsv16x_ctrl2_t ctrl2;
820 lsm6dsv16x_haodr_cfg_t haodr;
821 uint8_t sel;
822 int32_t ret;
823
824 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL2, (uint8_t *)&ctrl2, 1);
825 ctrl2.odr_g = (uint8_t)val & 0x0Fu;
826 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL2, (uint8_t *)&ctrl2, 1);
827 if (ret != 0) { return ret; }
828
829 sel = ((uint8_t)val >> 4) & 0xFU;
830 if (sel != 0U)
831 {
832 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_HAODR_CFG, (uint8_t *)&haodr, 1);
833 haodr.haodr_sel = sel;
834 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_HAODR_CFG, (uint8_t *)&haodr, 1);
835 }
836
837 return ret;
838 }
839
840 /**
841 * @brief Gyroscope output data rate (ODR) selection.[get]
842 *
843 * @param ctx read / write interface definitions
844 * @param val lsm6dsv16x_data_rate_t enum
845 * @retval interface status (MANDATORY: return 0 -> no Error)
846 *
847 */
lsm6dsv16x_gy_data_rate_get(stmdev_ctx_t * ctx,lsm6dsv16x_data_rate_t * val)848 int32_t lsm6dsv16x_gy_data_rate_get(stmdev_ctx_t *ctx,
849 lsm6dsv16x_data_rate_t *val)
850 {
851 lsm6dsv16x_ctrl2_t ctrl2;
852 lsm6dsv16x_haodr_cfg_t haodr;
853 uint8_t sel;
854 int32_t ret;
855
856 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL2, (uint8_t *)&ctrl2, 1);
857 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_HAODR_CFG, (uint8_t *)&haodr, 1);
858 if (ret != 0) { return ret; }
859
860 sel = haodr.haodr_sel;
861
862 switch (ctrl2.odr_g)
863 {
864 case LSM6DSV16X_ODR_OFF:
865 *val = LSM6DSV16X_ODR_OFF;
866 break;
867
868 case LSM6DSV16X_ODR_AT_1Hz875:
869 *val = LSM6DSV16X_ODR_AT_1Hz875;
870 break;
871
872 case LSM6DSV16X_ODR_AT_7Hz5:
873 *val = LSM6DSV16X_ODR_AT_7Hz5;
874 break;
875
876 case LSM6DSV16X_ODR_AT_15Hz:
877 switch (sel) {
878 default:
879 case 0:
880 *val = LSM6DSV16X_ODR_AT_15Hz;
881 break;
882 case 1:
883 *val = LSM6DSV16X_ODR_HA01_AT_15Hz625;
884 break;
885 case 2:
886 *val = LSM6DSV16X_ODR_HA02_AT_12Hz5;
887 break;
888 }
889 break;
890
891 case LSM6DSV16X_ODR_AT_30Hz:
892 switch (sel) {
893 default:
894 case 0:
895 *val = LSM6DSV16X_ODR_AT_30Hz;
896 break;
897 case 1:
898 *val = LSM6DSV16X_ODR_HA01_AT_31Hz25;
899 break;
900 case 2:
901 *val = LSM6DSV16X_ODR_HA02_AT_25Hz;
902 break;
903 }
904 break;
905
906 case LSM6DSV16X_ODR_AT_60Hz:
907 switch (sel) {
908 default:
909 case 0:
910 *val = LSM6DSV16X_ODR_AT_60Hz;
911 break;
912 case 1:
913 *val = LSM6DSV16X_ODR_HA01_AT_62Hz5;
914 break;
915 case 2:
916 *val = LSM6DSV16X_ODR_HA02_AT_50Hz;
917 break;
918 }
919 break;
920
921 case LSM6DSV16X_ODR_AT_120Hz:
922 switch (sel) {
923 default:
924 case 0:
925 *val = LSM6DSV16X_ODR_AT_120Hz;
926 break;
927 case 1:
928 *val = LSM6DSV16X_ODR_HA01_AT_125Hz;
929 break;
930 case 2:
931 *val = LSM6DSV16X_ODR_HA02_AT_100Hz;
932 break;
933 }
934 break;
935
936 case LSM6DSV16X_ODR_AT_240Hz:
937 switch (sel) {
938 default:
939 case 0:
940 *val = LSM6DSV16X_ODR_AT_240Hz;
941 break;
942 case 1:
943 *val = LSM6DSV16X_ODR_HA01_AT_250Hz;
944 break;
945 case 2:
946 *val = LSM6DSV16X_ODR_HA02_AT_200Hz;
947 break;
948 }
949 break;
950
951 case LSM6DSV16X_ODR_AT_480Hz:
952 switch (sel) {
953 default:
954 case 0:
955 *val = LSM6DSV16X_ODR_AT_480Hz;
956 break;
957 case 1:
958 *val = LSM6DSV16X_ODR_HA01_AT_500Hz;
959 break;
960 case 2:
961 *val = LSM6DSV16X_ODR_HA02_AT_400Hz;
962 break;
963 }
964 break;
965
966 case LSM6DSV16X_ODR_AT_960Hz:
967 switch (sel) {
968 default:
969 case 0:
970 *val = LSM6DSV16X_ODR_AT_960Hz;
971 break;
972 case 1:
973 *val = LSM6DSV16X_ODR_HA01_AT_1000Hz;
974 break;
975 case 2:
976 *val = LSM6DSV16X_ODR_HA02_AT_800Hz;
977 break;
978 }
979 break;
980
981 case LSM6DSV16X_ODR_AT_1920Hz:
982 switch (sel) {
983 default:
984 case 0:
985 *val = LSM6DSV16X_ODR_AT_1920Hz;
986 break;
987 case 1:
988 *val = LSM6DSV16X_ODR_HA01_AT_2000Hz;
989 break;
990 case 2:
991 *val = LSM6DSV16X_ODR_HA02_AT_1600Hz;
992 break;
993 }
994 break;
995
996 case LSM6DSV16X_ODR_AT_3840Hz:
997 switch (sel) {
998 default:
999 case 0:
1000 *val = LSM6DSV16X_ODR_AT_3840Hz;
1001 break;
1002 case 1:
1003 *val = LSM6DSV16X_ODR_HA01_AT_4000Hz;
1004 break;
1005 case 2:
1006 *val = LSM6DSV16X_ODR_HA02_AT_3200Hz;
1007 break;
1008 }
1009 break;
1010
1011 case LSM6DSV16X_ODR_AT_7680Hz:
1012 switch (sel) {
1013 default:
1014 case 0:
1015 *val = LSM6DSV16X_ODR_AT_7680Hz;
1016 break;
1017 case 1:
1018 *val = LSM6DSV16X_ODR_HA01_AT_8000Hz;
1019 break;
1020 case 2:
1021 *val = LSM6DSV16X_ODR_HA02_AT_6400Hz;
1022 break;
1023 }
1024 break;
1025
1026 default:
1027 *val = LSM6DSV16X_ODR_OFF;
1028 break;
1029 }
1030
1031 return ret;
1032 }
1033
1034 /**
1035 * @brief Gyroscope operating mode selection.[set]
1036 *
1037 * @param ctx read / write interface definitions
1038 * @param val GY_HIGH_PERFORMANCE_MD, GY_HIGH_ACCURACY_ODR_MD, GY_SLEEP_MD, GY_LOW_POWER_MD,
1039 * @retval interface status (MANDATORY: return 0 -> no Error)
1040 *
1041 */
lsm6dsv16x_gy_mode_set(stmdev_ctx_t * ctx,lsm6dsv16x_gy_mode_t val)1042 int32_t lsm6dsv16x_gy_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_gy_mode_t val)
1043 {
1044 lsm6dsv16x_ctrl2_t ctrl2;
1045 int32_t ret;
1046
1047 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL2, (uint8_t *)&ctrl2, 1);
1048 if (ret == 0)
1049 {
1050 ctrl2.op_mode_g = (uint8_t)val & 0x07U;
1051 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL2, (uint8_t *)&ctrl2, 1);
1052 }
1053
1054 return ret;
1055 }
1056
1057 /**
1058 * @brief Gyroscope operating mode selection.[get]
1059 *
1060 * @param ctx read / write interface definitions
1061 * @param val GY_HIGH_PERFORMANCE_MD, GY_HIGH_ACCURACY_ODR_MD, GY_SLEEP_MD, GY_LOW_POWER_MD,
1062 * @retval interface status (MANDATORY: return 0 -> no Error)
1063 *
1064 */
lsm6dsv16x_gy_mode_get(stmdev_ctx_t * ctx,lsm6dsv16x_gy_mode_t * val)1065 int32_t lsm6dsv16x_gy_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_gy_mode_t *val)
1066 {
1067 lsm6dsv16x_ctrl2_t ctrl2;
1068 int32_t ret;
1069
1070 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL2, (uint8_t *)&ctrl2, 1);
1071 if (ret != 0) { return ret; }
1072
1073 switch (ctrl2.op_mode_g)
1074 {
1075 case LSM6DSV16X_GY_HIGH_PERFORMANCE_MD:
1076 *val = LSM6DSV16X_GY_HIGH_PERFORMANCE_MD;
1077 break;
1078
1079 case LSM6DSV16X_GY_HIGH_ACCURACY_ODR_MD:
1080 *val = LSM6DSV16X_GY_HIGH_ACCURACY_ODR_MD;
1081 break;
1082
1083 case LSM6DSV16X_GY_SLEEP_MD:
1084 *val = LSM6DSV16X_GY_SLEEP_MD;
1085 break;
1086
1087 case LSM6DSV16X_GY_LOW_POWER_MD:
1088 *val = LSM6DSV16X_GY_LOW_POWER_MD;
1089 break;
1090
1091 default:
1092 *val = LSM6DSV16X_GY_HIGH_PERFORMANCE_MD;
1093 break;
1094 }
1095
1096 return ret;
1097 }
1098
1099 /**
1100 * @brief Register address automatically incremented during a multiple byte access with a serial interface (enable by default).[set]
1101 *
1102 * @param ctx read / write interface definitions
1103 * @param val Register address automatically incremented during a multiple byte access with a serial interface (enable by default).
1104 * @retval interface status (MANDATORY: return 0 -> no Error)
1105 *
1106 */
lsm6dsv16x_auto_increment_set(stmdev_ctx_t * ctx,uint8_t val)1107 int32_t lsm6dsv16x_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
1108 {
1109 lsm6dsv16x_ctrl3_t ctrl3;
1110 int32_t ret;
1111
1112 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL3, (uint8_t *)&ctrl3, 1);
1113 if (ret == 0)
1114 {
1115 ctrl3.if_inc = val;
1116 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL3, (uint8_t *)&ctrl3, 1);
1117 }
1118
1119 return ret;
1120 }
1121
1122 /**
1123 * @brief Register address automatically incremented during a multiple byte access with a serial interface (enable by default).[get]
1124 *
1125 * @param ctx read / write interface definitions
1126 * @param val Register address automatically incremented during a multiple byte access with a serial interface (enable by default).
1127 * @retval interface status (MANDATORY: return 0 -> no Error)
1128 *
1129 */
lsm6dsv16x_auto_increment_get(stmdev_ctx_t * ctx,uint8_t * val)1130 int32_t lsm6dsv16x_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
1131 {
1132 lsm6dsv16x_ctrl3_t ctrl3;
1133 int32_t ret;
1134
1135 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL3, (uint8_t *)&ctrl3, 1);
1136 *val = ctrl3.if_inc;
1137
1138 return ret;
1139 }
1140
1141 /**
1142 * @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [set]
1143 *
1144 * @param ctx read / write interface definitions
1145 * @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read).
1146 * @retval interface status (MANDATORY: return 0 -> no Error)
1147 *
1148 */
lsm6dsv16x_block_data_update_set(stmdev_ctx_t * ctx,uint8_t val)1149 int32_t lsm6dsv16x_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
1150 {
1151 lsm6dsv16x_ctrl3_t ctrl3;
1152 int32_t ret;
1153
1154 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL3, (uint8_t *)&ctrl3, 1);
1155
1156 if (ret == 0)
1157 {
1158 ctrl3.bdu = val;
1159 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL3, (uint8_t *)&ctrl3, 1);
1160 }
1161
1162 return ret;
1163 }
1164
1165 /**
1166 * @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [get]
1167 *
1168 * @param ctx read / write interface definitions
1169 * @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read).
1170 * @retval interface status (MANDATORY: return 0 -> no Error)
1171 *
1172 */
lsm6dsv16x_block_data_update_get(stmdev_ctx_t * ctx,uint8_t * val)1173 int32_t lsm6dsv16x_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
1174 {
1175 lsm6dsv16x_ctrl3_t ctrl3;
1176 int32_t ret;
1177
1178 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL3, (uint8_t *)&ctrl3, 1);
1179 *val = ctrl3.bdu;
1180
1181 return ret;
1182 }
1183
1184 /**
1185 * @brief Configure ODR trigger. [set]
1186 *
1187 * @param ctx read / write interface definitions
1188 * @param val number of data in the reference period.
1189 * @retval interface status (MANDATORY: return 0 -> no Error)
1190 *
1191 */
lsm6dsv16x_odr_trig_cfg_set(stmdev_ctx_t * ctx,uint8_t val)1192 int32_t lsm6dsv16x_odr_trig_cfg_set(stmdev_ctx_t *ctx, uint8_t val)
1193 {
1194 lsm6dsv16x_odr_trig_cfg_t odr_trig;
1195 int32_t ret;
1196
1197 if (val >= 1U && val <= 3U) {
1198 return -1;
1199 }
1200
1201 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_ODR_TRIG_CFG, (uint8_t *)&odr_trig, 1);
1202
1203 if (ret == 0)
1204 {
1205 odr_trig.odr_trig_nodr = val;
1206 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_ODR_TRIG_CFG, (uint8_t *)&odr_trig, 1);
1207 }
1208
1209 return ret;
1210 }
1211
1212 /**
1213 * @brief Configure ODR trigger. [get]
1214 *
1215 * @param ctx read / write interface definitions
1216 * @param val number of data in the reference period.
1217 * @retval interface status (MANDATORY: return 0 -> no Error)
1218 *
1219 */
lsm6dsv16x_odr_trig_cfg_get(stmdev_ctx_t * ctx,uint8_t * val)1220 int32_t lsm6dsv16x_odr_trig_cfg_get(stmdev_ctx_t *ctx, uint8_t *val)
1221 {
1222 lsm6dsv16x_odr_trig_cfg_t odr_trig;
1223 int32_t ret;
1224
1225 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_ODR_TRIG_CFG, (uint8_t *)&odr_trig, 1);
1226 *val = odr_trig.odr_trig_nodr;
1227
1228 return ret;
1229 }
1230
1231 /**
1232 * @brief Enables pulsed data-ready mode (~75 us).[set]
1233 *
1234 * @param ctx read / write interface definitions
1235 * @param val DRDY_LATCHED, DRDY_PULSED,
1236 * @retval interface status (MANDATORY: return 0 -> no Error)
1237 *
1238 */
lsm6dsv16x_data_ready_mode_set(stmdev_ctx_t * ctx,lsm6dsv16x_data_ready_mode_t val)1239 int32_t lsm6dsv16x_data_ready_mode_set(stmdev_ctx_t *ctx,
1240 lsm6dsv16x_data_ready_mode_t val)
1241 {
1242 lsm6dsv16x_ctrl4_t ctrl4;
1243 int32_t ret;
1244
1245 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL4, (uint8_t *)&ctrl4, 1);
1246
1247 if (ret == 0)
1248 {
1249 ctrl4.drdy_pulsed = (uint8_t)val & 0x1U;
1250 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL4, (uint8_t *)&ctrl4, 1);
1251 }
1252
1253 return ret;
1254 }
1255
1256 /**
1257 * @brief Enables pulsed data-ready mode (~75 us).[get]
1258 *
1259 * @param ctx read / write interface definitions
1260 * @param val DRDY_LATCHED, DRDY_PULSED,
1261 * @retval interface status (MANDATORY: return 0 -> no Error)
1262 *
1263 */
lsm6dsv16x_data_ready_mode_get(stmdev_ctx_t * ctx,lsm6dsv16x_data_ready_mode_t * val)1264 int32_t lsm6dsv16x_data_ready_mode_get(stmdev_ctx_t *ctx,
1265 lsm6dsv16x_data_ready_mode_t *val)
1266 {
1267 lsm6dsv16x_ctrl4_t ctrl4;
1268 int32_t ret;
1269
1270 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL4, (uint8_t *)&ctrl4, 1);
1271
1272 switch (ctrl4.drdy_pulsed)
1273 {
1274 case LSM6DSV16X_DRDY_LATCHED:
1275 *val = LSM6DSV16X_DRDY_LATCHED;
1276 break;
1277
1278 case LSM6DSV16X_DRDY_PULSED:
1279 *val = LSM6DSV16X_DRDY_PULSED;
1280 break;
1281
1282 default:
1283 *val = LSM6DSV16X_DRDY_LATCHED;
1284 break;
1285 }
1286
1287 return ret;
1288 }
1289
1290 /**
1291 * @brief Enables interrupt.[set]
1292 *
1293 * @param ctx read / write interface definitions
1294 * @param val enable/disable, latched/pulsed
1295 * @retval interface status (MANDATORY: return 0 -> no Error)
1296 *
1297 */
lsm6dsv16x_interrupt_enable_set(stmdev_ctx_t * ctx,lsm6dsv16x_interrupt_mode_t val)1298 int32_t lsm6dsv16x_interrupt_enable_set(stmdev_ctx_t *ctx,
1299 lsm6dsv16x_interrupt_mode_t val)
1300 {
1301 lsm6dsv16x_tap_cfg0_t cfg;
1302 lsm6dsv16x_functions_enable_t func;
1303 int32_t ret;
1304
1305 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&func, 1);
1306 func.interrupts_enable = val.enable;
1307 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&func, 1);
1308 if (ret != 0) { return ret; }
1309
1310 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&cfg, 1);
1311 cfg.lir = val.lir;
1312 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&cfg, 1);
1313
1314 return ret;
1315 }
1316
1317 /**
1318 * @brief Enables latched interrupt mode.[get]
1319 *
1320 * @param ctx read / write interface definitions
1321 * @param val enable/disable, latched/pulsed
1322 * @retval interface status (MANDATORY: return 0 -> no Error)
1323 *
1324 */
lsm6dsv16x_interrupt_enable_get(stmdev_ctx_t * ctx,lsm6dsv16x_interrupt_mode_t * val)1325 int32_t lsm6dsv16x_interrupt_enable_get(stmdev_ctx_t *ctx,
1326 lsm6dsv16x_interrupt_mode_t *val)
1327 {
1328 lsm6dsv16x_tap_cfg0_t cfg;
1329 lsm6dsv16x_functions_enable_t func;
1330 int32_t ret;
1331
1332 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&func, 1);
1333 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&cfg, 1);
1334 if (ret != 0) { return ret; }
1335
1336 val->enable = func.interrupts_enable;
1337 val->lir = cfg.lir;
1338
1339 return ret;
1340 }
1341
1342 /**
1343 * @brief Gyroscope full-scale selection[set]
1344 *
1345 * @param ctx read / write interface definitions
1346 * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps,
1347 * @retval interface status (MANDATORY: return 0 -> no Error)
1348 *
1349 */
lsm6dsv16x_gy_full_scale_set(stmdev_ctx_t * ctx,lsm6dsv16x_gy_full_scale_t val)1350 int32_t lsm6dsv16x_gy_full_scale_set(stmdev_ctx_t *ctx,
1351 lsm6dsv16x_gy_full_scale_t val)
1352 {
1353 lsm6dsv16x_ctrl6_t ctrl6;
1354 int32_t ret;
1355
1356 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL6, (uint8_t *)&ctrl6, 1);
1357
1358 if (ret == 0)
1359 {
1360 ctrl6.fs_g = (uint8_t)val & 0xfu;
1361 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL6, (uint8_t *)&ctrl6, 1);
1362 }
1363
1364 return ret;
1365 }
1366
1367 /**
1368 * @brief Gyroscope full-scale selection[get]
1369 *
1370 * @param ctx read / write interface definitions
1371 * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps,
1372 * @retval interface status (MANDATORY: return 0 -> no Error)
1373 *
1374 */
lsm6dsv16x_gy_full_scale_get(stmdev_ctx_t * ctx,lsm6dsv16x_gy_full_scale_t * val)1375 int32_t lsm6dsv16x_gy_full_scale_get(stmdev_ctx_t *ctx,
1376 lsm6dsv16x_gy_full_scale_t *val)
1377 {
1378 lsm6dsv16x_ctrl6_t ctrl6;
1379 int32_t ret;
1380
1381 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL6, (uint8_t *)&ctrl6, 1);
1382 if (ret != 0) { return ret; }
1383
1384 switch (ctrl6.fs_g)
1385 {
1386 case LSM6DSV16X_125dps:
1387 *val = LSM6DSV16X_125dps;
1388 break;
1389
1390 case LSM6DSV16X_250dps:
1391 *val = LSM6DSV16X_250dps;
1392 break;
1393
1394 case LSM6DSV16X_500dps:
1395 *val = LSM6DSV16X_500dps;
1396 break;
1397
1398 case LSM6DSV16X_1000dps:
1399 *val = LSM6DSV16X_1000dps;
1400 break;
1401
1402 case LSM6DSV16X_2000dps:
1403 *val = LSM6DSV16X_2000dps;
1404 break;
1405
1406 case LSM6DSV16X_4000dps:
1407 *val = LSM6DSV16X_4000dps;
1408 break;
1409
1410 default:
1411 *val = LSM6DSV16X_125dps;
1412 break;
1413 }
1414
1415 return ret;
1416 }
1417
1418 /**
1419 * @brief Accelerometer full-scale selection.[set]
1420 *
1421 * @param ctx read / write interface definitions
1422 * @param val 2g, 4g, 8g, 16g,
1423 * @retval interface status (MANDATORY: return 0 -> no Error)
1424 *
1425 */
lsm6dsv16x_xl_full_scale_set(stmdev_ctx_t * ctx,lsm6dsv16x_xl_full_scale_t val)1426 int32_t lsm6dsv16x_xl_full_scale_set(stmdev_ctx_t *ctx,
1427 lsm6dsv16x_xl_full_scale_t val)
1428 {
1429 lsm6dsv16x_ctrl8_t ctrl8;
1430 int32_t ret;
1431
1432 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL8, (uint8_t *)&ctrl8, 1);
1433
1434 if (ret == 0)
1435 {
1436 ctrl8.fs_xl = (uint8_t)val & 0x3U;
1437 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL8, (uint8_t *)&ctrl8, 1);
1438 }
1439
1440 return ret;
1441 }
1442
1443 /**
1444 * @brief Accelerometer full-scale selection.[get]
1445 *
1446 * @param ctx read / write interface definitions
1447 * @param val 2g, 4g, 8g, 16g,
1448 * @retval interface status (MANDATORY: return 0 -> no Error)
1449 *
1450 */
lsm6dsv16x_xl_full_scale_get(stmdev_ctx_t * ctx,lsm6dsv16x_xl_full_scale_t * val)1451 int32_t lsm6dsv16x_xl_full_scale_get(stmdev_ctx_t *ctx,
1452 lsm6dsv16x_xl_full_scale_t *val)
1453 {
1454 lsm6dsv16x_ctrl8_t ctrl8;
1455 int32_t ret;
1456
1457 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL8, (uint8_t *)&ctrl8, 1);
1458 if (ret != 0) { return ret; }
1459
1460 switch (ctrl8.fs_xl)
1461 {
1462 case LSM6DSV16X_2g:
1463 *val = LSM6DSV16X_2g;
1464 break;
1465
1466 case LSM6DSV16X_4g:
1467 *val = LSM6DSV16X_4g;
1468 break;
1469
1470 case LSM6DSV16X_8g:
1471 *val = LSM6DSV16X_8g;
1472 break;
1473
1474 case LSM6DSV16X_16g:
1475 *val = LSM6DSV16X_16g;
1476 break;
1477
1478 default:
1479 *val = LSM6DSV16X_2g;
1480 break;
1481 }
1482
1483 return ret;
1484 }
1485
1486 /**
1487 * @brief It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.[set]
1488 *
1489 * @param ctx read / write interface definitions
1490 * @param val It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.
1491 * @retval interface status (MANDATORY: return 0 -> no Error)
1492 *
1493 */
lsm6dsv16x_xl_dual_channel_set(stmdev_ctx_t * ctx,uint8_t val)1494 int32_t lsm6dsv16x_xl_dual_channel_set(stmdev_ctx_t *ctx, uint8_t val)
1495 {
1496 lsm6dsv16x_ctrl8_t ctrl8;
1497 int32_t ret;
1498
1499 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL8, (uint8_t *)&ctrl8, 1);
1500
1501 if (ret == 0)
1502 {
1503 ctrl8.xl_dualc_en = val;
1504 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL8, (uint8_t *)&ctrl8, 1);
1505 }
1506
1507 return ret;
1508 }
1509
1510 /**
1511 * @brief It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.[get]
1512 *
1513 * @param ctx read / write interface definitions
1514 * @param val It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.
1515 * @retval interface status (MANDATORY: return 0 -> no Error)
1516 *
1517 */
lsm6dsv16x_xl_dual_channel_get(stmdev_ctx_t * ctx,uint8_t * val)1518 int32_t lsm6dsv16x_xl_dual_channel_get(stmdev_ctx_t *ctx, uint8_t *val)
1519 {
1520 lsm6dsv16x_ctrl8_t ctrl8;
1521 int32_t ret;
1522
1523 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL8, (uint8_t *)&ctrl8, 1);
1524 *val = ctrl8.xl_dualc_en;
1525
1526 return ret;
1527 }
1528
1529 /**
1530 * @brief Accelerometer self-test selection.[set]
1531 *
1532 * @param ctx read / write interface definitions
1533 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1534 * @retval interface status (MANDATORY: return 0 -> no Error)
1535 *
1536 */
lsm6dsv16x_xl_self_test_set(stmdev_ctx_t * ctx,lsm6dsv16x_xl_self_test_t val)1537 int32_t lsm6dsv16x_xl_self_test_set(stmdev_ctx_t *ctx,
1538 lsm6dsv16x_xl_self_test_t val)
1539 {
1540 lsm6dsv16x_ctrl10_t ctrl10;
1541 int32_t ret;
1542
1543 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL10, (uint8_t *)&ctrl10, 1);
1544
1545 if (ret == 0)
1546 {
1547 ctrl10.st_xl = (uint8_t)val & 0x3U;
1548 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL10, (uint8_t *)&ctrl10, 1);
1549 }
1550
1551 return ret;
1552 }
1553
1554 /**
1555 * @brief Accelerometer self-test selection.[get]
1556 *
1557 * @param ctx read / write interface definitions
1558 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1559 * @retval interface status (MANDATORY: return 0 -> no Error)
1560 *
1561 */
lsm6dsv16x_xl_self_test_get(stmdev_ctx_t * ctx,lsm6dsv16x_xl_self_test_t * val)1562 int32_t lsm6dsv16x_xl_self_test_get(stmdev_ctx_t *ctx,
1563 lsm6dsv16x_xl_self_test_t *val)
1564 {
1565 lsm6dsv16x_ctrl10_t ctrl10;
1566 int32_t ret;
1567
1568 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL10, (uint8_t *)&ctrl10, 1);
1569 if (ret != 0) { return ret; }
1570
1571 switch (ctrl10.st_xl)
1572 {
1573 case LSM6DSV16X_XL_ST_DISABLE:
1574 *val = LSM6DSV16X_XL_ST_DISABLE;
1575 break;
1576
1577 case LSM6DSV16X_XL_ST_POSITIVE:
1578 *val = LSM6DSV16X_XL_ST_POSITIVE;
1579 break;
1580
1581 case LSM6DSV16X_XL_ST_NEGATIVE:
1582 *val = LSM6DSV16X_XL_ST_NEGATIVE;
1583 break;
1584
1585 default:
1586 *val = LSM6DSV16X_XL_ST_DISABLE;
1587 break;
1588 }
1589
1590 return ret;
1591 }
1592
1593 /**
1594 * @brief Gyroscope self-test selection.[set]
1595 *
1596 * @param ctx read / write interface definitions
1597 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1598 * @retval interface status (MANDATORY: return 0 -> no Error)
1599 *
1600 */
lsm6dsv16x_gy_self_test_set(stmdev_ctx_t * ctx,lsm6dsv16x_gy_self_test_t val)1601 int32_t lsm6dsv16x_gy_self_test_set(stmdev_ctx_t *ctx,
1602 lsm6dsv16x_gy_self_test_t val)
1603 {
1604 lsm6dsv16x_ctrl10_t ctrl10;
1605 int32_t ret;
1606
1607 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL10, (uint8_t *)&ctrl10, 1);
1608
1609 if (ret == 0)
1610 {
1611 ctrl10.st_g = (uint8_t)val & 0x3U;
1612 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL10, (uint8_t *)&ctrl10, 1);
1613 }
1614
1615 return ret;
1616 }
1617
1618 /**
1619 * @brief Gyroscope self-test selection.[get]
1620 *
1621 * @param ctx read / write interface definitions
1622 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1623 * @retval interface status (MANDATORY: return 0 -> no Error)
1624 *
1625 */
lsm6dsv16x_gy_self_test_get(stmdev_ctx_t * ctx,lsm6dsv16x_gy_self_test_t * val)1626 int32_t lsm6dsv16x_gy_self_test_get(stmdev_ctx_t *ctx,
1627 lsm6dsv16x_gy_self_test_t *val)
1628 {
1629 lsm6dsv16x_ctrl10_t ctrl10;
1630 int32_t ret;
1631
1632 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL10, (uint8_t *)&ctrl10, 1);
1633 if (ret != 0) { return ret; }
1634
1635 switch (ctrl10.st_g)
1636 {
1637 case LSM6DSV16X_GY_ST_DISABLE:
1638 *val = LSM6DSV16X_GY_ST_DISABLE;
1639 break;
1640
1641 case LSM6DSV16X_GY_ST_POSITIVE:
1642 *val = LSM6DSV16X_GY_ST_POSITIVE;
1643 break;
1644
1645 case LSM6DSV16X_GY_ST_NEGATIVE:
1646 *val = LSM6DSV16X_GY_ST_NEGATIVE;
1647 break;
1648
1649 default:
1650 *val = LSM6DSV16X_GY_ST_DISABLE;
1651 break;
1652 }
1653
1654 return ret;
1655 }
1656
1657 /**
1658 * @brief SPI2 Accelerometer self-test selection.[set]
1659 *
1660 * @param ctx read / write interface definitions
1661 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1662 * @retval interface status (MANDATORY: return 0 -> no Error)
1663 *
1664 */
lsm6dsv16x_ois_xl_self_test_set(stmdev_ctx_t * ctx,lsm6dsv16x_ois_xl_self_test_t val)1665 int32_t lsm6dsv16x_ois_xl_self_test_set(stmdev_ctx_t *ctx,
1666 lsm6dsv16x_ois_xl_self_test_t val)
1667 {
1668 lsm6dsv16x_spi2_int_ois_t spi2_int_ois;
1669 int32_t ret;
1670
1671 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1);
1672
1673 if (ret == 0)
1674 {
1675 spi2_int_ois.st_xl_ois = ((uint8_t)val & 0x3U);
1676 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1);
1677 }
1678
1679 return ret;
1680 }
1681
1682 /**
1683 * @brief SPI2 Accelerometer self-test selection.[get]
1684 *
1685 * @param ctx read / write interface definitions
1686 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1687 * @retval interface status (MANDATORY: return 0 -> no Error)
1688 *
1689 */
lsm6dsv16x_ois_xl_self_test_get(stmdev_ctx_t * ctx,lsm6dsv16x_ois_xl_self_test_t * val)1690 int32_t lsm6dsv16x_ois_xl_self_test_get(stmdev_ctx_t *ctx,
1691 lsm6dsv16x_ois_xl_self_test_t *val)
1692 {
1693 lsm6dsv16x_spi2_int_ois_t spi2_int_ois;
1694 int32_t ret;
1695
1696 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1);
1697 if (ret != 0) { return ret; }
1698
1699 switch (spi2_int_ois.st_xl_ois)
1700 {
1701 case LSM6DSV16X_OIS_XL_ST_DISABLE:
1702 *val = LSM6DSV16X_OIS_XL_ST_DISABLE;
1703 break;
1704
1705 case LSM6DSV16X_OIS_XL_ST_POSITIVE:
1706 *val = LSM6DSV16X_OIS_XL_ST_POSITIVE;
1707 break;
1708
1709 case LSM6DSV16X_OIS_XL_ST_NEGATIVE:
1710 *val = LSM6DSV16X_OIS_XL_ST_NEGATIVE;
1711 break;
1712
1713 default:
1714 *val = LSM6DSV16X_OIS_XL_ST_DISABLE;
1715 break;
1716 }
1717
1718 return ret;
1719 }
1720
1721 /**
1722 * @brief SPI2 Accelerometer self-test selection.[set]
1723 *
1724 * @param ctx read / write interface definitions
1725 * @param val GY_ST_DISABLE, GY_ST_POSITIVE, GY_ST_NEGATIVE, LSM6DSV16X_OIS_GY_ST_CLAMP_POS, LSM6DSV16X_OIS_GY_ST_CLAMP_NEG
1726 * @retval interface status (MANDATORY: return 0 -> no Error)
1727 *
1728 */
lsm6dsv16x_ois_gy_self_test_set(stmdev_ctx_t * ctx,lsm6dsv16x_ois_gy_self_test_t val)1729 int32_t lsm6dsv16x_ois_gy_self_test_set(stmdev_ctx_t *ctx,
1730 lsm6dsv16x_ois_gy_self_test_t val)
1731 {
1732 lsm6dsv16x_spi2_int_ois_t spi2_int_ois;
1733 int32_t ret;
1734
1735 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1);
1736
1737 if (ret == 0)
1738 {
1739 spi2_int_ois.st_g_ois = ((uint8_t)val & 0x3U);
1740 spi2_int_ois.st_ois_clampdis = ((uint8_t)val & 0x04U) >> 2;
1741 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1);
1742 }
1743
1744 return ret;
1745 }
1746
1747 /**
1748 * @brief SPI2 Accelerometer self-test selection.[get]
1749 *
1750 * @param ctx read / write interface definitions
1751 * @param val GY_ST_DISABLE, GY_ST_POSITIVE, GY_ST_NEGATIVE, LSM6DSV16X_OIS_GY_ST_CLAMP_POS, LSM6DSV16X_OIS_GY_ST_CLAMP_NEG
1752 * @retval interface status (MANDATORY: return 0 -> no Error)
1753 *
1754 */
lsm6dsv16x_ois_gy_self_test_get(stmdev_ctx_t * ctx,lsm6dsv16x_ois_gy_self_test_t * val)1755 int32_t lsm6dsv16x_ois_gy_self_test_get(stmdev_ctx_t *ctx,
1756 lsm6dsv16x_ois_gy_self_test_t *val)
1757 {
1758 lsm6dsv16x_spi2_int_ois_t spi2_int_ois;
1759 int32_t ret;
1760
1761 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1);
1762 if (ret != 0) { return ret; }
1763
1764 switch (spi2_int_ois.st_g_ois)
1765 {
1766 case LSM6DSV16X_OIS_GY_ST_DISABLE:
1767 *val = LSM6DSV16X_OIS_GY_ST_DISABLE;
1768 break;
1769
1770 case LSM6DSV16X_OIS_GY_ST_POSITIVE:
1771 *val = (spi2_int_ois.st_ois_clampdis == 1U) ? LSM6DSV16X_OIS_GY_ST_CLAMP_POS : LSM6DSV16X_OIS_GY_ST_POSITIVE;
1772 break;
1773
1774 case LSM6DSV16X_OIS_GY_ST_NEGATIVE:
1775 *val = (spi2_int_ois.st_ois_clampdis == 1U) ? LSM6DSV16X_OIS_GY_ST_CLAMP_NEG : LSM6DSV16X_OIS_GY_ST_NEGATIVE;
1776 break;
1777
1778 default:
1779 *val = LSM6DSV16X_OIS_GY_ST_DISABLE;
1780 break;
1781 }
1782
1783 return ret;
1784 }
1785
1786 /**
1787 * @defgroup interrupt_pins
1788 * @brief This section groups all the functions that manage
1789 * interrupt pins
1790 * @{
1791 *
1792 */
1793
1794 /**
1795 * @brief Select the signal that need to route on int1 pad[set]
1796 *
1797 * @param ctx Read / write interface definitions.(ptr)
1798 * @param val the signals to route on int1 pin.
1799 * @retval Interface status (MANDATORY: return 0 -> no Error).
1800 *
1801 */
lsm6dsv16x_pin_int1_route_set(stmdev_ctx_t * ctx,lsm6dsv16x_pin_int_route_t * val)1802 int32_t lsm6dsv16x_pin_int1_route_set(stmdev_ctx_t *ctx,
1803 lsm6dsv16x_pin_int_route_t *val)
1804 {
1805 lsm6dsv16x_int1_ctrl_t int1_ctrl;
1806 lsm6dsv16x_md1_cfg_t md1_cfg;
1807 int32_t ret;
1808
1809 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
1810 if (ret != 0) { return ret; }
1811
1812 int1_ctrl.int1_drdy_xl = val->drdy_xl;
1813 int1_ctrl.int1_drdy_g = val->drdy_g;
1814 int1_ctrl.int1_fifo_th = val->fifo_th;
1815 int1_ctrl.int1_fifo_ovr = val->fifo_ovr;
1816 int1_ctrl.int1_fifo_full = val->fifo_full;
1817 int1_ctrl.int1_cnt_bdr = val->cnt_bdr;
1818
1819 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
1820 if (ret != 0) { return ret; }
1821
1822 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MD1_CFG, (uint8_t *)&md1_cfg, 1);
1823 if (ret != 0) { return ret; }
1824
1825 md1_cfg.int1_shub = val->shub;
1826 md1_cfg.int1_emb_func = val->emb_func;
1827 md1_cfg.int1_6d = val->sixd;
1828 md1_cfg.int1_single_tap = val->single_tap;
1829 md1_cfg.int1_double_tap = val->double_tap;
1830 md1_cfg.int1_wu = val->wakeup;
1831 md1_cfg.int1_ff = val->freefall;
1832 md1_cfg.int1_sleep_change = val->sleep_change;
1833
1834 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_MD1_CFG, (uint8_t *)&md1_cfg, 1);
1835
1836 return ret;
1837 }
1838
1839 /**
1840 * @brief Select the signal that need to route on int1 pad.[get]
1841 *
1842 * @param ctx Read / write interface definitions.(ptr)
1843 * @param val the signals that are routed on int1 pin.(ptr)
1844 * @retval Interface status (MANDATORY: return 0 -> no Error).
1845 *
1846 */
lsm6dsv16x_pin_int1_route_get(stmdev_ctx_t * ctx,lsm6dsv16x_pin_int_route_t * val)1847 int32_t lsm6dsv16x_pin_int1_route_get(stmdev_ctx_t *ctx,
1848 lsm6dsv16x_pin_int_route_t *val)
1849 {
1850 lsm6dsv16x_int1_ctrl_t int1_ctrl;
1851 lsm6dsv16x_md1_cfg_t md1_cfg;
1852 int32_t ret;
1853
1854 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
1855 if (ret != 0) { return ret; }
1856
1857 val->drdy_xl = int1_ctrl.int1_drdy_xl;
1858 val->drdy_g = int1_ctrl.int1_drdy_g;
1859 val->fifo_th = int1_ctrl.int1_fifo_th;
1860 val->fifo_ovr = int1_ctrl.int1_fifo_ovr;
1861 val->fifo_full = int1_ctrl.int1_fifo_full;
1862 val->cnt_bdr = int1_ctrl.int1_cnt_bdr;
1863
1864 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MD1_CFG, (uint8_t *)&md1_cfg, 1);
1865 if (ret != 0) { return ret; }
1866
1867 val->shub = md1_cfg.int1_shub;
1868 val->emb_func = md1_cfg.int1_emb_func;
1869 val->sixd = md1_cfg.int1_6d;
1870 val->single_tap = md1_cfg.int1_single_tap;
1871 val->double_tap = md1_cfg.int1_double_tap;
1872 val->wakeup = md1_cfg.int1_wu;
1873 val->freefall = md1_cfg.int1_ff;
1874 val->sleep_change = md1_cfg.int1_sleep_change;
1875
1876 return ret;
1877 }
1878
1879 /**
1880 * @brief Select the signal that need to route on int2 pad[set]
1881 *
1882 * @param ctx Read / write interface definitions.(ptr)
1883 * @param val the signals to route on int1 pin.
1884 * @retval Interface status (MANDATORY: return 0 -> no Error).
1885 *
1886 */
lsm6dsv16x_pin_int2_route_set(stmdev_ctx_t * ctx,lsm6dsv16x_pin_int_route_t * val)1887 int32_t lsm6dsv16x_pin_int2_route_set(stmdev_ctx_t *ctx,
1888 lsm6dsv16x_pin_int_route_t *val)
1889 {
1890 lsm6dsv16x_int2_ctrl_t int2_ctrl;
1891 lsm6dsv16x_md2_cfg_t md2_cfg;
1892 int32_t ret;
1893
1894 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
1895 if (ret != 0) { return ret; }
1896
1897 int2_ctrl.int2_drdy_xl = val->drdy_xl;
1898 int2_ctrl.int2_drdy_g = val->drdy_g;
1899 int2_ctrl.int2_fifo_th = val->fifo_th;
1900 int2_ctrl.int2_fifo_ovr = val->fifo_ovr;
1901 int2_ctrl.int2_fifo_full = val->fifo_full;
1902 int2_ctrl.int2_cnt_bdr = val->cnt_bdr;
1903 int2_ctrl.int2_drdy_g_eis = val->drdy_g_eis;
1904 int2_ctrl.int2_emb_func_endop = val->emb_func_endop;
1905
1906 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
1907 if (ret != 0) { return ret; }
1908
1909 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MD2_CFG, (uint8_t *)&md2_cfg, 1);
1910 if (ret != 0) { return ret; }
1911
1912 md2_cfg.int2_timestamp = val->timestamp;
1913 md2_cfg.int2_emb_func = val->emb_func;
1914 md2_cfg.int2_6d = val->sixd;
1915 md2_cfg.int2_single_tap = val->single_tap;
1916 md2_cfg.int2_double_tap = val->double_tap;
1917 md2_cfg.int2_wu = val->wakeup;
1918 md2_cfg.int2_ff = val->freefall;
1919 md2_cfg.int2_sleep_change = val->sleep_change;
1920
1921 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_MD2_CFG, (uint8_t *)&md2_cfg, 1);
1922
1923 return ret;
1924 }
1925
1926 /**
1927 * @brief Select the signal that need to route on int2 pad.[get]
1928 *
1929 * @param ctx Read / write interface definitions.(ptr)
1930 * @param val the signals that are routed on int1 pin.(ptr)
1931 * @retval Interface status (MANDATORY: return 0 -> no Error).
1932 *
1933 */
lsm6dsv16x_pin_int2_route_get(stmdev_ctx_t * ctx,lsm6dsv16x_pin_int_route_t * val)1934 int32_t lsm6dsv16x_pin_int2_route_get(stmdev_ctx_t *ctx,
1935 lsm6dsv16x_pin_int_route_t *val)
1936 {
1937 lsm6dsv16x_int2_ctrl_t int2_ctrl;
1938 lsm6dsv16x_md2_cfg_t md2_cfg;
1939 int32_t ret;
1940
1941 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
1942 if (ret != 0) { return ret; }
1943
1944 val->drdy_xl = int2_ctrl.int2_drdy_xl;
1945 val->drdy_g = int2_ctrl.int2_drdy_g;
1946 val->fifo_th = int2_ctrl.int2_fifo_th;
1947 val->fifo_ovr = int2_ctrl.int2_fifo_ovr;
1948 val->fifo_full = int2_ctrl.int2_fifo_full;
1949 val->cnt_bdr = int2_ctrl.int2_cnt_bdr;
1950 val->drdy_g_eis = int2_ctrl.int2_drdy_g_eis;
1951 val->emb_func_endop = int2_ctrl.int2_emb_func_endop;
1952
1953 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MD2_CFG, (uint8_t *)&md2_cfg, 1);
1954 if (ret != 0) { return ret; }
1955
1956 val->timestamp = md2_cfg.int2_timestamp;
1957 val->emb_func = md2_cfg.int2_emb_func;
1958 val->sixd = md2_cfg.int2_6d;
1959 val->single_tap = md2_cfg.int2_single_tap;
1960 val->double_tap = md2_cfg.int2_double_tap;
1961 val->wakeup = md2_cfg.int2_wu;
1962 val->freefall = md2_cfg.int2_ff;
1963 val->sleep_change = md2_cfg.int2_sleep_change;
1964
1965 return ret;
1966 }
1967
1968 /**
1969 * @}
1970 *
1971 */
1972
1973 /**
1974 * @brief Get the status of all the interrupt sources.[get]
1975 *
1976 * @param ctx read / write interface definitions
1977 * @param val Get the status of all the interrupt sources.
1978 * @retval interface status (MANDATORY: return 0 -> no Error)
1979 *
1980 */
lsm6dsv16x_all_sources_get(stmdev_ctx_t * ctx,lsm6dsv16x_all_sources_t * val)1981 int32_t lsm6dsv16x_all_sources_get(stmdev_ctx_t *ctx,
1982 lsm6dsv16x_all_sources_t *val)
1983 {
1984 lsm6dsv16x_emb_func_status_mainpage_t emb_func_status_mainpage;
1985 lsm6dsv16x_emb_func_exec_status_t emb_func_exec_status;
1986 lsm6dsv16x_fsm_status_mainpage_t fsm_status_mainpage;
1987 lsm6dsv16x_mlc_status_mainpage_t mlc_status_mainpage;
1988 lsm6dsv16x_functions_enable_t functions_enable;
1989 lsm6dsv16x_emb_func_src_t emb_func_src;
1990 lsm6dsv16x_fifo_status2_t fifo_status2;
1991 lsm6dsv16x_all_int_src_t all_int_src;
1992 lsm6dsv16x_wake_up_src_t wake_up_src;
1993 lsm6dsv16x_status_reg_t status_reg;
1994 lsm6dsv16x_d6d_src_t d6d_src;
1995 lsm6dsv16x_tap_src_t tap_src;
1996 lsm6dsv16x_ui_status_reg_ois_t status_reg_ois;
1997 lsm6dsv16x_status_master_t status_shub;
1998 uint8_t buff[8];
1999 int32_t ret;
2000
2001 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
2002 functions_enable.dis_rst_lir_all_int = PROPERTY_ENABLE;
2003 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
2004 if (ret != 0) { return ret; }
2005
2006 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_STATUS1, (uint8_t *)&buff, 4);
2007 if (ret != 0) { return ret; }
2008
2009 bytecpy((uint8_t *)&fifo_status2, &buff[1]);
2010 bytecpy((uint8_t *)&all_int_src, &buff[2]);
2011 bytecpy((uint8_t *)&status_reg, &buff[3]);
2012
2013 val->fifo_ovr = fifo_status2.fifo_ovr_ia;
2014 val->fifo_bdr = fifo_status2.counter_bdr_ia;
2015 val->fifo_full = fifo_status2.fifo_full_ia;
2016 val->fifo_th = fifo_status2.fifo_wtm_ia;
2017
2018 val->free_fall = all_int_src.ff_ia;
2019 val->wake_up = all_int_src.wu_ia;
2020 val->six_d = all_int_src.d6d_ia;
2021
2022 val->drdy_xl = status_reg.xlda;
2023 val->drdy_gy = status_reg.gda;
2024 val->drdy_temp = status_reg.tda;
2025 val->drdy_ah_qvar = status_reg.ah_qvarda;
2026 val->drdy_eis = status_reg.gda_eis;
2027 val->drdy_ois = status_reg.ois_drdy;
2028 val->timestamp = status_reg.timestamp_endcount;
2029
2030 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
2031 functions_enable.dis_rst_lir_all_int = PROPERTY_DISABLE;
2032 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
2033 if (ret != 0) { return ret; }
2034
2035 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_STATUS_REG_OIS, (uint8_t *)&buff, 8);
2036 if (ret != 0) { return ret; }
2037
2038 bytecpy((uint8_t *)&status_reg_ois, &buff[0]);
2039 bytecpy((uint8_t *)&wake_up_src, &buff[1]);
2040 bytecpy((uint8_t *)&tap_src, &buff[2]);
2041 bytecpy((uint8_t *)&d6d_src, &buff[3]);
2042 bytecpy((uint8_t *)&emb_func_status_mainpage, &buff[5]);
2043 bytecpy((uint8_t *)&fsm_status_mainpage, &buff[6]);
2044 bytecpy((uint8_t *)&mlc_status_mainpage, &buff[7]);
2045
2046 val->gy_settling = status_reg_ois.gyro_settling;
2047 val->sleep_change = wake_up_src.sleep_change_ia;
2048 val->wake_up_x = wake_up_src.x_wu;
2049 val->wake_up_y = wake_up_src.y_wu;
2050 val->wake_up_z = wake_up_src.z_wu;
2051 val->sleep_state = wake_up_src.sleep_state;
2052
2053 val->tap_x = tap_src.x_tap;
2054 val->tap_y = tap_src.y_tap;
2055 val->tap_z = tap_src.z_tap;
2056 val->tap_sign = tap_src.tap_sign;
2057 val->double_tap = tap_src.double_tap;
2058 val->single_tap = tap_src.single_tap;
2059
2060 val->six_d_zl = d6d_src.zl;
2061 val->six_d_zh = d6d_src.zh;
2062 val->six_d_yl = d6d_src.yl;
2063 val->six_d_yh = d6d_src.yh;
2064 val->six_d_xl = d6d_src.xl;
2065 val->six_d_xh = d6d_src.xh;
2066
2067 val->step_detector = emb_func_status_mainpage.is_step_det;
2068 val->tilt = emb_func_status_mainpage.is_tilt;
2069 val->sig_mot = emb_func_status_mainpage.is_sigmot;
2070 val->fsm_lc = emb_func_status_mainpage.is_fsm_lc;
2071
2072 val->fsm1 = fsm_status_mainpage.is_fsm1;
2073 val->fsm2 = fsm_status_mainpage.is_fsm2;
2074 val->fsm3 = fsm_status_mainpage.is_fsm3;
2075 val->fsm4 = fsm_status_mainpage.is_fsm4;
2076 val->fsm5 = fsm_status_mainpage.is_fsm5;
2077 val->fsm6 = fsm_status_mainpage.is_fsm6;
2078 val->fsm7 = fsm_status_mainpage.is_fsm7;
2079 val->fsm8 = fsm_status_mainpage.is_fsm8;
2080
2081 val->mlc1 = mlc_status_mainpage.is_mlc1;
2082 val->mlc2 = mlc_status_mainpage.is_mlc2;
2083 val->mlc3 = mlc_status_mainpage.is_mlc3;
2084 val->mlc4 = mlc_status_mainpage.is_mlc4;
2085
2086
2087 /* embedded func */
2088 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
2089 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EXEC_STATUS, (uint8_t *)&emb_func_exec_status, 1);
2090 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1);
2091 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
2092 if (ret != 0) { return ret; }
2093
2094 val->emb_func_stand_by = emb_func_exec_status.emb_func_endop;
2095 val->emb_func_time_exceed = emb_func_exec_status.emb_func_exec_ovr;
2096 val->step_count_inc = emb_func_src.stepcounter_bit_set;
2097 val->step_count_overflow = emb_func_src.step_overflow;
2098 val->step_on_delta_time = emb_func_src.step_count_delta_ia;
2099
2100 val->step_detector = emb_func_src.step_detected;
2101
2102 /* sensor hub */
2103 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_STATUS_MASTER_MAINPAGE, (uint8_t *)&status_shub, 1);
2104 if (ret != 0) { return ret; }
2105
2106 val->sh_endop = status_shub.sens_hub_endop;
2107 val->sh_wr_once = status_shub.wr_once_done;
2108 val->sh_slave3_nack = status_shub.slave3_nack;
2109 val->sh_slave2_nack = status_shub.slave2_nack;
2110 val->sh_slave1_nack = status_shub.slave1_nack;
2111 val->sh_slave0_nack = status_shub.slave0_nack;
2112
2113 return ret;
2114 }
2115
lsm6dsv16x_flag_data_ready_get(stmdev_ctx_t * ctx,lsm6dsv16x_data_ready_t * val)2116 int32_t lsm6dsv16x_flag_data_ready_get(stmdev_ctx_t *ctx,
2117 lsm6dsv16x_data_ready_t *val)
2118 {
2119 lsm6dsv16x_status_reg_t status;
2120 int32_t ret;
2121
2122 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_STATUS_REG, (uint8_t *)&status, 1);
2123 if (ret != 0) { return ret; }
2124
2125 val->drdy_xl = status.xlda;
2126 val->drdy_gy = status.gda;
2127 val->drdy_temp = status.tda;
2128
2129 return ret;
2130 }
2131
2132 /**
2133 * @brief Mask status bit reset[set]
2134 *
2135 * @param ctx read / write interface definitions
2136 * @param val Mask to prevent status bit being reset
2137 * @retval interface status (MANDATORY: return 0 -> no Error)
2138 *
2139 */
lsm6dsv16x_int_ack_mask_set(stmdev_ctx_t * ctx,uint8_t val)2140 int32_t lsm6dsv16x_int_ack_mask_set(stmdev_ctx_t *ctx, uint8_t val)
2141 {
2142 int32_t ret;
2143
2144 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_INT_ACK_MASK, &val, 1);
2145
2146 return ret;
2147 }
2148
2149 /**
2150 * @brief Mask status bit reset[get]
2151 *
2152 * @param ctx read / write interface definitions
2153 * @param val Mask to prevent status bit being reset
2154 * @retval interface status (MANDATORY: return 0 -> no Error)
2155 *
2156 */
lsm6dsv16x_int_ack_mask_get(stmdev_ctx_t * ctx,uint8_t * val)2157 int32_t lsm6dsv16x_int_ack_mask_get(stmdev_ctx_t *ctx, uint8_t *val)
2158 {
2159 int32_t ret;
2160
2161 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INT_ACK_MASK, val, 1);
2162
2163 return ret;
2164 }
2165
2166 /**
2167 * @brief Temperature data output register[get]
2168 *
2169 * @param ctx read / write interface definitions
2170 * @param val Temperature data output register
2171 * @retval interface status (MANDATORY: return 0 -> no Error)
2172 *
2173 */
lsm6dsv16x_temperature_raw_get(stmdev_ctx_t * ctx,int16_t * val)2174 int32_t lsm6dsv16x_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
2175 {
2176 uint8_t buff[2];
2177 int32_t ret;
2178
2179 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_OUT_TEMP_L, &buff[0], 2);
2180 if (ret != 0) { return ret; }
2181
2182 *val = (int16_t)buff[1];
2183 *val = (*val * 256) + (int16_t)buff[0];
2184
2185 return ret;
2186 }
2187
2188 /**
2189 * @brief Angular rate sensor.[get]
2190 *
2191 * @param ctx read / write interface definitions
2192 * @param val Angular rate sensor.
2193 * @retval interface status (MANDATORY: return 0 -> no Error)
2194 *
2195 */
lsm6dsv16x_angular_rate_raw_get(stmdev_ctx_t * ctx,int16_t * val)2196 int32_t lsm6dsv16x_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val)
2197 {
2198 uint8_t buff[6];
2199 int32_t ret;
2200
2201 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_OUTX_L_G, &buff[0], 6);
2202 if (ret != 0) { return ret; }
2203
2204 val[0] = (int16_t)buff[1];
2205 val[0] = (val[0] * 256) + (int16_t)buff[0];
2206 val[1] = (int16_t)buff[3];
2207 val[1] = (val[1] * 256) + (int16_t)buff[2];
2208 val[2] = (int16_t)buff[5];
2209 val[2] = (val[2] * 256) + (int16_t)buff[4];
2210
2211 return ret;
2212 }
2213
2214 /**
2215 * @brief Angular rate sensor.[get]
2216 *
2217 * @param ctx read / write interface definitions
2218 * @param val OIS Angular rate sensor (thru SPI2).
2219 * @retval interface status (MANDATORY: return 0 -> no Error)
2220 *
2221 */
lsm6dsv16x_ois_angular_rate_raw_get(stmdev_ctx_t * ctx,int16_t * val)2222 int32_t lsm6dsv16x_ois_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val)
2223 {
2224 uint8_t buff[6];
2225 int32_t ret;
2226
2227 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SPI2_OUTX_L_G_OIS, &buff[0], 6);
2228 if (ret != 0) { return ret; }
2229
2230 val[0] = (int16_t)buff[1];
2231 val[0] = (*val * 256) + (int16_t)buff[0];
2232 val[1] = (int16_t)buff[3];
2233 val[1] = (*val * 256) + (int16_t)buff[2];
2234 val[2] = (int16_t)buff[5];
2235 val[2] = (*val * 256) + (int16_t)buff[4];
2236
2237 return ret;
2238 }
2239
2240 /**
2241 * @brief Angular rate sensor for OIS gyro or the EIS gyro channel.[get]
2242 *
2243 * @param ctx read / write interface definitions
2244 * @param val Angular rate sensor for OIS gyro or the EIS gyro channel.
2245 * @retval interface status (MANDATORY: return 0 -> no Error)
2246 *
2247 */
lsm6dsv16x_ois_eis_angular_rate_raw_get(stmdev_ctx_t * ctx,int16_t * val)2248 int32_t lsm6dsv16x_ois_eis_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val)
2249 {
2250 uint8_t buff[6];
2251 int32_t ret;
2252
2253 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_OUTX_L_G_OIS_EIS, &buff[0], 6);
2254 if (ret != 0) { return ret; }
2255
2256 val[0] = (int16_t)buff[1];
2257 val[0] = (*val * 256) + (int16_t)buff[0];
2258 val[1] = (int16_t)buff[3];
2259 val[1] = (*val * 256) + (int16_t)buff[2];
2260 val[2] = (int16_t)buff[5];
2261 val[2] = (*val * 256) + (int16_t)buff[4];
2262
2263 return ret;
2264 }
2265
2266 /**
2267 * @brief Linear acceleration sensor.[get]
2268 *
2269 * @param ctx read / write interface definitions
2270 * @param val Linear acceleration sensor.
2271 * @retval interface status (MANDATORY: return 0 -> no Error)
2272 *
2273 */
lsm6dsv16x_acceleration_raw_get(stmdev_ctx_t * ctx,int16_t * val)2274 int32_t lsm6dsv16x_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
2275 {
2276 uint8_t buff[6];
2277 int32_t ret;
2278
2279 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_OUTX_L_A, &buff[0], 6);
2280 if (ret != 0) { return ret; }
2281
2282 val[0] = (int16_t)buff[1];
2283 val[0] = (val[0] * 256) + (int16_t)buff[0];
2284 val[1] = (int16_t)buff[3];
2285 val[1] = (val[1] * 256) + (int16_t)buff[2];
2286 val[2] = (int16_t)buff[5];
2287 val[2] = (val[2] * 256) + (int16_t)buff[4];
2288
2289 return ret;
2290 }
2291
2292 /**
2293 * @brief Linear acceleration sensor for Dual channel mode.[get]
2294 *
2295 * @param ctx read / write interface definitions
2296 * @param val Linear acceleration sensor or Dual channel mode.
2297 * @retval interface status (MANDATORY: return 0 -> no Error)
2298 *
2299 */
lsm6dsv16x_dual_acceleration_raw_get(stmdev_ctx_t * ctx,int16_t * val)2300 int32_t lsm6dsv16x_dual_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
2301 {
2302 uint8_t buff[6];
2303 int32_t ret;
2304
2305 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_OUTX_L_A_OIS_DUALC, &buff[0], 6);
2306 if (ret != 0) { return ret; }
2307
2308 val[0] = (int16_t)buff[1];
2309 val[0] = (val[0] * 256) + (int16_t)buff[0];
2310 val[1] = (int16_t)buff[3];
2311 val[1] = (val[1] * 256) + (int16_t)buff[2];
2312 val[2] = (int16_t)buff[5];
2313 val[2] = (val[2] * 256) + (int16_t)buff[4];
2314
2315 return ret;
2316 }
2317
2318 /**
2319 * @brief ah_qvar data output register.[get]
2320 *
2321 * @param ctx read / write interface definitions
2322 * @param val ah_qvar data output register.
2323 * @retval interface status (MANDATORY: return 0 -> no Error)
2324 *
2325 */
lsm6dsv16x_ah_qvar_raw_get(stmdev_ctx_t * ctx,int16_t * val)2326 int32_t lsm6dsv16x_ah_qvar_raw_get(stmdev_ctx_t *ctx, int16_t *val)
2327 {
2328 uint8_t buff[2];
2329 int32_t ret;
2330
2331 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_AH_QVAR_OUT_L, &buff[0], 2);
2332 if (ret != 0) { return ret; }
2333
2334 *val = (int16_t)buff[1];
2335 *val = (*val * 256) + (int16_t)buff[0];
2336
2337 return ret;
2338 }
2339
2340 /**
2341 * @brief Difference in percentage of the effective ODR (and timestamp rate) with respect to the typical. Step: 0.13%. 8-bit format, 2's complement.[get]
2342 *
2343 * @param ctx read / write interface definitions
2344 * @param val Difference in percentage of the effective ODR (and timestamp rate) with respect to the typical. Step: 0.13%. 8-bit format, 2's complement.
2345 * @retval interface status (MANDATORY: return 0 -> no Error)
2346 *
2347 */
lsm6dsv16x_odr_cal_reg_get(stmdev_ctx_t * ctx,int8_t * val)2348 int32_t lsm6dsv16x_odr_cal_reg_get(stmdev_ctx_t *ctx, int8_t *val)
2349 {
2350 lsm6dsv16x_internal_freq_t internal_freq;
2351 int32_t ret;
2352
2353 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INTERNAL_FREQ, (uint8_t *)&internal_freq, 1);
2354 *val = (int8_t)internal_freq.freq_fine;
2355
2356 return ret;
2357 }
2358
2359 /**
2360 * @brief Write buffer in a page.[set]
2361 *
2362 * @param ctx read / write interface definitions
2363 * @param val Write buffer in a page.
2364 * @retval interface status (MANDATORY: return 0 -> no Error)
2365 *
2366 */
lsm6dsv16x_ln_pg_write(stmdev_ctx_t * ctx,uint16_t address,uint8_t * buf,uint8_t len)2367 int32_t lsm6dsv16x_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address,
2368 uint8_t *buf, uint8_t len)
2369 {
2370 lsm6dsv16x_page_address_t page_address;
2371 lsm6dsv16x_page_sel_t page_sel;
2372 lsm6dsv16x_page_rw_t page_rw;
2373 uint8_t msb;
2374 uint8_t lsb;
2375 int32_t ret;
2376 uint8_t i ;
2377
2378 msb = ((uint8_t)(address >> 8) & 0x0FU);
2379 lsb = (uint8_t)address & 0xFFU;
2380
2381 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
2382 if (ret != 0) { return ret; }
2383
2384 /* set page write */
2385 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PAGE_RW, (uint8_t *)&page_rw, 1);
2386 page_rw.page_read = PROPERTY_DISABLE;
2387 page_rw.page_write = PROPERTY_ENABLE;
2388 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_RW, (uint8_t *)&page_rw, 1);
2389 if (ret != 0) { goto exit; }
2390
2391 /* select page */
2392 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PAGE_SEL, (uint8_t *)&page_sel, 1);
2393 page_sel.page_sel = msb;
2394 page_sel.not_used0 = 1; // Default value
2395 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_SEL, (uint8_t *)&page_sel, 1);
2396 if (ret != 0) { goto exit; }
2397
2398 /* set page addr */
2399 page_address.page_addr = lsb;
2400 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_ADDRESS,
2401 (uint8_t *)&page_address, 1);
2402 if (ret != 0) { goto exit; }
2403
2404 for (i = 0; ((i < len) && (ret == 0)); i++)
2405 {
2406 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_VALUE, &buf[i], 1);
2407 if (ret != 0) { goto exit; }
2408
2409 lsb++;
2410
2411 /* Check if page wrap */
2412 if (((lsb & 0xFFU) == 0x00U) && (ret == 0))
2413 {
2414 msb++;
2415 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PAGE_SEL, (uint8_t *)&page_sel, 1);
2416 if (ret != 0) { goto exit; }
2417
2418 page_sel.page_sel = msb;
2419 page_sel.not_used0 = 1; // Default value
2420 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_SEL, (uint8_t *)&page_sel, 1);
2421 if (ret != 0) { goto exit; }
2422 }
2423 }
2424
2425 page_sel.page_sel = 0;
2426 page_sel.not_used0 = 1;// Default value
2427 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_SEL, (uint8_t *)&page_sel, 1);
2428 if (ret != 0) { goto exit; }
2429
2430 /* unset page write */
2431 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PAGE_RW, (uint8_t *)&page_rw, 1);
2432 page_rw.page_read = PROPERTY_DISABLE;
2433 page_rw.page_write = PROPERTY_DISABLE;
2434 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_RW, (uint8_t *)&page_rw, 1);
2435
2436 exit:
2437 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
2438
2439 return ret;
2440 }
2441
2442 /**
2443 * @defgroup Common
2444 * @brief This section groups common useful functions.
2445 * @{/
2446 *
2447 */
2448
2449 /**
2450 * @brief Read buffer in a page.[set]
2451 *
2452 * @param ctx read / write interface definitions
2453 * @param val Write buffer in a page.
2454 * @retval interface status (MANDATORY: return 0 -> no Error)
2455 *
2456 */
lsm6dsv16x_ln_pg_read(stmdev_ctx_t * ctx,uint16_t address,uint8_t * buf,uint8_t len)2457 int32_t lsm6dsv16x_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf,
2458 uint8_t len)
2459 {
2460 lsm6dsv16x_page_address_t page_address;
2461 lsm6dsv16x_page_sel_t page_sel;
2462 lsm6dsv16x_page_rw_t page_rw;
2463 uint8_t msb;
2464 uint8_t lsb;
2465 int32_t ret;
2466 uint8_t i ;
2467
2468 msb = ((uint8_t)(address >> 8) & 0x0FU);
2469 lsb = (uint8_t)address & 0xFFU;
2470
2471 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
2472 if (ret != 0) { return ret; }
2473
2474 /* set page write */
2475 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PAGE_RW, (uint8_t *)&page_rw, 1);
2476 page_rw.page_read = PROPERTY_ENABLE;
2477 page_rw.page_write = PROPERTY_DISABLE;
2478 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_RW, (uint8_t *)&page_rw, 1);
2479 if (ret != 0) { goto exit; }
2480
2481 /* select page */
2482 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PAGE_SEL, (uint8_t *)&page_sel, 1);
2483 page_sel.page_sel = msb;
2484 page_sel.not_used0 = 1; // Default value
2485 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_SEL, (uint8_t *)&page_sel, 1);
2486 if (ret != 0) { goto exit; }
2487
2488 /* set page addr */
2489 page_address.page_addr = lsb;
2490 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_ADDRESS,
2491 (uint8_t *)&page_address, 1);
2492 if (ret != 0) { goto exit; }
2493
2494 for (i = 0; ((i < len) && (ret == 0)); i++)
2495 {
2496 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PAGE_VALUE, &buf[i], 1);
2497 if (ret != 0) { goto exit; }
2498
2499 lsb++;
2500
2501 /* Check if page wrap */
2502 if (((lsb & 0xFFU) == 0x00U) && (ret == 0))
2503 {
2504 msb++;
2505 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PAGE_SEL, (uint8_t *)&page_sel, 1);
2506 if (ret != 0) { goto exit; }
2507
2508 page_sel.page_sel = msb;
2509 page_sel.not_used0 = 1; // Default value
2510 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_SEL, (uint8_t *)&page_sel, 1);
2511 if (ret != 0) { goto exit; }
2512 }
2513 }
2514
2515 page_sel.page_sel = 0;
2516 page_sel.not_used0 = 1;// Default value
2517 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_SEL, (uint8_t *)&page_sel, 1);
2518 if (ret != 0) { goto exit; }
2519
2520 /* unset page write */
2521 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PAGE_RW, (uint8_t *)&page_rw, 1);
2522 page_rw.page_read = PROPERTY_DISABLE;
2523 page_rw.page_write = PROPERTY_DISABLE;
2524 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_RW, (uint8_t *)&page_rw, 1);
2525
2526 exit:
2527 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
2528
2529 return ret;
2530 }
2531
2532 /**
2533 * @brief Enable debug mode for embedded functions [set]
2534 *
2535 * @param ctx read / write interface definitions
2536 * @param val 0, 1
2537 * @retval interface status (MANDATORY: return 0 -> no Error)
2538 *
2539 */
lsm6dsv16x_emb_function_dbg_set(stmdev_ctx_t * ctx,uint8_t val)2540 int32_t lsm6dsv16x_emb_function_dbg_set(stmdev_ctx_t *ctx, uint8_t val)
2541 {
2542 lsm6dsv16x_ctrl10_t ctrl10;
2543 int32_t ret;
2544
2545 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL10, (uint8_t *)&ctrl10, 1);
2546
2547 if (ret == 0)
2548 {
2549 ctrl10.emb_func_debug = val;
2550 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL10, (uint8_t *)&ctrl10, 1);
2551 }
2552
2553 return ret;
2554 }
2555
2556 /**
2557 * @brief Enable debug mode for embedded functions [get]
2558 *
2559 * @param ctx read / write interface definitions
2560 * @param val 0, 1
2561 * @retval interface status (MANDATORY: return 0 -> no Error)
2562 *
2563 */
lsm6dsv16x_emb_function_dbg_get(stmdev_ctx_t * ctx,uint8_t * val)2564 int32_t lsm6dsv16x_emb_function_dbg_get(stmdev_ctx_t *ctx, uint8_t *val)
2565 {
2566 lsm6dsv16x_ctrl10_t ctrl10;
2567 int32_t ret;
2568
2569 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL10, (uint8_t *)&ctrl10, 1);
2570 if (ret != 0) { return ret; }
2571
2572 *val = ctrl10.emb_func_debug;
2573
2574 return ret;
2575 }
2576
2577 /**
2578 * @}
2579 *
2580 */
2581
2582 /**
2583 * @defgroup Data ENable (DEN)
2584 * @brief This section groups all the functions concerning
2585 * DEN functionality.
2586 * @{
2587 *
2588 */
2589
2590 /**
2591 * @brief It changes the polarity of INT2 pin input trigger for data enable (DEN) or embedded functions.[set]
2592 *
2593 * @param ctx read / write interface definitions
2594 * @param val DEN_ACT_LOW, DEN_ACT_HIGH,
2595 * @retval interface status (MANDATORY: return 0 -> no Error)
2596 *
2597 */
lsm6dsv16x_den_polarity_set(stmdev_ctx_t * ctx,lsm6dsv16x_den_polarity_t val)2598 int32_t lsm6dsv16x_den_polarity_set(stmdev_ctx_t *ctx,
2599 lsm6dsv16x_den_polarity_t val)
2600 {
2601 lsm6dsv16x_ctrl4_t ctrl4;
2602 int32_t ret;
2603
2604 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL4, (uint8_t *)&ctrl4, 1);
2605
2606 if (ret == 0)
2607 {
2608 ctrl4.int2_in_lh = (uint8_t)val & 0x1U;
2609 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL4, (uint8_t *)&ctrl4, 1);
2610 }
2611
2612 return ret;
2613 }
2614
2615 /**
2616 * @brief It changes the polarity of INT2 pin input trigger for data enable (DEN) or embedded functions.[get]
2617 *
2618 * @param ctx read / write interface definitions
2619 * @param val DEN_ACT_LOW, DEN_ACT_HIGH,
2620 * @retval interface status (MANDATORY: return 0 -> no Error)
2621 *
2622 */
lsm6dsv16x_den_polarity_get(stmdev_ctx_t * ctx,lsm6dsv16x_den_polarity_t * val)2623 int32_t lsm6dsv16x_den_polarity_get(stmdev_ctx_t *ctx,
2624 lsm6dsv16x_den_polarity_t *val)
2625 {
2626 lsm6dsv16x_ctrl4_t ctrl4;
2627 int32_t ret;
2628
2629 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL4, (uint8_t *)&ctrl4, 1);
2630 if (ret != 0) { return ret; }
2631
2632 switch (ctrl4.int2_in_lh)
2633 {
2634 case LSM6DSV16X_DEN_ACT_LOW:
2635 *val = LSM6DSV16X_DEN_ACT_LOW;
2636 break;
2637
2638 case LSM6DSV16X_DEN_ACT_HIGH:
2639 *val = LSM6DSV16X_DEN_ACT_HIGH;
2640 break;
2641
2642 default:
2643 *val = LSM6DSV16X_DEN_ACT_LOW;
2644 break;
2645 }
2646
2647 return ret;
2648 }
2649
2650 /**
2651 * @brief Data ENable (DEN) configuration.[set]
2652 *
2653 * @param ctx read / write interface definitions
2654 * @param val Data ENable (DEN) configuration.
2655 * @retval interface status (MANDATORY: return 0 -> no Error)
2656 *
2657 */
lsm6dsv16x_den_conf_set(stmdev_ctx_t * ctx,lsm6dsv16x_den_conf_t val)2658 int32_t lsm6dsv16x_den_conf_set(stmdev_ctx_t *ctx, lsm6dsv16x_den_conf_t val)
2659 {
2660 lsm6dsv16x_den_t den;
2661 int32_t ret;
2662
2663 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_DEN, (uint8_t *)&den, 1);
2664 if (ret != 0) { return ret; }
2665
2666 den.den_z = val.den_z;
2667 den.den_y = val.den_y;
2668 den.den_x = val.den_x;
2669
2670 den.lvl2_en = (uint8_t)val.mode & 0x1U;
2671 den.lvl1_en = ((uint8_t)val.mode & 0x2U) >> 1;
2672
2673 if (val.stamp_in_gy_data == PROPERTY_ENABLE && val.stamp_in_xl_data == PROPERTY_ENABLE)
2674 {
2675 den.den_xl_g = PROPERTY_DISABLE;
2676 den.den_xl_en = PROPERTY_ENABLE;
2677 }
2678 else if (val.stamp_in_gy_data == PROPERTY_ENABLE && val.stamp_in_xl_data == PROPERTY_DISABLE)
2679 {
2680 den.den_xl_g = PROPERTY_DISABLE;
2681 den.den_xl_en = PROPERTY_DISABLE;
2682 }
2683 else if (val.stamp_in_gy_data == PROPERTY_DISABLE && val.stamp_in_xl_data == PROPERTY_ENABLE)
2684 {
2685 den.den_xl_g = PROPERTY_ENABLE;
2686 den.den_xl_en = PROPERTY_DISABLE;
2687 }
2688 else
2689 {
2690 den.den_xl_g = PROPERTY_DISABLE;
2691 den.den_xl_en = PROPERTY_DISABLE;
2692 den.den_z = PROPERTY_DISABLE;
2693 den.den_y = PROPERTY_DISABLE;
2694 den.den_x = PROPERTY_DISABLE;
2695 den.lvl2_en = PROPERTY_DISABLE;
2696 den.lvl1_en = PROPERTY_DISABLE;
2697 }
2698
2699 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_DEN, (uint8_t *)&den, 1);
2700
2701 return ret;
2702 }
2703
2704
2705 /**
2706 * @brief Data ENable (DEN) configuration.[get]
2707 *
2708 * @param ctx read / write interface definitions
2709 * @param val Data ENable (DEN) configuration.
2710 * @retval interface status (MANDATORY: return 0 -> no Error)
2711 *
2712 */
lsm6dsv16x_den_conf_get(stmdev_ctx_t * ctx,lsm6dsv16x_den_conf_t * val)2713 int32_t lsm6dsv16x_den_conf_get(stmdev_ctx_t *ctx, lsm6dsv16x_den_conf_t *val)
2714 {
2715 lsm6dsv16x_den_t den;
2716 int32_t ret;
2717
2718 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_DEN, (uint8_t *)&den, 1);
2719 if (ret != 0) { return ret; }
2720
2721 val->den_z = den.den_z;
2722 val->den_y = den.den_y;
2723 val->den_x = den.den_x;
2724
2725 if ((den.den_z | den.den_z | den.den_z) == PROPERTY_ENABLE)
2726 {
2727 if (den.den_xl_g == PROPERTY_DISABLE && den.den_xl_en == PROPERTY_ENABLE)
2728 {
2729 val->stamp_in_gy_data = PROPERTY_ENABLE;
2730 val->stamp_in_xl_data = PROPERTY_ENABLE;
2731 }
2732 else if (den.den_xl_g == PROPERTY_DISABLE && den.den_xl_en == PROPERTY_DISABLE)
2733 {
2734 val->stamp_in_gy_data = PROPERTY_ENABLE;
2735 val->stamp_in_xl_data = PROPERTY_DISABLE;
2736 }
2737 else // ( (den.den_xl_g & !den.den_xl_en) == PROPERTY_ENABLE )
2738 {
2739 val->stamp_in_gy_data = PROPERTY_DISABLE;
2740 val->stamp_in_xl_data = PROPERTY_ENABLE;
2741 }
2742 }
2743 else
2744 {
2745 val->stamp_in_gy_data = PROPERTY_DISABLE;
2746 val->stamp_in_xl_data = PROPERTY_DISABLE;
2747 }
2748
2749 switch ((den.lvl1_en << 1) + den.lvl2_en)
2750 {
2751 case LEVEL_TRIGGER:
2752 val->mode = LEVEL_TRIGGER;
2753 break;
2754
2755 case LEVEL_LATCHED:
2756 val->mode = LEVEL_LATCHED;
2757 break;
2758
2759 default:
2760 val->mode = DEN_NOT_DEFINED;
2761 break;
2762 }
2763
2764 return ret;
2765 }
2766
2767 /**
2768 * @}
2769 *
2770 */
2771
2772 /**
2773 * @defgroup Electronic Image Stabilization (EIS)
2774 * @brief Electronic Image Stabilization (EIS)
2775 * @{/
2776 *
2777 */
2778
2779 /**
2780 * @brief Gyroscope full-scale selection for EIS channel. WARNING: 4000dps will be available only if also User Interface chain is set to 4000dps[set]
2781 *
2782 * @param ctx read / write interface definitions
2783 * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps,
2784 * @retval interface status (MANDATORY: return 0 -> no Error)
2785 *
2786 */
lsm6dsv16x_eis_gy_full_scale_set(stmdev_ctx_t * ctx,lsm6dsv16x_eis_gy_full_scale_t val)2787 int32_t lsm6dsv16x_eis_gy_full_scale_set(stmdev_ctx_t *ctx,
2788 lsm6dsv16x_eis_gy_full_scale_t val)
2789 {
2790 lsm6dsv16x_ctrl_eis_t ctrl_eis;
2791 int32_t ret;
2792
2793 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
2794
2795 if (ret == 0)
2796 {
2797 ctrl_eis.fs_g_eis = (uint8_t)val & 0x7U;
2798 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
2799 }
2800
2801 return ret;
2802 }
2803
2804 /**
2805 * @brief Gyroscope full-scale selection for EIS channel. WARNING: 4000dps will be available only if also User Interface chain is set to 4000dps[get]
2806 *
2807 * @param ctx read / write interface definitions
2808 * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps
2809 * @retval interface status (MANDATORY: return 0 -> no Error)
2810 *
2811 */
lsm6dsv16x_eis_gy_full_scale_get(stmdev_ctx_t * ctx,lsm6dsv16x_eis_gy_full_scale_t * val)2812 int32_t lsm6dsv16x_eis_gy_full_scale_get(stmdev_ctx_t *ctx,
2813 lsm6dsv16x_eis_gy_full_scale_t *val)
2814 {
2815 lsm6dsv16x_ctrl_eis_t ctrl_eis;
2816 int32_t ret;
2817
2818 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
2819 if (ret != 0) { return ret; }
2820
2821 switch (ctrl_eis.fs_g_eis)
2822 {
2823 case LSM6DSV16X_EIS_125dps:
2824 *val = LSM6DSV16X_EIS_125dps;
2825 break;
2826
2827 case LSM6DSV16X_EIS_250dps:
2828 *val = LSM6DSV16X_EIS_250dps;
2829 break;
2830
2831 case LSM6DSV16X_EIS_500dps:
2832 *val = LSM6DSV16X_EIS_500dps;
2833 break;
2834
2835 case LSM6DSV16X_EIS_1000dps:
2836 *val = LSM6DSV16X_EIS_1000dps;
2837 break;
2838
2839 case LSM6DSV16X_EIS_2000dps:
2840 *val = LSM6DSV16X_EIS_2000dps;
2841 break;
2842
2843 default:
2844 *val = LSM6DSV16X_EIS_125dps;
2845 break;
2846 }
2847 return ret;
2848 }
2849
2850 /**
2851 * @brief Enables routing of gyroscope EIS outputs on SPI2 (OIS interface). The gyroscope data on SPI2 (OIS interface) cannot be read from User Interface (UI).[set]
2852 *
2853 * @param ctx read / write interface definitions
2854 * @param val Enables routing of gyroscope EIS outputs on SPI2 (OIS interface). The gyroscope data on SPI2 (OIS interface) cannot be read from User Interface (UI).
2855 * @retval interface status (MANDATORY: return 0 -> no Error)
2856 *
2857 */
lsm6dsv16x_eis_gy_on_spi2_set(stmdev_ctx_t * ctx,uint8_t val)2858 int32_t lsm6dsv16x_eis_gy_on_spi2_set(stmdev_ctx_t *ctx, uint8_t val)
2859 {
2860 lsm6dsv16x_ctrl_eis_t ctrl_eis;
2861 int32_t ret;
2862
2863 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
2864
2865 if (ret == 0)
2866 {
2867 ctrl_eis.g_eis_on_g_ois_out_reg = val;
2868 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
2869 }
2870
2871 return ret;
2872 }
2873
2874 /**
2875 * @brief Enables routing of gyroscope EIS outputs on SPI2 (OIS interface). The gyroscope data on SPI2 (OIS interface) cannot be read from User Interface (UI).[get]
2876 *
2877 * @param ctx read / write interface definitions
2878 * @param val Enables routing of gyroscope EIS outputs on SPI2 (OIS interface). The gyroscope data on SPI2 (OIS interface) cannot be read from User Interface (UI).
2879 * @retval interface status (MANDATORY: return 0 -> no Error)
2880 *
2881 */
lsm6dsv16x_eis_gy_on_spi2_get(stmdev_ctx_t * ctx,uint8_t * val)2882 int32_t lsm6dsv16x_eis_gy_on_spi2_get(stmdev_ctx_t *ctx, uint8_t *val)
2883 {
2884 lsm6dsv16x_ctrl_eis_t ctrl_eis;
2885 int32_t ret;
2886
2887 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
2888 *val = ctrl_eis.g_eis_on_g_ois_out_reg;
2889
2890 return ret;
2891 }
2892
2893 /**
2894 * @brief Enables and selects the ODR of the gyroscope EIS channel.[set]
2895 *
2896 * @param ctx read / write interface definitions
2897 * @param val EIS_1920Hz, EIS_960Hz,
2898 * @retval interface status (MANDATORY: return 0 -> no Error)
2899 *
2900 */
lsm6dsv16x_gy_eis_data_rate_set(stmdev_ctx_t * ctx,lsm6dsv16x_gy_eis_data_rate_t val)2901 int32_t lsm6dsv16x_gy_eis_data_rate_set(stmdev_ctx_t *ctx,
2902 lsm6dsv16x_gy_eis_data_rate_t val)
2903 {
2904 lsm6dsv16x_ctrl_eis_t ctrl_eis;
2905 int32_t ret;
2906
2907 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
2908
2909 if (ret == 0)
2910 {
2911 ctrl_eis.odr_g_eis = (uint8_t)val & 0x03U;
2912 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
2913 }
2914
2915 return ret;
2916 }
2917
2918 /**
2919 * @brief Enables and selects the ODR of the gyroscope EIS channel.[get]
2920 *
2921 * @param ctx read / write interface definitions
2922 * @param val EIS_1920Hz, EIS_960Hz,
2923 * @retval interface status (MANDATORY: return 0 -> no Error)
2924 *
2925 */
lsm6dsv16x_gy_eis_data_rate_get(stmdev_ctx_t * ctx,lsm6dsv16x_gy_eis_data_rate_t * val)2926 int32_t lsm6dsv16x_gy_eis_data_rate_get(stmdev_ctx_t *ctx,
2927 lsm6dsv16x_gy_eis_data_rate_t *val)
2928 {
2929 lsm6dsv16x_ctrl_eis_t ctrl_eis;
2930 int32_t ret;
2931
2932 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
2933 if (ret != 0) { return ret; }
2934
2935 switch (ctrl_eis.odr_g_eis)
2936 {
2937 case LSM6DSV16X_EIS_ODR_OFF:
2938 *val = LSM6DSV16X_EIS_ODR_OFF;
2939 break;
2940
2941 case LSM6DSV16X_EIS_1920Hz:
2942 *val = LSM6DSV16X_EIS_1920Hz;
2943 break;
2944
2945 case LSM6DSV16X_EIS_960Hz:
2946 *val = LSM6DSV16X_EIS_960Hz;
2947 break;
2948
2949 default:
2950 *val = LSM6DSV16X_EIS_1920Hz;
2951 break;
2952 }
2953
2954 return ret;
2955 }
2956
2957 /**
2958 * @}
2959 *
2960 */
2961
2962 /**
2963 * @defgroup FIFO
2964 * @brief This section group all the functions concerning the FIFO usage
2965 * @{
2966 *
2967 */
2968
2969 /**
2970 * @brief FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).[set]
2971 *
2972 * @param ctx read / write interface definitions
2973 * @param val FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).
2974 * @retval interface status (MANDATORY: return 0 -> no Error)
2975 *
2976 */
lsm6dsv16x_fifo_watermark_set(stmdev_ctx_t * ctx,uint8_t val)2977 int32_t lsm6dsv16x_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val)
2978 {
2979 lsm6dsv16x_fifo_ctrl1_t fifo_ctrl1;
2980 int32_t ret;
2981
2982 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1);
2983
2984 if (ret == 0)
2985 {
2986 fifo_ctrl1.wtm = val;
2987 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1);
2988 }
2989
2990 return ret;
2991 }
2992
2993 /**
2994 * @brief FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).[get]
2995 *
2996 * @param ctx read / write interface definitions
2997 * @param val FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).
2998 * @retval interface status (MANDATORY: return 0 -> no Error)
2999 *
3000 */
lsm6dsv16x_fifo_watermark_get(stmdev_ctx_t * ctx,uint8_t * val)3001 int32_t lsm6dsv16x_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
3002 {
3003 lsm6dsv16x_fifo_ctrl1_t fifo_ctrl1;
3004 int32_t ret;
3005
3006 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1);
3007 *val = fifo_ctrl1.wtm;
3008
3009 return ret;
3010 }
3011
3012 /**
3013 * @brief When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.[set]
3014 *
3015 * @param ctx read / write interface definitions
3016 * @param val When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.
3017 * @retval interface status (MANDATORY: return 0 -> no Error)
3018 *
3019 */
lsm6dsv16x_fifo_xl_dual_fsm_batch_set(stmdev_ctx_t * ctx,uint8_t val)3020 int32_t lsm6dsv16x_fifo_xl_dual_fsm_batch_set(stmdev_ctx_t *ctx, uint8_t val)
3021 {
3022 lsm6dsv16x_fifo_ctrl2_t fifo_ctrl2;
3023 int32_t ret;
3024
3025 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3026 if (ret == 0)
3027 {
3028 fifo_ctrl2.xl_dualc_batch_from_fsm = val;
3029 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3030 }
3031
3032 return ret;
3033 }
3034
3035 /**
3036 * @brief When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.[get]
3037 *
3038 * @param ctx read / write interface definitions
3039 * @param val When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.
3040 * @retval interface status (MANDATORY: return 0 -> no Error)
3041 *
3042 */
lsm6dsv16x_fifo_xl_dual_fsm_batch_get(stmdev_ctx_t * ctx,uint8_t * val)3043 int32_t lsm6dsv16x_fifo_xl_dual_fsm_batch_get(stmdev_ctx_t *ctx, uint8_t *val)
3044 {
3045 lsm6dsv16x_fifo_ctrl2_t fifo_ctrl2;
3046 int32_t ret;
3047
3048 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3049 *val = fifo_ctrl2.xl_dualc_batch_from_fsm;
3050
3051 return ret;
3052 }
3053
3054 /**
3055 * @brief It configures the compression algorithm to write non-compressed data at each rate.[set]
3056 *
3057 * @param ctx read / write interface definitions
3058 * @param val CMP_DISABLE, CMP_ALWAYS, CMP_8_TO_1, CMP_16_TO_1, CMP_32_TO_1,
3059 * @retval interface status (MANDATORY: return 0 -> no Error)
3060 *
3061 */
lsm6dsv16x_fifo_compress_algo_set(stmdev_ctx_t * ctx,lsm6dsv16x_fifo_compress_algo_t val)3062 int32_t lsm6dsv16x_fifo_compress_algo_set(stmdev_ctx_t *ctx,
3063 lsm6dsv16x_fifo_compress_algo_t val)
3064 {
3065 lsm6dsv16x_fifo_ctrl2_t fifo_ctrl2;
3066 int32_t ret;
3067
3068 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3069 if (ret == 0)
3070 {
3071 fifo_ctrl2.uncompr_rate = (uint8_t)val & 0x03U;
3072 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3073 }
3074
3075 return ret;
3076 }
3077
3078 /**
3079 * @brief It configures the compression algorithm to write non-compressed data at each rate.[get]
3080 *
3081 * @param ctx read / write interface definitions
3082 * @param val CMP_DISABLE, CMP_ALWAYS, CMP_8_TO_1, CMP_16_TO_1, CMP_32_TO_1,
3083 * @retval interface status (MANDATORY: return 0 -> no Error)
3084 *
3085 */
lsm6dsv16x_fifo_compress_algo_get(stmdev_ctx_t * ctx,lsm6dsv16x_fifo_compress_algo_t * val)3086 int32_t lsm6dsv16x_fifo_compress_algo_get(stmdev_ctx_t *ctx,
3087 lsm6dsv16x_fifo_compress_algo_t *val)
3088 {
3089 lsm6dsv16x_fifo_ctrl2_t fifo_ctrl2;
3090 int32_t ret;
3091
3092 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3093 if (ret != 0) { return ret; }
3094
3095 switch (fifo_ctrl2.uncompr_rate)
3096 {
3097 case LSM6DSV16X_CMP_DISABLE:
3098 *val = LSM6DSV16X_CMP_DISABLE;
3099 break;
3100
3101 case LSM6DSV16X_CMP_8_TO_1:
3102 *val = LSM6DSV16X_CMP_8_TO_1;
3103 break;
3104
3105 case LSM6DSV16X_CMP_16_TO_1:
3106 *val = LSM6DSV16X_CMP_16_TO_1;
3107 break;
3108
3109 case LSM6DSV16X_CMP_32_TO_1:
3110 *val = LSM6DSV16X_CMP_32_TO_1;
3111 break;
3112
3113 default:
3114 *val = LSM6DSV16X_CMP_DISABLE;
3115 break;
3116 }
3117 return ret;
3118 }
3119
3120 /**
3121 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set]
3122 *
3123 * @param ctx read / write interface definitions
3124 * @param val Enables ODR CHANGE virtual sensor to be batched in FIFO.
3125 * @retval interface status (MANDATORY: return 0 -> no Error)
3126 *
3127 */
lsm6dsv16x_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t * ctx,uint8_t val)3128 int32_t lsm6dsv16x_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, uint8_t val)
3129 {
3130 lsm6dsv16x_fifo_ctrl2_t fifo_ctrl2;
3131 int32_t ret;
3132
3133 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3134 if (ret == 0)
3135 {
3136 fifo_ctrl2.odr_chg_en = val;
3137 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3138 }
3139
3140 return ret;
3141 }
3142
3143 /**
3144 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get]
3145 *
3146 * @param ctx read / write interface definitions
3147 * @param val Enables ODR CHANGE virtual sensor to be batched in FIFO.
3148 * @retval interface status (MANDATORY: return 0 -> no Error)
3149 *
3150 */
lsm6dsv16x_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t * ctx,uint8_t * val)3151 int32_t lsm6dsv16x_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx,
3152 uint8_t *val)
3153 {
3154 lsm6dsv16x_fifo_ctrl2_t fifo_ctrl2;
3155 int32_t ret;
3156
3157 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3158 *val = fifo_ctrl2.odr_chg_en;
3159
3160 return ret;
3161 }
3162
3163 /**
3164 * @brief Enables/Disables compression algorithm runtime.[set]
3165 *
3166 * @param ctx read / write interface definitions
3167 * @param val Enables/Disables compression algorithm runtime.
3168 * @retval interface status (MANDATORY: return 0 -> no Error)
3169 *
3170 */
lsm6dsv16x_fifo_compress_algo_real_time_set(stmdev_ctx_t * ctx,uint8_t val)3171 int32_t lsm6dsv16x_fifo_compress_algo_real_time_set(stmdev_ctx_t *ctx,
3172 uint8_t val)
3173 {
3174 lsm6dsv16x_emb_func_en_b_t emb_func_en_b;
3175 lsm6dsv16x_fifo_ctrl2_t fifo_ctrl2;
3176
3177 int32_t ret;
3178
3179 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3180 fifo_ctrl2.fifo_compr_rt_en = val;
3181 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3182 if (ret != 0) { return ret; }
3183
3184 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
3185 if (ret != 0) { return ret; }
3186
3187 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
3188 emb_func_en_b.fifo_compr_en = val;
3189 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
3190 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
3191
3192 return ret;
3193 }
3194
3195 /**
3196 * @brief Enables/Disables compression algorithm runtime.[get]
3197 *
3198 * @param ctx read / write interface definitions
3199 * @param val Enables/Disables compression algorithm runtime.
3200 * @retval interface status (MANDATORY: return 0 -> no Error)
3201 *
3202 */
lsm6dsv16x_fifo_compress_algo_real_time_get(stmdev_ctx_t * ctx,uint8_t * val)3203 int32_t lsm6dsv16x_fifo_compress_algo_real_time_get(stmdev_ctx_t *ctx,
3204 uint8_t *val)
3205 {
3206 lsm6dsv16x_fifo_ctrl2_t fifo_ctrl2;
3207 int32_t ret;
3208
3209 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3210
3211 *val = fifo_ctrl2.fifo_compr_rt_en;
3212
3213 return ret;
3214 }
3215
3216 /**
3217 * @brief Sensing chain FIFO stop values memorization at threshold level.[set]
3218 *
3219 * @param ctx read / write interface definitions
3220 * @param val Sensing chain FIFO stop values memorization at threshold level.
3221 * @retval interface status (MANDATORY: return 0 -> no Error)
3222 *
3223 */
lsm6dsv16x_fifo_stop_on_wtm_set(stmdev_ctx_t * ctx,uint8_t val)3224 int32_t lsm6dsv16x_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val)
3225 {
3226 lsm6dsv16x_fifo_ctrl2_t fifo_ctrl2;
3227 int32_t ret;
3228
3229 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3230 if (ret == 0)
3231 {
3232 fifo_ctrl2.stop_on_wtm = val;
3233 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3234 }
3235
3236 return ret;
3237 }
3238
3239 /**
3240 * @brief Sensing chain FIFO stop values memorization at threshold level.[get]
3241 *
3242 * @param ctx read / write interface definitions
3243 * @param val Sensing chain FIFO stop values memorization at threshold level.
3244 * @retval interface status (MANDATORY: return 0 -> no Error)
3245 *
3246 */
lsm6dsv16x_fifo_stop_on_wtm_get(stmdev_ctx_t * ctx,uint8_t * val)3247 int32_t lsm6dsv16x_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val)
3248 {
3249 lsm6dsv16x_fifo_ctrl2_t fifo_ctrl2;
3250 int32_t ret;
3251
3252 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3253 *val = fifo_ctrl2.stop_on_wtm;
3254
3255 return ret;
3256 }
3257
3258 /**
3259 * @brief Selects Batch Data Rate (write frequency in FIFO) for accelerometer data.[set]
3260 *
3261 * @param ctx read / write interface definitions
3262 * @param val XL_NOT_BATCHED, XL_BATCHED_AT_1Hz875, XL_BATCHED_AT_7Hz5, XL_BATCHED_AT_15Hz, XL_BATCHED_AT_30Hz, XL_BATCHED_AT_60Hz, XL_BATCHED_AT_120Hz, XL_BATCHED_AT_240Hz, XL_BATCHED_AT_480Hz, XL_BATCHED_AT_960Hz, XL_BATCHED_AT_1920Hz, XL_BATCHED_AT_3840Hz, XL_BATCHED_AT_7680Hz,
3263 * @retval interface status (MANDATORY: return 0 -> no Error)
3264 *
3265 */
lsm6dsv16x_fifo_xl_batch_set(stmdev_ctx_t * ctx,lsm6dsv16x_fifo_xl_batch_t val)3266 int32_t lsm6dsv16x_fifo_xl_batch_set(stmdev_ctx_t *ctx,
3267 lsm6dsv16x_fifo_xl_batch_t val)
3268 {
3269 lsm6dsv16x_fifo_ctrl3_t fifo_ctrl3;
3270 int32_t ret;
3271
3272 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
3273 if (ret == 0)
3274 {
3275 fifo_ctrl3.bdr_xl = (uint8_t)val & 0xFu;
3276 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
3277 }
3278
3279 return ret;
3280 }
3281
3282 /**
3283 * @brief Selects Batch Data Rate (write frequency in FIFO) for accelerometer data.[get]
3284 *
3285 * @param ctx read / write interface definitions
3286 * @param val XL_NOT_BATCHED, XL_BATCHED_AT_1Hz875, XL_BATCHED_AT_7Hz5, XL_BATCHED_AT_15Hz, XL_BATCHED_AT_30Hz, XL_BATCHED_AT_60Hz, XL_BATCHED_AT_120Hz, XL_BATCHED_AT_240Hz, XL_BATCHED_AT_480Hz, XL_BATCHED_AT_960Hz, XL_BATCHED_AT_1920Hz, XL_BATCHED_AT_3840Hz, XL_BATCHED_AT_7680Hz,
3287 * @retval interface status (MANDATORY: return 0 -> no Error)
3288 *
3289 */
lsm6dsv16x_fifo_xl_batch_get(stmdev_ctx_t * ctx,lsm6dsv16x_fifo_xl_batch_t * val)3290 int32_t lsm6dsv16x_fifo_xl_batch_get(stmdev_ctx_t *ctx,
3291 lsm6dsv16x_fifo_xl_batch_t *val)
3292 {
3293 lsm6dsv16x_fifo_ctrl3_t fifo_ctrl3;
3294 int32_t ret;
3295
3296 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
3297 if (ret != 0) { return ret; }
3298
3299 switch (fifo_ctrl3.bdr_xl)
3300 {
3301 case LSM6DSV16X_XL_NOT_BATCHED:
3302 *val = LSM6DSV16X_XL_NOT_BATCHED;
3303 break;
3304
3305 case LSM6DSV16X_XL_BATCHED_AT_1Hz875:
3306 *val = LSM6DSV16X_XL_BATCHED_AT_1Hz875;
3307 break;
3308
3309 case LSM6DSV16X_XL_BATCHED_AT_7Hz5:
3310 *val = LSM6DSV16X_XL_BATCHED_AT_7Hz5;
3311 break;
3312
3313 case LSM6DSV16X_XL_BATCHED_AT_15Hz:
3314 *val = LSM6DSV16X_XL_BATCHED_AT_15Hz;
3315 break;
3316
3317 case LSM6DSV16X_XL_BATCHED_AT_30Hz:
3318 *val = LSM6DSV16X_XL_BATCHED_AT_30Hz;
3319 break;
3320
3321 case LSM6DSV16X_XL_BATCHED_AT_60Hz:
3322 *val = LSM6DSV16X_XL_BATCHED_AT_60Hz;
3323 break;
3324
3325 case LSM6DSV16X_XL_BATCHED_AT_120Hz:
3326 *val = LSM6DSV16X_XL_BATCHED_AT_120Hz;
3327 break;
3328
3329 case LSM6DSV16X_XL_BATCHED_AT_240Hz:
3330 *val = LSM6DSV16X_XL_BATCHED_AT_240Hz;
3331 break;
3332
3333 case LSM6DSV16X_XL_BATCHED_AT_480Hz:
3334 *val = LSM6DSV16X_XL_BATCHED_AT_480Hz;
3335 break;
3336
3337 case LSM6DSV16X_XL_BATCHED_AT_960Hz:
3338 *val = LSM6DSV16X_XL_BATCHED_AT_960Hz;
3339 break;
3340
3341 case LSM6DSV16X_XL_BATCHED_AT_1920Hz:
3342 *val = LSM6DSV16X_XL_BATCHED_AT_1920Hz;
3343 break;
3344
3345 case LSM6DSV16X_XL_BATCHED_AT_3840Hz:
3346 *val = LSM6DSV16X_XL_BATCHED_AT_3840Hz;
3347 break;
3348
3349 case LSM6DSV16X_XL_BATCHED_AT_7680Hz:
3350 *val = LSM6DSV16X_XL_BATCHED_AT_7680Hz;
3351 break;
3352
3353 default:
3354 *val = LSM6DSV16X_XL_NOT_BATCHED;
3355 break;
3356 }
3357
3358 return ret;
3359 }
3360
3361 /**
3362 * @brief Selects Batch Data Rate (write frequency in FIFO) for gyroscope data.[set]
3363 *
3364 * @param ctx read / write interface definitions
3365 * @param val GY_NOT_BATCHED, GY_BATCHED_AT_1Hz875, GY_BATCHED_AT_7Hz5, GY_BATCHED_AT_15Hz, GY_BATCHED_AT_30Hz, GY_BATCHED_AT_60Hz, GY_BATCHED_AT_120Hz, GY_BATCHED_AT_240Hz, GY_BATCHED_AT_480Hz, GY_BATCHED_AT_960Hz, GY_BATCHED_AT_1920Hz, GY_BATCHED_AT_3840Hz, GY_BATCHED_AT_7680Hz,
3366 * @retval interface status (MANDATORY: return 0 -> no Error)
3367 *
3368 */
lsm6dsv16x_fifo_gy_batch_set(stmdev_ctx_t * ctx,lsm6dsv16x_fifo_gy_batch_t val)3369 int32_t lsm6dsv16x_fifo_gy_batch_set(stmdev_ctx_t *ctx,
3370 lsm6dsv16x_fifo_gy_batch_t val)
3371 {
3372 lsm6dsv16x_fifo_ctrl3_t fifo_ctrl3;
3373 int32_t ret;
3374
3375 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
3376 if (ret == 0)
3377 {
3378 fifo_ctrl3.bdr_gy = (uint8_t)val & 0x0Fu;
3379 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
3380 }
3381
3382 return ret;
3383 }
3384
3385 /**
3386 * @brief Selects Batch Data Rate (write frequency in FIFO) for gyroscope data.[get]
3387 *
3388 * @param ctx read / write interface definitions
3389 * @param val GY_NOT_BATCHED, GY_BATCHED_AT_1Hz875, GY_BATCHED_AT_7Hz5, GY_BATCHED_AT_15Hz, GY_BATCHED_AT_30Hz, GY_BATCHED_AT_60Hz, GY_BATCHED_AT_120Hz, GY_BATCHED_AT_240Hz, GY_BATCHED_AT_480Hz, GY_BATCHED_AT_960Hz, GY_BATCHED_AT_1920Hz, GY_BATCHED_AT_3840Hz, GY_BATCHED_AT_7680Hz,
3390 * @retval interface status (MANDATORY: return 0 -> no Error)
3391 *
3392 */
lsm6dsv16x_fifo_gy_batch_get(stmdev_ctx_t * ctx,lsm6dsv16x_fifo_gy_batch_t * val)3393 int32_t lsm6dsv16x_fifo_gy_batch_get(stmdev_ctx_t *ctx,
3394 lsm6dsv16x_fifo_gy_batch_t *val)
3395 {
3396 lsm6dsv16x_fifo_ctrl3_t fifo_ctrl3;
3397 int32_t ret;
3398
3399 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
3400 if (ret != 0) { return ret; }
3401
3402 switch (fifo_ctrl3.bdr_gy)
3403 {
3404 case LSM6DSV16X_GY_NOT_BATCHED:
3405 *val = LSM6DSV16X_GY_NOT_BATCHED;
3406 break;
3407
3408 case LSM6DSV16X_GY_BATCHED_AT_1Hz875:
3409 *val = LSM6DSV16X_GY_BATCHED_AT_1Hz875;
3410 break;
3411
3412 case LSM6DSV16X_GY_BATCHED_AT_7Hz5:
3413 *val = LSM6DSV16X_GY_BATCHED_AT_7Hz5;
3414 break;
3415
3416 case LSM6DSV16X_GY_BATCHED_AT_15Hz:
3417 *val = LSM6DSV16X_GY_BATCHED_AT_15Hz;
3418 break;
3419
3420 case LSM6DSV16X_GY_BATCHED_AT_30Hz:
3421 *val = LSM6DSV16X_GY_BATCHED_AT_30Hz;
3422 break;
3423
3424 case LSM6DSV16X_GY_BATCHED_AT_60Hz:
3425 *val = LSM6DSV16X_GY_BATCHED_AT_60Hz;
3426 break;
3427
3428 case LSM6DSV16X_GY_BATCHED_AT_120Hz:
3429 *val = LSM6DSV16X_GY_BATCHED_AT_120Hz;
3430 break;
3431
3432 case LSM6DSV16X_GY_BATCHED_AT_240Hz:
3433 *val = LSM6DSV16X_GY_BATCHED_AT_240Hz;
3434 break;
3435
3436 case LSM6DSV16X_GY_BATCHED_AT_480Hz:
3437 *val = LSM6DSV16X_GY_BATCHED_AT_480Hz;
3438 break;
3439
3440 case LSM6DSV16X_GY_BATCHED_AT_960Hz:
3441 *val = LSM6DSV16X_GY_BATCHED_AT_960Hz;
3442 break;
3443
3444 case LSM6DSV16X_GY_BATCHED_AT_1920Hz:
3445 *val = LSM6DSV16X_GY_BATCHED_AT_1920Hz;
3446 break;
3447
3448 case LSM6DSV16X_GY_BATCHED_AT_3840Hz:
3449 *val = LSM6DSV16X_GY_BATCHED_AT_3840Hz;
3450 break;
3451
3452 case LSM6DSV16X_GY_BATCHED_AT_7680Hz:
3453 *val = LSM6DSV16X_GY_BATCHED_AT_7680Hz;
3454 break;
3455
3456 default:
3457 *val = LSM6DSV16X_GY_NOT_BATCHED;
3458 break;
3459 }
3460 return ret;
3461 }
3462
3463
3464 /**
3465 * @brief FIFO mode selection.[set]
3466 *
3467 * @param ctx read / write interface definitions
3468 * @param val BYPASS_MODE, FIFO_MODE, STREAM_WTM_TO_FULL_MODE, STREAM_TO_FIFO_MODE, BYPASS_TO_STREAM_MODE, STREAM_MODE, BYPASS_TO_FIFO_MODE,
3469 * @retval interface status (MANDATORY: return 0 -> no Error)
3470 *
3471 */
lsm6dsv16x_fifo_mode_set(stmdev_ctx_t * ctx,lsm6dsv16x_fifo_mode_t val)3472 int32_t lsm6dsv16x_fifo_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_fifo_mode_t val)
3473 {
3474 lsm6dsv16x_fifo_ctrl4_t fifo_ctrl4;
3475 int32_t ret;
3476
3477 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
3478 if (ret == 0)
3479 {
3480 fifo_ctrl4.fifo_mode = (uint8_t)val & 0x07U;
3481 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
3482 }
3483
3484 return ret;
3485 }
3486
3487 /**
3488 * @brief FIFO mode selection.[get]
3489 *
3490 * @param ctx read / write interface definitions
3491 * @param val BYPASS_MODE, FIFO_MODE, STREAM_WTM_TO_FULL_MODE, STREAM_TO_FIFO_MODE, BYPASS_TO_STREAM_MODE, STREAM_MODE, BYPASS_TO_FIFO_MODE,
3492 * @retval interface status (MANDATORY: return 0 -> no Error)
3493 *
3494 */
lsm6dsv16x_fifo_mode_get(stmdev_ctx_t * ctx,lsm6dsv16x_fifo_mode_t * val)3495 int32_t lsm6dsv16x_fifo_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_fifo_mode_t *val)
3496 {
3497 lsm6dsv16x_fifo_ctrl4_t fifo_ctrl4;
3498 int32_t ret;
3499
3500 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
3501 if (ret != 0) { return ret; }
3502
3503 switch (fifo_ctrl4.fifo_mode)
3504 {
3505 case LSM6DSV16X_BYPASS_MODE:
3506 *val = LSM6DSV16X_BYPASS_MODE;
3507 break;
3508
3509 case LSM6DSV16X_FIFO_MODE:
3510 *val = LSM6DSV16X_FIFO_MODE;
3511 break;
3512
3513 case LSM6DSV16X_STREAM_WTM_TO_FULL_MODE:
3514 *val = LSM6DSV16X_STREAM_WTM_TO_FULL_MODE;
3515 break;
3516
3517 case LSM6DSV16X_STREAM_TO_FIFO_MODE:
3518 *val = LSM6DSV16X_STREAM_TO_FIFO_MODE;
3519 break;
3520
3521 case LSM6DSV16X_BYPASS_TO_STREAM_MODE:
3522 *val = LSM6DSV16X_BYPASS_TO_STREAM_MODE;
3523 break;
3524
3525 case LSM6DSV16X_STREAM_MODE:
3526 *val = LSM6DSV16X_STREAM_MODE;
3527 break;
3528
3529 case LSM6DSV16X_BYPASS_TO_FIFO_MODE:
3530 *val = LSM6DSV16X_BYPASS_TO_FIFO_MODE;
3531 break;
3532
3533 default:
3534 *val = LSM6DSV16X_BYPASS_MODE;
3535 break;
3536 }
3537 return ret;
3538 }
3539
3540 /**
3541 * @brief Enables FIFO batching of EIS gyroscope output values.[set]
3542 *
3543 * @param ctx read / write interface definitions
3544 * @param val Enables FIFO batching of EIS gyroscope output values.
3545 * @retval interface status (MANDATORY: return 0 -> no Error)
3546 *
3547 */
lsm6dsv16x_fifo_gy_eis_batch_set(stmdev_ctx_t * ctx,uint8_t val)3548 int32_t lsm6dsv16x_fifo_gy_eis_batch_set(stmdev_ctx_t *ctx, uint8_t val)
3549 {
3550 lsm6dsv16x_fifo_ctrl4_t fifo_ctrl4;
3551 int32_t ret;
3552
3553 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
3554 if (ret == 0)
3555 {
3556 fifo_ctrl4.g_eis_fifo_en = val;
3557 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
3558 }
3559
3560 return ret;
3561 }
3562
3563 /**
3564 * @brief Enables FIFO batching of EIS gyroscope output values.[get]
3565 *
3566 * @param ctx read / write interface definitions
3567 * @param val Enables FIFO batching of EIS gyroscope output values.
3568 * @retval interface status (MANDATORY: return 0 -> no Error)
3569 *
3570 */
lsm6dsv16x_fifo_gy_eis_batch_get(stmdev_ctx_t * ctx,uint8_t * val)3571 int32_t lsm6dsv16x_fifo_gy_eis_batch_get(stmdev_ctx_t *ctx, uint8_t *val)
3572 {
3573 lsm6dsv16x_fifo_ctrl4_t fifo_ctrl4;
3574 int32_t ret;
3575
3576 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
3577 *val = fifo_ctrl4.g_eis_fifo_en;
3578
3579 return ret;
3580 }
3581
3582 /**
3583 * @brief Selects batch data rate (write frequency in FIFO) for temperature data.[set]
3584 *
3585 * @param ctx read / write interface definitions
3586 * @param val TEMP_NOT_BATCHED, TEMP_BATCHED_AT_1Hz875, TEMP_BATCHED_AT_15Hz, TEMP_BATCHED_AT_60Hz,
3587 * @retval interface status (MANDATORY: return 0 -> no Error)
3588 *
3589 */
lsm6dsv16x_fifo_temp_batch_set(stmdev_ctx_t * ctx,lsm6dsv16x_fifo_temp_batch_t val)3590 int32_t lsm6dsv16x_fifo_temp_batch_set(stmdev_ctx_t *ctx,
3591 lsm6dsv16x_fifo_temp_batch_t val)
3592 {
3593 lsm6dsv16x_fifo_ctrl4_t fifo_ctrl4;
3594 int32_t ret;
3595
3596 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
3597 if (ret == 0)
3598 {
3599 fifo_ctrl4.odr_t_batch = (uint8_t)val & 0x03U;
3600 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
3601 }
3602
3603 return ret;
3604 }
3605
3606 /**
3607 * @brief Selects batch data rate (write frequency in FIFO) for temperature data.[get]
3608 *
3609 * @param ctx read / write interface definitions
3610 * @param val TEMP_NOT_BATCHED, TEMP_BATCHED_AT_1Hz875, TEMP_BATCHED_AT_15Hz, TEMP_BATCHED_AT_60Hz,
3611 * @retval interface status (MANDATORY: return 0 -> no Error)
3612 *
3613 */
lsm6dsv16x_fifo_temp_batch_get(stmdev_ctx_t * ctx,lsm6dsv16x_fifo_temp_batch_t * val)3614 int32_t lsm6dsv16x_fifo_temp_batch_get(stmdev_ctx_t *ctx,
3615 lsm6dsv16x_fifo_temp_batch_t *val)
3616 {
3617 lsm6dsv16x_fifo_ctrl4_t fifo_ctrl4;
3618 int32_t ret;
3619
3620 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
3621 if (ret != 0) { return ret; }
3622
3623 switch (fifo_ctrl4.odr_t_batch)
3624 {
3625 case LSM6DSV16X_TEMP_NOT_BATCHED:
3626 *val = LSM6DSV16X_TEMP_NOT_BATCHED;
3627 break;
3628
3629 case LSM6DSV16X_TEMP_BATCHED_AT_1Hz875:
3630 *val = LSM6DSV16X_TEMP_BATCHED_AT_1Hz875;
3631 break;
3632
3633 case LSM6DSV16X_TEMP_BATCHED_AT_15Hz:
3634 *val = LSM6DSV16X_TEMP_BATCHED_AT_15Hz;
3635 break;
3636
3637 case LSM6DSV16X_TEMP_BATCHED_AT_60Hz:
3638 *val = LSM6DSV16X_TEMP_BATCHED_AT_60Hz;
3639 break;
3640
3641 default:
3642 *val = LSM6DSV16X_TEMP_NOT_BATCHED;
3643 break;
3644 }
3645 return ret;
3646 }
3647
3648 /**
3649 * @brief Selects decimation for timestamp batching in FIFO. Write rate will be the maximum rate between XL and GYRO BDR divided by decimation decoder.[set]
3650 *
3651 * @param ctx read / write interface definitions
3652 * @param val TMSTMP_NOT_BATCHED, TMSTMP_DEC_1, TMSTMP_DEC_8, TMSTMP_DEC_32,
3653 * @retval interface status (MANDATORY: return 0 -> no Error)
3654 *
3655 */
lsm6dsv16x_fifo_timestamp_batch_set(stmdev_ctx_t * ctx,lsm6dsv16x_fifo_timestamp_batch_t val)3656 int32_t lsm6dsv16x_fifo_timestamp_batch_set(stmdev_ctx_t *ctx,
3657 lsm6dsv16x_fifo_timestamp_batch_t val)
3658 {
3659 lsm6dsv16x_fifo_ctrl4_t fifo_ctrl4;
3660 int32_t ret;
3661
3662 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
3663 if (ret == 0)
3664 {
3665 fifo_ctrl4.dec_ts_batch = (uint8_t)val & 0x03U;
3666 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
3667 }
3668
3669 return ret;
3670 }
3671
3672 /**
3673 * @brief Selects decimation for timestamp batching in FIFO. Write rate will be the maximum rate between XL and GYRO BDR divided by decimation decoder.[get]
3674 *
3675 * @param ctx read / write interface definitions
3676 * @param val TMSTMP_NOT_BATCHED, TMSTMP_DEC_1, TMSTMP_DEC_8, TMSTMP_DEC_32,
3677 * @retval interface status (MANDATORY: return 0 -> no Error)
3678 *
3679 */
lsm6dsv16x_fifo_timestamp_batch_get(stmdev_ctx_t * ctx,lsm6dsv16x_fifo_timestamp_batch_t * val)3680 int32_t lsm6dsv16x_fifo_timestamp_batch_get(stmdev_ctx_t *ctx,
3681 lsm6dsv16x_fifo_timestamp_batch_t *val)
3682 {
3683 lsm6dsv16x_fifo_ctrl4_t fifo_ctrl4;
3684 int32_t ret;
3685
3686 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
3687 if (ret != 0) { return ret; }
3688
3689 switch (fifo_ctrl4.dec_ts_batch)
3690 {
3691 case LSM6DSV16X_TMSTMP_NOT_BATCHED:
3692 *val = LSM6DSV16X_TMSTMP_NOT_BATCHED;
3693 break;
3694
3695 case LSM6DSV16X_TMSTMP_DEC_1:
3696 *val = LSM6DSV16X_TMSTMP_DEC_1;
3697 break;
3698
3699 case LSM6DSV16X_TMSTMP_DEC_8:
3700 *val = LSM6DSV16X_TMSTMP_DEC_8;
3701 break;
3702
3703 case LSM6DSV16X_TMSTMP_DEC_32:
3704 *val = LSM6DSV16X_TMSTMP_DEC_32;
3705 break;
3706
3707 default:
3708 *val = LSM6DSV16X_TMSTMP_NOT_BATCHED;
3709 break;
3710 }
3711
3712 return ret;
3713 }
3714
3715 /**
3716 * @brief The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.[set]
3717 *
3718 * @param ctx read / write interface definitions
3719 * @param val The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.
3720 * @retval interface status (MANDATORY: return 0 -> no Error)
3721 *
3722 */
lsm6dsv16x_fifo_batch_counter_threshold_set(stmdev_ctx_t * ctx,uint16_t val)3723 int32_t lsm6dsv16x_fifo_batch_counter_threshold_set(stmdev_ctx_t *ctx,
3724 uint16_t val)
3725 {
3726 uint8_t buff[2];
3727 int32_t ret;
3728
3729 buff[1] = (uint8_t)(val / 256U);
3730 buff[0] = (uint8_t)(val - (buff[1] * 256U));
3731 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_COUNTER_BDR_REG1, (uint8_t *)&buff[0], 2);
3732
3733 return ret;
3734 }
3735
3736 /**
3737 * @brief The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.[get]
3738 *
3739 * @param ctx read / write interface definitions
3740 * @param val The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.
3741 * @retval interface status (MANDATORY: return 0 -> no Error)
3742 *
3743 */
lsm6dsv16x_fifo_batch_counter_threshold_get(stmdev_ctx_t * ctx,uint16_t * val)3744 int32_t lsm6dsv16x_fifo_batch_counter_threshold_get(stmdev_ctx_t *ctx,
3745 uint16_t *val)
3746 {
3747 uint8_t buff[2];
3748 int32_t ret;
3749
3750 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_COUNTER_BDR_REG1, &buff[0], 2);
3751 if (ret != 0) { return ret; }
3752
3753 *val = buff[1];
3754 *val = (*val * 256U) + buff[0];
3755
3756 return ret;
3757 }
3758
3759 /**
3760 * @brief Selects the trigger for the internal counter of batch events between the accelerometer, gyroscope and EIS gyroscope.[set]
3761 *
3762 * @param ctx read / write interface definitions
3763 * @param val XL_BATCH_EVENT, GY_BATCH_EVENT, GY_EIS_BATCH_EVENT,
3764 * @retval interface status (MANDATORY: return 0 -> no Error)
3765 *
3766 */
lsm6dsv16x_fifo_batch_cnt_event_set(stmdev_ctx_t * ctx,lsm6dsv16x_fifo_batch_cnt_event_t val)3767 int32_t lsm6dsv16x_fifo_batch_cnt_event_set(stmdev_ctx_t *ctx,
3768 lsm6dsv16x_fifo_batch_cnt_event_t val)
3769 {
3770 lsm6dsv16x_counter_bdr_reg1_t counter_bdr_reg1;
3771 int32_t ret;
3772
3773 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
3774 if (ret == 0)
3775 {
3776 counter_bdr_reg1.trig_counter_bdr = (uint8_t)val & 0x03U;
3777 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
3778 }
3779
3780 return ret;
3781 }
3782
3783 /**
3784 * @brief Selects the trigger for the internal counter of batch events between the accelerometer, gyroscope and EIS gyroscope.[get]
3785 *
3786 * @param ctx read / write interface definitions
3787 * @param val XL_BATCH_EVENT, GY_BATCH_EVENT, GY_EIS_BATCH_EVENT,
3788 * @retval interface status (MANDATORY: return 0 -> no Error)
3789 *
3790 */
lsm6dsv16x_fifo_batch_cnt_event_get(stmdev_ctx_t * ctx,lsm6dsv16x_fifo_batch_cnt_event_t * val)3791 int32_t lsm6dsv16x_fifo_batch_cnt_event_get(stmdev_ctx_t *ctx,
3792 lsm6dsv16x_fifo_batch_cnt_event_t *val)
3793 {
3794 lsm6dsv16x_counter_bdr_reg1_t counter_bdr_reg1;
3795 int32_t ret;
3796
3797 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
3798 if (ret != 0) { return ret; }
3799
3800 switch (counter_bdr_reg1.trig_counter_bdr)
3801 {
3802 case LSM6DSV16X_XL_BATCH_EVENT:
3803 *val = LSM6DSV16X_XL_BATCH_EVENT;
3804 break;
3805
3806 case LSM6DSV16X_GY_BATCH_EVENT:
3807 *val = LSM6DSV16X_GY_BATCH_EVENT;
3808 break;
3809
3810 case LSM6DSV16X_GY_EIS_BATCH_EVENT:
3811 *val = LSM6DSV16X_GY_EIS_BATCH_EVENT;
3812 break;
3813
3814 default:
3815 *val = LSM6DSV16X_XL_BATCH_EVENT;
3816 break;
3817 }
3818
3819 return ret;
3820 }
3821
lsm6dsv16x_fifo_status_get(stmdev_ctx_t * ctx,lsm6dsv16x_fifo_status_t * val)3822 int32_t lsm6dsv16x_fifo_status_get(stmdev_ctx_t *ctx,
3823 lsm6dsv16x_fifo_status_t *val)
3824 {
3825 uint8_t buff[2];
3826 lsm6dsv16x_fifo_status2_t status;
3827 int32_t ret;
3828
3829 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_STATUS1, (uint8_t *)&buff[0], 2);
3830 if (ret != 0) { return ret; }
3831
3832 bytecpy((uint8_t *)&status, &buff[1]);
3833
3834 val->fifo_bdr = status.counter_bdr_ia;
3835 val->fifo_ovr = status.fifo_ovr_ia;
3836 val->fifo_full = status.fifo_full_ia;
3837 val->fifo_th = status.fifo_wtm_ia;
3838
3839 val->fifo_level = (uint16_t)buff[1] & 0x01U;
3840 val->fifo_level = (val->fifo_level * 256U) + buff[0];
3841
3842 return ret;
3843 }
3844
3845
3846 /**
3847 * @brief FIFO data output[get]
3848 *
3849 * @param ctx read / write interface definitions
3850 * @param val FIFO_EMPTY, GY_NC_TAG, XL_NC_TAG, TIMESTAMP_TAG,
3851 TEMPERATURE_TAG, CFG_CHANGE_TAG, XL_NC_T_2_TAG,
3852 XL_NC_T_1_TAG, XL_2XC_TAG, XL_3XC_TAG, GY_NC_T_2_TAG,
3853 GY_NC_T_1_TAG, GY_2XC_TAG, GY_3XC_TAG, SENSORHUB_SLAVE0_TAG,
3854 SENSORHUB_SLAVE1_TAG, SENSORHUB_SLAVE2_TAG, SENSORHUB_SLAVE3_TAG,
3855 STEP_COUNTER_TAG, SFLP_GAME_ROTATION_VECTOR_TAG, SFLP_GYROSCOPE_BIAS_TAG,
3856 SFLP_GRAVITY_VECTOR_TAG, SENSORHUB_NACK_TAG, MLC_RESULT_TAG,
3857 MLC_FILTER, MLC_FEATURE, XL_DUAL_CORE, GY_ENHANCED_EIS,
3858 * @retval interface status (MANDATORY: return 0 -> no Error)
3859 *
3860 */
lsm6dsv16x_fifo_out_raw_get(stmdev_ctx_t * ctx,lsm6dsv16x_fifo_out_raw_t * val)3861 int32_t lsm6dsv16x_fifo_out_raw_get(stmdev_ctx_t *ctx,
3862 lsm6dsv16x_fifo_out_raw_t *val)
3863 {
3864 lsm6dsv16x_fifo_data_out_tag_t fifo_data_out_tag;
3865 uint8_t buff[7];
3866 int32_t ret;
3867
3868 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_DATA_OUT_TAG, buff, 7);
3869 if (ret != 0) { return ret; }
3870
3871 bytecpy((uint8_t *)&fifo_data_out_tag, &buff[0]);
3872
3873 switch (fifo_data_out_tag.tag_sensor)
3874 {
3875 case LSM6DSV16X_FIFO_EMPTY:
3876 val->tag = LSM6DSV16X_FIFO_EMPTY;
3877 break;
3878
3879 case LSM6DSV16X_GY_NC_TAG:
3880 val->tag = LSM6DSV16X_GY_NC_TAG;
3881 break;
3882
3883 case LSM6DSV16X_XL_NC_TAG:
3884 val->tag = LSM6DSV16X_XL_NC_TAG;
3885 break;
3886
3887 case LSM6DSV16X_TIMESTAMP_TAG:
3888 val->tag = LSM6DSV16X_TIMESTAMP_TAG;
3889 break;
3890
3891 case LSM6DSV16X_TEMPERATURE_TAG:
3892 val->tag = LSM6DSV16X_TEMPERATURE_TAG;
3893 break;
3894
3895 case LSM6DSV16X_CFG_CHANGE_TAG:
3896 val->tag = LSM6DSV16X_CFG_CHANGE_TAG;
3897 break;
3898
3899 case LSM6DSV16X_XL_NC_T_2_TAG:
3900 val->tag = LSM6DSV16X_XL_NC_T_2_TAG;
3901 break;
3902
3903 case LSM6DSV16X_XL_NC_T_1_TAG:
3904 val->tag = LSM6DSV16X_XL_NC_T_1_TAG;
3905 break;
3906
3907 case LSM6DSV16X_XL_2XC_TAG:
3908 val->tag = LSM6DSV16X_XL_2XC_TAG;
3909 break;
3910
3911 case LSM6DSV16X_XL_3XC_TAG:
3912 val->tag = LSM6DSV16X_XL_3XC_TAG;
3913 break;
3914
3915 case LSM6DSV16X_GY_NC_T_2_TAG:
3916 val->tag = LSM6DSV16X_GY_NC_T_2_TAG;
3917 break;
3918
3919 case LSM6DSV16X_GY_NC_T_1_TAG:
3920 val->tag = LSM6DSV16X_GY_NC_T_1_TAG;
3921 break;
3922
3923 case LSM6DSV16X_GY_2XC_TAG:
3924 val->tag = LSM6DSV16X_GY_2XC_TAG;
3925 break;
3926
3927 case LSM6DSV16X_GY_3XC_TAG:
3928 val->tag = LSM6DSV16X_GY_3XC_TAG;
3929 break;
3930
3931 case LSM6DSV16X_SENSORHUB_SLAVE0_TAG:
3932 val->tag = LSM6DSV16X_SENSORHUB_SLAVE0_TAG;
3933 break;
3934
3935 case LSM6DSV16X_SENSORHUB_SLAVE1_TAG:
3936 val->tag = LSM6DSV16X_SENSORHUB_SLAVE1_TAG;
3937 break;
3938
3939 case LSM6DSV16X_SENSORHUB_SLAVE2_TAG:
3940 val->tag = LSM6DSV16X_SENSORHUB_SLAVE2_TAG;
3941 break;
3942
3943 case LSM6DSV16X_SENSORHUB_SLAVE3_TAG:
3944 val->tag = LSM6DSV16X_SENSORHUB_SLAVE3_TAG;
3945 break;
3946
3947 case LSM6DSV16X_STEP_COUNTER_TAG:
3948 val->tag = LSM6DSV16X_STEP_COUNTER_TAG;
3949 break;
3950
3951 case LSM6DSV16X_SFLP_GAME_ROTATION_VECTOR_TAG:
3952 val->tag = LSM6DSV16X_SFLP_GAME_ROTATION_VECTOR_TAG;
3953 break;
3954
3955 case LSM6DSV16X_SFLP_GYROSCOPE_BIAS_TAG:
3956 val->tag = LSM6DSV16X_SFLP_GYROSCOPE_BIAS_TAG;
3957 break;
3958
3959 case LSM6DSV16X_SFLP_GRAVITY_VECTOR_TAG:
3960 val->tag = LSM6DSV16X_SFLP_GRAVITY_VECTOR_TAG;
3961 break;
3962
3963 case LSM6DSV16X_SENSORHUB_NACK_TAG:
3964 val->tag = LSM6DSV16X_SENSORHUB_NACK_TAG;
3965 break;
3966
3967 case LSM6DSV16X_MLC_RESULT_TAG:
3968 val->tag = LSM6DSV16X_MLC_RESULT_TAG;
3969 break;
3970
3971 case LSM6DSV16X_MLC_FILTER:
3972 val->tag = LSM6DSV16X_MLC_FILTER;
3973 break;
3974
3975 case LSM6DSV16X_MLC_FEATURE:
3976 val->tag = LSM6DSV16X_MLC_FEATURE;
3977 break;
3978
3979 case LSM6DSV16X_XL_DUAL_CORE:
3980 val->tag = LSM6DSV16X_XL_DUAL_CORE;
3981 break;
3982
3983 case LSM6DSV16X_GY_ENHANCED_EIS:
3984 val->tag = LSM6DSV16X_GY_ENHANCED_EIS;
3985 break;
3986
3987 default:
3988 val->tag = LSM6DSV16X_FIFO_EMPTY;
3989 break;
3990 }
3991
3992 val->cnt = fifo_data_out_tag.tag_cnt;
3993
3994 val->data[0] = buff[1];
3995 val->data[1] = buff[2];
3996 val->data[2] = buff[3];
3997 val->data[3] = buff[4];
3998 val->data[4] = buff[5];
3999 val->data[5] = buff[6];
4000
4001 return ret;
4002 }
4003
4004 /**
4005 * @brief Batching in FIFO buffer of step counter value.[set]
4006 *
4007 * @param ctx read / write interface definitions
4008 * @param val Batching in FIFO buffer of step counter value.
4009 * @retval interface status (MANDATORY: return 0 -> no Error)
4010 *
4011 */
lsm6dsv16x_fifo_stpcnt_batch_set(stmdev_ctx_t * ctx,uint8_t val)4012 int32_t lsm6dsv16x_fifo_stpcnt_batch_set(stmdev_ctx_t *ctx, uint8_t val)
4013 {
4014 lsm6dsv16x_emb_func_fifo_en_a_t emb_func_fifo_en_a;
4015 int32_t ret;
4016
4017 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
4018 if (ret != 0) { return ret; }
4019
4020 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
4021 emb_func_fifo_en_a.step_counter_fifo_en = val;
4022 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
4023
4024 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
4025
4026 return ret;
4027 }
4028
4029 /**
4030 * @brief Batching in FIFO buffer of step counter value.[get]
4031 *
4032 * @param ctx read / write interface definitions
4033 * @param val Batching in FIFO buffer of step counter value.
4034 * @retval interface status (MANDATORY: return 0 -> no Error)
4035 *
4036 */
lsm6dsv16x_fifo_stpcnt_batch_get(stmdev_ctx_t * ctx,uint8_t * val)4037 int32_t lsm6dsv16x_fifo_stpcnt_batch_get(stmdev_ctx_t *ctx, uint8_t *val)
4038 {
4039 lsm6dsv16x_emb_func_fifo_en_a_t emb_func_fifo_en_a;
4040 int32_t ret;
4041
4042 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
4043 if (ret != 0) { return ret; }
4044
4045 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
4046 *val = emb_func_fifo_en_a.step_counter_fifo_en;
4047
4048 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
4049
4050 return ret;
4051 }
4052
4053 /**
4054 * @brief Batching in FIFO buffer of machine learning core results.[set]
4055 *
4056 * @param ctx read / write interface definitions
4057 * @param val Batching in FIFO buffer of machine learning core results.
4058 * @retval interface status (MANDATORY: return 0 -> no Error)
4059 *
4060 */
lsm6dsv16x_fifo_mlc_batch_set(stmdev_ctx_t * ctx,uint8_t val)4061 int32_t lsm6dsv16x_fifo_mlc_batch_set(stmdev_ctx_t *ctx, uint8_t val)
4062 {
4063 lsm6dsv16x_emb_func_fifo_en_a_t emb_func_fifo_en_a;
4064 int32_t ret;
4065
4066 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
4067 if (ret != 0) { return ret; }
4068
4069 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
4070 emb_func_fifo_en_a.mlc_fifo_en = val;
4071 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
4072
4073 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
4074
4075 return ret;
4076 }
4077
4078 /**
4079 * @brief Batching in FIFO buffer of machine learning core results.[get]
4080 *
4081 * @param ctx read / write interface definitions
4082 * @param val Batching in FIFO buffer of machine learning core results.
4083 * @retval interface status (MANDATORY: return 0 -> no Error)
4084 *
4085 */
lsm6dsv16x_fifo_mlc_batch_get(stmdev_ctx_t * ctx,uint8_t * val)4086 int32_t lsm6dsv16x_fifo_mlc_batch_get(stmdev_ctx_t *ctx, uint8_t *val)
4087 {
4088 lsm6dsv16x_emb_func_fifo_en_a_t emb_func_fifo_en_a;
4089 int32_t ret;
4090
4091 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
4092 if (ret != 0) { return ret; }
4093
4094 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
4095 *val = emb_func_fifo_en_a.mlc_fifo_en;
4096
4097 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
4098
4099 return ret;
4100 }
4101
4102 /**
4103 * @brief Enables batching in FIFO buffer of machine learning core filters and features.[set]
4104 *
4105 * @param ctx read / write interface definitions
4106 * @param val Enables batching in FIFO buffer of machine learning core filters and features.
4107 * @retval interface status (MANDATORY: return 0 -> no Error)
4108 *
4109 */
lsm6dsv16x_fifo_mlc_filt_batch_set(stmdev_ctx_t * ctx,uint8_t val)4110 int32_t lsm6dsv16x_fifo_mlc_filt_batch_set(stmdev_ctx_t *ctx, uint8_t val)
4111 {
4112 lsm6dsv16x_emb_func_fifo_en_b_t emb_func_fifo_en_b;
4113 int32_t ret;
4114
4115 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
4116 if (ret != 0) { return ret; }
4117
4118 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1);
4119 emb_func_fifo_en_b.mlc_filter_feature_fifo_en = val;
4120 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1);
4121
4122 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
4123
4124 return ret;
4125 }
4126
4127 /**
4128 * @brief Enables batching in FIFO buffer of machine learning core filters and features.[get]
4129 *
4130 * @param ctx read / write interface definitions
4131 * @param val Enables batching in FIFO buffer of machine learning core filters and features.
4132 * @retval interface status (MANDATORY: return 0 -> no Error)
4133 *
4134 */
lsm6dsv16x_fifo_mlc_filt_batch_get(stmdev_ctx_t * ctx,uint8_t * val)4135 int32_t lsm6dsv16x_fifo_mlc_filt_batch_get(stmdev_ctx_t *ctx, uint8_t *val)
4136 {
4137 lsm6dsv16x_emb_func_fifo_en_b_t emb_func_fifo_en_b;
4138 int32_t ret;
4139
4140 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
4141 if (ret != 0) { return ret; }
4142
4143 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1);
4144 *val = emb_func_fifo_en_b.mlc_filter_feature_fifo_en;
4145
4146 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
4147
4148 return ret;
4149 }
4150
4151 /**
4152 * @brief Enable FIFO data batching of slave idx.[set]
4153 *
4154 * @param ctx read / write interface definitions
4155 * @param val Enable FIFO data batching of slave idx.
4156 * @retval interface status (MANDATORY: return 0 -> no Error)
4157 *
4158 */
lsm6dsv16x_fifo_sh_batch_slave_set(stmdev_ctx_t * ctx,uint8_t idx,uint8_t val)4159 int32_t lsm6dsv16x_fifo_sh_batch_slave_set(stmdev_ctx_t *ctx, uint8_t idx, uint8_t val)
4160 {
4161 lsm6dsv16x_slv0_config_t slv_config;
4162 int32_t ret;
4163
4164 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK);
4165 if (ret != 0) { return ret; }
4166
4167 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SLV0_CONFIG + idx*3U, (uint8_t *)&slv_config, 1);
4168 slv_config.batch_ext_sens_0_en = val;
4169 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SLV0_CONFIG + idx*3U, (uint8_t *)&slv_config, 1);
4170
4171 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
4172
4173 return ret;
4174 }
4175
4176 /**
4177 * @brief Enable FIFO data batching of slave idx.[get]
4178 *
4179 * @param ctx read / write interface definitions
4180 * @param val Enable FIFO data batching of slave idx.
4181 * @retval interface status (MANDATORY: return 0 -> no Error)
4182 *
4183 */
lsm6dsv16x_fifo_sh_batch_slave_get(stmdev_ctx_t * ctx,uint8_t idx,uint8_t * val)4184 int32_t lsm6dsv16x_fifo_sh_batch_slave_get(stmdev_ctx_t *ctx, uint8_t idx, uint8_t *val)
4185 {
4186 lsm6dsv16x_slv0_config_t slv_config;
4187 int32_t ret;
4188
4189 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK);
4190 if (ret != 0) { return ret; }
4191
4192 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SLV0_CONFIG + idx*3U, (uint8_t *)&slv_config, 1);
4193 *val = slv_config.batch_ext_sens_0_en;
4194
4195 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
4196
4197 return ret;
4198 }
4199
4200 /**
4201 * @brief Batching in FIFO buffer of SFLP.[set]
4202 *
4203 * @param ctx read / write interface definitions
4204 * @param val Batching in FIFO buffer of SFLP values.
4205 * @retval interface status (MANDATORY: return 0 -> no Error)
4206 *
4207 */
lsm6dsv16x_fifo_sflp_batch_set(stmdev_ctx_t * ctx,lsm6dsv16x_fifo_sflp_raw_t val)4208 int32_t lsm6dsv16x_fifo_sflp_batch_set(stmdev_ctx_t *ctx,
4209 lsm6dsv16x_fifo_sflp_raw_t val)
4210 {
4211 lsm6dsv16x_emb_func_fifo_en_a_t emb_func_fifo_en_a;
4212 int32_t ret;
4213
4214 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
4215 if (ret == 0)
4216 {
4217 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
4218 emb_func_fifo_en_a.sflp_game_fifo_en = val.game_rotation;
4219 emb_func_fifo_en_a.sflp_gravity_fifo_en = val.gravity;
4220 emb_func_fifo_en_a.sflp_gbias_fifo_en = val.gbias;
4221 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_FIFO_EN_A,
4222 (uint8_t *)&emb_func_fifo_en_a, 1);
4223 }
4224
4225 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
4226
4227 return ret;
4228 }
4229
4230 /**
4231 * @brief Batching in FIFO buffer of SFLP.[get]
4232 *
4233 * @param ctx read / write interface definitions
4234 * @param val Batching in FIFO buffer of SFLP values.
4235 * @retval interface status (MANDATORY: return 0 -> no Error)
4236 *
4237 */
lsm6dsv16x_fifo_sflp_batch_get(stmdev_ctx_t * ctx,lsm6dsv16x_fifo_sflp_raw_t * val)4238 int32_t lsm6dsv16x_fifo_sflp_batch_get(stmdev_ctx_t *ctx,
4239 lsm6dsv16x_fifo_sflp_raw_t *val)
4240 {
4241 lsm6dsv16x_emb_func_fifo_en_a_t emb_func_fifo_en_a;
4242 int32_t ret;
4243
4244 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
4245 if (ret == 0)
4246 {
4247 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
4248
4249 val->game_rotation = emb_func_fifo_en_a.sflp_game_fifo_en;
4250 val->gravity = emb_func_fifo_en_a.sflp_gravity_fifo_en;
4251 val->gbias = emb_func_fifo_en_a.sflp_gbias_fifo_en;
4252 }
4253
4254 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
4255
4256 return ret;
4257 }
4258
4259 /**
4260 * @}
4261 *
4262 */
4263
4264 /**
4265 * @defgroup Filters
4266 * @brief This section group all the functions concerning the
4267 * filters configuration
4268 * @{
4269 *
4270 */
4271
4272 /**
4273 * @brief Protocol anti-spike filters.[set]
4274 *
4275 * @param ctx read / write interface definitions
4276 * @param val AUTO, ALWAYS_ACTIVE,
4277 * @retval interface status (MANDATORY: return 0 -> no Error)
4278 *
4279 */
lsm6dsv16x_filt_anti_spike_set(stmdev_ctx_t * ctx,lsm6dsv16x_filt_anti_spike_t val)4280 int32_t lsm6dsv16x_filt_anti_spike_set(stmdev_ctx_t *ctx,
4281 lsm6dsv16x_filt_anti_spike_t val)
4282 {
4283 lsm6dsv16x_if_cfg_t if_cfg;
4284 int32_t ret;
4285
4286 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1);
4287
4288 if (ret == 0)
4289 {
4290 if_cfg.asf_ctrl = (uint8_t)val & 0x01U;
4291 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1);
4292 }
4293
4294 return ret;
4295 }
4296
4297 /**
4298 * @brief Protocol anti-spike filters.[get]
4299 *
4300 * @param ctx read / write interface definitions
4301 * @param val AUTO, ALWAYS_ACTIVE,
4302 * @retval interface status (MANDATORY: return 0 -> no Error)
4303 *
4304 */
lsm6dsv16x_filt_anti_spike_get(stmdev_ctx_t * ctx,lsm6dsv16x_filt_anti_spike_t * val)4305 int32_t lsm6dsv16x_filt_anti_spike_get(stmdev_ctx_t *ctx,
4306 lsm6dsv16x_filt_anti_spike_t *val)
4307 {
4308 lsm6dsv16x_if_cfg_t if_cfg;
4309 int32_t ret;
4310
4311 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1);
4312 if (ret != 0) { return ret; }
4313
4314 switch (if_cfg.asf_ctrl)
4315 {
4316 case LSM6DSV16X_AUTO:
4317 *val = LSM6DSV16X_AUTO;
4318 break;
4319
4320 case LSM6DSV16X_ALWAYS_ACTIVE:
4321 *val = LSM6DSV16X_ALWAYS_ACTIVE;
4322 break;
4323
4324 default:
4325 *val = LSM6DSV16X_AUTO;
4326 break;
4327 }
4328
4329 return ret;
4330 }
4331
4332 /**
4333 * @brief It masks DRDY and Interrupts RQ until filter settling ends.[set]
4334 *
4335 * @param ctx read / write interface definitions
4336 * @param val It masks DRDY and Interrupts RQ until filter settling ends.
4337 * @retval interface status (MANDATORY: return 0 -> no Error)
4338 *
4339 */
lsm6dsv16x_filt_settling_mask_set(stmdev_ctx_t * ctx,lsm6dsv16x_filt_settling_mask_t val)4340 int32_t lsm6dsv16x_filt_settling_mask_set(stmdev_ctx_t *ctx,
4341 lsm6dsv16x_filt_settling_mask_t val)
4342 {
4343 lsm6dsv16x_emb_func_cfg_t emb_func_cfg;
4344 lsm6dsv16x_ui_int_ois_t ui_int_ois;
4345 lsm6dsv16x_ctrl4_t ctrl4;
4346 int32_t ret;
4347
4348 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL4, (uint8_t *)&ctrl4, 1);
4349 ctrl4.drdy_mask = val.drdy;
4350 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL4, (uint8_t *)&ctrl4, 1);
4351 if (ret != 0) { return ret; }
4352
4353 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1);
4354 emb_func_cfg.emb_func_irq_mask_xl_settl = val.irq_xl;
4355 emb_func_cfg.emb_func_irq_mask_g_settl = val.irq_g;
4356 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1);
4357 if (ret != 0) { return ret; }
4358
4359 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_INT_OIS, (uint8_t *)&ui_int_ois, 1);
4360 ui_int_ois.drdy_mask_ois = val.ois_drdy;
4361 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_UI_INT_OIS, (uint8_t *)&ui_int_ois, 1);
4362
4363 return ret;
4364 }
4365
4366 /**
4367 * @brief It masks DRDY and Interrupts RQ until filter settling ends.[get]
4368 *
4369 * @param ctx read / write interface definitions
4370 * @param val It masks DRDY and Interrupts RQ until filter settling ends.
4371 * @retval interface status (MANDATORY: return 0 -> no Error)
4372 *
4373 */
lsm6dsv16x_filt_settling_mask_get(stmdev_ctx_t * ctx,lsm6dsv16x_filt_settling_mask_t * val)4374 int32_t lsm6dsv16x_filt_settling_mask_get(stmdev_ctx_t *ctx,
4375 lsm6dsv16x_filt_settling_mask_t *val)
4376 {
4377 lsm6dsv16x_emb_func_cfg_t emb_func_cfg;
4378 lsm6dsv16x_ui_int_ois_t ui_int_ois;
4379 lsm6dsv16x_ctrl4_t ctrl4;
4380 int32_t ret;
4381
4382 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL4, (uint8_t *)&ctrl4, 1);
4383 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1);
4384 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_INT_OIS, (uint8_t *)&ui_int_ois, 1);
4385
4386 val->irq_xl = emb_func_cfg.emb_func_irq_mask_xl_settl;
4387 val->irq_g = emb_func_cfg.emb_func_irq_mask_g_settl;
4388 val->drdy = ctrl4.drdy_mask;
4389
4390 return ret;
4391 }
4392
4393 /**
4394 * @brief It masks DRDY and Interrupts RQ until filter settling ends.[set]
4395 *
4396 * @param ctx read / write interface definitions
4397 * @param val It masks DRDY and Interrupts RQ until filter settling ends from OIS interface.
4398 * @retval interface status (MANDATORY: return 0 -> no Error)
4399 *
4400 */
lsm6dsv16x_filt_ois_settling_mask_set(stmdev_ctx_t * ctx,lsm6dsv16x_filt_ois_settling_mask_t val)4401 int32_t lsm6dsv16x_filt_ois_settling_mask_set(stmdev_ctx_t *ctx,
4402 lsm6dsv16x_filt_ois_settling_mask_t val)
4403 {
4404 lsm6dsv16x_spi2_int_ois_t spi2_int_ois;
4405 int32_t ret;
4406
4407 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1);
4408
4409 if (ret == 0)
4410 {
4411 spi2_int_ois.drdy_mask_ois = val.ois_drdy;
4412 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1);
4413 }
4414
4415 return ret;
4416 }
4417
4418 /**
4419 * @brief It masks DRDY and Interrupts RQ until filter settling ends.[get]
4420 *
4421 * @param ctx read / write interface definitions
4422 * @param val It masks DRDY and Interrupts RQ until filter settling ends.
4423 * @retval interface status (MANDATORY: return 0 -> no Error)
4424 *
4425 */
lsm6dsv16x_filt_ois_settling_mask_get(stmdev_ctx_t * ctx,lsm6dsv16x_filt_ois_settling_mask_t * val)4426 int32_t lsm6dsv16x_filt_ois_settling_mask_get(stmdev_ctx_t *ctx,
4427 lsm6dsv16x_filt_ois_settling_mask_t *val)
4428 {
4429
4430 lsm6dsv16x_spi2_int_ois_t spi2_int_ois;
4431 int32_t ret;
4432
4433 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1);
4434 val->ois_drdy = spi2_int_ois.drdy_mask_ois;
4435
4436 return ret;
4437 }
4438
4439 /**
4440 * @brief Gyroscope low-pass filter (LPF1) bandwidth selection.[set]
4441 *
4442 * @param ctx read / write interface definitions
4443 * @param val GY_ULTRA_LIGHT, GY_VERY_LIGHT, GY_LIGHT, GY_MEDIUM, GY_STRONG, GY_VERY_STRONG, GY_AGGRESSIVE, GY_XTREME,
4444 * @retval interface status (MANDATORY: return 0 -> no Error)
4445 *
4446 */
lsm6dsv16x_filt_gy_lp1_bandwidth_set(stmdev_ctx_t * ctx,lsm6dsv16x_filt_gy_lp1_bandwidth_t val)4447 int32_t lsm6dsv16x_filt_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
4448 lsm6dsv16x_filt_gy_lp1_bandwidth_t val)
4449 {
4450 lsm6dsv16x_ctrl6_t ctrl6;
4451 int32_t ret;
4452
4453 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL6, (uint8_t *)&ctrl6, 1);
4454 if (ret == 0)
4455 {
4456 ctrl6.lpf1_g_bw = (uint8_t)val & 0x0Fu;
4457 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL6, (uint8_t *)&ctrl6, 1);
4458 }
4459
4460 return ret;
4461 }
4462
4463 /**
4464 * @brief Gyroscope low-pass filter (LPF1) bandwidth selection.[get]
4465 *
4466 * @param ctx read / write interface definitions
4467 * @param val GY_ULTRA_LIGHT, GY_VERY_LIGHT, GY_LIGHT, GY_MEDIUM, GY_STRONG, GY_VERY_STRONG, GY_AGGRESSIVE, GY_XTREME,
4468 * @retval interface status (MANDATORY: return 0 -> no Error)
4469 *
4470 */
lsm6dsv16x_filt_gy_lp1_bandwidth_get(stmdev_ctx_t * ctx,lsm6dsv16x_filt_gy_lp1_bandwidth_t * val)4471 int32_t lsm6dsv16x_filt_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
4472 lsm6dsv16x_filt_gy_lp1_bandwidth_t *val)
4473 {
4474 lsm6dsv16x_ctrl6_t ctrl6;
4475 int32_t ret;
4476
4477 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL6, (uint8_t *)&ctrl6, 1);
4478 if (ret != 0) { return ret; }
4479
4480 switch (ctrl6.lpf1_g_bw)
4481 {
4482 case LSM6DSV16X_GY_ULTRA_LIGHT:
4483 *val = LSM6DSV16X_GY_ULTRA_LIGHT;
4484 break;
4485
4486 case LSM6DSV16X_GY_VERY_LIGHT:
4487 *val = LSM6DSV16X_GY_VERY_LIGHT;
4488 break;
4489
4490 case LSM6DSV16X_GY_LIGHT:
4491 *val = LSM6DSV16X_GY_LIGHT;
4492 break;
4493
4494 case LSM6DSV16X_GY_MEDIUM:
4495 *val = LSM6DSV16X_GY_MEDIUM;
4496 break;
4497
4498 case LSM6DSV16X_GY_STRONG:
4499 *val = LSM6DSV16X_GY_STRONG;
4500 break;
4501
4502 case LSM6DSV16X_GY_VERY_STRONG:
4503 *val = LSM6DSV16X_GY_VERY_STRONG;
4504 break;
4505
4506 case LSM6DSV16X_GY_AGGRESSIVE:
4507 *val = LSM6DSV16X_GY_AGGRESSIVE;
4508 break;
4509
4510 case LSM6DSV16X_GY_XTREME:
4511 *val = LSM6DSV16X_GY_XTREME;
4512 break;
4513
4514 default:
4515 *val = LSM6DSV16X_GY_ULTRA_LIGHT;
4516 break;
4517 }
4518
4519 return ret;
4520 }
4521
4522 /**
4523 * @brief It enables gyroscope digital LPF1 filter. If the OIS chain is disabled, the bandwidth can be selected through LPF1_G_BW.[set]
4524 *
4525 * @param ctx read / write interface definitions
4526 * @param val It enables gyroscope digital LPF1 filter. If the OIS chain is disabled, the bandwidth can be selected through LPF1_G_BW.
4527 * @retval interface status (MANDATORY: return 0 -> no Error)
4528 *
4529 */
lsm6dsv16x_filt_gy_lp1_set(stmdev_ctx_t * ctx,uint8_t val)4530 int32_t lsm6dsv16x_filt_gy_lp1_set(stmdev_ctx_t *ctx, uint8_t val)
4531 {
4532 lsm6dsv16x_ctrl7_t ctrl7;
4533 int32_t ret;
4534
4535 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL7, (uint8_t *)&ctrl7, 1);
4536 if (ret == 0)
4537 {
4538 ctrl7.lpf1_g_en = val;
4539 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL7, (uint8_t *)&ctrl7, 1);
4540 }
4541
4542 return ret;
4543 }
4544
4545
4546 /**
4547 * @brief It enables gyroscope digital LPF1 filter. If the OIS chain is disabled, the bandwidth can be selected through LPF1_G_BW.[get]
4548 *
4549 * @param ctx read / write interface definitions
4550 * @param val It enables gyroscope digital LPF1 filter. If the OIS chain is disabled, the bandwidth can be selected through LPF1_G_BW.
4551 * @retval interface status (MANDATORY: return 0 -> no Error)
4552 *
4553 */
lsm6dsv16x_filt_gy_lp1_get(stmdev_ctx_t * ctx,uint8_t * val)4554 int32_t lsm6dsv16x_filt_gy_lp1_get(stmdev_ctx_t *ctx, uint8_t *val)
4555 {
4556 lsm6dsv16x_ctrl7_t ctrl7;
4557 int32_t ret;
4558
4559 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL7, (uint8_t *)&ctrl7, 1);
4560 *val = ctrl7.lpf1_g_en;
4561
4562 return ret;
4563 }
4564
4565 /**
4566 * @brief Accelerometer LPF2 and high pass filter configuration and cutoff setting.[set]
4567 *
4568 * @param ctx read / write interface definitions
4569 * @param val XL_ULTRA_LIGHT, XL_VERY_LIGHT, XL_LIGHT, XL_MEDIUM, XL_STRONG, XL_VERY_STRONG, XL_AGGRESSIVE, XL_XTREME,
4570 * @retval interface status (MANDATORY: return 0 -> no Error)
4571 *
4572 */
lsm6dsv16x_filt_xl_lp2_bandwidth_set(stmdev_ctx_t * ctx,lsm6dsv16x_filt_xl_lp2_bandwidth_t val)4573 int32_t lsm6dsv16x_filt_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx,
4574 lsm6dsv16x_filt_xl_lp2_bandwidth_t val)
4575 {
4576 lsm6dsv16x_ctrl8_t ctrl8;
4577 int32_t ret;
4578
4579 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL8, (uint8_t *)&ctrl8, 1);
4580 if (ret == 0)
4581 {
4582 ctrl8.hp_lpf2_xl_bw = (uint8_t)val & 0x07U;
4583 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL8, (uint8_t *)&ctrl8, 1);
4584 }
4585
4586 return ret;
4587 }
4588
4589 /**
4590 * @brief Accelerometer LPF2 and high pass filter configuration and cutoff setting.[get]
4591 *
4592 * @param ctx read / write interface definitions
4593 * @param val XL_ULTRA_LIGHT, XL_VERY_LIGHT, XL_LIGHT, XL_MEDIUM, XL_STRONG, XL_VERY_STRONG, XL_AGGRESSIVE, XL_XTREME,
4594 * @retval interface status (MANDATORY: return 0 -> no Error)
4595 *
4596 */
lsm6dsv16x_filt_xl_lp2_bandwidth_get(stmdev_ctx_t * ctx,lsm6dsv16x_filt_xl_lp2_bandwidth_t * val)4597 int32_t lsm6dsv16x_filt_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx,
4598 lsm6dsv16x_filt_xl_lp2_bandwidth_t *val)
4599 {
4600 lsm6dsv16x_ctrl8_t ctrl8;
4601 int32_t ret;
4602
4603 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL8, (uint8_t *)&ctrl8, 1);
4604 if (ret != 0) { return ret; }
4605
4606 switch (ctrl8.hp_lpf2_xl_bw)
4607 {
4608 case LSM6DSV16X_XL_ULTRA_LIGHT:
4609 *val = LSM6DSV16X_XL_ULTRA_LIGHT;
4610 break;
4611
4612 case LSM6DSV16X_XL_VERY_LIGHT:
4613 *val = LSM6DSV16X_XL_VERY_LIGHT;
4614 break;
4615
4616 case LSM6DSV16X_XL_LIGHT:
4617 *val = LSM6DSV16X_XL_LIGHT;
4618 break;
4619
4620 case LSM6DSV16X_XL_MEDIUM:
4621 *val = LSM6DSV16X_XL_MEDIUM;
4622 break;
4623
4624 case LSM6DSV16X_XL_STRONG:
4625 *val = LSM6DSV16X_XL_STRONG;
4626 break;
4627
4628 case LSM6DSV16X_XL_VERY_STRONG:
4629 *val = LSM6DSV16X_XL_VERY_STRONG;
4630 break;
4631
4632 case LSM6DSV16X_XL_AGGRESSIVE:
4633 *val = LSM6DSV16X_XL_AGGRESSIVE;
4634 break;
4635
4636 case LSM6DSV16X_XL_XTREME:
4637 *val = LSM6DSV16X_XL_XTREME;
4638 break;
4639
4640 default:
4641 *val = LSM6DSV16X_XL_ULTRA_LIGHT;
4642 break;
4643 }
4644
4645 return ret;
4646 }
4647
4648 /**
4649 * @brief Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.[set]
4650 *
4651 * @param ctx read / write interface definitions
4652 * @param val Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.
4653 * @retval interface status (MANDATORY: return 0 -> no Error)
4654 *
4655 */
lsm6dsv16x_filt_xl_lp2_set(stmdev_ctx_t * ctx,uint8_t val)4656 int32_t lsm6dsv16x_filt_xl_lp2_set(stmdev_ctx_t *ctx, uint8_t val)
4657 {
4658 lsm6dsv16x_ctrl9_t ctrl9;
4659 int32_t ret;
4660
4661 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1);
4662 if (ret == 0)
4663 {
4664 ctrl9.lpf2_xl_en = val;
4665 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1);
4666 }
4667
4668 return ret;
4669 }
4670
4671 /**
4672 * @brief Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.[get]
4673 *
4674 * @param ctx read / write interface definitions
4675 * @param val Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.
4676 * @retval interface status (MANDATORY: return 0 -> no Error)
4677 *
4678 */
lsm6dsv16x_filt_xl_lp2_get(stmdev_ctx_t * ctx,uint8_t * val)4679 int32_t lsm6dsv16x_filt_xl_lp2_get(stmdev_ctx_t *ctx, uint8_t *val)
4680 {
4681 lsm6dsv16x_ctrl9_t ctrl9;
4682 int32_t ret;
4683
4684 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1);
4685 *val = ctrl9.lpf2_xl_en;
4686
4687 return ret;
4688 }
4689
4690 /**
4691 * @brief Accelerometer slope filter / high-pass filter selection.[set]
4692 *
4693 * @param ctx read / write interface definitions
4694 * @param val Accelerometer slope filter / high-pass filter selection.
4695 * @retval interface status (MANDATORY: return 0 -> no Error)
4696 *
4697 */
lsm6dsv16x_filt_xl_hp_set(stmdev_ctx_t * ctx,uint8_t val)4698 int32_t lsm6dsv16x_filt_xl_hp_set(stmdev_ctx_t *ctx, uint8_t val)
4699 {
4700 lsm6dsv16x_ctrl9_t ctrl9;
4701 int32_t ret;
4702
4703 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1);
4704 if (ret == 0)
4705 {
4706 ctrl9.hp_slope_xl_en = val;
4707 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1);
4708 }
4709
4710 return ret;
4711 }
4712
4713 /**
4714 * @brief Accelerometer slope filter / high-pass filter selection.[get]
4715 *
4716 * @param ctx read / write interface definitions
4717 * @param val Accelerometer slope filter / high-pass filter selection.
4718 * @retval interface status (MANDATORY: return 0 -> no Error)
4719 *
4720 */
lsm6dsv16x_filt_xl_hp_get(stmdev_ctx_t * ctx,uint8_t * val)4721 int32_t lsm6dsv16x_filt_xl_hp_get(stmdev_ctx_t *ctx, uint8_t *val)
4722 {
4723 lsm6dsv16x_ctrl9_t ctrl9;
4724 int32_t ret;
4725
4726 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1);
4727 *val = ctrl9.hp_slope_xl_en;
4728
4729 return ret;
4730 }
4731
4732 /**
4733 * @brief Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.[set]
4734 *
4735 * @param ctx read / write interface definitions
4736 * @param val Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.
4737 * @retval interface status (MANDATORY: return 0 -> no Error)
4738 *
4739 */
lsm6dsv16x_filt_xl_fast_settling_set(stmdev_ctx_t * ctx,uint8_t val)4740 int32_t lsm6dsv16x_filt_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val)
4741 {
4742 lsm6dsv16x_ctrl9_t ctrl9;
4743 int32_t ret;
4744
4745 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1);
4746 if (ret == 0)
4747 {
4748 ctrl9.xl_fastsettl_mode = val;
4749 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1);
4750 }
4751
4752 return ret;
4753 }
4754
4755 /**
4756 * @brief Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.[get]
4757 *
4758 * @param ctx read / write interface definitions
4759 * @param val Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.
4760 * @retval interface status (MANDATORY: return 0 -> no Error)
4761 *
4762 */
lsm6dsv16x_filt_xl_fast_settling_get(stmdev_ctx_t * ctx,uint8_t * val)4763 int32_t lsm6dsv16x_filt_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val)
4764 {
4765 lsm6dsv16x_ctrl9_t ctrl9;
4766 int32_t ret;
4767
4768 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1);
4769 *val = ctrl9.xl_fastsettl_mode;
4770
4771 return ret;
4772 }
4773
4774 /**
4775 * @brief Accelerometer high-pass filter mode.[set]
4776 *
4777 * @param ctx read / write interface definitions
4778 * @param val HP_MD_NORMAL, HP_MD_REFERENCE,
4779 * @retval interface status (MANDATORY: return 0 -> no Error)
4780 *
4781 */
lsm6dsv16x_filt_xl_hp_mode_set(stmdev_ctx_t * ctx,lsm6dsv16x_filt_xl_hp_mode_t val)4782 int32_t lsm6dsv16x_filt_xl_hp_mode_set(stmdev_ctx_t *ctx,
4783 lsm6dsv16x_filt_xl_hp_mode_t val)
4784 {
4785 lsm6dsv16x_ctrl9_t ctrl9;
4786 int32_t ret;
4787
4788 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1);
4789 if (ret == 0)
4790 {
4791 ctrl9.hp_ref_mode_xl = (uint8_t)val & 0x01U;
4792 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1);
4793 }
4794
4795 return ret;
4796 }
4797
4798 /**
4799 * @brief Accelerometer high-pass filter mode.[get]
4800 *
4801 * @param ctx read / write interface definitions
4802 * @param val HP_MD_NORMAL, HP_MD_REFERENCE,
4803 * @retval interface status (MANDATORY: return 0 -> no Error)
4804 *
4805 */
lsm6dsv16x_filt_xl_hp_mode_get(stmdev_ctx_t * ctx,lsm6dsv16x_filt_xl_hp_mode_t * val)4806 int32_t lsm6dsv16x_filt_xl_hp_mode_get(stmdev_ctx_t *ctx,
4807 lsm6dsv16x_filt_xl_hp_mode_t *val)
4808 {
4809 lsm6dsv16x_ctrl9_t ctrl9;
4810 int32_t ret;
4811
4812 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1);
4813 if (ret != 0) { return ret; }
4814
4815 switch (ctrl9.hp_ref_mode_xl)
4816 {
4817 case LSM6DSV16X_HP_MD_NORMAL:
4818 *val = LSM6DSV16X_HP_MD_NORMAL;
4819 break;
4820
4821 case LSM6DSV16X_HP_MD_REFERENCE:
4822 *val = LSM6DSV16X_HP_MD_REFERENCE;
4823 break;
4824
4825 default:
4826 *val = LSM6DSV16X_HP_MD_NORMAL;
4827 break;
4828 }
4829
4830 return ret;
4831 }
4832
4833 /**
4834 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity functions.[set]
4835 *
4836 * @param ctx read / write interface definitions
4837 * @param val WK_FEED_SLOPE, WK_FEED_HIGH_PASS, WK_FEED_LP_WITH_OFFSET,
4838 * @retval interface status (MANDATORY: return 0 -> no Error)
4839 *
4840 */
lsm6dsv16x_filt_wkup_act_feed_set(stmdev_ctx_t * ctx,lsm6dsv16x_filt_wkup_act_feed_t val)4841 int32_t lsm6dsv16x_filt_wkup_act_feed_set(stmdev_ctx_t *ctx,
4842 lsm6dsv16x_filt_wkup_act_feed_t val)
4843 {
4844 lsm6dsv16x_wake_up_ths_t wake_up_ths;
4845 lsm6dsv16x_tap_cfg0_t tap_cfg0;
4846 int32_t ret;
4847
4848 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
4849 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
4850 if (ret != 0) { return ret; }
4851
4852 tap_cfg0.slope_fds = (uint8_t)val & 0x01U;
4853 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
4854 if (ret != 0) { return ret; }
4855
4856 wake_up_ths.usr_off_on_wu = ((uint8_t)val & 0x02U) >> 1;
4857 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
4858
4859 return ret;
4860 }
4861
4862 /**
4863 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity functions.[get]
4864 *
4865 * @param ctx read / write interface definitions
4866 * @param val WK_FEED_SLOPE, WK_FEED_HIGH_PASS, WK_FEED_LP_WITH_OFFSET,
4867 * @retval interface status (MANDATORY: return 0 -> no Error)
4868 *
4869 */
lsm6dsv16x_filt_wkup_act_feed_get(stmdev_ctx_t * ctx,lsm6dsv16x_filt_wkup_act_feed_t * val)4870 int32_t lsm6dsv16x_filt_wkup_act_feed_get(stmdev_ctx_t *ctx,
4871 lsm6dsv16x_filt_wkup_act_feed_t *val)
4872 {
4873 lsm6dsv16x_wake_up_ths_t wake_up_ths;
4874 lsm6dsv16x_tap_cfg0_t tap_cfg0;
4875 int32_t ret;
4876
4877 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
4878 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
4879 if (ret != 0) { return ret; }
4880
4881 switch ((wake_up_ths.usr_off_on_wu << 1) + tap_cfg0.slope_fds)
4882 {
4883 case LSM6DSV16X_WK_FEED_SLOPE:
4884 *val = LSM6DSV16X_WK_FEED_SLOPE;
4885 break;
4886
4887 case LSM6DSV16X_WK_FEED_HIGH_PASS:
4888 *val = LSM6DSV16X_WK_FEED_HIGH_PASS;
4889 break;
4890
4891 case LSM6DSV16X_WK_FEED_LP_WITH_OFFSET:
4892 *val = LSM6DSV16X_WK_FEED_LP_WITH_OFFSET;
4893 break;
4894
4895 default:
4896 *val = LSM6DSV16X_WK_FEED_SLOPE;
4897 break;
4898 }
4899
4900 return ret;
4901 }
4902
4903 /**
4904 * @brief Mask hw function triggers when xl is settling.[set]
4905 *
4906 * @param ctx read / write interface definitions
4907 * @param val 0 or 1,
4908 * @retval interface status (MANDATORY: return 0 -> no Error)
4909 *
4910 */
lsm6dsv16x_mask_trigger_xl_settl_set(stmdev_ctx_t * ctx,uint8_t val)4911 int32_t lsm6dsv16x_mask_trigger_xl_settl_set(stmdev_ctx_t *ctx, uint8_t val)
4912 {
4913 lsm6dsv16x_tap_cfg0_t tap_cfg0;
4914 int32_t ret;
4915
4916 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
4917
4918 if (ret == 0)
4919 {
4920 tap_cfg0.hw_func_mask_xl_settl = val & 0x01U;
4921 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
4922 }
4923
4924 return ret;
4925 }
4926
4927 /**
4928 * @brief Mask hw function triggers when xl is settling.[get]
4929 *
4930 * @param ctx read / write interface definitions
4931 * @param val 0 or 1,
4932 * @retval interface status (MANDATORY: return 0 -> no Error)
4933 *
4934 */
lsm6dsv16x_mask_trigger_xl_settl_get(stmdev_ctx_t * ctx,uint8_t * val)4935 int32_t lsm6dsv16x_mask_trigger_xl_settl_get(stmdev_ctx_t *ctx, uint8_t *val)
4936 {
4937 lsm6dsv16x_tap_cfg0_t tap_cfg0;
4938 int32_t ret;
4939
4940 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
4941 *val = tap_cfg0.hw_func_mask_xl_settl;
4942
4943 return ret;
4944 }
4945
4946 /**
4947 * @brief LPF2 filter on 6D (sixd) function selection.[set]
4948 *
4949 * @param ctx read / write interface definitions
4950 * @param val SIXD_FEED_ODR_DIV_2, SIXD_FEED_LOW_PASS,
4951 * @retval interface status (MANDATORY: return 0 -> no Error)
4952 *
4953 */
lsm6dsv16x_filt_sixd_feed_set(stmdev_ctx_t * ctx,lsm6dsv16x_filt_sixd_feed_t val)4954 int32_t lsm6dsv16x_filt_sixd_feed_set(stmdev_ctx_t *ctx,
4955 lsm6dsv16x_filt_sixd_feed_t val)
4956 {
4957 lsm6dsv16x_tap_cfg0_t tap_cfg0;
4958 int32_t ret;
4959
4960 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
4961
4962 if (ret == 0)
4963 {
4964 tap_cfg0.low_pass_on_6d = (uint8_t)val & 0x01U;
4965 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
4966 }
4967
4968 return ret;
4969 }
4970
4971 /**
4972 * @brief LPF2 filter on 6D (sixd) function selection.[get]
4973 *
4974 * @param ctx read / write interface definitions
4975 * @param val SIXD_FEED_ODR_DIV_2, SIXD_FEED_LOW_PASS,
4976 * @retval interface status (MANDATORY: return 0 -> no Error)
4977 *
4978 */
lsm6dsv16x_filt_sixd_feed_get(stmdev_ctx_t * ctx,lsm6dsv16x_filt_sixd_feed_t * val)4979 int32_t lsm6dsv16x_filt_sixd_feed_get(stmdev_ctx_t *ctx,
4980 lsm6dsv16x_filt_sixd_feed_t *val)
4981 {
4982 lsm6dsv16x_tap_cfg0_t tap_cfg0;
4983 int32_t ret;
4984
4985 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
4986 if (ret != 0) { return ret; }
4987
4988 switch (tap_cfg0.low_pass_on_6d)
4989 {
4990 case LSM6DSV16X_SIXD_FEED_ODR_DIV_2:
4991 *val = LSM6DSV16X_SIXD_FEED_ODR_DIV_2;
4992 break;
4993
4994 case LSM6DSV16X_SIXD_FEED_LOW_PASS:
4995 *val = LSM6DSV16X_SIXD_FEED_LOW_PASS;
4996 break;
4997
4998 default:
4999 *val = LSM6DSV16X_SIXD_FEED_ODR_DIV_2;
5000 break;
5001 }
5002
5003 return ret;
5004 }
5005
5006 /**
5007 * @brief Gyroscope digital LPF_EIS filter bandwidth selection.[set]
5008 *
5009 * @param ctx read / write interface definitions
5010 * @param val EIS_LP_NORMAL, EIS_LP_LIGHT,
5011 * @retval interface status (MANDATORY: return 0 -> no Error)
5012 *
5013 */
lsm6dsv16x_filt_gy_eis_lp_bandwidth_set(stmdev_ctx_t * ctx,lsm6dsv16x_filt_gy_eis_lp_bandwidth_t val)5014 int32_t lsm6dsv16x_filt_gy_eis_lp_bandwidth_set(stmdev_ctx_t *ctx,
5015 lsm6dsv16x_filt_gy_eis_lp_bandwidth_t val)
5016 {
5017 lsm6dsv16x_ctrl_eis_t ctrl_eis;
5018 int32_t ret;
5019
5020 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
5021
5022 if (ret == 0)
5023 {
5024 ctrl_eis.lpf_g_eis_bw = (uint8_t)val & 0x01U;
5025 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
5026 }
5027
5028 return ret;
5029 }
5030
5031 /**
5032 * @brief Gyroscope digital LPF_EIS filter bandwidth selection.[get]
5033 *
5034 * @param ctx read / write interface definitions
5035 * @param val EIS_LP_NORMAL, EIS_LP_LIGHT,
5036 * @retval interface status (MANDATORY: return 0 -> no Error)
5037 *
5038 */
lsm6dsv16x_filt_gy_eis_lp_bandwidth_get(stmdev_ctx_t * ctx,lsm6dsv16x_filt_gy_eis_lp_bandwidth_t * val)5039 int32_t lsm6dsv16x_filt_gy_eis_lp_bandwidth_get(stmdev_ctx_t *ctx,
5040 lsm6dsv16x_filt_gy_eis_lp_bandwidth_t *val)
5041 {
5042 lsm6dsv16x_ctrl_eis_t ctrl_eis;
5043 int32_t ret;
5044
5045 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
5046 if (ret != 0) { return ret; }
5047
5048 switch (ctrl_eis.lpf_g_eis_bw)
5049 {
5050 case LSM6DSV16X_EIS_LP_NORMAL:
5051 *val = LSM6DSV16X_EIS_LP_NORMAL;
5052 break;
5053
5054 case LSM6DSV16X_EIS_LP_LIGHT:
5055 *val = LSM6DSV16X_EIS_LP_LIGHT;
5056 break;
5057
5058 default:
5059 *val = LSM6DSV16X_EIS_LP_NORMAL;
5060 break;
5061 }
5062
5063 return ret;
5064 }
5065
5066 /**
5067 * @brief Gyroscope OIS digital LPF1 filter bandwidth selection. This function works also on OIS interface (SPI2_CTRL2_OIS = UI_CTRL2_OIS).[set]
5068 *
5069 * @param ctx read / write interface definitions
5070 * @param val OIS_GY_LP_NORMAL, OIS_GY_LP_STRONG, OIS_GY_LP_AGGRESSIVE, OIS_GY_LP_LIGHT,
5071 * @retval interface status (MANDATORY: return 0 -> no Error)
5072 *
5073 */
lsm6dsv16x_filt_gy_ois_lp_bandwidth_set(stmdev_ctx_t * ctx,lsm6dsv16x_filt_gy_ois_lp_bandwidth_t val)5074 int32_t lsm6dsv16x_filt_gy_ois_lp_bandwidth_set(stmdev_ctx_t *ctx,
5075 lsm6dsv16x_filt_gy_ois_lp_bandwidth_t val)
5076 {
5077 lsm6dsv16x_ui_ctrl2_ois_t ui_ctrl2_ois;
5078 int32_t ret;
5079
5080 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1);
5081
5082 if (ret == 0)
5083 {
5084 ui_ctrl2_ois.lpf1_g_ois_bw = (uint8_t)val & 0x03U;
5085 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1);
5086 }
5087
5088 return ret;
5089 }
5090
5091 /**
5092 * @brief Gyroscope OIS digital LPF1 filter bandwidth selection. This function works also on OIS interface (SPI2_CTRL2_OIS = UI_CTRL2_OIS).[get]
5093 *
5094 * @param ctx read / write interface definitions
5095 * @param val OIS_GY_LP_NORMAL, OIS_GY_LP_STRONG, OIS_GY_LP_AGGRESSIVE, OIS_GY_LP_LIGHT,
5096 * @retval interface status (MANDATORY: return 0 -> no Error)
5097 *
5098 */
lsm6dsv16x_filt_gy_ois_lp_bandwidth_get(stmdev_ctx_t * ctx,lsm6dsv16x_filt_gy_ois_lp_bandwidth_t * val)5099 int32_t lsm6dsv16x_filt_gy_ois_lp_bandwidth_get(stmdev_ctx_t *ctx,
5100 lsm6dsv16x_filt_gy_ois_lp_bandwidth_t *val)
5101 {
5102
5103 lsm6dsv16x_ui_ctrl2_ois_t ui_ctrl2_ois;
5104 int32_t ret;
5105
5106 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1);
5107 if (ret != 0) { return ret; }
5108
5109 switch (ui_ctrl2_ois.lpf1_g_ois_bw)
5110 {
5111 case LSM6DSV16X_OIS_GY_LP_NORMAL:
5112 *val = LSM6DSV16X_OIS_GY_LP_NORMAL;
5113 break;
5114
5115 case LSM6DSV16X_OIS_GY_LP_STRONG:
5116 *val = LSM6DSV16X_OIS_GY_LP_STRONG;
5117 break;
5118
5119 case LSM6DSV16X_OIS_GY_LP_AGGRESSIVE:
5120 *val = LSM6DSV16X_OIS_GY_LP_AGGRESSIVE;
5121 break;
5122
5123 case LSM6DSV16X_OIS_GY_LP_LIGHT:
5124 *val = LSM6DSV16X_OIS_GY_LP_LIGHT;
5125 break;
5126
5127 default:
5128 *val = LSM6DSV16X_OIS_GY_LP_NORMAL;
5129 break;
5130 }
5131
5132 return ret;
5133 }
5134
5135 /**
5136 * @brief Selects accelerometer OIS channel bandwidth. This function works also on OIS interface (SPI2_CTRL3_OIS = UI_CTRL3_OIS).[set]
5137 *
5138 * @param ctx read / write interface definitions
5139 * @param val OIS_XL_LP_ULTRA_LIGHT, OIS_XL_LP_VERY_LIGHT, OIS_XL_LP_LIGHT, OIS_XL_LP_NORMAL, OIS_XL_LP_STRONG, OIS_XL_LP_VERY_STRONG, OIS_XL_LP_AGGRESSIVE, OIS_XL_LP_XTREME,
5140 * @retval interface status (MANDATORY: return 0 -> no Error)
5141 *
5142 */
lsm6dsv16x_filt_xl_ois_lp_bandwidth_set(stmdev_ctx_t * ctx,lsm6dsv16x_filt_xl_ois_lp_bandwidth_t val)5143 int32_t lsm6dsv16x_filt_xl_ois_lp_bandwidth_set(stmdev_ctx_t *ctx,
5144 lsm6dsv16x_filt_xl_ois_lp_bandwidth_t val)
5145 {
5146 lsm6dsv16x_ui_ctrl3_ois_t ui_ctrl3_ois;
5147 int32_t ret;
5148
5149 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1);
5150
5151 if (ret == 0)
5152 {
5153 ui_ctrl3_ois.lpf_xl_ois_bw = (uint8_t)val & 0x07U;
5154 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1);
5155 }
5156
5157 return ret;
5158 }
5159
5160 /**
5161 * @brief Selects accelerometer OIS channel bandwidth. This function works also on OIS interface (SPI2_CTRL3_OIS = UI_CTRL3_OIS).[get]
5162 *
5163 * @param ctx read / write interface definitions
5164 * @param val OIS_XL_LP_ULTRA_LIGHT, OIS_XL_LP_VERY_LIGHT, OIS_XL_LP_LIGHT, OIS_XL_LP_NORMAL, OIS_XL_LP_STRONG, OIS_XL_LP_VERY_STRONG, OIS_XL_LP_AGGRESSIVE, OIS_XL_LP_XTREME,
5165 * @retval interface status (MANDATORY: return 0 -> no Error)
5166 *
5167 */
lsm6dsv16x_filt_xl_ois_lp_bandwidth_get(stmdev_ctx_t * ctx,lsm6dsv16x_filt_xl_ois_lp_bandwidth_t * val)5168 int32_t lsm6dsv16x_filt_xl_ois_lp_bandwidth_get(stmdev_ctx_t *ctx,
5169 lsm6dsv16x_filt_xl_ois_lp_bandwidth_t *val)
5170 {
5171 lsm6dsv16x_ui_ctrl3_ois_t ui_ctrl3_ois;
5172 int32_t ret;
5173
5174 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1);
5175 if (ret != 0) { return ret; }
5176
5177 switch (ui_ctrl3_ois.lpf_xl_ois_bw)
5178 {
5179 case LSM6DSV16X_OIS_XL_LP_ULTRA_LIGHT:
5180 *val = LSM6DSV16X_OIS_XL_LP_ULTRA_LIGHT;
5181 break;
5182
5183 case LSM6DSV16X_OIS_XL_LP_VERY_LIGHT:
5184 *val = LSM6DSV16X_OIS_XL_LP_VERY_LIGHT;
5185 break;
5186
5187 case LSM6DSV16X_OIS_XL_LP_LIGHT:
5188 *val = LSM6DSV16X_OIS_XL_LP_LIGHT;
5189 break;
5190
5191 case LSM6DSV16X_OIS_XL_LP_NORMAL:
5192 *val = LSM6DSV16X_OIS_XL_LP_NORMAL;
5193 break;
5194
5195 case LSM6DSV16X_OIS_XL_LP_STRONG:
5196 *val = LSM6DSV16X_OIS_XL_LP_STRONG;
5197 break;
5198
5199 case LSM6DSV16X_OIS_XL_LP_VERY_STRONG:
5200 *val = LSM6DSV16X_OIS_XL_LP_VERY_STRONG;
5201 break;
5202
5203 case LSM6DSV16X_OIS_XL_LP_AGGRESSIVE:
5204 *val = LSM6DSV16X_OIS_XL_LP_AGGRESSIVE;
5205 break;
5206
5207 case LSM6DSV16X_OIS_XL_LP_XTREME:
5208 *val = LSM6DSV16X_OIS_XL_LP_XTREME;
5209 break;
5210
5211 default:
5212 *val = LSM6DSV16X_OIS_XL_LP_ULTRA_LIGHT;
5213 break;
5214 }
5215
5216 return ret;
5217 }
5218
5219 /**
5220 * @}
5221 *
5222 */
5223
5224 /**
5225 * @defgroup Finite State Machine (FSM)
5226 * @brief This section groups all the functions that manage the
5227 * state_machine.
5228 * @{
5229 *
5230 */
5231
5232 /**
5233 * @brief Enables the control of the CTRL registers to FSM (FSM can change some configurations of the device autonomously).[set]
5234 *
5235 * @param ctx read / write interface definitions
5236 * @param val PROTECT_CTRL_REGS, WRITE_CTRL_REG,
5237 * @retval interface status (MANDATORY: return 0 -> no Error)
5238 *
5239 */
lsm6dsv16x_fsm_permission_set(stmdev_ctx_t * ctx,lsm6dsv16x_fsm_permission_t val)5240 int32_t lsm6dsv16x_fsm_permission_set(stmdev_ctx_t *ctx,
5241 lsm6dsv16x_fsm_permission_t val)
5242 {
5243 lsm6dsv16x_func_cfg_access_t func_cfg_access;
5244 int32_t ret;
5245
5246 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
5247
5248 if (ret == 0)
5249 {
5250 func_cfg_access.fsm_wr_ctrl_en = (uint8_t)val & 0x01U;
5251 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
5252 }
5253
5254 return ret;
5255 }
5256
5257 /**
5258 * @brief Enables the control of the CTRL registers to FSM (FSM can change some configurations of the device autonomously).[get]
5259 *
5260 * @param ctx read / write interface definitions
5261 * @param val PROTECT_CTRL_REGS, WRITE_CTRL_REG,
5262 * @retval interface status (MANDATORY: return 0 -> no Error)
5263 *
5264 */
lsm6dsv16x_fsm_permission_get(stmdev_ctx_t * ctx,lsm6dsv16x_fsm_permission_t * val)5265 int32_t lsm6dsv16x_fsm_permission_get(stmdev_ctx_t *ctx,
5266 lsm6dsv16x_fsm_permission_t *val)
5267 {
5268 lsm6dsv16x_func_cfg_access_t func_cfg_access;
5269 int32_t ret;
5270
5271 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
5272 if (ret != 0) { return ret; }
5273
5274 switch (func_cfg_access.fsm_wr_ctrl_en)
5275 {
5276 case LSM6DSV16X_PROTECT_CTRL_REGS:
5277 *val = LSM6DSV16X_PROTECT_CTRL_REGS;
5278 break;
5279
5280 case LSM6DSV16X_WRITE_CTRL_REG:
5281 *val = LSM6DSV16X_WRITE_CTRL_REG;
5282 break;
5283
5284 default:
5285 *val = LSM6DSV16X_PROTECT_CTRL_REGS;
5286 break;
5287 }
5288
5289 return ret;
5290 }
5291
5292 /**
5293 * @brief Get the FSM permission status
5294 *
5295 * @param ctx read / write interface definitions
5296 * @param val 0: All reg writable from std if - 1: some regs are under FSM control.
5297 * @retval interface status (MANDATORY: return 0 -> no Error)
5298 *
5299 */
lsm6dsv16x_fsm_permission_status(stmdev_ctx_t * ctx,uint8_t * val)5300 int32_t lsm6dsv16x_fsm_permission_status(stmdev_ctx_t *ctx, uint8_t *val)
5301 {
5302 lsm6dsv16x_ctrl_status_t ctrl_status;
5303 int32_t ret;
5304
5305 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL_STATUS, (uint8_t *)&ctrl_status, 1);
5306
5307 *val = ctrl_status.fsm_wr_ctrl_status;
5308
5309 return ret;
5310 }
5311
5312 /**
5313 * @brief Enable Finite State Machine (FSM) feature.[set]
5314 *
5315 * @param ctx read / write interface definitions
5316 * @param val Enable Finite State Machine (FSM) feature.
5317 * @retval interface status (MANDATORY: return 0 -> no Error)
5318 *
5319 */
lsm6dsv16x_fsm_mode_set(stmdev_ctx_t * ctx,lsm6dsv16x_fsm_mode_t val)5320 int32_t lsm6dsv16x_fsm_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_fsm_mode_t val)
5321 {
5322 lsm6dsv16x_emb_func_en_b_t emb_func_en_b;
5323 lsm6dsv16x_fsm_enable_t fsm_enable;
5324 int32_t ret;
5325
5326 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
5327 if (ret != 0) { return ret; }
5328
5329 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
5330 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FSM_ENABLE, (uint8_t *)&fsm_enable, 1);
5331 if (ret != 0) { goto exit; }
5332
5333 if ((val.fsm1_en | val.fsm2_en | val.fsm1_en | val.fsm1_en
5334 | val.fsm1_en | val.fsm2_en | val.fsm1_en | val.fsm1_en) == PROPERTY_ENABLE)
5335 {
5336 emb_func_en_b.fsm_en = PROPERTY_ENABLE;
5337 }
5338 else
5339 {
5340 emb_func_en_b.fsm_en = PROPERTY_DISABLE;
5341 }
5342
5343 fsm_enable.fsm1_en = val.fsm1_en;
5344 fsm_enable.fsm2_en = val.fsm2_en;
5345 fsm_enable.fsm3_en = val.fsm3_en;
5346 fsm_enable.fsm4_en = val.fsm4_en;
5347 fsm_enable.fsm5_en = val.fsm5_en;
5348 fsm_enable.fsm6_en = val.fsm6_en;
5349 fsm_enable.fsm7_en = val.fsm7_en;
5350 fsm_enable.fsm8_en = val.fsm8_en;
5351
5352 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FSM_ENABLE, (uint8_t *)&fsm_enable, 1);
5353 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
5354
5355 exit:
5356 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
5357
5358 return ret;
5359 }
5360
5361 /**
5362 * @brief Enable Finite State Machine (FSM) feature.[get]
5363 *
5364 * @param ctx read / write interface definitions
5365 * @param val Enable Finite State Machine (FSM) feature.
5366 * @retval interface status (MANDATORY: return 0 -> no Error)
5367 *
5368 */
lsm6dsv16x_fsm_mode_get(stmdev_ctx_t * ctx,lsm6dsv16x_fsm_mode_t * val)5369 int32_t lsm6dsv16x_fsm_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_fsm_mode_t *val)
5370 {
5371 lsm6dsv16x_fsm_enable_t fsm_enable;
5372 int32_t ret;
5373
5374 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
5375 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FSM_ENABLE, (uint8_t *)&fsm_enable, 1);
5376 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
5377 if (ret != 0) { return ret; }
5378
5379 val->fsm1_en = fsm_enable.fsm1_en;
5380 val->fsm2_en = fsm_enable.fsm2_en;
5381 val->fsm3_en = fsm_enable.fsm3_en;
5382 val->fsm4_en = fsm_enable.fsm4_en;
5383 val->fsm5_en = fsm_enable.fsm5_en;
5384 val->fsm6_en = fsm_enable.fsm6_en;
5385 val->fsm7_en = fsm_enable.fsm7_en;
5386 val->fsm8_en = fsm_enable.fsm8_en;
5387
5388 return ret;
5389 }
5390
5391 /**
5392 * @brief FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).[set]
5393 *
5394 * @param ctx read / write interface definitions
5395 * @param val FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).
5396 * @retval interface status (MANDATORY: return 0 -> no Error)
5397 *
5398 */
lsm6dsv16x_fsm_long_cnt_set(stmdev_ctx_t * ctx,uint16_t val)5399 int32_t lsm6dsv16x_fsm_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val)
5400 {
5401 uint8_t buff[2];
5402 int32_t ret;
5403
5404 buff[1] = (uint8_t)(val / 256U);
5405 buff[0] = (uint8_t)(val - (buff[1] * 256U));
5406
5407 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
5408 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FSM_LONG_COUNTER_L, (uint8_t *)&buff[0], 2);
5409 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
5410
5411 return ret;
5412 }
5413
5414 /**
5415 * @brief FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).[get]
5416 *
5417 * @param ctx read / write interface definitions
5418 * @param val FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).
5419 * @retval interface status (MANDATORY: return 0 -> no Error)
5420 *
5421 */
lsm6dsv16x_fsm_long_cnt_get(stmdev_ctx_t * ctx,uint16_t * val)5422 int32_t lsm6dsv16x_fsm_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val)
5423 {
5424 uint8_t buff[2];
5425 int32_t ret;
5426
5427 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
5428 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FSM_LONG_COUNTER_L, &buff[0], 2);
5429 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
5430 if (ret != 0) { return ret; }
5431
5432 *val = buff[1];
5433 *val = (*val * 256U) + buff[0];
5434
5435 return ret;
5436 }
5437
5438 /**
5439 * @brief FSM output registers[get]
5440 *
5441 * @param ctx read / write interface definitions
5442 * @param val FSM output registers
5443 * @retval interface status (MANDATORY: return 0 -> no Error)
5444 *
5445 */
lsm6dsv16x_fsm_out_get(stmdev_ctx_t * ctx,lsm6dsv16x_fsm_out_t * val)5446 int32_t lsm6dsv16x_fsm_out_get(stmdev_ctx_t *ctx, lsm6dsv16x_fsm_out_t *val)
5447 {
5448 int32_t ret;
5449
5450 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
5451 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FSM_OUTS1, (uint8_t *)val, 8);
5452 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
5453
5454 return ret;
5455 }
5456
5457 /**
5458 * @brief Finite State Machine Output Data Rate (ODR) configuration.[set]
5459 *
5460 * @param ctx read / write interface definitions
5461 * @param val FSM_15Hz, FSM_30Hz, FSM_60Hz, FSM_120Hz, FSM_240Hz, FSM_480Hz, FSM_960Hz,
5462 * @retval interface status (MANDATORY: return 0 -> no Error)
5463 *
5464 */
lsm6dsv16x_fsm_data_rate_set(stmdev_ctx_t * ctx,lsm6dsv16x_fsm_data_rate_t val)5465 int32_t lsm6dsv16x_fsm_data_rate_set(stmdev_ctx_t *ctx,
5466 lsm6dsv16x_fsm_data_rate_t val)
5467 {
5468 lsm6dsv16x_fsm_odr_t fsm_odr;
5469 int32_t ret;
5470
5471 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
5472 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FSM_ODR, (uint8_t *)&fsm_odr, 1);
5473 if (ret != 0) { goto exit; }
5474
5475 fsm_odr.fsm_odr = (uint8_t)val & 0x07U;
5476 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FSM_ODR, (uint8_t *)&fsm_odr, 1);
5477
5478 exit:
5479 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
5480
5481 return ret;
5482 }
5483
5484 /**
5485 * @brief Finite State Machine Output Data Rate (ODR) configuration.[get]
5486 *
5487 * @param ctx read / write interface definitions
5488 * @param val FSM_15Hz, FSM_30Hz, FSM_60Hz, FSM_120Hz, FSM_240Hz, FSM_480Hz, FSM_960Hz,
5489 * @retval interface status (MANDATORY: return 0 -> no Error)
5490 *
5491 */
lsm6dsv16x_fsm_data_rate_get(stmdev_ctx_t * ctx,lsm6dsv16x_fsm_data_rate_t * val)5492 int32_t lsm6dsv16x_fsm_data_rate_get(stmdev_ctx_t *ctx,
5493 lsm6dsv16x_fsm_data_rate_t *val)
5494 {
5495 lsm6dsv16x_fsm_odr_t fsm_odr;
5496 int32_t ret;
5497
5498 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
5499 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FSM_ODR, (uint8_t *)&fsm_odr, 1);
5500 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
5501 if (ret != 0) { return ret; }
5502
5503 switch (fsm_odr.fsm_odr)
5504 {
5505 case LSM6DSV16X_FSM_15Hz:
5506 *val = LSM6DSV16X_FSM_15Hz;
5507 break;
5508
5509 case LSM6DSV16X_FSM_30Hz:
5510 *val = LSM6DSV16X_FSM_30Hz;
5511 break;
5512
5513 case LSM6DSV16X_FSM_60Hz:
5514 *val = LSM6DSV16X_FSM_60Hz;
5515 break;
5516
5517 case LSM6DSV16X_FSM_120Hz:
5518 *val = LSM6DSV16X_FSM_120Hz;
5519 break;
5520
5521 case LSM6DSV16X_FSM_240Hz:
5522 *val = LSM6DSV16X_FSM_240Hz;
5523 break;
5524
5525 case LSM6DSV16X_FSM_480Hz:
5526 *val = LSM6DSV16X_FSM_480Hz;
5527 break;
5528
5529 case LSM6DSV16X_FSM_960Hz:
5530 *val = LSM6DSV16X_FSM_960Hz;
5531 break;
5532
5533 default:
5534 *val = LSM6DSV16X_FSM_15Hz;
5535 break;
5536 }
5537
5538 return ret;
5539 }
5540
5541 /*
5542 * Original conversion routines taken from: https://github.com/numpy/numpy
5543 *
5544 * uint16_t npy_floatbits_to_halfbits(uint32_t f);
5545 * uint16_t npy_float_to_half(float_t f);
5546 *
5547 * Released under BSD-3-Clause License
5548 */
npy_floatbits_to_halfbits(uint32_t f)5549 static uint16_t npy_floatbits_to_halfbits(uint32_t f)
5550 {
5551 uint32_t f_exp, f_sig;
5552 uint16_t h_sgn, h_exp, h_sig;
5553
5554 h_sgn = (uint16_t)((f & 0x80000000u) >> 16);
5555 f_exp = (f & 0x7f800000u);
5556
5557 /* Exponent overflow/NaN converts to signed inf/NaN */
5558 if (f_exp >= 0x47800000u)
5559 {
5560 if (f_exp == 0x7f800000u)
5561 {
5562 /* Inf or NaN */
5563 f_sig = (f & 0x007fffffu);
5564 if (f_sig != 0U)
5565 {
5566 /* NaN - propagate the flag in the significand... */
5567 uint16_t ret = (uint16_t)(0x7c00u + (f_sig >> 13));
5568 /* ...but make sure it stays a NaN */
5569 if (ret == 0x7c00u)
5570 {
5571 ret++;
5572 }
5573 return h_sgn + ret;
5574 }
5575 else
5576 {
5577 /* signed inf */
5578 return (uint16_t)(h_sgn + 0x7c00u);
5579 }
5580 }
5581 else
5582 {
5583 /* overflow to signed inf */
5584 #if NPY_HALF_GENERATE_OVERFLOW
5585 npy_set_floatstatus_overflow();
5586 #endif
5587 return (uint16_t)(h_sgn + 0x7c00u);
5588 }
5589 }
5590
5591 /* Exponent underflow converts to a subnormal half or signed zero */
5592 if (f_exp <= 0x38000000u)
5593 {
5594 /*
5595 * Signed zeros, subnormal floats, and floats with small
5596 * exponents all convert to signed zero half-floats.
5597 */
5598 if (f_exp < 0x33000000u)
5599 {
5600 #if NPY_HALF_GENERATE_UNDERFLOW
5601 /* If f != 0, it underflowed to 0 */
5602 if ((f & 0x7fffffff) != 0)
5603 {
5604 npy_set_floatstatus_underflow();
5605 }
5606 #endif
5607 return h_sgn;
5608 }
5609 /* Make the subnormal significand */
5610 f_exp >>= 23;
5611 f_sig = (0x00800000u + (f & 0x007fffffu));
5612 #if NPY_HALF_GENERATE_UNDERFLOW
5613 /* If it's not exactly represented, it underflowed */
5614 if ((f_sig & (((uint32_t)1 << (126 - f_exp)) - 1)) != 0)
5615 {
5616 npy_set_floatstatus_underflow();
5617 }
5618 #endif
5619 /*
5620 * Usually the significand is shifted by 13. For subnormals an
5621 * additional shift needs to occur. This shift is one for the largest
5622 * exponent giving a subnormal `f_exp = 0x38000000 >> 23 = 112`, which
5623 * offsets the new first bit. At most the shift can be 1+10 bits.
5624 */
5625 f_sig >>= (113U - f_exp);
5626 /* Handle rounding by adding 1 to the bit beyond half precision */
5627 #if NPY_HALF_ROUND_TIES_TO_EVEN
5628 /*
5629 * If the last bit in the half significand is 0 (already even), and
5630 * the remaining bit pattern is 1000...0, then we do not add one
5631 * to the bit after the half significand. However, the (113 - f_exp)
5632 * shift can lose up to 11 bits, so the || checks them in the original.
5633 * In all other cases, we can just add one.
5634 */
5635 if (((f_sig & 0x00003fffu) != 0x00001000u) || (f & 0x000007ffu))
5636 {
5637 f_sig += 0x00001000u;
5638 }
5639 #else
5640 f_sig += 0x00001000u;
5641 #endif
5642 h_sig = (uint16_t)(f_sig >> 13);
5643 /*
5644 * If the rounding causes a bit to spill into h_exp, it will
5645 * increment h_exp from zero to one and h_sig will be zero.
5646 * This is the correct result.
5647 */
5648 return (uint16_t)(h_sgn + h_sig);
5649 }
5650
5651 /* Regular case with no overflow or underflow */
5652 h_exp = (uint16_t)((f_exp - 0x38000000u) >> 13);
5653 /* Handle rounding by adding 1 to the bit beyond half precision */
5654 f_sig = (f & 0x007fffffu);
5655 #if NPY_HALF_ROUND_TIES_TO_EVEN
5656 /*
5657 * If the last bit in the half significand is 0 (already even), and
5658 * the remaining bit pattern is 1000...0, then we do not add one
5659 * to the bit after the half significand. In all other cases, we do.
5660 */
5661 if ((f_sig & 0x00003fffu) != 0x00001000u)
5662 {
5663 f_sig += 0x00001000u;
5664 }
5665 #else
5666 f_sig += 0x00001000u;
5667 #endif
5668 h_sig = (uint16_t)(f_sig >> 13);
5669 /*
5670 * If the rounding causes a bit to spill into h_exp, it will
5671 * increment h_exp by one and h_sig will be zero. This is the
5672 * correct result. h_exp may increment to 15, at greatest, in
5673 * which case the result overflows to a signed inf.
5674 */
5675 #if NPY_HALF_GENERATE_OVERFLOW
5676 h_sig += h_exp;
5677 if (h_sig == 0x7c00u)
5678 {
5679 npy_set_floatstatus_overflow();
5680 }
5681 return h_sgn + h_sig;
5682 #else
5683 return h_sgn + h_exp + h_sig;
5684 #endif
5685 }
5686
npy_float_to_half(float_t f)5687 static uint16_t npy_float_to_half(float_t f)
5688 {
5689 union
5690 {
5691 float_t f;
5692 uint32_t fbits;
5693 } conv;
5694 conv.f = f;
5695 return npy_floatbits_to_halfbits(conv.fbits);
5696 }
5697
5698 /**
5699 * @brief SFLP GBIAS value. The register value is expressed as half-precision
5700 * floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent
5701 * bits; F: 10 fraction bits).[set]
5702 *
5703 * @param ctx read / write interface definitions
5704 * @param val GBIAS x/y/z val.
5705 * @retval interface status (MANDATORY: return 0 -> no Error)
5706 *
5707 */
lsm6dsv16x_sflp_game_gbias_set(stmdev_ctx_t * ctx,lsm6dsv16x_sflp_gbias_t * val)5708 int32_t lsm6dsv16x_sflp_game_gbias_set(stmdev_ctx_t *ctx,
5709 lsm6dsv16x_sflp_gbias_t *val)
5710 {
5711 lsm6dsv16x_sflp_data_rate_t sflp_odr;
5712 lsm6dsv16x_emb_func_exec_status_t emb_func_sts;
5713 lsm6dsv16x_data_ready_t drdy;
5714 lsm6dsv16x_xl_full_scale_t xl_fs;
5715 lsm6dsv16x_ctrl10_t ctrl10;
5716 uint8_t master_config;
5717 uint8_t emb_func_en_saved[2];
5718 uint8_t conf_saved[2];
5719 uint8_t reg_zero[2] = {0x0, 0x0};
5720 uint16_t gbias_hf[3];
5721 float_t k = 0.005f;
5722 int16_t xl_data[3];
5723 int32_t data_tmp;
5724 uint8_t *data_ptr = (uint8_t *)&data_tmp;
5725 uint8_t i, j;
5726 int32_t ret;
5727
5728 ret = lsm6dsv16x_sflp_data_rate_get(ctx, &sflp_odr);
5729 if (ret != 0) { return ret; }
5730
5731 /* Calculate k factor */
5732 switch (sflp_odr)
5733 {
5734 default:
5735 case LSM6DSV16X_SFLP_15Hz:
5736 k = 0.04f;
5737 break;
5738 case LSM6DSV16X_SFLP_30Hz:
5739 k = 0.02f;
5740 break;
5741 case LSM6DSV16X_SFLP_60Hz:
5742 k = 0.01f;
5743 break;
5744 case LSM6DSV16X_SFLP_120Hz:
5745 k = 0.005f;
5746 break;
5747 case LSM6DSV16X_SFLP_240Hz:
5748 k = 0.0025f;
5749 break;
5750 case LSM6DSV16X_SFLP_480Hz:
5751 k = 0.00125f;
5752 break;
5753 }
5754
5755 /* compute gbias as half precision float in order to be put in embedded advanced feature register */
5756 gbias_hf[0] = npy_float_to_half(val->gbias_x * (3.14159265358979323846f / 180.0f) / k);
5757 gbias_hf[1] = npy_float_to_half(val->gbias_y * (3.14159265358979323846f / 180.0f) / k);
5758 gbias_hf[2] = npy_float_to_half(val->gbias_z * (3.14159265358979323846f / 180.0f) / k);
5759
5760 /* Save sensor configuration and set high-performance mode (if the sensor is in power-down mode, turn it on) */
5761 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL1, conf_saved, 2);
5762 ret += lsm6dsv16x_xl_mode_set(ctx, LSM6DSV16X_XL_HIGH_PERFORMANCE_MD);
5763 ret += lsm6dsv16x_gy_mode_set(ctx, LSM6DSV16X_GY_HIGH_PERFORMANCE_MD);
5764 if (((uint8_t)conf_saved[0] & 0x0FU) == (uint8_t)LSM6DSV16X_ODR_OFF)
5765 {
5766 ret += lsm6dsv16x_xl_data_rate_set(ctx, LSM6DSV16X_ODR_AT_120Hz);
5767 }
5768
5769 /* Make sure to turn the sensor-hub master off */
5770 ret += lsm6dsv16x_sh_master_get(ctx, &master_config);
5771 ret += lsm6dsv16x_sh_master_set(ctx, 0);
5772
5773 /* disable algos */
5774 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
5775 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, emb_func_en_saved, 2);
5776 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, reg_zero, 2);
5777 do
5778 {
5779 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EXEC_STATUS,
5780 (uint8_t *)&emb_func_sts, 1);
5781 } while (emb_func_sts.emb_func_endop != 1U);
5782 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
5783
5784 // enable gbias setting
5785 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL10, (uint8_t *)&ctrl10, 1);
5786 ctrl10.emb_func_debug = 1;
5787 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL10, (uint8_t *)&ctrl10, 1);
5788
5789 /* enable algos */
5790 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
5791 emb_func_en_saved[0] |= 0x02U; /* force SFLP GAME en */
5792 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, emb_func_en_saved,
5793 2);
5794 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
5795
5796 ret += lsm6dsv16x_xl_full_scale_get(ctx, &xl_fs);
5797
5798 /* Read XL data */
5799 do
5800 {
5801 ret += lsm6dsv16x_flag_data_ready_get(ctx, &drdy);
5802 } while (drdy.drdy_xl != 1U);
5803 ret += lsm6dsv16x_acceleration_raw_get(ctx, xl_data);
5804
5805 /* force sflp initialization */
5806 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK);
5807 for (i = 0; i < 3U; i++)
5808 {
5809 j = 0;
5810 data_tmp = (int32_t)xl_data[i];
5811 data_tmp <<= xl_fs; // shift based on current fs
5812 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SENSOR_HUB_1 + 3U * i,
5813 &data_ptr[j++], 1);
5814 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SENSOR_HUB_2 + 3U * i,
5815 &data_ptr[j++], 1);
5816 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SENSOR_HUB_3 + 3U * i, &data_ptr[j],
5817 1);
5818 }
5819 for (i = 0; i < 3U; i++)
5820 {
5821 j = 0;
5822 data_tmp = 0;
5823 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SENSOR_HUB_10 + 3U * i,
5824 &data_ptr[j++], 1);
5825 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SENSOR_HUB_11 + 3U * i,
5826 &data_ptr[j++], 1);
5827 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SENSOR_HUB_12 + 3U * i, &data_ptr[j],
5828 1);
5829 }
5830 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
5831
5832 // wait end_op (and at least 30 us)
5833 ctx->mdelay(1);
5834 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
5835 do
5836 {
5837 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EXEC_STATUS,
5838 (uint8_t *)&emb_func_sts, 1);
5839 } while (emb_func_sts.emb_func_endop != 1U);
5840 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
5841
5842 /* write gbias in embedded advanced features registers */
5843 ret += lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_SFLP_GAME_GBIASX_L,
5844 (uint8_t *)gbias_hf, 6);
5845
5846 /* reload previous sensor configuration */
5847 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL1, conf_saved, 2);
5848
5849 // disable gbias setting
5850 ctrl10.emb_func_debug = 0;
5851 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL10, (uint8_t *)&ctrl10, 1);
5852
5853 /* reload previous master configuration */
5854 ret += lsm6dsv16x_sh_master_set(ctx, master_config);
5855
5856 return ret;
5857 }
5858
5859 /**
5860 * @brief External sensor sensitivity value register for the Finite State Machine (r/w). This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Default value is 0x1624 (when using an external magnetometer this value corresponds to 0.0015 gauss/LSB).[set]
5861 *
5862 * @param ctx read / write interface definitions
5863 * @param val External sensor sensitivity value register for the Finite State Machine (r/w). This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Default value is 0x1624 (when using an external magnetometer this value corresponds to 0.0015 gauss/LSB).
5864 * @retval interface status (MANDATORY: return 0 -> no Error)
5865 *
5866 */
lsm6dsv16x_fsm_ext_sens_sensitivity_set(stmdev_ctx_t * ctx,uint16_t val)5867 int32_t lsm6dsv16x_fsm_ext_sens_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val)
5868 {
5869 uint8_t buff[2];
5870 int32_t ret;
5871
5872 buff[1] = (uint8_t)(val / 256U);
5873 buff[0] = (uint8_t)(val - (buff[1] * 256U));
5874 ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_FSM_EXT_SENSITIVITY_L, (uint8_t *)&buff[0], 2);
5875
5876 return ret;
5877 }
5878
5879 /**
5880 * @brief External sensor sensitivity value register for the Finite State Machine (r/w). This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Default value is 0x1624 (when using an external magnetometer this value corresponds to 0.0015 gauss/LSB).[get]
5881 *
5882 * @param ctx read / write interface definitions
5883 * @param val External sensor sensitivity value register for the Finite State Machine (r/w). This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Default value is 0x1624 (when using an external magnetometer this value corresponds to 0.0015 gauss/LSB).
5884 * @retval interface status (MANDATORY: return 0 -> no Error)
5885 *
5886 */
lsm6dsv16x_fsm_ext_sens_sensitivity_get(stmdev_ctx_t * ctx,uint16_t * val)5887 int32_t lsm6dsv16x_fsm_ext_sens_sensitivity_get(stmdev_ctx_t *ctx,
5888 uint16_t *val)
5889 {
5890 uint8_t buff[2];
5891 int32_t ret;
5892
5893 ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_FSM_EXT_SENSITIVITY_L, &buff[0], 2);
5894 if (ret != 0) { return ret; }
5895
5896 *val = buff[1];
5897 *val = (*val * 256U) + buff[0];
5898
5899 return ret;
5900 }
5901
5902 /**
5903 * @brief External sensor offsets (X,Y,Z). The values are expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[set]
5904 *
5905 * @param ctx read / write interface definitions
5906 * @param val External sensor offsets (X,Y,Z). The values are expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).
5907 * @retval interface status (MANDATORY: return 0 -> no Error)
5908 *
5909 */
lsm6dsv16x_fsm_ext_sens_offset_set(stmdev_ctx_t * ctx,lsm6dsv16x_xl_fsm_ext_sens_offset_t val)5910 int32_t lsm6dsv16x_fsm_ext_sens_offset_set(stmdev_ctx_t *ctx,
5911 lsm6dsv16x_xl_fsm_ext_sens_offset_t val)
5912 {
5913 uint8_t buff[6];
5914 int32_t ret;
5915
5916 buff[1] = (uint8_t)(val.x / 256U);
5917 buff[0] = (uint8_t)(val.x - (buff[1] * 256U));
5918 buff[3] = (uint8_t)(val.y / 256U);
5919 buff[2] = (uint8_t)(val.y - (buff[3] * 256U));
5920 buff[5] = (uint8_t)(val.z / 256U);
5921 buff[4] = (uint8_t)(val.z - (buff[5] * 256U));
5922 ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_FSM_EXT_OFFX_L, (uint8_t *)&buff[0], 6);
5923
5924 return ret;
5925 }
5926
5927 /**
5928 * @brief External sensor offsets (X,Y,Z). The values are expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[get]
5929 *
5930 * @param ctx read / write interface definitions
5931 * @param val External sensor offsets (X,Y,Z). The values are expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).
5932 * @retval interface status (MANDATORY: return 0 -> no Error)
5933 *
5934 */
lsm6dsv16x_fsm_ext_sens_offset_get(stmdev_ctx_t * ctx,lsm6dsv16x_xl_fsm_ext_sens_offset_t * val)5935 int32_t lsm6dsv16x_fsm_ext_sens_offset_get(stmdev_ctx_t *ctx,
5936 lsm6dsv16x_xl_fsm_ext_sens_offset_t *val)
5937 {
5938 uint8_t buff[6];
5939 int32_t ret;
5940
5941 ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_FSM_EXT_OFFX_L, &buff[0], 6);
5942 if (ret != 0) { return ret; }
5943
5944 val->x = buff[1];
5945 val->x = (val->x * 256U) + buff[0];
5946 val->y = buff[3];
5947 val->y = (val->y * 256U) + buff[2];
5948 val->z = buff[5];
5949 val->z = (val->z * 256U) + buff[4];
5950
5951 return ret;
5952 }
5953
5954 /**
5955 * @brief External sensor transformation matrix. The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[set]
5956 *
5957 * @param ctx read / write interface definitions
5958 * @param val External sensor transformation matrix. The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).
5959 * @retval interface status (MANDATORY: return 0 -> no Error)
5960 *
5961 */
lsm6dsv16x_fsm_ext_sens_matrix_set(stmdev_ctx_t * ctx,lsm6dsv16x_xl_fsm_ext_sens_matrix_t val)5962 int32_t lsm6dsv16x_fsm_ext_sens_matrix_set(stmdev_ctx_t *ctx,
5963 lsm6dsv16x_xl_fsm_ext_sens_matrix_t val)
5964 {
5965 uint8_t buff[12];
5966 int32_t ret;
5967
5968 buff[1] = (uint8_t)(val.xx / 256U);
5969 buff[0] = (uint8_t)(val.xx - (buff[1] * 256U));
5970 buff[3] = (uint8_t)(val.xy / 256U);
5971 buff[2] = (uint8_t)(val.xy - (buff[3] * 256U));
5972 buff[5] = (uint8_t)(val.xz / 256U);
5973 buff[4] = (uint8_t)(val.xz - (buff[5] * 256U));
5974 buff[7] = (uint8_t)(val.yy / 256U);
5975 buff[6] = (uint8_t)(val.yy - (buff[7] * 256U));
5976 buff[9] = (uint8_t)(val.yz / 256U);
5977 buff[8] = (uint8_t)(val.yz - (buff[9] * 256U));
5978 buff[11] = (uint8_t)(val.zz / 256U);
5979 buff[10] = (uint8_t)(val.zz - (buff[11] * 256U));
5980 ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_FSM_EXT_MATRIX_XX_L, (uint8_t *)&buff[0], 12);
5981
5982 return ret;
5983 }
5984
5985 /**
5986 * @brief External sensor transformation matrix. The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[get]
5987 *
5988 * @param ctx read / write interface definitions
5989 * @param val External sensor transformation matrix. The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).
5990 * @retval interface status (MANDATORY: return 0 -> no Error)
5991 *
5992 */
lsm6dsv16x_fsm_ext_sens_matrix_get(stmdev_ctx_t * ctx,lsm6dsv16x_xl_fsm_ext_sens_matrix_t * val)5993 int32_t lsm6dsv16x_fsm_ext_sens_matrix_get(stmdev_ctx_t *ctx,
5994 lsm6dsv16x_xl_fsm_ext_sens_matrix_t *val)
5995 {
5996 uint8_t buff[12];
5997 int32_t ret;
5998
5999 ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_FSM_EXT_MATRIX_XX_L, &buff[0], 12);
6000 if (ret != 0) { return ret; }
6001
6002 val->xx = buff[1];
6003 val->xx = (val->xx * 256U) + buff[0];
6004 val->xy = buff[3];
6005 val->xy = (val->xy * 256U) + buff[2];
6006 val->xz = buff[5];
6007 val->xz = (val->xz * 256U) + buff[4];
6008 val->yy = buff[7];
6009 val->yy = (val->yy * 256U) + buff[6];
6010 val->yz = buff[9];
6011 val->yz = (val->yz * 256U) + buff[8];
6012 val->zz = buff[11];
6013 val->zz = (val->zz * 256U) + buff[10];
6014
6015 return ret;
6016 }
6017
6018 /**
6019 * @brief External sensor z-axis coordinates rotation.[set]
6020 *
6021 * @param ctx read / write interface definitions
6022 * @param val Z_EQ_Y, Z_EQ_MIN_Y, Z_EQ_X, Z_EQ_MIN_X, Z_EQ_MIN_Z, Z_EQ_Z,
6023 * @retval interface status (MANDATORY: return 0 -> no Error)
6024 *
6025 */
lsm6dsv16x_fsm_ext_sens_z_orient_set(stmdev_ctx_t * ctx,lsm6dsv16x_fsm_ext_sens_z_orient_t val)6026 int32_t lsm6dsv16x_fsm_ext_sens_z_orient_set(stmdev_ctx_t *ctx,
6027 lsm6dsv16x_fsm_ext_sens_z_orient_t val)
6028 {
6029 lsm6dsv16x_ext_cfg_a_t ext_cfg_a;
6030 int32_t ret;
6031
6032 ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1);
6033 ext_cfg_a.ext_z_axis = (uint8_t)val & 0x07U;
6034 ret += lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1);
6035
6036 return ret;
6037 }
6038
6039 /**
6040 * @brief External sensor z-axis coordinates rotation.[get]
6041 *
6042 * @param ctx read / write interface definitions
6043 * @param val Z_EQ_Y, Z_EQ_MIN_Y, Z_EQ_X, Z_EQ_MIN_X, Z_EQ_MIN_Z, Z_EQ_Z,
6044 * @retval interface status (MANDATORY: return 0 -> no Error)
6045 *
6046 */
lsm6dsv16x_fsm_ext_sens_z_orient_get(stmdev_ctx_t * ctx,lsm6dsv16x_fsm_ext_sens_z_orient_t * val)6047 int32_t lsm6dsv16x_fsm_ext_sens_z_orient_get(stmdev_ctx_t *ctx,
6048 lsm6dsv16x_fsm_ext_sens_z_orient_t *val)
6049 {
6050 lsm6dsv16x_ext_cfg_a_t ext_cfg_a;
6051 int32_t ret;
6052
6053 ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1);
6054 if (ret != 0) { return ret; }
6055
6056 switch (ext_cfg_a.ext_z_axis)
6057 {
6058 case LSM6DSV16X_Z_EQ_Y:
6059 *val = LSM6DSV16X_Z_EQ_Y;
6060 break;
6061
6062 case LSM6DSV16X_Z_EQ_MIN_Y:
6063 *val = LSM6DSV16X_Z_EQ_MIN_Y;
6064 break;
6065
6066 case LSM6DSV16X_Z_EQ_X:
6067 *val = LSM6DSV16X_Z_EQ_X;
6068 break;
6069
6070 case LSM6DSV16X_Z_EQ_MIN_X:
6071 *val = LSM6DSV16X_Z_EQ_MIN_X;
6072 break;
6073
6074 case LSM6DSV16X_Z_EQ_MIN_Z:
6075 *val = LSM6DSV16X_Z_EQ_MIN_Z;
6076 break;
6077
6078 case LSM6DSV16X_Z_EQ_Z:
6079 *val = LSM6DSV16X_Z_EQ_Z;
6080 break;
6081
6082 default:
6083 *val = LSM6DSV16X_Z_EQ_Y;
6084 break;
6085 }
6086
6087 return ret;
6088 }
6089
6090 /**
6091 * @brief External sensor Y-axis coordinates rotation.[set]
6092 *
6093 * @param ctx read / write interface definitions
6094 * @param val Y_EQ_Y, Y_EQ_MIN_Y, Y_EQ_X, Y_EQ_MIN_X, Y_EQ_MIN_Z, Y_EQ_Z,
6095 * @retval interface status (MANDATORY: return 0 -> no Error)
6096 *
6097 */
lsm6dsv16x_fsm_ext_sens_y_orient_set(stmdev_ctx_t * ctx,lsm6dsv16x_fsm_ext_sens_y_orient_t val)6098 int32_t lsm6dsv16x_fsm_ext_sens_y_orient_set(stmdev_ctx_t *ctx,
6099 lsm6dsv16x_fsm_ext_sens_y_orient_t val)
6100 {
6101 lsm6dsv16x_ext_cfg_a_t ext_cfg_a;
6102 int32_t ret;
6103
6104 ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1);
6105 if (ret == 0)
6106 {
6107 ext_cfg_a.ext_y_axis = (uint8_t)val & 0x7U;
6108 ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1);
6109 }
6110
6111 return ret;
6112 }
6113
6114 /**
6115 * @brief External sensor Y-axis coordinates rotation.[get]
6116 *
6117 * @param ctx read / write interface definitions
6118 * @param val Y_EQ_Y, Y_EQ_MIN_Y, Y_EQ_X, Y_EQ_MIN_X, Y_EQ_MIN_Z, Y_EQ_Z,
6119 * @retval interface status (MANDATORY: return 0 -> no Error)
6120 *
6121 */
lsm6dsv16x_fsm_ext_sens_y_orient_get(stmdev_ctx_t * ctx,lsm6dsv16x_fsm_ext_sens_y_orient_t * val)6122 int32_t lsm6dsv16x_fsm_ext_sens_y_orient_get(stmdev_ctx_t *ctx,
6123 lsm6dsv16x_fsm_ext_sens_y_orient_t *val)
6124 {
6125 lsm6dsv16x_ext_cfg_a_t ext_cfg_a;
6126 int32_t ret;
6127
6128 ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1);
6129 if (ret != 0) { return ret; }
6130
6131 switch (ext_cfg_a.ext_y_axis)
6132 {
6133 case LSM6DSV16X_Y_EQ_Y:
6134 *val = LSM6DSV16X_Y_EQ_Y;
6135 break;
6136
6137 case LSM6DSV16X_Y_EQ_MIN_Y:
6138 *val = LSM6DSV16X_Y_EQ_MIN_Y;
6139 break;
6140
6141 case LSM6DSV16X_Y_EQ_X:
6142 *val = LSM6DSV16X_Y_EQ_X;
6143 break;
6144
6145 case LSM6DSV16X_Y_EQ_MIN_X:
6146 *val = LSM6DSV16X_Y_EQ_MIN_X;
6147 break;
6148
6149 case LSM6DSV16X_Y_EQ_MIN_Z:
6150 *val = LSM6DSV16X_Y_EQ_MIN_Z;
6151 break;
6152
6153 case LSM6DSV16X_Y_EQ_Z:
6154 *val = LSM6DSV16X_Y_EQ_Z;
6155 break;
6156
6157 default:
6158 *val = LSM6DSV16X_Y_EQ_Y;
6159 break;
6160 }
6161
6162 return ret;
6163 }
6164
6165 /**
6166 * @brief External sensor X-axis coordinates rotation.[set]
6167 *
6168 * @param ctx read / write interface definitions
6169 * @param val X_EQ_Y, X_EQ_MIN_Y, X_EQ_X, X_EQ_MIN_X, X_EQ_MIN_Z, X_EQ_Z,
6170 * @retval interface status (MANDATORY: return 0 -> no Error)
6171 *
6172 */
lsm6dsv16x_fsm_ext_sens_x_orient_set(stmdev_ctx_t * ctx,lsm6dsv16x_fsm_ext_sens_x_orient_t val)6173 int32_t lsm6dsv16x_fsm_ext_sens_x_orient_set(stmdev_ctx_t *ctx,
6174 lsm6dsv16x_fsm_ext_sens_x_orient_t val)
6175 {
6176 lsm6dsv16x_ext_cfg_b_t ext_cfg_b;
6177 int32_t ret;
6178
6179 ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EXT_CFG_B, (uint8_t *)&ext_cfg_b, 1);
6180 if (ret == 0)
6181 {
6182 ext_cfg_b.ext_x_axis = (uint8_t)val & 0x7U;
6183 ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_EXT_CFG_B, (uint8_t *)&ext_cfg_b, 1);
6184 }
6185
6186 return ret;
6187 }
6188
6189 /**
6190 * @brief External sensor X-axis coordinates rotation.[get]
6191 *
6192 * @param ctx read / write interface definitions
6193 * @param val X_EQ_Y, X_EQ_MIN_Y, X_EQ_X, X_EQ_MIN_X, X_EQ_MIN_Z, X_EQ_Z,
6194 * @retval interface status (MANDATORY: return 0 -> no Error)
6195 *
6196 */
lsm6dsv16x_fsm_ext_sens_x_orient_get(stmdev_ctx_t * ctx,lsm6dsv16x_fsm_ext_sens_x_orient_t * val)6197 int32_t lsm6dsv16x_fsm_ext_sens_x_orient_get(stmdev_ctx_t *ctx,
6198 lsm6dsv16x_fsm_ext_sens_x_orient_t *val)
6199 {
6200 lsm6dsv16x_ext_cfg_b_t ext_cfg_b;
6201 int32_t ret;
6202
6203 ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EXT_CFG_B, (uint8_t *)&ext_cfg_b, 1);
6204 if (ret != 0) { return ret; }
6205
6206 switch (ext_cfg_b.ext_x_axis)
6207 {
6208 case LSM6DSV16X_X_EQ_Y:
6209 *val = LSM6DSV16X_X_EQ_Y;
6210 break;
6211
6212 case LSM6DSV16X_X_EQ_MIN_Y:
6213 *val = LSM6DSV16X_X_EQ_MIN_Y;
6214 break;
6215
6216 case LSM6DSV16X_X_EQ_X:
6217 *val = LSM6DSV16X_X_EQ_X;
6218 break;
6219
6220 case LSM6DSV16X_X_EQ_MIN_X:
6221 *val = LSM6DSV16X_X_EQ_MIN_X;
6222 break;
6223
6224 case LSM6DSV16X_X_EQ_MIN_Z:
6225 *val = LSM6DSV16X_X_EQ_MIN_Z;
6226 break;
6227
6228 case LSM6DSV16X_X_EQ_Z:
6229 *val = LSM6DSV16X_X_EQ_Z;
6230 break;
6231
6232 default:
6233 *val = LSM6DSV16X_X_EQ_Y;
6234 break;
6235 }
6236
6237 return ret;
6238 }
6239
6240 /**
6241 * @brief FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.[set]
6242 *
6243 * @param ctx read / write interface definitions
6244 * @param val FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.
6245 * @retval interface status (MANDATORY: return 0 -> no Error)
6246 *
6247 */
lsm6dsv16x_fsm_long_cnt_timeout_set(stmdev_ctx_t * ctx,uint16_t val)6248 int32_t lsm6dsv16x_fsm_long_cnt_timeout_set(stmdev_ctx_t *ctx, uint16_t val)
6249 {
6250 uint8_t buff[2];
6251 int32_t ret;
6252
6253 buff[1] = (uint8_t)(val / 256U);
6254 buff[0] = (uint8_t)(val - (buff[1] * 256U));
6255 ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_FSM_LC_TIMEOUT_L, (uint8_t *)&buff[0], 2);
6256
6257 return ret;
6258 }
6259
6260 /**
6261 * @brief FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.[get]
6262 *
6263 * @param ctx read / write interface definitions
6264 * @param val FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.
6265 * @retval interface status (MANDATORY: return 0 -> no Error)
6266 *
6267 */
lsm6dsv16x_fsm_long_cnt_timeout_get(stmdev_ctx_t * ctx,uint16_t * val)6268 int32_t lsm6dsv16x_fsm_long_cnt_timeout_get(stmdev_ctx_t *ctx, uint16_t *val)
6269 {
6270 uint8_t buff[2];
6271 int32_t ret;
6272
6273 ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_FSM_LC_TIMEOUT_L, &buff[0], 2);
6274 if (ret != 0) { return ret; }
6275
6276 *val = buff[1];
6277 *val = (*val * 256U) + buff[0];
6278
6279 return ret;
6280 }
6281
6282 /**
6283 * @brief FSM number of programs.[set]
6284 *
6285 * @param ctx read / write interface definitions
6286 * @param val FSM number of programs.
6287 * @retval interface status (MANDATORY: return 0 -> no Error)
6288 *
6289 */
lsm6dsv16x_fsm_number_of_programs_set(stmdev_ctx_t * ctx,uint8_t val)6290 int32_t lsm6dsv16x_fsm_number_of_programs_set(stmdev_ctx_t *ctx, uint8_t val)
6291 {
6292 lsm6dsv16x_fsm_programs_t fsm_programs;
6293 int32_t ret;
6294
6295 ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1);
6296 if (ret == 0)
6297 {
6298 fsm_programs.fsm_n_prog = val;
6299 ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1);
6300 }
6301
6302 return ret;
6303 }
6304
6305 /**
6306 * @brief FSM number of programs.[get]
6307 *
6308 * @param ctx read / write interface definitions
6309 * @param val FSM number of programs.
6310 * @retval interface status (MANDATORY: return 0 -> no Error)
6311 *
6312 */
lsm6dsv16x_fsm_number_of_programs_get(stmdev_ctx_t * ctx,uint8_t * val)6313 int32_t lsm6dsv16x_fsm_number_of_programs_get(stmdev_ctx_t *ctx, uint8_t *val)
6314 {
6315 lsm6dsv16x_fsm_programs_t fsm_programs;
6316 int32_t ret;
6317
6318 ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1);
6319 *val = fsm_programs.fsm_n_prog;
6320
6321 return ret;
6322 }
6323
6324 /**
6325 * @brief FSM start address. First available address is 0x35C.[set]
6326 *
6327 * @param ctx read / write interface definitions
6328 * @param val FSM start address. First available address is 0x35C.
6329 * @retval interface status (MANDATORY: return 0 -> no Error)
6330 *
6331 */
lsm6dsv16x_fsm_start_address_set(stmdev_ctx_t * ctx,uint16_t val)6332 int32_t lsm6dsv16x_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val)
6333 {
6334 uint8_t buff[2];
6335 int32_t ret;
6336
6337 buff[1] = (uint8_t)(val / 256U);
6338 buff[0] = (uint8_t)(val - (buff[1] * 256U));
6339 ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_FSM_START_ADD_L, (uint8_t *)&buff[0], 2);
6340
6341 return ret;
6342 }
6343
6344 /**
6345 * @brief FSM start address. First available address is 0x35C.[get]
6346 *
6347 * @param ctx read / write interface definitions
6348 * @param val FSM start address. First available address is 0x35C.
6349 * @retval interface status (MANDATORY: return 0 -> no Error)
6350 *
6351 */
lsm6dsv16x_fsm_start_address_get(stmdev_ctx_t * ctx,uint16_t * val)6352 int32_t lsm6dsv16x_fsm_start_address_get(stmdev_ctx_t *ctx, uint16_t *val)
6353 {
6354 uint8_t buff[2];
6355 int32_t ret;
6356
6357 ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_FSM_START_ADD_L, &buff[0], 2);
6358 if (ret != 0) { return ret; }
6359
6360 *val = buff[1];
6361 *val = (*val * 256U) + buff[0];
6362
6363 return ret;
6364 }
6365
6366 /**
6367 * @}
6368 *
6369 */
6370
6371 /**
6372 * @defgroup Free fall
6373 * @brief This section group all the functions concerning the free
6374 * fall detection.
6375 * @{
6376 *
6377 */
6378
6379 /**
6380 * @brief Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time[set]
6381 *
6382 * @param ctx read / write interface definitions
6383 * @param val Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time
6384 * @retval interface status (MANDATORY: return 0 -> no Error)
6385 *
6386 */
lsm6dsv16x_ff_time_windows_set(stmdev_ctx_t * ctx,uint8_t val)6387 int32_t lsm6dsv16x_ff_time_windows_set(stmdev_ctx_t *ctx, uint8_t val)
6388 {
6389 lsm6dsv16x_wake_up_dur_t wake_up_dur;
6390 lsm6dsv16x_free_fall_t free_fall;
6391 int32_t ret;
6392
6393 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
6394 wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5;
6395 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
6396 if (ret != 0) { return ret; }
6397
6398 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FREE_FALL, (uint8_t *)&free_fall, 1);
6399 free_fall.ff_dur = (uint8_t)val & 0x1FU;
6400 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FREE_FALL, (uint8_t *)&free_fall, 1);
6401
6402 return ret;
6403 }
6404
6405 /**
6406 * @brief Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time[get]
6407 *
6408 * @param ctx read / write interface definitions
6409 * @param val Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time
6410 * @retval interface status (MANDATORY: return 0 -> no Error)
6411 *
6412 */
lsm6dsv16x_ff_time_windows_get(stmdev_ctx_t * ctx,uint8_t * val)6413 int32_t lsm6dsv16x_ff_time_windows_get(stmdev_ctx_t *ctx, uint8_t *val)
6414 {
6415 lsm6dsv16x_wake_up_dur_t wake_up_dur;
6416 lsm6dsv16x_free_fall_t free_fall;
6417 int32_t ret;
6418
6419 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
6420 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FREE_FALL, (uint8_t *)&free_fall, 1);
6421
6422 *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
6423
6424 return ret;
6425 }
6426
6427 /**
6428 * @brief Free fall threshold setting.[set]
6429 *
6430 * @param ctx read / write interface definitions
6431 * @param val 156_mg, 219_mg, 250_mg, 312_mg, 344_mg, 406_mg, 469_mg, 500_mg,
6432 * @retval interface status (MANDATORY: return 0 -> no Error)
6433 *
6434 */
lsm6dsv16x_ff_thresholds_set(stmdev_ctx_t * ctx,lsm6dsv16x_ff_thresholds_t val)6435 int32_t lsm6dsv16x_ff_thresholds_set(stmdev_ctx_t *ctx,
6436 lsm6dsv16x_ff_thresholds_t val)
6437 {
6438 lsm6dsv16x_free_fall_t free_fall;
6439 int32_t ret;
6440
6441 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FREE_FALL, (uint8_t *)&free_fall, 1);
6442 if (ret == 0)
6443 {
6444 free_fall.ff_ths = (uint8_t)val & 0x7U;
6445 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FREE_FALL, (uint8_t *)&free_fall, 1);
6446 }
6447
6448 return ret;
6449 }
6450
6451 /**
6452 * @brief Free fall threshold setting.[get]
6453 *
6454 * @param ctx read / write interface definitions
6455 * @param val 156_mg, 219_mg, 250_mg, 312_mg, 344_mg, 406_mg, 469_mg, 500_mg,
6456 * @retval interface status (MANDATORY: return 0 -> no Error)
6457 *
6458 */
lsm6dsv16x_ff_thresholds_get(stmdev_ctx_t * ctx,lsm6dsv16x_ff_thresholds_t * val)6459 int32_t lsm6dsv16x_ff_thresholds_get(stmdev_ctx_t *ctx,
6460 lsm6dsv16x_ff_thresholds_t *val)
6461 {
6462 lsm6dsv16x_free_fall_t free_fall;
6463 int32_t ret;
6464
6465 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FREE_FALL, (uint8_t *)&free_fall, 1);
6466 if (ret != 0) { return ret; }
6467
6468 switch (free_fall.ff_ths)
6469 {
6470 case LSM6DSV16X_156_mg:
6471 *val = LSM6DSV16X_156_mg;
6472 break;
6473
6474 case LSM6DSV16X_219_mg:
6475 *val = LSM6DSV16X_219_mg;
6476 break;
6477
6478 case LSM6DSV16X_250_mg:
6479 *val = LSM6DSV16X_250_mg;
6480 break;
6481
6482 case LSM6DSV16X_312_mg:
6483 *val = LSM6DSV16X_312_mg;
6484 break;
6485
6486 case LSM6DSV16X_344_mg:
6487 *val = LSM6DSV16X_344_mg;
6488 break;
6489
6490 case LSM6DSV16X_406_mg:
6491 *val = LSM6DSV16X_406_mg;
6492 break;
6493
6494 case LSM6DSV16X_469_mg:
6495 *val = LSM6DSV16X_469_mg;
6496 break;
6497
6498 case LSM6DSV16X_500_mg:
6499 *val = LSM6DSV16X_500_mg;
6500 break;
6501
6502 default:
6503 *val = LSM6DSV16X_156_mg;
6504 break;
6505 }
6506
6507 return ret;
6508 }
6509
6510 /**
6511 * @}
6512 *
6513 */
6514
6515 /**
6516 * @defgroup Machine Learning Core (MLC)
6517 * @brief This section group all the functions concerning the
6518 * usage of Machine Learning Core
6519 * @{
6520 *
6521 */
6522
6523 /**
6524 * @brief It enables Machine Learning Core feature (MLC). When the Machine Learning Core is enabled the Finite State Machine (FSM) programs are executed before executing the MLC algorithms.[set]
6525 *
6526 * @param ctx read / write interface definitions
6527 * @param val MLC_OFF, MLC_ON, MLC_BEFORE_FSM,
6528 * @retval interface status (MANDATORY: return 0 -> no Error)
6529 *
6530 */
lsm6dsv16x_mlc_set(stmdev_ctx_t * ctx,lsm6dsv16x_mlc_mode_t val)6531 int32_t lsm6dsv16x_mlc_set(stmdev_ctx_t *ctx, lsm6dsv16x_mlc_mode_t val)
6532 {
6533 lsm6dsv16x_emb_func_en_b_t emb_en_b;
6534 lsm6dsv16x_emb_func_en_a_t emb_en_a;
6535 int32_t ret;
6536
6537 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
6538 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1);
6539 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1);
6540 if (ret != 0) { goto exit; }
6541
6542 switch(val)
6543 {
6544 case LSM6DSV16X_MLC_OFF:
6545 emb_en_a.mlc_before_fsm_en = 0;
6546 emb_en_b.mlc_en = 0;
6547 break;
6548 case LSM6DSV16X_MLC_ON:
6549 emb_en_a.mlc_before_fsm_en = 0;
6550 emb_en_b.mlc_en = 1;
6551 break;
6552 case LSM6DSV16X_MLC_ON_BEFORE_FSM:
6553 emb_en_a.mlc_before_fsm_en = 1;
6554 emb_en_b.mlc_en = 0;
6555 break;
6556 default:
6557 break;
6558 }
6559
6560 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1);
6561 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1);
6562
6563 exit:
6564 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
6565
6566 return ret;
6567 }
6568
6569 /**
6570 * @brief It enables Machine Learning Core feature (MLC). When the Machine Learning Core is enabled the Finite State Machine (FSM) programs are executed before executing the MLC algorithms.[get]
6571 *
6572 * @param ctx read / write interface definitions
6573 * @param val MLC_OFF, MLC_ON, MLC_BEFORE_FSM,
6574 * @retval interface status (MANDATORY: return 0 -> no Error)
6575 *
6576 */
lsm6dsv16x_mlc_get(stmdev_ctx_t * ctx,lsm6dsv16x_mlc_mode_t * val)6577 int32_t lsm6dsv16x_mlc_get(stmdev_ctx_t *ctx, lsm6dsv16x_mlc_mode_t *val)
6578 {
6579 lsm6dsv16x_emb_func_en_b_t emb_en_b;
6580 lsm6dsv16x_emb_func_en_a_t emb_en_a;
6581 int32_t ret;
6582
6583 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
6584 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1);
6585 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1);
6586 if (ret != 0) { goto exit; }
6587
6588 if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 0U)
6589 {
6590 *val = LSM6DSV16X_MLC_OFF;
6591 }
6592 else if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 1U)
6593 {
6594 *val = LSM6DSV16X_MLC_ON;
6595 }
6596 else if (emb_en_a.mlc_before_fsm_en == 1U)
6597 {
6598 *val = LSM6DSV16X_MLC_ON_BEFORE_FSM;
6599 }
6600 else
6601 {
6602 /* Do nothing */
6603 }
6604
6605 exit:
6606 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
6607
6608 return ret;
6609 }
6610
6611 /**
6612 * @brief Machine Learning Core Output Data Rate (ODR) configuration.[set]
6613 *
6614 * @param ctx read / write interface definitions
6615 * @param val MLC_15Hz, MLC_30Hz, MLC_60Hz, MLC_120Hz, MLC_240Hz, MLC_480Hz, MLC_960Hz,
6616 * @retval interface status (MANDATORY: return 0 -> no Error)
6617 *
6618 */
lsm6dsv16x_mlc_data_rate_set(stmdev_ctx_t * ctx,lsm6dsv16x_mlc_data_rate_t val)6619 int32_t lsm6dsv16x_mlc_data_rate_set(stmdev_ctx_t *ctx,
6620 lsm6dsv16x_mlc_data_rate_t val)
6621 {
6622 lsm6dsv16x_mlc_odr_t mlc_odr;
6623 int32_t ret;
6624
6625 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
6626 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MLC_ODR, (uint8_t *)&mlc_odr, 1);
6627 if (ret != 0) { goto exit; }
6628
6629 mlc_odr.mlc_odr = (uint8_t)val & 0x07U;
6630 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_MLC_ODR, (uint8_t *)&mlc_odr, 1);
6631
6632 exit:
6633 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
6634
6635 return ret;
6636 }
6637
6638 /**
6639 * @brief Machine Learning Core Output Data Rate (ODR) configuration.[get]
6640 *
6641 * @param ctx read / write interface definitions
6642 * @param val MLC_15Hz, MLC_30Hz, MLC_60Hz, MLC_120Hz, MLC_240Hz, MLC_480Hz, MLC_960Hz,
6643 * @retval interface status (MANDATORY: return 0 -> no Error)
6644 *
6645 */
lsm6dsv16x_mlc_data_rate_get(stmdev_ctx_t * ctx,lsm6dsv16x_mlc_data_rate_t * val)6646 int32_t lsm6dsv16x_mlc_data_rate_get(stmdev_ctx_t *ctx,
6647 lsm6dsv16x_mlc_data_rate_t *val)
6648 {
6649 lsm6dsv16x_mlc_odr_t mlc_odr;
6650 int32_t ret;
6651
6652 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
6653 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MLC_ODR, (uint8_t *)&mlc_odr, 1);
6654 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
6655 if (ret != 0) { return ret; }
6656
6657 switch (mlc_odr.mlc_odr)
6658 {
6659 case LSM6DSV16X_MLC_15Hz:
6660 *val = LSM6DSV16X_MLC_15Hz;
6661 break;
6662
6663 case LSM6DSV16X_MLC_30Hz:
6664 *val = LSM6DSV16X_MLC_30Hz;
6665 break;
6666
6667 case LSM6DSV16X_MLC_60Hz:
6668 *val = LSM6DSV16X_MLC_60Hz;
6669 break;
6670
6671 case LSM6DSV16X_MLC_120Hz:
6672 *val = LSM6DSV16X_MLC_120Hz;
6673 break;
6674
6675 case LSM6DSV16X_MLC_240Hz:
6676 *val = LSM6DSV16X_MLC_240Hz;
6677 break;
6678
6679 case LSM6DSV16X_MLC_480Hz:
6680 *val = LSM6DSV16X_MLC_480Hz;
6681 break;
6682
6683 case LSM6DSV16X_MLC_960Hz:
6684 *val = LSM6DSV16X_MLC_960Hz;
6685 break;
6686
6687 default:
6688 *val = LSM6DSV16X_MLC_15Hz;
6689 break;
6690 }
6691
6692 return ret;
6693 }
6694
6695 /**
6696 * @brief Output value of all MLC decision trees.[get]
6697 *
6698 * @param ctx read / write interface definitions
6699 * @param val Output value of all MLC decision trees.
6700 * @retval interface status (MANDATORY: return 0 -> no Error)
6701 *
6702 */
lsm6dsv16x_mlc_out_get(stmdev_ctx_t * ctx,lsm6dsv16x_mlc_out_t * val)6703 int32_t lsm6dsv16x_mlc_out_get(stmdev_ctx_t *ctx, lsm6dsv16x_mlc_out_t *val)
6704 {
6705 int32_t ret;
6706
6707 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
6708 if (ret == 0)
6709 {
6710 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MLC1_SRC, (uint8_t *)val, 4);
6711 }
6712 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
6713
6714 return ret;
6715 }
6716
6717 /**
6718 * @brief External sensor sensitivity value register for the Machine Learning Core. This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).Default value is 0x3C00 (when using an external magnetometer this value corresponds to 1 gauss/LSB).[set]
6719 *
6720 * @param ctx read / write interface definitions
6721 * @param val External sensor sensitivity value register for the Machine Learning Core. This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).Default value is 0x3C00 (when using an external magnetometer this value corresponds to 1 gauss/LSB).
6722 * @retval interface status (MANDATORY: return 0 -> no Error)
6723 *
6724 */
lsm6dsv16x_mlc_ext_sens_sensitivity_set(stmdev_ctx_t * ctx,uint16_t val)6725 int32_t lsm6dsv16x_mlc_ext_sens_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val)
6726 {
6727 uint8_t buff[2];
6728 int32_t ret;
6729
6730 buff[1] = (uint8_t)(val / 256U);
6731 buff[0] = (uint8_t)(val - (buff[1] * 256U));
6732
6733 ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_MLC_EXT_SENSITIVITY_L, (uint8_t *)&buff[0], 2);
6734
6735 return ret;
6736 }
6737
6738 /**
6739 * @brief External sensor sensitivity value register for the Machine Learning Core. This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).Default value is 0x3C00 (when using an external magnetometer this value corresponds to 1 gauss/LSB).[get]
6740 *
6741 * @param ctx read / write interface definitions
6742 * @param val External sensor sensitivity value register for the Machine Learning Core. This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).Default value is 0x3C00 (when using an external magnetometer this value corresponds to 1 gauss/LSB).
6743 * @retval interface status (MANDATORY: return 0 -> no Error)
6744 *
6745 */
lsm6dsv16x_mlc_ext_sens_sensitivity_get(stmdev_ctx_t * ctx,uint16_t * val)6746 int32_t lsm6dsv16x_mlc_ext_sens_sensitivity_get(stmdev_ctx_t *ctx,
6747 uint16_t *val)
6748 {
6749 uint8_t buff[2];
6750 int32_t ret;
6751
6752 ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_MLC_EXT_SENSITIVITY_L, &buff[0], 2);
6753 if (ret != 0) { return ret; }
6754
6755 *val = buff[1];
6756 *val = (*val * 256U) + buff[0];
6757
6758 return ret;
6759 }
6760
6761 /**
6762 * @}
6763 *
6764 */
6765
6766 /**
6767 * @defgroup Optical Image Stabilization (OIS)
6768 * @brief This section groups all the functions concerning
6769 * Optical Image Stabilization (OIS).
6770 * @{
6771 *
6772 */
6773
6774 /**
6775 * @brief Enable the full control of OIS configurations from the UI (User Interface).[set]
6776 *
6777 * @param ctx read / write interface definitions
6778 * @param val OIS_CTRL_FROM_OIS, OIS_CTRL_FROM_UI,
6779 * @retval interface status (MANDATORY: return 0 -> no Error)
6780 *
6781 */
lsm6dsv16x_ois_ctrl_mode_set(stmdev_ctx_t * ctx,lsm6dsv16x_ois_ctrl_mode_t val)6782 int32_t lsm6dsv16x_ois_ctrl_mode_set(stmdev_ctx_t *ctx,
6783 lsm6dsv16x_ois_ctrl_mode_t val)
6784 {
6785 lsm6dsv16x_func_cfg_access_t func_cfg_access;
6786 int32_t ret;
6787
6788 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
6789 if (ret == 0)
6790 {
6791 func_cfg_access.ois_ctrl_from_ui = (uint8_t)val & 0x1U;
6792 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
6793 }
6794
6795 return ret;
6796 }
6797
6798 /**
6799 * @brief Enable the full control of OIS configurations from the UI (User Interface).[get]
6800 *
6801 * @param ctx read / write interface definitions
6802 * @param val OIS_CTRL_FROM_OIS, OIS_CTRL_FROM_UI,
6803 * @retval interface status (MANDATORY: return 0 -> no Error)
6804 *
6805 */
lsm6dsv16x_ois_ctrl_mode_get(stmdev_ctx_t * ctx,lsm6dsv16x_ois_ctrl_mode_t * val)6806 int32_t lsm6dsv16x_ois_ctrl_mode_get(stmdev_ctx_t *ctx,
6807 lsm6dsv16x_ois_ctrl_mode_t *val)
6808 {
6809 lsm6dsv16x_func_cfg_access_t func_cfg_access;
6810 int32_t ret;
6811
6812 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
6813 if (ret != 0) { return ret; }
6814
6815 switch (func_cfg_access.ois_ctrl_from_ui)
6816 {
6817 case LSM6DSV16X_OIS_CTRL_FROM_OIS:
6818 *val = LSM6DSV16X_OIS_CTRL_FROM_OIS;
6819 break;
6820
6821 case LSM6DSV16X_OIS_CTRL_FROM_UI:
6822 *val = LSM6DSV16X_OIS_CTRL_FROM_UI;
6823 break;
6824
6825 default:
6826 *val = LSM6DSV16X_OIS_CTRL_FROM_OIS;
6827 break;
6828 }
6829
6830 return ret;
6831 }
6832
6833 /**
6834 * @brief Resets the control registers of OIS from the UI (User Interface)[set]
6835 *
6836 * @param ctx read / write interface definitions
6837 * @param val Resets the control registers of OIS from the UI (User Interface)
6838 * @retval interface status (MANDATORY: return 0 -> no Error)
6839 *
6840 */
lsm6dsv16x_ois_reset_set(stmdev_ctx_t * ctx,int8_t val)6841 int32_t lsm6dsv16x_ois_reset_set(stmdev_ctx_t *ctx, int8_t val)
6842 {
6843 lsm6dsv16x_func_cfg_access_t func_cfg_access;
6844 int32_t ret;
6845
6846 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
6847 if (ret == 0)
6848 {
6849 func_cfg_access.spi2_reset = (uint8_t)val;
6850 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
6851 }
6852
6853 return ret;
6854 }
6855
6856 /**
6857 * @brief Resets the control registers of OIS from the UI (User Interface)[get]
6858 *
6859 * @param ctx read / write interface definitions
6860 * @param val Resets the control registers of OIS from the UI (User Interface)
6861 * @retval interface status (MANDATORY: return 0 -> no Error)
6862 *
6863 */
lsm6dsv16x_ois_reset_get(stmdev_ctx_t * ctx,int8_t * val)6864 int32_t lsm6dsv16x_ois_reset_get(stmdev_ctx_t *ctx, int8_t *val)
6865 {
6866 lsm6dsv16x_func_cfg_access_t func_cfg_access;
6867 int32_t ret;
6868
6869 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
6870 *val = (int8_t)func_cfg_access.spi2_reset;
6871
6872 return ret;
6873 }
6874
6875 /**
6876 * @brief Enable/disable pull up on OIS interface.[set]
6877 *
6878 * @param ctx read / write interface definitions
6879 * @param val Enable/disable pull up on OIS interface.
6880 * @retval interface status (MANDATORY: return 0 -> no Error)
6881 *
6882 */
lsm6dsv16x_ois_interface_pull_up_set(stmdev_ctx_t * ctx,uint8_t val)6883 int32_t lsm6dsv16x_ois_interface_pull_up_set(stmdev_ctx_t *ctx, uint8_t val)
6884 {
6885 lsm6dsv16x_pin_ctrl_t pin_ctrl;
6886 int32_t ret;
6887
6888 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
6889 if (ret == 0)
6890 {
6891 pin_ctrl.ois_pu_dis = val;
6892 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
6893 }
6894
6895 return ret;
6896 }
6897
6898 /**
6899 * @brief Enable/disable pull up on OIS interface.[get]
6900 *
6901 * @param ctx read / write interface definitions
6902 * @param val Enable/disable pull up on OIS interface.
6903 * @retval interface status (MANDATORY: return 0 -> no Error)
6904 *
6905 */
lsm6dsv16x_ois_interface_pull_up_get(stmdev_ctx_t * ctx,uint8_t * val)6906 int32_t lsm6dsv16x_ois_interface_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val)
6907 {
6908 lsm6dsv16x_pin_ctrl_t pin_ctrl;
6909 int32_t ret;
6910
6911 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
6912 *val = pin_ctrl.ois_pu_dis;
6913
6914 return ret;
6915 }
6916
6917 /**
6918 * @brief Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit.[set]
6919 *
6920 * @param ctx read / write interface definitions
6921 * @param val Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit.
6922 * @retval interface status (MANDATORY: return 0 -> no Error)
6923 *
6924 */
lsm6dsv16x_ois_handshake_from_ui_set(stmdev_ctx_t * ctx,lsm6dsv16x_ois_handshake_t val)6925 int32_t lsm6dsv16x_ois_handshake_from_ui_set(stmdev_ctx_t *ctx,
6926 lsm6dsv16x_ois_handshake_t val)
6927 {
6928 lsm6dsv16x_ui_handshake_ctrl_t ui_handshake_ctrl;
6929 int32_t ret;
6930
6931 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_HANDSHAKE_CTRL, (uint8_t *)&ui_handshake_ctrl, 1);
6932 if (ret == 0)
6933 {
6934 ui_handshake_ctrl.ui_shared_ack = val.ack;
6935 ui_handshake_ctrl.ui_shared_req = val.req;
6936 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_UI_HANDSHAKE_CTRL, (uint8_t *)&ui_handshake_ctrl, 1);
6937 }
6938
6939 return ret;
6940 }
6941
6942 /**
6943 * @brief Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit.[get]
6944 *
6945 * @param ctx read / write interface definitions
6946 * @param val Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit.
6947 * @retval interface status (MANDATORY: return 0 -> no Error)
6948 *
6949 */
lsm6dsv16x_ois_handshake_from_ui_get(stmdev_ctx_t * ctx,lsm6dsv16x_ois_handshake_t * val)6950 int32_t lsm6dsv16x_ois_handshake_from_ui_get(stmdev_ctx_t *ctx,
6951 lsm6dsv16x_ois_handshake_t *val)
6952 {
6953 lsm6dsv16x_ui_handshake_ctrl_t ui_handshake_ctrl;
6954 int32_t ret;
6955
6956 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_HANDSHAKE_CTRL, (uint8_t *)&ui_handshake_ctrl, 1);
6957 if (ret != 0) { return ret; }
6958
6959 val->ack = ui_handshake_ctrl.ui_shared_ack;
6960 val->req = ui_handshake_ctrl.ui_shared_req;
6961
6962 return ret;
6963 }
6964
6965 /**
6966 * @brief Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit.[set]
6967 *
6968 * @param ctx read / write interface definitions
6969 * @param val Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit.
6970 * @retval interface status (MANDATORY: return 0 -> no Error)
6971 *
6972 */
lsm6dsv16x_ois_handshake_from_ois_set(stmdev_ctx_t * ctx,lsm6dsv16x_ois_handshake_t val)6973 int32_t lsm6dsv16x_ois_handshake_from_ois_set(stmdev_ctx_t *ctx,
6974 lsm6dsv16x_ois_handshake_t val)
6975 {
6976 lsm6dsv16x_spi2_handshake_ctrl_t spi2_handshake_ctrl;
6977 int32_t ret;
6978
6979 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SPI2_HANDSHAKE_CTRL, (uint8_t *)&spi2_handshake_ctrl, 1);
6980 if (ret == 0)
6981 {
6982 spi2_handshake_ctrl.spi2_shared_ack = val.ack;
6983 spi2_handshake_ctrl.spi2_shared_req = val.req;
6984 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SPI2_HANDSHAKE_CTRL, (uint8_t *)&spi2_handshake_ctrl, 1);
6985 }
6986
6987 return ret;
6988 }
6989
6990 /**
6991 * @brief Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit.[get]
6992 *
6993 * @param ctx read / write interface definitions
6994 * @param val Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit.
6995 * @retval interface status (MANDATORY: return 0 -> no Error)
6996 *
6997 */
lsm6dsv16x_ois_handshake_from_ois_get(stmdev_ctx_t * ctx,lsm6dsv16x_ois_handshake_t * val)6998 int32_t lsm6dsv16x_ois_handshake_from_ois_get(stmdev_ctx_t *ctx,
6999 lsm6dsv16x_ois_handshake_t *val)
7000 {
7001 lsm6dsv16x_spi2_handshake_ctrl_t spi2_handshake_ctrl;
7002 int32_t ret;
7003
7004 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SPI2_HANDSHAKE_CTRL, (uint8_t *)&spi2_handshake_ctrl, 1);
7005 if (ret != 0) { return ret; }
7006
7007 val->ack = spi2_handshake_ctrl.spi2_shared_ack;
7008 val->req = spi2_handshake_ctrl.spi2_shared_req;
7009
7010 return ret;
7011 }
7012
7013 /**
7014 * @brief User interface (UI) / SPI2 (OIS) shared registers[set]
7015 *
7016 * @param ctx read / write interface definitions
7017 * @param val User interface (UI) / SPI2 (OIS) shared registers
7018 * @retval interface status (MANDATORY: return 0 -> no Error)
7019 *
7020 */
lsm6dsv16x_ois_shared_set(stmdev_ctx_t * ctx,uint8_t val[6])7021 int32_t lsm6dsv16x_ois_shared_set(stmdev_ctx_t *ctx, uint8_t val[6])
7022 {
7023 int32_t ret;
7024
7025 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_UI_SPI2_SHARED_0, val, 6);
7026
7027 return ret;
7028 }
7029
7030 /**
7031 * @brief User interface (UI) / SPI2 (OIS) shared registers[get]
7032 *
7033 * @param ctx read / write interface definitions
7034 * @param val User interface (UI) / SPI2 (OIS) shared registers
7035 * @retval interface status (MANDATORY: return 0 -> no Error)
7036 *
7037 */
lsm6dsv16x_ois_shared_get(stmdev_ctx_t * ctx,uint8_t val[6])7038 int32_t lsm6dsv16x_ois_shared_get(stmdev_ctx_t *ctx, uint8_t val[6])
7039 {
7040 int32_t ret;
7041
7042 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_SPI2_SHARED_0, val, 6);
7043
7044 return ret;
7045 }
7046
7047 /**
7048 * @brief In User Interface (UI) full control mode, enables SPI2 (OIS Interface) for reading OIS data. This function works also on OIS (UI_CTRL1_OIS = SPI2_CTRL1_OIS).[set]
7049 *
7050 * @param ctx read / write interface definitions
7051 * @param val In User Interface (UI) full control mode, enables SPI2 (OIS Interface) for reading OIS data.
7052 * @retval interface status (MANDATORY: return 0 -> no Error)
7053 *
7054 */
lsm6dsv16x_ois_on_spi2_set(stmdev_ctx_t * ctx,uint8_t val)7055 int32_t lsm6dsv16x_ois_on_spi2_set(stmdev_ctx_t *ctx, uint8_t val)
7056 {
7057 lsm6dsv16x_ui_ctrl1_ois_t ui_ctrl1_ois;
7058 int32_t ret;
7059
7060 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1);
7061 if (ret == 0)
7062 {
7063 ui_ctrl1_ois.spi2_read_en = val;
7064 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1);
7065 }
7066
7067 return ret;
7068 }
7069
7070 /**
7071 * @brief In User Interface (UI) full control mode, enables SPI2 (OIS Interface) for reading OIS data. This function works also on OIS (UI_CTRL1_OIS = SPI2_CTRL1_OIS).[get]
7072 *
7073 * @param ctx read / write interface definitions
7074 * @param val In User Interface (UI) full control mode, enables SPI2 (OIS Interface) for reading OIS data.
7075 * @retval interface status (MANDATORY: return 0 -> no Error)
7076 *
7077 */
lsm6dsv16x_ois_on_spi2_get(stmdev_ctx_t * ctx,uint8_t * val)7078 int32_t lsm6dsv16x_ois_on_spi2_get(stmdev_ctx_t *ctx, uint8_t *val)
7079 {
7080 lsm6dsv16x_ui_ctrl1_ois_t ui_ctrl1_ois;
7081 int32_t ret;
7082
7083 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1);
7084 *val = ui_ctrl1_ois.spi2_read_en;
7085
7086 return ret;
7087 }
7088
7089 /**
7090 * @brief Enables gyroscope/accelerometer OIS chain. This function works also on OIS (UI_CTRL1_OIS = SPI2_CTRL1_OIS).[set]
7091 *
7092 * @param ctx read / write interface definitions
7093 * @param val Enables gyroscope/accelerometer OIS chain.
7094 * @retval interface status (MANDATORY: return 0 -> no Error)
7095 *
7096 */
lsm6dsv16x_ois_chain_set(stmdev_ctx_t * ctx,lsm6dsv16x_ois_chain_t val)7097 int32_t lsm6dsv16x_ois_chain_set(stmdev_ctx_t *ctx, lsm6dsv16x_ois_chain_t val)
7098 {
7099 lsm6dsv16x_ui_ctrl1_ois_t ui_ctrl1_ois;
7100 int32_t ret;
7101
7102 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1);
7103 if (ret == 0)
7104 {
7105 ui_ctrl1_ois.ois_g_en = val.gy;
7106 ui_ctrl1_ois.ois_xl_en = val.xl;
7107 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1);
7108 }
7109
7110 return ret;
7111 }
7112
7113 /**
7114 * @brief Enables gyroscope/accelerometer OIS chain.[get]
7115 *
7116 * @param ctx read / write interface definitions
7117 * @param val Enables gyroscope/accelerometer OIS chain.
7118 * @retval interface status (MANDATORY: return 0 -> no Error)
7119 *
7120 */
lsm6dsv16x_ois_chain_get(stmdev_ctx_t * ctx,lsm6dsv16x_ois_chain_t * val)7121 int32_t lsm6dsv16x_ois_chain_get(stmdev_ctx_t *ctx, lsm6dsv16x_ois_chain_t *val)
7122 {
7123 lsm6dsv16x_ui_ctrl1_ois_t ui_ctrl1_ois;
7124 int32_t ret;
7125
7126 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1);
7127 if (ret != 0) { return ret; }
7128
7129 val->gy = ui_ctrl1_ois.ois_g_en;
7130 val->xl = ui_ctrl1_ois.ois_xl_en;
7131
7132 return ret;
7133 }
7134
7135 /**
7136 * @brief Gyroscope OIS full-scale selection[set]
7137 *
7138 * @param ctx read / write interface definitions
7139 * @param val OIS_125dps, OIS_250dps, OIS_500dps, OIS_1000dps, OIS_2000dps,
7140 * @retval interface status (MANDATORY: return 0 -> no Error)
7141 *
7142 */
lsm6dsv16x_ois_gy_full_scale_set(stmdev_ctx_t * ctx,lsm6dsv16x_ois_gy_full_scale_t val)7143 int32_t lsm6dsv16x_ois_gy_full_scale_set(stmdev_ctx_t *ctx,
7144 lsm6dsv16x_ois_gy_full_scale_t val)
7145 {
7146 lsm6dsv16x_ui_ctrl2_ois_t ui_ctrl2_ois;
7147 int32_t ret;
7148
7149 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1);
7150 if (ret == 0)
7151 {
7152 ui_ctrl2_ois.fs_g_ois = (uint8_t)val & 0x03U;
7153 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1);
7154 }
7155
7156 return ret;
7157 }
7158
7159 /**
7160 * @brief Gyroscope OIS full-scale selection[get]
7161 *
7162 * @param ctx read / write interface definitions
7163 * @param val OIS_125dps, OIS_250dps, OIS_500dps, OIS_1000dps, OIS_2000dps,
7164 * @retval interface status (MANDATORY: return 0 -> no Error)
7165 *
7166 */
lsm6dsv16x_ois_gy_full_scale_get(stmdev_ctx_t * ctx,lsm6dsv16x_ois_gy_full_scale_t * val)7167 int32_t lsm6dsv16x_ois_gy_full_scale_get(stmdev_ctx_t *ctx,
7168 lsm6dsv16x_ois_gy_full_scale_t *val)
7169 {
7170 lsm6dsv16x_ui_ctrl2_ois_t ui_ctrl2_ois;
7171 int32_t ret;
7172
7173 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1);
7174 if (ret != 0) { return ret; }
7175
7176 switch (ui_ctrl2_ois.fs_g_ois)
7177 {
7178 case LSM6DSV16X_OIS_125dps:
7179 *val = LSM6DSV16X_OIS_125dps;
7180 break;
7181
7182 case LSM6DSV16X_OIS_250dps:
7183 *val = LSM6DSV16X_OIS_250dps;
7184 break;
7185
7186 case LSM6DSV16X_OIS_500dps:
7187 *val = LSM6DSV16X_OIS_500dps;
7188 break;
7189
7190 case LSM6DSV16X_OIS_1000dps:
7191 *val = LSM6DSV16X_OIS_1000dps;
7192 break;
7193
7194 case LSM6DSV16X_OIS_2000dps:
7195 *val = LSM6DSV16X_OIS_2000dps;
7196 break;
7197
7198 default:
7199 *val = LSM6DSV16X_OIS_125dps;
7200 break;
7201 }
7202
7203 return ret;
7204 }
7205
7206 /**
7207 * @brief Selects accelerometer OIS channel full-scale.[set]
7208 *
7209 * @param ctx read / write interface definitions
7210 * @param val OIS_2g, OIS_4g, OIS_8g, OIS_16g,
7211 * @retval interface status (MANDATORY: return 0 -> no Error)
7212 *
7213 */
lsm6dsv16x_ois_xl_full_scale_set(stmdev_ctx_t * ctx,lsm6dsv16x_ois_xl_full_scale_t val)7214 int32_t lsm6dsv16x_ois_xl_full_scale_set(stmdev_ctx_t *ctx,
7215 lsm6dsv16x_ois_xl_full_scale_t val)
7216 {
7217 lsm6dsv16x_ui_ctrl3_ois_t ui_ctrl3_ois;
7218 int32_t ret;
7219
7220 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1);
7221 if (ret == 0)
7222 {
7223 ui_ctrl3_ois.fs_xl_ois = (uint8_t)val & 0x3U;
7224 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1);
7225 }
7226
7227 return ret;
7228 }
7229
7230 /**
7231 * @brief Selects accelerometer OIS channel full-scale.[get]
7232 *
7233 * @param ctx read / write interface definitions
7234 * @param val OIS_2g, OIS_4g, OIS_8g, OIS_16g,
7235 * @retval interface status (MANDATORY: return 0 -> no Error)
7236 *
7237 */
lsm6dsv16x_ois_xl_full_scale_get(stmdev_ctx_t * ctx,lsm6dsv16x_ois_xl_full_scale_t * val)7238 int32_t lsm6dsv16x_ois_xl_full_scale_get(stmdev_ctx_t *ctx,
7239 lsm6dsv16x_ois_xl_full_scale_t *val)
7240 {
7241 lsm6dsv16x_ui_ctrl3_ois_t ui_ctrl3_ois;
7242 int32_t ret;
7243
7244 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1);
7245 if (ret != 0) { return ret; }
7246
7247 switch (ui_ctrl3_ois.fs_xl_ois)
7248 {
7249 case LSM6DSV16X_OIS_2g:
7250 *val = LSM6DSV16X_OIS_2g;
7251 break;
7252
7253 case LSM6DSV16X_OIS_4g:
7254 *val = LSM6DSV16X_OIS_4g;
7255 break;
7256
7257 case LSM6DSV16X_OIS_8g:
7258 *val = LSM6DSV16X_OIS_8g;
7259 break;
7260
7261 case LSM6DSV16X_OIS_16g:
7262 *val = LSM6DSV16X_OIS_16g;
7263 break;
7264
7265 default:
7266 *val = LSM6DSV16X_OIS_2g;
7267 break;
7268 }
7269
7270 return ret;
7271 }
7272
7273 /**
7274 * @}
7275 *
7276 */
7277
7278 /**
7279 * @defgroup Orientation 6D (and 4D)
7280 * @brief This section groups all the functions concerning six position
7281 * detection (6D).
7282 * @{
7283 *
7284 */
7285
7286 /**
7287 * @brief Threshold for 4D/6D function.[set]
7288 *
7289 * @param ctx read / write interface definitions
7290 * @param val DEG_80, DEG_70, DEG_60, DEG_50,
7291 * @retval interface status (MANDATORY: return 0 -> no Error)
7292 *
7293 */
lsm6dsv16x_6d_threshold_set(stmdev_ctx_t * ctx,lsm6dsv16x_6d_threshold_t val)7294 int32_t lsm6dsv16x_6d_threshold_set(stmdev_ctx_t *ctx,
7295 lsm6dsv16x_6d_threshold_t val)
7296 {
7297 lsm6dsv16x_tap_ths_6d_t tap_ths_6d;
7298 int32_t ret;
7299
7300 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
7301 if (ret == 0)
7302 {
7303 tap_ths_6d.sixd_ths = (uint8_t)val & 0x03U;
7304 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
7305 }
7306
7307 return ret;
7308 }
7309
7310 /**
7311 * @brief Threshold for 4D/6D function.[get]
7312 *
7313 * @param ctx read / write interface definitions
7314 * @param val DEG_80, DEG_70, DEG_60, DEG_50,
7315 * @retval interface status (MANDATORY: return 0 -> no Error)
7316 *
7317 */
lsm6dsv16x_6d_threshold_get(stmdev_ctx_t * ctx,lsm6dsv16x_6d_threshold_t * val)7318 int32_t lsm6dsv16x_6d_threshold_get(stmdev_ctx_t *ctx,
7319 lsm6dsv16x_6d_threshold_t *val)
7320 {
7321 lsm6dsv16x_tap_ths_6d_t tap_ths_6d;
7322 int32_t ret;
7323
7324 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
7325 if (ret != 0) { return ret; }
7326
7327 switch (tap_ths_6d.sixd_ths)
7328 {
7329 case LSM6DSV16X_DEG_80:
7330 *val = LSM6DSV16X_DEG_80;
7331 break;
7332
7333 case LSM6DSV16X_DEG_70:
7334 *val = LSM6DSV16X_DEG_70;
7335 break;
7336
7337 case LSM6DSV16X_DEG_60:
7338 *val = LSM6DSV16X_DEG_60;
7339 break;
7340
7341 case LSM6DSV16X_DEG_50:
7342 *val = LSM6DSV16X_DEG_50;
7343 break;
7344
7345 default:
7346 *val = LSM6DSV16X_DEG_80;
7347 break;
7348 }
7349
7350 return ret;
7351 }
7352
7353 /**
7354 * @brief 4D orientation detection enable. Z-axis position detection is disabled.[set]
7355 *
7356 * @param ctx read / write interface definitions
7357 * @param val 4D orientation detection enable. Z-axis position detection is disabled.
7358 * @retval interface status (MANDATORY: return 0 -> no Error)
7359 *
7360 */
lsm6dsv16x_4d_mode_set(stmdev_ctx_t * ctx,uint8_t val)7361 int32_t lsm6dsv16x_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val)
7362 {
7363 lsm6dsv16x_tap_ths_6d_t tap_ths_6d;
7364 int32_t ret;
7365
7366 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
7367 if (ret == 0)
7368 {
7369 tap_ths_6d.d4d_en = val;
7370 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
7371 }
7372
7373 return ret;
7374 }
7375
7376 /**
7377 * @brief 4D orientation detection enable. Z-axis position detection is disabled.[get]
7378 *
7379 * @param ctx read / write interface definitions
7380 * @param val 4D orientation detection enable. Z-axis position detection is disabled.
7381 * @retval interface status (MANDATORY: return 0 -> no Error)
7382 *
7383 */
lsm6dsv16x_4d_mode_get(stmdev_ctx_t * ctx,uint8_t * val)7384 int32_t lsm6dsv16x_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
7385 {
7386 lsm6dsv16x_tap_ths_6d_t tap_ths_6d;
7387 int32_t ret;
7388
7389 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
7390 *val = tap_ths_6d.d4d_en;
7391
7392 return ret;
7393 }
7394
7395 /**
7396 * @}
7397 *
7398 */
7399
7400 /**
7401 * @defgroup AH_QVAR
7402 * @brief This section group all the functions concerning the
7403 * usage of AH_QVAR
7404 * @{
7405 *
7406 */
7407
7408 /**
7409 * @brief Configures the equivalent input impedance of the AH_QVAR buffers.[set]
7410 *
7411 * @param ctx read / write interface definitions
7412 * @param val 2400MOhm, 730MOhm, 300MOhm, 255MOhm,
7413 * @retval interface status (MANDATORY: return 0 -> no Error)
7414 *
7415 */
lsm6dsv16x_ah_qvar_zin_set(stmdev_ctx_t * ctx,lsm6dsv16x_ah_qvar_zin_t val)7416 int32_t lsm6dsv16x_ah_qvar_zin_set(stmdev_ctx_t *ctx,
7417 lsm6dsv16x_ah_qvar_zin_t val)
7418 {
7419 lsm6dsv16x_ctrl7_t ctrl7;
7420 int32_t ret;
7421
7422 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL7, (uint8_t *)&ctrl7, 1);
7423 if (ret == 0)
7424 {
7425 ctrl7.ah_qvar_c_zin = (uint8_t)val & 0x03U;
7426 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL7, (uint8_t *)&ctrl7, 1);
7427 }
7428
7429 return ret;
7430 }
7431
7432 /**
7433 * @brief Configures the equivalent input impedance of the AH_QVAR buffers.[get]
7434 *
7435 * @param ctx read / write interface definitions
7436 * @param val 2400MOhm, 730MOhm, 300MOhm, 255MOhm,
7437 * @retval interface status (MANDATORY: return 0 -> no Error)
7438 *
7439 */
lsm6dsv16x_ah_qvar_zin_get(stmdev_ctx_t * ctx,lsm6dsv16x_ah_qvar_zin_t * val)7440 int32_t lsm6dsv16x_ah_qvar_zin_get(stmdev_ctx_t *ctx,
7441 lsm6dsv16x_ah_qvar_zin_t *val)
7442 {
7443 lsm6dsv16x_ctrl7_t ctrl7;
7444 int32_t ret;
7445
7446 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL7, (uint8_t *)&ctrl7, 1);
7447 if (ret != 0) { return ret; }
7448
7449 switch (ctrl7.ah_qvar_c_zin)
7450 {
7451 case LSM6DSV16X_2400MOhm:
7452 *val = LSM6DSV16X_2400MOhm;
7453 break;
7454
7455 case LSM6DSV16X_730MOhm:
7456 *val = LSM6DSV16X_730MOhm;
7457 break;
7458
7459 case LSM6DSV16X_300MOhm:
7460 *val = LSM6DSV16X_300MOhm;
7461 break;
7462
7463 case LSM6DSV16X_255MOhm:
7464 *val = LSM6DSV16X_255MOhm;
7465 break;
7466
7467 default:
7468 *val = LSM6DSV16X_2400MOhm;
7469 break;
7470 }
7471
7472 return ret;
7473 }
7474
7475 /**
7476 * @brief Enables AH_QVAR chain. When this bit is set to ‘1’, the AH_QVAR buffers are connected to the SDx/AH1/Qvar1 and SCx/AH2/Qvar2 pins. Before setting this bit to 1, the accelerometer and gyroscope sensor have to be configured in power-down mode.[set]
7477 *
7478 * @param ctx read / write interface definitions
7479 * @param val Enables AH_QVAR chain. When this bit is set to ‘1’, the AH_QVAR buffers are connected to the SDx/AH1/Qvar1 and SCx/AH2/Qvar2 pins. Before setting this bit to 1, the accelerometer and gyroscope sensor have to be configured in power-down mode.
7480 * @retval interface status (MANDATORY: return 0 -> no Error)
7481 *
7482 */
lsm6dsv16x_ah_qvar_mode_set(stmdev_ctx_t * ctx,lsm6dsv16x_ah_qvar_mode_t val)7483 int32_t lsm6dsv16x_ah_qvar_mode_set(stmdev_ctx_t *ctx,
7484 lsm6dsv16x_ah_qvar_mode_t val)
7485 {
7486 lsm6dsv16x_ctrl7_t ctrl7;
7487 int32_t ret;
7488
7489 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL7, (uint8_t *)&ctrl7, 1);
7490 if (ret == 0)
7491 {
7492 ctrl7.ah_qvar_en = val.ah_qvar_en;
7493 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL7, (uint8_t *)&ctrl7, 1);
7494 }
7495
7496 return ret;
7497 }
7498
7499 /**
7500 * @brief Enables AH_QVAR chain. When this bit is set to ‘1’, the AH_QVAR buffers are connected to the SDx/AH1/Qvar1 and SCx/AH2/Qvar2 pins. Before setting this bit to 1, the accelerometer and gyroscope sensor have to be configured in power-down mode.[get]
7501 *
7502 * @param ctx read / write interface definitions
7503 * @param val Enables AH_QVAR chain. When this bit is set to ‘1’, the AH_QVAR buffers are connected to the SDx/AH1/Qvar1 and SCx/AH2/Qvar2 pins. Before setting this bit to 1, the accelerometer and gyroscope sensor have to be configured in power-down mode.
7504 * @retval interface status (MANDATORY: return 0 -> no Error)
7505 *
7506 */
lsm6dsv16x_ah_qvar_mode_get(stmdev_ctx_t * ctx,lsm6dsv16x_ah_qvar_mode_t * val)7507 int32_t lsm6dsv16x_ah_qvar_mode_get(stmdev_ctx_t *ctx,
7508 lsm6dsv16x_ah_qvar_mode_t *val)
7509 {
7510 lsm6dsv16x_ctrl7_t ctrl7;
7511 int32_t ret;
7512
7513 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL7, (uint8_t *)&ctrl7, 1);
7514 val->ah_qvar_en = ctrl7.ah_qvar_en;
7515
7516 return ret;
7517 }
7518
7519 /**
7520 * @}
7521 *
7522 */
7523
7524 /**
7525 * @defgroup SenseWire (I3C)
7526 * @brief This section group all the functions concerning the
7527 * usage of SenseWire (I3C)
7528 * @{
7529 *
7530 */
7531
7532 /**
7533 * @brief Selects the action the device will perform after "Reset whole chip" I3C pattern.[set]
7534 *
7535 * @param ctx read / write interface definitions
7536 * @param val SW_RST_DYN_ADDRESS_RST, GLOBAL_RST,
7537 * @retval interface status (MANDATORY: return 0 -> no Error)
7538 *
7539 */
lsm6dsv16x_i3c_reset_mode_set(stmdev_ctx_t * ctx,lsm6dsv16x_i3c_reset_mode_t val)7540 int32_t lsm6dsv16x_i3c_reset_mode_set(stmdev_ctx_t *ctx,
7541 lsm6dsv16x_i3c_reset_mode_t val)
7542 {
7543 lsm6dsv16x_pin_ctrl_t pin_ctrl;
7544 int32_t ret;
7545
7546 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
7547 if (ret == 0)
7548 {
7549 pin_ctrl.ibhr_por_en = (uint8_t)val & 0x01U;
7550 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
7551 }
7552
7553 return ret;
7554 }
7555
7556 /**
7557 * @brief Selects the action the device will perform after "Reset whole chip" I3C pattern.[get]
7558 *
7559 * @param ctx read / write interface definitions
7560 * @param val SW_RST_DYN_ADDRESS_RST, I3C_GLOBAL_RST,
7561 * @retval interface status (MANDATORY: return 0 -> no Error)
7562 *
7563 */
lsm6dsv16x_i3c_reset_mode_get(stmdev_ctx_t * ctx,lsm6dsv16x_i3c_reset_mode_t * val)7564 int32_t lsm6dsv16x_i3c_reset_mode_get(stmdev_ctx_t *ctx,
7565 lsm6dsv16x_i3c_reset_mode_t *val)
7566 {
7567 lsm6dsv16x_pin_ctrl_t pin_ctrl;
7568 int32_t ret;
7569
7570 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
7571 if (ret != 0) { return ret; }
7572
7573 switch (pin_ctrl.ibhr_por_en)
7574 {
7575 case LSM6DSV16X_SW_RST_DYN_ADDRESS_RST:
7576 *val = LSM6DSV16X_SW_RST_DYN_ADDRESS_RST;
7577 break;
7578
7579 case LSM6DSV16X_I3C_GLOBAL_RST:
7580 *val = LSM6DSV16X_I3C_GLOBAL_RST;
7581 break;
7582
7583 default:
7584 *val = LSM6DSV16X_SW_RST_DYN_ADDRESS_RST;
7585 break;
7586 }
7587
7588 return ret;
7589 }
7590
7591 /**
7592 * @brief Select the us activity time for IBI (In-Band Interrupt) with I3C[set]
7593 *
7594 * @param ctx read / write interface definitions
7595 * @param val IBI_2us, IBI_50us, IBI_1ms, IBI_25ms,
7596 * @retval interface status (MANDATORY: return 0 -> no Error)
7597 *
7598 */
lsm6dsv16x_i3c_ibi_time_set(stmdev_ctx_t * ctx,lsm6dsv16x_i3c_ibi_time_t val)7599 int32_t lsm6dsv16x_i3c_ibi_time_set(stmdev_ctx_t *ctx,
7600 lsm6dsv16x_i3c_ibi_time_t val)
7601 {
7602 lsm6dsv16x_ctrl5_t ctrl5;
7603 int32_t ret;
7604
7605 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL5, (uint8_t *)&ctrl5, 1);
7606 if (ret == 0)
7607 {
7608 ctrl5.bus_act_sel = (uint8_t)val & 0x03U;
7609 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL5, (uint8_t *)&ctrl5, 1);
7610 }
7611
7612 return ret;
7613 }
7614
7615 /**
7616 * @brief Select the us activity time for IBI (In-Band Interrupt) with I3C[get]
7617 *
7618 * @param ctx read / write interface definitions
7619 * @param val IBI_2us, IBI_50us, IBI_1ms, IBI_25ms,
7620 * @retval interface status (MANDATORY: return 0 -> no Error)
7621 *
7622 */
lsm6dsv16x_i3c_ibi_time_get(stmdev_ctx_t * ctx,lsm6dsv16x_i3c_ibi_time_t * val)7623 int32_t lsm6dsv16x_i3c_ibi_time_get(stmdev_ctx_t *ctx,
7624 lsm6dsv16x_i3c_ibi_time_t *val)
7625 {
7626 lsm6dsv16x_ctrl5_t ctrl5;
7627 int32_t ret;
7628
7629 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL5, (uint8_t *)&ctrl5, 1);
7630 if (ret != 0) { return ret; }
7631
7632 switch (ctrl5.bus_act_sel)
7633 {
7634 case LSM6DSV16X_IBI_2us:
7635 *val = LSM6DSV16X_IBI_2us;
7636 break;
7637
7638 case LSM6DSV16X_IBI_50us:
7639 *val = LSM6DSV16X_IBI_50us;
7640 break;
7641
7642 case LSM6DSV16X_IBI_1ms:
7643 *val = LSM6DSV16X_IBI_1ms;
7644 break;
7645
7646 case LSM6DSV16X_IBI_25ms:
7647 *val = LSM6DSV16X_IBI_25ms;
7648 break;
7649
7650 default:
7651 *val = LSM6DSV16X_IBI_2us;
7652 break;
7653 }
7654
7655 return ret;
7656 }
7657
7658 /**
7659 * @}
7660 *
7661 */
7662
7663 /**
7664 * @defgroup Sensor hub
7665 * @brief This section groups all the functions that manage the
7666 * sensor hub.
7667 * @{
7668 *
7669 */
7670
7671 /**
7672 * @brief Sensor Hub master I2C pull-up enable.[set]
7673 *
7674 * @param ctx read / write interface definitions
7675 * @param val Sensor Hub master I2C pull-up enable.
7676 * @retval interface status (MANDATORY: return 0 -> no Error)
7677 *
7678 */
lsm6dsv16x_sh_master_interface_pull_up_set(stmdev_ctx_t * ctx,uint8_t val)7679 int32_t lsm6dsv16x_sh_master_interface_pull_up_set(stmdev_ctx_t *ctx,
7680 uint8_t val)
7681 {
7682 lsm6dsv16x_if_cfg_t if_cfg;
7683 int32_t ret;
7684
7685 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1);
7686 if (ret == 0)
7687 {
7688 if_cfg.shub_pu_en = val;
7689 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1);
7690 }
7691
7692 return ret;
7693 }
7694
7695 /**
7696 * @brief Sensor Hub master I2C pull-up enable.[get]
7697 *
7698 * @param ctx read / write interface definitions
7699 * @param val Sensor Hub master I2C pull-up enable.
7700 * @retval interface status (MANDATORY: return 0 -> no Error)
7701 *
7702 */
lsm6dsv16x_sh_master_interface_pull_up_get(stmdev_ctx_t * ctx,uint8_t * val)7703 int32_t lsm6dsv16x_sh_master_interface_pull_up_get(stmdev_ctx_t *ctx,
7704 uint8_t *val)
7705 {
7706 lsm6dsv16x_if_cfg_t if_cfg;
7707 int32_t ret;
7708
7709 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1);
7710 *val = if_cfg.shub_pu_en;
7711
7712 return ret;
7713 }
7714
7715 /**
7716 * @brief Sensor hub output registers.[get]
7717 *
7718 * @param ctx read / write interface definitions
7719 * @param val Sensor hub output registers.
7720 * @retval interface status (MANDATORY: return 0 -> no Error)
7721 *
7722 */
lsm6dsv16x_sh_read_data_raw_get(stmdev_ctx_t * ctx,uint8_t * val,uint8_t len)7723 int32_t lsm6dsv16x_sh_read_data_raw_get(stmdev_ctx_t *ctx, uint8_t *val,
7724 uint8_t len)
7725 {
7726 int32_t ret;
7727
7728 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK);
7729 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SENSOR_HUB_1, val, len);
7730 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
7731
7732 return ret;
7733 }
7734
7735 /**
7736 * @brief Number of external sensors to be read by the sensor hub.[set]
7737 *
7738 * @param ctx read / write interface definitions
7739 * @param val SLV_0, SLV_0_1, SLV_0_1_2, SLV_0_1_2_3,
7740 * @retval interface status (MANDATORY: return 0 -> no Error)
7741 *
7742 */
lsm6dsv16x_sh_slave_connected_set(stmdev_ctx_t * ctx,lsm6dsv16x_sh_slave_connected_t val)7743 int32_t lsm6dsv16x_sh_slave_connected_set(stmdev_ctx_t *ctx,
7744 lsm6dsv16x_sh_slave_connected_t val)
7745 {
7746 lsm6dsv16x_master_config_t master_config;
7747 int32_t ret;
7748
7749 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK);
7750 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
7751 if (ret != 0) { goto exit; }
7752
7753 master_config.aux_sens_on = (uint8_t)val & 0x3U;
7754 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
7755
7756 exit:
7757 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
7758
7759 return ret;
7760 }
7761
7762 /**
7763 * @brief Number of external sensors to be read by the sensor hub.[get]
7764 *
7765 * @param ctx read / write interface definitions
7766 * @param val SLV_0, SLV_0_1, SLV_0_1_2, SLV_0_1_2_3,
7767 * @retval interface status (MANDATORY: return 0 -> no Error)
7768 *
7769 */
lsm6dsv16x_sh_slave_connected_get(stmdev_ctx_t * ctx,lsm6dsv16x_sh_slave_connected_t * val)7770 int32_t lsm6dsv16x_sh_slave_connected_get(stmdev_ctx_t *ctx,
7771 lsm6dsv16x_sh_slave_connected_t *val)
7772 {
7773 lsm6dsv16x_master_config_t master_config;
7774 int32_t ret;
7775
7776 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK);
7777 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
7778 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
7779 if (ret != 0) { return ret; }
7780
7781 switch (master_config.aux_sens_on)
7782 {
7783 case LSM6DSV16X_SLV_0:
7784 *val = LSM6DSV16X_SLV_0;
7785 break;
7786
7787 case LSM6DSV16X_SLV_0_1:
7788 *val = LSM6DSV16X_SLV_0_1;
7789 break;
7790
7791 case LSM6DSV16X_SLV_0_1_2:
7792 *val = LSM6DSV16X_SLV_0_1_2;
7793 break;
7794
7795 case LSM6DSV16X_SLV_0_1_2_3:
7796 *val = LSM6DSV16X_SLV_0_1_2_3;
7797 break;
7798
7799 default:
7800 *val = LSM6DSV16X_SLV_0;
7801 break;
7802 }
7803
7804 return ret;
7805 }
7806
7807 /**
7808 * @brief Sensor hub I2C master enable.[set]
7809 *
7810 * @param ctx read / write interface definitions
7811 * @param val Sensor hub I2C master enable.
7812 * @retval interface status (MANDATORY: return 0 -> no Error)
7813 *
7814 */
lsm6dsv16x_sh_master_set(stmdev_ctx_t * ctx,uint8_t val)7815 int32_t lsm6dsv16x_sh_master_set(stmdev_ctx_t *ctx, uint8_t val)
7816 {
7817 lsm6dsv16x_master_config_t master_config;
7818 int32_t ret;
7819
7820 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK);
7821 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
7822 if (ret != 0) { goto exit; }
7823
7824 master_config.master_on = val;
7825 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
7826
7827 exit:
7828 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
7829
7830 return ret;
7831 }
7832
7833 /**
7834 * @brief Sensor hub I2C master enable.[get]
7835 *
7836 * @param ctx read / write interface definitions
7837 * @param val Sensor hub I2C master enable.
7838 * @retval interface status (MANDATORY: return 0 -> no Error)
7839 *
7840 */
lsm6dsv16x_sh_master_get(stmdev_ctx_t * ctx,uint8_t * val)7841 int32_t lsm6dsv16x_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val)
7842 {
7843 lsm6dsv16x_master_config_t master_config;
7844 int32_t ret;
7845
7846 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK);
7847 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
7848
7849 *val = master_config.master_on;
7850
7851 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
7852
7853 return ret;
7854 }
7855
7856 /**
7857 * @brief I2C interface pass-through.[set]
7858 *
7859 * @param ctx read / write interface definitions
7860 * @param val I2C interface pass-through.
7861 * @retval interface status (MANDATORY: return 0 -> no Error)
7862 *
7863 */
lsm6dsv16x_sh_pass_through_set(stmdev_ctx_t * ctx,uint8_t val)7864 int32_t lsm6dsv16x_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val)
7865 {
7866 lsm6dsv16x_master_config_t master_config;
7867 int32_t ret;
7868
7869 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK);
7870 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
7871 if (ret != 0) { goto exit; }
7872
7873 master_config.pass_through_mode = val;
7874 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
7875
7876 exit:
7877 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
7878
7879 return ret;
7880 }
7881
7882 /**
7883 * @brief I2C interface pass-through.[get]
7884 *
7885 * @param ctx read / write interface definitions
7886 * @param val I2C interface pass-through.
7887 * @retval interface status (MANDATORY: return 0 -> no Error)
7888 *
7889 */
lsm6dsv16x_sh_pass_through_get(stmdev_ctx_t * ctx,uint8_t * val)7890 int32_t lsm6dsv16x_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val)
7891 {
7892 lsm6dsv16x_master_config_t master_config;
7893 int32_t ret;
7894
7895 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK);
7896 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
7897
7898 *val = master_config.pass_through_mode;
7899
7900 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
7901
7902 return ret;
7903 }
7904
7905 /**
7906 * @brief Sensor hub trigger signal selection.[set]
7907 *
7908 * @param ctx read / write interface definitions
7909 * @param val SH_TRG_XL_GY_DRDY, SH_TRIG_INT2,
7910 * @retval interface status (MANDATORY: return 0 -> no Error)
7911 *
7912 */
lsm6dsv16x_sh_syncro_mode_set(stmdev_ctx_t * ctx,lsm6dsv16x_sh_syncro_mode_t val)7913 int32_t lsm6dsv16x_sh_syncro_mode_set(stmdev_ctx_t *ctx,
7914 lsm6dsv16x_sh_syncro_mode_t val)
7915 {
7916 lsm6dsv16x_master_config_t master_config;
7917 int32_t ret;
7918
7919 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK);
7920 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
7921 if (ret != 0) { goto exit; }
7922
7923 master_config.start_config = (uint8_t)val & 0x01U;
7924 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
7925
7926 exit:
7927 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
7928
7929 return ret;
7930 }
7931
7932 /**
7933 * @brief Sensor hub trigger signal selection.[get]
7934 *
7935 * @param ctx read / write interface definitions
7936 * @param val SH_TRG_XL_GY_DRDY, SH_TRIG_INT2,
7937 * @retval interface status (MANDATORY: return 0 -> no Error)
7938 *
7939 */
lsm6dsv16x_sh_syncro_mode_get(stmdev_ctx_t * ctx,lsm6dsv16x_sh_syncro_mode_t * val)7940 int32_t lsm6dsv16x_sh_syncro_mode_get(stmdev_ctx_t *ctx,
7941 lsm6dsv16x_sh_syncro_mode_t *val)
7942 {
7943 lsm6dsv16x_master_config_t master_config;
7944 int32_t ret;
7945
7946 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK);
7947 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
7948 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
7949 if (ret != 0) { return ret; }
7950
7951 switch (master_config.start_config)
7952 {
7953 case LSM6DSV16X_SH_TRG_XL_GY_DRDY:
7954 *val = LSM6DSV16X_SH_TRG_XL_GY_DRDY;
7955 break;
7956
7957 case LSM6DSV16X_SH_TRIG_INT2:
7958 *val = LSM6DSV16X_SH_TRIG_INT2;
7959 break;
7960
7961 default:
7962 *val = LSM6DSV16X_SH_TRG_XL_GY_DRDY;
7963 break;
7964 }
7965
7966 return ret;
7967 }
7968
7969 /**
7970 * @brief Slave 0 write operation is performed only at the first sensor hub cycle.[set]
7971 *
7972 * @param ctx read / write interface definitions
7973 * @param val EACH_SH_CYCLE, ONLY_FIRST_CYCLE,
7974 * @retval interface status (MANDATORY: return 0 -> no Error)
7975 *
7976 */
lsm6dsv16x_sh_write_mode_set(stmdev_ctx_t * ctx,lsm6dsv16x_sh_write_mode_t val)7977 int32_t lsm6dsv16x_sh_write_mode_set(stmdev_ctx_t *ctx,
7978 lsm6dsv16x_sh_write_mode_t val)
7979 {
7980 lsm6dsv16x_master_config_t master_config;
7981 int32_t ret;
7982
7983 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK);
7984 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
7985 if (ret != 0) { goto exit; }
7986
7987 master_config.write_once = (uint8_t)val & 0x01U;
7988 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
7989
7990 exit:
7991 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
7992
7993 return ret;
7994 }
7995
7996 /**
7997 * @brief Slave 0 write operation is performed only at the first sensor hub cycle.[get]
7998 *
7999 * @param ctx read / write interface definitions
8000 * @param val EACH_SH_CYCLE, ONLY_FIRST_CYCLE,
8001 * @retval interface status (MANDATORY: return 0 -> no Error)
8002 *
8003 */
lsm6dsv16x_sh_write_mode_get(stmdev_ctx_t * ctx,lsm6dsv16x_sh_write_mode_t * val)8004 int32_t lsm6dsv16x_sh_write_mode_get(stmdev_ctx_t *ctx,
8005 lsm6dsv16x_sh_write_mode_t *val)
8006 {
8007 lsm6dsv16x_master_config_t master_config;
8008 int32_t ret;
8009
8010 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK);
8011 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8012 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
8013 if (ret != 0) { return ret; }
8014
8015 switch (master_config.write_once)
8016 {
8017 case LSM6DSV16X_EACH_SH_CYCLE:
8018 *val = LSM6DSV16X_EACH_SH_CYCLE;
8019 break;
8020
8021 case LSM6DSV16X_ONLY_FIRST_CYCLE:
8022 *val = LSM6DSV16X_ONLY_FIRST_CYCLE;
8023 break;
8024
8025 default:
8026 *val = LSM6DSV16X_EACH_SH_CYCLE;
8027 break;
8028 }
8029
8030 return ret;
8031 }
8032
8033 /**
8034 * @brief Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’.[set]
8035 *
8036 * @param ctx read / write interface definitions
8037 * @param val Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’.
8038 * @retval interface status (MANDATORY: return 0 -> no Error)
8039 *
8040 */
lsm6dsv16x_sh_reset_set(stmdev_ctx_t * ctx,uint8_t val)8041 int32_t lsm6dsv16x_sh_reset_set(stmdev_ctx_t *ctx, uint8_t val)
8042 {
8043 lsm6dsv16x_master_config_t master_config;
8044 int32_t ret;
8045
8046 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK);
8047 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8048 if (ret != 0) { goto exit; }
8049
8050 master_config.rst_master_regs = val;
8051 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8052
8053 exit:
8054 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
8055
8056 return ret;
8057 }
8058
8059 /**
8060 * @brief Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’.[get]
8061 *
8062 * @param ctx read / write interface definitions
8063 * @param val Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’.
8064 * @retval interface status (MANDATORY: return 0 -> no Error)
8065 *
8066 */
lsm6dsv16x_sh_reset_get(stmdev_ctx_t * ctx,uint8_t * val)8067 int32_t lsm6dsv16x_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
8068 {
8069 lsm6dsv16x_master_config_t master_config;
8070 int32_t ret;
8071
8072 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK);
8073 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8074
8075 *val = master_config.rst_master_regs;
8076
8077 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
8078
8079 return ret;
8080 }
8081
8082 /**
8083 * @brief Configure slave 0 for perform a write.[set]
8084 *
8085 * @param ctx read / write interface definitions
8086 * @param val a structure that contain
8087 * - uint8_t slv1_add; 8 bit i2c device address
8088 * - uint8_t slv1_subadd; 8 bit register device address
8089 * - uint8_t slv1_data; 8 bit data to write
8090 * @retval interface status (MANDATORY: return 0 -> no Error)
8091 *
8092 */
lsm6dsv16x_sh_cfg_write(stmdev_ctx_t * ctx,lsm6dsv16x_sh_cfg_write_t * val)8093 int32_t lsm6dsv16x_sh_cfg_write(stmdev_ctx_t *ctx,
8094 lsm6dsv16x_sh_cfg_write_t *val)
8095 {
8096 lsm6dsv16x_slv0_add_t reg;
8097 int32_t ret;
8098
8099 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK);
8100 if (ret != 0) { return ret; }
8101
8102 reg.slave0_add = val->slv0_add;
8103 reg.rw_0 = 0;
8104 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SLV0_ADD, (uint8_t *)®, 1);
8105 if (ret != 0) { goto exit; }
8106
8107 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SLV0_SUBADD,
8108 &(val->slv0_subadd), 1);
8109 if (ret != 0) { goto exit; }
8110
8111 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_DATAWRITE_SLV0,
8112 &(val->slv0_data), 1);
8113
8114 exit:
8115 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
8116
8117 return ret;
8118 }
8119
8120 /**
8121 * @brief Rate at which the master communicates.[set]
8122 *
8123 * @param ctx read / write interface definitions
8124 * @param val SH_15Hz, SH_30Hz, SH_60Hz, SH_120Hz, SH_240Hz, SH_480Hz,
8125 * @retval interface status (MANDATORY: return 0 -> no Error)
8126 *
8127 */
lsm6dsv16x_sh_data_rate_set(stmdev_ctx_t * ctx,lsm6dsv16x_sh_data_rate_t val)8128 int32_t lsm6dsv16x_sh_data_rate_set(stmdev_ctx_t *ctx,
8129 lsm6dsv16x_sh_data_rate_t val)
8130 {
8131 lsm6dsv16x_slv0_config_t slv0_config;
8132 int32_t ret;
8133
8134 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK);
8135 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SLV0_CONFIG, (uint8_t *)&slv0_config, 1);
8136 if (ret != 0) { goto exit; }
8137
8138 slv0_config.shub_odr = (uint8_t)val & 0x07U;
8139 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SLV0_CONFIG, (uint8_t *)&slv0_config, 1);
8140
8141 exit:
8142 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
8143
8144 return ret;
8145 }
8146
8147 /**
8148 * @brief Rate at which the master communicates.[get]
8149 *
8150 * @param ctx read / write interface definitions
8151 * @param val SH_15Hz, SH_30Hz, SH_60Hz, SH_120Hz, SH_240Hz, SH_480Hz,
8152 * @retval interface status (MANDATORY: return 0 -> no Error)
8153 *
8154 */
lsm6dsv16x_sh_data_rate_get(stmdev_ctx_t * ctx,lsm6dsv16x_sh_data_rate_t * val)8155 int32_t lsm6dsv16x_sh_data_rate_get(stmdev_ctx_t *ctx,
8156 lsm6dsv16x_sh_data_rate_t *val)
8157 {
8158 lsm6dsv16x_slv0_config_t slv0_config;
8159 int32_t ret;
8160
8161 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK);
8162 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SLV0_CONFIG, (uint8_t *)&slv0_config, 1);
8163 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
8164 if (ret != 0) { return ret; }
8165
8166 switch (slv0_config.shub_odr)
8167 {
8168 case LSM6DSV16X_SH_15Hz:
8169 *val = LSM6DSV16X_SH_15Hz;
8170 break;
8171
8172 case LSM6DSV16X_SH_30Hz:
8173 *val = LSM6DSV16X_SH_30Hz;
8174 break;
8175
8176 case LSM6DSV16X_SH_60Hz:
8177 *val = LSM6DSV16X_SH_60Hz;
8178 break;
8179
8180 case LSM6DSV16X_SH_120Hz:
8181 *val = LSM6DSV16X_SH_120Hz;
8182 break;
8183
8184 case LSM6DSV16X_SH_240Hz:
8185 *val = LSM6DSV16X_SH_240Hz;
8186 break;
8187
8188 case LSM6DSV16X_SH_480Hz:
8189 *val = LSM6DSV16X_SH_480Hz;
8190 break;
8191
8192 default:
8193 *val = LSM6DSV16X_SH_15Hz;
8194 break;
8195 }
8196
8197 return ret;
8198 }
8199
8200 /**
8201 * @brief Configure slave idx for perform a read.[set]
8202 *
8203 * @param ctx read / write interface definitions
8204 * @param val Structure that contain
8205 * - uint8_t slv_add; 8 bit i2c device address
8206 * - uint8_t slv_subadd; 8 bit register device address
8207 * - uint8_t slv_len; num of bit to read
8208 * @retval interface status (MANDATORY: return 0 -> no Error)
8209 *
8210 */
lsm6dsv16x_sh_slv_cfg_read(stmdev_ctx_t * ctx,uint8_t idx,lsm6dsv16x_sh_cfg_read_t * val)8211 int32_t lsm6dsv16x_sh_slv_cfg_read(stmdev_ctx_t *ctx, uint8_t idx,
8212 lsm6dsv16x_sh_cfg_read_t *val)
8213 {
8214 lsm6dsv16x_slv0_add_t slv_add;
8215 lsm6dsv16x_slv0_config_t slv_config;
8216 int32_t ret;
8217
8218 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK);
8219 if (ret != 0) { return ret; }
8220
8221 slv_add.slave0_add = val->slv_add;
8222 slv_add.rw_0 = 1;
8223 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SLV0_ADD + idx*3U,
8224 (uint8_t *)&slv_add, 1);
8225 if (ret != 0) { goto exit; }
8226
8227 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SLV0_SUBADD + idx*3U,
8228 &(val->slv_subadd), 1);
8229 if (ret != 0) { goto exit; }
8230
8231 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SLV0_CONFIG + idx*3U,
8232 (uint8_t *)&slv_config, 1);
8233 if (ret != 0) { goto exit; }
8234
8235 slv_config.slave0_numop = val->slv_len;
8236 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SLV0_CONFIG + idx*3U,
8237 (uint8_t *)&slv_config, 1);
8238
8239 exit:
8240 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
8241
8242 return ret;
8243 }
8244
8245 /**
8246 * @brief Sensor hub source register.[get]
8247 *
8248 * @param ctx read / write interface definitions
8249 * @param val union of registers from STATUS_MASTER to
8250 * @retval interface status (MANDATORY: return 0 -> no Error)
8251 *
8252 */
lsm6dsv16x_sh_status_get(stmdev_ctx_t * ctx,lsm6dsv16x_status_master_t * val)8253 int32_t lsm6dsv16x_sh_status_get(stmdev_ctx_t *ctx,
8254 lsm6dsv16x_status_master_t *val)
8255 {
8256 int32_t ret;
8257
8258 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_STATUS_MASTER_MAINPAGE, (uint8_t *) val, 1);
8259
8260 return ret;
8261 }
8262
8263 /**
8264 * @}
8265 *
8266 */
8267
8268 /**
8269 * @defgroup Serial interfaces
8270 * @brief This section groups all the functions concerning
8271 * serial interfaces management (not auxiliary)
8272 * @{
8273 *
8274 */
8275
8276 /**
8277 * @brief Enables pull-up on SDO pin of UI (User Interface).[set]
8278 *
8279 * @param ctx read / write interface definitions
8280 * @param val Enables pull-up on SDO pin of UI (User Interface).
8281 * @retval interface status (MANDATORY: return 0 -> no Error)
8282 *
8283 */
lsm6dsv16x_ui_sdo_pull_up_set(stmdev_ctx_t * ctx,uint8_t val)8284 int32_t lsm6dsv16x_ui_sdo_pull_up_set(stmdev_ctx_t *ctx, uint8_t val)
8285 {
8286 lsm6dsv16x_pin_ctrl_t pin_ctrl;
8287 int32_t ret;
8288
8289 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
8290 if (ret == 0)
8291 {
8292 pin_ctrl.sdo_pu_en = val;
8293 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
8294 }
8295
8296 return ret;
8297 }
8298
8299 /**
8300 * @brief Enables pull-up on SDO pin of UI (User Interface).[get]
8301 *
8302 * @param ctx read / write interface definitions
8303 * @param val Enables pull-up on SDO pin of UI (User Interface).
8304 * @retval interface status (MANDATORY: return 0 -> no Error)
8305 *
8306 */
lsm6dsv16x_ui_sdo_pull_up_get(stmdev_ctx_t * ctx,uint8_t * val)8307 int32_t lsm6dsv16x_ui_sdo_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val)
8308 {
8309 lsm6dsv16x_pin_ctrl_t pin_ctrl;
8310 int32_t ret;
8311
8312 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
8313 *val = pin_ctrl.sdo_pu_en;
8314
8315 return ret;
8316 }
8317
8318 /**
8319 * @brief Disables I2C and I3C on UI (User Interface).[set]
8320 *
8321 * @param ctx read / write interface definitions
8322 * @param val I2C_I3C_ENABLE, I2C_I3C_DISABLE,
8323 * @retval interface status (MANDATORY: return 0 -> no Error)
8324 *
8325 */
lsm6dsv16x_ui_i2c_i3c_mode_set(stmdev_ctx_t * ctx,lsm6dsv16x_ui_i2c_i3c_mode_t val)8326 int32_t lsm6dsv16x_ui_i2c_i3c_mode_set(stmdev_ctx_t *ctx,
8327 lsm6dsv16x_ui_i2c_i3c_mode_t val)
8328 {
8329 lsm6dsv16x_if_cfg_t if_cfg;
8330 int32_t ret;
8331
8332 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1);
8333 if (ret == 0)
8334 {
8335 if_cfg.i2c_i3c_disable = (uint8_t)val & 0x1U;
8336 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1);
8337 }
8338
8339 return ret;
8340 }
8341
8342 /**
8343 * @brief Disables I2C and I3C on UI (User Interface).[get]
8344 *
8345 * @param ctx read / write interface definitions
8346 * @param val I2C_I3C_ENABLE, I2C_I3C_DISABLE,
8347 * @retval interface status (MANDATORY: return 0 -> no Error)
8348 *
8349 */
lsm6dsv16x_ui_i2c_i3c_mode_get(stmdev_ctx_t * ctx,lsm6dsv16x_ui_i2c_i3c_mode_t * val)8350 int32_t lsm6dsv16x_ui_i2c_i3c_mode_get(stmdev_ctx_t *ctx,
8351 lsm6dsv16x_ui_i2c_i3c_mode_t *val)
8352 {
8353 lsm6dsv16x_if_cfg_t if_cfg;
8354 int32_t ret;
8355
8356 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1);
8357 if (ret != 0) { return ret; }
8358
8359 switch (if_cfg.i2c_i3c_disable)
8360 {
8361 case LSM6DSV16X_I2C_I3C_ENABLE:
8362 *val = LSM6DSV16X_I2C_I3C_ENABLE;
8363 break;
8364
8365 case LSM6DSV16X_I2C_I3C_DISABLE:
8366 *val = LSM6DSV16X_I2C_I3C_DISABLE;
8367 break;
8368
8369 default:
8370 *val = LSM6DSV16X_I2C_I3C_ENABLE;
8371 break;
8372 }
8373
8374 return ret;
8375 }
8376
8377 /**
8378 * @brief SPI Serial Interface Mode selection.[set]
8379 *
8380 * @param ctx read / write interface definitions
8381 * @param val SPI_4_WIRE, SPI_3_WIRE,
8382 * @retval interface status (MANDATORY: return 0 -> no Error)
8383 *
8384 */
lsm6dsv16x_spi_mode_set(stmdev_ctx_t * ctx,lsm6dsv16x_spi_mode_t val)8385 int32_t lsm6dsv16x_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_spi_mode_t val)
8386 {
8387 lsm6dsv16x_if_cfg_t if_cfg;
8388 int32_t ret;
8389
8390 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1);
8391 if (ret == 0)
8392 {
8393 if_cfg.sim = (uint8_t)val & 0x01U;
8394 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1);
8395 }
8396
8397 return ret;
8398 }
8399
8400 /**
8401 * @brief SPI Serial Interface Mode selection.[get]
8402 *
8403 * @param ctx read / write interface definitions
8404 * @param val SPI_4_WIRE, SPI_3_WIRE,
8405 * @retval interface status (MANDATORY: return 0 -> no Error)
8406 *
8407 */
lsm6dsv16x_spi_mode_get(stmdev_ctx_t * ctx,lsm6dsv16x_spi_mode_t * val)8408 int32_t lsm6dsv16x_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_spi_mode_t *val)
8409 {
8410 lsm6dsv16x_if_cfg_t if_cfg;
8411 int32_t ret;
8412
8413 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1);
8414 if (ret != 0) { return ret; }
8415
8416 switch (if_cfg.sim)
8417 {
8418 case LSM6DSV16X_SPI_4_WIRE:
8419 *val = LSM6DSV16X_SPI_4_WIRE;
8420 break;
8421
8422 case LSM6DSV16X_SPI_3_WIRE:
8423 *val = LSM6DSV16X_SPI_3_WIRE;
8424 break;
8425
8426 default:
8427 *val = LSM6DSV16X_SPI_4_WIRE;
8428 break;
8429 }
8430
8431 return ret;
8432 }
8433
8434 /**
8435 * @brief Enables pull-up on SDA pin.[set]
8436 *
8437 * @param ctx read / write interface definitions
8438 * @param val Enables pull-up on SDA pin.
8439 * @retval interface status (MANDATORY: return 0 -> no Error)
8440 *
8441 */
lsm6dsv16x_ui_sda_pull_up_set(stmdev_ctx_t * ctx,uint8_t val)8442 int32_t lsm6dsv16x_ui_sda_pull_up_set(stmdev_ctx_t *ctx, uint8_t val)
8443 {
8444 lsm6dsv16x_if_cfg_t if_cfg;
8445 int32_t ret;
8446
8447 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1);
8448 if (ret == 0)
8449 {
8450 if_cfg.sda_pu_en = val;
8451 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1);
8452 }
8453
8454 return ret;
8455 }
8456
8457 /**
8458 * @brief Enables pull-up on SDA pin.[get]
8459 *
8460 * @param ctx read / write interface definitions
8461 * @param val Enables pull-up on SDA pin.
8462 * @retval interface status (MANDATORY: return 0 -> no Error)
8463 *
8464 */
lsm6dsv16x_ui_sda_pull_up_get(stmdev_ctx_t * ctx,uint8_t * val)8465 int32_t lsm6dsv16x_ui_sda_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val)
8466 {
8467 lsm6dsv16x_if_cfg_t if_cfg;
8468 int32_t ret;
8469
8470 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1);
8471 *val = if_cfg.sda_pu_en;
8472
8473 return ret;
8474 }
8475
8476 /**
8477 * @brief SPI2 (OIS Inteface) Serial Interface Mode selection. This function works also on OIS (UI_CTRL1_OIS = SPI2_CTRL1_OIS).[set]
8478 *
8479 * @param ctx read / write interface definitions
8480 * @param val SPI2_4_WIRE, SPI2_3_WIRE,
8481 * @retval interface status (MANDATORY: return 0 -> no Error)
8482 *
8483 */
lsm6dsv16x_spi2_mode_set(stmdev_ctx_t * ctx,lsm6dsv16x_spi2_mode_t val)8484 int32_t lsm6dsv16x_spi2_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_spi2_mode_t val)
8485 {
8486 lsm6dsv16x_ui_ctrl1_ois_t ui_ctrl1_ois;
8487 int32_t ret;
8488
8489 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1);
8490 if (ret == 0)
8491 {
8492 ui_ctrl1_ois.sim_ois = (uint8_t)val & 0x01U;
8493 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1);
8494 }
8495
8496 return ret;
8497 }
8498
8499 /**
8500 * @brief SPI2 (OIS Inteface) Serial Interface Mode selection. This function works also on OIS (UI_CTRL1_OIS = SPI2_CTRL1_OIS).[get]
8501 *
8502 * @param ctx read / write interface definitions
8503 * @param val SPI2_4_WIRE, SPI2_3_WIRE,
8504 * @retval interface status (MANDATORY: return 0 -> no Error)
8505 *
8506 */
lsm6dsv16x_spi2_mode_get(stmdev_ctx_t * ctx,lsm6dsv16x_spi2_mode_t * val)8507 int32_t lsm6dsv16x_spi2_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_spi2_mode_t *val)
8508 {
8509 lsm6dsv16x_ui_ctrl1_ois_t ui_ctrl1_ois;
8510 int32_t ret;
8511
8512 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1);
8513 if (ret != 0) { return ret; }
8514
8515 switch (ui_ctrl1_ois.sim_ois)
8516 {
8517 case LSM6DSV16X_SPI2_4_WIRE:
8518 *val = LSM6DSV16X_SPI2_4_WIRE;
8519 break;
8520
8521 case LSM6DSV16X_SPI2_3_WIRE:
8522 *val = LSM6DSV16X_SPI2_3_WIRE;
8523 break;
8524
8525 default:
8526 *val = LSM6DSV16X_SPI2_4_WIRE;
8527 break;
8528 }
8529
8530 return ret;
8531 }
8532
8533 /**
8534 * @}
8535 *
8536 */
8537
8538 /**
8539 * @defgroup Significant motion detection
8540 * @brief This section groups all the functions that manage the
8541 * significant motion detection.
8542 * @{
8543 *
8544 */
8545
8546
8547 /**
8548 * @brief Enables significant motion detection function.[set]
8549 *
8550 * @param ctx read / write interface definitions
8551 * @param val Enables significant motion detection function.
8552 * @retval interface status (MANDATORY: return 0 -> no Error)
8553 *
8554 */
lsm6dsv16x_sigmot_mode_set(stmdev_ctx_t * ctx,uint8_t val)8555 int32_t lsm6dsv16x_sigmot_mode_set(stmdev_ctx_t *ctx, uint8_t val)
8556 {
8557 lsm6dsv16x_emb_func_en_a_t emb_func_en_a;
8558 int32_t ret;
8559
8560 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
8561 if (ret != 0) { return ret; }
8562
8563 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
8564 emb_func_en_a.sign_motion_en = val;
8565 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
8566
8567 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
8568
8569 return ret;
8570 }
8571
8572 /**
8573 * @brief Enables significant motion detection function.[get]
8574 *
8575 * @param ctx read / write interface definitions
8576 * @param val Enables significant motion detection function.
8577 * @retval interface status (MANDATORY: return 0 -> no Error)
8578 *
8579 */
lsm6dsv16x_sigmot_mode_get(stmdev_ctx_t * ctx,uint8_t * val)8580 int32_t lsm6dsv16x_sigmot_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
8581 {
8582 lsm6dsv16x_emb_func_en_a_t emb_func_en_a;
8583 int32_t ret;
8584
8585 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
8586 if (ret != 0) { return ret; }
8587
8588 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
8589 *val = emb_func_en_a.sign_motion_en;
8590
8591 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
8592
8593 return ret;
8594 }
8595
8596 /**
8597 * @}
8598 *
8599 */
8600
8601 /**
8602 * @defgroup Step Counter (Pedometer)
8603 * @brief This section groups all the functions that manage pedometer.
8604 * @{
8605 *
8606 */
8607
8608 /**
8609 * @brief Step counter mode[set]
8610 *
8611 * @param ctx read / write interface definitions
8612 * @param val Step counter mode
8613 * @retval interface status (MANDATORY: return 0 -> no Error)
8614 *
8615 */
lsm6dsv16x_stpcnt_mode_set(stmdev_ctx_t * ctx,lsm6dsv16x_stpcnt_mode_t val)8616 int32_t lsm6dsv16x_stpcnt_mode_set(stmdev_ctx_t *ctx,
8617 lsm6dsv16x_stpcnt_mode_t val)
8618 {
8619 lsm6dsv16x_emb_func_en_a_t emb_func_en_a;
8620 lsm6dsv16x_emb_func_en_b_t emb_func_en_b;
8621 lsm6dsv16x_pedo_cmd_reg_t pedo_cmd_reg;
8622 int32_t ret;
8623
8624 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
8625 if (ret != 0) { return ret; }
8626
8627 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
8628 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
8629 if (ret != 0) { goto exit; }
8630
8631 if ((val.false_step_rej == PROPERTY_ENABLE)
8632 && ((emb_func_en_a.mlc_before_fsm_en & emb_func_en_b.mlc_en) ==
8633 PROPERTY_DISABLE))
8634 {
8635 emb_func_en_a.mlc_before_fsm_en = PROPERTY_ENABLE;
8636 }
8637
8638 emb_func_en_a.pedo_en = val.step_counter_enable;
8639 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
8640
8641 exit:
8642 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
8643
8644 if (ret == 0)
8645 {
8646 ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1);
8647 pedo_cmd_reg.fp_rejection_en = val.false_step_rej;
8648 ret += lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1);
8649 }
8650
8651 return ret;
8652 }
8653
8654 /**
8655 * @brief Step counter mode[get]
8656 *
8657 * @param ctx read / write interface definitions
8658 * @param val false_step_rej, step_counter, step_detector,
8659 * @retval interface status (MANDATORY: return 0 -> no Error)
8660 *
8661 */
lsm6dsv16x_stpcnt_mode_get(stmdev_ctx_t * ctx,lsm6dsv16x_stpcnt_mode_t * val)8662 int32_t lsm6dsv16x_stpcnt_mode_get(stmdev_ctx_t *ctx,
8663 lsm6dsv16x_stpcnt_mode_t *val)
8664 {
8665 lsm6dsv16x_emb_func_en_a_t emb_func_en_a;
8666 lsm6dsv16x_pedo_cmd_reg_t pedo_cmd_reg;
8667 int32_t ret;
8668
8669 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
8670 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
8671 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
8672 if (ret != 0) { return ret; }
8673
8674 ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1);
8675 if (ret != 0) { return ret; }
8676
8677 val->false_step_rej = pedo_cmd_reg.fp_rejection_en;
8678 val->step_counter_enable = emb_func_en_a.pedo_en;
8679
8680 return ret;
8681 }
8682
8683 /**
8684 * @brief Step counter output, number of detected steps.[get]
8685 *
8686 * @param ctx read / write interface definitions
8687 * @param val Step counter output, number of detected steps.
8688 * @retval interface status (MANDATORY: return 0 -> no Error)
8689 *
8690 */
lsm6dsv16x_stpcnt_steps_get(stmdev_ctx_t * ctx,uint16_t * val)8691 int32_t lsm6dsv16x_stpcnt_steps_get(stmdev_ctx_t *ctx, uint16_t *val)
8692 {
8693 uint8_t buff[2];
8694 int32_t ret;
8695
8696 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
8697 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_STEP_COUNTER_L, &buff[0], 2);
8698 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
8699 if (ret != 0) { return ret; }
8700
8701 *val = buff[1];
8702 *val = (*val * 256U) + buff[0];
8703
8704 return ret;
8705 }
8706
8707 /**
8708 * @brief Reset step counter.[set]
8709 *
8710 * @param ctx read / write interface definitions
8711 * @param val Reset step counter.
8712 * @retval interface status (MANDATORY: return 0 -> no Error)
8713 *
8714 */
lsm6dsv16x_stpcnt_rst_step_set(stmdev_ctx_t * ctx,uint8_t val)8715 int32_t lsm6dsv16x_stpcnt_rst_step_set(stmdev_ctx_t *ctx, uint8_t val)
8716 {
8717 lsm6dsv16x_emb_func_src_t emb_func_src;
8718 int32_t ret;
8719
8720 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
8721 if (ret != 0) { return ret; }
8722
8723 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1);
8724 if (ret != 0) { goto exit; }
8725
8726 emb_func_src.pedo_rst_step = val;
8727 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1);
8728
8729 exit:
8730 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
8731
8732 return ret;
8733 }
8734
8735 /**
8736 * @brief Reset step counter.[get]
8737 *
8738 * @param ctx read / write interface definitions
8739 * @param val Reset step counter.
8740 * @retval interface status (MANDATORY: return 0 -> no Error)
8741 *
8742 */
lsm6dsv16x_stpcnt_rst_step_get(stmdev_ctx_t * ctx,uint8_t * val)8743 int32_t lsm6dsv16x_stpcnt_rst_step_get(stmdev_ctx_t *ctx, uint8_t *val)
8744 {
8745 lsm6dsv16x_emb_func_src_t emb_func_src;
8746 int32_t ret;
8747
8748 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
8749 if (ret != 0) { return ret; }
8750
8751 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1);
8752 *val = emb_func_src.pedo_rst_step;
8753
8754 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
8755
8756 return ret;
8757 }
8758
8759 /**
8760 * @brief Pedometer debounce configuration.[set]
8761 *
8762 * @param ctx read / write interface definitions
8763 * @param val Pedometer debounce configuration.
8764 * @retval interface status (MANDATORY: return 0 -> no Error)
8765 *
8766 */
lsm6dsv16x_stpcnt_debounce_set(stmdev_ctx_t * ctx,uint8_t val)8767 int32_t lsm6dsv16x_stpcnt_debounce_set(stmdev_ctx_t *ctx, uint8_t val)
8768 {
8769 lsm6dsv16x_pedo_deb_steps_conf_t pedo_deb_steps_conf;
8770 int32_t ret;
8771
8772 ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1);
8773 if (ret == 0)
8774 {
8775 pedo_deb_steps_conf.deb_step = val;
8776 ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1);
8777 }
8778
8779 return ret;
8780 }
8781
8782 /**
8783 * @brief Pedometer debounce configuration.[get]
8784 *
8785 * @param ctx read / write interface definitions
8786 * @param val Pedometer debounce configuration.
8787 * @retval interface status (MANDATORY: return 0 -> no Error)
8788 *
8789 */
lsm6dsv16x_stpcnt_debounce_get(stmdev_ctx_t * ctx,uint8_t * val)8790 int32_t lsm6dsv16x_stpcnt_debounce_get(stmdev_ctx_t *ctx, uint8_t *val)
8791 {
8792 lsm6dsv16x_pedo_deb_steps_conf_t pedo_deb_steps_conf;
8793 int32_t ret;
8794
8795 ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1);
8796 *val = pedo_deb_steps_conf.deb_step;
8797
8798 return ret;
8799 }
8800
8801 /**
8802 * @brief Time period register for step detection on delta time.[set]
8803 *
8804 * @param ctx read / write interface definitions
8805 * @param val Time period register for step detection on delta time.
8806 * @retval interface status (MANDATORY: return 0 -> no Error)
8807 *
8808 */
lsm6dsv16x_stpcnt_period_set(stmdev_ctx_t * ctx,uint16_t val)8809 int32_t lsm6dsv16x_stpcnt_period_set(stmdev_ctx_t *ctx, uint16_t val)
8810 {
8811 uint8_t buff[2];
8812 int32_t ret;
8813
8814 buff[1] = (uint8_t)(val / 256U);
8815 buff[0] = (uint8_t)(val - (buff[1] * 256U));
8816 ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_PEDO_SC_DELTAT_L, (uint8_t *)&buff[0], 2);
8817
8818 return ret;
8819 }
8820
8821 /**
8822 * @brief Time period register for step detection on delta time.[get]
8823 *
8824 * @param ctx read / write interface definitions
8825 * @param val Time period register for step detection on delta time.
8826 * @retval interface status (MANDATORY: return 0 -> no Error)
8827 *
8828 */
lsm6dsv16x_stpcnt_period_get(stmdev_ctx_t * ctx,uint16_t * val)8829 int32_t lsm6dsv16x_stpcnt_period_get(stmdev_ctx_t *ctx, uint16_t *val)
8830 {
8831 uint8_t buff[2];
8832 int32_t ret;
8833
8834 ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_PEDO_SC_DELTAT_L, &buff[0], 2);
8835 if (ret != 0) { return ret; }
8836
8837 *val = buff[1];
8838 *val = (*val * 256U) + buff[0];
8839
8840 return ret;
8841 }
8842
8843 /**
8844 * @}
8845 *
8846 */
8847
8848 /**
8849 * @defgroup Sensor Fusion Low Power (SFLP)
8850 * @brief This section groups all the functions that manage pedometer.
8851 * @{
8852 *
8853 */
8854
8855 /**
8856 * @brief Enable SFLP Game Rotation Vector (6x).[set]
8857 *
8858 * @param ctx read / write interface definitions
8859 * @param val Enable/Disable game rotation value (0/1).
8860 * @retval interface status (MANDATORY: return 0 -> no Error)
8861 *
8862 */
lsm6dsv16x_sflp_game_rotation_set(stmdev_ctx_t * ctx,uint8_t val)8863 int32_t lsm6dsv16x_sflp_game_rotation_set(stmdev_ctx_t *ctx, uint8_t val)
8864 {
8865 lsm6dsv16x_emb_func_en_a_t emb_func_en_a;
8866 int32_t ret;
8867
8868 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
8869 if (ret != 0) { return ret; }
8870
8871 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
8872 if (ret != 0) { goto exit; }
8873
8874 emb_func_en_a.sflp_game_en = val;
8875 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A,
8876 (uint8_t *)&emb_func_en_a, 1);
8877
8878 exit:
8879 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
8880
8881 return ret;
8882 }
8883
8884 /**
8885 * @brief Enable SFLP Game Rotation Vector (6x).[get]
8886 *
8887 * @param ctx read / write interface definitions
8888 * @param val Enable/Disable game rotation value (0/1).
8889 * @retval interface status (MANDATORY: return 0 -> no Error)
8890 *
8891 */
lsm6dsv16x_sflp_game_rotation_get(stmdev_ctx_t * ctx,uint8_t * val)8892 int32_t lsm6dsv16x_sflp_game_rotation_get(stmdev_ctx_t *ctx, uint8_t *val)
8893 {
8894 lsm6dsv16x_emb_func_en_a_t emb_func_en_a;
8895 int32_t ret;
8896
8897 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
8898 if (ret != 0) { return ret; }
8899
8900 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
8901 *val = emb_func_en_a.sflp_game_en;
8902
8903 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
8904
8905 return ret;
8906 }
8907
8908 /**
8909 * @brief SFLP Data Rate (ODR) configuration.[set]
8910 *
8911 * @param ctx read / write interface definitions
8912 * @param val SFLP_15Hz, SFLP_30Hz, SFLP_60Hz, SFLP_120Hz, SFLP_240Hz, SFLP_480Hz
8913 * @retval interface status (MANDATORY: return 0 -> no Error)
8914 *
8915 */
lsm6dsv16x_sflp_data_rate_set(stmdev_ctx_t * ctx,lsm6dsv16x_sflp_data_rate_t val)8916 int32_t lsm6dsv16x_sflp_data_rate_set(stmdev_ctx_t *ctx,
8917 lsm6dsv16x_sflp_data_rate_t val)
8918 {
8919 lsm6dsv16x_sflp_odr_t sflp_odr;
8920 int32_t ret;
8921
8922 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
8923 if (ret != 0) { return ret; }
8924
8925 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SFLP_ODR, (uint8_t *)&sflp_odr, 1);
8926 if (ret != 0) { goto exit; }
8927
8928 sflp_odr.sflp_game_odr = (uint8_t)val & 0x07U;
8929 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SFLP_ODR, (uint8_t *)&sflp_odr, 1);
8930
8931 exit:
8932 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
8933
8934 return ret;
8935 }
8936
8937 /**
8938 * @brief SFLP Data Rate (ODR) configuration.[get]
8939 *
8940 * @param ctx read / write interface definitions
8941 * @param val SFLP_15Hz, SFLP_30Hz, SFLP_60Hz, SFLP_120Hz, SFLP_240Hz, SFLP_480Hz
8942 * @retval interface status (MANDATORY: return 0 -> no Error)
8943 *
8944 */
lsm6dsv16x_sflp_data_rate_get(stmdev_ctx_t * ctx,lsm6dsv16x_sflp_data_rate_t * val)8945 int32_t lsm6dsv16x_sflp_data_rate_get(stmdev_ctx_t *ctx,
8946 lsm6dsv16x_sflp_data_rate_t *val)
8947 {
8948 lsm6dsv16x_sflp_odr_t sflp_odr;
8949 int32_t ret;
8950
8951 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
8952 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SFLP_ODR, (uint8_t *)&sflp_odr, 1);
8953 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
8954 if (ret != 0) { return ret; }
8955
8956 switch (sflp_odr.sflp_game_odr)
8957 {
8958 case LSM6DSV16X_SFLP_15Hz:
8959 *val = LSM6DSV16X_SFLP_15Hz;
8960 break;
8961
8962 case LSM6DSV16X_SFLP_30Hz:
8963 *val = LSM6DSV16X_SFLP_30Hz;
8964 break;
8965
8966 case LSM6DSV16X_SFLP_60Hz:
8967 *val = LSM6DSV16X_SFLP_60Hz;
8968 break;
8969
8970 case LSM6DSV16X_SFLP_120Hz:
8971 *val = LSM6DSV16X_SFLP_120Hz;
8972 break;
8973
8974 case LSM6DSV16X_SFLP_240Hz:
8975 *val = LSM6DSV16X_SFLP_240Hz;
8976 break;
8977
8978 case LSM6DSV16X_SFLP_480Hz:
8979 *val = LSM6DSV16X_SFLP_480Hz;
8980 break;
8981
8982 default:
8983 *val = LSM6DSV16X_SFLP_15Hz;
8984 break;
8985 }
8986
8987 return ret;
8988 }
8989
8990 /**
8991 * @}
8992 *
8993 */
8994
8995 /**
8996 * @defgroup Tap - Double Tap
8997 * @brief This section groups all the functions that manage the
8998 * tap and double tap event generation.
8999 * @{
9000 *
9001 */
9002
9003 /**
9004 * @brief Enable axis for Tap - Double Tap detection.[set]
9005 *
9006 * @param ctx read / write interface definitions
9007 * @param val Enable axis for Tap - Double Tap detection.
9008 * @retval interface status (MANDATORY: return 0 -> no Error)
9009 *
9010 */
lsm6dsv16x_tap_detection_set(stmdev_ctx_t * ctx,lsm6dsv16x_tap_detection_t val)9011 int32_t lsm6dsv16x_tap_detection_set(stmdev_ctx_t *ctx,
9012 lsm6dsv16x_tap_detection_t val)
9013 {
9014 lsm6dsv16x_tap_cfg0_t tap_cfg0;
9015 int32_t ret;
9016
9017 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
9018 if (ret == 0)
9019 {
9020 tap_cfg0.tap_x_en = val.tap_x_en;
9021 tap_cfg0.tap_y_en = val.tap_y_en;
9022 tap_cfg0.tap_z_en = val.tap_z_en;
9023 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
9024 }
9025
9026 return ret;
9027 }
9028
9029 /**
9030 * @brief Enable axis for Tap - Double Tap detection.[get]
9031 *
9032 * @param ctx read / write interface definitions
9033 * @param val Enable axis for Tap - Double Tap detection.
9034 * @retval interface status (MANDATORY: return 0 -> no Error)
9035 *
9036 */
lsm6dsv16x_tap_detection_get(stmdev_ctx_t * ctx,lsm6dsv16x_tap_detection_t * val)9037 int32_t lsm6dsv16x_tap_detection_get(stmdev_ctx_t *ctx,
9038 lsm6dsv16x_tap_detection_t *val)
9039 {
9040 lsm6dsv16x_tap_cfg0_t tap_cfg0;
9041 int32_t ret;
9042
9043 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
9044 if (ret != 0) { return ret; }
9045
9046 val->tap_x_en = tap_cfg0.tap_x_en;
9047 val->tap_y_en = tap_cfg0.tap_y_en;
9048 val->tap_z_en = tap_cfg0.tap_z_en;
9049
9050 return ret;
9051 }
9052
9053 /**
9054 * @brief axis Tap - Double Tap recognition thresholds.[set]
9055 *
9056 * @param ctx read / write interface definitions
9057 * @param val axis Tap - Double Tap recognition thresholds.
9058 * @retval interface status (MANDATORY: return 0 -> no Error)
9059 *
9060 */
lsm6dsv16x_tap_thresholds_set(stmdev_ctx_t * ctx,lsm6dsv16x_tap_thresholds_t val)9061 int32_t lsm6dsv16x_tap_thresholds_set(stmdev_ctx_t *ctx,
9062 lsm6dsv16x_tap_thresholds_t val)
9063 {
9064 lsm6dsv16x_tap_ths_6d_t tap_ths_6d;
9065 lsm6dsv16x_tap_cfg2_t tap_cfg2;
9066 lsm6dsv16x_tap_cfg1_t tap_cfg1;
9067 int32_t ret;
9068
9069 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
9070 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
9071 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
9072 if (ret != 0) { return ret; }
9073
9074 tap_cfg1.tap_ths_x = val.x;
9075 tap_cfg2.tap_ths_y = val.y;
9076 tap_ths_6d.tap_ths_z = val.z;
9077
9078 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
9079 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
9080 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
9081
9082 return ret;
9083 }
9084
9085 /**
9086 * @brief axis Tap - Double Tap recognition thresholds.[get]
9087 *
9088 * @param ctx read / write interface definitions
9089 * @param val axis Tap - Double Tap recognition thresholds.
9090 * @retval interface status (MANDATORY: return 0 -> no Error)
9091 *
9092 */
lsm6dsv16x_tap_thresholds_get(stmdev_ctx_t * ctx,lsm6dsv16x_tap_thresholds_t * val)9093 int32_t lsm6dsv16x_tap_thresholds_get(stmdev_ctx_t *ctx,
9094 lsm6dsv16x_tap_thresholds_t *val)
9095 {
9096 lsm6dsv16x_tap_ths_6d_t tap_ths_6d;
9097 lsm6dsv16x_tap_cfg2_t tap_cfg2;
9098 lsm6dsv16x_tap_cfg1_t tap_cfg1;
9099 int32_t ret;
9100
9101 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
9102 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
9103 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
9104 if (ret != 0) { return ret; }
9105
9106 val->x = tap_cfg1.tap_ths_x;
9107 val->y = tap_cfg2.tap_ths_y;
9108 val->z = tap_ths_6d.tap_ths_z;
9109
9110 return ret;
9111 }
9112
9113 /**
9114 * @brief Selection of axis priority for TAP detection.[set]
9115 *
9116 * @param ctx read / write interface definitions
9117 * @param val XYZ , YXZ , XZY, ZYX , YZX , ZXY ,
9118 * @retval interface status (MANDATORY: return 0 -> no Error)
9119 *
9120 */
lsm6dsv16x_tap_axis_priority_set(stmdev_ctx_t * ctx,lsm6dsv16x_tap_axis_priority_t val)9121 int32_t lsm6dsv16x_tap_axis_priority_set(stmdev_ctx_t *ctx,
9122 lsm6dsv16x_tap_axis_priority_t val)
9123 {
9124 lsm6dsv16x_tap_cfg1_t tap_cfg1;
9125 int32_t ret;
9126
9127 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
9128 if (ret == 0)
9129 {
9130 tap_cfg1.tap_priority = (uint8_t)val & 0x7U;
9131 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
9132 }
9133
9134 return ret;
9135 }
9136
9137 /**
9138 * @brief Selection of axis priority for TAP detection.[get]
9139 *
9140 * @param ctx read / write interface definitions
9141 * @param val XYZ , YXZ , XZY, ZYX , YZX , ZXY ,
9142 * @retval interface status (MANDATORY: return 0 -> no Error)
9143 *
9144 */
lsm6dsv16x_tap_axis_priority_get(stmdev_ctx_t * ctx,lsm6dsv16x_tap_axis_priority_t * val)9145 int32_t lsm6dsv16x_tap_axis_priority_get(stmdev_ctx_t *ctx,
9146 lsm6dsv16x_tap_axis_priority_t *val)
9147 {
9148 lsm6dsv16x_tap_cfg1_t tap_cfg1;
9149 int32_t ret;
9150
9151 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
9152 if (ret != 0) { return ret; }
9153
9154 switch (tap_cfg1.tap_priority)
9155 {
9156 case LSM6DSV16X_XYZ :
9157 *val = LSM6DSV16X_XYZ ;
9158 break;
9159
9160 case LSM6DSV16X_YXZ :
9161 *val = LSM6DSV16X_YXZ ;
9162 break;
9163
9164 case LSM6DSV16X_XZY:
9165 *val = LSM6DSV16X_XZY;
9166 break;
9167
9168 case LSM6DSV16X_ZYX :
9169 *val = LSM6DSV16X_ZYX ;
9170 break;
9171
9172 case LSM6DSV16X_YZX :
9173 *val = LSM6DSV16X_YZX ;
9174 break;
9175
9176 case LSM6DSV16X_ZXY :
9177 *val = LSM6DSV16X_ZXY ;
9178 break;
9179
9180 default:
9181 *val = LSM6DSV16X_XYZ ;
9182 break;
9183 }
9184
9185 return ret;
9186 }
9187
9188 /**
9189 * @brief Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.[set]
9190 *
9191 * @param ctx read / write interface definitions
9192 * @param val Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.
9193 * @retval interface status (MANDATORY: return 0 -> no Error)
9194 *
9195 */
lsm6dsv16x_tap_time_windows_set(stmdev_ctx_t * ctx,lsm6dsv16x_tap_time_windows_t val)9196 int32_t lsm6dsv16x_tap_time_windows_set(stmdev_ctx_t *ctx,
9197 lsm6dsv16x_tap_time_windows_t val)
9198 {
9199 lsm6dsv16x_tap_dur_t tap_dur;
9200 int32_t ret;
9201
9202 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_DUR, (uint8_t *)&tap_dur, 1);
9203 if (ret == 0)
9204 {
9205 tap_dur.shock = val.shock;
9206 tap_dur.quiet = val.quiet;
9207 tap_dur.dur = val.tap_gap;
9208 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_TAP_DUR, (uint8_t *)&tap_dur, 1);
9209 }
9210
9211 return ret;
9212 }
9213
9214 /**
9215 * @brief Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.[get]
9216 *
9217 * @param ctx read / write interface definitions
9218 * @param val Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.
9219 * @retval interface status (MANDATORY: return 0 -> no Error)
9220 *
9221 */
lsm6dsv16x_tap_time_windows_get(stmdev_ctx_t * ctx,lsm6dsv16x_tap_time_windows_t * val)9222 int32_t lsm6dsv16x_tap_time_windows_get(stmdev_ctx_t *ctx,
9223 lsm6dsv16x_tap_time_windows_t *val)
9224 {
9225 lsm6dsv16x_tap_dur_t tap_dur;
9226 int32_t ret;
9227
9228 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_DUR, (uint8_t *)&tap_dur, 1);
9229 if (ret != 0) { return ret; }
9230
9231 val->shock = tap_dur.shock;
9232 val->quiet = tap_dur.quiet;
9233 val->tap_gap = tap_dur.dur;
9234
9235 return ret;
9236 }
9237
9238 /**
9239 * @brief Single/double-tap event enable.[set]
9240 *
9241 * @param ctx read / write interface definitions
9242 * @param val ONLY_SINGLE, BOTH_SINGLE_DOUBLE,
9243 * @retval interface status (MANDATORY: return 0 -> no Error)
9244 *
9245 */
lsm6dsv16x_tap_mode_set(stmdev_ctx_t * ctx,lsm6dsv16x_tap_mode_t val)9246 int32_t lsm6dsv16x_tap_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_tap_mode_t val)
9247 {
9248 lsm6dsv16x_wake_up_ths_t wake_up_ths;
9249 int32_t ret;
9250
9251 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
9252 if (ret == 0)
9253 {
9254 wake_up_ths.single_double_tap = (uint8_t)val & 0x01U;
9255 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
9256 }
9257
9258 return ret;
9259 }
9260
9261 /**
9262 * @brief Single/double-tap event enable.[get]
9263 *
9264 * @param ctx read / write interface definitions
9265 * @param val ONLY_SINGLE, BOTH_SINGLE_DOUBLE,
9266 * @retval interface status (MANDATORY: return 0 -> no Error)
9267 *
9268 */
lsm6dsv16x_tap_mode_get(stmdev_ctx_t * ctx,lsm6dsv16x_tap_mode_t * val)9269 int32_t lsm6dsv16x_tap_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_tap_mode_t *val)
9270 {
9271 lsm6dsv16x_wake_up_ths_t wake_up_ths;
9272 int32_t ret;
9273
9274 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
9275 if (ret != 0) { return ret; }
9276
9277 switch (wake_up_ths.single_double_tap)
9278 {
9279 case LSM6DSV16X_ONLY_SINGLE:
9280 *val = LSM6DSV16X_ONLY_SINGLE;
9281 break;
9282
9283 case LSM6DSV16X_BOTH_SINGLE_DOUBLE:
9284 *val = LSM6DSV16X_BOTH_SINGLE_DOUBLE;
9285 break;
9286
9287 default:
9288 *val = LSM6DSV16X_ONLY_SINGLE;
9289 break;
9290 }
9291
9292 return ret;
9293 }
9294
9295 /**
9296 * @}
9297 *
9298 */
9299
9300 /**
9301 * @defgroup Tilt detection
9302 * @brief This section groups all the functions that manage the tilt
9303 * event detection.
9304 * @{
9305 *
9306 */
9307
9308 /**
9309 * @brief Tilt calculation.[set]
9310 *
9311 * @param ctx read / write interface definitions
9312 * @param val Tilt calculation.
9313 * @retval interface status (MANDATORY: return 0 -> no Error)
9314 *
9315 */
lsm6dsv16x_tilt_mode_set(stmdev_ctx_t * ctx,uint8_t val)9316 int32_t lsm6dsv16x_tilt_mode_set(stmdev_ctx_t *ctx, uint8_t val)
9317 {
9318 lsm6dsv16x_emb_func_en_a_t emb_func_en_a;
9319 int32_t ret;
9320
9321 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
9322 if (ret != 0) { return ret; }
9323
9324 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
9325 emb_func_en_a.tilt_en = val;
9326 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
9327
9328 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
9329
9330 return ret;
9331 }
9332
9333 /**
9334 * @brief Tilt calculation.[get]
9335 *
9336 * @param ctx read / write interface definitions
9337 * @param val Tilt calculation.
9338 * @retval interface status (MANDATORY: return 0 -> no Error)
9339 *
9340 */
lsm6dsv16x_tilt_mode_get(stmdev_ctx_t * ctx,uint8_t * val)9341 int32_t lsm6dsv16x_tilt_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
9342 {
9343 lsm6dsv16x_emb_func_en_a_t emb_func_en_a;
9344 int32_t ret;
9345
9346 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
9347 if (ret != 0) { return ret; }
9348
9349 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
9350 *val = emb_func_en_a.tilt_en;
9351
9352 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
9353
9354 return ret;
9355 }
9356
9357 /**
9358 * @}
9359 *
9360 */
9361
9362 /**
9363 * @defgroup Timestamp
9364 * @brief This section groups all the functions that manage the
9365 * timestamp generation.
9366 * @{
9367 *
9368 */
9369
9370 /**
9371 * @brief Timestamp data output.[get]
9372 *
9373 * @param ctx read / write interface definitions
9374 * @param val Timestamp data output.
9375 * @retval interface status (MANDATORY: return 0 -> no Error)
9376 *
9377 */
lsm6dsv16x_timestamp_raw_get(stmdev_ctx_t * ctx,uint32_t * val)9378 int32_t lsm6dsv16x_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val)
9379 {
9380 uint8_t buff[4];
9381 int32_t ret;
9382
9383 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TIMESTAMP0, &buff[0], 4);
9384 if (ret != 0) { return ret; }
9385
9386 *val = buff[3];
9387 *val = (*val * 256U) + buff[2];
9388 *val = (*val * 256U) + buff[1];
9389 *val = (*val * 256U) + buff[0];
9390
9391 return ret;
9392 }
9393
9394 /**
9395 * @brief Enables timestamp counter.[set]
9396 *
9397 * @param ctx read / write interface definitions
9398 * @param val Enables timestamp counter.
9399 * @retval interface status (MANDATORY: return 0 -> no Error)
9400 *
9401 */
lsm6dsv16x_timestamp_set(stmdev_ctx_t * ctx,uint8_t val)9402 int32_t lsm6dsv16x_timestamp_set(stmdev_ctx_t *ctx, uint8_t val)
9403 {
9404 lsm6dsv16x_functions_enable_t functions_enable;
9405 int32_t ret;
9406
9407 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
9408 if (ret == 0)
9409 {
9410 functions_enable.timestamp_en = val;
9411 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
9412 }
9413
9414 return ret;
9415 }
9416
9417 /**
9418 * @brief Enables timestamp counter.[get]
9419 *
9420 * @param ctx read / write interface definitions
9421 * @param val Enables timestamp counter.
9422 * @retval interface status (MANDATORY: return 0 -> no Error)
9423 *
9424 */
lsm6dsv16x_timestamp_get(stmdev_ctx_t * ctx,uint8_t * val)9425 int32_t lsm6dsv16x_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val)
9426 {
9427 lsm6dsv16x_functions_enable_t functions_enable;
9428 int32_t ret;
9429
9430 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
9431 *val = functions_enable.timestamp_en;
9432
9433 return ret;
9434 }
9435
9436 /**
9437 * @}
9438 *
9439 */
9440
9441 /**
9442 * @defgroup Wake Up - Activity - Inactivity (Sleep)
9443 * @brief This section groups all the functions that manage the Wake Up
9444 * event generation.
9445 * @{
9446 *
9447 */
9448
9449 /**
9450 * @brief Enable activity/inactivity (sleep) function.[set]
9451 *
9452 * @param ctx read / write interface definitions
9453 * @param val XL_AND_GY_NOT_AFFECTED, XL_LOW_POWER_GY_NOT_AFFECTED, XL_LOW_POWER_GY_SLEEP, XL_LOW_POWER_GY_POWER_DOWN,
9454 * @retval interface status (MANDATORY: return 0 -> no Error)
9455 *
9456 */
lsm6dsv16x_act_mode_set(stmdev_ctx_t * ctx,lsm6dsv16x_act_mode_t val)9457 int32_t lsm6dsv16x_act_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_act_mode_t val)
9458 {
9459 lsm6dsv16x_functions_enable_t functions_enable;
9460 int32_t ret;
9461
9462 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
9463 if (ret == 0)
9464 {
9465 functions_enable.inact_en = (uint8_t)val & 0x3U;
9466 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
9467 }
9468
9469 return ret;
9470 }
9471
9472 /**
9473 * @brief Enable activity/inactivity (sleep) function.[get]
9474 *
9475 * @param ctx read / write interface definitions
9476 * @param val XL_AND_GY_NOT_AFFECTED, XL_LOW_POWER_GY_NOT_AFFECTED, XL_LOW_POWER_GY_SLEEP, XL_LOW_POWER_GY_POWER_DOWN,
9477 * @retval interface status (MANDATORY: return 0 -> no Error)
9478 *
9479 */
lsm6dsv16x_act_mode_get(stmdev_ctx_t * ctx,lsm6dsv16x_act_mode_t * val)9480 int32_t lsm6dsv16x_act_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_act_mode_t *val)
9481 {
9482 lsm6dsv16x_functions_enable_t functions_enable;
9483 int32_t ret;
9484
9485 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
9486 if (ret != 0) { return ret; }
9487
9488 switch (functions_enable.inact_en)
9489 {
9490 case LSM6DSV16X_XL_AND_GY_NOT_AFFECTED:
9491 *val = LSM6DSV16X_XL_AND_GY_NOT_AFFECTED;
9492 break;
9493
9494 case LSM6DSV16X_XL_LOW_POWER_GY_NOT_AFFECTED:
9495 *val = LSM6DSV16X_XL_LOW_POWER_GY_NOT_AFFECTED;
9496 break;
9497
9498 case LSM6DSV16X_XL_LOW_POWER_GY_SLEEP:
9499 *val = LSM6DSV16X_XL_LOW_POWER_GY_SLEEP;
9500 break;
9501
9502 case LSM6DSV16X_XL_LOW_POWER_GY_POWER_DOWN:
9503 *val = LSM6DSV16X_XL_LOW_POWER_GY_POWER_DOWN;
9504 break;
9505
9506 default:
9507 *val = LSM6DSV16X_XL_AND_GY_NOT_AFFECTED;
9508 break;
9509 }
9510
9511 return ret;
9512 }
9513
9514 /**
9515 * @brief Duration in the transition from Stationary to Motion (from Inactivity to Activity).[set]
9516 *
9517 * @param ctx read / write interface definitions
9518 * @param val SLEEP_TO_ACT_AT_1ST_SAMPLE, SLEEP_TO_ACT_AT_2ND_SAMPLE, SLEEP_TO_ACT_AT_3RD_SAMPLE, SLEEP_TO_ACT_AT_4th_SAMPLE,
9519 * @retval interface status (MANDATORY: return 0 -> no Error)
9520 *
9521 */
lsm6dsv16x_act_from_sleep_to_act_dur_set(stmdev_ctx_t * ctx,lsm6dsv16x_act_from_sleep_to_act_dur_t val)9522 int32_t lsm6dsv16x_act_from_sleep_to_act_dur_set(stmdev_ctx_t *ctx,
9523 lsm6dsv16x_act_from_sleep_to_act_dur_t val)
9524 {
9525 lsm6dsv16x_inactivity_dur_t inactivity_dur;
9526 int32_t ret;
9527
9528 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
9529 if (ret == 0)
9530 {
9531 inactivity_dur.inact_dur = (uint8_t)val & 0x3U;
9532 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
9533 }
9534
9535 return ret;
9536 }
9537
9538 /**
9539 * @brief Duration in the transition from Stationary to Motion (from Inactivity to Activity).[get]
9540 *
9541 * @param ctx read / write interface definitions
9542 * @param val SLEEP_TO_ACT_AT_1ST_SAMPLE, SLEEP_TO_ACT_AT_2ND_SAMPLE, SLEEP_TO_ACT_AT_3RD_SAMPLE, SLEEP_TO_ACT_AT_4th_SAMPLE,
9543 * @retval interface status (MANDATORY: return 0 -> no Error)
9544 *
9545 */
lsm6dsv16x_act_from_sleep_to_act_dur_get(stmdev_ctx_t * ctx,lsm6dsv16x_act_from_sleep_to_act_dur_t * val)9546 int32_t lsm6dsv16x_act_from_sleep_to_act_dur_get(stmdev_ctx_t *ctx,
9547 lsm6dsv16x_act_from_sleep_to_act_dur_t *val)
9548 {
9549 lsm6dsv16x_inactivity_dur_t inactivity_dur;
9550 int32_t ret;
9551
9552 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
9553 if (ret != 0) { return ret; }
9554
9555 switch (inactivity_dur.inact_dur)
9556 {
9557 case LSM6DSV16X_SLEEP_TO_ACT_AT_1ST_SAMPLE:
9558 *val = LSM6DSV16X_SLEEP_TO_ACT_AT_1ST_SAMPLE;
9559 break;
9560
9561 case LSM6DSV16X_SLEEP_TO_ACT_AT_2ND_SAMPLE:
9562 *val = LSM6DSV16X_SLEEP_TO_ACT_AT_2ND_SAMPLE;
9563 break;
9564
9565 case LSM6DSV16X_SLEEP_TO_ACT_AT_3RD_SAMPLE:
9566 *val = LSM6DSV16X_SLEEP_TO_ACT_AT_3RD_SAMPLE;
9567 break;
9568
9569 case LSM6DSV16X_SLEEP_TO_ACT_AT_4th_SAMPLE:
9570 *val = LSM6DSV16X_SLEEP_TO_ACT_AT_4th_SAMPLE;
9571 break;
9572
9573 default:
9574 *val = LSM6DSV16X_SLEEP_TO_ACT_AT_1ST_SAMPLE;
9575 break;
9576 }
9577
9578 return ret;
9579 }
9580
9581 /**
9582 * @brief Selects the accelerometer data rate during Inactivity.[set]
9583 *
9584 * @param ctx read / write interface definitions
9585 * @param val 1Hz875, 15Hz, 30Hz, 60Hz,
9586 * @retval interface status (MANDATORY: return 0 -> no Error)
9587 *
9588 */
lsm6dsv16x_act_sleep_xl_odr_set(stmdev_ctx_t * ctx,lsm6dsv16x_act_sleep_xl_odr_t val)9589 int32_t lsm6dsv16x_act_sleep_xl_odr_set(stmdev_ctx_t *ctx,
9590 lsm6dsv16x_act_sleep_xl_odr_t val)
9591 {
9592 lsm6dsv16x_inactivity_dur_t inactivity_dur;
9593 int32_t ret;
9594
9595 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
9596 if (ret == 0)
9597 {
9598 inactivity_dur.xl_inact_odr = (uint8_t)val & 0x03U;
9599 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
9600 }
9601
9602 return ret;
9603 }
9604
9605 /**
9606 * @brief Selects the accelerometer data rate during Inactivity.[get]
9607 *
9608 * @param ctx read / write interface definitions
9609 * @param val 1Hz875, 15Hz, 30Hz, 60Hz,
9610 * @retval interface status (MANDATORY: return 0 -> no Error)
9611 *
9612 */
lsm6dsv16x_act_sleep_xl_odr_get(stmdev_ctx_t * ctx,lsm6dsv16x_act_sleep_xl_odr_t * val)9613 int32_t lsm6dsv16x_act_sleep_xl_odr_get(stmdev_ctx_t *ctx,
9614 lsm6dsv16x_act_sleep_xl_odr_t *val)
9615 {
9616 lsm6dsv16x_inactivity_dur_t inactivity_dur;
9617 int32_t ret;
9618
9619 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
9620 if (ret != 0) { return ret; }
9621
9622 switch (inactivity_dur.xl_inact_odr)
9623 {
9624 case LSM6DSV16X_1Hz875:
9625 *val = LSM6DSV16X_1Hz875;
9626 break;
9627
9628 case LSM6DSV16X_15Hz:
9629 *val = LSM6DSV16X_15Hz;
9630 break;
9631
9632 case LSM6DSV16X_30Hz:
9633 *val = LSM6DSV16X_30Hz;
9634 break;
9635
9636 case LSM6DSV16X_60Hz:
9637 *val = LSM6DSV16X_60Hz;
9638 break;
9639
9640 default:
9641 *val = LSM6DSV16X_1Hz875;
9642 break;
9643 }
9644
9645 return ret;
9646 }
9647
9648 /**
9649 * @brief Wakeup and activity/inactivity threshold.[set]
9650 *
9651 * @param ctx read / write interface definitions
9652 * @param val Wakeup and activity/inactivity threshold.
9653 * @retval interface status (MANDATORY: return 0 -> no Error)
9654 *
9655 */
lsm6dsv16x_act_thresholds_set(stmdev_ctx_t * ctx,lsm6dsv16x_act_thresholds_t * val)9656 int32_t lsm6dsv16x_act_thresholds_set(stmdev_ctx_t *ctx,
9657 lsm6dsv16x_act_thresholds_t *val)
9658 {
9659 lsm6dsv16x_inactivity_ths_t inactivity_ths;
9660 lsm6dsv16x_inactivity_dur_t inactivity_dur;
9661 lsm6dsv16x_wake_up_ths_t wake_up_ths;
9662 lsm6dsv16x_wake_up_dur_t wake_up_dur;
9663 int32_t ret;
9664
9665 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
9666 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1);
9667 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
9668 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
9669 if (ret != 0) { return ret; }
9670
9671 inactivity_dur.wu_inact_ths_w = val->inactivity_cfg.wu_inact_ths_w;
9672 inactivity_dur.xl_inact_odr = val->inactivity_cfg.xl_inact_odr;
9673 inactivity_dur.inact_dur = val->inactivity_cfg.inact_dur;
9674
9675 inactivity_ths.inact_ths = val->inactivity_ths;
9676 wake_up_ths.wk_ths = val->threshold;
9677 wake_up_dur.wake_dur = val->duration;
9678
9679 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
9680 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1);
9681 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
9682 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
9683
9684 return ret;
9685 }
9686
9687 /**
9688 * @brief Wakeup and activity/inactivity threshold.[get]
9689 *
9690 * @param ctx read / write interface definitions
9691 * @param val Wakeup and activity/inactivity threshold.
9692 * @retval interface status (MANDATORY: return 0 -> no Error)
9693 *
9694 */
lsm6dsv16x_act_thresholds_get(stmdev_ctx_t * ctx,lsm6dsv16x_act_thresholds_t * val)9695 int32_t lsm6dsv16x_act_thresholds_get(stmdev_ctx_t *ctx,
9696 lsm6dsv16x_act_thresholds_t *val)
9697 {
9698 lsm6dsv16x_inactivity_dur_t inactivity_dur;
9699 lsm6dsv16x_inactivity_ths_t inactivity_ths;
9700 lsm6dsv16x_wake_up_ths_t wake_up_ths;
9701 lsm6dsv16x_wake_up_dur_t wake_up_dur;
9702 int32_t ret;
9703
9704 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
9705 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1);
9706 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
9707 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
9708 if (ret != 0) { return ret; }
9709
9710 val->inactivity_cfg.wu_inact_ths_w = inactivity_dur.wu_inact_ths_w;
9711 val->inactivity_cfg.xl_inact_odr = inactivity_dur.xl_inact_odr;
9712 val->inactivity_cfg.inact_dur = inactivity_dur.inact_dur;
9713
9714 val->inactivity_ths = inactivity_ths.inact_ths;
9715 val->threshold = wake_up_ths.wk_ths;
9716 val->duration = wake_up_dur.wake_dur;
9717
9718 return ret;
9719 }
9720
9721 /**
9722 * @brief Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. [set]
9723 *
9724 * @param ctx read / write interface definitions
9725 * @param val Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time.
9726 * @retval interface status (MANDATORY: return 0 -> no Error)
9727 *
9728 */
lsm6dsv16x_act_wkup_time_windows_set(stmdev_ctx_t * ctx,lsm6dsv16x_act_wkup_time_windows_t val)9729 int32_t lsm6dsv16x_act_wkup_time_windows_set(stmdev_ctx_t *ctx,
9730 lsm6dsv16x_act_wkup_time_windows_t val)
9731 {
9732 lsm6dsv16x_wake_up_dur_t wake_up_dur;
9733 int32_t ret;
9734
9735 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
9736 if (ret == 0)
9737 {
9738 wake_up_dur.wake_dur = val.shock;
9739 wake_up_dur.sleep_dur = val.quiet;
9740 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
9741 }
9742
9743 return ret;
9744 }
9745
9746 /**
9747 * @brief Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. [get]
9748 *
9749 * @param ctx read / write interface definitions
9750 * @param val Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time.
9751 * @retval interface status (MANDATORY: return 0 -> no Error)
9752 *
9753 */
lsm6dsv16x_act_wkup_time_windows_get(stmdev_ctx_t * ctx,lsm6dsv16x_act_wkup_time_windows_t * val)9754 int32_t lsm6dsv16x_act_wkup_time_windows_get(stmdev_ctx_t *ctx,
9755 lsm6dsv16x_act_wkup_time_windows_t *val)
9756 {
9757 lsm6dsv16x_wake_up_dur_t wake_up_dur;
9758 int32_t ret;
9759
9760 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
9761 if (ret != 0) { return ret; }
9762
9763 val->shock = wake_up_dur.wake_dur;
9764 val->quiet = wake_up_dur.sleep_dur;
9765
9766 return ret;
9767 }
9768
9769 /**
9770 * @}
9771 *
9772 */
9773
