1 /** 2 ****************************************************************************** 3 * @file lsm6dsm_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * lsm6dsm_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef LSM6DSM_REGS_H 23 #define LSM6DSM_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup LSM6DSM 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 71 /** @defgroup STMicroelectronics sensors common types 72 * @{ 73 * 74 */ 75 76 #ifndef MEMS_SHARED_TYPES 77 #define MEMS_SHARED_TYPES 78 79 typedef struct 80 { 81 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 82 uint8_t bit0 : 1; 83 uint8_t bit1 : 1; 84 uint8_t bit2 : 1; 85 uint8_t bit3 : 1; 86 uint8_t bit4 : 1; 87 uint8_t bit5 : 1; 88 uint8_t bit6 : 1; 89 uint8_t bit7 : 1; 90 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 91 uint8_t bit7 : 1; 92 uint8_t bit6 : 1; 93 uint8_t bit5 : 1; 94 uint8_t bit4 : 1; 95 uint8_t bit3 : 1; 96 uint8_t bit2 : 1; 97 uint8_t bit1 : 1; 98 uint8_t bit0 : 1; 99 #endif /* DRV_BYTE_ORDER */ 100 } bitwise_t; 101 102 #define PROPERTY_DISABLE (0U) 103 #define PROPERTY_ENABLE (1U) 104 105 /** @addtogroup Interfaces_Functions 106 * @brief This section provide a set of functions used to read and 107 * write a generic register of the device. 108 * MANDATORY: return 0 -> no Error. 109 * @{ 110 * 111 */ 112 113 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 114 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 115 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 116 117 typedef struct 118 { 119 /** Component mandatory fields **/ 120 stmdev_write_ptr write_reg; 121 stmdev_read_ptr read_reg; 122 /** Component optional fields **/ 123 stmdev_mdelay_ptr mdelay; 124 /** Customizable optional pointer **/ 125 void *handle; 126 } stmdev_ctx_t; 127 128 /** 129 * @} 130 * 131 */ 132 133 #endif /* MEMS_SHARED_TYPES */ 134 135 #ifndef MEMS_UCF_SHARED_TYPES 136 #define MEMS_UCF_SHARED_TYPES 137 138 /** @defgroup Generic address-data structure definition 139 * @brief This structure is useful to load a predefined configuration 140 * of a sensor. 141 * You can create a sensor configuration by your own or using 142 * Unico / Unicleo tools available on STMicroelectronics 143 * web site. 144 * 145 * @{ 146 * 147 */ 148 149 typedef struct 150 { 151 uint8_t address; 152 uint8_t data; 153 } ucf_line_t; 154 155 /** 156 * @} 157 * 158 */ 159 160 #endif /* MEMS_UCF_SHARED_TYPES */ 161 162 /** 163 * @} 164 * 165 */ 166 167 /** @defgroup LSM6DSM_Infos 168 * @{ 169 * 170 */ 171 172 /** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ 173 #define LSM6DSM_I2C_ADD_L 0xD5U 174 #define LSM6DSM_I2C_ADD_H 0xD7U 175 176 /** Device Identification (Who am I) **/ 177 #define LSM6DSM_ID 0x6AU 178 179 /** 180 * @} 181 * 182 */ 183 184 #define LSM6DSM_FUNC_CFG_ACCESS 0x01U 185 typedef struct 186 { 187 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 188 uint8_t not_used_01 : 5; 189 uint8_t func_cfg_en : 190 3; /* func_cfg_en + func_cfg_en_b */ 191 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 192 uint8_t func_cfg_en : 193 3; /* func_cfg_en + func_cfg_en_b */ 194 uint8_t not_used_01 : 5; 195 #endif /* DRV_BYTE_ORDER */ 196 } lsm6dsm_func_cfg_access_t; 197 198 #define LSM6DSM_SENSOR_SYNC_TIME_FRAME 0x04U 199 typedef struct 200 { 201 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 202 uint8_t tph : 4; 203 uint8_t not_used_01 : 4; 204 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 205 uint8_t not_used_01 : 4; 206 uint8_t tph : 4; 207 #endif /* DRV_BYTE_ORDER */ 208 } lsm6dsm_sensor_sync_time_frame_t; 209 210 #define LSM6DSM_SENSOR_SYNC_RES_RATIO 0x05U 211 typedef struct 212 { 213 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 214 uint8_t rr : 2; 215 uint8_t not_used_01 : 6; 216 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 217 uint8_t not_used_01 : 6; 218 uint8_t rr : 2; 219 #endif /* DRV_BYTE_ORDER */ 220 } lsm6dsm_sensor_sync_res_ratio_t; 221 222 #define LSM6DSM_FIFO_CTRL1 0x06U 223 typedef struct 224 { 225 uint8_t fth : 8; /* + FIFO_CTRL2(fth) */ 226 } lsm6dsm_fifo_ctrl1_t; 227 228 #define LSM6DSM_FIFO_CTRL2 0x07U 229 typedef struct 230 { 231 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 232 uint8_t fth : 3; /* + FIFO_CTRL1(fth) */ 233 uint8_t fifo_temp_en : 1; 234 uint8_t not_used_01 : 2; 235 uint8_t timer_pedo_fifo_drdy : 1; 236 uint8_t timer_pedo_fifo_en : 1; 237 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 238 uint8_t timer_pedo_fifo_en : 1; 239 uint8_t timer_pedo_fifo_drdy : 1; 240 uint8_t not_used_01 : 2; 241 uint8_t fifo_temp_en : 1; 242 uint8_t fth : 3; /* + FIFO_CTRL1(fth) */ 243 #endif /* DRV_BYTE_ORDER */ 244 } lsm6dsm_fifo_ctrl2_t; 245 246 #define LSM6DSM_FIFO_CTRL3 0x08U 247 typedef struct 248 { 249 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 250 uint8_t dec_fifo_xl : 3; 251 uint8_t dec_fifo_gyro : 3; 252 uint8_t not_used_01 : 2; 253 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 254 uint8_t not_used_01 : 2; 255 uint8_t dec_fifo_gyro : 3; 256 uint8_t dec_fifo_xl : 3; 257 #endif /* DRV_BYTE_ORDER */ 258 } lsm6dsm_fifo_ctrl3_t; 259 260 #define LSM6DSM_FIFO_CTRL4 0x09U 261 typedef struct 262 { 263 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 264 uint8_t dec_ds3_fifo : 3; 265 uint8_t dec_ds4_fifo : 3; 266 uint8_t only_high_data : 1; 267 uint8_t stop_on_fth : 1; 268 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 269 uint8_t stop_on_fth : 1; 270 uint8_t only_high_data : 1; 271 uint8_t dec_ds4_fifo : 3; 272 uint8_t dec_ds3_fifo : 3; 273 #endif /* DRV_BYTE_ORDER */ 274 } lsm6dsm_fifo_ctrl4_t; 275 276 #define LSM6DSM_FIFO_CTRL5 0x0AU 277 typedef struct 278 { 279 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 280 uint8_t fifo_mode : 3; 281 uint8_t odr_fifo : 4; 282 uint8_t not_used_01 : 1; 283 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 284 uint8_t not_used_01 : 1; 285 uint8_t odr_fifo : 4; 286 uint8_t fifo_mode : 3; 287 #endif /* DRV_BYTE_ORDER */ 288 } lsm6dsm_fifo_ctrl5_t; 289 290 #define LSM6DSM_DRDY_PULSE_CFG 0x0BU 291 typedef struct 292 { 293 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 294 uint8_t int2_wrist_tilt : 1; 295 uint8_t not_used_01 : 6; 296 uint8_t drdy_pulsed : 1; 297 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 298 uint8_t drdy_pulsed : 1; 299 uint8_t not_used_01 : 6; 300 uint8_t int2_wrist_tilt : 1; 301 #endif /* DRV_BYTE_ORDER */ 302 } lsm6dsm_drdy_pulse_cfg_t; 303 304 #define LSM6DSM_INT1_CTRL 0x0DU 305 typedef struct 306 { 307 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 308 uint8_t int1_drdy_xl : 1; 309 uint8_t int1_drdy_g : 1; 310 uint8_t int1_boot : 1; 311 uint8_t int1_fth : 1; 312 uint8_t int1_fifo_ovr : 1; 313 uint8_t int1_full_flag : 1; 314 uint8_t int1_sign_mot : 1; 315 uint8_t int1_step_detector : 1; 316 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 317 uint8_t int1_step_detector : 1; 318 uint8_t int1_sign_mot : 1; 319 uint8_t int1_full_flag : 1; 320 uint8_t int1_fifo_ovr : 1; 321 uint8_t int1_fth : 1; 322 uint8_t int1_boot : 1; 323 uint8_t int1_drdy_g : 1; 324 uint8_t int1_drdy_xl : 1; 325 #endif /* DRV_BYTE_ORDER */ 326 } lsm6dsm_int1_ctrl_t; 327 328 #define LSM6DSM_INT2_CTRL 0x0EU 329 typedef struct 330 { 331 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 332 uint8_t int2_drdy_xl : 1; 333 uint8_t int2_drdy_g : 1; 334 uint8_t int2_drdy_temp : 1; 335 uint8_t int2_fth : 1; 336 uint8_t int2_fifo_ovr : 1; 337 uint8_t int2_full_flag : 1; 338 uint8_t int2_step_count_ov : 1; 339 uint8_t int2_step_delta : 1; 340 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 341 uint8_t int2_step_delta : 1; 342 uint8_t int2_step_count_ov : 1; 343 uint8_t int2_full_flag : 1; 344 uint8_t int2_fifo_ovr : 1; 345 uint8_t int2_fth : 1; 346 uint8_t int2_drdy_temp : 1; 347 uint8_t int2_drdy_g : 1; 348 uint8_t int2_drdy_xl : 1; 349 #endif /* DRV_BYTE_ORDER */ 350 } lsm6dsm_int2_ctrl_t; 351 352 #define LSM6DSM_WHO_AM_I 0x0FU 353 #define LSM6DSM_CTRL1_XL 0x10U 354 typedef struct 355 { 356 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 357 uint8_t bw0_xl : 1; 358 uint8_t lpf1_bw_sel : 1; 359 uint8_t fs_xl : 2; 360 uint8_t odr_xl : 4; 361 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 362 uint8_t odr_xl : 4; 363 uint8_t fs_xl : 2; 364 uint8_t lpf1_bw_sel : 1; 365 uint8_t bw0_xl : 1; 366 #endif /* DRV_BYTE_ORDER */ 367 } lsm6dsm_ctrl1_xl_t; 368 369 #define LSM6DSM_CTRL2_G 0x11U 370 typedef struct 371 { 372 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 373 uint8_t not_used_01 : 1; 374 uint8_t fs_g : 3; /* fs_g + fs_125 */ 375 uint8_t odr_g : 4; 376 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 377 uint8_t odr_g : 4; 378 uint8_t fs_g : 3; /* fs_g + fs_125 */ 379 uint8_t not_used_01 : 1; 380 #endif /* DRV_BYTE_ORDER */ 381 } lsm6dsm_ctrl2_g_t; 382 383 #define LSM6DSM_CTRL3_C 0x12U 384 typedef struct 385 { 386 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 387 uint8_t sw_reset : 1; 388 uint8_t ble : 1; 389 uint8_t if_inc : 1; 390 uint8_t sim : 1; 391 uint8_t pp_od : 1; 392 uint8_t h_lactive : 1; 393 uint8_t bdu : 1; 394 uint8_t boot : 1; 395 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 396 uint8_t boot : 1; 397 uint8_t bdu : 1; 398 uint8_t h_lactive : 1; 399 uint8_t pp_od : 1; 400 uint8_t sim : 1; 401 uint8_t if_inc : 1; 402 uint8_t ble : 1; 403 uint8_t sw_reset : 1; 404 #endif /* DRV_BYTE_ORDER */ 405 } lsm6dsm_ctrl3_c_t; 406 407 #define LSM6DSM_CTRL4_C 0x13U 408 typedef struct 409 { 410 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 411 uint8_t not_used_01 : 1; 412 uint8_t lpf1_sel_g : 1; 413 uint8_t i2c_disable : 1; 414 uint8_t drdy_mask : 1; 415 uint8_t den_drdy_int1 : 1; 416 uint8_t int2_on_int1 : 1; 417 uint8_t sleep : 1; 418 uint8_t den_xl_en : 1; 419 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 420 uint8_t den_xl_en : 1; 421 uint8_t sleep : 1; 422 uint8_t int2_on_int1 : 1; 423 uint8_t den_drdy_int1 : 1; 424 uint8_t drdy_mask : 1; 425 uint8_t i2c_disable : 1; 426 uint8_t lpf1_sel_g : 1; 427 uint8_t not_used_01 : 1; 428 #endif /* DRV_BYTE_ORDER */ 429 } lsm6dsm_ctrl4_c_t; 430 431 #define LSM6DSM_CTRL5_C 0x14U 432 typedef struct 433 { 434 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 435 uint8_t st_xl : 2; 436 uint8_t st_g : 2; 437 uint8_t den_lh : 1; 438 uint8_t rounding : 3; 439 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 440 uint8_t rounding : 3; 441 uint8_t den_lh : 1; 442 uint8_t st_g : 2; 443 uint8_t st_xl : 2; 444 #endif /* DRV_BYTE_ORDER */ 445 } lsm6dsm_ctrl5_c_t; 446 447 #define LSM6DSM_CTRL6_C 0x15U 448 typedef struct 449 { 450 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 451 uint8_t ftype : 2; 452 uint8_t not_used_01 : 1; 453 uint8_t usr_off_w : 1; 454 uint8_t xl_hm_mode : 1; 455 uint8_t den_mode : 456 3; /* trig_en + lvl_en + lvl2_en */ 457 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 458 uint8_t den_mode : 459 3; /* trig_en + lvl_en + lvl2_en */ 460 uint8_t xl_hm_mode : 1; 461 uint8_t usr_off_w : 1; 462 uint8_t not_used_01 : 1; 463 uint8_t ftype : 2; 464 #endif /* DRV_BYTE_ORDER */ 465 } lsm6dsm_ctrl6_c_t; 466 467 #define LSM6DSM_CTRL7_G 0x16U 468 typedef struct 469 { 470 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 471 uint8_t not_used_01 : 2; 472 uint8_t rounding_status : 1; 473 uint8_t not_used_02 : 1; 474 uint8_t hpm_g : 2; 475 uint8_t hp_en_g : 1; 476 uint8_t g_hm_mode : 1; 477 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 478 uint8_t g_hm_mode : 1; 479 uint8_t hp_en_g : 1; 480 uint8_t hpm_g : 2; 481 uint8_t not_used_02 : 1; 482 uint8_t rounding_status : 1; 483 uint8_t not_used_01 : 2; 484 #endif /* DRV_BYTE_ORDER */ 485 } lsm6dsm_ctrl7_g_t; 486 487 #define LSM6DSM_CTRL8_XL 0x17U 488 typedef struct 489 { 490 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 491 uint8_t low_pass_on_6d : 1; 492 uint8_t not_used_01 : 1; 493 uint8_t hp_slope_xl_en : 1; 494 uint8_t input_composite : 1; 495 uint8_t hp_ref_mode : 1; 496 uint8_t hpcf_xl : 2; 497 uint8_t lpf2_xl_en : 1; 498 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 499 uint8_t lpf2_xl_en : 1; 500 uint8_t hpcf_xl : 2; 501 uint8_t hp_ref_mode : 1; 502 uint8_t input_composite : 1; 503 uint8_t hp_slope_xl_en : 1; 504 uint8_t not_used_01 : 1; 505 uint8_t low_pass_on_6d : 1; 506 #endif /* DRV_BYTE_ORDER */ 507 } lsm6dsm_ctrl8_xl_t; 508 509 #define LSM6DSM_CTRL9_XL 0x18U 510 typedef struct 511 { 512 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 513 uint8_t not_used_01 : 2; 514 uint8_t soft_en : 1; 515 uint8_t not_used_02 : 1; 516 uint8_t den_xl_g : 1; 517 uint8_t den_z : 1; 518 uint8_t den_y : 1; 519 uint8_t den_x : 1; 520 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 521 uint8_t den_x : 1; 522 uint8_t den_y : 1; 523 uint8_t den_z : 1; 524 uint8_t den_xl_g : 1; 525 uint8_t not_used_02 : 1; 526 uint8_t soft_en : 1; 527 uint8_t not_used_01 : 2; 528 #endif /* DRV_BYTE_ORDER */ 529 } lsm6dsm_ctrl9_xl_t; 530 531 #define LSM6DSM_CTRL10_C 0x19U 532 typedef struct 533 { 534 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 535 uint8_t sign_motion_en : 1; 536 uint8_t pedo_rst_step : 1; 537 uint8_t func_en : 1; 538 uint8_t tilt_en : 1; 539 uint8_t pedo_en : 1; 540 uint8_t timer_en : 1; 541 uint8_t not_used_01 : 1; 542 uint8_t wrist_tilt_en : 1; 543 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 544 uint8_t wrist_tilt_en : 1; 545 uint8_t not_used_01 : 1; 546 uint8_t timer_en : 1; 547 uint8_t pedo_en : 1; 548 uint8_t tilt_en : 1; 549 uint8_t func_en : 1; 550 uint8_t pedo_rst_step : 1; 551 uint8_t sign_motion_en : 1; 552 #endif /* DRV_BYTE_ORDER */ 553 } lsm6dsm_ctrl10_c_t; 554 555 #define LSM6DSM_MASTER_CONFIG 0x1AU 556 typedef struct 557 { 558 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 559 uint8_t master_on : 1; 560 uint8_t iron_en : 1; 561 uint8_t pass_through_mode : 1; 562 uint8_t pull_up_en : 1; 563 uint8_t start_config : 1; 564 uint8_t not_used_01 : 1; 565 uint8_t data_valid_sel_fifo : 1; 566 uint8_t drdy_on_int1 : 1; 567 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 568 uint8_t drdy_on_int1 : 1; 569 uint8_t data_valid_sel_fifo : 1; 570 uint8_t not_used_01 : 1; 571 uint8_t start_config : 1; 572 uint8_t pull_up_en : 1; 573 uint8_t pass_through_mode : 1; 574 uint8_t iron_en : 1; 575 uint8_t master_on : 1; 576 #endif /* DRV_BYTE_ORDER */ 577 } lsm6dsm_master_config_t; 578 579 #define LSM6DSM_WAKE_UP_SRC 0x1BU 580 typedef struct 581 { 582 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 583 uint8_t z_wu : 1; 584 uint8_t y_wu : 1; 585 uint8_t x_wu : 1; 586 uint8_t wu_ia : 1; 587 uint8_t sleep_state_ia : 1; 588 uint8_t ff_ia : 1; 589 uint8_t not_used_01 : 2; 590 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 591 uint8_t not_used_01 : 2; 592 uint8_t ff_ia : 1; 593 uint8_t sleep_state_ia : 1; 594 uint8_t wu_ia : 1; 595 uint8_t x_wu : 1; 596 uint8_t y_wu : 1; 597 uint8_t z_wu : 1; 598 #endif /* DRV_BYTE_ORDER */ 599 } lsm6dsm_wake_up_src_t; 600 601 #define LSM6DSM_TAP_SRC 0x1CU 602 typedef struct 603 { 604 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 605 uint8_t z_tap : 1; 606 uint8_t y_tap : 1; 607 uint8_t x_tap : 1; 608 uint8_t tap_sign : 1; 609 uint8_t double_tap : 1; 610 uint8_t single_tap : 1; 611 uint8_t tap_ia : 1; 612 uint8_t not_used_01 : 1; 613 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 614 uint8_t not_used_01 : 1; 615 uint8_t tap_ia : 1; 616 uint8_t single_tap : 1; 617 uint8_t double_tap : 1; 618 uint8_t tap_sign : 1; 619 uint8_t x_tap : 1; 620 uint8_t y_tap : 1; 621 uint8_t z_tap : 1; 622 #endif /* DRV_BYTE_ORDER */ 623 } lsm6dsm_tap_src_t; 624 625 #define LSM6DSM_D6D_SRC 0x1DU 626 typedef struct 627 { 628 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 629 uint8_t xl : 1; 630 uint8_t xh : 1; 631 uint8_t yl : 1; 632 uint8_t yh : 1; 633 uint8_t zl : 1; 634 uint8_t zh : 1; 635 uint8_t d6d_ia : 1; 636 uint8_t den_drdy : 1; 637 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 638 uint8_t den_drdy : 1; 639 uint8_t d6d_ia : 1; 640 uint8_t zh : 1; 641 uint8_t zl : 1; 642 uint8_t yh : 1; 643 uint8_t yl : 1; 644 uint8_t xh : 1; 645 uint8_t xl : 1; 646 #endif /* DRV_BYTE_ORDER */ 647 } lsm6dsm_d6d_src_t; 648 649 #define LSM6DSM_STATUS_REG 0x1EU 650 typedef struct 651 { 652 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 653 uint8_t xlda : 1; 654 uint8_t gda : 1; 655 uint8_t tda : 1; 656 uint8_t not_used_01 : 5; 657 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 658 uint8_t not_used_01 : 5; 659 uint8_t tda : 1; 660 uint8_t gda : 1; 661 uint8_t xlda : 1; 662 #endif /* DRV_BYTE_ORDER */ 663 } lsm6dsm_status_reg_t; 664 665 #define LSM6DSM_STATUS_SPIAUX 0x1EU 666 typedef struct 667 { 668 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 669 uint8_t xlda : 1; 670 uint8_t gda : 1; 671 uint8_t gyro_settling : 1; 672 uint8_t not_used_01 : 5; 673 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 674 uint8_t not_used_01 : 5; 675 uint8_t gyro_settling : 1; 676 uint8_t gda : 1; 677 uint8_t xlda : 1; 678 #endif /* DRV_BYTE_ORDER */ 679 } lsm6dsm_status_spiaux_t; 680 681 #define LSM6DSM_OUT_TEMP_L 0x20U 682 #define LSM6DSM_OUT_TEMP_H 0x21U 683 #define LSM6DSM_OUTX_L_G 0x22U 684 #define LSM6DSM_OUTX_H_G 0x23U 685 #define LSM6DSM_OUTY_L_G 0x24U 686 #define LSM6DSM_OUTY_H_G 0x25U 687 #define LSM6DSM_OUTZ_L_G 0x26U 688 #define LSM6DSM_OUTZ_H_G 0x27U 689 #define LSM6DSM_OUTX_L_XL 0x28U 690 #define LSM6DSM_OUTX_H_XL 0x29U 691 #define LSM6DSM_OUTY_L_XL 0x2AU 692 #define LSM6DSM_OUTY_H_XL 0x2BU 693 #define LSM6DSM_OUTZ_L_XL 0x2CU 694 #define LSM6DSM_OUTZ_H_XL 0x2DU 695 #define LSM6DSM_SENSORHUB1_REG 0x2EU 696 typedef struct 697 { 698 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 699 uint8_t bit0 : 1; 700 uint8_t bit1 : 1; 701 uint8_t bit2 : 1; 702 uint8_t bit3 : 1; 703 uint8_t bit4 : 1; 704 uint8_t bit5 : 1; 705 uint8_t bit6 : 1; 706 uint8_t bit7 : 1; 707 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 708 uint8_t bit7 : 1; 709 uint8_t bit6 : 1; 710 uint8_t bit5 : 1; 711 uint8_t bit4 : 1; 712 uint8_t bit3 : 1; 713 uint8_t bit2 : 1; 714 uint8_t bit1 : 1; 715 uint8_t bit0 : 1; 716 #endif /* DRV_BYTE_ORDER */ 717 } lsm6dsm_sensorhub1_reg_t; 718 719 #define LSM6DSM_SENSORHUB2_REG 0x2FU 720 typedef struct 721 { 722 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 723 uint8_t bit0 : 1; 724 uint8_t bit1 : 1; 725 uint8_t bit2 : 1; 726 uint8_t bit3 : 1; 727 uint8_t bit4 : 1; 728 uint8_t bit5 : 1; 729 uint8_t bit6 : 1; 730 uint8_t bit7 : 1; 731 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 732 uint8_t bit7 : 1; 733 uint8_t bit6 : 1; 734 uint8_t bit5 : 1; 735 uint8_t bit4 : 1; 736 uint8_t bit3 : 1; 737 uint8_t bit2 : 1; 738 uint8_t bit1 : 1; 739 uint8_t bit0 : 1; 740 #endif /* DRV_BYTE_ORDER */ 741 } lsm6dsm_sensorhub2_reg_t; 742 743 #define LSM6DSM_SENSORHUB3_REG 0x30U 744 typedef struct 745 { 746 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 747 uint8_t bit0 : 1; 748 uint8_t bit1 : 1; 749 uint8_t bit2 : 1; 750 uint8_t bit3 : 1; 751 uint8_t bit4 : 1; 752 uint8_t bit5 : 1; 753 uint8_t bit6 : 1; 754 uint8_t bit7 : 1; 755 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 756 uint8_t bit7 : 1; 757 uint8_t bit6 : 1; 758 uint8_t bit5 : 1; 759 uint8_t bit4 : 1; 760 uint8_t bit3 : 1; 761 uint8_t bit2 : 1; 762 uint8_t bit1 : 1; 763 uint8_t bit0 : 1; 764 #endif /* DRV_BYTE_ORDER */ 765 } lsm6dsm_sensorhub3_reg_t; 766 767 #define LSM6DSM_SENSORHUB4_REG 0x31U 768 typedef struct 769 { 770 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 771 uint8_t bit0 : 1; 772 uint8_t bit1 : 1; 773 uint8_t bit2 : 1; 774 uint8_t bit3 : 1; 775 uint8_t bit4 : 1; 776 uint8_t bit5 : 1; 777 uint8_t bit6 : 1; 778 uint8_t bit7 : 1; 779 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 780 uint8_t bit7 : 1; 781 uint8_t bit6 : 1; 782 uint8_t bit5 : 1; 783 uint8_t bit4 : 1; 784 uint8_t bit3 : 1; 785 uint8_t bit2 : 1; 786 uint8_t bit1 : 1; 787 uint8_t bit0 : 1; 788 #endif /* DRV_BYTE_ORDER */ 789 } lsm6dsm_sensorhub4_reg_t; 790 791 #define LSM6DSM_SENSORHUB5_REG 0x32U 792 typedef struct 793 { 794 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 795 uint8_t bit0 : 1; 796 uint8_t bit1 : 1; 797 uint8_t bit2 : 1; 798 uint8_t bit3 : 1; 799 uint8_t bit4 : 1; 800 uint8_t bit5 : 1; 801 uint8_t bit6 : 1; 802 uint8_t bit7 : 1; 803 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 804 uint8_t bit7 : 1; 805 uint8_t bit6 : 1; 806 uint8_t bit5 : 1; 807 uint8_t bit4 : 1; 808 uint8_t bit3 : 1; 809 uint8_t bit2 : 1; 810 uint8_t bit1 : 1; 811 uint8_t bit0 : 1; 812 #endif /* DRV_BYTE_ORDER */ 813 } lsm6dsm_sensorhub5_reg_t; 814 815 #define LSM6DSM_SENSORHUB6_REG 0x33U 816 typedef struct 817 { 818 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 819 uint8_t bit0 : 1; 820 uint8_t bit1 : 1; 821 uint8_t bit2 : 1; 822 uint8_t bit3 : 1; 823 uint8_t bit4 : 1; 824 uint8_t bit5 : 1; 825 uint8_t bit6 : 1; 826 uint8_t bit7 : 1; 827 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 828 uint8_t bit7 : 1; 829 uint8_t bit6 : 1; 830 uint8_t bit5 : 1; 831 uint8_t bit4 : 1; 832 uint8_t bit3 : 1; 833 uint8_t bit2 : 1; 834 uint8_t bit1 : 1; 835 uint8_t bit0 : 1; 836 #endif /* DRV_BYTE_ORDER */ 837 } lsm6dsm_sensorhub6_reg_t; 838 839 #define LSM6DSM_SENSORHUB7_REG 0x34U 840 typedef struct 841 { 842 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 843 uint8_t bit0 : 1; 844 uint8_t bit1 : 1; 845 uint8_t bit2 : 1; 846 uint8_t bit3 : 1; 847 uint8_t bit4 : 1; 848 uint8_t bit5 : 1; 849 uint8_t bit6 : 1; 850 uint8_t bit7 : 1; 851 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 852 uint8_t bit7 : 1; 853 uint8_t bit6 : 1; 854 uint8_t bit5 : 1; 855 uint8_t bit4 : 1; 856 uint8_t bit3 : 1; 857 uint8_t bit2 : 1; 858 uint8_t bit1 : 1; 859 uint8_t bit0 : 1; 860 #endif /* DRV_BYTE_ORDER */ 861 } lsm6dsm_sensorhub7_reg_t; 862 863 #define LSM6DSM_SENSORHUB8_REG 0x35U 864 typedef struct 865 { 866 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 867 uint8_t bit0 : 1; 868 uint8_t bit1 : 1; 869 uint8_t bit2 : 1; 870 uint8_t bit3 : 1; 871 uint8_t bit4 : 1; 872 uint8_t bit5 : 1; 873 uint8_t bit6 : 1; 874 uint8_t bit7 : 1; 875 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 876 uint8_t bit7 : 1; 877 uint8_t bit6 : 1; 878 uint8_t bit5 : 1; 879 uint8_t bit4 : 1; 880 uint8_t bit3 : 1; 881 uint8_t bit2 : 1; 882 uint8_t bit1 : 1; 883 uint8_t bit0 : 1; 884 #endif /* DRV_BYTE_ORDER */ 885 } lsm6dsm_sensorhub8_reg_t; 886 887 #define LSM6DSM_SENSORHUB9_REG 0x36U 888 typedef struct 889 { 890 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 891 uint8_t bit0 : 1; 892 uint8_t bit1 : 1; 893 uint8_t bit2 : 1; 894 uint8_t bit3 : 1; 895 uint8_t bit4 : 1; 896 uint8_t bit5 : 1; 897 uint8_t bit6 : 1; 898 uint8_t bit7 : 1; 899 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 900 uint8_t bit7 : 1; 901 uint8_t bit6 : 1; 902 uint8_t bit5 : 1; 903 uint8_t bit4 : 1; 904 uint8_t bit3 : 1; 905 uint8_t bit2 : 1; 906 uint8_t bit1 : 1; 907 uint8_t bit0 : 1; 908 #endif /* DRV_BYTE_ORDER */ 909 } lsm6dsm_sensorhub9_reg_t; 910 911 #define LSM6DSM_SENSORHUB10_REG 0x37U 912 typedef struct 913 { 914 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 915 uint8_t bit0 : 1; 916 uint8_t bit1 : 1; 917 uint8_t bit2 : 1; 918 uint8_t bit3 : 1; 919 uint8_t bit4 : 1; 920 uint8_t bit5 : 1; 921 uint8_t bit6 : 1; 922 uint8_t bit7 : 1; 923 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 924 uint8_t bit7 : 1; 925 uint8_t bit6 : 1; 926 uint8_t bit5 : 1; 927 uint8_t bit4 : 1; 928 uint8_t bit3 : 1; 929 uint8_t bit2 : 1; 930 uint8_t bit1 : 1; 931 uint8_t bit0 : 1; 932 #endif /* DRV_BYTE_ORDER */ 933 } lsm6dsm_sensorhub10_reg_t; 934 935 #define LSM6DSM_SENSORHUB11_REG 0x38U 936 typedef struct 937 { 938 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 939 uint8_t bit0 : 1; 940 uint8_t bit1 : 1; 941 uint8_t bit2 : 1; 942 uint8_t bit3 : 1; 943 uint8_t bit4 : 1; 944 uint8_t bit5 : 1; 945 uint8_t bit6 : 1; 946 uint8_t bit7 : 1; 947 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 948 uint8_t bit7 : 1; 949 uint8_t bit6 : 1; 950 uint8_t bit5 : 1; 951 uint8_t bit4 : 1; 952 uint8_t bit3 : 1; 953 uint8_t bit2 : 1; 954 uint8_t bit1 : 1; 955 uint8_t bit0 : 1; 956 #endif /* DRV_BYTE_ORDER */ 957 } lsm6dsm_sensorhub11_reg_t; 958 959 #define LSM6DSM_SENSORHUB12_REG 0x39U 960 typedef struct 961 { 962 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 963 uint8_t bit0 : 1; 964 uint8_t bit1 : 1; 965 uint8_t bit2 : 1; 966 uint8_t bit3 : 1; 967 uint8_t bit4 : 1; 968 uint8_t bit5 : 1; 969 uint8_t bit6 : 1; 970 uint8_t bit7 : 1; 971 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 972 uint8_t bit7 : 1; 973 uint8_t bit6 : 1; 974 uint8_t bit5 : 1; 975 uint8_t bit4 : 1; 976 uint8_t bit3 : 1; 977 uint8_t bit2 : 1; 978 uint8_t bit1 : 1; 979 uint8_t bit0 : 1; 980 #endif /* DRV_BYTE_ORDER */ 981 } lsm6dsm_sensorhub12_reg_t; 982 983 #define LSM6DSM_FIFO_STATUS1 0x3AU 984 typedef struct 985 { 986 uint8_t diff_fifo : 8; /* + FIFO_STATUS2(diff_fifo) */ 987 } lsm6dsm_fifo_status1_t; 988 989 #define LSM6DSM_FIFO_STATUS2 0x3BU 990 typedef struct 991 { 992 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 993 uint8_t diff_fifo : 3; /* + FIFO_STATUS1(diff_fifo) */ 994 uint8_t not_used_01 : 1; 995 uint8_t fifo_empty : 1; 996 uint8_t fifo_full_smart : 1; 997 uint8_t over_run : 1; 998 uint8_t waterm : 1; 999 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1000 uint8_t waterm : 1; 1001 uint8_t over_run : 1; 1002 uint8_t fifo_full_smart : 1; 1003 uint8_t fifo_empty : 1; 1004 uint8_t not_used_01 : 1; 1005 uint8_t diff_fifo : 3; /* + FIFO_STATUS1(diff_fifo) */ 1006 #endif /* DRV_BYTE_ORDER */ 1007 } lsm6dsm_fifo_status2_t; 1008 1009 #define LSM6DSM_FIFO_STATUS3 0x3CU 1010 typedef struct 1011 { 1012 uint8_t fifo_pattern : 1013 8; /* + FIFO_STATUS4(fifo_pattern) */ 1014 } lsm6dsm_fifo_status3_t; 1015 1016 #define LSM6DSM_FIFO_STATUS4 0x3DU 1017 typedef struct 1018 { 1019 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1020 uint8_t fifo_pattern : 1021 2; /* + FIFO_STATUS3(fifo_pattern) */ 1022 uint8_t not_used_01 : 6; 1023 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1024 uint8_t not_used_01 : 6; 1025 uint8_t fifo_pattern : 1026 2; /* + FIFO_STATUS3(fifo_pattern) */ 1027 #endif /* DRV_BYTE_ORDER */ 1028 } lsm6dsm_fifo_status4_t; 1029 1030 #define LSM6DSM_FIFO_DATA_OUT_L 0x3EU 1031 #define LSM6DSM_FIFO_DATA_OUT_H 0x3FU 1032 #define LSM6DSM_TIMESTAMP0_REG 0x40U 1033 #define LSM6DSM_TIMESTAMP1_REG 0x41U 1034 #define LSM6DSM_TIMESTAMP2_REG 0x42U 1035 #define LSM6DSM_STEP_TIMESTAMP_L 0x49U 1036 #define LSM6DSM_STEP_TIMESTAMP_H 0x4AU 1037 #define LSM6DSM_STEP_COUNTER_L 0x4BU 1038 #define LSM6DSM_STEP_COUNTER_H 0x4CU 1039 1040 #define LSM6DSM_SENSORHUB13_REG 0x4DU 1041 typedef struct 1042 { 1043 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1044 uint8_t bit0 : 1; 1045 uint8_t bit1 : 1; 1046 uint8_t bit2 : 1; 1047 uint8_t bit3 : 1; 1048 uint8_t bit4 : 1; 1049 uint8_t bit5 : 1; 1050 uint8_t bit6 : 1; 1051 uint8_t bit7 : 1; 1052 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1053 uint8_t bit7 : 1; 1054 uint8_t bit6 : 1; 1055 uint8_t bit5 : 1; 1056 uint8_t bit4 : 1; 1057 uint8_t bit3 : 1; 1058 uint8_t bit2 : 1; 1059 uint8_t bit1 : 1; 1060 uint8_t bit0 : 1; 1061 #endif /* DRV_BYTE_ORDER */ 1062 } lsm6dsm_sensorhub13_reg_t; 1063 1064 #define LSM6DSM_SENSORHUB14_REG 0x4EU 1065 typedef struct 1066 { 1067 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1068 uint8_t bit0 : 1; 1069 uint8_t bit1 : 1; 1070 uint8_t bit2 : 1; 1071 uint8_t bit3 : 1; 1072 uint8_t bit4 : 1; 1073 uint8_t bit5 : 1; 1074 uint8_t bit6 : 1; 1075 uint8_t bit7 : 1; 1076 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1077 uint8_t bit7 : 1; 1078 uint8_t bit6 : 1; 1079 uint8_t bit5 : 1; 1080 uint8_t bit4 : 1; 1081 uint8_t bit3 : 1; 1082 uint8_t bit2 : 1; 1083 uint8_t bit1 : 1; 1084 uint8_t bit0 : 1; 1085 #endif /* DRV_BYTE_ORDER */ 1086 } lsm6dsm_sensorhub14_reg_t; 1087 1088 #define LSM6DSM_SENSORHUB15_REG 0x4FU 1089 typedef struct 1090 { 1091 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1092 uint8_t bit0 : 1; 1093 uint8_t bit1 : 1; 1094 uint8_t bit2 : 1; 1095 uint8_t bit3 : 1; 1096 uint8_t bit4 : 1; 1097 uint8_t bit5 : 1; 1098 uint8_t bit6 : 1; 1099 uint8_t bit7 : 1; 1100 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1101 uint8_t bit7 : 1; 1102 uint8_t bit6 : 1; 1103 uint8_t bit5 : 1; 1104 uint8_t bit4 : 1; 1105 uint8_t bit3 : 1; 1106 uint8_t bit2 : 1; 1107 uint8_t bit1 : 1; 1108 uint8_t bit0 : 1; 1109 #endif /* DRV_BYTE_ORDER */ 1110 } lsm6dsm_sensorhub15_reg_t; 1111 1112 #define LSM6DSM_SENSORHUB16_REG 0x50U 1113 typedef struct 1114 { 1115 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1116 uint8_t bit0 : 1; 1117 uint8_t bit1 : 1; 1118 uint8_t bit2 : 1; 1119 uint8_t bit3 : 1; 1120 uint8_t bit4 : 1; 1121 uint8_t bit5 : 1; 1122 uint8_t bit6 : 1; 1123 uint8_t bit7 : 1; 1124 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1125 uint8_t bit7 : 1; 1126 uint8_t bit6 : 1; 1127 uint8_t bit5 : 1; 1128 uint8_t bit4 : 1; 1129 uint8_t bit3 : 1; 1130 uint8_t bit2 : 1; 1131 uint8_t bit1 : 1; 1132 uint8_t bit0 : 1; 1133 #endif /* DRV_BYTE_ORDER */ 1134 } lsm6dsm_sensorhub16_reg_t; 1135 1136 #define LSM6DSM_SENSORHUB17_REG 0x51U 1137 typedef struct 1138 { 1139 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1140 uint8_t bit0 : 1; 1141 uint8_t bit1 : 1; 1142 uint8_t bit2 : 1; 1143 uint8_t bit3 : 1; 1144 uint8_t bit4 : 1; 1145 uint8_t bit5 : 1; 1146 uint8_t bit6 : 1; 1147 uint8_t bit7 : 1; 1148 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1149 uint8_t bit7 : 1; 1150 uint8_t bit6 : 1; 1151 uint8_t bit5 : 1; 1152 uint8_t bit4 : 1; 1153 uint8_t bit3 : 1; 1154 uint8_t bit2 : 1; 1155 uint8_t bit1 : 1; 1156 uint8_t bit0 : 1; 1157 #endif /* DRV_BYTE_ORDER */ 1158 } lsm6dsm_sensorhub17_reg_t; 1159 1160 #define LSM6DSM_SENSORHUB18_REG 0x52U 1161 typedef struct 1162 { 1163 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1164 uint8_t bit0 : 1; 1165 uint8_t bit1 : 1; 1166 uint8_t bit2 : 1; 1167 uint8_t bit3 : 1; 1168 uint8_t bit4 : 1; 1169 uint8_t bit5 : 1; 1170 uint8_t bit6 : 1; 1171 uint8_t bit7 : 1; 1172 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1173 uint8_t bit7 : 1; 1174 uint8_t bit6 : 1; 1175 uint8_t bit5 : 1; 1176 uint8_t bit4 : 1; 1177 uint8_t bit3 : 1; 1178 uint8_t bit2 : 1; 1179 uint8_t bit1 : 1; 1180 uint8_t bit0 : 1; 1181 #endif /* DRV_BYTE_ORDER */ 1182 } lsm6dsm_sensorhub18_reg_t; 1183 1184 #define LSM6DSM_FUNC_SRC1 0x53U 1185 typedef struct 1186 { 1187 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1188 uint8_t sensorhub_end_op : 1; 1189 uint8_t si_end_op : 1; 1190 uint8_t hi_fail : 1; 1191 uint8_t step_overflow : 1; 1192 uint8_t step_detected : 1; 1193 uint8_t tilt_ia : 1; 1194 uint8_t sign_motion_ia : 1; 1195 uint8_t step_count_delta_ia : 1; 1196 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1197 uint8_t step_count_delta_ia : 1; 1198 uint8_t sign_motion_ia : 1; 1199 uint8_t tilt_ia : 1; 1200 uint8_t step_detected : 1; 1201 uint8_t step_overflow : 1; 1202 uint8_t hi_fail : 1; 1203 uint8_t si_end_op : 1; 1204 uint8_t sensorhub_end_op : 1; 1205 #endif /* DRV_BYTE_ORDER */ 1206 } lsm6dsm_func_src1_t; 1207 1208 #define LSM6DSM_FUNC_SRC2 0x54U 1209 typedef struct 1210 { 1211 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1212 uint8_t wrist_tilt_ia : 1; 1213 uint8_t not_used_01 : 2; 1214 uint8_t slave0_nack : 1; 1215 uint8_t slave1_nack : 1; 1216 uint8_t slave2_nack : 1; 1217 uint8_t slave3_nack : 1; 1218 uint8_t not_used_02 : 1; 1219 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1220 uint8_t not_used_02 : 1; 1221 uint8_t slave3_nack : 1; 1222 uint8_t slave2_nack : 1; 1223 uint8_t slave1_nack : 1; 1224 uint8_t slave0_nack : 1; 1225 uint8_t not_used_01 : 2; 1226 uint8_t wrist_tilt_ia : 1; 1227 #endif /* DRV_BYTE_ORDER */ 1228 } lsm6dsm_func_src2_t; 1229 1230 #define LSM6DSM_WRIST_TILT_IA 0x55U 1231 typedef struct 1232 { 1233 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1234 uint8_t not_used_01 : 2; 1235 uint8_t wrist_tilt_ia_zneg : 1; 1236 uint8_t wrist_tilt_ia_zpos : 1; 1237 uint8_t wrist_tilt_ia_yneg : 1; 1238 uint8_t wrist_tilt_ia_ypos : 1; 1239 uint8_t wrist_tilt_ia_xneg : 1; 1240 uint8_t wrist_tilt_ia_xpos : 1; 1241 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1242 uint8_t wrist_tilt_ia_xpos : 1; 1243 uint8_t wrist_tilt_ia_xneg : 1; 1244 uint8_t wrist_tilt_ia_ypos : 1; 1245 uint8_t wrist_tilt_ia_yneg : 1; 1246 uint8_t wrist_tilt_ia_zpos : 1; 1247 uint8_t wrist_tilt_ia_zneg : 1; 1248 uint8_t not_used_01 : 2; 1249 #endif /* DRV_BYTE_ORDER */ 1250 } lsm6dsm_wrist_tilt_ia_t; 1251 1252 #define LSM6DSM_TAP_CFG 0x58U 1253 typedef struct 1254 { 1255 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1256 uint8_t lir : 1; 1257 uint8_t tap_z_en : 1; 1258 uint8_t tap_y_en : 1; 1259 uint8_t tap_x_en : 1; 1260 uint8_t slope_fds : 1; 1261 uint8_t inact_en : 2; 1262 uint8_t interrupts_enable : 1; 1263 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1264 uint8_t interrupts_enable : 1; 1265 uint8_t inact_en : 2; 1266 uint8_t slope_fds : 1; 1267 uint8_t tap_x_en : 1; 1268 uint8_t tap_y_en : 1; 1269 uint8_t tap_z_en : 1; 1270 uint8_t lir : 1; 1271 #endif /* DRV_BYTE_ORDER */ 1272 } lsm6dsm_tap_cfg_t; 1273 1274 #define LSM6DSM_TAP_THS_6D 0x59U 1275 typedef struct 1276 { 1277 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1278 uint8_t tap_ths : 5; 1279 uint8_t sixd_ths : 2; 1280 uint8_t d4d_en : 1; 1281 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1282 uint8_t d4d_en : 1; 1283 uint8_t sixd_ths : 2; 1284 uint8_t tap_ths : 5; 1285 #endif /* DRV_BYTE_ORDER */ 1286 } lsm6dsm_tap_ths_6d_t; 1287 1288 #define LSM6DSM_INT_DUR2 0x5AU 1289 typedef struct 1290 { 1291 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1292 uint8_t shock : 2; 1293 uint8_t quiet : 2; 1294 uint8_t dur : 4; 1295 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1296 uint8_t dur : 4; 1297 uint8_t quiet : 2; 1298 uint8_t shock : 2; 1299 #endif /* DRV_BYTE_ORDER */ 1300 } lsm6dsm_int_dur2_t; 1301 1302 #define LSM6DSM_WAKE_UP_THS 0x5BU 1303 typedef struct 1304 { 1305 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1306 uint8_t wk_ths : 6; 1307 uint8_t not_used_01 : 1; 1308 uint8_t single_double_tap : 1; 1309 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1310 uint8_t single_double_tap : 1; 1311 uint8_t not_used_01 : 1; 1312 uint8_t wk_ths : 6; 1313 #endif /* DRV_BYTE_ORDER */ 1314 } lsm6dsm_wake_up_ths_t; 1315 1316 #define LSM6DSM_WAKE_UP_DUR 0x5CU 1317 typedef struct 1318 { 1319 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1320 uint8_t sleep_dur : 4; 1321 uint8_t timer_hr : 1; 1322 uint8_t wake_dur : 2; 1323 uint8_t ff_dur : 1; 1324 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1325 uint8_t ff_dur : 1; 1326 uint8_t wake_dur : 2; 1327 uint8_t timer_hr : 1; 1328 uint8_t sleep_dur : 4; 1329 #endif /* DRV_BYTE_ORDER */ 1330 } lsm6dsm_wake_up_dur_t; 1331 1332 #define LSM6DSM_FREE_FALL 0x5DU 1333 typedef struct 1334 { 1335 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1336 uint8_t ff_ths : 3; 1337 uint8_t ff_dur : 5; 1338 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1339 uint8_t ff_dur : 5; 1340 uint8_t ff_ths : 3; 1341 #endif /* DRV_BYTE_ORDER */ 1342 } lsm6dsm_free_fall_t; 1343 1344 #define LSM6DSM_MD1_CFG 0x5EU 1345 typedef struct 1346 { 1347 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1348 uint8_t int1_timer : 1; 1349 uint8_t int1_tilt : 1; 1350 uint8_t int1_6d : 1; 1351 uint8_t int1_double_tap : 1; 1352 uint8_t int1_ff : 1; 1353 uint8_t int1_wu : 1; 1354 uint8_t int1_single_tap : 1; 1355 uint8_t int1_inact_state : 1; 1356 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1357 uint8_t int1_inact_state : 1; 1358 uint8_t int1_single_tap : 1; 1359 uint8_t int1_wu : 1; 1360 uint8_t int1_ff : 1; 1361 uint8_t int1_double_tap : 1; 1362 uint8_t int1_6d : 1; 1363 uint8_t int1_tilt : 1; 1364 uint8_t int1_timer : 1; 1365 #endif /* DRV_BYTE_ORDER */ 1366 } lsm6dsm_md1_cfg_t; 1367 1368 #define LSM6DSM_MD2_CFG 0x5FU 1369 typedef struct 1370 { 1371 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1372 uint8_t int2_iron : 1; 1373 uint8_t int2_tilt : 1; 1374 uint8_t int2_6d : 1; 1375 uint8_t int2_double_tap : 1; 1376 uint8_t int2_ff : 1; 1377 uint8_t int2_wu : 1; 1378 uint8_t int2_single_tap : 1; 1379 uint8_t int2_inact_state : 1; 1380 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1381 uint8_t int2_inact_state : 1; 1382 uint8_t int2_single_tap : 1; 1383 uint8_t int2_wu : 1; 1384 uint8_t int2_ff : 1; 1385 uint8_t int2_double_tap : 1; 1386 uint8_t int2_6d : 1; 1387 uint8_t int2_tilt : 1; 1388 uint8_t int2_iron : 1; 1389 #endif /* DRV_BYTE_ORDER */ 1390 } lsm6dsm_md2_cfg_t; 1391 1392 #define LSM6DSM_MASTER_CMD_CODE 0x60U 1393 typedef struct 1394 { 1395 uint8_t master_cmd_code : 8; 1396 } lsm6dsm_master_cmd_code_t; 1397 1398 #define LSM6DSM_SENS_SYNC_SPI_ERROR_CODE 0x61U 1399 typedef struct 1400 { 1401 uint8_t error_code : 8; 1402 } lsm6dsm_sens_sync_spi_error_code_t; 1403 1404 #define LSM6DSM_OUT_MAG_RAW_X_L 0x66U 1405 #define LSM6DSM_OUT_MAG_RAW_X_H 0x67U 1406 #define LSM6DSM_OUT_MAG_RAW_Y_L 0x68U 1407 #define LSM6DSM_OUT_MAG_RAW_Y_H 0x69U 1408 #define LSM6DSM_OUT_MAG_RAW_Z_L 0x6AU 1409 #define LSM6DSM_OUT_MAG_RAW_Z_H 0x6BU 1410 #define LSM6DSM_INT_OIS 0x6FU 1411 typedef struct 1412 { 1413 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1414 uint8_t not_used_01 : 6; 1415 uint8_t lvl2_ois : 1; 1416 uint8_t int2_drdy_ois : 1; 1417 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1418 uint8_t int2_drdy_ois : 1; 1419 uint8_t lvl2_ois : 1; 1420 uint8_t not_used_01 : 6; 1421 #endif /* DRV_BYTE_ORDER */ 1422 } lsm6dsm_int_ois_t; 1423 1424 #define LSM6DSM_CTRL1_OIS 0x70U 1425 typedef struct 1426 { 1427 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1428 uint8_t ois_en_spi2 : 1; 1429 uint8_t fs_g_ois : 3; /* fs_g_ois + fs_125_ois */ 1430 uint8_t mode4_en : 1; 1431 uint8_t sim_ois : 1; 1432 uint8_t lvl1_ois : 1; 1433 uint8_t ble_ois : 1; 1434 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1435 uint8_t ble_ois : 1; 1436 uint8_t lvl1_ois : 1; 1437 uint8_t sim_ois : 1; 1438 uint8_t mode4_en : 1; 1439 uint8_t fs_g_ois : 3; /* fs_g_ois + fs_125_ois */ 1440 uint8_t ois_en_spi2 : 1; 1441 #endif /* DRV_BYTE_ORDER */ 1442 } lsm6dsm_ctrl1_ois_t; 1443 1444 #define LSM6DSM_CTRL2_OIS 0x71U 1445 typedef struct 1446 { 1447 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1448 uint8_t hp_en_ois : 1; 1449 uint8_t ftype_ois : 2; 1450 uint8_t not_used_01 : 1; 1451 uint8_t hpm_ois : 2; 1452 uint8_t not_used_02 : 2; 1453 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1454 uint8_t not_used_02 : 2; 1455 uint8_t hpm_ois : 2; 1456 uint8_t not_used_01 : 1; 1457 uint8_t ftype_ois : 2; 1458 uint8_t hp_en_ois : 1; 1459 #endif /* DRV_BYTE_ORDER */ 1460 } lsm6dsm_ctrl2_ois_t; 1461 1462 #define LSM6DSM_CTRL3_OIS 0x72U 1463 typedef struct 1464 { 1465 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1466 uint8_t st_ois_clampdis : 1; 1467 uint8_t st_ois : 2; 1468 uint8_t filter_xl_conf_ois : 2; 1469 uint8_t fs_xl_ois : 2; 1470 uint8_t den_lh_ois : 1; 1471 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1472 uint8_t den_lh_ois : 1; 1473 uint8_t fs_xl_ois : 2; 1474 uint8_t filter_xl_conf_ois : 2; 1475 uint8_t st_ois : 2; 1476 uint8_t st_ois_clampdis : 1; 1477 #endif /* DRV_BYTE_ORDER */ 1478 } lsm6dsm_ctrl3_ois_t; 1479 1480 #define LSM6DSM_X_OFS_USR 0x73U 1481 #define LSM6DSM_Y_OFS_USR 0x74U 1482 #define LSM6DSM_Z_OFS_USR 0x75U 1483 #define LSM6DSM_SLV0_ADD 0x02U 1484 typedef struct 1485 { 1486 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1487 uint8_t rw_0 : 1; 1488 uint8_t slave0_add : 7; 1489 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1490 uint8_t slave0_add : 7; 1491 uint8_t rw_0 : 1; 1492 #endif /* DRV_BYTE_ORDER */ 1493 } lsm6dsm_slv0_add_t; 1494 1495 #define LSM6DSM_SLV0_SUBADD 0x03U 1496 typedef struct 1497 { 1498 uint8_t slave0_reg : 8; 1499 } lsm6dsm_slv0_subadd_t; 1500 1501 #define LSM6DSM_SLAVE0_CONFIG 0x04U 1502 typedef struct 1503 { 1504 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1505 uint8_t slave0_numop : 3; 1506 uint8_t src_mode : 1; 1507 uint8_t aux_sens_on : 2; 1508 uint8_t slave0_rate : 2; 1509 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1510 uint8_t slave0_rate : 2; 1511 uint8_t aux_sens_on : 2; 1512 uint8_t src_mode : 1; 1513 uint8_t slave0_numop : 3; 1514 #endif /* DRV_BYTE_ORDER */ 1515 } lsm6dsm_slave0_config_t; 1516 1517 #define LSM6DSM_SLV1_ADD 0x05U 1518 typedef struct 1519 { 1520 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1521 uint8_t r_1 : 1; 1522 uint8_t slave1_add : 7; 1523 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1524 uint8_t slave1_add : 7; 1525 uint8_t r_1 : 1; 1526 #endif /* DRV_BYTE_ORDER */ 1527 } lsm6dsm_slv1_add_t; 1528 1529 #define LSM6DSM_SLV1_SUBADD 0x06U 1530 typedef struct 1531 { 1532 uint8_t slave1_reg : 8; 1533 } lsm6dsm_slv1_subadd_t; 1534 1535 #define LSM6DSM_SLAVE1_CONFIG 0x07U 1536 typedef struct 1537 { 1538 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1539 uint8_t slave1_numop : 3; 1540 uint8_t not_used_01 : 2; 1541 uint8_t write_once : 1; 1542 uint8_t slave1_rate : 2; 1543 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1544 uint8_t slave1_rate : 2; 1545 uint8_t write_once : 1; 1546 uint8_t not_used_01 : 2; 1547 uint8_t slave1_numop : 3; 1548 #endif /* DRV_BYTE_ORDER */ 1549 } lsm6dsm_slave1_config_t; 1550 1551 #define LSM6DSM_SLV2_ADD 0x08U 1552 typedef struct 1553 { 1554 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1555 uint8_t r_2 : 1; 1556 uint8_t slave2_add : 7; 1557 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1558 uint8_t slave2_add : 7; 1559 uint8_t r_2 : 1; 1560 #endif /* DRV_BYTE_ORDER */ 1561 } lsm6dsm_slv2_add_t; 1562 1563 #define LSM6DSM_SLV2_SUBADD 0x09U 1564 typedef struct 1565 { 1566 uint8_t slave2_reg : 8; 1567 } lsm6dsm_slv2_subadd_t; 1568 1569 #define LSM6DSM_SLAVE2_CONFIG 0x0AU 1570 typedef struct 1571 { 1572 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1573 uint8_t slave2_numop : 3; 1574 uint8_t not_used_01 : 3; 1575 uint8_t slave2_rate : 2; 1576 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1577 uint8_t slave2_rate : 2; 1578 uint8_t not_used_01 : 3; 1579 uint8_t slave2_numop : 3; 1580 #endif /* DRV_BYTE_ORDER */ 1581 } lsm6dsm_slave2_config_t; 1582 1583 #define LSM6DSM_SLV3_ADD 0x0BU 1584 typedef struct 1585 { 1586 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1587 uint8_t r_3 : 1; 1588 uint8_t slave3_add : 7; 1589 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1590 uint8_t slave3_add : 7; 1591 uint8_t r_3 : 1; 1592 #endif /* DRV_BYTE_ORDER */ 1593 } lsm6dsm_slv3_add_t; 1594 1595 #define LSM6DSM_SLV3_SUBADD 0x0CU 1596 typedef struct 1597 { 1598 uint8_t slave3_reg : 8; 1599 } lsm6dsm_slv3_subadd_t; 1600 1601 #define LSM6DSM_SLAVE3_CONFIG 0x0DU 1602 typedef struct 1603 { 1604 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1605 uint8_t slave3_numop : 3; 1606 uint8_t not_used_01 : 3; 1607 uint8_t slave3_rate : 2; 1608 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1609 uint8_t slave3_rate : 2; 1610 uint8_t not_used_01 : 3; 1611 uint8_t slave3_numop : 3; 1612 #endif /* DRV_BYTE_ORDER */ 1613 } lsm6dsm_slave3_config_t; 1614 1615 #define LSM6DSM_DATAWRITE_SRC_MODE_SUB_SLV0 0x0EU 1616 typedef struct 1617 { 1618 uint8_t slave_dataw : 8; 1619 } lsm6dsm_datawrite_src_mode_sub_slv0_t; 1620 1621 #define LSM6DSM_CONFIG_PEDO_THS_MIN 0x0FU 1622 typedef struct 1623 { 1624 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1625 uint8_t ths_min : 5; 1626 uint8_t not_used_01 : 2; 1627 uint8_t pedo_fs : 1; 1628 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1629 uint8_t pedo_fs : 1; 1630 uint8_t not_used_01 : 2; 1631 uint8_t ths_min : 5; 1632 #endif /* DRV_BYTE_ORDER */ 1633 } lsm6dsm_config_pedo_ths_min_t; 1634 1635 #define LSM6DSM_SM_THS 0x13U 1636 #define LSM6DSM_PEDO_DEB_REG 0x14U 1637 typedef struct 1638 { 1639 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1640 uint8_t deb_step : 3; 1641 uint8_t deb_time : 5; 1642 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1643 uint8_t deb_time : 5; 1644 uint8_t deb_step : 3; 1645 #endif /* DRV_BYTE_ORDER */ 1646 } lsm6dsm_pedo_deb_reg_t; 1647 1648 #define LSM6DSM_STEP_COUNT_DELTA 0x15U 1649 #define LSM6DSM_MAG_SI_XX 0x24U 1650 #define LSM6DSM_MAG_SI_XY 0x25U 1651 #define LSM6DSM_MAG_SI_XZ 0x26U 1652 #define LSM6DSM_MAG_SI_YX 0x27U 1653 #define LSM6DSM_MAG_SI_YY 0x28U 1654 #define LSM6DSM_MAG_SI_YZ 0x29U 1655 #define LSM6DSM_MAG_SI_ZX 0x2AU 1656 #define LSM6DSM_MAG_SI_ZY 0x2BU 1657 #define LSM6DSM_MAG_SI_ZZ 0x2CU 1658 #define LSM6DSM_MAG_OFFX_L 0x2DU 1659 #define LSM6DSM_MAG_OFFX_H 0x2EU 1660 #define LSM6DSM_MAG_OFFY_L 0x2FU 1661 #define LSM6DSM_MAG_OFFY_H 0x30U 1662 #define LSM6DSM_MAG_OFFZ_L 0x31U 1663 #define LSM6DSM_MAG_OFFZ_H 0x32U 1664 #define LSM6DSM_A_WRIST_TILT_LAT 0x50U 1665 #define LSM6DSM_A_WRIST_TILT_THS 0x54U 1666 #define LSM6DSM_A_WRIST_TILT_MASK 0x59U 1667 typedef struct 1668 { 1669 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1670 uint8_t not_used_01 : 2; 1671 uint8_t wrist_tilt_mask_zneg : 1; 1672 uint8_t wrist_tilt_mask_zpos : 1; 1673 uint8_t wrist_tilt_mask_yneg : 1; 1674 uint8_t wrist_tilt_mask_ypos : 1; 1675 uint8_t wrist_tilt_mask_xneg : 1; 1676 uint8_t wrist_tilt_mask_xpos : 1; 1677 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1678 uint8_t wrist_tilt_mask_xpos : 1; 1679 uint8_t wrist_tilt_mask_xneg : 1; 1680 uint8_t wrist_tilt_mask_ypos : 1; 1681 uint8_t wrist_tilt_mask_yneg : 1; 1682 uint8_t wrist_tilt_mask_zpos : 1; 1683 uint8_t wrist_tilt_mask_zneg : 1; 1684 uint8_t not_used_01 : 2; 1685 #endif /* DRV_BYTE_ORDER */ 1686 } lsm6dsm_a_wrist_tilt_mask_t; 1687 1688 /** 1689 * @defgroup LSM6DSM_Register_Union 1690 * @brief This union group all the registers having a bit-field 1691 * description. 1692 * This union is useful but it's not needed by the driver. 1693 * 1694 * REMOVING this union you are compliant with: 1695 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 1696 * 1697 * @{ 1698 * 1699 */ 1700 typedef union 1701 { 1702 lsm6dsm_func_cfg_access_t func_cfg_access; 1703 lsm6dsm_sensor_sync_time_frame_t sensor_sync_time_frame; 1704 lsm6dsm_sensor_sync_res_ratio_t sensor_sync_res_ratio; 1705 lsm6dsm_fifo_ctrl1_t fifo_ctrl1; 1706 lsm6dsm_fifo_ctrl2_t fifo_ctrl2; 1707 lsm6dsm_fifo_ctrl3_t fifo_ctrl3; 1708 lsm6dsm_fifo_ctrl4_t fifo_ctrl4; 1709 lsm6dsm_fifo_ctrl5_t fifo_ctrl5; 1710 lsm6dsm_drdy_pulse_cfg_t drdy_pulse_cfg; 1711 lsm6dsm_int1_ctrl_t int1_ctrl; 1712 lsm6dsm_int2_ctrl_t int2_ctrl; 1713 lsm6dsm_ctrl1_xl_t ctrl1_xl; 1714 lsm6dsm_ctrl2_g_t ctrl2_g; 1715 lsm6dsm_ctrl3_c_t ctrl3_c; 1716 lsm6dsm_ctrl4_c_t ctrl4_c; 1717 lsm6dsm_ctrl5_c_t ctrl5_c; 1718 lsm6dsm_ctrl6_c_t ctrl6_c; 1719 lsm6dsm_ctrl7_g_t ctrl7_g; 1720 lsm6dsm_ctrl8_xl_t ctrl8_xl; 1721 lsm6dsm_ctrl9_xl_t ctrl9_xl; 1722 lsm6dsm_ctrl10_c_t ctrl10_c; 1723 lsm6dsm_master_config_t master_config; 1724 lsm6dsm_wake_up_src_t wake_up_src; 1725 lsm6dsm_tap_src_t tap_src; 1726 lsm6dsm_d6d_src_t d6d_src; 1727 lsm6dsm_status_reg_t status_reg; 1728 lsm6dsm_status_spiaux_t status_spiaux; 1729 lsm6dsm_sensorhub1_reg_t sensorhub1_reg; 1730 lsm6dsm_sensorhub2_reg_t sensorhub2_reg; 1731 lsm6dsm_sensorhub3_reg_t sensorhub3_reg; 1732 lsm6dsm_sensorhub4_reg_t sensorhub4_reg; 1733 lsm6dsm_sensorhub5_reg_t sensorhub5_reg; 1734 lsm6dsm_sensorhub6_reg_t sensorhub6_reg; 1735 lsm6dsm_sensorhub7_reg_t sensorhub7_reg; 1736 lsm6dsm_sensorhub8_reg_t sensorhub8_reg; 1737 lsm6dsm_sensorhub9_reg_t sensorhub9_reg; 1738 lsm6dsm_sensorhub10_reg_t sensorhub10_reg; 1739 lsm6dsm_sensorhub11_reg_t sensorhub11_reg; 1740 lsm6dsm_sensorhub12_reg_t sensorhub12_reg; 1741 lsm6dsm_fifo_status1_t fifo_status1; 1742 lsm6dsm_fifo_status2_t fifo_status2; 1743 lsm6dsm_fifo_status3_t fifo_status3; 1744 lsm6dsm_fifo_status4_t fifo_status4; 1745 lsm6dsm_sensorhub13_reg_t sensorhub13_reg; 1746 lsm6dsm_sensorhub14_reg_t sensorhub14_reg; 1747 lsm6dsm_sensorhub15_reg_t sensorhub15_reg; 1748 lsm6dsm_sensorhub16_reg_t sensorhub16_reg; 1749 lsm6dsm_sensorhub17_reg_t sensorhub17_reg; 1750 lsm6dsm_sensorhub18_reg_t sensorhub18_reg; 1751 lsm6dsm_func_src1_t func_src1; 1752 lsm6dsm_func_src2_t func_src2; 1753 lsm6dsm_wrist_tilt_ia_t wrist_tilt_ia; 1754 lsm6dsm_tap_cfg_t tap_cfg; 1755 lsm6dsm_tap_ths_6d_t tap_ths_6d; 1756 lsm6dsm_int_dur2_t int_dur2; 1757 lsm6dsm_wake_up_ths_t wake_up_ths; 1758 lsm6dsm_wake_up_dur_t wake_up_dur; 1759 lsm6dsm_free_fall_t free_fall; 1760 lsm6dsm_md1_cfg_t md1_cfg; 1761 lsm6dsm_md2_cfg_t md2_cfg; 1762 lsm6dsm_master_cmd_code_t master_cmd_code; 1763 lsm6dsm_sens_sync_spi_error_code_t sens_sync_spi_error_code; 1764 lsm6dsm_int_ois_t int_ois; 1765 lsm6dsm_ctrl1_ois_t ctrl1_ois; 1766 lsm6dsm_ctrl2_ois_t ctrl2_ois; 1767 lsm6dsm_ctrl3_ois_t ctrl3_ois; 1768 lsm6dsm_slv0_add_t slv0_add; 1769 lsm6dsm_slv0_subadd_t slv0_subadd; 1770 lsm6dsm_slave0_config_t slave0_config; 1771 lsm6dsm_slv1_add_t slv1_add; 1772 lsm6dsm_slv1_subadd_t slv1_subadd; 1773 lsm6dsm_slave1_config_t slave1_config; 1774 lsm6dsm_slv2_add_t slv2_add; 1775 lsm6dsm_slv2_subadd_t slv2_subadd; 1776 lsm6dsm_slave2_config_t slave2_config; 1777 lsm6dsm_slv3_add_t slv3_add; 1778 lsm6dsm_slv3_subadd_t slv3_subadd; 1779 lsm6dsm_slave3_config_t slave3_config; 1780 lsm6dsm_datawrite_src_mode_sub_slv0_t 1781 datawrite_src_mode_sub_slv0; 1782 lsm6dsm_config_pedo_ths_min_t config_pedo_ths_min; 1783 lsm6dsm_pedo_deb_reg_t pedo_deb_reg; 1784 lsm6dsm_a_wrist_tilt_mask_t a_wrist_tilt_mask; 1785 bitwise_t bitwise; 1786 uint8_t byte; 1787 } lsm6dsm_reg_t; 1788 1789 /** 1790 * @} 1791 * 1792 */ 1793 1794 #ifndef __weak 1795 #define __weak __attribute__((weak)) 1796 #endif /* __weak */ 1797 1798 /* 1799 * These are the basic platform dependent I/O routines to read 1800 * and write device registers connected on a standard bus. 1801 * The driver keeps offering a default implementation based on function 1802 * pointers to read/write routines for backward compatibility. 1803 * The __weak directive allows the final application to overwrite 1804 * them with a custom implementation. 1805 */ 1806 1807 int32_t lsm6dsm_read_reg(stmdev_ctx_t *ctx, uint8_t reg, 1808 uint8_t *data, 1809 uint16_t len); 1810 int32_t lsm6dsm_write_reg(stmdev_ctx_t *ctx, uint8_t reg, 1811 uint8_t *data, 1812 uint16_t len); 1813 1814 float_t lsm6dsm_from_fs2g_to_mg(int16_t lsb); 1815 float_t lsm6dsm_from_fs4g_to_mg(int16_t lsb); 1816 float_t lsm6dsm_from_fs8g_to_mg(int16_t lsb); 1817 float_t lsm6dsm_from_fs16g_to_mg(int16_t lsb); 1818 1819 float_t lsm6dsm_from_fs125dps_to_mdps(int16_t lsb); 1820 float_t lsm6dsm_from_fs250dps_to_mdps(int16_t lsb); 1821 float_t lsm6dsm_from_fs500dps_to_mdps(int16_t lsb); 1822 float_t lsm6dsm_from_fs1000dps_to_mdps(int16_t lsb); 1823 float_t lsm6dsm_from_fs2000dps_to_mdps(int16_t lsb); 1824 1825 float_t lsm6dsm_from_lsb_to_celsius(int16_t lsb); 1826 1827 typedef enum 1828 { 1829 LSM6DSM_2g = 0, 1830 LSM6DSM_16g = 1, 1831 LSM6DSM_4g = 2, 1832 LSM6DSM_8g = 3, 1833 } lsm6dsm_fs_xl_t; 1834 int32_t lsm6dsm_xl_full_scale_set(stmdev_ctx_t *ctx, 1835 lsm6dsm_fs_xl_t val); 1836 int32_t lsm6dsm_xl_full_scale_get(stmdev_ctx_t *ctx, 1837 lsm6dsm_fs_xl_t *val); 1838 1839 typedef enum 1840 { 1841 LSM6DSM_XL_ODR_OFF = 0, 1842 LSM6DSM_XL_ODR_12Hz5 = 1, 1843 LSM6DSM_XL_ODR_26Hz = 2, 1844 LSM6DSM_XL_ODR_52Hz = 3, 1845 LSM6DSM_XL_ODR_104Hz = 4, 1846 LSM6DSM_XL_ODR_208Hz = 5, 1847 LSM6DSM_XL_ODR_416Hz = 6, 1848 LSM6DSM_XL_ODR_833Hz = 7, 1849 LSM6DSM_XL_ODR_1k66Hz = 8, 1850 LSM6DSM_XL_ODR_3k33Hz = 9, 1851 LSM6DSM_XL_ODR_6k66Hz = 10, 1852 LSM6DSM_XL_ODR_1Hz6 = 11, 1853 } lsm6dsm_odr_xl_t; 1854 int32_t lsm6dsm_xl_data_rate_set(stmdev_ctx_t *ctx, 1855 lsm6dsm_odr_xl_t val); 1856 int32_t lsm6dsm_xl_data_rate_get(stmdev_ctx_t *ctx, 1857 lsm6dsm_odr_xl_t *val); 1858 1859 typedef enum 1860 { 1861 LSM6DSM_250dps = 0, 1862 LSM6DSM_125dps = 1, 1863 LSM6DSM_500dps = 2, 1864 LSM6DSM_1000dps = 4, 1865 LSM6DSM_2000dps = 6, 1866 } lsm6dsm_fs_g_t; 1867 int32_t lsm6dsm_gy_full_scale_set(stmdev_ctx_t *ctx, 1868 lsm6dsm_fs_g_t val); 1869 int32_t lsm6dsm_gy_full_scale_get(stmdev_ctx_t *ctx, 1870 lsm6dsm_fs_g_t *val); 1871 1872 typedef enum 1873 { 1874 LSM6DSM_GY_ODR_OFF = 0, 1875 LSM6DSM_GY_ODR_12Hz5 = 1, 1876 LSM6DSM_GY_ODR_26Hz = 2, 1877 LSM6DSM_GY_ODR_52Hz = 3, 1878 LSM6DSM_GY_ODR_104Hz = 4, 1879 LSM6DSM_GY_ODR_208Hz = 5, 1880 LSM6DSM_GY_ODR_416Hz = 6, 1881 LSM6DSM_GY_ODR_833Hz = 7, 1882 LSM6DSM_GY_ODR_1k66Hz = 8, 1883 LSM6DSM_GY_ODR_3k33Hz = 9, 1884 LSM6DSM_GY_ODR_6k66Hz = 10, 1885 } lsm6dsm_odr_g_t; 1886 int32_t lsm6dsm_gy_data_rate_set(stmdev_ctx_t *ctx, 1887 lsm6dsm_odr_g_t val); 1888 int32_t lsm6dsm_gy_data_rate_get(stmdev_ctx_t *ctx, 1889 lsm6dsm_odr_g_t *val); 1890 1891 int32_t lsm6dsm_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); 1892 int32_t lsm6dsm_block_data_update_get(stmdev_ctx_t *ctx, 1893 uint8_t *val); 1894 1895 typedef enum 1896 { 1897 LSM6DSM_LSb_1mg = 0, 1898 LSM6DSM_LSb_16mg = 1, 1899 } lsm6dsm_usr_off_w_t; 1900 int32_t lsm6dsm_xl_offset_weight_set(stmdev_ctx_t *ctx, 1901 lsm6dsm_usr_off_w_t val); 1902 int32_t lsm6dsm_xl_offset_weight_get(stmdev_ctx_t *ctx, 1903 lsm6dsm_usr_off_w_t *val); 1904 1905 typedef enum 1906 { 1907 LSM6DSM_XL_HIGH_PERFORMANCE = 0, 1908 LSM6DSM_XL_NORMAL = 1, 1909 } lsm6dsm_xl_hm_mode_t; 1910 int32_t lsm6dsm_xl_power_mode_set(stmdev_ctx_t *ctx, 1911 lsm6dsm_xl_hm_mode_t val); 1912 int32_t lsm6dsm_xl_power_mode_get(stmdev_ctx_t *ctx, 1913 lsm6dsm_xl_hm_mode_t *val); 1914 1915 typedef enum 1916 { 1917 LSM6DSM_STAT_RND_DISABLE = 0, 1918 LSM6DSM_STAT_RND_ENABLE = 1, 1919 } lsm6dsm_rounding_status_t; 1920 int32_t lsm6dsm_rounding_on_status_set(stmdev_ctx_t *ctx, 1921 lsm6dsm_rounding_status_t val); 1922 int32_t lsm6dsm_rounding_on_status_get(stmdev_ctx_t *ctx, 1923 lsm6dsm_rounding_status_t *val); 1924 1925 typedef enum 1926 { 1927 LSM6DSM_GY_HIGH_PERFORMANCE = 0, 1928 LSM6DSM_GY_NORMAL = 1, 1929 } lsm6dsm_g_hm_mode_t; 1930 int32_t lsm6dsm_gy_power_mode_set(stmdev_ctx_t *ctx, 1931 lsm6dsm_g_hm_mode_t val); 1932 int32_t lsm6dsm_gy_power_mode_get(stmdev_ctx_t *ctx, 1933 lsm6dsm_g_hm_mode_t *val); 1934 1935 typedef struct 1936 { 1937 lsm6dsm_wake_up_src_t wake_up_src; 1938 lsm6dsm_tap_src_t tap_src; 1939 lsm6dsm_d6d_src_t d6d_src; 1940 lsm6dsm_status_reg_t status_reg; 1941 lsm6dsm_func_src1_t func_src1; 1942 lsm6dsm_func_src2_t func_src2; 1943 lsm6dsm_wrist_tilt_ia_t wrist_tilt_ia; 1944 lsm6dsm_a_wrist_tilt_mask_t a_wrist_tilt_mask; 1945 } lsm6dsm_all_sources_t; 1946 int32_t lsm6dsm_all_sources_get(stmdev_ctx_t *ctx, 1947 lsm6dsm_all_sources_t *val); 1948 1949 int32_t lsm6dsm_status_reg_get(stmdev_ctx_t *ctx, 1950 lsm6dsm_status_reg_t *val); 1951 1952 int32_t lsm6dsm_xl_flag_data_ready_get(stmdev_ctx_t *ctx, 1953 uint8_t *val); 1954 1955 int32_t lsm6dsm_gy_flag_data_ready_get(stmdev_ctx_t *ctx, 1956 uint8_t *val); 1957 1958 int32_t lsm6dsm_temp_flag_data_ready_get(stmdev_ctx_t *ctx, 1959 uint8_t *val); 1960 1961 int32_t lsm6dsm_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t *buff); 1962 int32_t lsm6dsm_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *buff); 1963 int32_t lsm6dsm_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); 1964 int32_t lsm6dsm_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); 1965 1966 typedef enum 1967 { 1968 LSM6DSM_LSB_6ms4 = 0, 1969 LSM6DSM_LSB_25us = 1, 1970 } lsm6dsm_timer_hr_t; 1971 int32_t lsm6dsm_timestamp_res_set(stmdev_ctx_t *ctx, 1972 lsm6dsm_timer_hr_t val); 1973 int32_t lsm6dsm_timestamp_res_get(stmdev_ctx_t *ctx, 1974 lsm6dsm_timer_hr_t *val); 1975 1976 typedef enum 1977 { 1978 LSM6DSM_ROUND_DISABLE = 0, 1979 LSM6DSM_ROUND_XL = 1, 1980 LSM6DSM_ROUND_GY = 2, 1981 LSM6DSM_ROUND_GY_XL = 3, 1982 LSM6DSM_ROUND_SH1_TO_SH6 = 4, 1983 LSM6DSM_ROUND_XL_SH1_TO_SH6 = 5, 1984 LSM6DSM_ROUND_GY_XL_SH1_TO_SH12 = 6, 1985 LSM6DSM_ROUND_GY_XL_SH1_TO_SH6 = 7, 1986 } lsm6dsm_rounding_t; 1987 int32_t lsm6dsm_rounding_mode_set(stmdev_ctx_t *ctx, 1988 lsm6dsm_rounding_t val); 1989 int32_t lsm6dsm_rounding_mode_get(stmdev_ctx_t *ctx, 1990 lsm6dsm_rounding_t *val); 1991 1992 int32_t lsm6dsm_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); 1993 int32_t lsm6dsm_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val); 1994 int32_t lsm6dsm_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val); 1995 1996 int32_t lsm6dsm_mag_calibrated_raw_get(stmdev_ctx_t *ctx, 1997 int16_t *val); 1998 1999 int32_t lsm6dsm_fifo_raw_data_get(stmdev_ctx_t *ctx, uint8_t *buffer, 2000 uint8_t len); 2001 2002 typedef enum 2003 { 2004 LSM6DSM_USER_BANK = 0, 2005 LSM6DSM_BANK_A = 4, 2006 LSM6DSM_BANK_B = 5, 2007 } lsm6dsm_func_cfg_en_t; 2008 int32_t lsm6dsm_mem_bank_set(stmdev_ctx_t *ctx, 2009 lsm6dsm_func_cfg_en_t val); 2010 int32_t lsm6dsm_mem_bank_get(stmdev_ctx_t *ctx, 2011 lsm6dsm_func_cfg_en_t *val); 2012 2013 typedef enum 2014 { 2015 LSM6DSM_DRDY_LATCHED = 0, 2016 LSM6DSM_DRDY_PULSED = 1, 2017 } lsm6dsm_drdy_pulsed_g_t; 2018 int32_t lsm6dsm_data_ready_mode_set(stmdev_ctx_t *ctx, 2019 lsm6dsm_drdy_pulsed_g_t val); 2020 int32_t lsm6dsm_data_ready_mode_get(stmdev_ctx_t *ctx, 2021 lsm6dsm_drdy_pulsed_g_t *val); 2022 2023 int32_t lsm6dsm_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); 2024 int32_t lsm6dsm_reset_set(stmdev_ctx_t *ctx, uint8_t val); 2025 int32_t lsm6dsm_reset_get(stmdev_ctx_t *ctx, uint8_t *val); 2026 2027 typedef enum 2028 { 2029 LSM6DSM_LSB_AT_LOW_ADD = 0, 2030 LSM6DSM_MSB_AT_LOW_ADD = 1, 2031 } lsm6dsm_ble_t; 2032 int32_t lsm6dsm_data_format_set(stmdev_ctx_t *ctx, lsm6dsm_ble_t val); 2033 int32_t lsm6dsm_data_format_get(stmdev_ctx_t *ctx, 2034 lsm6dsm_ble_t *val); 2035 2036 int32_t lsm6dsm_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); 2037 int32_t lsm6dsm_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); 2038 2039 int32_t lsm6dsm_boot_set(stmdev_ctx_t *ctx, uint8_t val); 2040 int32_t lsm6dsm_boot_get(stmdev_ctx_t *ctx, uint8_t *val); 2041 2042 typedef enum 2043 { 2044 LSM6DSM_XL_ST_DISABLE = 0, 2045 LSM6DSM_XL_ST_POSITIVE = 1, 2046 LSM6DSM_XL_ST_NEGATIVE = 2, 2047 } lsm6dsm_st_xl_t; 2048 int32_t lsm6dsm_xl_self_test_set(stmdev_ctx_t *ctx, 2049 lsm6dsm_st_xl_t val); 2050 int32_t lsm6dsm_xl_self_test_get(stmdev_ctx_t *ctx, 2051 lsm6dsm_st_xl_t *val); 2052 2053 typedef enum 2054 { 2055 LSM6DSM_GY_ST_DISABLE = 0, 2056 LSM6DSM_GY_ST_POSITIVE = 1, 2057 LSM6DSM_GY_ST_NEGATIVE = 3, 2058 } lsm6dsm_st_g_t; 2059 int32_t lsm6dsm_gy_self_test_set(stmdev_ctx_t *ctx, 2060 lsm6dsm_st_g_t val); 2061 int32_t lsm6dsm_gy_self_test_get(stmdev_ctx_t *ctx, 2062 lsm6dsm_st_g_t *val); 2063 2064 int32_t lsm6dsm_filter_settling_mask_set(stmdev_ctx_t *ctx, 2065 uint8_t val); 2066 int32_t lsm6dsm_filter_settling_mask_get(stmdev_ctx_t *ctx, 2067 uint8_t *val); 2068 2069 typedef enum 2070 { 2071 LSM6DSM_USE_SLOPE = 0, 2072 LSM6DSM_USE_HPF = 1, 2073 } lsm6dsm_slope_fds_t; 2074 int32_t lsm6dsm_xl_hp_path_internal_set(stmdev_ctx_t *ctx, 2075 lsm6dsm_slope_fds_t val); 2076 int32_t lsm6dsm_xl_hp_path_internal_get(stmdev_ctx_t *ctx, 2077 lsm6dsm_slope_fds_t *val); 2078 2079 typedef enum 2080 { 2081 LSM6DSM_XL_ANA_BW_1k5Hz = 0, 2082 LSM6DSM_XL_ANA_BW_400Hz = 1, 2083 } lsm6dsm_bw0_xl_t; 2084 int32_t lsm6dsm_xl_filter_analog_set(stmdev_ctx_t *ctx, 2085 lsm6dsm_bw0_xl_t val); 2086 int32_t lsm6dsm_xl_filter_analog_get(stmdev_ctx_t *ctx, 2087 lsm6dsm_bw0_xl_t *val); 2088 2089 typedef enum 2090 { 2091 LSM6DSM_XL_LP1_ODR_DIV_2 = 0, 2092 LSM6DSM_XL_LP1_ODR_DIV_4 = 1, 2093 LSM6DSM_XL_LP1_NA = 2, /* ERROR CODE */ 2094 } lsm6dsm_lpf1_bw_sel_t; 2095 int32_t lsm6dsm_xl_lp1_bandwidth_set(stmdev_ctx_t *ctx, 2096 lsm6dsm_lpf1_bw_sel_t val); 2097 int32_t lsm6dsm_xl_lp1_bandwidth_get(stmdev_ctx_t *ctx, 2098 lsm6dsm_lpf1_bw_sel_t *val); 2099 2100 typedef enum 2101 { 2102 LSM6DSM_XL_LOW_LAT_LP_ODR_DIV_50 = 0x00, 2103 LSM6DSM_XL_LOW_LAT_LP_ODR_DIV_100 = 0x01, 2104 LSM6DSM_XL_LOW_LAT_LP_ODR_DIV_9 = 0x02, 2105 LSM6DSM_XL_LOW_LAT_LP_ODR_DIV_400 = 0x03, 2106 LSM6DSM_XL_LOW_NOISE_LP_ODR_DIV_50 = 0x10, 2107 LSM6DSM_XL_LOW_NOISE_LP_ODR_DIV_100 = 0x11, 2108 LSM6DSM_XL_LOW_NOISE_LP_ODR_DIV_9 = 0x12, 2109 LSM6DSM_XL_LOW_NOISE_LP_ODR_DIV_400 = 0x13, 2110 LSM6DSM_XL_LP_NA = 0x20, /* ERROR CODE */ 2111 } lsm6dsm_input_composite_t; 2112 int32_t lsm6dsm_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx, 2113 lsm6dsm_input_composite_t val); 2114 int32_t lsm6dsm_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx, 2115 lsm6dsm_input_composite_t *val); 2116 2117 int32_t lsm6dsm_xl_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val); 2118 int32_t lsm6dsm_xl_reference_mode_get(stmdev_ctx_t *ctx, 2119 uint8_t *val); 2120 2121 typedef enum 2122 { 2123 LSM6DSM_XL_HP_ODR_DIV_4 = 0x00, /* Slope filter */ 2124 LSM6DSM_XL_HP_ODR_DIV_100 = 0x01, 2125 LSM6DSM_XL_HP_ODR_DIV_9 = 0x02, 2126 LSM6DSM_XL_HP_ODR_DIV_400 = 0x03, 2127 LSM6DSM_XL_HP_NA = 0x10, /* ERROR CODE */ 2128 } lsm6dsm_hpcf_xl_t; 2129 int32_t lsm6dsm_xl_hp_bandwidth_set(stmdev_ctx_t *ctx, 2130 lsm6dsm_hpcf_xl_t val); 2131 int32_t lsm6dsm_xl_hp_bandwidth_get(stmdev_ctx_t *ctx, 2132 lsm6dsm_hpcf_xl_t *val); 2133 2134 typedef enum 2135 { 2136 LSM6DSM_XL_UI_LP1_ODR_DIV_2 = 0, 2137 LSM6DSM_XL_UI_LP1_ODR_DIV_4 = 1, 2138 LSM6DSM_XL_UI_LP1_NA = 2, 2139 } lsm6dsm_ui_lpf1_bw_sel_t; 2140 int32_t lsm6dsm_xl_ui_lp1_bandwidth_set(stmdev_ctx_t *ctx, 2141 lsm6dsm_ui_lpf1_bw_sel_t val); 2142 int32_t lsm6dsm_xl_ui_lp1_bandwidth_get(stmdev_ctx_t *ctx, 2143 lsm6dsm_ui_lpf1_bw_sel_t *val); 2144 2145 int32_t lsm6dsm_xl_ui_slope_set(stmdev_ctx_t *ctx, uint8_t val); 2146 int32_t lsm6dsm_xl_ui_slope_get(stmdev_ctx_t *ctx, uint8_t *val); 2147 2148 typedef enum 2149 { 2150 LSM6DSM_AUX_LP_LIGHT = 2, 2151 LSM6DSM_AUX_LP_NORMAL = 3, 2152 LSM6DSM_AUX_LP_STRONG = 0, 2153 LSM6DSM_AUX_LP_AGGRESSIVE = 1, 2154 } lsm6dsm_filter_xl_conf_ois_t; 2155 int32_t lsm6dsm_xl_aux_lp_bandwidth_set(stmdev_ctx_t *ctx, 2156 lsm6dsm_filter_xl_conf_ois_t val); 2157 int32_t lsm6dsm_xl_aux_lp_bandwidth_get(stmdev_ctx_t *ctx, 2158 lsm6dsm_filter_xl_conf_ois_t *val); 2159 2160 typedef enum 2161 { 2162 LSM6DSM_LP2_ONLY = 0x00, 2163 2164 LSM6DSM_HP_16mHz_LP2 = 0x80, 2165 LSM6DSM_HP_65mHz_LP2 = 0x90, 2166 LSM6DSM_HP_260mHz_LP2 = 0xA0, 2167 LSM6DSM_HP_1Hz04_LP2 = 0xB0, 2168 2169 LSM6DSM_HP_DISABLE_LP1_LIGHT = 0x0A, 2170 LSM6DSM_HP_DISABLE_LP1_NORMAL = 0x09, 2171 LSM6DSM_HP_DISABLE_LP_STRONG = 0x08, 2172 LSM6DSM_HP_DISABLE_LP1_AGGRESSIVE = 0x0B, 2173 2174 LSM6DSM_HP_16mHz_LP1_LIGHT = 0x8A, 2175 LSM6DSM_HP_65mHz_LP1_NORMAL = 0x99, 2176 LSM6DSM_HP_260mHz_LP1_STRONG = 0xA8, 2177 LSM6DSM_HP_1Hz04_LP1_AGGRESSIVE = 0xBB, 2178 } lsm6dsm_lpf1_sel_g_t; 2179 int32_t lsm6dsm_gy_band_pass_set(stmdev_ctx_t *ctx, 2180 lsm6dsm_lpf1_sel_g_t val); 2181 int32_t lsm6dsm_gy_band_pass_get(stmdev_ctx_t *ctx, 2182 lsm6dsm_lpf1_sel_g_t *val); 2183 2184 int32_t lsm6dsm_gy_ui_high_pass_set(stmdev_ctx_t *ctx, uint8_t val); 2185 int32_t lsm6dsm_gy_ui_high_pass_get(stmdev_ctx_t *ctx, uint8_t *val); 2186 2187 typedef enum 2188 { 2189 LSM6DSM_HP_DISABLE_LP_173Hz = 0x02, 2190 LSM6DSM_HP_DISABLE_LP_237Hz = 0x01, 2191 LSM6DSM_HP_DISABLE_LP_351Hz = 0x00, 2192 LSM6DSM_HP_DISABLE_LP_937Hz = 0x03, 2193 2194 LSM6DSM_HP_16mHz_LP_173Hz = 0x82, 2195 LSM6DSM_HP_65mHz_LP_237Hz = 0x91, 2196 LSM6DSM_HP_260mHz_LP_351Hz = 0xA0, 2197 LSM6DSM_HP_1Hz04_LP_937Hz = 0xB3, 2198 } lsm6dsm_hp_en_ois_t; 2199 int32_t lsm6dsm_gy_aux_bandwidth_set(stmdev_ctx_t *ctx, 2200 lsm6dsm_hp_en_ois_t val); 2201 int32_t lsm6dsm_gy_aux_bandwidth_get(stmdev_ctx_t *ctx, 2202 lsm6dsm_hp_en_ois_t *val); 2203 2204 int32_t lsm6dsm_aux_status_reg_get(stmdev_ctx_t *ctx, 2205 lsm6dsm_status_spiaux_t *val); 2206 2207 int32_t lsm6dsm_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx, 2208 uint8_t *val); 2209 2210 int32_t lsm6dsm_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx, 2211 uint8_t *val); 2212 2213 int32_t lsm6dsm_aux_gy_flag_settling_get(stmdev_ctx_t *ctx, 2214 uint8_t *val); 2215 2216 typedef enum 2217 { 2218 LSM6DSM_AUX_DEN_DISABLE = 0, 2219 LSM6DSM_AUX_DEN_LEVEL_LATCH = 3, 2220 LSM6DSM_AUX_DEN_LEVEL_TRIG = 2, 2221 } lsm6dsm_lvl_ois_t; 2222 int32_t lsm6dsm_aux_den_mode_set(stmdev_ctx_t *ctx, 2223 lsm6dsm_lvl_ois_t val); 2224 int32_t lsm6dsm_aux_den_mode_get(stmdev_ctx_t *ctx, 2225 lsm6dsm_lvl_ois_t *val); 2226 2227 int32_t lsm6dsm_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val); 2228 int32_t lsm6dsm_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val); 2229 2230 typedef enum 2231 { 2232 LSM6DSM_AUX_DISABLE = 0, 2233 LSM6DSM_MODE_3_GY = 1, 2234 LSM6DSM_MODE_4_GY_XL = 3, 2235 } lsm6dsm_ois_en_spi2_t; 2236 int32_t lsm6dsm_aux_mode_set(stmdev_ctx_t *ctx, 2237 lsm6dsm_ois_en_spi2_t val); 2238 int32_t lsm6dsm_aux_mode_get(stmdev_ctx_t *ctx, 2239 lsm6dsm_ois_en_spi2_t *val); 2240 2241 typedef enum 2242 { 2243 LSM6DSM_250dps_AUX = 0, 2244 LSM6DSM_125dps_AUX = 1, 2245 LSM6DSM_500dps_AUX = 2, 2246 LSM6DSM_1000dps_AUX = 4, 2247 LSM6DSM_2000dps_AUX = 6, 2248 } lsm6dsm_fs_g_ois_t; 2249 int32_t lsm6dsm_aux_gy_full_scale_set(stmdev_ctx_t *ctx, 2250 lsm6dsm_fs_g_ois_t val); 2251 int32_t lsm6dsm_aux_gy_full_scale_get(stmdev_ctx_t *ctx, 2252 lsm6dsm_fs_g_ois_t *val); 2253 2254 typedef enum 2255 { 2256 LSM6DSM_AUX_SPI_4_WIRE = 0, 2257 LSM6DSM_AUX_SPI_3_WIRE = 1, 2258 } lsm6dsm_sim_ois_t; 2259 int32_t lsm6dsm_aux_spi_mode_set(stmdev_ctx_t *ctx, 2260 lsm6dsm_sim_ois_t val); 2261 int32_t lsm6dsm_aux_spi_mode_get(stmdev_ctx_t *ctx, 2262 lsm6dsm_sim_ois_t *val); 2263 2264 typedef enum 2265 { 2266 LSM6DSM_AUX_LSB_AT_LOW_ADD = 0, 2267 LSM6DSM_AUX_MSB_AT_LOW_ADD = 1, 2268 } lsm6dsm_ble_ois_t; 2269 int32_t lsm6dsm_aux_data_format_set(stmdev_ctx_t *ctx, 2270 lsm6dsm_ble_ois_t val); 2271 int32_t lsm6dsm_aux_data_format_get(stmdev_ctx_t *ctx, 2272 lsm6dsm_ble_ois_t *val); 2273 2274 typedef enum 2275 { 2276 LSM6DSM_ENABLE_CLAMP = 0, 2277 LSM6DSM_DISABLE_CLAMP = 1, 2278 } lsm6dsm_st_ois_clampdis_t; 2279 int32_t lsm6dsm_aux_gy_clamp_set(stmdev_ctx_t *ctx, 2280 lsm6dsm_st_ois_clampdis_t val); 2281 int32_t lsm6dsm_aux_gy_clamp_get(stmdev_ctx_t *ctx, 2282 lsm6dsm_st_ois_clampdis_t *val); 2283 2284 typedef enum 2285 { 2286 LSM6DSM_AUX_GY_DISABLE = 0, 2287 LSM6DSM_AUX_GY_POS = 1, 2288 LSM6DSM_AUX_GY_NEG = 3, 2289 } lsm6dsm_st_ois_t; 2290 int32_t lsm6dsm_aux_gy_self_test_set(stmdev_ctx_t *ctx, 2291 lsm6dsm_st_ois_t val); 2292 int32_t lsm6dsm_aux_gy_self_test_get(stmdev_ctx_t *ctx, 2293 lsm6dsm_st_ois_t *val); 2294 2295 typedef enum 2296 { 2297 LSM6DSM_AUX_2g = 0, 2298 LSM6DSM_AUX_16g = 1, 2299 LSM6DSM_AUX_4g = 2, 2300 LSM6DSM_AUX_8g = 3, 2301 } lsm6dsm_fs_xl_ois_t; 2302 int32_t lsm6dsm_aux_xl_full_scale_set(stmdev_ctx_t *ctx, 2303 lsm6dsm_fs_xl_ois_t val); 2304 int32_t lsm6dsm_aux_xl_full_scale_get(stmdev_ctx_t *ctx, 2305 lsm6dsm_fs_xl_ois_t *val); 2306 2307 typedef enum 2308 { 2309 LSM6DSM_AUX_DEN_ACTIVE_LOW = 0, 2310 LSM6DSM_AUX_DEN_ACTIVE_HIGH = 1, 2311 } lsm6dsm_den_lh_ois_t; 2312 int32_t lsm6dsm_aux_den_polarity_set(stmdev_ctx_t *ctx, 2313 lsm6dsm_den_lh_ois_t val); 2314 int32_t lsm6dsm_aux_den_polarity_get(stmdev_ctx_t *ctx, 2315 lsm6dsm_den_lh_ois_t *val); 2316 2317 typedef enum 2318 { 2319 LSM6DSM_SPI_4_WIRE = 0, 2320 LSM6DSM_SPI_3_WIRE = 1, 2321 } lsm6dsm_sim_t; 2322 int32_t lsm6dsm_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsm_sim_t val); 2323 int32_t lsm6dsm_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsm_sim_t *val); 2324 2325 typedef enum 2326 { 2327 LSM6DSM_I2C_ENABLE = 0, 2328 LSM6DSM_I2C_DISABLE = 1, 2329 } lsm6dsm_i2c_disable_t; 2330 int32_t lsm6dsm_i2c_interface_set(stmdev_ctx_t *ctx, 2331 lsm6dsm_i2c_disable_t val); 2332 int32_t lsm6dsm_i2c_interface_get(stmdev_ctx_t *ctx, 2333 lsm6dsm_i2c_disable_t *val); 2334 2335 typedef struct 2336 { 2337 uint8_t int1_drdy_xl : 1; 2338 uint8_t int1_drdy_g : 1; 2339 uint8_t int1_boot : 1; 2340 uint8_t int1_fth : 1; 2341 uint8_t int1_fifo_ovr : 1; 2342 uint8_t int1_full_flag : 1; 2343 uint8_t int1_sign_mot : 1; 2344 uint8_t int1_step_detector : 1; 2345 uint8_t int1_timer : 1; 2346 uint8_t int1_tilt : 1; 2347 uint8_t int1_6d : 1; 2348 uint8_t int1_double_tap : 1; 2349 uint8_t int1_ff : 1; 2350 uint8_t int1_wu : 1; 2351 uint8_t int1_single_tap : 1; 2352 uint8_t int1_inact_state : 1; 2353 uint8_t den_drdy_int1 : 1; 2354 uint8_t drdy_on_int1 : 1; 2355 } lsm6dsm_int1_route_t; 2356 int32_t lsm6dsm_pin_int1_route_set(stmdev_ctx_t *ctx, 2357 lsm6dsm_int1_route_t val); 2358 int32_t lsm6dsm_pin_int1_route_get(stmdev_ctx_t *ctx, 2359 lsm6dsm_int1_route_t *val); 2360 2361 typedef struct 2362 { 2363 uint8_t int2_drdy_xl : 1; 2364 uint8_t int2_drdy_g : 1; 2365 uint8_t int2_drdy_temp : 1; 2366 uint8_t int2_fth : 1; 2367 uint8_t int2_fifo_ovr : 1; 2368 uint8_t int2_full_flag : 1; 2369 uint8_t int2_step_count_ov : 1; 2370 uint8_t int2_step_delta : 1; 2371 uint8_t int2_iron : 1; 2372 uint8_t int2_tilt : 1; 2373 uint8_t int2_6d : 1; 2374 uint8_t int2_double_tap : 1; 2375 uint8_t int2_ff : 1; 2376 uint8_t int2_wu : 1; 2377 uint8_t int2_single_tap : 1; 2378 uint8_t int2_inact_state : 1; 2379 uint8_t int2_wrist_tilt : 1; 2380 } lsm6dsm_int2_route_t; 2381 int32_t lsm6dsm_pin_int2_route_set(stmdev_ctx_t *ctx, 2382 lsm6dsm_int2_route_t val); 2383 int32_t lsm6dsm_pin_int2_route_get(stmdev_ctx_t *ctx, 2384 lsm6dsm_int2_route_t *val); 2385 2386 typedef enum 2387 { 2388 LSM6DSM_PUSH_PULL = 0, 2389 LSM6DSM_OPEN_DRAIN = 1, 2390 } lsm6dsm_pp_od_t; 2391 int32_t lsm6dsm_pin_mode_set(stmdev_ctx_t *ctx, lsm6dsm_pp_od_t val); 2392 int32_t lsm6dsm_pin_mode_get(stmdev_ctx_t *ctx, lsm6dsm_pp_od_t *val); 2393 2394 typedef enum 2395 { 2396 LSM6DSM_ACTIVE_HIGH = 0, 2397 LSM6DSM_ACTIVE_LOW = 1, 2398 } lsm6dsm_h_lactive_t; 2399 int32_t lsm6dsm_pin_polarity_set(stmdev_ctx_t *ctx, 2400 lsm6dsm_h_lactive_t val); 2401 int32_t lsm6dsm_pin_polarity_get(stmdev_ctx_t *ctx, 2402 lsm6dsm_h_lactive_t *val); 2403 2404 int32_t lsm6dsm_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); 2405 int32_t lsm6dsm_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); 2406 2407 typedef enum 2408 { 2409 LSM6DSM_INT_PULSED = 0, 2410 LSM6DSM_INT_LATCHED = 1, 2411 } lsm6dsm_lir_t; 2412 int32_t lsm6dsm_int_notification_set(stmdev_ctx_t *ctx, 2413 lsm6dsm_lir_t val); 2414 int32_t lsm6dsm_int_notification_get(stmdev_ctx_t *ctx, 2415 lsm6dsm_lir_t *val); 2416 2417 int32_t lsm6dsm_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val); 2418 int32_t lsm6dsm_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); 2419 2420 int32_t lsm6dsm_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val); 2421 int32_t lsm6dsm_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 2422 2423 int32_t lsm6dsm_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val); 2424 int32_t lsm6dsm_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val); 2425 2426 typedef enum 2427 { 2428 LSM6DSM_PROPERTY_DISABLE = 0, 2429 LSM6DSM_XL_12Hz5_GY_NOT_AFFECTED = 1, 2430 LSM6DSM_XL_12Hz5_GY_SLEEP = 2, 2431 LSM6DSM_XL_12Hz5_GY_PD = 3, 2432 } lsm6dsm_inact_en_t; 2433 int32_t lsm6dsm_act_mode_set(stmdev_ctx_t *ctx, 2434 lsm6dsm_inact_en_t val); 2435 int32_t lsm6dsm_act_mode_get(stmdev_ctx_t *ctx, 2436 lsm6dsm_inact_en_t *val); 2437 2438 int32_t lsm6dsm_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val); 2439 int32_t lsm6dsm_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 2440 2441 int32_t lsm6dsm_tap_src_get(stmdev_ctx_t *ctx, 2442 lsm6dsm_tap_src_t *val); 2443 2444 int32_t lsm6dsm_tap_detection_on_z_set(stmdev_ctx_t *ctx, 2445 uint8_t val); 2446 int32_t lsm6dsm_tap_detection_on_z_get(stmdev_ctx_t *ctx, 2447 uint8_t *val); 2448 2449 int32_t lsm6dsm_tap_detection_on_y_set(stmdev_ctx_t *ctx, 2450 uint8_t val); 2451 int32_t lsm6dsm_tap_detection_on_y_get(stmdev_ctx_t *ctx, 2452 uint8_t *val); 2453 2454 int32_t lsm6dsm_tap_detection_on_x_set(stmdev_ctx_t *ctx, 2455 uint8_t val); 2456 int32_t lsm6dsm_tap_detection_on_x_get(stmdev_ctx_t *ctx, 2457 uint8_t *val); 2458 2459 int32_t lsm6dsm_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val); 2460 int32_t lsm6dsm_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val); 2461 2462 int32_t lsm6dsm_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val); 2463 int32_t lsm6dsm_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val); 2464 2465 int32_t lsm6dsm_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val); 2466 int32_t lsm6dsm_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val); 2467 2468 int32_t lsm6dsm_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val); 2469 int32_t lsm6dsm_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 2470 2471 typedef enum 2472 { 2473 LSM6DSM_ONLY_SINGLE = 0, 2474 LSM6DSM_BOTH_SINGLE_DOUBLE = 1, 2475 } lsm6dsm_single_double_tap_t; 2476 int32_t lsm6dsm_tap_mode_set(stmdev_ctx_t *ctx, 2477 lsm6dsm_single_double_tap_t val); 2478 int32_t lsm6dsm_tap_mode_get(stmdev_ctx_t *ctx, 2479 lsm6dsm_single_double_tap_t *val); 2480 2481 typedef enum 2482 { 2483 LSM6DSM_ODR_DIV_2_FEED = 0, 2484 LSM6DSM_LPF2_FEED = 1, 2485 } lsm6dsm_low_pass_on_6d_t; 2486 int32_t lsm6dsm_6d_feed_data_set(stmdev_ctx_t *ctx, 2487 lsm6dsm_low_pass_on_6d_t val); 2488 int32_t lsm6dsm_6d_feed_data_get(stmdev_ctx_t *ctx, 2489 lsm6dsm_low_pass_on_6d_t *val); 2490 2491 typedef enum 2492 { 2493 LSM6DSM_DEG_80 = 0, 2494 LSM6DSM_DEG_70 = 1, 2495 LSM6DSM_DEG_60 = 2, 2496 LSM6DSM_DEG_50 = 3, 2497 } lsm6dsm_sixd_ths_t; 2498 int32_t lsm6dsm_6d_threshold_set(stmdev_ctx_t *ctx, 2499 lsm6dsm_sixd_ths_t val); 2500 int32_t lsm6dsm_6d_threshold_get(stmdev_ctx_t *ctx, 2501 lsm6dsm_sixd_ths_t *val); 2502 2503 int32_t lsm6dsm_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val); 2504 int32_t lsm6dsm_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val); 2505 2506 int32_t lsm6dsm_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val); 2507 int32_t lsm6dsm_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 2508 2509 typedef enum 2510 { 2511 LSM6DSM_FF_TSH_156mg = 0, 2512 LSM6DSM_FF_TSH_219mg = 1, 2513 LSM6DSM_FF_TSH_250mg = 2, 2514 LSM6DSM_FF_TSH_312mg = 3, 2515 LSM6DSM_FF_TSH_344mg = 4, 2516 LSM6DSM_FF_TSH_406mg = 5, 2517 LSM6DSM_FF_TSH_469mg = 6, 2518 LSM6DSM_FF_TSH_500mg = 7, 2519 } lsm6dsm_ff_ths_t; 2520 int32_t lsm6dsm_ff_threshold_set(stmdev_ctx_t *ctx, 2521 lsm6dsm_ff_ths_t val); 2522 int32_t lsm6dsm_ff_threshold_get(stmdev_ctx_t *ctx, 2523 lsm6dsm_ff_ths_t *val); 2524 2525 int32_t lsm6dsm_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val); 2526 int32_t lsm6dsm_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val); 2527 2528 int32_t lsm6dsm_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val); 2529 2530 int32_t lsm6dsm_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); 2531 int32_t lsm6dsm_fifo_over_run_get(stmdev_ctx_t *ctx, uint8_t *val); 2532 2533 int32_t lsm6dsm_fifo_pattern_get(stmdev_ctx_t *ctx, uint16_t *val); 2534 2535 int32_t lsm6dsm_fifo_temp_batch_set(stmdev_ctx_t *ctx, uint8_t val); 2536 int32_t lsm6dsm_fifo_temp_batch_get(stmdev_ctx_t *ctx, uint8_t *val); 2537 2538 typedef enum 2539 { 2540 LSM6DSM_TRG_XL_GY_DRDY = 0, 2541 LSM6DSM_TRG_STEP_DETECT = 1, 2542 LSM6DSM_TRG_SH_DRDY = 2, 2543 } lsm6dsm_trigger_fifo_t; 2544 int32_t lsm6dsm_fifo_write_trigger_set(stmdev_ctx_t *ctx, 2545 lsm6dsm_trigger_fifo_t val); 2546 int32_t lsm6dsm_fifo_write_trigger_get(stmdev_ctx_t *ctx, 2547 lsm6dsm_trigger_fifo_t *val); 2548 2549 int32_t lsm6dsm_fifo_pedo_and_timestamp_batch_set(stmdev_ctx_t *ctx, 2550 uint8_t val); 2551 int32_t lsm6dsm_fifo_pedo_and_timestamp_batch_get(stmdev_ctx_t *ctx, 2552 uint8_t *val); 2553 2554 typedef enum 2555 { 2556 LSM6DSM_FIFO_XL_DISABLE = 0, 2557 LSM6DSM_FIFO_XL_NO_DEC = 1, 2558 LSM6DSM_FIFO_XL_DEC_2 = 2, 2559 LSM6DSM_FIFO_XL_DEC_3 = 3, 2560 LSM6DSM_FIFO_XL_DEC_4 = 4, 2561 LSM6DSM_FIFO_XL_DEC_8 = 5, 2562 LSM6DSM_FIFO_XL_DEC_16 = 6, 2563 LSM6DSM_FIFO_XL_DEC_32 = 7, 2564 } lsm6dsm_dec_fifo_xl_t; 2565 int32_t lsm6dsm_fifo_xl_batch_set(stmdev_ctx_t *ctx, 2566 lsm6dsm_dec_fifo_xl_t val); 2567 int32_t lsm6dsm_fifo_xl_batch_get(stmdev_ctx_t *ctx, 2568 lsm6dsm_dec_fifo_xl_t *val); 2569 2570 typedef enum 2571 { 2572 LSM6DSM_FIFO_GY_DISABLE = 0, 2573 LSM6DSM_FIFO_GY_NO_DEC = 1, 2574 LSM6DSM_FIFO_GY_DEC_2 = 2, 2575 LSM6DSM_FIFO_GY_DEC_3 = 3, 2576 LSM6DSM_FIFO_GY_DEC_4 = 4, 2577 LSM6DSM_FIFO_GY_DEC_8 = 5, 2578 LSM6DSM_FIFO_GY_DEC_16 = 6, 2579 LSM6DSM_FIFO_GY_DEC_32 = 7, 2580 } lsm6dsm_dec_fifo_gyro_t; 2581 int32_t lsm6dsm_fifo_gy_batch_set(stmdev_ctx_t *ctx, 2582 lsm6dsm_dec_fifo_gyro_t val); 2583 int32_t lsm6dsm_fifo_gy_batch_get(stmdev_ctx_t *ctx, 2584 lsm6dsm_dec_fifo_gyro_t *val); 2585 2586 typedef enum 2587 { 2588 LSM6DSM_FIFO_DS3_DISABLE = 0, 2589 LSM6DSM_FIFO_DS3_NO_DEC = 1, 2590 LSM6DSM_FIFO_DS3_DEC_2 = 2, 2591 LSM6DSM_FIFO_DS3_DEC_3 = 3, 2592 LSM6DSM_FIFO_DS3_DEC_4 = 4, 2593 LSM6DSM_FIFO_DS3_DEC_8 = 5, 2594 LSM6DSM_FIFO_DS3_DEC_16 = 6, 2595 LSM6DSM_FIFO_DS3_DEC_32 = 7, 2596 } lsm6dsm_dec_ds3_fifo_t; 2597 int32_t lsm6dsm_fifo_dataset_3_batch_set(stmdev_ctx_t *ctx, 2598 lsm6dsm_dec_ds3_fifo_t val); 2599 int32_t lsm6dsm_fifo_dataset_3_batch_get(stmdev_ctx_t *ctx, 2600 lsm6dsm_dec_ds3_fifo_t *val); 2601 2602 typedef enum 2603 { 2604 LSM6DSM_FIFO_DS4_DISABLE = 0, 2605 LSM6DSM_FIFO_DS4_NO_DEC = 1, 2606 LSM6DSM_FIFO_DS4_DEC_2 = 2, 2607 LSM6DSM_FIFO_DS4_DEC_3 = 3, 2608 LSM6DSM_FIFO_DS4_DEC_4 = 4, 2609 LSM6DSM_FIFO_DS4_DEC_8 = 5, 2610 LSM6DSM_FIFO_DS4_DEC_16 = 6, 2611 LSM6DSM_FIFO_DS4_DEC_32 = 7, 2612 } lsm6dsm_dec_ds4_fifo_t; 2613 int32_t lsm6dsm_fifo_dataset_4_batch_set(stmdev_ctx_t *ctx, 2614 lsm6dsm_dec_ds4_fifo_t val); 2615 int32_t lsm6dsm_fifo_dataset_4_batch_get(stmdev_ctx_t *ctx, 2616 lsm6dsm_dec_ds4_fifo_t *val); 2617 2618 int32_t lsm6dsm_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx, 2619 uint8_t val); 2620 int32_t lsm6dsm_fifo_xl_gy_8bit_format_get(stmdev_ctx_t *ctx, 2621 uint8_t *val); 2622 2623 int32_t lsm6dsm_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val); 2624 int32_t lsm6dsm_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val); 2625 2626 typedef enum 2627 { 2628 LSM6DSM_BYPASS_MODE = 0, 2629 LSM6DSM_FIFO_MODE = 1, 2630 LSM6DSM_STREAM_TO_FIFO_MODE = 3, 2631 LSM6DSM_BYPASS_TO_STREAM_MODE = 4, 2632 LSM6DSM_STREAM_MODE = 6, 2633 } lsm6dsm_fifo_mode_t; 2634 int32_t lsm6dsm_fifo_mode_set(stmdev_ctx_t *ctx, 2635 lsm6dsm_fifo_mode_t val); 2636 int32_t lsm6dsm_fifo_mode_get(stmdev_ctx_t *ctx, 2637 lsm6dsm_fifo_mode_t *val); 2638 2639 typedef enum 2640 { 2641 LSM6DSM_FIFO_DISABLE = 0, 2642 LSM6DSM_FIFO_12Hz5 = 1, 2643 LSM6DSM_FIFO_26Hz = 2, 2644 LSM6DSM_FIFO_52Hz = 3, 2645 LSM6DSM_FIFO_104Hz = 4, 2646 LSM6DSM_FIFO_208Hz = 5, 2647 LSM6DSM_FIFO_416Hz = 6, 2648 LSM6DSM_FIFO_833Hz = 7, 2649 LSM6DSM_FIFO_1k66Hz = 8, 2650 LSM6DSM_FIFO_3k33Hz = 9, 2651 LSM6DSM_FIFO_6k66Hz = 10, 2652 } lsm6dsm_odr_fifo_t; 2653 int32_t lsm6dsm_fifo_data_rate_set(stmdev_ctx_t *ctx, 2654 lsm6dsm_odr_fifo_t val); 2655 int32_t lsm6dsm_fifo_data_rate_get(stmdev_ctx_t *ctx, 2656 lsm6dsm_odr_fifo_t *val); 2657 2658 typedef enum 2659 { 2660 LSM6DSM_DEN_ACT_LOW = 0, 2661 LSM6DSM_DEN_ACT_HIGH = 1, 2662 } lsm6dsm_den_lh_t; 2663 int32_t lsm6dsm_den_polarity_set(stmdev_ctx_t *ctx, 2664 lsm6dsm_den_lh_t val); 2665 int32_t lsm6dsm_den_polarity_get(stmdev_ctx_t *ctx, 2666 lsm6dsm_den_lh_t *val); 2667 2668 typedef enum 2669 { 2670 LSM6DSM_DEN_DISABLE = 0, 2671 LSM6DSM_LEVEL_FIFO = 6, 2672 LSM6DSM_LEVEL_LETCHED = 3, 2673 LSM6DSM_LEVEL_TRIGGER = 2, 2674 LSM6DSM_EDGE_TRIGGER = 4, 2675 } lsm6dsm_den_mode_t; 2676 int32_t lsm6dsm_den_mode_set(stmdev_ctx_t *ctx, 2677 lsm6dsm_den_mode_t val); 2678 int32_t lsm6dsm_den_mode_get(stmdev_ctx_t *ctx, 2679 lsm6dsm_den_mode_t *val); 2680 2681 typedef enum 2682 { 2683 LSM6DSM_STAMP_IN_GY_DATA = 0, 2684 LSM6DSM_STAMP_IN_XL_DATA = 1, 2685 LSM6DSM_STAMP_IN_GY_XL_DATA = 2, 2686 } lsm6dsm_den_xl_en_t; 2687 int32_t lsm6dsm_den_enable_set(stmdev_ctx_t *ctx, 2688 lsm6dsm_den_xl_en_t val); 2689 int32_t lsm6dsm_den_enable_get(stmdev_ctx_t *ctx, 2690 lsm6dsm_den_xl_en_t *val); 2691 2692 int32_t lsm6dsm_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val); 2693 int32_t lsm6dsm_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val); 2694 2695 int32_t lsm6dsm_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val); 2696 int32_t lsm6dsm_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val); 2697 2698 int32_t lsm6dsm_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val); 2699 int32_t lsm6dsm_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val); 2700 2701 int32_t lsm6dsm_pedo_step_reset_set(stmdev_ctx_t *ctx, uint8_t val); 2702 int32_t lsm6dsm_pedo_step_reset_get(stmdev_ctx_t *ctx, uint8_t *val); 2703 2704 int32_t lsm6dsm_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val); 2705 int32_t lsm6dsm_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val); 2706 2707 int32_t lsm6dsm_pedo_threshold_set(stmdev_ctx_t *ctx, uint8_t val); 2708 int32_t lsm6dsm_pedo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); 2709 2710 typedef enum 2711 { 2712 LSM6DSM_PEDO_AT_2g = 0, 2713 LSM6DSM_PEDO_AT_4g = 1, 2714 } lsm6dsm_pedo_fs_t; 2715 int32_t lsm6dsm_pedo_full_scale_set(stmdev_ctx_t *ctx, 2716 lsm6dsm_pedo_fs_t val); 2717 int32_t lsm6dsm_pedo_full_scale_get(stmdev_ctx_t *ctx, 2718 lsm6dsm_pedo_fs_t *val); 2719 2720 int32_t lsm6dsm_pedo_debounce_steps_set(stmdev_ctx_t *ctx, 2721 uint8_t val); 2722 int32_t lsm6dsm_pedo_debounce_steps_get(stmdev_ctx_t *ctx, 2723 uint8_t *val); 2724 2725 int32_t lsm6dsm_pedo_timeout_set(stmdev_ctx_t *ctx, uint8_t val); 2726 int32_t lsm6dsm_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val); 2727 2728 int32_t lsm6dsm_pedo_steps_period_set(stmdev_ctx_t *ctx, 2729 uint8_t *buff); 2730 int32_t lsm6dsm_pedo_steps_period_get(stmdev_ctx_t *ctx, 2731 uint8_t *buff); 2732 2733 int32_t lsm6dsm_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val); 2734 int32_t lsm6dsm_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val); 2735 2736 int32_t lsm6dsm_motion_threshold_set(stmdev_ctx_t *ctx, 2737 uint8_t *buff); 2738 int32_t lsm6dsm_motion_threshold_get(stmdev_ctx_t *ctx, 2739 uint8_t *buff); 2740 2741 int32_t lsm6dsm_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val); 2742 int32_t lsm6dsm_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val); 2743 2744 int32_t lsm6dsm_wrist_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val); 2745 int32_t lsm6dsm_wrist_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val); 2746 2747 int32_t lsm6dsm_tilt_latency_set(stmdev_ctx_t *ctx, uint8_t *buff); 2748 int32_t lsm6dsm_tilt_latency_get(stmdev_ctx_t *ctx, uint8_t *buff); 2749 2750 int32_t lsm6dsm_tilt_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff); 2751 int32_t lsm6dsm_tilt_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff); 2752 2753 int32_t lsm6dsm_tilt_src_set(stmdev_ctx_t *ctx, 2754 lsm6dsm_a_wrist_tilt_mask_t *val); 2755 int32_t lsm6dsm_tilt_src_get(stmdev_ctx_t *ctx, 2756 lsm6dsm_a_wrist_tilt_mask_t *val); 2757 2758 int32_t lsm6dsm_mag_soft_iron_set(stmdev_ctx_t *ctx, uint8_t val); 2759 int32_t lsm6dsm_mag_soft_iron_get(stmdev_ctx_t *ctx, uint8_t *val); 2760 2761 int32_t lsm6dsm_mag_hard_iron_set(stmdev_ctx_t *ctx, uint8_t val); 2762 int32_t lsm6dsm_mag_hard_iron_get(stmdev_ctx_t *ctx, uint8_t *val); 2763 2764 int32_t lsm6dsm_mag_soft_iron_mat_set(stmdev_ctx_t *ctx, 2765 uint8_t *buff); 2766 int32_t lsm6dsm_mag_soft_iron_mat_get(stmdev_ctx_t *ctx, 2767 uint8_t *buff); 2768 2769 int32_t lsm6dsm_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val); 2770 int32_t lsm6dsm_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val); 2771 2772 int32_t lsm6dsm_func_en_set(stmdev_ctx_t *ctx, uint8_t val); 2773 2774 int32_t lsm6dsm_sh_sync_sens_frame_set(stmdev_ctx_t *ctx, 2775 uint8_t val); 2776 int32_t lsm6dsm_sh_sync_sens_frame_get(stmdev_ctx_t *ctx, 2777 uint8_t *val); 2778 2779 typedef enum 2780 { 2781 LSM6DSM_RES_RATIO_2_11 = 0, 2782 LSM6DSM_RES_RATIO_2_12 = 1, 2783 LSM6DSM_RES_RATIO_2_13 = 2, 2784 LSM6DSM_RES_RATIO_2_14 = 3, 2785 } lsm6dsm_rr_t; 2786 int32_t lsm6dsm_sh_sync_sens_ratio_set(stmdev_ctx_t *ctx, 2787 lsm6dsm_rr_t val); 2788 int32_t lsm6dsm_sh_sync_sens_ratio_get(stmdev_ctx_t *ctx, 2789 lsm6dsm_rr_t *val); 2790 2791 int32_t lsm6dsm_sh_master_set(stmdev_ctx_t *ctx, uint8_t val); 2792 int32_t lsm6dsm_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val); 2793 2794 int32_t lsm6dsm_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val); 2795 int32_t lsm6dsm_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val); 2796 2797 typedef enum 2798 { 2799 LSM6DSM_EXT_PULL_UP = 0, 2800 LSM6DSM_INTERNAL_PULL_UP = 1, 2801 LSM6DSM_SH_PIN_MODE = 2, 2802 } lsm6dsm_pull_up_en_t; 2803 int32_t lsm6dsm_sh_pin_mode_set(stmdev_ctx_t *ctx, 2804 lsm6dsm_pull_up_en_t val); 2805 int32_t lsm6dsm_sh_pin_mode_get(stmdev_ctx_t *ctx, 2806 lsm6dsm_pull_up_en_t *val); 2807 2808 typedef enum 2809 { 2810 LSM6DSM_XL_GY_DRDY = 0, 2811 LSM6DSM_EXT_ON_INT2_PIN = 1, 2812 } lsm6dsm_start_config_t; 2813 int32_t lsm6dsm_sh_syncro_mode_set(stmdev_ctx_t *ctx, 2814 lsm6dsm_start_config_t val); 2815 int32_t lsm6dsm_sh_syncro_mode_get(stmdev_ctx_t *ctx, 2816 lsm6dsm_start_config_t *val); 2817 2818 int32_t lsm6dsm_sh_drdy_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); 2819 int32_t lsm6dsm_sh_drdy_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); 2820 2821 typedef struct 2822 { 2823 lsm6dsm_sensorhub1_reg_t sh_byte_1; 2824 lsm6dsm_sensorhub2_reg_t sh_byte_2; 2825 lsm6dsm_sensorhub3_reg_t sh_byte_3; 2826 lsm6dsm_sensorhub4_reg_t sh_byte_4; 2827 lsm6dsm_sensorhub5_reg_t sh_byte_5; 2828 lsm6dsm_sensorhub6_reg_t sh_byte_6; 2829 lsm6dsm_sensorhub7_reg_t sh_byte_7; 2830 lsm6dsm_sensorhub8_reg_t sh_byte_8; 2831 lsm6dsm_sensorhub9_reg_t sh_byte_9; 2832 lsm6dsm_sensorhub10_reg_t sh_byte_10; 2833 lsm6dsm_sensorhub11_reg_t sh_byte_11; 2834 lsm6dsm_sensorhub12_reg_t sh_byte_12; 2835 lsm6dsm_sensorhub13_reg_t sh_byte_13; 2836 lsm6dsm_sensorhub14_reg_t sh_byte_14; 2837 lsm6dsm_sensorhub15_reg_t sh_byte_15; 2838 lsm6dsm_sensorhub16_reg_t sh_byte_16; 2839 lsm6dsm_sensorhub17_reg_t sh_byte_17; 2840 lsm6dsm_sensorhub18_reg_t sh_byte_18; 2841 } lsm6dsm_emb_sh_read_t; 2842 int32_t lsm6dsm_sh_read_data_raw_get(stmdev_ctx_t *ctx, 2843 lsm6dsm_emb_sh_read_t *val); 2844 2845 int32_t lsm6dsm_sh_cmd_sens_sync_set(stmdev_ctx_t *ctx, uint8_t val); 2846 int32_t lsm6dsm_sh_cmd_sens_sync_get(stmdev_ctx_t *ctx, uint8_t *val); 2847 2848 int32_t lsm6dsm_sh_spi_sync_error_set(stmdev_ctx_t *ctx, uint8_t val); 2849 int32_t lsm6dsm_sh_spi_sync_error_get(stmdev_ctx_t *ctx, 2850 uint8_t *val); 2851 2852 typedef enum 2853 { 2854 LSM6DSM_NORMAL_MODE_READ = 0, 2855 LSM6DSM_SRC_MODE_READ = 1, 2856 } lsm6dsm_src_mode_t; 2857 int32_t lsm6dsm_sh_cfg_slave_0_rd_mode_set(stmdev_ctx_t *ctx, 2858 lsm6dsm_src_mode_t val); 2859 int32_t lsm6dsm_sh_cfg_slave_0_rd_mode_get(stmdev_ctx_t *ctx, 2860 lsm6dsm_src_mode_t *val); 2861 2862 typedef enum 2863 { 2864 LSM6DSM_SLV_0 = 0, 2865 LSM6DSM_SLV_0_1 = 1, 2866 LSM6DSM_SLV_0_1_2 = 2, 2867 LSM6DSM_SLV_0_1_2_3 = 3, 2868 } lsm6dsm_aux_sens_on_t; 2869 int32_t lsm6dsm_sh_num_of_dev_connected_set(stmdev_ctx_t *ctx, 2870 lsm6dsm_aux_sens_on_t val); 2871 int32_t lsm6dsm_sh_num_of_dev_connected_get(stmdev_ctx_t *ctx, 2872 lsm6dsm_aux_sens_on_t *val); 2873 2874 typedef struct 2875 { 2876 uint8_t slv0_add; 2877 uint8_t slv0_subadd; 2878 uint8_t slv0_data; 2879 } lsm6dsm_sh_cfg_write_t; 2880 int32_t lsm6dsm_sh_cfg_write(stmdev_ctx_t *ctx, 2881 lsm6dsm_sh_cfg_write_t *val); 2882 2883 typedef struct 2884 { 2885 uint8_t slv_add; 2886 uint8_t slv_subadd; 2887 uint8_t slv_len; 2888 } lsm6dsm_sh_cfg_read_t; 2889 int32_t lsm6dsm_sh_slv0_cfg_read(stmdev_ctx_t *ctx, 2890 lsm6dsm_sh_cfg_read_t *val); 2891 int32_t lsm6dsm_sh_slv1_cfg_read(stmdev_ctx_t *ctx, 2892 lsm6dsm_sh_cfg_read_t *val); 2893 int32_t lsm6dsm_sh_slv2_cfg_read(stmdev_ctx_t *ctx, 2894 lsm6dsm_sh_cfg_read_t *val); 2895 int32_t lsm6dsm_sh_slv3_cfg_read(stmdev_ctx_t *ctx, 2896 lsm6dsm_sh_cfg_read_t *val); 2897 2898 typedef enum 2899 { 2900 LSM6DSM_SL0_NO_DEC = 0, 2901 LSM6DSM_SL0_DEC_2 = 1, 2902 LSM6DSM_SL0_DEC_4 = 2, 2903 LSM6DSM_SL0_DEC_8 = 3, 2904 } lsm6dsm_slave0_rate_t; 2905 int32_t lsm6dsm_sh_slave_0_dec_set(stmdev_ctx_t *ctx, 2906 lsm6dsm_slave0_rate_t val); 2907 int32_t lsm6dsm_sh_slave_0_dec_get(stmdev_ctx_t *ctx, 2908 lsm6dsm_slave0_rate_t *val); 2909 2910 typedef enum 2911 { 2912 LSM6DSM_EACH_SH_CYCLE = 0, 2913 LSM6DSM_ONLY_FIRST_CYCLE = 1, 2914 } lsm6dsm_write_once_t; 2915 int32_t lsm6dsm_sh_write_mode_set(stmdev_ctx_t *ctx, 2916 lsm6dsm_write_once_t val); 2917 int32_t lsm6dsm_sh_write_mode_get(stmdev_ctx_t *ctx, 2918 lsm6dsm_write_once_t *val); 2919 2920 typedef enum 2921 { 2922 LSM6DSM_SL1_NO_DEC = 0, 2923 LSM6DSM_SL1_DEC_2 = 1, 2924 LSM6DSM_SL1_DEC_4 = 2, 2925 LSM6DSM_SL1_DEC_8 = 3, 2926 } lsm6dsm_slave1_rate_t; 2927 int32_t lsm6dsm_sh_slave_1_dec_set(stmdev_ctx_t *ctx, 2928 lsm6dsm_slave1_rate_t val); 2929 int32_t lsm6dsm_sh_slave_1_dec_get(stmdev_ctx_t *ctx, 2930 lsm6dsm_slave1_rate_t *val); 2931 2932 typedef enum 2933 { 2934 LSM6DSM_SL2_NO_DEC = 0, 2935 LSM6DSM_SL2_DEC_2 = 1, 2936 LSM6DSM_SL2_DEC_4 = 2, 2937 LSM6DSM_SL2_DEC_8 = 3, 2938 } lsm6dsm_slave2_rate_t; 2939 int32_t lsm6dsm_sh_slave_2_dec_set(stmdev_ctx_t *ctx, 2940 lsm6dsm_slave2_rate_t val); 2941 int32_t lsm6dsm_sh_slave_2_dec_get(stmdev_ctx_t *ctx, 2942 lsm6dsm_slave2_rate_t *val); 2943 2944 typedef enum 2945 { 2946 LSM6DSM_SL3_NO_DEC = 0, 2947 LSM6DSM_SL3_DEC_2 = 1, 2948 LSM6DSM_SL3_DEC_4 = 2, 2949 LSM6DSM_SL3_DEC_8 = 3, 2950 } lsm6dsm_slave3_rate_t; 2951 int32_t lsm6dsm_sh_slave_3_dec_set(stmdev_ctx_t *ctx, 2952 lsm6dsm_slave3_rate_t val); 2953 int32_t lsm6dsm_sh_slave_3_dec_get(stmdev_ctx_t *ctx, 2954 lsm6dsm_slave3_rate_t *val); 2955 2956 /** 2957 * @} 2958 * 2959 */ 2960 2961 #ifdef __cplusplus 2962 } 2963 #endif 2964 2965 #endif /* LSM6DSM_DRIVER_H */ 2966 2967 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 2968
