1 /** 2 ****************************************************************************** 3 * @file lsm6dso32x_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * lsm6dso32x_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef LSM6DSO32X_REGS_H 23 #define LSM6DSO32X_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup LSM6DSO32X 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup LSM6DSO32X_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ 172 #define LSM6DSO32X_I2C_ADD_L 0xD5U 173 #define LSM6DSO32X_I2C_ADD_H 0xD7U 174 175 /** Device Identification (Who am I) **/ 176 #define LSM6DSO32X_ID 0x6CU 177 178 /** 179 * @} 180 * 181 */ 182 183 #define LSM6DSO32X_FUNC_CFG_ACCESS 0x01U 184 typedef struct 185 { 186 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 187 uint8_t not_used_01 : 6; 188 uint8_t reg_access : 189 2; /* shub_reg_access + func_cfg_access */ 190 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 191 uint8_t reg_access : 192 2; /* shub_reg_access + func_cfg_access */ 193 uint8_t not_used_01 : 6; 194 #endif /* DRV_BYTE_ORDER */ 195 } lsm6dso32x_func_cfg_access_t; 196 197 #define LSM6DSO32X_PIN_CTRL 0x02U 198 typedef struct 199 { 200 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 201 uint8_t not_used_01 : 6; 202 uint8_t sdo_pu_en : 1; 203 uint8_t not_used_02 : 1; 204 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 205 uint8_t not_used_02 : 1; 206 uint8_t sdo_pu_en : 1; 207 uint8_t not_used_01 : 6; 208 #endif /* DRV_BYTE_ORDER */ 209 } lsm6dso32x_pin_ctrl_t; 210 211 #define LSM6DSO32X_FIFO_CTRL1 0x07U 212 typedef struct 213 { 214 uint8_t wtm : 8; 215 } lsm6dso32x_fifo_ctrl1_t; 216 217 #define LSM6DSO32X_FIFO_CTRL2 0x08U 218 typedef struct 219 { 220 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 221 uint8_t wtm : 1; 222 uint8_t uncoptr_rate : 2; 223 uint8_t not_used_01 : 1; 224 uint8_t odrchg_en : 1; 225 uint8_t not_used_02 : 1; 226 uint8_t fifo_compr_rt_en : 1; 227 uint8_t stop_on_wtm : 1; 228 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 229 uint8_t stop_on_wtm : 1; 230 uint8_t fifo_compr_rt_en : 1; 231 uint8_t not_used_02 : 1; 232 uint8_t odrchg_en : 1; 233 uint8_t not_used_01 : 1; 234 uint8_t uncoptr_rate : 2; 235 uint8_t wtm : 1; 236 #endif /* DRV_BYTE_ORDER */ 237 } lsm6dso32x_fifo_ctrl2_t; 238 239 #define LSM6DSO32X_FIFO_CTRL3 0x09U 240 typedef struct 241 { 242 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 243 uint8_t bdr_xl : 4; 244 uint8_t bdr_gy : 4; 245 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 246 uint8_t bdr_gy : 4; 247 uint8_t bdr_xl : 4; 248 #endif /* DRV_BYTE_ORDER */ 249 } lsm6dso32x_fifo_ctrl3_t; 250 251 #define LSM6DSO32X_FIFO_CTRL4 0x0AU 252 typedef struct 253 { 254 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 255 uint8_t fifo_mode : 3; 256 uint8_t not_used_01 : 1; 257 uint8_t odr_t_batch : 2; 258 uint8_t odr_ts_batch : 2; 259 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 260 uint8_t odr_ts_batch : 2; 261 uint8_t odr_t_batch : 2; 262 uint8_t not_used_01 : 1; 263 uint8_t fifo_mode : 3; 264 #endif /* DRV_BYTE_ORDER */ 265 } lsm6dso32x_fifo_ctrl4_t; 266 267 #define LSM6DSO32X_COUNTER_BDR_REG1 0x0BU 268 typedef struct 269 { 270 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 271 uint8_t cnt_bdr_th : 3; 272 uint8_t not_used_01 : 2; 273 uint8_t trig_counter_bdr : 1; 274 uint8_t rst_counter_bdr : 1; 275 uint8_t dataready_pulsed : 1; 276 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 277 uint8_t dataready_pulsed : 1; 278 uint8_t rst_counter_bdr : 1; 279 uint8_t trig_counter_bdr : 1; 280 uint8_t not_used_01 : 2; 281 uint8_t cnt_bdr_th : 3; 282 #endif /* DRV_BYTE_ORDER */ 283 } lsm6dso32x_counter_bdr_reg1_t; 284 285 #define LSM6DSO32X_COUNTER_BDR_REG2 0x0CU 286 typedef struct 287 { 288 uint8_t cnt_bdr_th : 8; 289 } lsm6dso32x_counter_bdr_reg2_t; 290 291 #define LSM6DSO32X_INT1_CTRL 0x0D 292 typedef struct 293 { 294 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 295 uint8_t int1_drdy_xl : 1; 296 uint8_t int1_drdy_g : 1; 297 uint8_t int1_boot : 1; 298 uint8_t int1_fifo_th : 1; 299 uint8_t int1_fifo_ovr : 1; 300 uint8_t int1_fifo_full : 1; 301 uint8_t int1_cnt_bdr : 1; 302 uint8_t den_drdy_flag : 1; 303 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 304 uint8_t den_drdy_flag : 1; 305 uint8_t int1_cnt_bdr : 1; 306 uint8_t int1_fifo_full : 1; 307 uint8_t int1_fifo_ovr : 1; 308 uint8_t int1_fifo_th : 1; 309 uint8_t int1_boot : 1; 310 uint8_t int1_drdy_g : 1; 311 uint8_t int1_drdy_xl : 1; 312 #endif /* DRV_BYTE_ORDER */ 313 } lsm6dso32x_int1_ctrl_t; 314 315 #define LSM6DSO32X_INT2_CTRL 0x0EU 316 typedef struct 317 { 318 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 319 uint8_t int2_drdy_xl : 1; 320 uint8_t int2_drdy_g : 1; 321 uint8_t int2_drdy_temp : 1; 322 uint8_t int2_fifo_th : 1; 323 uint8_t int2_fifo_ovr : 1; 324 uint8_t int2_fifo_full : 1; 325 uint8_t int2_cnt_bdr : 1; 326 uint8_t not_used_01 : 1; 327 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 328 uint8_t not_used_01 : 1; 329 uint8_t int2_cnt_bdr : 1; 330 uint8_t int2_fifo_full : 1; 331 uint8_t int2_fifo_ovr : 1; 332 uint8_t int2_fifo_th : 1; 333 uint8_t int2_drdy_temp : 1; 334 uint8_t int2_drdy_g : 1; 335 uint8_t int2_drdy_xl : 1; 336 #endif /* DRV_BYTE_ORDER */ 337 } lsm6dso32x_int2_ctrl_t; 338 339 #define LSM6DSO32X_WHO_AM_I 0x0FU 340 #define LSM6DSO32X_CTRL1_XL 0x10U 341 typedef struct 342 { 343 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 344 uint8_t not_used_01 : 1; 345 uint8_t lpf2_xl_en : 1; 346 uint8_t fs_xl : 2; 347 uint8_t odr_xl : 4; 348 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 349 uint8_t odr_xl : 4; 350 uint8_t fs_xl : 2; 351 uint8_t lpf2_xl_en : 1; 352 uint8_t not_used_01 : 1; 353 #endif /* DRV_BYTE_ORDER */ 354 } lsm6dso32x_ctrl1_xl_t; 355 356 #define LSM6DSO32X_CTRL2_G 0x11U 357 typedef struct 358 { 359 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 360 uint8_t not_used_01 : 1; 361 uint8_t fs_g : 3; /* fs_125 + fs_g */ 362 uint8_t odr_g : 4; 363 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 364 uint8_t odr_g : 4; 365 uint8_t fs_g : 3; /* fs_125 + fs_g */ 366 uint8_t not_used_01 : 1; 367 #endif /* DRV_BYTE_ORDER */ 368 } lsm6dso32x_ctrl2_g_t; 369 370 #define LSM6DSO32X_CTRL3_C 0x12U 371 typedef struct 372 { 373 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 374 uint8_t sw_reset : 1; 375 uint8_t not_used_01 : 1; 376 uint8_t if_inc : 1; 377 uint8_t sim : 1; 378 uint8_t pp_od : 1; 379 uint8_t h_lactive : 1; 380 uint8_t bdu : 1; 381 uint8_t boot : 1; 382 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 383 uint8_t boot : 1; 384 uint8_t bdu : 1; 385 uint8_t h_lactive : 1; 386 uint8_t pp_od : 1; 387 uint8_t sim : 1; 388 uint8_t if_inc : 1; 389 uint8_t not_used_01 : 1; 390 uint8_t sw_reset : 1; 391 #endif /* DRV_BYTE_ORDER */ 392 } lsm6dso32x_ctrl3_c_t; 393 394 #define LSM6DSO32X_CTRL4_C 0x13U 395 typedef struct 396 { 397 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 398 uint8_t not_used_01 : 1; 399 uint8_t lpf1_sel_g : 1; 400 uint8_t i2c_disable : 1; 401 uint8_t drdy_mask : 1; 402 uint8_t not_used_02 : 1; 403 uint8_t int2_on_int1 : 1; 404 uint8_t sleep_g : 1; 405 uint8_t not_used_03 : 1; 406 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 407 uint8_t not_used_03 : 1; 408 uint8_t sleep_g : 1; 409 uint8_t int2_on_int1 : 1; 410 uint8_t not_used_02 : 1; 411 uint8_t drdy_mask : 1; 412 uint8_t i2c_disable : 1; 413 uint8_t lpf1_sel_g : 1; 414 uint8_t not_used_01 : 1; 415 #endif /* DRV_BYTE_ORDER */ 416 } lsm6dso32x_ctrl4_c_t; 417 418 #define LSM6DSO32X_CTRL5_C 0x14U 419 typedef struct 420 { 421 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 422 uint8_t st_xl : 2; 423 uint8_t st_g : 2; 424 uint8_t not_used_01 : 1; 425 uint8_t rounding : 2; 426 uint8_t xl_ulp_en : 1; 427 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 428 uint8_t xl_ulp_en : 1; 429 uint8_t rounding : 2; 430 uint8_t not_used_01 : 1; 431 uint8_t st_g : 2; 432 uint8_t st_xl : 2; 433 #endif /* DRV_BYTE_ORDER */ 434 } lsm6dso32x_ctrl5_c_t; 435 436 #define LSM6DSO32X_CTRL6_C 0x15U 437 typedef struct 438 { 439 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 440 uint8_t ftype : 3; 441 uint8_t usr_off_w : 1; 442 uint8_t xl_hm_mode : 1; 443 uint8_t den_mode : 444 3; /* trig_en + lvl1_en + lvl2_en */ 445 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 446 uint8_t den_mode : 447 3; /* trig_en + lvl1_en + lvl2_en */ 448 uint8_t xl_hm_mode : 1; 449 uint8_t usr_off_w : 1; 450 uint8_t ftype : 3; 451 #endif /* DRV_BYTE_ORDER */ 452 } lsm6dso32x_ctrl6_c_t; 453 454 #define LSM6DSO32X_CTRL7_G 0x16U 455 typedef struct 456 { 457 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 458 uint8_t not_used_01 : 1; 459 uint8_t usr_off_on_out : 1; 460 uint8_t not_used_02 : 2; 461 uint8_t hpm_g : 2; 462 uint8_t hp_en_g : 1; 463 uint8_t g_hm_mode : 1; 464 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 465 uint8_t g_hm_mode : 1; 466 uint8_t hp_en_g : 1; 467 uint8_t hpm_g : 2; 468 uint8_t not_used_02 : 2; 469 uint8_t usr_off_on_out : 1; 470 uint8_t not_used_01 : 1; 471 #endif /* DRV_BYTE_ORDER */ 472 } lsm6dso32x_ctrl7_g_t; 473 474 #define LSM6DSO32X_CTRL8_XL 0x17U 475 typedef struct 476 { 477 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 478 uint8_t low_pass_on_6d : 1; 479 uint8_t not_used_01 : 1; 480 uint8_t hp_slope_xl_en : 1; 481 uint8_t fastsettl_mode_xl : 1; 482 uint8_t hp_ref_mode_xl : 1; 483 uint8_t hpcf_xl : 3; 484 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 485 uint8_t hpcf_xl : 3; 486 uint8_t hp_ref_mode_xl : 1; 487 uint8_t fastsettl_mode_xl : 1; 488 uint8_t hp_slope_xl_en : 1; 489 uint8_t not_used_01 : 1; 490 uint8_t low_pass_on_6d : 1; 491 #endif /* DRV_BYTE_ORDER */ 492 } lsm6dso32x_ctrl8_xl_t; 493 494 #define LSM6DSO32X_CTRL9_XL 0x18U 495 typedef struct 496 { 497 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 498 uint8_t not_used_01 : 1; 499 uint8_t i3c_disable : 1; 500 uint8_t den_lh : 1; 501 uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */ 502 uint8_t den_z : 1; 503 uint8_t den_y : 1; 504 uint8_t den_x : 1; 505 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 506 uint8_t den_x : 1; 507 uint8_t den_y : 1; 508 uint8_t den_z : 1; 509 uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */ 510 uint8_t den_lh : 1; 511 uint8_t i3c_disable : 1; 512 uint8_t not_used_01 : 1; 513 #endif /* DRV_BYTE_ORDER */ 514 } lsm6dso32x_ctrl9_xl_t; 515 516 #define LSM6DSO32X_CTRL10_C 0x19U 517 typedef struct 518 { 519 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 520 uint8_t not_used_01 : 5; 521 uint8_t timestamp_en : 1; 522 uint8_t not_used_02 : 2; 523 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 524 uint8_t not_used_02 : 2; 525 uint8_t timestamp_en : 1; 526 uint8_t not_used_01 : 5; 527 #endif /* DRV_BYTE_ORDER */ 528 } lsm6dso32x_ctrl10_c_t; 529 530 #define LSM6DSO32X_ALL_INT_SRC 0x1AU 531 typedef struct 532 { 533 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 534 uint8_t ff_ia : 1; 535 uint8_t wu_ia : 1; 536 uint8_t single_tap : 1; 537 uint8_t double_tap : 1; 538 uint8_t d6d_ia : 1; 539 uint8_t sleep_change_ia : 1; 540 uint8_t not_used_01 : 1; 541 uint8_t timestamp_endcount : 1; 542 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 543 uint8_t timestamp_endcount : 1; 544 uint8_t not_used_01 : 1; 545 uint8_t sleep_change_ia : 1; 546 uint8_t d6d_ia : 1; 547 uint8_t double_tap : 1; 548 uint8_t single_tap : 1; 549 uint8_t wu_ia : 1; 550 uint8_t ff_ia : 1; 551 #endif /* DRV_BYTE_ORDER */ 552 } lsm6dso32x_all_int_src_t; 553 554 #define LSM6DSO32X_WAKE_UP_SRC 0x1BU 555 typedef struct 556 { 557 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 558 uint8_t z_wu : 1; 559 uint8_t y_wu : 1; 560 uint8_t x_wu : 1; 561 uint8_t wu_ia : 1; 562 uint8_t sleep_state : 1; 563 uint8_t ff_ia : 1; 564 uint8_t sleep_change_ia : 2; 565 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 566 uint8_t sleep_change_ia : 2; 567 uint8_t ff_ia : 1; 568 uint8_t sleep_state : 1; 569 uint8_t wu_ia : 1; 570 uint8_t x_wu : 1; 571 uint8_t y_wu : 1; 572 uint8_t z_wu : 1; 573 #endif /* DRV_BYTE_ORDER */ 574 } lsm6dso32x_wake_up_src_t; 575 576 #define LSM6DSO32X_TAP_SRC 0x1CU 577 typedef struct 578 { 579 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 580 uint8_t z_tap : 1; 581 uint8_t y_tap : 1; 582 uint8_t x_tap : 1; 583 uint8_t tap_sign : 1; 584 uint8_t double_tap : 1; 585 uint8_t single_tap : 1; 586 uint8_t tap_ia : 1; 587 uint8_t not_used_02 : 1; 588 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 589 uint8_t not_used_02 : 1; 590 uint8_t tap_ia : 1; 591 uint8_t single_tap : 1; 592 uint8_t double_tap : 1; 593 uint8_t tap_sign : 1; 594 uint8_t x_tap : 1; 595 uint8_t y_tap : 1; 596 uint8_t z_tap : 1; 597 #endif /* DRV_BYTE_ORDER */ 598 } lsm6dso32x_tap_src_t; 599 600 #define LSM6DSO32X_D6D_SRC 0x1DU 601 typedef struct 602 { 603 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 604 uint8_t xl : 1; 605 uint8_t xh : 1; 606 uint8_t yl : 1; 607 uint8_t yh : 1; 608 uint8_t zl : 1; 609 uint8_t zh : 1; 610 uint8_t d6d_ia : 1; 611 uint8_t den_drdy : 1; 612 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 613 uint8_t den_drdy : 1; 614 uint8_t d6d_ia : 1; 615 uint8_t zh : 1; 616 uint8_t zl : 1; 617 uint8_t yh : 1; 618 uint8_t yl : 1; 619 uint8_t xh : 1; 620 uint8_t xl : 1; 621 #endif /* DRV_BYTE_ORDER */ 622 } lsm6dso32x_d6d_src_t; 623 624 #define LSM6DSO32X_STATUS_REG 0x1EU 625 typedef struct 626 { 627 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 628 uint8_t xlda : 1; 629 uint8_t gda : 1; 630 uint8_t tda : 1; 631 uint8_t not_used_01 : 5; 632 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 633 uint8_t not_used_01 : 5; 634 uint8_t tda : 1; 635 uint8_t gda : 1; 636 uint8_t xlda : 1; 637 #endif /* DRV_BYTE_ORDER */ 638 } lsm6dso32x_status_reg_t; 639 640 #define LSM6DSO32X_OUT_TEMP_L 0x20U 641 #define LSM6DSO32X_OUT_TEMP_H 0x21U 642 #define LSM6DSO32X_OUTX_L_G 0x22U 643 #define LSM6DSO32X_OUTX_H_G 0x23U 644 #define LSM6DSO32X_OUTY_L_G 0x24U 645 #define LSM6DSO32X_OUTY_H_G 0x25U 646 #define LSM6DSO32X_OUTZ_L_G 0x26U 647 #define LSM6DSO32X_OUTZ_H_G 0x27U 648 #define LSM6DSO32X_OUTX_L_A 0x28U 649 #define LSM6DSO32X_OUTX_H_A 0x29U 650 #define LSM6DSO32X_OUTY_L_A 0x2AU 651 #define LSM6DSO32X_OUTY_H_A 0x2BU 652 #define LSM6DSO32X_OUTZ_L_A 0x2CU 653 #define LSM6DSO32X_OUTZ_H_A 0x2DU 654 #define LSM6DSO32X_EMB_FUNC_STATUS_MAINPAGE 0x35U 655 typedef struct 656 { 657 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 658 uint8_t not_used_01 : 3; 659 uint8_t is_step_det : 1; 660 uint8_t is_tilt : 1; 661 uint8_t is_sigmot : 1; 662 uint8_t not_used_02 : 1; 663 uint8_t is_fsm_lc : 1; 664 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 665 uint8_t is_fsm_lc : 1; 666 uint8_t not_used_02 : 1; 667 uint8_t is_sigmot : 1; 668 uint8_t is_tilt : 1; 669 uint8_t is_step_det : 1; 670 uint8_t not_used_01 : 3; 671 #endif /* DRV_BYTE_ORDER */ 672 } lsm6dso32x_emb_func_status_mainpage_t; 673 674 #define LSM6DSO32X_FSM_STATUS_A_MAINPAGE 0x36U 675 typedef struct 676 { 677 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 678 uint8_t is_fsm1 : 1; 679 uint8_t is_fsm2 : 1; 680 uint8_t is_fsm3 : 1; 681 uint8_t is_fsm4 : 1; 682 uint8_t is_fsm5 : 1; 683 uint8_t is_fsm6 : 1; 684 uint8_t is_fsm7 : 1; 685 uint8_t is_fsm8 : 1; 686 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 687 uint8_t is_fsm8 : 1; 688 uint8_t is_fsm7 : 1; 689 uint8_t is_fsm6 : 1; 690 uint8_t is_fsm5 : 1; 691 uint8_t is_fsm4 : 1; 692 uint8_t is_fsm3 : 1; 693 uint8_t is_fsm2 : 1; 694 uint8_t is_fsm1 : 1; 695 #endif /* DRV_BYTE_ORDER */ 696 } lsm6dso32x_fsm_status_a_mainpage_t; 697 698 #define LSM6DSO32X_FSM_STATUS_B_MAINPAGE 0x37U 699 typedef struct 700 { 701 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 702 uint8_t is_fsm9 : 1; 703 uint8_t is_fsm10 : 1; 704 uint8_t is_fsm11 : 1; 705 uint8_t is_fsm12 : 1; 706 uint8_t is_fsm13 : 1; 707 uint8_t is_fsm14 : 1; 708 uint8_t is_fsm15 : 1; 709 uint8_t is_fsm16 : 1; 710 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 711 uint8_t is_fsm16 : 1; 712 uint8_t is_fsm15 : 1; 713 uint8_t is_fsm14 : 1; 714 uint8_t is_fsm13 : 1; 715 uint8_t is_fsm12 : 1; 716 uint8_t is_fsm11 : 1; 717 uint8_t is_fsm10 : 1; 718 uint8_t is_fsm9 : 1; 719 #endif /* DRV_BYTE_ORDER */ 720 } lsm6dso32x_fsm_status_b_mainpage_t; 721 722 #define LSM6DSO32X_MLC_STATUS_MAINPAGE 0x38U 723 typedef struct 724 { 725 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 726 uint8_t is_mlc1 : 1; 727 uint8_t is_mlc2 : 1; 728 uint8_t is_mlc3 : 1; 729 uint8_t is_mlc4 : 1; 730 uint8_t is_mlc5 : 1; 731 uint8_t is_mlc6 : 1; 732 uint8_t is_mlc7 : 1; 733 uint8_t is_mlc8 : 1; 734 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 735 uint8_t is_mlc8 : 1; 736 uint8_t is_mlc7 : 1; 737 uint8_t is_mlc6 : 1; 738 uint8_t is_mlc5 : 1; 739 uint8_t is_mlc4 : 1; 740 uint8_t is_mlc3 : 1; 741 uint8_t is_mlc2 : 1; 742 uint8_t is_mlc1 : 1; 743 #endif /* DRV_BYTE_ORDER */ 744 } lsm6dso32x_mlc_status_mainpage_t; 745 746 #define LSM6DSO32X_STATUS_MASTER_MAINPAGE 0x39U 747 typedef struct 748 { 749 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 750 uint8_t sens_hub_endop : 1; 751 uint8_t not_used_01 : 2; 752 uint8_t slave0_nack : 1; 753 uint8_t slave1_nack : 1; 754 uint8_t slave2_nack : 1; 755 uint8_t slave3_nack : 1; 756 uint8_t wr_once_done : 1; 757 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 758 uint8_t wr_once_done : 1; 759 uint8_t slave3_nack : 1; 760 uint8_t slave2_nack : 1; 761 uint8_t slave1_nack : 1; 762 uint8_t slave0_nack : 1; 763 uint8_t not_used_01 : 2; 764 uint8_t sens_hub_endop : 1; 765 #endif /* DRV_BYTE_ORDER */ 766 } lsm6dso32x_status_master_mainpage_t; 767 768 #define LSM6DSO32X_FIFO_STATUS1 0x3AU 769 typedef struct 770 { 771 uint8_t diff_fifo : 8; 772 } lsm6dso32x_fifo_status1_t; 773 774 #define LSM6DSO32X_FIFO_STATUS2 0x3B 775 typedef struct 776 { 777 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 778 uint8_t diff_fifo : 2; 779 uint8_t not_used_01 : 1; 780 uint8_t over_run_latched : 1; 781 uint8_t counter_bdr_ia : 1; 782 uint8_t fifo_full_ia : 1; 783 uint8_t fifo_ovr_ia : 1; 784 uint8_t fifo_wtm_ia : 1; 785 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 786 uint8_t fifo_wtm_ia : 1; 787 uint8_t fifo_ovr_ia : 1; 788 uint8_t fifo_full_ia : 1; 789 uint8_t counter_bdr_ia : 1; 790 uint8_t over_run_latched : 1; 791 uint8_t not_used_01 : 1; 792 uint8_t diff_fifo : 2; 793 #endif /* DRV_BYTE_ORDER */ 794 } lsm6dso32x_fifo_status2_t; 795 796 #define LSM6DSO32X_TIMESTAMP0 0x40U 797 #define LSM6DSO32X_TIMESTAMP1 0x41U 798 #define LSM6DSO32X_TIMESTAMP2 0x42U 799 #define LSM6DSO32X_TIMESTAMP3 0x43U 800 801 #define LSM6DSO32X_TAP_CFG0 0x56U 802 typedef struct 803 { 804 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 805 uint8_t lir : 1; 806 uint8_t tap_z_en : 1; 807 uint8_t tap_y_en : 1; 808 uint8_t tap_x_en : 1; 809 uint8_t slope_fds : 1; 810 uint8_t sleep_status_on_int : 1; 811 uint8_t int_clr_on_read : 1; 812 uint8_t not_used_01 : 1; 813 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 814 uint8_t not_used_01 : 1; 815 uint8_t int_clr_on_read : 1; 816 uint8_t sleep_status_on_int : 1; 817 uint8_t slope_fds : 1; 818 uint8_t tap_x_en : 1; 819 uint8_t tap_y_en : 1; 820 uint8_t tap_z_en : 1; 821 uint8_t lir : 1; 822 #endif /* DRV_BYTE_ORDER */ 823 } lsm6dso32x_tap_cfg0_t; 824 825 #define LSM6DSO32X_TAP_CFG1 0x57U 826 typedef struct 827 { 828 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 829 uint8_t tap_ths_x : 5; 830 uint8_t tap_priority : 3; 831 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 832 uint8_t tap_priority : 3; 833 uint8_t tap_ths_x : 5; 834 #endif /* DRV_BYTE_ORDER */ 835 } lsm6dso32x_tap_cfg1_t; 836 837 #define LSM6DSO32X_TAP_CFG2 0x58U 838 typedef struct 839 { 840 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 841 uint8_t tap_ths_y : 5; 842 uint8_t inact_en : 2; 843 uint8_t interrupts_enable : 1; 844 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 845 uint8_t interrupts_enable : 1; 846 uint8_t inact_en : 2; 847 uint8_t tap_ths_y : 5; 848 #endif /* DRV_BYTE_ORDER */ 849 } lsm6dso32x_tap_cfg2_t; 850 851 #define LSM6DSO32X_TAP_THS_6D 0x59U 852 typedef struct 853 { 854 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 855 uint8_t tap_ths_z : 5; 856 uint8_t sixd_ths : 2; 857 uint8_t d4d_en : 1; 858 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 859 uint8_t d4d_en : 1; 860 uint8_t sixd_ths : 2; 861 uint8_t tap_ths_z : 5; 862 #endif /* DRV_BYTE_ORDER */ 863 } lsm6dso32x_tap_ths_6d_t; 864 865 #define LSM6DSO32X_INT_DUR2 0x5AU 866 typedef struct 867 { 868 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 869 uint8_t shock : 2; 870 uint8_t quiet : 2; 871 uint8_t dur : 4; 872 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 873 uint8_t dur : 4; 874 uint8_t quiet : 2; 875 uint8_t shock : 2; 876 #endif /* DRV_BYTE_ORDER */ 877 } lsm6dso32x_int_dur2_t; 878 879 #define LSM6DSO32X_WAKE_UP_THS 0x5BU 880 typedef struct 881 { 882 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 883 uint8_t wk_ths : 6; 884 uint8_t usr_off_on_wu : 1; 885 uint8_t single_double_tap : 1; 886 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 887 uint8_t single_double_tap : 1; 888 uint8_t usr_off_on_wu : 1; 889 uint8_t wk_ths : 6; 890 #endif /* DRV_BYTE_ORDER */ 891 } lsm6dso32x_wake_up_ths_t; 892 893 #define LSM6DSO32X_WAKE_UP_DUR 0x5CU 894 typedef struct 895 { 896 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 897 uint8_t sleep_dur : 4; 898 uint8_t wake_ths_w : 1; 899 uint8_t wake_dur : 2; 900 uint8_t ff_dur : 1; 901 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 902 uint8_t ff_dur : 1; 903 uint8_t wake_dur : 2; 904 uint8_t wake_ths_w : 1; 905 uint8_t sleep_dur : 4; 906 #endif /* DRV_BYTE_ORDER */ 907 } lsm6dso32x_wake_up_dur_t; 908 909 #define LSM6DSO32X_FREE_FALL 0x5DU 910 typedef struct 911 { 912 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 913 uint8_t ff_ths : 3; 914 uint8_t ff_dur : 5; 915 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 916 uint8_t ff_dur : 5; 917 uint8_t ff_ths : 3; 918 #endif /* DRV_BYTE_ORDER */ 919 } lsm6dso32x_free_fall_t; 920 921 #define LSM6DSO32X_MD1_CFG 0x5EU 922 typedef struct 923 { 924 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 925 uint8_t int1_shub : 1; 926 uint8_t int1_emb_func : 1; 927 uint8_t int1_6d : 1; 928 uint8_t int1_double_tap : 1; 929 uint8_t int1_ff : 1; 930 uint8_t int1_wu : 1; 931 uint8_t int1_single_tap : 1; 932 uint8_t int1_sleep_change : 1; 933 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 934 uint8_t int1_sleep_change : 1; 935 uint8_t int1_single_tap : 1; 936 uint8_t int1_wu : 1; 937 uint8_t int1_ff : 1; 938 uint8_t int1_double_tap : 1; 939 uint8_t int1_6d : 1; 940 uint8_t int1_emb_func : 1; 941 uint8_t int1_shub : 1; 942 #endif /* DRV_BYTE_ORDER */ 943 } lsm6dso32x_md1_cfg_t; 944 945 #define LSM6DSO32X_MD2_CFG 0x5FU 946 typedef struct 947 { 948 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 949 uint8_t int2_timestamp : 1; 950 uint8_t int2_emb_func : 1; 951 uint8_t int2_6d : 1; 952 uint8_t int2_double_tap : 1; 953 uint8_t int2_ff : 1; 954 uint8_t int2_wu : 1; 955 uint8_t int2_single_tap : 1; 956 uint8_t int2_sleep_change : 1; 957 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 958 uint8_t int2_sleep_change : 1; 959 uint8_t int2_single_tap : 1; 960 uint8_t int2_wu : 1; 961 uint8_t int2_ff : 1; 962 uint8_t int2_double_tap : 1; 963 uint8_t int2_6d : 1; 964 uint8_t int2_emb_func : 1; 965 uint8_t int2_timestamp : 1; 966 #endif /* DRV_BYTE_ORDER */ 967 } lsm6dso32x_md2_cfg_t; 968 969 #define LSM6DSO32X_I3C_BUS_AVB 0x62U 970 typedef struct 971 { 972 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 973 uint8_t pd_dis_int1 : 1; 974 uint8_t not_used_01 : 2; 975 uint8_t i3c_bus_avb_sel : 2; 976 uint8_t not_used_02 : 3; 977 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 978 uint8_t not_used_02 : 3; 979 uint8_t i3c_bus_avb_sel : 2; 980 uint8_t not_used_01 : 2; 981 uint8_t pd_dis_int1 : 1; 982 #endif /* DRV_BYTE_ORDER */ 983 } lsm6dso32x_i3c_bus_avb_t; 984 985 #define LSM6DSO32X_INTERNAL_FREQ_FINE 0x63U 986 typedef struct 987 { 988 uint8_t freq_fine : 8; 989 } lsm6dso32x_internal_freq_fine_t; 990 991 #define LSM6DSO32X_X_OFS_USR 0x73U 992 #define LSM6DSO32X_Y_OFS_USR 0x74U 993 #define LSM6DSO32X_Z_OFS_USR 0x75U 994 #define LSM6DSO32X_FIFO_DATA_OUT_TAG 0x78U 995 typedef struct 996 { 997 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 998 uint8_t tag_parity : 1; 999 uint8_t tag_cnt : 2; 1000 uint8_t tag_sensor : 5; 1001 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1002 uint8_t tag_sensor : 5; 1003 uint8_t tag_cnt : 2; 1004 uint8_t tag_parity : 1; 1005 #endif /* DRV_BYTE_ORDER */ 1006 } lsm6dso32x_fifo_data_out_tag_t; 1007 1008 #define LSM6DSO32X_FIFO_DATA_OUT_X_L 0x79 1009 #define LSM6DSO32X_FIFO_DATA_OUT_X_H 0x7A 1010 #define LSM6DSO32X_FIFO_DATA_OUT_Y_L 0x7B 1011 #define LSM6DSO32X_FIFO_DATA_OUT_Y_H 0x7C 1012 #define LSM6DSO32X_FIFO_DATA_OUT_Z_L 0x7D 1013 #define LSM6DSO32X_FIFO_DATA_OUT_Z_H 0x7E 1014 1015 #define LSM6DSO32X_PAGE_SEL 0x02U 1016 typedef struct 1017 { 1018 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1019 uint8_t not_used_01 : 4; 1020 uint8_t page_sel : 4; 1021 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1022 uint8_t page_sel : 4; 1023 uint8_t not_used_01 : 4; 1024 #endif /* DRV_BYTE_ORDER */ 1025 } lsm6dso32x_page_sel_t; 1026 1027 #define LSM6DSO32X_EMB_FUNC_EN_A 0x04U 1028 typedef struct 1029 { 1030 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1031 uint8_t not_used_01 : 3; 1032 uint8_t pedo_en : 1; 1033 uint8_t tilt_en : 1; 1034 uint8_t sign_motion_en : 1; 1035 uint8_t not_used_02 : 2; 1036 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1037 uint8_t not_used_02 : 2; 1038 uint8_t sign_motion_en : 1; 1039 uint8_t tilt_en : 1; 1040 uint8_t pedo_en : 1; 1041 uint8_t not_used_01 : 3; 1042 #endif /* DRV_BYTE_ORDER */ 1043 } lsm6dso32x_emb_func_en_a_t; 1044 1045 #define LSM6DSO32X_EMB_FUNC_EN_B 0x05U 1046 typedef struct 1047 { 1048 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1049 uint8_t fsm_en : 1; 1050 uint8_t not_used_01 : 2; 1051 uint8_t fifo_compr_en : 1; 1052 uint8_t mlc_en : 1; 1053 uint8_t not_used_02 : 3; 1054 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1055 uint8_t not_used_02 : 3; 1056 uint8_t mlc_en : 1; 1057 uint8_t fifo_compr_en : 1; 1058 uint8_t not_used_01 : 2; 1059 uint8_t fsm_en : 1; 1060 #endif /* DRV_BYTE_ORDER */ 1061 } lsm6dso32x_emb_func_en_b_t; 1062 1063 #define LSM6DSO32X_PAGE_ADDRESS 0x08U 1064 typedef struct 1065 { 1066 uint8_t page_addr : 8; 1067 } lsm6dso32x_page_address_t; 1068 1069 #define LSM6DSO32X_PAGE_VALUE 0x09U 1070 typedef struct 1071 { 1072 uint8_t page_value : 8; 1073 } lsm6dso32x_page_value_t; 1074 1075 #define LSM6DSO32X_EMB_FUNC_INT1 0x0AU 1076 typedef struct 1077 { 1078 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1079 uint8_t not_used_01 : 3; 1080 uint8_t int1_step_detector : 1; 1081 uint8_t int1_tilt : 1; 1082 uint8_t int1_sig_mot : 1; 1083 uint8_t not_used_02 : 1; 1084 uint8_t int1_fsm_lc : 1; 1085 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1086 uint8_t int1_fsm_lc : 1; 1087 uint8_t not_used_02 : 1; 1088 uint8_t int1_sig_mot : 1; 1089 uint8_t int1_tilt : 1; 1090 uint8_t int1_step_detector : 1; 1091 uint8_t not_used_01 : 3; 1092 #endif /* DRV_BYTE_ORDER */ 1093 } lsm6dso32x_emb_func_int1_t; 1094 1095 #define LSM6DSO32X_FSM_INT1_A 0x0BU 1096 typedef struct 1097 { 1098 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1099 uint8_t int1_fsm1 : 1; 1100 uint8_t int1_fsm2 : 1; 1101 uint8_t int1_fsm3 : 1; 1102 uint8_t int1_fsm4 : 1; 1103 uint8_t int1_fsm5 : 1; 1104 uint8_t int1_fsm6 : 1; 1105 uint8_t int1_fsm7 : 1; 1106 uint8_t int1_fsm8 : 1; 1107 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1108 uint8_t int1_fsm8 : 1; 1109 uint8_t int1_fsm7 : 1; 1110 uint8_t int1_fsm6 : 1; 1111 uint8_t int1_fsm5 : 1; 1112 uint8_t int1_fsm4 : 1; 1113 uint8_t int1_fsm3 : 1; 1114 uint8_t int1_fsm2 : 1; 1115 uint8_t int1_fsm1 : 1; 1116 #endif /* DRV_BYTE_ORDER */ 1117 } lsm6dso32x_fsm_int1_a_t; 1118 1119 #define LSM6DSO32X_FSM_INT1_B 0x0CU 1120 typedef struct 1121 { 1122 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1123 uint8_t int1_fsm16 : 1; 1124 uint8_t int1_fsm15 : 1; 1125 uint8_t int1_fsm14 : 1; 1126 uint8_t int1_fsm13 : 1; 1127 uint8_t int1_fsm12 : 1; 1128 uint8_t int1_fsm11 : 1; 1129 uint8_t int1_fsm10 : 1; 1130 uint8_t int1_fsm9 : 1; 1131 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1132 #endif /* DRV_BYTE_ORDER */ 1133 } lsm6dso32x_fsm_int1_b_t; 1134 1135 #define LSM6DSO32X_MLC_INT1 0x0DU 1136 typedef struct 1137 { 1138 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1139 uint8_t int1_mlc1 : 1; 1140 uint8_t int1_mlc2 : 1; 1141 uint8_t int1_mlc3 : 1; 1142 uint8_t int1_mlc4 : 1; 1143 uint8_t int1_mlc5 : 1; 1144 uint8_t int1_mlc6 : 1; 1145 uint8_t int1_mlc7 : 1; 1146 uint8_t int1_mlc8 : 1; 1147 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1148 uint8_t int1_mlc8 : 1; 1149 uint8_t int1_mlc7 : 1; 1150 uint8_t int1_mlc6 : 1; 1151 uint8_t int1_mlc5 : 1; 1152 uint8_t int1_mlc4 : 1; 1153 uint8_t int1_mlc3 : 1; 1154 uint8_t int1_mlc2 : 1; 1155 uint8_t int1_mlc1 : 1; 1156 #endif /* DRV_BYTE_ORDER */ 1157 } lsm6dso32x_mlc_int1_t; 1158 1159 #define LSM6DSO32X_EMB_FUNC_INT2 0x0EU 1160 typedef struct 1161 { 1162 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1163 uint8_t not_used_01 : 3; 1164 uint8_t int2_step_detector : 1; 1165 uint8_t int2_tilt : 1; 1166 uint8_t int2_sig_mot : 1; 1167 uint8_t not_used_02 : 1; 1168 uint8_t int2_fsm_lc : 1; 1169 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1170 uint8_t int2_fsm_lc : 1; 1171 uint8_t not_used_02 : 1; 1172 uint8_t int2_sig_mot : 1; 1173 uint8_t int2_tilt : 1; 1174 uint8_t int2_step_detector : 1; 1175 uint8_t not_used_01 : 3; 1176 #endif /* DRV_BYTE_ORDER */ 1177 } lsm6dso32x_emb_func_int2_t; 1178 1179 #define LSM6DSO32X_FSM_INT2_A 0x0FU 1180 typedef struct 1181 { 1182 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1183 uint8_t int2_fsm1 : 1; 1184 uint8_t int2_fsm2 : 1; 1185 uint8_t int2_fsm3 : 1; 1186 uint8_t int2_fsm4 : 1; 1187 uint8_t int2_fsm5 : 1; 1188 uint8_t int2_fsm6 : 1; 1189 uint8_t int2_fsm7 : 1; 1190 uint8_t int2_fsm8 : 1; 1191 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1192 uint8_t int2_fsm8 : 1; 1193 uint8_t int2_fsm7 : 1; 1194 uint8_t int2_fsm6 : 1; 1195 uint8_t int2_fsm5 : 1; 1196 uint8_t int2_fsm4 : 1; 1197 uint8_t int2_fsm3 : 1; 1198 uint8_t int2_fsm2 : 1; 1199 uint8_t int2_fsm1 : 1; 1200 #endif /* DRV_BYTE_ORDER */ 1201 } lsm6dso32x_fsm_int2_a_t; 1202 1203 #define LSM6DSO32X_FSM_INT2_B 0x10U 1204 typedef struct 1205 { 1206 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1207 uint8_t int2_fsm9 : 1; 1208 uint8_t int2_fsm10 : 1; 1209 uint8_t int2_fsm11 : 1; 1210 uint8_t int2_fsm12 : 1; 1211 uint8_t int2_fsm13 : 1; 1212 uint8_t int2_fsm14 : 1; 1213 uint8_t int2_fsm15 : 1; 1214 uint8_t int2_fsm16 : 1; 1215 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1216 uint8_t int2_fsm16 : 1; 1217 uint8_t int2_fsm15 : 1; 1218 uint8_t int2_fsm14 : 1; 1219 uint8_t int2_fsm13 : 1; 1220 uint8_t int2_fsm12 : 1; 1221 uint8_t int2_fsm11 : 1; 1222 uint8_t int2_fsm10 : 1; 1223 uint8_t int2_fsm9 : 1; 1224 #endif /* DRV_BYTE_ORDER */ 1225 } lsm6dso32x_fsm_int2_b_t; 1226 1227 #define LSM6DSO32X_MLC_INT2 0x11U 1228 typedef struct 1229 { 1230 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1231 uint8_t int2_mlc1 : 1; 1232 uint8_t int2_mlc2 : 1; 1233 uint8_t int2_mlc3 : 1; 1234 uint8_t int2_mlc4 : 1; 1235 uint8_t int2_mlc5 : 1; 1236 uint8_t int2_mlc6 : 1; 1237 uint8_t int2_mlc7 : 1; 1238 uint8_t int2_mlc8 : 1; 1239 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1240 uint8_t int2_mlc8 : 1; 1241 uint8_t int2_mlc7 : 1; 1242 uint8_t int2_mlc6 : 1; 1243 uint8_t int2_mlc5 : 1; 1244 uint8_t int2_mlc4 : 1; 1245 uint8_t int2_mlc3 : 1; 1246 uint8_t int2_mlc2 : 1; 1247 uint8_t int2_mlc1 : 1; 1248 #endif /* DRV_BYTE_ORDER */ 1249 } lsm6dso32x_mlc_int2_t; 1250 1251 #define LSM6DSO32X_EMB_FUNC_STATUS 0x12U 1252 typedef struct 1253 { 1254 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1255 uint8_t not_used_01 : 3; 1256 uint8_t is_step_det : 1; 1257 uint8_t is_tilt : 1; 1258 uint8_t is_sigmot : 1; 1259 uint8_t not_used_02 : 1; 1260 uint8_t is_fsm_lc : 1; 1261 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1262 uint8_t is_fsm_lc : 1; 1263 uint8_t not_used_02 : 1; 1264 uint8_t is_sigmot : 1; 1265 uint8_t is_tilt : 1; 1266 uint8_t is_step_det : 1; 1267 uint8_t not_used_01 : 3; 1268 #endif /* DRV_BYTE_ORDER */ 1269 } lsm6dso32x_emb_func_status_t; 1270 1271 #define LSM6DSO32X_FSM_STATUS_A 0x13U 1272 typedef struct 1273 { 1274 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1275 uint8_t is_fsm1 : 1; 1276 uint8_t is_fsm2 : 1; 1277 uint8_t is_fsm3 : 1; 1278 uint8_t is_fsm4 : 1; 1279 uint8_t is_fsm5 : 1; 1280 uint8_t is_fsm6 : 1; 1281 uint8_t is_fsm7 : 1; 1282 uint8_t is_fsm8 : 1; 1283 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1284 uint8_t is_fsm8 : 1; 1285 uint8_t is_fsm7 : 1; 1286 uint8_t is_fsm6 : 1; 1287 uint8_t is_fsm5 : 1; 1288 uint8_t is_fsm4 : 1; 1289 uint8_t is_fsm3 : 1; 1290 uint8_t is_fsm2 : 1; 1291 uint8_t is_fsm1 : 1; 1292 #endif /* DRV_BYTE_ORDER */ 1293 } lsm6dso32x_fsm_status_a_t; 1294 1295 #define LSM6DSO32X_FSM_STATUS_B 0x14U 1296 typedef struct 1297 { 1298 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1299 uint8_t is_fsm9 : 1; 1300 uint8_t is_fsm10 : 1; 1301 uint8_t is_fsm11 : 1; 1302 uint8_t is_fsm12 : 1; 1303 uint8_t is_fsm13 : 1; 1304 uint8_t is_fsm14 : 1; 1305 uint8_t is_fsm15 : 1; 1306 uint8_t is_fsm16 : 1; 1307 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1308 uint8_t is_fsm16 : 1; 1309 uint8_t is_fsm15 : 1; 1310 uint8_t is_fsm14 : 1; 1311 uint8_t is_fsm13 : 1; 1312 uint8_t is_fsm12 : 1; 1313 uint8_t is_fsm11 : 1; 1314 uint8_t is_fsm10 : 1; 1315 uint8_t is_fsm9 : 1; 1316 #endif /* DRV_BYTE_ORDER */ 1317 } lsm6dso32x_fsm_status_b_t; 1318 1319 #define LSM6DSO32X_MLC_STATUS 0x15U 1320 typedef struct 1321 { 1322 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1323 uint8_t is_mlc1 : 1; 1324 uint8_t is_mlc2 : 1; 1325 uint8_t is_mlc3 : 1; 1326 uint8_t is_mlc4 : 1; 1327 uint8_t is_mlc5 : 1; 1328 uint8_t is_mlc6 : 1; 1329 uint8_t is_mlc7 : 1; 1330 uint8_t is_mlc8 : 1; 1331 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1332 uint8_t is_mlc8 : 1; 1333 uint8_t is_mlc7 : 1; 1334 uint8_t is_mlc6 : 1; 1335 uint8_t is_mlc5 : 1; 1336 uint8_t is_mlc4 : 1; 1337 uint8_t is_mlc3 : 1; 1338 uint8_t is_mlc2 : 1; 1339 uint8_t is_mlc1 : 1; 1340 #endif /* DRV_BYTE_ORDER */ 1341 } lsm6dso32x_mlc_status_t; 1342 1343 #define LSM6DSO32X_PAGE_RW 0x17U 1344 typedef struct 1345 { 1346 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1347 uint8_t not_used_01 : 5; 1348 uint8_t page_rw : 2; /* page_write + page_read */ 1349 uint8_t emb_func_lir : 1; 1350 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1351 uint8_t emb_func_lir : 1; 1352 uint8_t page_rw : 2; /* page_write + page_read */ 1353 uint8_t not_used_01 : 5; 1354 #endif /* DRV_BYTE_ORDER */ 1355 } lsm6dso32x_page_rw_t; 1356 1357 #define LSM6DSO32X_EMB_FUNC_FIFO_CFG 0x44U 1358 typedef struct 1359 { 1360 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1361 uint8_t not_used_00 : 6; 1362 uint8_t pedo_fifo_en : 1; 1363 uint8_t not_used_01 : 1; 1364 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1365 uint8_t not_used_01 : 1; 1366 uint8_t pedo_fifo_en : 1; 1367 uint8_t not_used_00 : 6; 1368 #endif /* DRV_BYTE_ORDER */ 1369 } lsm6dso32x_emb_func_fifo_cfg_t; 1370 1371 #define LSM6DSO32X_FSM_ENABLE_A 0x46U 1372 typedef struct 1373 { 1374 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1375 uint8_t fsm1_en : 1; 1376 uint8_t fsm2_en : 1; 1377 uint8_t fsm3_en : 1; 1378 uint8_t fsm4_en : 1; 1379 uint8_t fsm5_en : 1; 1380 uint8_t fsm6_en : 1; 1381 uint8_t fsm7_en : 1; 1382 uint8_t fsm8_en : 1; 1383 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1384 uint8_t fsm8_en : 1; 1385 uint8_t fsm7_en : 1; 1386 uint8_t fsm6_en : 1; 1387 uint8_t fsm5_en : 1; 1388 uint8_t fsm4_en : 1; 1389 uint8_t fsm3_en : 1; 1390 uint8_t fsm2_en : 1; 1391 uint8_t fsm1_en : 1; 1392 #endif /* DRV_BYTE_ORDER */ 1393 } lsm6dso32x_fsm_enable_a_t; 1394 1395 #define LSM6DSO32X_FSM_ENABLE_B 0x47U 1396 typedef struct 1397 { 1398 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1399 uint8_t fsm9_en : 1; 1400 uint8_t fsm10_en : 1; 1401 uint8_t fsm11_en : 1; 1402 uint8_t fsm12_en : 1; 1403 uint8_t fsm13_en : 1; 1404 uint8_t fsm14_en : 1; 1405 uint8_t fsm15_en : 1; 1406 uint8_t fsm16_en : 1; 1407 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1408 uint8_t fsm16_en : 1; 1409 uint8_t fsm15_en : 1; 1410 uint8_t fsm14_en : 1; 1411 uint8_t fsm13_en : 1; 1412 uint8_t fsm12_en : 1; 1413 uint8_t fsm11_en : 1; 1414 uint8_t fsm10_en : 1; 1415 uint8_t fsm9_en : 1; 1416 #endif /* DRV_BYTE_ORDER */ 1417 } lsm6dso32x_fsm_enable_b_t; 1418 1419 #define LSM6DSO32X_FSM_LONG_COUNTER_L 0x48U 1420 #define LSM6DSO32X_FSM_LONG_COUNTER_H 0x49U 1421 #define LSM6DSO32X_FSM_LONG_COUNTER_CLEAR 0x4AU 1422 typedef struct 1423 { 1424 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1425 uint8_t fsm_lc_clr : 1426 2; /* fsm_lc_cleared + fsm_lc_clear */ 1427 uint8_t not_used_01 : 6; 1428 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1429 uint8_t not_used_01 : 6; 1430 uint8_t fsm_lc_clr : 1431 2; /* fsm_lc_cleared + fsm_lc_clear */ 1432 #endif /* DRV_BYTE_ORDER */ 1433 } lsm6dso32x_fsm_long_counter_clear_t; 1434 1435 #define LSM6DSO32X_FSM_OUTS1 0x4CU 1436 typedef struct 1437 { 1438 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1439 uint8_t n_v : 1; 1440 uint8_t p_v : 1; 1441 uint8_t n_z : 1; 1442 uint8_t p_z : 1; 1443 uint8_t n_y : 1; 1444 uint8_t p_y : 1; 1445 uint8_t n_x : 1; 1446 uint8_t p_x : 1; 1447 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1448 uint8_t p_x : 1; 1449 uint8_t n_x : 1; 1450 uint8_t p_y : 1; 1451 uint8_t n_y : 1; 1452 uint8_t p_z : 1; 1453 uint8_t n_z : 1; 1454 uint8_t p_v : 1; 1455 uint8_t n_v : 1; 1456 #endif /* DRV_BYTE_ORDER */ 1457 } lsm6dso32x_fsm_outs1_t; 1458 1459 #define LSM6DSO32X_FSM_OUTS2 0x4DU 1460 typedef struct 1461 { 1462 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1463 uint8_t n_v : 1; 1464 uint8_t p_v : 1; 1465 uint8_t n_z : 1; 1466 uint8_t p_z : 1; 1467 uint8_t n_y : 1; 1468 uint8_t p_y : 1; 1469 uint8_t n_x : 1; 1470 uint8_t p_x : 1; 1471 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1472 uint8_t p_x : 1; 1473 uint8_t n_x : 1; 1474 uint8_t p_y : 1; 1475 uint8_t n_y : 1; 1476 uint8_t p_z : 1; 1477 uint8_t n_z : 1; 1478 uint8_t p_v : 1; 1479 uint8_t n_v : 1; 1480 #endif /* DRV_BYTE_ORDER */ 1481 } lsm6dso32x_fsm_outs2_t; 1482 1483 #define LSM6DSO32X_FSM_OUTS3 0x4EU 1484 typedef struct 1485 { 1486 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1487 uint8_t n_v : 1; 1488 uint8_t p_v : 1; 1489 uint8_t n_z : 1; 1490 uint8_t p_z : 1; 1491 uint8_t n_y : 1; 1492 uint8_t p_y : 1; 1493 uint8_t n_x : 1; 1494 uint8_t p_x : 1; 1495 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1496 uint8_t p_x : 1; 1497 uint8_t n_x : 1; 1498 uint8_t p_y : 1; 1499 uint8_t n_y : 1; 1500 uint8_t p_z : 1; 1501 uint8_t n_z : 1; 1502 uint8_t p_v : 1; 1503 uint8_t n_v : 1; 1504 #endif /* DRV_BYTE_ORDER */ 1505 } lsm6dso32x_fsm_outs3_t; 1506 1507 #define LSM6DSO32X_FSM_OUTS4 0x4FU 1508 typedef struct 1509 { 1510 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1511 uint8_t n_v : 1; 1512 uint8_t p_v : 1; 1513 uint8_t n_z : 1; 1514 uint8_t p_z : 1; 1515 uint8_t n_y : 1; 1516 uint8_t p_y : 1; 1517 uint8_t n_x : 1; 1518 uint8_t p_x : 1; 1519 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1520 uint8_t p_x : 1; 1521 uint8_t n_x : 1; 1522 uint8_t p_y : 1; 1523 uint8_t n_y : 1; 1524 uint8_t p_z : 1; 1525 uint8_t n_z : 1; 1526 uint8_t p_v : 1; 1527 uint8_t n_v : 1; 1528 #endif /* DRV_BYTE_ORDER */ 1529 } lsm6dso32x_fsm_outs4_t; 1530 1531 #define LSM6DSO32X_FSM_OUTS5 0x50U 1532 typedef struct 1533 { 1534 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1535 uint8_t n_v : 1; 1536 uint8_t p_v : 1; 1537 uint8_t n_z : 1; 1538 uint8_t p_z : 1; 1539 uint8_t n_y : 1; 1540 uint8_t p_y : 1; 1541 uint8_t n_x : 1; 1542 uint8_t p_x : 1; 1543 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1544 uint8_t p_x : 1; 1545 uint8_t n_x : 1; 1546 uint8_t p_y : 1; 1547 uint8_t n_y : 1; 1548 uint8_t p_z : 1; 1549 uint8_t n_z : 1; 1550 uint8_t p_v : 1; 1551 uint8_t n_v : 1; 1552 #endif /* DRV_BYTE_ORDER */ 1553 } lsm6dso32x_fsm_outs5_t; 1554 1555 #define LSM6DSO32X_FSM_OUTS6 0x51U 1556 typedef struct 1557 { 1558 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1559 uint8_t n_v : 1; 1560 uint8_t p_v : 1; 1561 uint8_t n_z : 1; 1562 uint8_t p_z : 1; 1563 uint8_t n_y : 1; 1564 uint8_t p_y : 1; 1565 uint8_t n_x : 1; 1566 uint8_t p_x : 1; 1567 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1568 uint8_t p_x : 1; 1569 uint8_t n_x : 1; 1570 uint8_t p_y : 1; 1571 uint8_t n_y : 1; 1572 uint8_t p_z : 1; 1573 uint8_t n_z : 1; 1574 uint8_t p_v : 1; 1575 uint8_t n_v : 1; 1576 #endif /* DRV_BYTE_ORDER */ 1577 } lsm6dso32x_fsm_outs6_t; 1578 1579 #define LSM6DSO32X_FSM_OUTS7 0x52U 1580 typedef struct 1581 { 1582 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1583 uint8_t n_v : 1; 1584 uint8_t p_v : 1; 1585 uint8_t n_z : 1; 1586 uint8_t p_z : 1; 1587 uint8_t n_y : 1; 1588 uint8_t p_y : 1; 1589 uint8_t n_x : 1; 1590 uint8_t p_x : 1; 1591 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1592 uint8_t p_x : 1; 1593 uint8_t n_x : 1; 1594 uint8_t p_y : 1; 1595 uint8_t n_y : 1; 1596 uint8_t p_z : 1; 1597 uint8_t n_z : 1; 1598 uint8_t p_v : 1; 1599 uint8_t n_v : 1; 1600 #endif /* DRV_BYTE_ORDER */ 1601 } lsm6dso32x_fsm_outs7_t; 1602 1603 #define LSM6DSO32X_FSM_OUTS8 0x53U 1604 typedef struct 1605 { 1606 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1607 uint8_t n_v : 1; 1608 uint8_t p_v : 1; 1609 uint8_t n_z : 1; 1610 uint8_t p_z : 1; 1611 uint8_t n_y : 1; 1612 uint8_t p_y : 1; 1613 uint8_t n_x : 1; 1614 uint8_t p_x : 1; 1615 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1616 uint8_t p_x : 1; 1617 uint8_t n_x : 1; 1618 uint8_t p_y : 1; 1619 uint8_t n_y : 1; 1620 uint8_t p_z : 1; 1621 uint8_t n_z : 1; 1622 uint8_t p_v : 1; 1623 uint8_t n_v : 1; 1624 #endif /* DRV_BYTE_ORDER */ 1625 } lsm6dso32x_fsm_outs8_t; 1626 1627 #define LSM6DSO32X_FSM_OUTS9 0x54U 1628 typedef struct 1629 { 1630 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1631 uint8_t n_v : 1; 1632 uint8_t p_v : 1; 1633 uint8_t n_z : 1; 1634 uint8_t p_z : 1; 1635 uint8_t n_y : 1; 1636 uint8_t p_y : 1; 1637 uint8_t n_x : 1; 1638 uint8_t p_x : 1; 1639 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1640 uint8_t p_x : 1; 1641 uint8_t n_x : 1; 1642 uint8_t p_y : 1; 1643 uint8_t n_y : 1; 1644 uint8_t p_z : 1; 1645 uint8_t n_z : 1; 1646 uint8_t p_v : 1; 1647 uint8_t n_v : 1; 1648 #endif /* DRV_BYTE_ORDER */ 1649 } lsm6dso32x_fsm_outs9_t; 1650 1651 #define LSM6DSO32X_FSM_OUTS10 0x55U 1652 typedef struct 1653 { 1654 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1655 uint8_t n_v : 1; 1656 uint8_t p_v : 1; 1657 uint8_t n_z : 1; 1658 uint8_t p_z : 1; 1659 uint8_t n_y : 1; 1660 uint8_t p_y : 1; 1661 uint8_t n_x : 1; 1662 uint8_t p_x : 1; 1663 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1664 uint8_t p_x : 1; 1665 uint8_t n_x : 1; 1666 uint8_t p_y : 1; 1667 uint8_t n_y : 1; 1668 uint8_t p_z : 1; 1669 uint8_t n_z : 1; 1670 uint8_t p_v : 1; 1671 uint8_t n_v : 1; 1672 #endif /* DRV_BYTE_ORDER */ 1673 } lsm6dso32x_fsm_outs10_t; 1674 1675 #define LSM6DSO32X_FSM_OUTS11 0x56U 1676 typedef struct 1677 { 1678 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1679 uint8_t n_v : 1; 1680 uint8_t p_v : 1; 1681 uint8_t n_z : 1; 1682 uint8_t p_z : 1; 1683 uint8_t n_y : 1; 1684 uint8_t p_y : 1; 1685 uint8_t n_x : 1; 1686 uint8_t p_x : 1; 1687 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1688 uint8_t p_x : 1; 1689 uint8_t n_x : 1; 1690 uint8_t p_y : 1; 1691 uint8_t n_y : 1; 1692 uint8_t p_z : 1; 1693 uint8_t n_z : 1; 1694 uint8_t p_v : 1; 1695 uint8_t n_v : 1; 1696 #endif /* DRV_BYTE_ORDER */ 1697 } lsm6dso32x_fsm_outs11_t; 1698 1699 #define LSM6DSO32X_FSM_OUTS12 0x57U 1700 typedef struct 1701 { 1702 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1703 uint8_t n_v : 1; 1704 uint8_t p_v : 1; 1705 uint8_t n_z : 1; 1706 uint8_t p_z : 1; 1707 uint8_t n_y : 1; 1708 uint8_t p_y : 1; 1709 uint8_t n_x : 1; 1710 uint8_t p_x : 1; 1711 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1712 uint8_t p_x : 1; 1713 uint8_t n_x : 1; 1714 uint8_t p_y : 1; 1715 uint8_t n_y : 1; 1716 uint8_t p_z : 1; 1717 uint8_t n_z : 1; 1718 uint8_t p_v : 1; 1719 uint8_t n_v : 1; 1720 #endif /* DRV_BYTE_ORDER */ 1721 } lsm6dso32x_fsm_outs12_t; 1722 1723 #define LSM6DSO32X_FSM_OUTS13 0x58U 1724 typedef struct 1725 { 1726 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1727 uint8_t n_v : 1; 1728 uint8_t p_v : 1; 1729 uint8_t n_z : 1; 1730 uint8_t p_z : 1; 1731 uint8_t n_y : 1; 1732 uint8_t p_y : 1; 1733 uint8_t n_x : 1; 1734 uint8_t p_x : 1; 1735 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1736 uint8_t p_x : 1; 1737 uint8_t n_x : 1; 1738 uint8_t p_y : 1; 1739 uint8_t n_y : 1; 1740 uint8_t p_z : 1; 1741 uint8_t n_z : 1; 1742 uint8_t p_v : 1; 1743 uint8_t n_v : 1; 1744 #endif /* DRV_BYTE_ORDER */ 1745 } lsm6dso32x_fsm_outs13_t; 1746 1747 #define LSM6DSO32X_FSM_OUTS14 0x59U 1748 typedef struct 1749 { 1750 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1751 uint8_t n_v : 1; 1752 uint8_t p_v : 1; 1753 uint8_t n_z : 1; 1754 uint8_t p_z : 1; 1755 uint8_t n_y : 1; 1756 uint8_t p_y : 1; 1757 uint8_t n_x : 1; 1758 uint8_t p_x : 1; 1759 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1760 uint8_t p_x : 1; 1761 uint8_t n_x : 1; 1762 uint8_t p_y : 1; 1763 uint8_t n_y : 1; 1764 uint8_t p_z : 1; 1765 uint8_t n_z : 1; 1766 uint8_t p_v : 1; 1767 uint8_t n_v : 1; 1768 #endif /* DRV_BYTE_ORDER */ 1769 } lsm6dso32x_fsm_outs14_t; 1770 1771 #define LSM6DSO32X_FSM_OUTS15 0x5AU 1772 typedef struct 1773 { 1774 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1775 uint8_t n_v : 1; 1776 uint8_t p_v : 1; 1777 uint8_t n_z : 1; 1778 uint8_t p_z : 1; 1779 uint8_t n_y : 1; 1780 uint8_t p_y : 1; 1781 uint8_t n_x : 1; 1782 uint8_t p_x : 1; 1783 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1784 uint8_t p_x : 1; 1785 uint8_t n_x : 1; 1786 uint8_t p_y : 1; 1787 uint8_t n_y : 1; 1788 uint8_t p_z : 1; 1789 uint8_t n_z : 1; 1790 uint8_t p_v : 1; 1791 uint8_t n_v : 1; 1792 #endif /* DRV_BYTE_ORDER */ 1793 } lsm6dso32x_fsm_outs15_t; 1794 1795 #define LSM6DSO32X_FSM_OUTS16 0x5BU 1796 typedef struct 1797 { 1798 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1799 uint8_t n_v : 1; 1800 uint8_t p_v : 1; 1801 uint8_t n_z : 1; 1802 uint8_t p_z : 1; 1803 uint8_t n_y : 1; 1804 uint8_t p_y : 1; 1805 uint8_t n_x : 1; 1806 uint8_t p_x : 1; 1807 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1808 uint8_t p_x : 1; 1809 uint8_t n_x : 1; 1810 uint8_t p_y : 1; 1811 uint8_t n_y : 1; 1812 uint8_t p_z : 1; 1813 uint8_t n_z : 1; 1814 uint8_t p_v : 1; 1815 uint8_t n_v : 1; 1816 #endif /* DRV_BYTE_ORDER */ 1817 } lsm6dso32x_fsm_outs16_t; 1818 1819 #define LSM6DSO32X_EMB_FUNC_ODR_CFG_B 0x5FU 1820 typedef struct 1821 { 1822 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1823 uint8_t not_used_01 : 3; 1824 uint8_t fsm_odr : 2; 1825 uint8_t not_used_02 : 3; 1826 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1827 uint8_t not_used_02 : 3; 1828 uint8_t fsm_odr : 2; 1829 uint8_t not_used_01 : 3; 1830 #endif /* DRV_BYTE_ORDER */ 1831 } lsm6dso32x_emb_func_odr_cfg_b_t; 1832 1833 #define LSM6DSO32X_EMB_FUNC_ODR_CFG_C 0x60U 1834 typedef struct 1835 { 1836 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1837 uint8_t not_used_01 : 4; 1838 uint8_t mlc_odr : 2; 1839 uint8_t not_used_02 : 2; 1840 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1841 uint8_t not_used_02 : 2; 1842 uint8_t mlc_odr : 2; 1843 uint8_t not_used_01 : 4; 1844 #endif /* DRV_BYTE_ORDER */ 1845 } lsm6dso32x_emb_func_odr_cfg_c_t; 1846 1847 #define LSM6DSO32X_STEP_COUNTER_L 0x62U 1848 #define LSM6DSO32X_STEP_COUNTER_H 0x63U 1849 #define LSM6DSO32X_EMB_FUNC_SRC 0x64U 1850 typedef struct 1851 { 1852 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1853 uint8_t not_used_01 : 2; 1854 uint8_t stepcounter_bit_set : 1; 1855 uint8_t step_overflow : 1; 1856 uint8_t step_count_delta_ia : 1; 1857 uint8_t step_detected : 1; 1858 uint8_t not_used_02 : 1; 1859 uint8_t pedo_rst_step : 1; 1860 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1861 uint8_t pedo_rst_step : 1; 1862 uint8_t not_used_02 : 1; 1863 uint8_t step_detected : 1; 1864 uint8_t step_count_delta_ia : 1; 1865 uint8_t step_overflow : 1; 1866 uint8_t stepcounter_bit_set : 1; 1867 uint8_t not_used_01 : 2; 1868 #endif /* DRV_BYTE_ORDER */ 1869 } lsm6dso32x_emb_func_src_t; 1870 1871 #define LSM6DSO32X_EMB_FUNC_INIT_A 0x66U 1872 typedef struct 1873 { 1874 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1875 uint8_t not_used_01 : 3; 1876 uint8_t step_det_init : 1; 1877 uint8_t tilt_init : 1; 1878 uint8_t sig_mot_init : 1; 1879 uint8_t not_used_02 : 2; 1880 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1881 uint8_t not_used_02 : 2; 1882 uint8_t sig_mot_init : 1; 1883 uint8_t tilt_init : 1; 1884 uint8_t step_det_init : 1; 1885 uint8_t not_used_01 : 3; 1886 #endif /* DRV_BYTE_ORDER */ 1887 } lsm6dso32x_emb_func_init_a_t; 1888 1889 #define LSM6DSO32X_EMB_FUNC_INIT_B 0x67U 1890 typedef struct 1891 { 1892 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1893 uint8_t fsm_init : 1; 1894 uint8_t not_used_01 : 2; 1895 uint8_t fifo_compr_init : 1; 1896 uint8_t mlc_init : 1; 1897 uint8_t not_used_02 : 3; 1898 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1899 uint8_t not_used_02 : 3; 1900 uint8_t mlc_init : 1; 1901 uint8_t fifo_compr_init : 1; 1902 uint8_t not_used_01 : 2; 1903 uint8_t fsm_init : 1; 1904 #endif /* DRV_BYTE_ORDER */ 1905 } lsm6dso32x_emb_func_init_b_t; 1906 1907 #define LSM6DSO32X_MLC0_SRC 0x70U 1908 #define LSM6DSO32X_MLC1_SRC 0x71U 1909 #define LSM6DSO32X_MLC2_SRC 0x72U 1910 #define LSM6DSO32X_MLC3_SRC 0x73U 1911 #define LSM6DSO32X_MLC4_SRC 0x74U 1912 #define LSM6DSO32X_MLC5_SRC 0x75U 1913 #define LSM6DSO32X_MLC6_SRC 0x76U 1914 #define LSM6DSO32X_MLC7_SRC 0x77U 1915 #define LSM6DSO32X_MAG_SENSITIVITY_L 0xBAU 1916 #define LSM6DSO32X_MAG_SENSITIVITY_H 0xBBU 1917 #define LSM6DSO32X_MAG_OFFX_L 0xC0U 1918 #define LSM6DSO32X_MAG_OFFX_H 0xC1U 1919 #define LSM6DSO32X_MAG_OFFY_L 0xC2U 1920 #define LSM6DSO32X_MAG_OFFY_H 0xC3U 1921 #define LSM6DSO32X_MAG_OFFZ_L 0xC4U 1922 #define LSM6DSO32X_MAG_OFFZ_H 0xC5U 1923 #define LSM6DSO32X_MAG_SI_XX_L 0xC6U 1924 #define LSM6DSO32X_MAG_SI_XX_H 0xC7U 1925 #define LSM6DSO32X_MAG_SI_XY_L 0xC8U 1926 #define LSM6DSO32X_MAG_SI_XY_H 0xC9U 1927 #define LSM6DSO32X_MAG_SI_XZ_L 0xCAU 1928 #define LSM6DSO32X_MAG_SI_XZ_H 0xCBU 1929 #define LSM6DSO32X_MAG_SI_YY_L 0xCCU 1930 #define LSM6DSO32X_MAG_SI_YY_H 0xCDU 1931 #define LSM6DSO32X_MAG_SI_YZ_L 0xCEU 1932 #define LSM6DSO32X_MAG_SI_YZ_H 0xCFU 1933 #define LSM6DSO32X_MAG_SI_ZZ_L 0xD0U 1934 #define LSM6DSO32X_MAG_SI_ZZ_H 0xD1U 1935 #define LSM6DSO32X_MAG_CFG_A 0xD4U 1936 typedef struct 1937 { 1938 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1939 uint8_t mag_z_axis : 3; 1940 uint8_t not_used_01 : 1; 1941 uint8_t mag_y_axis : 3; 1942 uint8_t not_used_02 : 1; 1943 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1944 uint8_t not_used_02 : 1; 1945 uint8_t mag_y_axis : 3; 1946 uint8_t not_used_01 : 1; 1947 uint8_t mag_z_axis : 3; 1948 #endif /* DRV_BYTE_ORDER */ 1949 } lsm6dso32x_mag_cfg_a_t; 1950 1951 #define LSM6DSO32X_MAG_CFG_B 0xD5U 1952 typedef struct 1953 { 1954 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1955 uint8_t mag_x_axis : 3; 1956 uint8_t not_used_01 : 5; 1957 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1958 uint8_t not_used_01 : 5; 1959 uint8_t mag_x_axis : 3; 1960 #endif /* DRV_BYTE_ORDER */ 1961 } lsm6dso32x_mag_cfg_b_t; 1962 1963 #define LSM6DSO32X_FSM_LC_TIMEOUT_L 0x17AU 1964 #define LSM6DSO32X_FSM_LC_TIMEOUT_H 0x17BU 1965 #define LSM6DSO32X_FSM_PROGRAMS 0x17CU 1966 #define LSM6DSO32X_FSM_START_ADD_L 0x17EU 1967 #define LSM6DSO32X_FSM_START_ADD_H 0x17FU 1968 #define LSM6DSO32X_PEDO_CMD_REG 0x183U 1969 typedef struct 1970 { 1971 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1972 uint8_t ad_det_en : 1; 1973 uint8_t not_used_01 : 1; 1974 uint8_t fp_rejection_en : 1; 1975 uint8_t carry_count_en : 1; 1976 uint8_t not_used_02 : 4; 1977 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1978 uint8_t not_used_02 : 4; 1979 uint8_t carry_count_en : 1; 1980 uint8_t fp_rejection_en : 1; 1981 uint8_t not_used_01 : 1; 1982 uint8_t ad_det_en : 1; 1983 #endif /* DRV_BYTE_ORDER */ 1984 } lsm6dso32x_pedo_cmd_reg_t; 1985 1986 #define LSM6DSO32X_PEDO_DEB_STEPS_CONF 0x184U 1987 #define LSM6DSO32X_PEDO_SC_DELTAT_L 0x1D0U 1988 #define LSM6DSO32X_PEDO_SC_DELTAT_H 0x1D1U 1989 1990 #define LSM6DSO32X_MLC_MAG_SENSITIVITY_L 0x1E8U 1991 #define LSM6DSO32X_MLC_MAG_SENSITIVITY_H 0x1E9U 1992 1993 #define LSM6DSO32X_SENSOR_HUB_1 0x02U 1994 typedef struct 1995 { 1996 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1997 uint8_t bit0 : 1; 1998 uint8_t bit1 : 1; 1999 uint8_t bit2 : 1; 2000 uint8_t bit3 : 1; 2001 uint8_t bit4 : 1; 2002 uint8_t bit5 : 1; 2003 uint8_t bit6 : 1; 2004 uint8_t bit7 : 1; 2005 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2006 uint8_t bit7 : 1; 2007 uint8_t bit6 : 1; 2008 uint8_t bit5 : 1; 2009 uint8_t bit4 : 1; 2010 uint8_t bit3 : 1; 2011 uint8_t bit2 : 1; 2012 uint8_t bit1 : 1; 2013 uint8_t bit0 : 1; 2014 #endif /* DRV_BYTE_ORDER */ 2015 } lsm6dso32x_sensor_hub_1_t; 2016 2017 #define LSM6DSO32X_SENSOR_HUB_2 0x03U 2018 typedef struct 2019 { 2020 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2021 uint8_t bit0 : 1; 2022 uint8_t bit1 : 1; 2023 uint8_t bit2 : 1; 2024 uint8_t bit3 : 1; 2025 uint8_t bit4 : 1; 2026 uint8_t bit5 : 1; 2027 uint8_t bit6 : 1; 2028 uint8_t bit7 : 1; 2029 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2030 uint8_t bit7 : 1; 2031 uint8_t bit6 : 1; 2032 uint8_t bit5 : 1; 2033 uint8_t bit4 : 1; 2034 uint8_t bit3 : 1; 2035 uint8_t bit2 : 1; 2036 uint8_t bit1 : 1; 2037 uint8_t bit0 : 1; 2038 #endif /* DRV_BYTE_ORDER */ 2039 } lsm6dso32x_sensor_hub_2_t; 2040 2041 #define LSM6DSO32X_SENSOR_HUB_3 0x04U 2042 typedef struct 2043 { 2044 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2045 uint8_t bit0 : 1; 2046 uint8_t bit1 : 1; 2047 uint8_t bit2 : 1; 2048 uint8_t bit3 : 1; 2049 uint8_t bit4 : 1; 2050 uint8_t bit5 : 1; 2051 uint8_t bit6 : 1; 2052 uint8_t bit7 : 1; 2053 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2054 uint8_t bit7 : 1; 2055 uint8_t bit6 : 1; 2056 uint8_t bit5 : 1; 2057 uint8_t bit4 : 1; 2058 uint8_t bit3 : 1; 2059 uint8_t bit2 : 1; 2060 uint8_t bit1 : 1; 2061 uint8_t bit0 : 1; 2062 #endif /* DRV_BYTE_ORDER */ 2063 } lsm6dso32x_sensor_hub_3_t; 2064 2065 #define LSM6DSO32X_SENSOR_HUB_4 0x05U 2066 typedef struct 2067 { 2068 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2069 uint8_t bit0 : 1; 2070 uint8_t bit1 : 1; 2071 uint8_t bit2 : 1; 2072 uint8_t bit3 : 1; 2073 uint8_t bit4 : 1; 2074 uint8_t bit5 : 1; 2075 uint8_t bit6 : 1; 2076 uint8_t bit7 : 1; 2077 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2078 uint8_t bit7 : 1; 2079 uint8_t bit6 : 1; 2080 uint8_t bit5 : 1; 2081 uint8_t bit4 : 1; 2082 uint8_t bit3 : 1; 2083 uint8_t bit2 : 1; 2084 uint8_t bit1 : 1; 2085 uint8_t bit0 : 1; 2086 #endif /* DRV_BYTE_ORDER */ 2087 } lsm6dso32x_sensor_hub_4_t; 2088 2089 #define LSM6DSO32X_SENSOR_HUB_5 0x06U 2090 typedef struct 2091 { 2092 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2093 uint8_t bit0 : 1; 2094 uint8_t bit1 : 1; 2095 uint8_t bit2 : 1; 2096 uint8_t bit3 : 1; 2097 uint8_t bit4 : 1; 2098 uint8_t bit5 : 1; 2099 uint8_t bit6 : 1; 2100 uint8_t bit7 : 1; 2101 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2102 uint8_t bit7 : 1; 2103 uint8_t bit6 : 1; 2104 uint8_t bit5 : 1; 2105 uint8_t bit4 : 1; 2106 uint8_t bit3 : 1; 2107 uint8_t bit2 : 1; 2108 uint8_t bit1 : 1; 2109 uint8_t bit0 : 1; 2110 #endif /* DRV_BYTE_ORDER */ 2111 } lsm6dso32x_sensor_hub_5_t; 2112 2113 #define LSM6DSO32X_SENSOR_HUB_6 0x07U 2114 typedef struct 2115 { 2116 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2117 uint8_t bit0 : 1; 2118 uint8_t bit1 : 1; 2119 uint8_t bit2 : 1; 2120 uint8_t bit3 : 1; 2121 uint8_t bit4 : 1; 2122 uint8_t bit5 : 1; 2123 uint8_t bit6 : 1; 2124 uint8_t bit7 : 1; 2125 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2126 uint8_t bit7 : 1; 2127 uint8_t bit6 : 1; 2128 uint8_t bit5 : 1; 2129 uint8_t bit4 : 1; 2130 uint8_t bit3 : 1; 2131 uint8_t bit2 : 1; 2132 uint8_t bit1 : 1; 2133 uint8_t bit0 : 1; 2134 #endif /* DRV_BYTE_ORDER */ 2135 } lsm6dso32x_sensor_hub_6_t; 2136 2137 #define LSM6DSO32X_SENSOR_HUB_7 0x08U 2138 typedef struct 2139 { 2140 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2141 uint8_t bit0 : 1; 2142 uint8_t bit1 : 1; 2143 uint8_t bit2 : 1; 2144 uint8_t bit3 : 1; 2145 uint8_t bit4 : 1; 2146 uint8_t bit5 : 1; 2147 uint8_t bit6 : 1; 2148 uint8_t bit7 : 1; 2149 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2150 uint8_t bit7 : 1; 2151 uint8_t bit6 : 1; 2152 uint8_t bit5 : 1; 2153 uint8_t bit4 : 1; 2154 uint8_t bit3 : 1; 2155 uint8_t bit2 : 1; 2156 uint8_t bit1 : 1; 2157 uint8_t bit0 : 1; 2158 #endif /* DRV_BYTE_ORDER */ 2159 } lsm6dso32x_sensor_hub_7_t; 2160 2161 #define LSM6DSO32X_SENSOR_HUB_8 0x09U 2162 typedef struct 2163 { 2164 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2165 uint8_t bit0 : 1; 2166 uint8_t bit1 : 1; 2167 uint8_t bit2 : 1; 2168 uint8_t bit3 : 1; 2169 uint8_t bit4 : 1; 2170 uint8_t bit5 : 1; 2171 uint8_t bit6 : 1; 2172 uint8_t bit7 : 1; 2173 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2174 uint8_t bit7 : 1; 2175 uint8_t bit6 : 1; 2176 uint8_t bit5 : 1; 2177 uint8_t bit4 : 1; 2178 uint8_t bit3 : 1; 2179 uint8_t bit2 : 1; 2180 uint8_t bit1 : 1; 2181 uint8_t bit0 : 1; 2182 #endif /* DRV_BYTE_ORDER */ 2183 } lsm6dso32x_sensor_hub_8_t; 2184 2185 #define LSM6DSO32X_SENSOR_HUB_9 0x0AU 2186 typedef struct 2187 { 2188 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2189 uint8_t bit0 : 1; 2190 uint8_t bit1 : 1; 2191 uint8_t bit2 : 1; 2192 uint8_t bit3 : 1; 2193 uint8_t bit4 : 1; 2194 uint8_t bit5 : 1; 2195 uint8_t bit6 : 1; 2196 uint8_t bit7 : 1; 2197 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2198 uint8_t bit7 : 1; 2199 uint8_t bit6 : 1; 2200 uint8_t bit5 : 1; 2201 uint8_t bit4 : 1; 2202 uint8_t bit3 : 1; 2203 uint8_t bit2 : 1; 2204 uint8_t bit1 : 1; 2205 uint8_t bit0 : 1; 2206 #endif /* DRV_BYTE_ORDER */ 2207 } lsm6dso32x_sensor_hub_9_t; 2208 2209 #define LSM6DSO32X_SENSOR_HUB_10 0x0BU 2210 typedef struct 2211 { 2212 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2213 uint8_t bit0 : 1; 2214 uint8_t bit1 : 1; 2215 uint8_t bit2 : 1; 2216 uint8_t bit3 : 1; 2217 uint8_t bit4 : 1; 2218 uint8_t bit5 : 1; 2219 uint8_t bit6 : 1; 2220 uint8_t bit7 : 1; 2221 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2222 uint8_t bit7 : 1; 2223 uint8_t bit6 : 1; 2224 uint8_t bit5 : 1; 2225 uint8_t bit4 : 1; 2226 uint8_t bit3 : 1; 2227 uint8_t bit2 : 1; 2228 uint8_t bit1 : 1; 2229 uint8_t bit0 : 1; 2230 #endif /* DRV_BYTE_ORDER */ 2231 } lsm6dso32x_sensor_hub_10_t; 2232 2233 #define LSM6DSO32X_SENSOR_HUB_11 0x0CU 2234 typedef struct 2235 { 2236 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2237 uint8_t bit0 : 1; 2238 uint8_t bit1 : 1; 2239 uint8_t bit2 : 1; 2240 uint8_t bit3 : 1; 2241 uint8_t bit4 : 1; 2242 uint8_t bit5 : 1; 2243 uint8_t bit6 : 1; 2244 uint8_t bit7 : 1; 2245 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2246 uint8_t bit7 : 1; 2247 uint8_t bit6 : 1; 2248 uint8_t bit5 : 1; 2249 uint8_t bit4 : 1; 2250 uint8_t bit3 : 1; 2251 uint8_t bit2 : 1; 2252 uint8_t bit1 : 1; 2253 uint8_t bit0 : 1; 2254 #endif /* DRV_BYTE_ORDER */ 2255 } lsm6dso32x_sensor_hub_11_t; 2256 2257 #define LSM6DSO32X_SENSOR_HUB_12 0x0DU 2258 typedef struct 2259 { 2260 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2261 uint8_t bit0 : 1; 2262 uint8_t bit1 : 1; 2263 uint8_t bit2 : 1; 2264 uint8_t bit3 : 1; 2265 uint8_t bit4 : 1; 2266 uint8_t bit5 : 1; 2267 uint8_t bit6 : 1; 2268 uint8_t bit7 : 1; 2269 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2270 uint8_t bit7 : 1; 2271 uint8_t bit6 : 1; 2272 uint8_t bit5 : 1; 2273 uint8_t bit4 : 1; 2274 uint8_t bit3 : 1; 2275 uint8_t bit2 : 1; 2276 uint8_t bit1 : 1; 2277 uint8_t bit0 : 1; 2278 #endif /* DRV_BYTE_ORDER */ 2279 } lsm6dso32x_sensor_hub_12_t; 2280 2281 #define LSM6DSO32X_SENSOR_HUB_13 0x0EU 2282 typedef struct 2283 { 2284 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2285 uint8_t bit0 : 1; 2286 uint8_t bit1 : 1; 2287 uint8_t bit2 : 1; 2288 uint8_t bit3 : 1; 2289 uint8_t bit4 : 1; 2290 uint8_t bit5 : 1; 2291 uint8_t bit6 : 1; 2292 uint8_t bit7 : 1; 2293 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2294 uint8_t bit7 : 1; 2295 uint8_t bit6 : 1; 2296 uint8_t bit5 : 1; 2297 uint8_t bit4 : 1; 2298 uint8_t bit3 : 1; 2299 uint8_t bit2 : 1; 2300 uint8_t bit1 : 1; 2301 uint8_t bit0 : 1; 2302 #endif /* DRV_BYTE_ORDER */ 2303 } lsm6dso32x_sensor_hub_13_t; 2304 2305 #define LSM6DSO32X_SENSOR_HUB_14 0x0FU 2306 typedef struct 2307 { 2308 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2309 uint8_t bit0 : 1; 2310 uint8_t bit1 : 1; 2311 uint8_t bit2 : 1; 2312 uint8_t bit3 : 1; 2313 uint8_t bit4 : 1; 2314 uint8_t bit5 : 1; 2315 uint8_t bit6 : 1; 2316 uint8_t bit7 : 1; 2317 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2318 uint8_t bit7 : 1; 2319 uint8_t bit6 : 1; 2320 uint8_t bit5 : 1; 2321 uint8_t bit4 : 1; 2322 uint8_t bit3 : 1; 2323 uint8_t bit2 : 1; 2324 uint8_t bit1 : 1; 2325 uint8_t bit0 : 1; 2326 #endif /* DRV_BYTE_ORDER */ 2327 } lsm6dso32x_sensor_hub_14_t; 2328 2329 #define LSM6DSO32X_SENSOR_HUB_15 0x10U 2330 typedef struct 2331 { 2332 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2333 uint8_t bit0 : 1; 2334 uint8_t bit1 : 1; 2335 uint8_t bit2 : 1; 2336 uint8_t bit3 : 1; 2337 uint8_t bit4 : 1; 2338 uint8_t bit5 : 1; 2339 uint8_t bit6 : 1; 2340 uint8_t bit7 : 1; 2341 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2342 uint8_t bit7 : 1; 2343 uint8_t bit6 : 1; 2344 uint8_t bit5 : 1; 2345 uint8_t bit4 : 1; 2346 uint8_t bit3 : 1; 2347 uint8_t bit2 : 1; 2348 uint8_t bit1 : 1; 2349 uint8_t bit0 : 1; 2350 #endif /* DRV_BYTE_ORDER */ 2351 } lsm6dso32x_sensor_hub_15_t; 2352 2353 #define LSM6DSO32X_SENSOR_HUB_16 0x11U 2354 typedef struct 2355 { 2356 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2357 uint8_t bit0 : 1; 2358 uint8_t bit1 : 1; 2359 uint8_t bit2 : 1; 2360 uint8_t bit3 : 1; 2361 uint8_t bit4 : 1; 2362 uint8_t bit5 : 1; 2363 uint8_t bit6 : 1; 2364 uint8_t bit7 : 1; 2365 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2366 uint8_t bit7 : 1; 2367 uint8_t bit6 : 1; 2368 uint8_t bit5 : 1; 2369 uint8_t bit4 : 1; 2370 uint8_t bit3 : 1; 2371 uint8_t bit2 : 1; 2372 uint8_t bit1 : 1; 2373 uint8_t bit0 : 1; 2374 #endif /* DRV_BYTE_ORDER */ 2375 } lsm6dso32x_sensor_hub_16_t; 2376 2377 #define LSM6DSO32X_SENSOR_HUB_17 0x12U 2378 typedef struct 2379 { 2380 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2381 uint8_t bit0 : 1; 2382 uint8_t bit1 : 1; 2383 uint8_t bit2 : 1; 2384 uint8_t bit3 : 1; 2385 uint8_t bit4 : 1; 2386 uint8_t bit5 : 1; 2387 uint8_t bit6 : 1; 2388 uint8_t bit7 : 1; 2389 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2390 uint8_t bit7 : 1; 2391 uint8_t bit6 : 1; 2392 uint8_t bit5 : 1; 2393 uint8_t bit4 : 1; 2394 uint8_t bit3 : 1; 2395 uint8_t bit2 : 1; 2396 uint8_t bit1 : 1; 2397 uint8_t bit0 : 1; 2398 #endif /* DRV_BYTE_ORDER */ 2399 } lsm6dso32x_sensor_hub_17_t; 2400 2401 #define LSM6DSO32X_SENSOR_HUB_18 0x13U 2402 typedef struct 2403 { 2404 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2405 uint8_t bit0 : 1; 2406 uint8_t bit1 : 1; 2407 uint8_t bit2 : 1; 2408 uint8_t bit3 : 1; 2409 uint8_t bit4 : 1; 2410 uint8_t bit5 : 1; 2411 uint8_t bit6 : 1; 2412 uint8_t bit7 : 1; 2413 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2414 uint8_t bit7 : 1; 2415 uint8_t bit6 : 1; 2416 uint8_t bit5 : 1; 2417 uint8_t bit4 : 1; 2418 uint8_t bit3 : 1; 2419 uint8_t bit2 : 1; 2420 uint8_t bit1 : 1; 2421 uint8_t bit0 : 1; 2422 #endif /* DRV_BYTE_ORDER */ 2423 } lsm6dso32x_sensor_hub_18_t; 2424 2425 #define LSM6DSO32X_MASTER_CONFIG 0x14U 2426 typedef struct 2427 { 2428 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2429 uint8_t aux_sens_on : 2; 2430 uint8_t master_on : 1; 2431 uint8_t shub_pu_en : 1; 2432 uint8_t pass_through_mode : 1; 2433 uint8_t start_config : 1; 2434 uint8_t write_once : 1; 2435 uint8_t rst_master_regs : 1; 2436 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2437 uint8_t rst_master_regs : 1; 2438 uint8_t write_once : 1; 2439 uint8_t start_config : 1; 2440 uint8_t pass_through_mode : 1; 2441 uint8_t shub_pu_en : 1; 2442 uint8_t master_on : 1; 2443 uint8_t aux_sens_on : 2; 2444 #endif /* DRV_BYTE_ORDER */ 2445 } lsm6dso32x_master_config_t; 2446 2447 #define LSM6DSO32X_SLV0_ADD 0x15U 2448 typedef struct 2449 { 2450 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2451 uint8_t rw_0 : 1; 2452 uint8_t slave0 : 7; 2453 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2454 uint8_t slave0 : 7; 2455 uint8_t rw_0 : 1; 2456 #endif /* DRV_BYTE_ORDER */ 2457 } lsm6dso32x_slv0_add_t; 2458 2459 #define LSM6DSO32X_SLV0_SUBADD 0x16U 2460 typedef struct 2461 { 2462 uint8_t slave0_reg : 8; 2463 } lsm6dso32x_slv0_subadd_t; 2464 2465 #define LSM6DSO32X_SLV0_CONFIG 0x17U 2466 typedef struct 2467 { 2468 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2469 uint8_t slave0_numop : 3; 2470 uint8_t batch_ext_sens_0_en : 1; 2471 uint8_t not_used_01 : 2; 2472 uint8_t shub_odr : 2; 2473 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2474 uint8_t shub_odr : 2; 2475 uint8_t not_used_01 : 2; 2476 uint8_t batch_ext_sens_0_en : 1; 2477 uint8_t slave0_numop : 3; 2478 #endif /* DRV_BYTE_ORDER */ 2479 } lsm6dso32x_slv0_config_t; 2480 2481 #define LSM6DSO32X_SLV1_ADD 0x18U 2482 typedef struct 2483 { 2484 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2485 uint8_t r_1 : 1; 2486 uint8_t slave1_add : 7; 2487 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2488 uint8_t slave1_add : 7; 2489 uint8_t r_1 : 1; 2490 #endif /* DRV_BYTE_ORDER */ 2491 } lsm6dso32x_slv1_add_t; 2492 2493 #define LSM6DSO32X_SLV1_SUBADD 0x19U 2494 typedef struct 2495 { 2496 uint8_t slave1_reg : 8; 2497 } lsm6dso32x_slv1_subadd_t; 2498 2499 #define LSM6DSO32X_SLV1_CONFIG 0x1AU 2500 typedef struct 2501 { 2502 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2503 uint8_t slave1_numop : 3; 2504 uint8_t batch_ext_sens_1_en : 1; 2505 uint8_t not_used_01 : 4; 2506 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2507 uint8_t not_used_01 : 4; 2508 uint8_t batch_ext_sens_1_en : 1; 2509 uint8_t slave1_numop : 3; 2510 #endif /* DRV_BYTE_ORDER */ 2511 } lsm6dso32x_slv1_config_t; 2512 2513 #define LSM6DSO32X_SLV2_ADD 0x1BU 2514 typedef struct 2515 { 2516 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2517 uint8_t r_2 : 1; 2518 uint8_t slave2_add : 7; 2519 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2520 uint8_t slave2_add : 7; 2521 uint8_t r_2 : 1; 2522 #endif /* DRV_BYTE_ORDER */ 2523 } lsm6dso32x_slv2_add_t; 2524 2525 #define LSM6DSO32X_SLV2_SUBADD 0x1CU 2526 typedef struct 2527 { 2528 uint8_t slave2_reg : 8; 2529 } lsm6dso32x_slv2_subadd_t; 2530 2531 #define LSM6DSO32X_SLV2_CONFIG 0x1DU 2532 typedef struct 2533 { 2534 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2535 uint8_t slave2_numop : 3; 2536 uint8_t batch_ext_sens_2_en : 1; 2537 uint8_t not_used_01 : 4; 2538 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2539 uint8_t not_used_01 : 4; 2540 uint8_t batch_ext_sens_2_en : 1; 2541 uint8_t slave2_numop : 3; 2542 #endif /* DRV_BYTE_ORDER */ 2543 } lsm6dso32x_slv2_config_t; 2544 2545 #define LSM6DSO32X_SLV3_ADD 0x1EU 2546 typedef struct 2547 { 2548 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2549 uint8_t r_3 : 1; 2550 uint8_t slave3_add : 7; 2551 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2552 uint8_t slave3_add : 7; 2553 uint8_t r_3 : 1; 2554 #endif /* DRV_BYTE_ORDER */ 2555 } lsm6dso32x_slv3_add_t; 2556 2557 #define LSM6DSO32X_SLV3_SUBADD 0x1FU 2558 typedef struct 2559 { 2560 uint8_t slave3_reg : 8; 2561 } lsm6dso32x_slv3_subadd_t; 2562 2563 #define LSM6DSO32X_SLV3_CONFIG 0x20U 2564 typedef struct 2565 { 2566 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2567 uint8_t slave3_numop : 3; 2568 uint8_t batch_ext_sens_3_en : 1; 2569 uint8_t not_used_01 : 4; 2570 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2571 uint8_t not_used_01 : 4; 2572 uint8_t batch_ext_sens_3_en : 1; 2573 uint8_t slave3_numop : 3; 2574 #endif /* DRV_BYTE_ORDER */ 2575 } lsm6dso32x_slv3_config_t; 2576 2577 #define LSM6DSO32X_DATAWRITE_SLV0 0x21U 2578 typedef struct 2579 { 2580 uint8_t slave0_dataw : 8; 2581 } lsm6dso32x_datawrite_slv0_t; 2582 2583 #define LSM6DSO32X_STATUS_MASTER 0x22U 2584 typedef struct 2585 { 2586 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2587 uint8_t sens_hub_endop : 1; 2588 uint8_t not_used_01 : 2; 2589 uint8_t slave0_nack : 1; 2590 uint8_t slave1_nack : 1; 2591 uint8_t slave2_nack : 1; 2592 uint8_t slave3_nack : 1; 2593 uint8_t wr_once_done : 1; 2594 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2595 uint8_t wr_once_done : 1; 2596 uint8_t slave3_nack : 1; 2597 uint8_t slave2_nack : 1; 2598 uint8_t slave1_nack : 1; 2599 uint8_t slave0_nack : 1; 2600 uint8_t not_used_01 : 2; 2601 uint8_t sens_hub_endop : 1; 2602 #endif /* DRV_BYTE_ORDER */ 2603 } lsm6dso32x_status_master_t; 2604 2605 #define LSM6DSO32X_START_FSM_ADD 0x0400U 2606 2607 /** 2608 * @defgroup LSM6DSO32X_Register_Union 2609 * @brief This union group all the registers that has a bitfield 2610 * description. 2611 * This union is useful but not need by the driver. 2612 * 2613 * REMOVING this union you are compliant with: 2614 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 2615 * 2616 * @{ 2617 * 2618 */ 2619 typedef union 2620 { 2621 lsm6dso32x_func_cfg_access_t func_cfg_access; 2622 lsm6dso32x_pin_ctrl_t pin_ctrl; 2623 lsm6dso32x_fifo_ctrl1_t fifo_ctrl1; 2624 lsm6dso32x_fifo_ctrl2_t fifo_ctrl2; 2625 lsm6dso32x_fifo_ctrl3_t fifo_ctrl3; 2626 lsm6dso32x_fifo_ctrl4_t fifo_ctrl4; 2627 lsm6dso32x_counter_bdr_reg1_t counter_bdr_reg1; 2628 lsm6dso32x_counter_bdr_reg2_t counter_bdr_reg2; 2629 lsm6dso32x_int1_ctrl_t int1_ctrl; 2630 lsm6dso32x_int2_ctrl_t int2_ctrl; 2631 lsm6dso32x_ctrl1_xl_t ctrl1_xl; 2632 lsm6dso32x_ctrl2_g_t ctrl2_g; 2633 lsm6dso32x_ctrl3_c_t ctrl3_c; 2634 lsm6dso32x_ctrl4_c_t ctrl4_c; 2635 lsm6dso32x_ctrl5_c_t ctrl5_c; 2636 lsm6dso32x_ctrl6_c_t ctrl6_c; 2637 lsm6dso32x_ctrl7_g_t ctrl7_g; 2638 lsm6dso32x_ctrl8_xl_t ctrl8_xl; 2639 lsm6dso32x_ctrl9_xl_t ctrl9_xl; 2640 lsm6dso32x_ctrl10_c_t ctrl10_c; 2641 lsm6dso32x_all_int_src_t all_int_src; 2642 lsm6dso32x_wake_up_src_t wake_up_src; 2643 lsm6dso32x_tap_src_t tap_src; 2644 lsm6dso32x_d6d_src_t d6d_src; 2645 lsm6dso32x_status_reg_t status_reg; 2646 lsm6dso32x_fifo_status1_t fifo_status1; 2647 lsm6dso32x_fifo_status2_t fifo_status2; 2648 lsm6dso32x_tap_cfg0_t tap_cfg0; 2649 lsm6dso32x_tap_cfg1_t tap_cfg1; 2650 lsm6dso32x_tap_cfg2_t tap_cfg2; 2651 lsm6dso32x_tap_ths_6d_t tap_ths_6d; 2652 lsm6dso32x_int_dur2_t int_dur2; 2653 lsm6dso32x_wake_up_ths_t wake_up_ths; 2654 lsm6dso32x_wake_up_dur_t wake_up_dur; 2655 lsm6dso32x_free_fall_t free_fall; 2656 lsm6dso32x_md1_cfg_t md1_cfg; 2657 lsm6dso32x_md2_cfg_t md2_cfg; 2658 lsm6dso32x_i3c_bus_avb_t i3c_bus_avb; 2659 lsm6dso32x_internal_freq_fine_t internal_freq_fine; 2660 lsm6dso32x_fifo_data_out_tag_t fifo_data_out_tag; 2661 lsm6dso32x_page_sel_t page_sel; 2662 lsm6dso32x_emb_func_en_a_t emb_func_en_a; 2663 lsm6dso32x_emb_func_en_b_t emb_func_en_b; 2664 lsm6dso32x_page_address_t page_address; 2665 lsm6dso32x_page_value_t page_value; 2666 lsm6dso32x_emb_func_int1_t emb_func_int1; 2667 lsm6dso32x_fsm_int1_a_t fsm_int1_a; 2668 lsm6dso32x_fsm_int1_b_t fsm_int1_b; 2669 lsm6dso32x_emb_func_int2_t emb_func_int2; 2670 lsm6dso32x_fsm_int2_a_t fsm_int2_a; 2671 lsm6dso32x_fsm_int2_b_t fsm_int2_b; 2672 lsm6dso32x_emb_func_status_t emb_func_status; 2673 lsm6dso32x_fsm_status_a_t fsm_status_a; 2674 lsm6dso32x_fsm_status_b_t fsm_status_b; 2675 lsm6dso32x_page_rw_t page_rw; 2676 lsm6dso32x_emb_func_fifo_cfg_t emb_func_fifo_cfg; 2677 lsm6dso32x_fsm_enable_a_t fsm_enable_a; 2678 lsm6dso32x_fsm_enable_b_t fsm_enable_b; 2679 lsm6dso32x_fsm_long_counter_clear_t fsm_long_counter_clear; 2680 lsm6dso32x_fsm_outs1_t fsm_outs1; 2681 lsm6dso32x_fsm_outs2_t fsm_outs2; 2682 lsm6dso32x_fsm_outs3_t fsm_outs3; 2683 lsm6dso32x_fsm_outs4_t fsm_outs4; 2684 lsm6dso32x_fsm_outs5_t fsm_outs5; 2685 lsm6dso32x_fsm_outs6_t fsm_outs6; 2686 lsm6dso32x_fsm_outs7_t fsm_outs7; 2687 lsm6dso32x_fsm_outs8_t fsm_outs8; 2688 lsm6dso32x_fsm_outs9_t fsm_outs9; 2689 lsm6dso32x_fsm_outs10_t fsm_outs10; 2690 lsm6dso32x_fsm_outs11_t fsm_outs11; 2691 lsm6dso32x_fsm_outs12_t fsm_outs12; 2692 lsm6dso32x_fsm_outs13_t fsm_outs13; 2693 lsm6dso32x_fsm_outs14_t fsm_outs14; 2694 lsm6dso32x_fsm_outs15_t fsm_outs15; 2695 lsm6dso32x_fsm_outs16_t fsm_outs16; 2696 lsm6dso32x_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; 2697 lsm6dso32x_emb_func_odr_cfg_c_t emb_func_odr_cfg_c; 2698 lsm6dso32x_emb_func_src_t emb_func_src; 2699 lsm6dso32x_emb_func_init_a_t emb_func_init_a; 2700 lsm6dso32x_emb_func_init_b_t emb_func_init_b; 2701 lsm6dso32x_mag_cfg_a_t mag_cfg_a; 2702 lsm6dso32x_mag_cfg_b_t mag_cfg_b; 2703 lsm6dso32x_pedo_cmd_reg_t pedo_cmd_reg; 2704 lsm6dso32x_sensor_hub_1_t sensor_hub_1; 2705 lsm6dso32x_sensor_hub_2_t sensor_hub_2; 2706 lsm6dso32x_sensor_hub_3_t sensor_hub_3; 2707 lsm6dso32x_sensor_hub_4_t sensor_hub_4; 2708 lsm6dso32x_sensor_hub_5_t sensor_hub_5; 2709 lsm6dso32x_sensor_hub_6_t sensor_hub_6; 2710 lsm6dso32x_sensor_hub_7_t sensor_hub_7; 2711 lsm6dso32x_sensor_hub_8_t sensor_hub_8; 2712 lsm6dso32x_sensor_hub_9_t sensor_hub_9; 2713 lsm6dso32x_sensor_hub_10_t sensor_hub_10; 2714 lsm6dso32x_sensor_hub_11_t sensor_hub_11; 2715 lsm6dso32x_sensor_hub_12_t sensor_hub_12; 2716 lsm6dso32x_sensor_hub_13_t sensor_hub_13; 2717 lsm6dso32x_sensor_hub_14_t sensor_hub_14; 2718 lsm6dso32x_sensor_hub_15_t sensor_hub_15; 2719 lsm6dso32x_sensor_hub_16_t sensor_hub_16; 2720 lsm6dso32x_sensor_hub_17_t sensor_hub_17; 2721 lsm6dso32x_sensor_hub_18_t sensor_hub_18; 2722 lsm6dso32x_master_config_t master_config; 2723 lsm6dso32x_slv0_add_t slv0_add; 2724 lsm6dso32x_slv0_subadd_t slv0_subadd; 2725 lsm6dso32x_slv0_config_t slv0_config; 2726 lsm6dso32x_slv1_add_t slv1_add; 2727 lsm6dso32x_slv1_subadd_t slv1_subadd; 2728 lsm6dso32x_slv1_config_t slv1_config; 2729 lsm6dso32x_slv2_add_t slv2_add; 2730 lsm6dso32x_slv2_subadd_t slv2_subadd; 2731 lsm6dso32x_slv2_config_t slv2_config; 2732 lsm6dso32x_slv3_add_t slv3_add; 2733 lsm6dso32x_slv3_subadd_t slv3_subadd; 2734 lsm6dso32x_slv3_config_t slv3_config; 2735 lsm6dso32x_datawrite_slv0_t datawrite_slv0; 2736 lsm6dso32x_status_master_t status_master; 2737 bitwise_t bitwise; 2738 uint8_t byte; 2739 } lsm6dso32x_reg_t; 2740 2741 /** 2742 * @} 2743 * 2744 */ 2745 2746 #ifndef __weak 2747 #define __weak __attribute__((weak)) 2748 #endif /* __weak */ 2749 2750 /* 2751 * These are the basic platform dependent I/O routines to read 2752 * and write device registers connected on a standard bus. 2753 * The driver keeps offering a default implementation based on function 2754 * pointers to read/write routines for backward compatibility. 2755 * The __weak directive allows the final application to overwrite 2756 * them with a custom implementation. 2757 */ 2758 2759 int32_t lsm6dso32x_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, 2760 uint16_t len); 2761 int32_t lsm6dso32x_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, 2762 uint16_t len); 2763 2764 float_t lsm6dso32x_from_fs4_to_mg(int16_t lsb); 2765 float_t lsm6dso32x_from_fs8_to_mg(int16_t lsb); 2766 float_t lsm6dso32x_from_fs16_to_mg(int16_t lsb); 2767 float_t lsm6dso32x_from_fs32_to_mg(int16_t lsb); 2768 float_t lsm6dso32x_from_fs125_to_mdps(int16_t lsb); 2769 float_t lsm6dso32x_from_fs500_to_mdps(int16_t lsb); 2770 float_t lsm6dso32x_from_fs250_to_mdps(int16_t lsb); 2771 float_t lsm6dso32x_from_fs1000_to_mdps(int16_t lsb); 2772 float_t lsm6dso32x_from_fs2000_to_mdps(int16_t lsb); 2773 float_t lsm6dso32x_from_lsb_to_celsius(int16_t lsb); 2774 float_t lsm6dso32x_from_lsb_to_nsec(int16_t lsb); 2775 2776 typedef enum 2777 { 2778 LSM6DSO32X_4g = 0, 2779 LSM6DSO32X_32g = 1, 2780 LSM6DSO32X_8g = 2, 2781 LSM6DSO32X_16g = 3, 2782 } lsm6dso32x_fs_xl_t; 2783 int32_t lsm6dso32x_xl_full_scale_set(stmdev_ctx_t *ctx, lsm6dso32x_fs_xl_t val); 2784 int32_t lsm6dso32x_xl_full_scale_get(stmdev_ctx_t *ctx, 2785 lsm6dso32x_fs_xl_t *val); 2786 2787 typedef enum 2788 { 2789 LSM6DSO32X_XL_ODR_OFF = 0, 2790 LSM6DSO32X_XL_ODR_12Hz5 = 1, 2791 LSM6DSO32X_XL_ODR_26Hz = 2, 2792 LSM6DSO32X_XL_ODR_52Hz = 3, 2793 LSM6DSO32X_XL_ODR_104Hz = 4, 2794 LSM6DSO32X_XL_ODR_208Hz = 5, 2795 LSM6DSO32X_XL_ODR_417Hz = 6, 2796 LSM6DSO32X_XL_ODR_833Hz = 7, 2797 LSM6DSO32X_XL_ODR_1667Hz = 8, 2798 LSM6DSO32X_XL_ODR_3333Hz = 9, 2799 LSM6DSO32X_XL_ODR_6667Hz = 10, 2800 LSM6DSO32X_XL_ODR_1Hz6 = 11, /* (low power only) */ 2801 } lsm6dso32x_odr_xl_t; 2802 int32_t lsm6dso32x_xl_data_rate_set(stmdev_ctx_t *ctx, lsm6dso32x_odr_xl_t val); 2803 int32_t lsm6dso32x_xl_data_rate_get(stmdev_ctx_t *ctx, 2804 lsm6dso32x_odr_xl_t *val); 2805 2806 typedef enum 2807 { 2808 LSM6DSO32X_250dps = 0, 2809 LSM6DSO32X_125dps = 1, 2810 LSM6DSO32X_500dps = 2, 2811 LSM6DSO32X_1000dps = 4, 2812 LSM6DSO32X_2000dps = 6, 2813 } lsm6dso32x_fs_g_t; 2814 int32_t lsm6dso32x_gy_full_scale_set(stmdev_ctx_t *ctx, lsm6dso32x_fs_g_t val); 2815 int32_t lsm6dso32x_gy_full_scale_get(stmdev_ctx_t *ctx, lsm6dso32x_fs_g_t *val); 2816 2817 typedef enum 2818 { 2819 LSM6DSO32X_GY_ODR_OFF = 0, 2820 LSM6DSO32X_GY_ODR_12Hz5 = 1, 2821 LSM6DSO32X_GY_ODR_26Hz = 2, 2822 LSM6DSO32X_GY_ODR_52Hz = 3, 2823 LSM6DSO32X_GY_ODR_104Hz = 4, 2824 LSM6DSO32X_GY_ODR_208Hz = 5, 2825 LSM6DSO32X_GY_ODR_417Hz = 6, 2826 LSM6DSO32X_GY_ODR_833Hz = 7, 2827 LSM6DSO32X_GY_ODR_1667Hz = 8, 2828 LSM6DSO32X_GY_ODR_3333Hz = 9, 2829 LSM6DSO32X_GY_ODR_6667Hz = 10, 2830 } lsm6dso32x_odr_g_t; 2831 int32_t lsm6dso32x_gy_data_rate_set(stmdev_ctx_t *ctx, 2832 lsm6dso32x_odr_g_t val); 2833 int32_t lsm6dso32x_gy_data_rate_get(stmdev_ctx_t *ctx, 2834 lsm6dso32x_odr_g_t *val); 2835 2836 int32_t lsm6dso32x_block_data_update_set(stmdev_ctx_t *ctx, 2837 uint8_t val); 2838 int32_t lsm6dso32x_block_data_update_get(stmdev_ctx_t *ctx, 2839 uint8_t *val); 2840 2841 typedef enum 2842 { 2843 LSM6DSO32X_LSb_1mg = 0, 2844 LSM6DSO32X_LSb_16mg = 1, 2845 } lsm6dso32x_usr_off_w_t; 2846 int32_t lsm6dso32x_xl_offset_weight_set(stmdev_ctx_t *ctx, 2847 lsm6dso32x_usr_off_w_t val); 2848 int32_t lsm6dso32x_xl_offset_weight_get(stmdev_ctx_t *ctx, 2849 lsm6dso32x_usr_off_w_t *val); 2850 2851 typedef enum 2852 { 2853 LSM6DSO32X_HIGH_PERFORMANCE_MD = 0, 2854 LSM6DSO32X_LOW_NORMAL_POWER_MD = 1, 2855 LSM6DSO32X_ULTRA_LOW_POWER_MD = 2, 2856 } lsm6dso32x_xl_hm_mode_t; 2857 int32_t lsm6dso32x_xl_power_mode_set(stmdev_ctx_t *ctx, 2858 lsm6dso32x_xl_hm_mode_t val); 2859 int32_t lsm6dso32x_xl_power_mode_get(stmdev_ctx_t *ctx, 2860 lsm6dso32x_xl_hm_mode_t *val); 2861 2862 typedef enum 2863 { 2864 LSM6DSO32X_GY_HIGH_PERFORMANCE = 0, 2865 LSM6DSO32X_GY_NORMAL = 1, 2866 } lsm6dso32x_g_hm_mode_t; 2867 int32_t lsm6dso32x_gy_power_mode_set(stmdev_ctx_t *ctx, 2868 lsm6dso32x_g_hm_mode_t val); 2869 int32_t lsm6dso32x_gy_power_mode_get(stmdev_ctx_t *ctx, 2870 lsm6dso32x_g_hm_mode_t *val); 2871 2872 int32_t lsm6dso32x_status_reg_get(stmdev_ctx_t *ctx, 2873 lsm6dso32x_status_reg_t *val); 2874 2875 int32_t lsm6dso32x_xl_flag_data_ready_get(stmdev_ctx_t *ctx, 2876 uint8_t *val); 2877 2878 int32_t lsm6dso32x_gy_flag_data_ready_get(stmdev_ctx_t *ctx, 2879 uint8_t *val); 2880 2881 int32_t lsm6dso32x_temp_flag_data_ready_get(stmdev_ctx_t *ctx, 2882 uint8_t *val); 2883 2884 int32_t lsm6dso32x_xl_usr_offset_x_set(stmdev_ctx_t *ctx, 2885 uint8_t *buff); 2886 int32_t lsm6dso32x_xl_usr_offset_x_get(stmdev_ctx_t *ctx, 2887 uint8_t *buff); 2888 2889 int32_t lsm6dso32x_xl_usr_offset_y_set(stmdev_ctx_t *ctx, 2890 uint8_t *buff); 2891 int32_t lsm6dso32x_xl_usr_offset_y_get(stmdev_ctx_t *ctx, 2892 uint8_t *buff); 2893 2894 int32_t lsm6dso32x_xl_usr_offset_z_set(stmdev_ctx_t *ctx, 2895 uint8_t *buff); 2896 int32_t lsm6dso32x_xl_usr_offset_z_get(stmdev_ctx_t *ctx, 2897 uint8_t *buff); 2898 2899 int32_t lsm6dso32x_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val); 2900 int32_t lsm6dso32x_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val); 2901 2902 int32_t lsm6dso32x_timestamp_rst(stmdev_ctx_t *ctx); 2903 2904 int32_t lsm6dso32x_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); 2905 int32_t lsm6dso32x_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); 2906 2907 int32_t lsm6dso32x_timestamp_raw_get(stmdev_ctx_t *ctx, 2908 uint32_t *val); 2909 2910 typedef enum 2911 { 2912 LSM6DSO32X_NO_ROUND = 0, 2913 LSM6DSO32X_ROUND_XL = 1, 2914 LSM6DSO32X_ROUND_GY = 2, 2915 LSM6DSO32X_ROUND_GY_XL = 3, 2916 } lsm6dso32x_rounding_t; 2917 int32_t lsm6dso32x_rounding_mode_set(stmdev_ctx_t *ctx, 2918 lsm6dso32x_rounding_t val); 2919 int32_t lsm6dso32x_rounding_mode_get(stmdev_ctx_t *ctx, 2920 lsm6dso32x_rounding_t *val); 2921 2922 int32_t lsm6dso32x_temperature_raw_get(stmdev_ctx_t *ctx, 2923 int16_t *val); 2924 2925 int32_t lsm6dso32x_angular_rate_raw_get(stmdev_ctx_t *ctx, 2926 int16_t *val); 2927 2928 int32_t lsm6dso32x_acceleration_raw_get(stmdev_ctx_t *ctx, 2929 int16_t *val); 2930 2931 int32_t lsm6dso32x_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff); 2932 2933 int32_t lsm6dso32x_number_of_steps_get(stmdev_ctx_t *ctx, 2934 uint16_t *val); 2935 2936 int32_t lsm6dso32x_steps_reset(stmdev_ctx_t *ctx); 2937 2938 int32_t lsm6dso32x_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff); 2939 2940 int32_t lsm6dso32x_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val); 2941 int32_t lsm6dso32x_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val); 2942 2943 typedef enum 2944 { 2945 LSM6DSO32X_USER_BANK = 0, 2946 LSM6DSO32X_SENSOR_HUB_BANK = 1, 2947 LSM6DSO32X_EMBEDDED_FUNC_BANK = 2, 2948 } lsm6dso32x_reg_access_t; 2949 int32_t lsm6dso32x_mem_bank_set(stmdev_ctx_t *ctx, 2950 lsm6dso32x_reg_access_t val); 2951 int32_t lsm6dso32x_mem_bank_get(stmdev_ctx_t *ctx, 2952 lsm6dso32x_reg_access_t *val); 2953 2954 int32_t lsm6dso32x_ln_pg_write_byte(stmdev_ctx_t *ctx, 2955 uint16_t address, 2956 uint8_t *val); 2957 int32_t lsm6dso32x_ln_pg_read_byte(stmdev_ctx_t *ctx, 2958 uint16_t address, 2959 uint8_t *val); 2960 2961 int32_t lsm6dso32x_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, 2962 uint8_t *buf, uint8_t len); 2963 int32_t lsm6dso32x_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, 2964 uint8_t *val); 2965 2966 typedef enum 2967 { 2968 LSM6DSO32X_DRDY_LATCHED = 0, 2969 LSM6DSO32X_DRDY_PULSED = 1, 2970 } lsm6dso32x_dataready_pulsed_t; 2971 int32_t lsm6dso32x_data_ready_mode_set(stmdev_ctx_t *ctx, 2972 lsm6dso32x_dataready_pulsed_t val); 2973 int32_t lsm6dso32x_data_ready_mode_get(stmdev_ctx_t *ctx, 2974 lsm6dso32x_dataready_pulsed_t *val); 2975 2976 int32_t lsm6dso32x_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); 2977 2978 int32_t lsm6dso32x_reset_set(stmdev_ctx_t *ctx, uint8_t val); 2979 int32_t lsm6dso32x_reset_get(stmdev_ctx_t *ctx, uint8_t *val); 2980 2981 int32_t lsm6dso32x_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); 2982 int32_t lsm6dso32x_auto_increment_get(stmdev_ctx_t *ctx, 2983 uint8_t *val); 2984 2985 int32_t lsm6dso32x_boot_set(stmdev_ctx_t *ctx, uint8_t val); 2986 int32_t lsm6dso32x_boot_get(stmdev_ctx_t *ctx, uint8_t *val); 2987 2988 typedef enum 2989 { 2990 LSM6DSO32X_XL_ST_DISABLE = 0, 2991 LSM6DSO32X_XL_ST_POSITIVE = 1, 2992 LSM6DSO32X_XL_ST_NEGATIVE = 2, 2993 } lsm6dso32x_st_xl_t; 2994 int32_t lsm6dso32x_xl_self_test_set(stmdev_ctx_t *ctx, 2995 lsm6dso32x_st_xl_t val); 2996 int32_t lsm6dso32x_xl_self_test_get(stmdev_ctx_t *ctx, 2997 lsm6dso32x_st_xl_t *val); 2998 2999 typedef enum 3000 { 3001 LSM6DSO32X_GY_ST_DISABLE = 0, 3002 LSM6DSO32X_GY_ST_POSITIVE = 1, 3003 LSM6DSO32X_GY_ST_NEGATIVE = 3, 3004 } lsm6dso32x_st_g_t; 3005 int32_t lsm6dso32x_gy_self_test_set(stmdev_ctx_t *ctx, 3006 lsm6dso32x_st_g_t val); 3007 int32_t lsm6dso32x_gy_self_test_get(stmdev_ctx_t *ctx, 3008 lsm6dso32x_st_g_t *val); 3009 3010 int32_t lsm6dso32x_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val); 3011 int32_t lsm6dso32x_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val); 3012 3013 int32_t lsm6dso32x_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val); 3014 int32_t lsm6dso32x_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val); 3015 3016 int32_t lsm6dso32x_filter_settling_mask_set(stmdev_ctx_t *ctx, 3017 uint8_t val); 3018 int32_t lsm6dso32x_filter_settling_mask_get(stmdev_ctx_t *ctx, 3019 uint8_t *val); 3020 3021 typedef enum 3022 { 3023 LSM6DSO32X_ULTRA_LIGHT = 0, 3024 LSM6DSO32X_VERY_LIGHT = 1, 3025 LSM6DSO32X_LIGHT = 2, 3026 LSM6DSO32X_MEDIUM = 3, 3027 LSM6DSO32X_STRONG = 4, 3028 LSM6DSO32X_VERY_STRONG = 5, 3029 LSM6DSO32X_AGGRESSIVE = 6, 3030 LSM6DSO32X_XTREME = 7, 3031 } lsm6dso32x_ftype_t; 3032 int32_t lsm6dso32x_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, 3033 lsm6dso32x_ftype_t val); 3034 int32_t lsm6dso32x_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, 3035 lsm6dso32x_ftype_t *val); 3036 3037 int32_t lsm6dso32x_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val); 3038 int32_t lsm6dso32x_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val); 3039 3040 typedef enum 3041 { 3042 LSM6DSO32X_HP_PATH_DISABLE_ON_OUT = 0x00, 3043 LSM6DSO32X_SLOPE_ODR_DIV_4 = 0x10, 3044 LSM6DSO32X_HP_ODR_DIV_10 = 0x11, 3045 LSM6DSO32X_HP_ODR_DIV_20 = 0x12, 3046 LSM6DSO32X_HP_ODR_DIV_45 = 0x13, 3047 LSM6DSO32X_HP_ODR_DIV_100 = 0x14, 3048 LSM6DSO32X_HP_ODR_DIV_200 = 0x15, 3049 LSM6DSO32X_HP_ODR_DIV_400 = 0x16, 3050 LSM6DSO32X_HP_ODR_DIV_800 = 0x17, 3051 LSM6DSO32X_HP_REF_MD_ODR_DIV_10 = 0x31, 3052 LSM6DSO32X_HP_REF_MD_ODR_DIV_20 = 0x32, 3053 LSM6DSO32X_HP_REF_MD_ODR_DIV_45 = 0x33, 3054 LSM6DSO32X_HP_REF_MD_ODR_DIV_100 = 0x34, 3055 LSM6DSO32X_HP_REF_MD_ODR_DIV_200 = 0x35, 3056 LSM6DSO32X_HP_REF_MD_ODR_DIV_400 = 0x36, 3057 LSM6DSO32X_HP_REF_MD_ODR_DIV_800 = 0x37, 3058 LSM6DSO32X_LP_ODR_DIV_10 = 0x01, 3059 LSM6DSO32X_LP_ODR_DIV_20 = 0x02, 3060 LSM6DSO32X_LP_ODR_DIV_45 = 0x03, 3061 LSM6DSO32X_LP_ODR_DIV_100 = 0x04, 3062 LSM6DSO32X_LP_ODR_DIV_200 = 0x05, 3063 LSM6DSO32X_LP_ODR_DIV_400 = 0x06, 3064 LSM6DSO32X_LP_ODR_DIV_800 = 0x07, 3065 } lsm6dso32x_hp_slope_xl_en_t; 3066 int32_t lsm6dso32x_xl_hp_path_on_out_set(stmdev_ctx_t *ctx, 3067 lsm6dso32x_hp_slope_xl_en_t val); 3068 int32_t lsm6dso32x_xl_hp_path_on_out_get(stmdev_ctx_t *ctx, 3069 lsm6dso32x_hp_slope_xl_en_t *val); 3070 3071 int32_t lsm6dso32x_xl_fast_settling_set(stmdev_ctx_t *ctx, 3072 uint8_t val); 3073 int32_t lsm6dso32x_xl_fast_settling_get(stmdev_ctx_t *ctx, 3074 uint8_t *val); 3075 3076 typedef enum 3077 { 3078 LSM6DSO32X_USE_SLOPE = 0, 3079 LSM6DSO32X_USE_HPF = 1, 3080 } lsm6dso32x_slope_fds_t; 3081 int32_t lsm6dso32x_xl_hp_path_internal_set(stmdev_ctx_t *ctx, 3082 lsm6dso32x_slope_fds_t val); 3083 int32_t lsm6dso32x_xl_hp_path_internal_get(stmdev_ctx_t *ctx, 3084 lsm6dso32x_slope_fds_t *val); 3085 3086 typedef enum 3087 { 3088 LSM6DSO32X_HP_FILTER_NONE = 0x00, 3089 LSM6DSO32X_HP_FILTER_16mHz = 0x80, 3090 LSM6DSO32X_HP_FILTER_65mHz = 0x81, 3091 LSM6DSO32X_HP_FILTER_260mHz = 0x82, 3092 LSM6DSO32X_HP_FILTER_1Hz04 = 0x83, 3093 } lsm6dso32x_hpm_g_t; 3094 int32_t lsm6dso32x_gy_hp_path_internal_set(stmdev_ctx_t *ctx, 3095 lsm6dso32x_hpm_g_t val); 3096 int32_t lsm6dso32x_gy_hp_path_internal_get(stmdev_ctx_t *ctx, 3097 lsm6dso32x_hpm_g_t *val); 3098 3099 typedef enum 3100 { 3101 LSM6DSO32X_PULL_UP_DISC = 0, 3102 LSM6DSO32X_PULL_UP_CONNECT = 1, 3103 } lsm6dso32x_sdo_pu_en_t; 3104 int32_t lsm6dso32x_sdo_sa0_mode_set(stmdev_ctx_t *ctx, 3105 lsm6dso32x_sdo_pu_en_t val); 3106 int32_t lsm6dso32x_sdo_sa0_mode_get(stmdev_ctx_t *ctx, 3107 lsm6dso32x_sdo_pu_en_t *val); 3108 3109 typedef enum 3110 { 3111 LSM6DSO32X_SPI_4_WIRE = 0, 3112 LSM6DSO32X_SPI_3_WIRE = 1, 3113 } lsm6dso32x_sim_t; 3114 int32_t lsm6dso32x_spi_mode_set(stmdev_ctx_t *ctx, 3115 lsm6dso32x_sim_t val); 3116 int32_t lsm6dso32x_spi_mode_get(stmdev_ctx_t *ctx, 3117 lsm6dso32x_sim_t *val); 3118 3119 typedef enum 3120 { 3121 LSM6DSO32X_I2C_ENABLE = 0, 3122 LSM6DSO32X_I2C_DISABLE = 1, 3123 } lsm6dso32x_i2c_disable_t; 3124 int32_t lsm6dso32x_i2c_interface_set(stmdev_ctx_t *ctx, 3125 lsm6dso32x_i2c_disable_t val); 3126 int32_t lsm6dso32x_i2c_interface_get(stmdev_ctx_t *ctx, 3127 lsm6dso32x_i2c_disable_t *val); 3128 3129 typedef enum 3130 { 3131 LSM6DSO32X_I3C_DISABLE = 0x80, 3132 LSM6DSO32X_I3C_ENABLE_T_50us = 0x00, 3133 LSM6DSO32X_I3C_ENABLE_T_2us = 0x01, 3134 LSM6DSO32X_I3C_ENABLE_T_1ms = 0x02, 3135 LSM6DSO32X_I3C_ENABLE_T_25ms = 0x03, 3136 } lsm6dso32x_i3c_disable_t; 3137 int32_t lsm6dso32x_i3c_disable_set(stmdev_ctx_t *ctx, 3138 lsm6dso32x_i3c_disable_t val); 3139 int32_t lsm6dso32x_i3c_disable_get(stmdev_ctx_t *ctx, 3140 lsm6dso32x_i3c_disable_t *val); 3141 3142 typedef enum 3143 { 3144 LSM6DSO32X_PUSH_PULL = 0x00, 3145 LSM6DSO32X_OPEN_DRAIN = 0x01, 3146 LSM6DSO32X_INT1_NOPULL_DOWN_INT2_PUSH_PULL = 0x02, 3147 LSM6DSO32X_INT1_NOPULL_DOWN_INT2_OPEN_DRAIN = 0x03, 3148 } lsm6dso32x_pp_od_t; 3149 int32_t lsm6dso32x_pin_mode_set(stmdev_ctx_t *ctx, 3150 lsm6dso32x_pp_od_t val); 3151 int32_t lsm6dso32x_pin_mode_get(stmdev_ctx_t *ctx, 3152 lsm6dso32x_pp_od_t *val); 3153 3154 typedef enum 3155 { 3156 LSM6DSO32X_ACTIVE_HIGH = 0, 3157 LSM6DSO32X_ACTIVE_LOW = 1, 3158 } lsm6dso32x_h_lactive_t; 3159 int32_t lsm6dso32x_pin_polarity_set(stmdev_ctx_t *ctx, 3160 lsm6dso32x_h_lactive_t val); 3161 int32_t lsm6dso32x_pin_polarity_get(stmdev_ctx_t *ctx, 3162 lsm6dso32x_h_lactive_t *val); 3163 3164 int32_t lsm6dso32x_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); 3165 int32_t lsm6dso32x_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); 3166 3167 typedef enum 3168 { 3169 LSM6DSO32X_ALL_INT_PULSED = 0, 3170 LSM6DSO32X_BASE_LATCHED_EMB_PULSED = 1, 3171 LSM6DSO32X_BASE_PULSED_EMB_LATCHED = 2, 3172 LSM6DSO32X_ALL_INT_LATCHED = 3, 3173 } lsm6dso32x_lir_t; 3174 int32_t lsm6dso32x_int_notification_set(stmdev_ctx_t *ctx, 3175 lsm6dso32x_lir_t val); 3176 int32_t lsm6dso32x_int_notification_get(stmdev_ctx_t *ctx, 3177 lsm6dso32x_lir_t *val); 3178 3179 typedef enum 3180 { 3181 LSM6DSO32X_LSb_FS_DIV_64 = 0, 3182 LSM6DSO32X_LSb_FS_DIV_256 = 1, 3183 } lsm6dso32x_wake_ths_w_t; 3184 int32_t lsm6dso32x_wkup_ths_weight_set(stmdev_ctx_t *ctx, 3185 lsm6dso32x_wake_ths_w_t val); 3186 int32_t lsm6dso32x_wkup_ths_weight_get(stmdev_ctx_t *ctx, 3187 lsm6dso32x_wake_ths_w_t *val); 3188 3189 int32_t lsm6dso32x_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val); 3190 int32_t lsm6dso32x_wkup_threshold_get(stmdev_ctx_t *ctx, 3191 uint8_t *val); 3192 3193 int32_t lsm6dso32x_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, 3194 uint8_t val); 3195 int32_t lsm6dso32x_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, 3196 uint8_t *val); 3197 3198 int32_t lsm6dso32x_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val); 3199 int32_t lsm6dso32x_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 3200 3201 int32_t lsm6dso32x_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val); 3202 int32_t lsm6dso32x_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val); 3203 3204 typedef enum 3205 { 3206 LSM6DSO32X_DRIVE_SLEEP_CHG_EVENT = 0, 3207 LSM6DSO32X_DRIVE_SLEEP_STATUS = 1, 3208 } lsm6dso32x_sleep_status_on_int_t; 3209 int32_t lsm6dso32x_act_pin_notification_set(stmdev_ctx_t *ctx, 3210 lsm6dso32x_sleep_status_on_int_t val); 3211 int32_t lsm6dso32x_act_pin_notification_get(stmdev_ctx_t *ctx, 3212 lsm6dso32x_sleep_status_on_int_t *val); 3213 3214 typedef enum 3215 { 3216 LSM6DSO32X_XL_AND_GY_NOT_AFFECTED = 0, 3217 LSM6DSO32X_XL_12Hz5_GY_NOT_AFFECTED = 1, 3218 LSM6DSO32X_XL_12Hz5_GY_SLEEP = 2, 3219 LSM6DSO32X_XL_12Hz5_GY_PD = 3, 3220 } lsm6dso32x_inact_en_t; 3221 int32_t lsm6dso32x_act_mode_set(stmdev_ctx_t *ctx, 3222 lsm6dso32x_inact_en_t val); 3223 int32_t lsm6dso32x_act_mode_get(stmdev_ctx_t *ctx, 3224 lsm6dso32x_inact_en_t *val); 3225 3226 int32_t lsm6dso32x_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val); 3227 int32_t lsm6dso32x_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 3228 3229 int32_t lsm6dso32x_tap_detection_on_z_set(stmdev_ctx_t *ctx, 3230 uint8_t val); 3231 int32_t lsm6dso32x_tap_detection_on_z_get(stmdev_ctx_t *ctx, 3232 uint8_t *val); 3233 3234 int32_t lsm6dso32x_tap_detection_on_y_set(stmdev_ctx_t *ctx, 3235 uint8_t val); 3236 int32_t lsm6dso32x_tap_detection_on_y_get(stmdev_ctx_t *ctx, 3237 uint8_t *val); 3238 3239 int32_t lsm6dso32x_tap_detection_on_x_set(stmdev_ctx_t *ctx, 3240 uint8_t val); 3241 int32_t lsm6dso32x_tap_detection_on_x_get(stmdev_ctx_t *ctx, 3242 uint8_t *val); 3243 3244 int32_t lsm6dso32x_tap_threshold_x_set(stmdev_ctx_t *ctx, 3245 uint8_t val); 3246 int32_t lsm6dso32x_tap_threshold_x_get(stmdev_ctx_t *ctx, 3247 uint8_t *val); 3248 3249 typedef enum 3250 { 3251 LSM6DSO32X_XYZ = 0, 3252 LSM6DSO32X_YXZ = 1, 3253 LSM6DSO32X_XZY = 2, 3254 LSM6DSO32X_ZYX = 3, 3255 LSM6DSO32X_YZX = 5, 3256 LSM6DSO32X_ZXY = 6, 3257 } lsm6dso32x_tap_priority_t; 3258 int32_t lsm6dso32x_tap_axis_priority_set(stmdev_ctx_t *ctx, 3259 lsm6dso32x_tap_priority_t val); 3260 int32_t lsm6dso32x_tap_axis_priority_get(stmdev_ctx_t *ctx, 3261 lsm6dso32x_tap_priority_t *val); 3262 3263 int32_t lsm6dso32x_tap_threshold_y_set(stmdev_ctx_t *ctx, 3264 uint8_t val); 3265 int32_t lsm6dso32x_tap_threshold_y_get(stmdev_ctx_t *ctx, 3266 uint8_t *val); 3267 3268 int32_t lsm6dso32x_tap_threshold_z_set(stmdev_ctx_t *ctx, 3269 uint8_t val); 3270 int32_t lsm6dso32x_tap_threshold_z_get(stmdev_ctx_t *ctx, 3271 uint8_t *val); 3272 3273 int32_t lsm6dso32x_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val); 3274 int32_t lsm6dso32x_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val); 3275 3276 int32_t lsm6dso32x_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val); 3277 int32_t lsm6dso32x_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val); 3278 3279 int32_t lsm6dso32x_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val); 3280 int32_t lsm6dso32x_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 3281 3282 typedef enum 3283 { 3284 LSM6DSO32X_ONLY_SINGLE = 0, 3285 LSM6DSO32X_BOTH_SINGLE_DOUBLE = 1, 3286 } lsm6dso32x_single_double_tap_t; 3287 int32_t lsm6dso32x_tap_mode_set(stmdev_ctx_t *ctx, 3288 lsm6dso32x_single_double_tap_t val); 3289 int32_t lsm6dso32x_tap_mode_get(stmdev_ctx_t *ctx, 3290 lsm6dso32x_single_double_tap_t *val); 3291 3292 typedef enum 3293 { 3294 LSM6DSO32X_DEG_80 = 0, 3295 LSM6DSO32X_DEG_70 = 1, 3296 LSM6DSO32X_DEG_60 = 2, 3297 LSM6DSO32X_DEG_50 = 3, 3298 } lsm6dso32x_sixd_ths_t; 3299 int32_t lsm6dso32x_6d_threshold_set(stmdev_ctx_t *ctx, 3300 lsm6dso32x_sixd_ths_t val); 3301 int32_t lsm6dso32x_6d_threshold_get(stmdev_ctx_t *ctx, 3302 lsm6dso32x_sixd_ths_t *val); 3303 3304 int32_t lsm6dso32x_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val); 3305 int32_t lsm6dso32x_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val); 3306 3307 typedef enum 3308 { 3309 LSM6DSO32X_FF_TSH_312mg = 0, 3310 LSM6DSO32X_FF_TSH_438mg = 1, 3311 LSM6DSO32X_FF_TSH_500mg = 2, 3312 } lsm6dso32x_ff_ths_t; 3313 int32_t lsm6dso32x_ff_threshold_set(stmdev_ctx_t *ctx, 3314 lsm6dso32x_ff_ths_t val); 3315 int32_t lsm6dso32x_ff_threshold_get(stmdev_ctx_t *ctx, 3316 lsm6dso32x_ff_ths_t *val); 3317 3318 int32_t lsm6dso32x_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val); 3319 int32_t lsm6dso32x_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 3320 3321 int32_t lsm6dso32x_fifo_watermark_set(stmdev_ctx_t *ctx, 3322 uint16_t val); 3323 int32_t lsm6dso32x_fifo_watermark_get(stmdev_ctx_t *ctx, 3324 uint16_t *val); 3325 3326 int32_t lsm6dso32x_compression_algo_init_set(stmdev_ctx_t *ctx, 3327 uint8_t val); 3328 int32_t lsm6dso32x_compression_algo_init_get(stmdev_ctx_t *ctx, 3329 uint8_t *val); 3330 3331 typedef enum 3332 { 3333 LSM6DSO32X_CMP_DISABLE = 0x00, 3334 LSM6DSO32X_CMP_ALWAYS = 0x04, 3335 LSM6DSO32X_CMP_8_TO_1 = 0x05, 3336 LSM6DSO32X_CMP_16_TO_1 = 0x06, 3337 LSM6DSO32X_CMP_32_TO_1 = 0x07, 3338 } lsm6dso32x_uncoptr_rate_t; 3339 int32_t lsm6dso32x_compression_algo_set(stmdev_ctx_t *ctx, 3340 lsm6dso32x_uncoptr_rate_t val); 3341 int32_t lsm6dso32x_compression_algo_get(stmdev_ctx_t *ctx, 3342 lsm6dso32x_uncoptr_rate_t *val); 3343 3344 int32_t lsm6dso32x_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, 3345 uint8_t val); 3346 int32_t lsm6dso32x_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, 3347 uint8_t *val); 3348 3349 int32_t lsm6dso32x_compression_algo_real_time_set(stmdev_ctx_t *ctx, 3350 uint8_t val); 3351 int32_t lsm6dso32x_compression_algo_real_time_get(stmdev_ctx_t *ctx, 3352 uint8_t *val); 3353 3354 int32_t lsm6dso32x_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, 3355 uint8_t val); 3356 int32_t lsm6dso32x_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, 3357 uint8_t *val); 3358 3359 typedef enum 3360 { 3361 LSM6DSO32X_XL_NOT_BATCHED = 0, 3362 LSM6DSO32X_XL_BATCHED_AT_12Hz5 = 1, 3363 LSM6DSO32X_XL_BATCHED_AT_26Hz = 2, 3364 LSM6DSO32X_XL_BATCHED_AT_52Hz = 3, 3365 LSM6DSO32X_XL_BATCHED_AT_104Hz = 4, 3366 LSM6DSO32X_XL_BATCHED_AT_208Hz = 5, 3367 LSM6DSO32X_XL_BATCHED_AT_417Hz = 6, 3368 LSM6DSO32X_XL_BATCHED_AT_833Hz = 7, 3369 LSM6DSO32X_XL_BATCHED_AT_1667Hz = 8, 3370 LSM6DSO32X_XL_BATCHED_AT_3333Hz = 9, 3371 LSM6DSO32X_XL_BATCHED_AT_6667Hz = 10, 3372 LSM6DSO32X_XL_BATCHED_AT_6Hz5 = 11, 3373 } lsm6dso32x_bdr_xl_t; 3374 int32_t lsm6dso32x_fifo_xl_batch_set(stmdev_ctx_t *ctx, 3375 lsm6dso32x_bdr_xl_t val); 3376 int32_t lsm6dso32x_fifo_xl_batch_get(stmdev_ctx_t *ctx, 3377 lsm6dso32x_bdr_xl_t *val); 3378 3379 typedef enum 3380 { 3381 LSM6DSO32X_GY_NOT_BATCHED = 0, 3382 LSM6DSO32X_GY_BATCHED_AT_12Hz5 = 1, 3383 LSM6DSO32X_GY_BATCHED_AT_26Hz = 2, 3384 LSM6DSO32X_GY_BATCHED_AT_52Hz = 3, 3385 LSM6DSO32X_GY_BATCHED_AT_104Hz = 4, 3386 LSM6DSO32X_GY_BATCHED_AT_208Hz = 5, 3387 LSM6DSO32X_GY_BATCHED_AT_417Hz = 6, 3388 LSM6DSO32X_GY_BATCHED_AT_833Hz = 7, 3389 LSM6DSO32X_GY_BATCHED_AT_1667Hz = 8, 3390 LSM6DSO32X_GY_BATCHED_AT_3333Hz = 9, 3391 LSM6DSO32X_GY_BATCHED_AT_6667Hz = 10, 3392 LSM6DSO32X_GY_BATCHED_AT_6Hz5 = 11, 3393 } lsm6dso32x_bdr_gy_t; 3394 int32_t lsm6dso32x_fifo_gy_batch_set(stmdev_ctx_t *ctx, 3395 lsm6dso32x_bdr_gy_t val); 3396 int32_t lsm6dso32x_fifo_gy_batch_get(stmdev_ctx_t *ctx, 3397 lsm6dso32x_bdr_gy_t *val); 3398 3399 typedef enum 3400 { 3401 LSM6DSO32X_BYPASS_MODE = 0, 3402 LSM6DSO32X_FIFO_MODE = 1, 3403 LSM6DSO32X_STREAM_TO_FIFO_MODE = 3, 3404 LSM6DSO32X_BYPASS_TO_STREAM_MODE = 4, 3405 LSM6DSO32X_STREAM_MODE = 6, 3406 LSM6DSO32X_BYPASS_TO_FIFO_MODE = 7, 3407 } lsm6dso32x_fifo_mode_t; 3408 int32_t lsm6dso32x_fifo_mode_set(stmdev_ctx_t *ctx, 3409 lsm6dso32x_fifo_mode_t val); 3410 int32_t lsm6dso32x_fifo_mode_get(stmdev_ctx_t *ctx, 3411 lsm6dso32x_fifo_mode_t *val); 3412 3413 typedef enum 3414 { 3415 LSM6DSO32X_TEMP_NOT_BATCHED = 0, 3416 LSM6DSO32X_TEMP_BATCHED_AT_1Hz6 = 1, 3417 LSM6DSO32X_TEMP_BATCHED_AT_12Hz5 = 2, 3418 LSM6DSO32X_TEMP_BATCHED_AT_52Hz = 3, 3419 } lsm6dso32x_odr_t_batch_t; 3420 int32_t lsm6dso32x_fifo_temp_batch_set(stmdev_ctx_t *ctx, 3421 lsm6dso32x_odr_t_batch_t val); 3422 int32_t lsm6dso32x_fifo_temp_batch_get(stmdev_ctx_t *ctx, 3423 lsm6dso32x_odr_t_batch_t *val); 3424 3425 typedef enum 3426 { 3427 LSM6DSO32X_NO_DECIMATION = 0, 3428 LSM6DSO32X_DEC_1 = 1, 3429 LSM6DSO32X_DEC_8 = 2, 3430 LSM6DSO32X_DEC_32 = 3, 3431 } lsm6dso32x_odr_ts_batch_t; 3432 int32_t lsm6dso32x_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, 3433 lsm6dso32x_odr_ts_batch_t val); 3434 int32_t lsm6dso32x_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, 3435 lsm6dso32x_odr_ts_batch_t *val); 3436 3437 typedef enum 3438 { 3439 LSM6DSO32X_XL_BATCH_EVENT = 0, 3440 LSM6DSO32X_GYRO_BATCH_EVENT = 1, 3441 } lsm6dso32x_trig_counter_bdr_t; 3442 3443 typedef enum 3444 { 3445 LSM6DSO32X_GYRO_NC_TAG = 1, 3446 LSM6DSO32X_XL_NC_TAG, 3447 LSM6DSO32X_TEMPERATURE_TAG, 3448 LSM6DSO32X_TIMESTAMP_TAG, 3449 LSM6DSO32X_CFG_CHANGE_TAG, 3450 LSM6DSO32X_XL_NC_T_2_TAG, 3451 LSM6DSO32X_XL_NC_T_1_TAG, 3452 LSM6DSO32X_XL_2XC_TAG, 3453 LSM6DSO32X_XL_3XC_TAG, 3454 LSM6DSO32X_GYRO_NC_T_2_TAG, 3455 LSM6DSO32X_GYRO_NC_T_1_TAG, 3456 LSM6DSO32X_GYRO_2XC_TAG, 3457 LSM6DSO32X_GYRO_3XC_TAG, 3458 LSM6DSO32X_SENSORHUB_SLAVE0_TAG, 3459 LSM6DSO32X_SENSORHUB_SLAVE1_TAG, 3460 LSM6DSO32X_SENSORHUB_SLAVE2_TAG, 3461 LSM6DSO32X_SENSORHUB_SLAVE3_TAG, 3462 LSM6DSO32X_STEP_CPUNTER_TAG, 3463 LSM6DSO32X_GAME_ROTATION_TAG, 3464 LSM6DSO32X_GEOMAG_ROTATION_TAG, 3465 LSM6DSO32X_ROTATION_TAG, 3466 LSM6DSO32X_SENSORHUB_NACK_TAG = 0x19, 3467 } lsm6dso32x_fifo_tag_t; 3468 int32_t lsm6dso32x_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx, 3469 lsm6dso32x_trig_counter_bdr_t val); 3470 int32_t lsm6dso32x_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx, 3471 lsm6dso32x_trig_counter_bdr_t *val); 3472 3473 int32_t lsm6dso32x_rst_batch_counter_set(stmdev_ctx_t *ctx, 3474 uint8_t val); 3475 int32_t lsm6dso32x_rst_batch_counter_get(stmdev_ctx_t *ctx, 3476 uint8_t *val); 3477 3478 int32_t lsm6dso32x_batch_counter_threshold_set(stmdev_ctx_t *ctx, 3479 uint16_t val); 3480 int32_t lsm6dso32x_batch_counter_threshold_get(stmdev_ctx_t *ctx, 3481 uint16_t *val); 3482 3483 int32_t lsm6dso32x_fifo_data_level_get(stmdev_ctx_t *ctx, 3484 uint16_t *val); 3485 3486 int32_t lsm6dso32x_fifo_status_get(stmdev_ctx_t *ctx, 3487 lsm6dso32x_fifo_status2_t *val); 3488 3489 int32_t lsm6dso32x_fifo_full_flag_get(stmdev_ctx_t *ctx, 3490 uint8_t *val); 3491 3492 int32_t lsm6dso32x_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); 3493 3494 int32_t lsm6dso32x_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); 3495 3496 int32_t lsm6dso32x_fifo_sensor_tag_get(stmdev_ctx_t *ctx, 3497 lsm6dso32x_fifo_tag_t *val); 3498 3499 int32_t lsm6dso32x_fifo_pedo_batch_set(stmdev_ctx_t *ctx, 3500 uint8_t val); 3501 int32_t lsm6dso32x_fifo_pedo_batch_get(stmdev_ctx_t *ctx, 3502 uint8_t *val); 3503 3504 int32_t lsm6dso32x_sh_batch_slave_0_set(stmdev_ctx_t *ctx, 3505 uint8_t val); 3506 int32_t lsm6dso32x_sh_batch_slave_0_get(stmdev_ctx_t *ctx, 3507 uint8_t *val); 3508 3509 int32_t lsm6dso32x_sh_batch_slave_1_set(stmdev_ctx_t *ctx, 3510 uint8_t val); 3511 int32_t lsm6dso32x_sh_batch_slave_1_get(stmdev_ctx_t *ctx, 3512 uint8_t *val); 3513 3514 int32_t lsm6dso32x_sh_batch_slave_2_set(stmdev_ctx_t *ctx, 3515 uint8_t val); 3516 int32_t lsm6dso32x_sh_batch_slave_2_get(stmdev_ctx_t *ctx, 3517 uint8_t *val); 3518 3519 int32_t lsm6dso32x_sh_batch_slave_3_set(stmdev_ctx_t *ctx, 3520 uint8_t val); 3521 int32_t lsm6dso32x_sh_batch_slave_3_get(stmdev_ctx_t *ctx, 3522 uint8_t *val); 3523 3524 typedef enum 3525 { 3526 LSM6DSO32X_DEN_DISABLE = 0, 3527 LSM6DSO32X_LEVEL_FIFO = 6, 3528 LSM6DSO32X_LEVEL_LETCHED = 3, 3529 LSM6DSO32X_LEVEL_TRIGGER = 2, 3530 LSM6DSO32X_EDGE_TRIGGER = 4, 3531 } lsm6dso32x_den_mode_t; 3532 int32_t lsm6dso32x_den_mode_set(stmdev_ctx_t *ctx, 3533 lsm6dso32x_den_mode_t val); 3534 int32_t lsm6dso32x_den_mode_get(stmdev_ctx_t *ctx, 3535 lsm6dso32x_den_mode_t *val); 3536 3537 typedef enum 3538 { 3539 LSM6DSO32X_DEN_ACT_LOW = 0, 3540 LSM6DSO32X_DEN_ACT_HIGH = 1, 3541 } lsm6dso32x_den_lh_t; 3542 int32_t lsm6dso32x_den_polarity_set(stmdev_ctx_t *ctx, 3543 lsm6dso32x_den_lh_t val); 3544 int32_t lsm6dso32x_den_polarity_get(stmdev_ctx_t *ctx, 3545 lsm6dso32x_den_lh_t *val); 3546 3547 typedef enum 3548 { 3549 LSM6DSO32X_STAMP_IN_GY_DATA = 0, 3550 LSM6DSO32X_STAMP_IN_XL_DATA = 1, 3551 LSM6DSO32X_STAMP_IN_GY_XL_DATA = 2, 3552 } lsm6dso32x_den_xl_g_t; 3553 int32_t lsm6dso32x_den_enable_set(stmdev_ctx_t *ctx, 3554 lsm6dso32x_den_xl_g_t val); 3555 int32_t lsm6dso32x_den_enable_get(stmdev_ctx_t *ctx, 3556 lsm6dso32x_den_xl_g_t *val); 3557 3558 int32_t lsm6dso32x_den_mark_axis_x_set(stmdev_ctx_t *ctx, 3559 uint8_t val); 3560 int32_t lsm6dso32x_den_mark_axis_x_get(stmdev_ctx_t *ctx, 3561 uint8_t *val); 3562 3563 int32_t lsm6dso32x_den_mark_axis_y_set(stmdev_ctx_t *ctx, 3564 uint8_t val); 3565 int32_t lsm6dso32x_den_mark_axis_y_get(stmdev_ctx_t *ctx, 3566 uint8_t *val); 3567 3568 int32_t lsm6dso32x_den_mark_axis_z_set(stmdev_ctx_t *ctx, 3569 uint8_t val); 3570 int32_t lsm6dso32x_den_mark_axis_z_get(stmdev_ctx_t *ctx, 3571 uint8_t *val); 3572 3573 typedef enum 3574 { 3575 LSM6DSO32X_PEDO_BASE_MODE = 0x00, 3576 LSM6DSO32X_FALSE_STEP_REJ = 0x10, 3577 LSM6DSO32X_FALSE_STEP_REJ_ADV_MODE = 0x30, 3578 } lsm6dso32x_pedo_md_t; 3579 int32_t lsm6dso32x_pedo_sens_set(stmdev_ctx_t *ctx, 3580 lsm6dso32x_pedo_md_t val); 3581 int32_t lsm6dso32x_pedo_sens_get(stmdev_ctx_t *ctx, 3582 lsm6dso32x_pedo_md_t *val); 3583 3584 int32_t lsm6dso32x_pedo_step_detect_get(stmdev_ctx_t *ctx, 3585 uint8_t *val); 3586 3587 int32_t lsm6dso32x_pedo_debounce_steps_set(stmdev_ctx_t *ctx, 3588 uint8_t *buff); 3589 int32_t lsm6dso32x_pedo_debounce_steps_get(stmdev_ctx_t *ctx, 3590 uint8_t *buff); 3591 3592 int32_t lsm6dso32x_pedo_steps_period_set(stmdev_ctx_t *ctx, 3593 uint16_t val); 3594 int32_t lsm6dso32x_pedo_steps_period_get(stmdev_ctx_t *ctx, 3595 uint16_t *val); 3596 3597 int32_t lsm6dso32x_pedo_adv_detection_set(stmdev_ctx_t *ctx, 3598 uint8_t val); 3599 int32_t lsm6dso32x_pedo_adv_detection_get(stmdev_ctx_t *ctx, 3600 uint8_t *val); 3601 3602 int32_t lsm6dso32x_pedo_false_step_rejection_set(stmdev_ctx_t *ctx, 3603 uint8_t val); 3604 int32_t lsm6dso32x_pedo_false_step_rejection_get(stmdev_ctx_t *ctx, 3605 uint8_t *val); 3606 3607 typedef enum 3608 { 3609 LSM6DSO32X_EVERY_STEP = 0, 3610 LSM6DSO32X_COUNT_OVERFLOW = 1, 3611 } lsm6dso32x_carry_count_en_t; 3612 int32_t lsm6dso32x_pedo_int_mode_set(stmdev_ctx_t *ctx, 3613 lsm6dso32x_carry_count_en_t val); 3614 int32_t lsm6dso32x_pedo_int_mode_get(stmdev_ctx_t *ctx, 3615 lsm6dso32x_carry_count_en_t *val); 3616 3617 int32_t lsm6dso32x_motion_flag_data_ready_get(stmdev_ctx_t *ctx, 3618 uint8_t *val); 3619 3620 int32_t lsm6dso32x_tilt_flag_data_ready_get(stmdev_ctx_t *ctx, 3621 uint8_t *val); 3622 3623 int32_t lsm6dso32x_sh_mag_sensitivity_set(stmdev_ctx_t *ctx, 3624 uint16_t val); 3625 int32_t lsm6dso32x_sh_mag_sensitivity_get(stmdev_ctx_t *ctx, 3626 uint16_t *val); 3627 3628 int32_t lsm6dso32x_mlc_mag_sensitivity_set(stmdev_ctx_t *ctx, 3629 uint16_t val); 3630 int32_t lsm6dso32x_mlc_mag_sensitivity_get(stmdev_ctx_t *ctx, 3631 uint16_t *val); 3632 3633 int32_t lsm6dso32x_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val); 3634 int32_t lsm6dso32x_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val); 3635 3636 int32_t lsm6dso32x_mag_soft_iron_set(stmdev_ctx_t *ctx, 3637 uint16_t *val); 3638 int32_t lsm6dso32x_mag_soft_iron_get(stmdev_ctx_t *ctx, 3639 uint16_t *val); 3640 3641 typedef enum 3642 { 3643 LSM6DSO32X_Z_EQ_Y = 0, 3644 LSM6DSO32X_Z_EQ_MIN_Y = 1, 3645 LSM6DSO32X_Z_EQ_X = 2, 3646 LSM6DSO32X_Z_EQ_MIN_X = 3, 3647 LSM6DSO32X_Z_EQ_MIN_Z = 4, 3648 LSM6DSO32X_Z_EQ_Z = 5, 3649 } lsm6dso32x_mag_z_axis_t; 3650 int32_t lsm6dso32x_mag_z_orient_set(stmdev_ctx_t *ctx, 3651 lsm6dso32x_mag_z_axis_t val); 3652 int32_t lsm6dso32x_mag_z_orient_get(stmdev_ctx_t *ctx, 3653 lsm6dso32x_mag_z_axis_t *val); 3654 3655 typedef enum 3656 { 3657 LSM6DSO32X_Y_EQ_Y = 0, 3658 LSM6DSO32X_Y_EQ_MIN_Y = 1, 3659 LSM6DSO32X_Y_EQ_X = 2, 3660 LSM6DSO32X_Y_EQ_MIN_X = 3, 3661 LSM6DSO32X_Y_EQ_MIN_Z = 4, 3662 LSM6DSO32X_Y_EQ_Z = 5, 3663 } lsm6dso32x_mag_y_axis_t; 3664 int32_t lsm6dso32x_mag_y_orient_set(stmdev_ctx_t *ctx, 3665 lsm6dso32x_mag_y_axis_t val); 3666 int32_t lsm6dso32x_mag_y_orient_get(stmdev_ctx_t *ctx, 3667 lsm6dso32x_mag_y_axis_t *val); 3668 3669 typedef enum 3670 { 3671 LSM6DSO32X_X_EQ_Y = 0, 3672 LSM6DSO32X_X_EQ_MIN_Y = 1, 3673 LSM6DSO32X_X_EQ_X = 2, 3674 LSM6DSO32X_X_EQ_MIN_X = 3, 3675 LSM6DSO32X_X_EQ_MIN_Z = 4, 3676 LSM6DSO32X_X_EQ_Z = 5, 3677 } lsm6dso32x_mag_x_axis_t; 3678 int32_t lsm6dso32x_mag_x_orient_set(stmdev_ctx_t *ctx, 3679 lsm6dso32x_mag_x_axis_t val); 3680 int32_t lsm6dso32x_mag_x_orient_get(stmdev_ctx_t *ctx, 3681 lsm6dso32x_mag_x_axis_t *val); 3682 3683 int32_t lsm6dso32x_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, 3684 uint8_t *val); 3685 3686 typedef struct 3687 { 3688 lsm6dso32x_fsm_enable_a_t fsm_enable_a; 3689 lsm6dso32x_fsm_enable_b_t fsm_enable_b; 3690 } lsm6dso32x_emb_fsm_enable_t; 3691 int32_t lsm6dso32x_fsm_enable_set(stmdev_ctx_t *ctx, 3692 lsm6dso32x_emb_fsm_enable_t *val); 3693 int32_t lsm6dso32x_fsm_enable_get(stmdev_ctx_t *ctx, 3694 lsm6dso32x_emb_fsm_enable_t *val); 3695 3696 int32_t lsm6dso32x_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val); 3697 int32_t lsm6dso32x_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val); 3698 3699 typedef enum 3700 { 3701 LSM6DSO32X_LC_NORMAL = 0, 3702 LSM6DSO32X_LC_CLEAR = 1, 3703 LSM6DSO32X_LC_CLEAR_DONE = 2, 3704 } lsm6dso32x_fsm_lc_clr_t; 3705 int32_t lsm6dso32x_long_clr_set(stmdev_ctx_t *ctx, 3706 lsm6dso32x_fsm_lc_clr_t val); 3707 int32_t lsm6dso32x_long_clr_get(stmdev_ctx_t *ctx, 3708 lsm6dso32x_fsm_lc_clr_t *val); 3709 3710 typedef struct 3711 { 3712 lsm6dso32x_fsm_outs1_t fsm_outs1; 3713 lsm6dso32x_fsm_outs2_t fsm_outs2; 3714 lsm6dso32x_fsm_outs3_t fsm_outs3; 3715 lsm6dso32x_fsm_outs4_t fsm_outs4; 3716 lsm6dso32x_fsm_outs5_t fsm_outs5; 3717 lsm6dso32x_fsm_outs6_t fsm_outs6; 3718 lsm6dso32x_fsm_outs7_t fsm_outs7; 3719 lsm6dso32x_fsm_outs8_t fsm_outs8; 3720 lsm6dso32x_fsm_outs1_t fsm_outs9; 3721 lsm6dso32x_fsm_outs2_t fsm_outs10; 3722 lsm6dso32x_fsm_outs3_t fsm_outs11; 3723 lsm6dso32x_fsm_outs4_t fsm_outs12; 3724 lsm6dso32x_fsm_outs5_t fsm_outs13; 3725 lsm6dso32x_fsm_outs6_t fsm_outs14; 3726 lsm6dso32x_fsm_outs7_t fsm_outs15; 3727 lsm6dso32x_fsm_outs8_t fsm_outs16; 3728 } lsm6dso32x_fsm_out_t; 3729 int32_t lsm6dso32x_fsm_out_get(stmdev_ctx_t *ctx, 3730 lsm6dso32x_fsm_out_t *val); 3731 3732 typedef enum 3733 { 3734 LSM6DSO32X_ODR_FSM_12Hz5 = 0, 3735 LSM6DSO32X_ODR_FSM_26Hz = 1, 3736 LSM6DSO32X_ODR_FSM_52Hz = 2, 3737 LSM6DSO32X_ODR_FSM_104Hz = 3, 3738 } lsm6dso32x_fsm_odr_t; 3739 int32_t lsm6dso32x_fsm_data_rate_set(stmdev_ctx_t *ctx, 3740 lsm6dso32x_fsm_odr_t val); 3741 int32_t lsm6dso32x_fsm_data_rate_get(stmdev_ctx_t *ctx, 3742 lsm6dso32x_fsm_odr_t *val); 3743 3744 int32_t lsm6dso32x_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val); 3745 int32_t lsm6dso32x_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val); 3746 3747 int32_t lsm6dso32x_long_cnt_int_value_set(stmdev_ctx_t *ctx, 3748 uint16_t val); 3749 int32_t lsm6dso32x_long_cnt_int_value_get(stmdev_ctx_t *ctx, 3750 uint16_t *val); 3751 3752 int32_t lsm6dso32x_fsm_number_of_programs_set(stmdev_ctx_t *ctx, 3753 uint8_t val); 3754 int32_t lsm6dso32x_fsm_number_of_programs_get(stmdev_ctx_t *ctx, 3755 uint8_t *val); 3756 3757 int32_t lsm6dso32x_fsm_start_address_set(stmdev_ctx_t *ctx, 3758 uint16_t val); 3759 int32_t lsm6dso32x_fsm_start_address_get(stmdev_ctx_t *ctx, 3760 uint16_t *val); 3761 3762 int32_t lsm6dso32x_mlc_status_get(stmdev_ctx_t *ctx, 3763 lsm6dso32x_mlc_status_mainpage_t *val); 3764 3765 typedef enum 3766 { 3767 LSM6DSO32X_ODR_PRGS_12Hz5 = 0, 3768 LSM6DSO32X_ODR_PRGS_26Hz = 1, 3769 LSM6DSO32X_ODR_PRGS_52Hz = 2, 3770 LSM6DSO32X_ODR_PRGS_104Hz = 3, 3771 } lsm6dso32x_mlc_odr_t; 3772 int32_t lsm6dso32x_mlc_data_rate_set(stmdev_ctx_t *ctx, 3773 lsm6dso32x_mlc_odr_t val); 3774 int32_t lsm6dso32x_mlc_data_rate_get(stmdev_ctx_t *ctx, 3775 lsm6dso32x_mlc_odr_t *val); 3776 3777 typedef struct 3778 { 3779 lsm6dso32x_sensor_hub_1_t sh_byte_1; 3780 lsm6dso32x_sensor_hub_2_t sh_byte_2; 3781 lsm6dso32x_sensor_hub_3_t sh_byte_3; 3782 lsm6dso32x_sensor_hub_4_t sh_byte_4; 3783 lsm6dso32x_sensor_hub_5_t sh_byte_5; 3784 lsm6dso32x_sensor_hub_6_t sh_byte_6; 3785 lsm6dso32x_sensor_hub_7_t sh_byte_7; 3786 lsm6dso32x_sensor_hub_8_t sh_byte_8; 3787 lsm6dso32x_sensor_hub_9_t sh_byte_9; 3788 lsm6dso32x_sensor_hub_10_t sh_byte_10; 3789 lsm6dso32x_sensor_hub_11_t sh_byte_11; 3790 lsm6dso32x_sensor_hub_12_t sh_byte_12; 3791 lsm6dso32x_sensor_hub_13_t sh_byte_13; 3792 lsm6dso32x_sensor_hub_14_t sh_byte_14; 3793 lsm6dso32x_sensor_hub_15_t sh_byte_15; 3794 lsm6dso32x_sensor_hub_16_t sh_byte_16; 3795 lsm6dso32x_sensor_hub_17_t sh_byte_17; 3796 lsm6dso32x_sensor_hub_18_t sh_byte_18; 3797 } lsm6dso32x_emb_sh_read_t; 3798 int32_t lsm6dso32x_sh_read_data_raw_get(stmdev_ctx_t *ctx, 3799 lsm6dso32x_emb_sh_read_t *val, 3800 uint8_t len); 3801 3802 typedef enum 3803 { 3804 LSM6DSO32X_SLV_0 = 0, 3805 LSM6DSO32X_SLV_0_1 = 1, 3806 LSM6DSO32X_SLV_0_1_2 = 2, 3807 LSM6DSO32X_SLV_0_1_2_3 = 3, 3808 } lsm6dso32x_aux_sens_on_t; 3809 int32_t lsm6dso32x_sh_slave_connected_set(stmdev_ctx_t *ctx, 3810 lsm6dso32x_aux_sens_on_t val); 3811 int32_t lsm6dso32x_sh_slave_connected_get(stmdev_ctx_t *ctx, 3812 lsm6dso32x_aux_sens_on_t *val); 3813 3814 int32_t lsm6dso32x_sh_master_set(stmdev_ctx_t *ctx, uint8_t val); 3815 int32_t lsm6dso32x_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val); 3816 3817 typedef enum 3818 { 3819 LSM6DSO32X_EXT_PULL_UP = 0, 3820 LSM6DSO32X_INTERNAL_PULL_UP = 1, 3821 } lsm6dso32x_shub_pu_en_t; 3822 int32_t lsm6dso32x_sh_pin_mode_set(stmdev_ctx_t *ctx, 3823 lsm6dso32x_shub_pu_en_t val); 3824 int32_t lsm6dso32x_sh_pin_mode_get(stmdev_ctx_t *ctx, 3825 lsm6dso32x_shub_pu_en_t *val); 3826 3827 int32_t lsm6dso32x_sh_pass_through_set(stmdev_ctx_t *ctx, 3828 uint8_t val); 3829 int32_t lsm6dso32x_sh_pass_through_get(stmdev_ctx_t *ctx, 3830 uint8_t *val); 3831 3832 typedef enum 3833 { 3834 LSM6DSO32X_EXT_ON_INT2_PIN = 1, 3835 LSM6DSO32X_XL_GY_DRDY = 0, 3836 } lsm6dso32x_start_config_t; 3837 int32_t lsm6dso32x_sh_syncro_mode_set(stmdev_ctx_t *ctx, 3838 lsm6dso32x_start_config_t val); 3839 int32_t lsm6dso32x_sh_syncro_mode_get(stmdev_ctx_t *ctx, 3840 lsm6dso32x_start_config_t *val); 3841 3842 typedef enum 3843 { 3844 LSM6DSO32X_EACH_SH_CYCLE = 0, 3845 LSM6DSO32X_ONLY_FIRST_CYCLE = 1, 3846 } lsm6dso32x_write_once_t; 3847 int32_t lsm6dso32x_sh_write_mode_set(stmdev_ctx_t *ctx, 3848 lsm6dso32x_write_once_t val); 3849 int32_t lsm6dso32x_sh_write_mode_get(stmdev_ctx_t *ctx, 3850 lsm6dso32x_write_once_t *val); 3851 3852 int32_t lsm6dso32x_sh_reset_set(stmdev_ctx_t *ctx); 3853 int32_t lsm6dso32x_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val); 3854 3855 typedef enum 3856 { 3857 LSM6DSO32X_SH_ODR_104Hz = 0, 3858 LSM6DSO32X_SH_ODR_52Hz = 1, 3859 LSM6DSO32X_SH_ODR_26Hz = 2, 3860 LSM6DSO32X_SH_ODR_13Hz = 3, 3861 } lsm6dso32x_shub_odr_t; 3862 int32_t lsm6dso32x_sh_data_rate_set(stmdev_ctx_t *ctx, 3863 lsm6dso32x_shub_odr_t val); 3864 int32_t lsm6dso32x_sh_data_rate_get(stmdev_ctx_t *ctx, 3865 lsm6dso32x_shub_odr_t *val); 3866 3867 typedef struct 3868 { 3869 uint8_t slv0_add; 3870 uint8_t slv0_subadd; 3871 uint8_t slv0_data; 3872 } lsm6dso32x_sh_cfg_write_t; 3873 int32_t lsm6dso32x_sh_cfg_write(stmdev_ctx_t *ctx, 3874 lsm6dso32x_sh_cfg_write_t *val); 3875 3876 typedef struct 3877 { 3878 uint8_t slv_add; 3879 uint8_t slv_subadd; 3880 uint8_t slv_len; 3881 } lsm6dso32x_sh_cfg_read_t; 3882 int32_t lsm6dso32x_sh_slv0_cfg_read(stmdev_ctx_t *ctx, 3883 lsm6dso32x_sh_cfg_read_t *val); 3884 int32_t lsm6dso32x_sh_slv1_cfg_read(stmdev_ctx_t *ctx, 3885 lsm6dso32x_sh_cfg_read_t *val); 3886 int32_t lsm6dso32x_sh_slv2_cfg_read(stmdev_ctx_t *ctx, 3887 lsm6dso32x_sh_cfg_read_t *val); 3888 int32_t lsm6dso32x_sh_slv3_cfg_read(stmdev_ctx_t *ctx, 3889 lsm6dso32x_sh_cfg_read_t *val); 3890 3891 int32_t lsm6dso32x_sh_status_get(stmdev_ctx_t *ctx, 3892 lsm6dso32x_status_master_t *val); 3893 typedef struct 3894 { 3895 uint8_t ui; 3896 uint8_t aux; 3897 } lsm6dso32x_id_t; 3898 int32_t lsm6dso32x_id_get(stmdev_ctx_t *ctx, 3899 lsm6dso32x_id_t *val); 3900 3901 typedef struct 3902 { 3903 enum 3904 { 3905 LSM6DSO32X_SEL_BY_HW = 0x00, /* bus mode select by HW (SPI 3W disable) */ 3906 LSM6DSO32X_SPI_4W = 0x06, /* Only SPI: SDO / SDI separated pins */ 3907 LSM6DSO32X_SPI_3W = 0x07, /* Only SPI: SDO / SDI share the same pin */ 3908 LSM6DSO32X_I2C = 0x04, /* Only I2C */ 3909 LSM6DSO32X_I3C_T_50us = 0x02, /* I3C: available time equal to 50 μs */ 3910 LSM6DSO32X_I3C_T_2us = 0x12, /* I3C: available time equal to 2 μs */ 3911 LSM6DSO32X_I3C_T_1ms = 0x22, /* I3C: available time equal to 1 ms */ 3912 LSM6DSO32X_I3C_T_25ms = 0x32, /* I3C: available time equal to 25 ms */ 3913 } ui_bus_md; 3914 enum 3915 { 3916 LSM6DSO32X_SPI_4W_AUX = 0x00, 3917 LSM6DSO32X_SPI_3W_AUX = 0x01, 3918 } aux_bus_md; 3919 } lsm6dso32x_bus_mode_t; 3920 int32_t lsm6dso32x_bus_mode_set(stmdev_ctx_t *ctx, 3921 lsm6dso32x_bus_mode_t val); 3922 int32_t lsm6dso32x_bus_mode_get(stmdev_ctx_t *ctx, 3923 lsm6dso32x_bus_mode_t *val); 3924 3925 typedef enum 3926 { 3927 LSM6DSO32X_DRV_RDY = 0x00, /* Initialize the device for driver usage */ 3928 LSM6DSO32X_BOOT = 0x01, /* Restore calib. param. ( it takes 10ms ) */ 3929 LSM6DSO32X_RESET = 0x02, /* Reset configuration registers */ 3930 LSM6DSO32X_FIFO_COMP = 0x04, /* FIFO compression initialization request. */ 3931 LSM6DSO32X_FSM = 0x08, /* Finite State Machine initialization request */ 3932 LSM6DSO32X_MLC = 0x10, /* Machine Learning Core initialization request */ 3933 LSM6DSO32X_PEDO = 0x20, /* Pedometer algo initialization request. */ 3934 LSM6DSO32X_TILT = 0x40, /* Tilt algo initialization request */ 3935 LSM6DSO32X_SMOTION = 0x80, /* Significant Motion initialization request */ 3936 } lsm6dso32x_init_t; 3937 int32_t lsm6dso32x_init_set(stmdev_ctx_t *ctx, lsm6dso32x_init_t val); 3938 3939 typedef struct 3940 { 3941 uint8_t sw_reset : 3942 1; /* Restoring configuration registers */ 3943 uint8_t boot : 1; /* Restoring calibration parameters */ 3944 uint8_t drdy_xl : 1; /* Accelerometer data ready */ 3945 uint8_t drdy_g : 1; /* Gyroscope data ready */ 3946 uint8_t drdy_temp : 1; /* Temperature data ready */ 3947 } lsm6dso32x_status_t; 3948 int32_t lsm6dso32x_status_get(stmdev_ctx_t *ctx, 3949 lsm6dso32x_status_t *val); 3950 3951 typedef struct 3952 { 3953 uint8_t sdo_sa0_pull_up : 1; /* 1 = pull-up on SDO/SA0 pin */ 3954 uint8_t aux_sdo_ocs_pull_up : 3955 1; /* 1 = pull-up on OCS_Aux/SDO_Aux pins */ 3956 uint8_t int1_int2_push_pull : 1; /* 1 = push-pull / 0 = open-drain*/ 3957 uint8_t int1_pull_down : 3958 1; /* 1 = pull-down always disabled (0=auto) */ 3959 } lsm6dso32x_pin_conf_t; 3960 int32_t lsm6dso32x_pin_conf_set(stmdev_ctx_t *ctx, 3961 lsm6dso32x_pin_conf_t val); 3962 int32_t lsm6dso32x_pin_conf_get(stmdev_ctx_t *ctx, 3963 lsm6dso32x_pin_conf_t *val); 3964 3965 typedef struct 3966 { 3967 uint8_t active_low : 1; /* 1 = active low / 0 = active high */ 3968 uint8_t base_latched : 3969 1; /* base functions are: FF, WU, 6D, Tap, Act/Inac */ 3970 uint8_t emb_latched : 3971 1; /* emb functions are: Pedo, Tilt, SMot, Timestamp */ 3972 } lsm6dso32x_int_mode_t; 3973 int32_t lsm6dso32x_interrupt_mode_set(stmdev_ctx_t *ctx, 3974 lsm6dso32x_int_mode_t val); 3975 int32_t lsm6dso32x_interrupt_mode_get(stmdev_ctx_t *ctx, 3976 lsm6dso32x_int_mode_t *val); 3977 3978 typedef struct 3979 { 3980 uint8_t drdy_xl : 1; /* Accelerometer data ready */ 3981 uint8_t drdy_g : 1; /* Gyroscope data ready */ 3982 uint8_t drdy_temp : 3983 1; /* Temperature data ready (1 = int2 pin disable) */ 3984 uint8_t boot : 1; /* Restoring calibration parameters */ 3985 uint8_t fifo_th : 1; /* FIFO threshold reached */ 3986 uint8_t fifo_ovr : 1; /* FIFO overrun */ 3987 uint8_t fifo_full : 1; /* FIFO full */ 3988 uint8_t fifo_bdr : 1; /* FIFO Batch counter threshold reached */ 3989 uint8_t den_flag : 3990 1; /* external trigger level recognition (DEN) */ 3991 uint8_t sh_endop : 1; /* sensor hub end operation */ 3992 uint8_t timestamp : 3993 1; /* timestamp overflow (1 = int2 pin disable) */ 3994 uint8_t six_d : 1; /* orientation change (6D/4D detection) */ 3995 uint8_t double_tap : 1; /* double-tap event */ 3996 uint8_t free_fall : 1; /* free fall event */ 3997 uint8_t wake_up : 1; /* wake up event */ 3998 uint8_t single_tap : 1; /* single-tap event */ 3999 uint8_t sleep_change : 4000 1; /* Act/Inact (or Vice-versa) status changed */ 4001 uint8_t step_detector : 1; /* Step detected */ 4002 uint8_t tilt : 1; /* Relative tilt event detected */ 4003 uint8_t sig_mot : 1; /* "significant motion" event detected */ 4004 uint8_t fsm_lc : 4005 1; /* fsm long counter timeout interrupt event */ 4006 uint8_t fsm1 : 1; /* fsm 1 interrupt event */ 4007 uint8_t fsm2 : 1; /* fsm 2 interrupt event */ 4008 uint8_t fsm3 : 1; /* fsm 3 interrupt event */ 4009 uint8_t fsm4 : 1; /* fsm 4 interrupt event */ 4010 uint8_t fsm5 : 1; /* fsm 5 interrupt event */ 4011 uint8_t fsm6 : 1; /* fsm 6 interrupt event */ 4012 uint8_t fsm7 : 1; /* fsm 7 interrupt event */ 4013 uint8_t fsm8 : 1; /* fsm 8 interrupt event */ 4014 uint8_t fsm9 : 1; /* fsm 9 interrupt event */ 4015 uint8_t fsm10 : 1; /* fsm 10 interrupt event */ 4016 uint8_t fsm11 : 1; /* fsm 11 interrupt event */ 4017 uint8_t fsm12 : 1; /* fsm 12 interrupt event */ 4018 uint8_t fsm13 : 1; /* fsm 13 interrupt event */ 4019 uint8_t fsm14 : 1; /* fsm 14 interrupt event */ 4020 uint8_t fsm15 : 1; /* fsm 15 interrupt event */ 4021 uint8_t fsm16 : 1; /* fsm 16 interrupt event */ 4022 uint8_t mlc1 : 1; /* mlc 1 interrupt event */ 4023 uint8_t mlc2 : 1; /* mlc 2 interrupt event */ 4024 uint8_t mlc3 : 1; /* mlc 3 interrupt event */ 4025 uint8_t mlc4 : 1; /* mlc 4 interrupt event */ 4026 uint8_t mlc5 : 1; /* mlc 5 interrupt event */ 4027 uint8_t mlc6 : 1; /* mlc 6 interrupt event */ 4028 uint8_t mlc7 : 1; /* mlc 7 interrupt event */ 4029 uint8_t mlc8 : 1; /* mlc 8 interrupt event */ 4030 } lsm6dso32x_pin_int1_route_t; 4031 4032 int32_t lsm6dso32x_pin_int1_route_set(stmdev_ctx_t *ctx, 4033 lsm6dso32x_pin_int1_route_t val); 4034 int32_t lsm6dso32x_pin_int1_route_get(stmdev_ctx_t *ctx, 4035 lsm6dso32x_pin_int1_route_t *val); 4036 4037 typedef struct 4038 { 4039 uint8_t drdy_xl : 1; /* Accelerometer data ready */ 4040 uint8_t drdy_g : 1; /* Gyroscope data ready */ 4041 uint8_t drdy_temp : 1; /* Temperature data ready */ 4042 uint8_t fifo_th : 1; /* FIFO threshold reached */ 4043 uint8_t fifo_ovr : 1; /* FIFO overrun */ 4044 uint8_t fifo_full : 1; /* FIFO full */ 4045 uint8_t fifo_bdr : 1; /* FIFO Batch counter threshold reached */ 4046 uint8_t timestamp : 1; /* timestamp overflow */ 4047 uint8_t six_d : 1; /* orientation change (6D/4D detection) */ 4048 uint8_t double_tap : 1; /* double-tap event */ 4049 uint8_t free_fall : 1; /* free fall event */ 4050 uint8_t wake_up : 1; /* wake up event */ 4051 uint8_t single_tap : 1; /* single-tap event */ 4052 uint8_t sleep_change : 4053 1; /* Act/Inact (or Vice-versa) status changed */ 4054 uint8_t step_detector : 1; /* Step detected */ 4055 uint8_t tilt : 1; /* Relative tilt event detected */ 4056 uint8_t sig_mot : 1; /* "significant motion" event detected */ 4057 uint8_t fsm_lc : 4058 1; /* fsm long counter timeout interrupt event */ 4059 uint8_t fsm1 : 1; /* fsm 1 interrupt event */ 4060 uint8_t fsm2 : 1; /* fsm 2 interrupt event */ 4061 uint8_t fsm3 : 1; /* fsm 3 interrupt event */ 4062 uint8_t fsm4 : 1; /* fsm 4 interrupt event */ 4063 uint8_t fsm5 : 1; /* fsm 5 interrupt event */ 4064 uint8_t fsm6 : 1; /* fsm 6 interrupt event */ 4065 uint8_t fsm7 : 1; /* fsm 7 interrupt event */ 4066 uint8_t fsm8 : 1; /* fsm 8 interrupt event */ 4067 uint8_t fsm9 : 1; /* fsm 9 interrupt event */ 4068 uint8_t fsm10 : 1; /* fsm 10 interrupt event */ 4069 uint8_t fsm11 : 1; /* fsm 11 interrupt event */ 4070 uint8_t fsm12 : 1; /* fsm 12 interrupt event */ 4071 uint8_t fsm13 : 1; /* fsm 13 interrupt event */ 4072 uint8_t fsm14 : 1; /* fsm 14 interrupt event */ 4073 uint8_t fsm15 : 1; /* fsm 15 interrupt event */ 4074 uint8_t fsm16 : 1; /* fsm 16 interrupt event */ 4075 uint8_t mlc1 : 1; /* mlc 1 interrupt event */ 4076 uint8_t mlc2 : 1; /* mlc 2 interrupt event */ 4077 uint8_t mlc3 : 1; /* mlc 3 interrupt event */ 4078 uint8_t mlc4 : 1; /* mlc 4 interrupt event */ 4079 uint8_t mlc5 : 1; /* mlc 5 interrupt event */ 4080 uint8_t mlc6 : 1; /* mlc 6 interrupt event */ 4081 uint8_t mlc7 : 1; /* mlc 7 interrupt event */ 4082 uint8_t mlc8 : 1; /* mlc 8 interrupt event */ 4083 } lsm6dso32x_pin_int2_route_t; 4084 4085 int32_t lsm6dso32x_pin_int2_route_set(stmdev_ctx_t *ctx, 4086 lsm6dso32x_pin_int2_route_t val); 4087 int32_t lsm6dso32x_pin_int2_route_get(stmdev_ctx_t *ctx, 4088 lsm6dso32x_pin_int2_route_t *val); 4089 4090 typedef struct 4091 { 4092 uint8_t drdy_xl : 1; /* Accelerometer data ready */ 4093 uint8_t drdy_g : 1; /* Gyroscope data ready */ 4094 uint8_t drdy_temp : 1; /* Temperature data ready */ 4095 uint8_t den_flag : 4096 1; /* external trigger level recognition (DEN) */ 4097 uint8_t timestamp : 4098 1; /* timestamp overflow (1 = int2 pin disable) */ 4099 uint8_t free_fall : 1; /* free fall event */ 4100 uint8_t wake_up : 1; /* wake up event */ 4101 uint8_t wake_up_z : 1; /* wake up on Z axis event */ 4102 uint8_t wake_up_y : 1; /* wake up on Y axis event */ 4103 uint8_t wake_up_x : 1; /* wake up on X axis event */ 4104 uint8_t single_tap : 1; /* single-tap event */ 4105 uint8_t double_tap : 1; /* double-tap event */ 4106 uint8_t tap_z : 1; /* single-tap on Z axis event */ 4107 uint8_t tap_y : 1; /* single-tap on Y axis event */ 4108 uint8_t tap_x : 1; /* single-tap on X axis event */ 4109 uint8_t tap_sign : 1; /* sign of tap event (0-pos / 1-neg) */ 4110 uint8_t six_d : 4111 1; /* orientation change (6D/4D detection) */ 4112 uint8_t six_d_xl : 4113 1; /* X-axis low 6D/4D event (under threshold) */ 4114 uint8_t six_d_xh : 4115 1; /* X-axis high 6D/4D event (over threshold) */ 4116 uint8_t six_d_yl : 4117 1; /* Y-axis low 6D/4D event (under threshold) */ 4118 uint8_t six_d_yh : 4119 1; /* Y-axis high 6D/4D event (over threshold) */ 4120 uint8_t six_d_zl : 4121 1; /* Z-axis low 6D/4D event (under threshold) */ 4122 uint8_t six_d_zh : 4123 1; /* Z-axis high 6D/4D event (over threshold) */ 4124 uint8_t sleep_change : 4125 1; /* Act/Inact (or Vice-versa) status changed */ 4126 uint8_t sleep_state : 4127 1; /* Act/Inact status flag (0-Act / 1-Inact) */ 4128 uint8_t step_detector : 1; /* Step detected */ 4129 uint8_t tilt : 1; /* Relative tilt event detected */ 4130 uint8_t sig_mot : 4131 1; /* "significant motion" event detected */ 4132 uint8_t fsm_lc : 4133 1; /* fsm long counter timeout interrupt event */ 4134 uint8_t fsm1 : 1; /* fsm 1 interrupt event */ 4135 uint8_t fsm2 : 1; /* fsm 2 interrupt event */ 4136 uint8_t fsm3 : 1; /* fsm 3 interrupt event */ 4137 uint8_t fsm4 : 1; /* fsm 4 interrupt event */ 4138 uint8_t fsm5 : 1; /* fsm 5 interrupt event */ 4139 uint8_t fsm6 : 1; /* fsm 6 interrupt event */ 4140 uint8_t fsm7 : 1; /* fsm 7 interrupt event */ 4141 uint8_t fsm8 : 1; /* fsm 8 interrupt event */ 4142 uint8_t fsm9 : 1; /* fsm 9 interrupt event */ 4143 uint8_t fsm10 : 1; /* fsm 10 interrupt event */ 4144 uint8_t fsm11 : 1; /* fsm 11 interrupt event */ 4145 uint8_t fsm12 : 1; /* fsm 12 interrupt event */ 4146 uint8_t fsm13 : 1; /* fsm 13 interrupt event */ 4147 uint8_t fsm14 : 1; /* fsm 14 interrupt event */ 4148 uint8_t fsm15 : 1; /* fsm 15 interrupt event */ 4149 uint8_t fsm16 : 1; /* fsm 16 interrupt event */ 4150 uint8_t mlc1 : 1; /* mlc 1 interrupt event */ 4151 uint8_t mlc2 : 1; /* mlc 2 interrupt event */ 4152 uint8_t mlc3 : 1; /* mlc 3 interrupt event */ 4153 uint8_t mlc4 : 1; /* mlc 4 interrupt event */ 4154 uint8_t mlc5 : 1; /* mlc 5 interrupt event */ 4155 uint8_t mlc6 : 1; /* mlc 6 interrupt event */ 4156 uint8_t mlc7 : 1; /* mlc 7 interrupt event */ 4157 uint8_t mlc8 : 1; /* mlc 8 interrupt event */ 4158 uint8_t sh_endop : 1; /* sensor hub end operation */ 4159 uint8_t sh_slave0_nack : 4160 1; /* Not acknowledge on sensor hub slave 0 */ 4161 uint8_t sh_slave1_nack : 4162 1; /* Not acknowledge on sensor hub slave 1 */ 4163 uint8_t sh_slave2_nack : 4164 1; /* Not acknowledge on sensor hub slave 2 */ 4165 uint8_t sh_slave3_nack : 4166 1; /* Not acknowledge on sensor hub slave 3 */ 4167 uint8_t sh_wr_once : 4168 1; /* "WRITE_ONCE" end on sensor hub slave 0 */ 4169 uint16_t fifo_diff : 4170 10; /* Number of unread sensor data in FIFO*/ 4171 uint8_t fifo_ovr_latched : 1; /* Latched FIFO overrun status */ 4172 uint8_t fifo_bdr : 4173 1; /* FIFO Batch counter threshold reached */ 4174 uint8_t fifo_full : 1; /* FIFO full */ 4175 uint8_t fifo_ovr : 1; /* FIFO overrun */ 4176 uint8_t fifo_th : 1; /* FIFO threshold reached */ 4177 } lsm6dso32x_all_sources_t; 4178 int32_t lsm6dso32x_all_sources_get(stmdev_ctx_t *ctx, 4179 lsm6dso32x_all_sources_t *val); 4180 4181 typedef struct 4182 { 4183 uint8_t odr_fine_tune; 4184 } lsm6dso32x_dev_cal_t; 4185 int32_t lsm6dso32x_calibration_get(stmdev_ctx_t *ctx, 4186 lsm6dso32x_dev_cal_t *val); 4187 4188 typedef struct 4189 { 4190 struct 4191 { 4192 struct 4193 { 4194 enum 4195 { 4196 LSM6DSO32X_XL_UI_OFF = 0x00, /* in power down */ 4197 LSM6DSO32X_XL_UI_1Hz6_LP = 0x1B, /* @1Hz6 (low power) */ 4198 LSM6DSO32X_XL_UI_1Hz6_ULP = 0x2B, /* @1Hz6 (ultra low/Gy) */ 4199 LSM6DSO32X_XL_UI_12Hz5_HP = 0x01, /* @12Hz5 (high performance) */ 4200 LSM6DSO32X_XL_UI_12Hz5_LP = 0x11, /* @12Hz5 (low power) */ 4201 LSM6DSO32X_XL_UI_12Hz5_ULP = 0x21, /* @12Hz5 (ultra low/Gy) */ 4202 LSM6DSO32X_XL_UI_26Hz_HP = 0x02, /* @26Hz (high performance) */ 4203 LSM6DSO32X_XL_UI_26Hz_LP = 0x12, /* @26Hz (low power) */ 4204 LSM6DSO32X_XL_UI_26Hz_ULP = 0x22, /* @26Hz (ultra low/Gy) */ 4205 LSM6DSO32X_XL_UI_52Hz_HP = 0x03, /* @52Hz (high performance) */ 4206 LSM6DSO32X_XL_UI_52Hz_LP = 0x13, /* @52Hz (low power) */ 4207 LSM6DSO32X_XL_UI_52Hz_ULP = 0x23, /* @52Hz (ultra low/Gy) */ 4208 LSM6DSO32X_XL_UI_104Hz_HP = 0x04, /* @104Hz (high performance) */ 4209 LSM6DSO32X_XL_UI_104Hz_NM = 0x14, /* @104Hz (normal mode) */ 4210 LSM6DSO32X_XL_UI_104Hz_ULP = 0x24, /* @104Hz (ultra low/Gy) */ 4211 LSM6DSO32X_XL_UI_208Hz_HP = 0x05, /* @208Hz (high performance) */ 4212 LSM6DSO32X_XL_UI_208Hz_NM = 0x15, /* @208Hz (normal mode) */ 4213 LSM6DSO32X_XL_UI_208Hz_ULP = 0x25, /* @208Hz (ultra low/Gy) */ 4214 LSM6DSO32X_XL_UI_416Hz_HP = 0x06, /* @416Hz (high performance) */ 4215 LSM6DSO32X_XL_UI_833Hz_HP = 0x07, /* @833Hz (high performance) */ 4216 LSM6DSO32X_XL_UI_1667Hz_HP = 0x08, /* @1kHz66 (high performance) */ 4217 LSM6DSO32X_XL_UI_3333Hz_HP = 0x09, /* @3kHz33 (high performance) */ 4218 LSM6DSO32X_XL_UI_6667Hz_HP = 0x0A, /* @6kHz66 (high performance) */ 4219 } odr; 4220 enum 4221 { 4222 LSM6DSO32X_XL_UI_4g = 0, 4223 LSM6DSO32X_XL_UI_32g = 1, 4224 LSM6DSO32X_XL_UI_8g = 2, 4225 LSM6DSO32X_XL_UI_16g = 3, 4226 } fs; 4227 } xl; 4228 struct 4229 { 4230 enum 4231 { 4232 LSM6DSO32X_GY_UI_OFF = 0x00, /* gy in power down */ 4233 LSM6DSO32X_GY_UI_12Hz5_LP = 0x11, /* gy @12Hz5 (low power) */ 4234 LSM6DSO32X_GY_UI_12Hz5_HP = 0x01, /* gy @12Hz5 (high performance) */ 4235 LSM6DSO32X_GY_UI_26Hz_LP = 0x12, /* gy @26Hz (low power) */ 4236 LSM6DSO32X_GY_UI_26Hz_HP = 0x02, /* gy @26Hz (high performance) */ 4237 LSM6DSO32X_GY_UI_52Hz_LP = 0x13, /* gy @52Hz (low power) */ 4238 LSM6DSO32X_GY_UI_52Hz_HP = 0x03, /* gy @52Hz (high performance) */ 4239 LSM6DSO32X_GY_UI_104Hz_NM = 0x14, /* gy @104Hz (low power) */ 4240 LSM6DSO32X_GY_UI_104Hz_HP = 0x04, /* gy @104Hz (high performance) */ 4241 LSM6DSO32X_GY_UI_208Hz_NM = 0x15, /* gy @208Hz (low power) */ 4242 LSM6DSO32X_GY_UI_208Hz_HP = 0x05, /* gy @208Hz (high performance) */ 4243 LSM6DSO32X_GY_UI_416Hz_HP = 0x06, /* gy @416Hz (high performance) */ 4244 LSM6DSO32X_GY_UI_833Hz_HP = 0x07, /* gy @833Hz (high performance) */ 4245 LSM6DSO32X_GY_UI_1667Hz_HP = 0x08, /* gy @1kHz66 (high performance) */ 4246 LSM6DSO32X_GY_UI_3333Hz_HP = 0x09, /* gy @3kHz33 (high performance) */ 4247 LSM6DSO32X_GY_UI_6667Hz_HP = 0x0A, /* gy @6kHz66 (high performance) */ 4248 } odr; 4249 enum 4250 { 4251 LSM6DSO32X_GY_UI_250dps = 0, 4252 LSM6DSO32X_GY_UI_125dps = 1, 4253 LSM6DSO32X_GY_UI_500dps = 2, 4254 LSM6DSO32X_GY_UI_1000dps = 4, 4255 LSM6DSO32X_GY_UI_2000dps = 6, 4256 } fs; 4257 } gy; 4258 } ui; 4259 struct 4260 { 4261 enum 4262 { 4263 LSM6DSO32X_FSM_DISABLE = 0x00, 4264 LSM6DSO32X_FSM_XL = 0x01, 4265 LSM6DSO32X_FSM_GY = 0x02, 4266 LSM6DSO32X_FSM_XL_GY = 0x03, 4267 } sens; 4268 enum 4269 { 4270 LSM6DSO32X_FSM_12Hz5 = 0x00, 4271 LSM6DSO32X_FSM_26Hz = 0x01, 4272 LSM6DSO32X_FSM_52Hz = 0x02, 4273 LSM6DSO32X_FSM_104Hz = 0x03, 4274 } odr; 4275 } fsm; 4276 struct 4277 { 4278 enum 4279 { 4280 LSM6DSO32X_MLC_DISABLE = 0x00, 4281 LSM6DSO32X_MLC_XL = 0x01, 4282 LSM6DSO32X_MLC_XL_GY = 0x03, 4283 } sens; 4284 enum 4285 { 4286 LSM6DSO32X_MLC_12Hz5 = 0x00, 4287 LSM6DSO32X_MLC_26Hz = 0x01, 4288 LSM6DSO32X_MLC_52Hz = 0x02, 4289 LSM6DSO32X_MLC_104Hz = 0x03, 4290 } odr; 4291 } mlc; 4292 } lsm6dso32x_md_t; 4293 int32_t lsm6dso32x_mode_set(stmdev_ctx_t *ctx, 4294 lsm6dso32x_md_t *val); 4295 int32_t lsm6dso32x_mode_get(stmdev_ctx_t *ctx, 4296 lsm6dso32x_md_t *val); 4297 4298 typedef struct 4299 { 4300 struct 4301 { 4302 struct 4303 { 4304 float mg[3]; 4305 int16_t raw[3]; 4306 } xl; 4307 struct 4308 { 4309 float mdps[3]; 4310 int16_t raw[3]; 4311 } gy; 4312 struct 4313 { 4314 float deg_c; 4315 int16_t raw; 4316 } heat; 4317 } ui; 4318 } lsm6dso32x_data_t; 4319 int32_t lsm6dso32x_data_get(stmdev_ctx_t *ctx, 4320 lsm6dso32x_md_t *md, 4321 lsm6dso32x_data_t *data); 4322 4323 typedef struct 4324 { 4325 uint8_t sig_mot : 1; /* significant motion */ 4326 uint8_t tilt : 1; /* tilt detection */ 4327 uint8_t step : 1; /* step counter/detector */ 4328 uint8_t mlc : 1; /* machine learning core */ 4329 uint8_t fsm : 1; /* finite state machine */ 4330 uint8_t fifo_compr : 1; /* mlc 8 interrupt event */ 4331 } lsm6dso32x_emb_sens_t; 4332 int32_t lsm6dso32x_embedded_sens_set(stmdev_ctx_t *ctx, 4333 lsm6dso32x_emb_sens_t *emb_sens); 4334 int32_t lsm6dso32x_embedded_sens_get(stmdev_ctx_t *ctx, 4335 lsm6dso32x_emb_sens_t *emb_sens); 4336 int32_t lsm6dso32x_embedded_sens_off(stmdev_ctx_t *ctx); 4337 4338 /** 4339 * @} 4340 * 4341 */ 4342 4343 #ifdef __cplusplus 4344 } 4345 #endif 4346 4347 #endif /*LSM6DSO32X_DRIVER_H */ 4348 4349 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 4350
