1 /** 2 ****************************************************************************** 3 * @file lsm6dso_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * lsm6dso_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef LSM6DSO_REGS_H 23 #define LSM6DSO_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup LSM6DSO 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 /* #define DRV_BYTE_ORDER DRV_BIG_ENDIAN */ 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 #ifndef __weak 128 #define __weak __attribute__((weak)) 129 #endif /* __weak */ 130 131 /* 132 * These are the basic platform dependent I/O routines to read 133 * and write device registers connected on a standard bus. 134 * The driver keeps offering a default implementation based on function 135 * pointers to read/write routines for backward compatibility. 136 * The __weak directive allows the final application to overwrite 137 * them with a custom implementation. 138 */ 139 int32_t lsm6dso_read_reg(stmdev_ctx_t* ctx, uint8_t reg, 140 uint8_t* data, 141 uint16_t len); 142 int32_t lsm6dso_write_reg(stmdev_ctx_t* ctx, uint8_t reg, 143 uint8_t* data, 144 uint16_t len); 145 146 /** 147 * @} 148 * 149 */ 150 151 #endif /* MEMS_SHARED_TYPES */ 152 153 #ifndef MEMS_UCF_SHARED_TYPES 154 #define MEMS_UCF_SHARED_TYPES 155 156 /** @defgroup Generic address-data structure definition 157 * @brief This structure is useful to load a predefined configuration 158 * of a sensor. 159 * You can create a sensor configuration by your own or using 160 * Unico / Unicleo tools available on STMicroelectronics 161 * web site. 162 * 163 * @{ 164 * 165 */ 166 167 typedef struct 168 { 169 uint8_t address; 170 uint8_t data; 171 } ucf_line_t; 172 173 /** 174 * @} 175 * 176 */ 177 178 #endif /* MEMS_UCF_SHARED_TYPES */ 179 180 /** 181 * @} 182 * 183 */ 184 185 /** @defgroup LSM6DSO_Infos 186 * @{ 187 * 188 */ 189 190 /** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ 191 #define LSM6DSO_I2C_ADD_L 0xD5 192 #define LSM6DSO_I2C_ADD_H 0xD7 193 194 /** Device Identification (Who am I) **/ 195 #define LSM6DSO_ID 0x6C 196 197 /** 198 * @} 199 * 200 */ 201 202 #define LSM6DSO_FUNC_CFG_ACCESS 0x01U 203 typedef struct 204 { 205 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 206 uint8_t not_used_01 : 6; 207 uint8_t reg_access : 208 2; /* shub_reg_access + func_cfg_access */ 209 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 210 uint8_t reg_access : 211 2; /* shub_reg_access + func_cfg_access */ 212 uint8_t not_used_01 : 6; 213 #endif /* DRV_BYTE_ORDER */ 214 } lsm6dso_func_cfg_access_t; 215 216 #define LSM6DSO_PIN_CTRL 0x02U 217 typedef struct 218 { 219 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 220 uint8_t not_used_01 : 6; 221 uint8_t sdo_pu_en : 1; 222 uint8_t ois_pu_dis : 1; 223 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 224 uint8_t ois_pu_dis : 1; 225 uint8_t sdo_pu_en : 1; 226 uint8_t not_used_01 : 6; 227 #endif /* DRV_BYTE_ORDER */ 228 } lsm6dso_pin_ctrl_t; 229 230 #define LSM6DSO_FIFO_CTRL1 0x07U 231 typedef struct 232 { 233 uint8_t wtm : 8; 234 } lsm6dso_fifo_ctrl1_t; 235 236 #define LSM6DSO_FIFO_CTRL2 0x08U 237 typedef struct 238 { 239 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 240 uint8_t wtm : 1; 241 uint8_t uncoptr_rate : 2; 242 uint8_t not_used_01 : 1; 243 uint8_t odrchg_en : 1; 244 uint8_t not_used_02 : 1; 245 uint8_t fifo_compr_rt_en : 1; 246 uint8_t stop_on_wtm : 1; 247 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 248 uint8_t stop_on_wtm : 1; 249 uint8_t fifo_compr_rt_en : 1; 250 uint8_t not_used_02 : 1; 251 uint8_t odrchg_en : 1; 252 uint8_t not_used_01 : 1; 253 uint8_t uncoptr_rate : 2; 254 uint8_t wtm : 1; 255 #endif /* DRV_BYTE_ORDER */ 256 } lsm6dso_fifo_ctrl2_t; 257 258 #define LSM6DSO_FIFO_CTRL3 0x09U 259 typedef struct 260 { 261 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 262 uint8_t bdr_xl : 4; 263 uint8_t bdr_gy : 4; 264 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 265 uint8_t bdr_gy : 4; 266 uint8_t bdr_xl : 4; 267 #endif /* DRV_BYTE_ORDER */ 268 } lsm6dso_fifo_ctrl3_t; 269 270 #define LSM6DSO_FIFO_CTRL4 0x0AU 271 typedef struct 272 { 273 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 274 uint8_t fifo_mode : 3; 275 uint8_t not_used_01 : 1; 276 uint8_t odr_t_batch : 2; 277 uint8_t odr_ts_batch : 2; 278 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 279 uint8_t odr_ts_batch : 2; 280 uint8_t odr_t_batch : 2; 281 uint8_t not_used_01 : 1; 282 uint8_t fifo_mode : 3; 283 #endif /* DRV_BYTE_ORDER */ 284 } lsm6dso_fifo_ctrl4_t; 285 286 #define LSM6DSO_COUNTER_BDR_REG1 0x0BU 287 typedef struct 288 { 289 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 290 uint8_t cnt_bdr_th : 3; 291 uint8_t not_used_01 : 2; 292 uint8_t trig_counter_bdr : 1; 293 uint8_t rst_counter_bdr : 1; 294 uint8_t dataready_pulsed : 1; 295 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 296 uint8_t dataready_pulsed : 1; 297 uint8_t rst_counter_bdr : 1; 298 uint8_t trig_counter_bdr : 1; 299 uint8_t not_used_01 : 2; 300 uint8_t cnt_bdr_th : 3; 301 #endif /* DRV_BYTE_ORDER */ 302 } lsm6dso_counter_bdr_reg1_t; 303 304 #define LSM6DSO_COUNTER_BDR_REG2 0x0CU 305 typedef struct 306 { 307 uint8_t cnt_bdr_th : 8; 308 } lsm6dso_counter_bdr_reg2_t; 309 310 #define LSM6DSO_INT1_CTRL 0x0D 311 typedef struct 312 { 313 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 314 uint8_t int1_drdy_xl : 1; 315 uint8_t int1_drdy_g : 1; 316 uint8_t int1_boot : 1; 317 uint8_t int1_fifo_th : 1; 318 uint8_t int1_fifo_ovr : 1; 319 uint8_t int1_fifo_full : 1; 320 uint8_t int1_cnt_bdr : 1; 321 uint8_t den_drdy_flag : 1; 322 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 323 uint8_t den_drdy_flag : 1; 324 uint8_t int1_cnt_bdr : 1; 325 uint8_t int1_fifo_full : 1; 326 uint8_t int1_fifo_ovr : 1; 327 uint8_t int1_fifo_th : 1; 328 uint8_t int1_boot : 1; 329 uint8_t int1_drdy_g : 1; 330 uint8_t int1_drdy_xl : 1; 331 #endif /* DRV_BYTE_ORDER */ 332 } lsm6dso_int1_ctrl_t; 333 334 #define LSM6DSO_INT2_CTRL 0x0EU 335 typedef struct 336 { 337 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 338 uint8_t int2_drdy_xl : 1; 339 uint8_t int2_drdy_g : 1; 340 uint8_t int2_drdy_temp : 1; 341 uint8_t int2_fifo_th : 1; 342 uint8_t int2_fifo_ovr : 1; 343 uint8_t int2_fifo_full : 1; 344 uint8_t int2_cnt_bdr : 1; 345 uint8_t not_used_01 : 1; 346 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 347 uint8_t not_used_01 : 1; 348 uint8_t int2_cnt_bdr : 1; 349 uint8_t int2_fifo_full : 1; 350 uint8_t int2_fifo_ovr : 1; 351 uint8_t int2_fifo_th : 1; 352 uint8_t int2_drdy_temp : 1; 353 uint8_t int2_drdy_g : 1; 354 uint8_t int2_drdy_xl : 1; 355 #endif /* DRV_BYTE_ORDER */ 356 } lsm6dso_int2_ctrl_t; 357 358 #define LSM6DSO_WHO_AM_I 0x0FU 359 #define LSM6DSO_CTRL1_XL 0x10U 360 typedef struct 361 { 362 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 363 uint8_t not_used_01 : 1; 364 uint8_t lpf2_xl_en : 1; 365 uint8_t fs_xl : 2; 366 uint8_t odr_xl : 4; 367 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 368 uint8_t odr_xl : 4; 369 uint8_t fs_xl : 2; 370 uint8_t lpf2_xl_en : 1; 371 uint8_t not_used_01 : 1; 372 #endif /* DRV_BYTE_ORDER */ 373 } lsm6dso_ctrl1_xl_t; 374 375 #define LSM6DSO_CTRL2_G 0x11U 376 typedef struct 377 { 378 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 379 uint8_t not_used_01 : 1; 380 uint8_t fs_g : 3; /* fs_125 + fs_g */ 381 uint8_t odr_g : 4; 382 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 383 uint8_t odr_g : 4; 384 uint8_t fs_g : 3; /* fs_125 + fs_g */ 385 uint8_t not_used_01 : 1; 386 #endif /* DRV_BYTE_ORDER */ 387 } lsm6dso_ctrl2_g_t; 388 389 #define LSM6DSO_CTRL3_C 0x12U 390 typedef struct 391 { 392 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 393 uint8_t sw_reset : 1; 394 uint8_t not_used_01 : 1; 395 uint8_t if_inc : 1; 396 uint8_t sim : 1; 397 uint8_t pp_od : 1; 398 uint8_t h_lactive : 1; 399 uint8_t bdu : 1; 400 uint8_t boot : 1; 401 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 402 uint8_t boot : 1; 403 uint8_t bdu : 1; 404 uint8_t h_lactive : 1; 405 uint8_t pp_od : 1; 406 uint8_t sim : 1; 407 uint8_t if_inc : 1; 408 uint8_t not_used_01 : 1; 409 uint8_t sw_reset : 1; 410 #endif /* DRV_BYTE_ORDER */ 411 } lsm6dso_ctrl3_c_t; 412 413 #define LSM6DSO_CTRL4_C 0x13U 414 typedef struct 415 { 416 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 417 uint8_t not_used_01 : 1; 418 uint8_t lpf1_sel_g : 1; 419 uint8_t i2c_disable : 1; 420 uint8_t drdy_mask : 1; 421 uint8_t not_used_02 : 1; 422 uint8_t int2_on_int1 : 1; 423 uint8_t sleep_g : 1; 424 uint8_t not_used_03 : 1; 425 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 426 uint8_t not_used_03 : 1; 427 uint8_t sleep_g : 1; 428 uint8_t int2_on_int1 : 1; 429 uint8_t not_used_02 : 1; 430 uint8_t drdy_mask : 1; 431 uint8_t i2c_disable : 1; 432 uint8_t lpf1_sel_g : 1; 433 uint8_t not_used_01 : 1; 434 #endif /* DRV_BYTE_ORDER */ 435 } lsm6dso_ctrl4_c_t; 436 437 #define LSM6DSO_CTRL5_C 0x14U 438 typedef struct 439 { 440 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 441 uint8_t st_xl : 2; 442 uint8_t st_g : 2; 443 uint8_t not_used_01 : 1; 444 uint8_t rounding : 2; 445 uint8_t xl_ulp_en : 1; 446 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 447 uint8_t xl_ulp_en : 1; 448 uint8_t rounding : 2; 449 uint8_t not_used_01 : 1; 450 uint8_t st_g : 2; 451 uint8_t st_xl : 2; 452 #endif /* DRV_BYTE_ORDER */ 453 } lsm6dso_ctrl5_c_t; 454 455 #define LSM6DSO_CTRL6_C 0x15U 456 typedef struct 457 { 458 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 459 uint8_t ftype : 3; 460 uint8_t usr_off_w : 1; 461 uint8_t xl_hm_mode : 1; 462 uint8_t den_mode : 463 3; /* trig_en + lvl1_en + lvl2_en */ 464 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 465 uint8_t den_mode : 466 3; /* trig_en + lvl1_en + lvl2_en */ 467 uint8_t xl_hm_mode : 1; 468 uint8_t usr_off_w : 1; 469 uint8_t ftype : 3; 470 #endif /* DRV_BYTE_ORDER */ 471 } lsm6dso_ctrl6_c_t; 472 473 #define LSM6DSO_CTRL7_G 0x16U 474 typedef struct 475 { 476 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 477 uint8_t ois_on : 1; 478 uint8_t usr_off_on_out : 1; 479 uint8_t ois_on_en : 1; 480 uint8_t not_used_01 : 1; 481 uint8_t hpm_g : 2; 482 uint8_t hp_en_g : 1; 483 uint8_t g_hm_mode : 1; 484 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 485 uint8_t g_hm_mode : 1; 486 uint8_t hp_en_g : 1; 487 uint8_t hpm_g : 2; 488 uint8_t not_used_01 : 1; 489 uint8_t ois_on_en : 1; 490 uint8_t usr_off_on_out : 1; 491 uint8_t ois_on : 1; 492 #endif /* DRV_BYTE_ORDER */ 493 } lsm6dso_ctrl7_g_t; 494 495 #define LSM6DSO_CTRL8_XL 0x17U 496 typedef struct 497 { 498 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 499 uint8_t low_pass_on_6d : 1; 500 uint8_t xl_fs_mode : 1; 501 uint8_t hp_slope_xl_en : 1; 502 uint8_t fastsettl_mode_xl : 1; 503 uint8_t hp_ref_mode_xl : 1; 504 uint8_t hpcf_xl : 3; 505 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 506 uint8_t hpcf_xl : 3; 507 uint8_t hp_ref_mode_xl : 1; 508 uint8_t fastsettl_mode_xl : 1; 509 uint8_t hp_slope_xl_en : 1; 510 uint8_t xl_fs_mode : 1; 511 uint8_t low_pass_on_6d : 1; 512 #endif /* DRV_BYTE_ORDER */ 513 } lsm6dso_ctrl8_xl_t; 514 515 #define LSM6DSO_CTRL9_XL 0x18U 516 typedef struct 517 { 518 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 519 uint8_t not_used_01 : 1; 520 uint8_t i3c_disable : 1; 521 uint8_t den_lh : 1; 522 uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */ 523 uint8_t den_z : 1; 524 uint8_t den_y : 1; 525 uint8_t den_x : 1; 526 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 527 uint8_t den_x : 1; 528 uint8_t den_y : 1; 529 uint8_t den_z : 1; 530 uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */ 531 uint8_t den_lh : 1; 532 uint8_t i3c_disable : 1; 533 uint8_t not_used_01 : 1; 534 #endif /* DRV_BYTE_ORDER */ 535 } lsm6dso_ctrl9_xl_t; 536 537 #define LSM6DSO_CTRL10_C 0x19U 538 typedef struct 539 { 540 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 541 uint8_t not_used_01 : 5; 542 uint8_t timestamp_en : 1; 543 uint8_t not_used_02 : 2; 544 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 545 uint8_t not_used_02 : 2; 546 uint8_t timestamp_en : 1; 547 uint8_t not_used_01 : 5; 548 #endif /* DRV_BYTE_ORDER */ 549 } lsm6dso_ctrl10_c_t; 550 551 #define LSM6DSO_ALL_INT_SRC 0x1AU 552 typedef struct 553 { 554 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 555 uint8_t ff_ia : 1; 556 uint8_t wu_ia : 1; 557 uint8_t single_tap : 1; 558 uint8_t double_tap : 1; 559 uint8_t d6d_ia : 1; 560 uint8_t sleep_change_ia : 1; 561 uint8_t not_used_01 : 1; 562 uint8_t timestamp_endcount : 1; 563 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 564 uint8_t timestamp_endcount : 1; 565 uint8_t not_used_01 : 1; 566 uint8_t sleep_change_ia : 1; 567 uint8_t d6d_ia : 1; 568 uint8_t double_tap : 1; 569 uint8_t single_tap : 1; 570 uint8_t wu_ia : 1; 571 uint8_t ff_ia : 1; 572 #endif /* DRV_BYTE_ORDER */ 573 } lsm6dso_all_int_src_t; 574 575 #define LSM6DSO_WAKE_UP_SRC 0x1BU 576 typedef struct 577 { 578 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 579 uint8_t z_wu : 1; 580 uint8_t y_wu : 1; 581 uint8_t x_wu : 1; 582 uint8_t wu_ia : 1; 583 uint8_t sleep_state : 1; 584 uint8_t ff_ia : 1; 585 uint8_t sleep_change_ia : 1; 586 uint8_t not_used_01 : 1; 587 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 588 uint8_t not_used_01 : 1; 589 uint8_t sleep_change_ia : 1; 590 uint8_t ff_ia : 1; 591 uint8_t sleep_state : 1; 592 uint8_t wu_ia : 1; 593 uint8_t x_wu : 1; 594 uint8_t y_wu : 1; 595 uint8_t z_wu : 1; 596 #endif /* DRV_BYTE_ORDER */ 597 } lsm6dso_wake_up_src_t; 598 599 #define LSM6DSO_TAP_SRC 0x1CU 600 typedef struct 601 { 602 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 603 uint8_t z_tap : 1; 604 uint8_t y_tap : 1; 605 uint8_t x_tap : 1; 606 uint8_t tap_sign : 1; 607 uint8_t double_tap : 1; 608 uint8_t single_tap : 1; 609 uint8_t tap_ia : 1; 610 uint8_t not_used_02 : 1; 611 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 612 uint8_t not_used_02 : 1; 613 uint8_t tap_ia : 1; 614 uint8_t single_tap : 1; 615 uint8_t double_tap : 1; 616 uint8_t tap_sign : 1; 617 uint8_t x_tap : 1; 618 uint8_t y_tap : 1; 619 uint8_t z_tap : 1; 620 #endif /* DRV_BYTE_ORDER */ 621 } lsm6dso_tap_src_t; 622 623 #define LSM6DSO_D6D_SRC 0x1DU 624 typedef struct 625 { 626 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 627 uint8_t xl : 1; 628 uint8_t xh : 1; 629 uint8_t yl : 1; 630 uint8_t yh : 1; 631 uint8_t zl : 1; 632 uint8_t zh : 1; 633 uint8_t d6d_ia : 1; 634 uint8_t den_drdy : 1; 635 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 636 uint8_t den_drdy : 1; 637 uint8_t d6d_ia : 1; 638 uint8_t zh : 1; 639 uint8_t zl : 1; 640 uint8_t yh : 1; 641 uint8_t yl : 1; 642 uint8_t xh : 1; 643 uint8_t xl : 1; 644 #endif /* DRV_BYTE_ORDER */ 645 } lsm6dso_d6d_src_t; 646 647 #define LSM6DSO_STATUS_REG 0x1EU 648 typedef struct 649 { 650 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 651 uint8_t xlda : 1; 652 uint8_t gda : 1; 653 uint8_t tda : 1; 654 uint8_t not_used_01 : 5; 655 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 656 uint8_t not_used_01 : 5; 657 uint8_t tda : 1; 658 uint8_t gda : 1; 659 uint8_t xlda : 1; 660 #endif /* DRV_BYTE_ORDER */ 661 } lsm6dso_status_reg_t; 662 663 #define LSM6DSO_STATUS_SPIAUX 0x1EU 664 typedef struct 665 { 666 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 667 uint8_t xlda : 1; 668 uint8_t gda : 1; 669 uint8_t gyro_settling : 1; 670 uint8_t not_used_01 : 5; 671 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 672 uint8_t not_used_01 : 5; 673 uint8_t gyro_settling : 1; 674 uint8_t gda : 1; 675 uint8_t xlda : 1; 676 #endif /* DRV_BYTE_ORDER */ 677 } lsm6dso_status_spiaux_t; 678 679 #define LSM6DSO_OUT_TEMP_L 0x20U 680 #define LSM6DSO_OUT_TEMP_H 0x21U 681 #define LSM6DSO_OUTX_L_G 0x22U 682 #define LSM6DSO_OUTX_H_G 0x23U 683 #define LSM6DSO_OUTY_L_G 0x24U 684 #define LSM6DSO_OUTY_H_G 0x25U 685 #define LSM6DSO_OUTZ_L_G 0x26U 686 #define LSM6DSO_OUTZ_H_G 0x27U 687 #define LSM6DSO_OUTX_L_A 0x28U 688 #define LSM6DSO_OUTX_H_A 0x29U 689 #define LSM6DSO_OUTY_L_A 0x2AU 690 #define LSM6DSO_OUTY_H_A 0x2BU 691 #define LSM6DSO_OUTZ_L_A 0x2CU 692 #define LSM6DSO_OUTZ_H_A 0x2DU 693 #define LSM6DSO_EMB_FUNC_STATUS_MAINPAGE 0x35U 694 typedef struct 695 { 696 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 697 uint8_t not_used_01 : 3; 698 uint8_t is_step_det : 1; 699 uint8_t is_tilt : 1; 700 uint8_t is_sigmot : 1; 701 uint8_t not_used_02 : 1; 702 uint8_t is_fsm_lc : 1; 703 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 704 uint8_t is_fsm_lc : 1; 705 uint8_t not_used_02 : 1; 706 uint8_t is_sigmot : 1; 707 uint8_t is_tilt : 1; 708 uint8_t is_step_det : 1; 709 uint8_t not_used_01 : 3; 710 #endif /* DRV_BYTE_ORDER */ 711 } lsm6dso_emb_func_status_mainpage_t; 712 713 #define LSM6DSO_FSM_STATUS_A_MAINPAGE 0x36U 714 typedef struct 715 { 716 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 717 uint8_t is_fsm1 : 1; 718 uint8_t is_fsm2 : 1; 719 uint8_t is_fsm3 : 1; 720 uint8_t is_fsm4 : 1; 721 uint8_t is_fsm5 : 1; 722 uint8_t is_fsm6 : 1; 723 uint8_t is_fsm7 : 1; 724 uint8_t is_fsm8 : 1; 725 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 726 uint8_t is_fsm8 : 1; 727 uint8_t is_fsm7 : 1; 728 uint8_t is_fsm6 : 1; 729 uint8_t is_fsm5 : 1; 730 uint8_t is_fsm4 : 1; 731 uint8_t is_fsm3 : 1; 732 uint8_t is_fsm2 : 1; 733 uint8_t is_fsm1 : 1; 734 #endif /* DRV_BYTE_ORDER */ 735 } lsm6dso_fsm_status_a_mainpage_t; 736 737 #define LSM6DSO_FSM_STATUS_B_MAINPAGE 0x37U 738 typedef struct 739 { 740 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 741 uint8_t is_fsm9 : 1; 742 uint8_t is_fsm10 : 1; 743 uint8_t is_fsm11 : 1; 744 uint8_t is_fsm12 : 1; 745 uint8_t is_fsm13 : 1; 746 uint8_t is_fsm14 : 1; 747 uint8_t is_fsm15 : 1; 748 uint8_t is_fsm16 : 1; 749 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 750 uint8_t is_fsm16 : 1; 751 uint8_t is_fsm15 : 1; 752 uint8_t is_fsm14 : 1; 753 uint8_t is_fsm13 : 1; 754 uint8_t is_fsm12 : 1; 755 uint8_t is_fsm11 : 1; 756 uint8_t is_fsm10 : 1; 757 uint8_t is_fsm9 : 1; 758 #endif /* DRV_BYTE_ORDER */ 759 } lsm6dso_fsm_status_b_mainpage_t; 760 761 #define LSM6DSO_STATUS_MASTER_MAINPAGE 0x39U 762 typedef struct 763 { 764 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 765 uint8_t sens_hub_endop : 1; 766 uint8_t not_used_01 : 2; 767 uint8_t slave0_nack : 1; 768 uint8_t slave1_nack : 1; 769 uint8_t slave2_nack : 1; 770 uint8_t slave3_nack : 1; 771 uint8_t wr_once_done : 1; 772 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 773 uint8_t wr_once_done : 1; 774 uint8_t slave3_nack : 1; 775 uint8_t slave2_nack : 1; 776 uint8_t slave1_nack : 1; 777 uint8_t slave0_nack : 1; 778 uint8_t not_used_01 : 2; 779 uint8_t sens_hub_endop : 1; 780 #endif /* DRV_BYTE_ORDER */ 781 } lsm6dso_status_master_mainpage_t; 782 783 #define LSM6DSO_FIFO_STATUS1 0x3AU 784 typedef struct 785 { 786 uint8_t diff_fifo : 8; 787 } lsm6dso_fifo_status1_t; 788 789 #define LSM6DSO_FIFO_STATUS2 0x3B 790 typedef struct 791 { 792 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 793 uint8_t diff_fifo : 2; 794 uint8_t not_used_01 : 1; 795 uint8_t over_run_latched : 1; 796 uint8_t counter_bdr_ia : 1; 797 uint8_t fifo_full_ia : 1; 798 uint8_t fifo_ovr_ia : 1; 799 uint8_t fifo_wtm_ia : 1; 800 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 801 uint8_t fifo_wtm_ia : 1; 802 uint8_t fifo_ovr_ia : 1; 803 uint8_t fifo_full_ia : 1; 804 uint8_t counter_bdr_ia : 1; 805 uint8_t over_run_latched : 1; 806 uint8_t not_used_01 : 1; 807 uint8_t diff_fifo : 2; 808 #endif /* DRV_BYTE_ORDER */ 809 } lsm6dso_fifo_status2_t; 810 811 #define LSM6DSO_TIMESTAMP0 0x40U 812 #define LSM6DSO_TIMESTAMP1 0x41U 813 #define LSM6DSO_TIMESTAMP2 0x42U 814 #define LSM6DSO_TIMESTAMP3 0x43U 815 #define LSM6DSO_TAP_CFG0 0x56U 816 typedef struct 817 { 818 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 819 uint8_t lir : 1; 820 uint8_t tap_z_en : 1; 821 uint8_t tap_y_en : 1; 822 uint8_t tap_x_en : 1; 823 uint8_t slope_fds : 1; 824 uint8_t sleep_status_on_int : 1; 825 uint8_t int_clr_on_read : 1; 826 uint8_t not_used_01 : 1; 827 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 828 uint8_t not_used_01 : 1; 829 uint8_t int_clr_on_read : 1; 830 uint8_t sleep_status_on_int : 1; 831 uint8_t slope_fds : 1; 832 uint8_t tap_x_en : 1; 833 uint8_t tap_y_en : 1; 834 uint8_t tap_z_en : 1; 835 uint8_t lir : 1; 836 #endif /* DRV_BYTE_ORDER */ 837 } lsm6dso_tap_cfg0_t; 838 839 #define LSM6DSO_TAP_CFG1 0x57U 840 typedef struct 841 { 842 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 843 uint8_t tap_ths_x : 5; 844 uint8_t tap_priority : 3; 845 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 846 uint8_t tap_priority : 3; 847 uint8_t tap_ths_x : 5; 848 #endif /* DRV_BYTE_ORDER */ 849 } lsm6dso_tap_cfg1_t; 850 851 #define LSM6DSO_TAP_CFG2 0x58U 852 typedef struct 853 { 854 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 855 uint8_t tap_ths_y : 5; 856 uint8_t inact_en : 2; 857 uint8_t interrupts_enable : 1; 858 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 859 uint8_t interrupts_enable : 1; 860 uint8_t inact_en : 2; 861 uint8_t tap_ths_y : 5; 862 #endif /* DRV_BYTE_ORDER */ 863 } lsm6dso_tap_cfg2_t; 864 865 #define LSM6DSO_TAP_THS_6D 0x59U 866 typedef struct 867 { 868 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 869 uint8_t tap_ths_z : 5; 870 uint8_t sixd_ths : 2; 871 uint8_t d4d_en : 1; 872 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 873 uint8_t d4d_en : 1; 874 uint8_t sixd_ths : 2; 875 uint8_t tap_ths_z : 5; 876 #endif /* DRV_BYTE_ORDER */ 877 } lsm6dso_tap_ths_6d_t; 878 879 #define LSM6DSO_INT_DUR2 0x5AU 880 typedef struct 881 { 882 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 883 uint8_t shock : 2; 884 uint8_t quiet : 2; 885 uint8_t dur : 4; 886 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 887 uint8_t dur : 4; 888 uint8_t quiet : 2; 889 uint8_t shock : 2; 890 #endif /* DRV_BYTE_ORDER */ 891 } lsm6dso_int_dur2_t; 892 893 #define LSM6DSO_WAKE_UP_THS 0x5BU 894 typedef struct 895 { 896 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 897 uint8_t wk_ths : 6; 898 uint8_t usr_off_on_wu : 1; 899 uint8_t single_double_tap : 1; 900 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 901 uint8_t single_double_tap : 1; 902 uint8_t usr_off_on_wu : 1; 903 uint8_t wk_ths : 6; 904 #endif /* DRV_BYTE_ORDER */ 905 } lsm6dso_wake_up_ths_t; 906 907 #define LSM6DSO_WAKE_UP_DUR 0x5CU 908 typedef struct 909 { 910 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 911 uint8_t sleep_dur : 4; 912 uint8_t wake_ths_w : 1; 913 uint8_t wake_dur : 2; 914 uint8_t ff_dur : 1; 915 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 916 uint8_t ff_dur : 1; 917 uint8_t wake_dur : 2; 918 uint8_t wake_ths_w : 1; 919 uint8_t sleep_dur : 4; 920 #endif /* DRV_BYTE_ORDER */ 921 } lsm6dso_wake_up_dur_t; 922 923 #define LSM6DSO_FREE_FALL 0x5DU 924 typedef struct 925 { 926 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 927 uint8_t ff_ths : 3; 928 uint8_t ff_dur : 5; 929 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 930 uint8_t ff_dur : 5; 931 uint8_t ff_ths : 3; 932 #endif /* DRV_BYTE_ORDER */ 933 } lsm6dso_free_fall_t; 934 935 #define LSM6DSO_MD1_CFG 0x5EU 936 typedef struct 937 { 938 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 939 uint8_t int1_shub : 1; 940 uint8_t int1_emb_func : 1; 941 uint8_t int1_6d : 1; 942 uint8_t int1_double_tap : 1; 943 uint8_t int1_ff : 1; 944 uint8_t int1_wu : 1; 945 uint8_t int1_single_tap : 1; 946 uint8_t int1_sleep_change : 1; 947 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 948 uint8_t int1_sleep_change : 1; 949 uint8_t int1_single_tap : 1; 950 uint8_t int1_wu : 1; 951 uint8_t int1_ff : 1; 952 uint8_t int1_double_tap : 1; 953 uint8_t int1_6d : 1; 954 uint8_t int1_emb_func : 1; 955 uint8_t int1_shub : 1; 956 #endif /* DRV_BYTE_ORDER */ 957 } lsm6dso_md1_cfg_t; 958 959 #define LSM6DSO_MD2_CFG 0x5FU 960 typedef struct 961 { 962 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 963 uint8_t int2_timestamp : 1; 964 uint8_t int2_emb_func : 1; 965 uint8_t int2_6d : 1; 966 uint8_t int2_double_tap : 1; 967 uint8_t int2_ff : 1; 968 uint8_t int2_wu : 1; 969 uint8_t int2_single_tap : 1; 970 uint8_t int2_sleep_change : 1; 971 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 972 uint8_t int2_sleep_change : 1; 973 uint8_t int2_single_tap : 1; 974 uint8_t int2_wu : 1; 975 uint8_t int2_ff : 1; 976 uint8_t int2_double_tap : 1; 977 uint8_t int2_6d : 1; 978 uint8_t int2_emb_func : 1; 979 uint8_t int2_timestamp : 1; 980 #endif /* DRV_BYTE_ORDER */ 981 } lsm6dso_md2_cfg_t; 982 983 #define LSM6DSO_I3C_BUS_AVB 0x62U 984 typedef struct 985 { 986 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 987 uint8_t pd_dis_int1 : 1; 988 uint8_t not_used_01 : 2; 989 uint8_t i3c_bus_avb_sel : 2; 990 uint8_t not_used_02 : 3; 991 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 992 uint8_t not_used_02 : 3; 993 uint8_t i3c_bus_avb_sel : 2; 994 uint8_t not_used_01 : 2; 995 uint8_t pd_dis_int1 : 1; 996 #endif /* DRV_BYTE_ORDER */ 997 } lsm6dso_i3c_bus_avb_t; 998 999 #define LSM6DSO_INTERNAL_FREQ_FINE 0x63U 1000 typedef struct 1001 { 1002 uint8_t freq_fine : 8; 1003 } lsm6dso_internal_freq_fine_t; 1004 1005 #define LSM6DSO_INT_OIS 0x6FU 1006 typedef struct 1007 { 1008 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1009 uint8_t st_xl_ois : 2; 1010 uint8_t not_used_01 : 3; 1011 uint8_t den_lh_ois : 1; 1012 uint8_t lvl2_ois : 1; 1013 uint8_t int2_drdy_ois : 1; 1014 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1015 uint8_t int2_drdy_ois : 1; 1016 uint8_t lvl2_ois : 1; 1017 uint8_t den_lh_ois : 1; 1018 uint8_t not_used_01 : 3; 1019 uint8_t st_xl_ois : 2; 1020 #endif /* DRV_BYTE_ORDER */ 1021 } lsm6dso_int_ois_t; 1022 1023 #define LSM6DSO_CTRL1_OIS 0x70U 1024 typedef struct 1025 { 1026 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1027 uint8_t ois_en_spi2 : 1; 1028 uint8_t fs_g_ois : 3; /* fs_125_ois + fs[1:0]_g_ois */ 1029 uint8_t mode4_en : 1; 1030 uint8_t sim_ois : 1; 1031 uint8_t lvl1_ois : 1; 1032 uint8_t not_used_01 : 1; 1033 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1034 uint8_t not_used_01 : 1; 1035 uint8_t lvl1_ois : 1; 1036 uint8_t sim_ois : 1; 1037 uint8_t mode4_en : 1; 1038 uint8_t fs_g_ois : 3; /* fs_125_ois + fs[1:0]_g_ois */ 1039 uint8_t ois_en_spi2 : 1; 1040 #endif /* DRV_BYTE_ORDER */ 1041 } lsm6dso_ctrl1_ois_t; 1042 1043 #define LSM6DSO_CTRL2_OIS 0x71U 1044 typedef struct 1045 { 1046 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1047 uint8_t hp_en_ois : 1; 1048 uint8_t ftype_ois : 2; 1049 uint8_t not_used_01 : 1; 1050 uint8_t hpm_ois : 2; 1051 uint8_t not_used_02 : 2; 1052 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1053 uint8_t not_used_02 : 2; 1054 uint8_t hpm_ois : 2; 1055 uint8_t not_used_01 : 1; 1056 uint8_t ftype_ois : 2; 1057 uint8_t hp_en_ois : 1; 1058 #endif /* DRV_BYTE_ORDER */ 1059 } lsm6dso_ctrl2_ois_t; 1060 1061 #define LSM6DSO_CTRL3_OIS 0x72U 1062 typedef struct 1063 { 1064 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1065 uint8_t st_ois_clampdis : 1; 1066 uint8_t st_ois : 2; 1067 uint8_t filter_xl_conf_ois : 3; 1068 uint8_t fs_xl_ois : 2; 1069 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1070 uint8_t fs_xl_ois : 2; 1071 uint8_t filter_xl_conf_ois : 3; 1072 uint8_t st_ois : 2; 1073 uint8_t st_ois_clampdis : 1; 1074 #endif /* DRV_BYTE_ORDER */ 1075 } lsm6dso_ctrl3_ois_t; 1076 1077 #define LSM6DSO_X_OFS_USR 0x73U 1078 #define LSM6DSO_Y_OFS_USR 0x74U 1079 #define LSM6DSO_Z_OFS_USR 0x75U 1080 #define LSM6DSO_FIFO_DATA_OUT_TAG 0x78U 1081 typedef struct 1082 { 1083 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1084 uint8_t tag_parity : 1; 1085 uint8_t tag_cnt : 2; 1086 uint8_t tag_sensor : 5; 1087 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1088 uint8_t tag_sensor : 5; 1089 uint8_t tag_cnt : 2; 1090 uint8_t tag_parity : 1; 1091 #endif /* DRV_BYTE_ORDER */ 1092 } lsm6dso_fifo_data_out_tag_t; 1093 1094 #define LSM6DSO_FIFO_DATA_OUT_X_L 0x79U 1095 #define LSM6DSO_FIFO_DATA_OUT_X_H 0x7AU 1096 #define LSM6DSO_FIFO_DATA_OUT_Y_L 0x7BU 1097 #define LSM6DSO_FIFO_DATA_OUT_Y_H 0x7CU 1098 #define LSM6DSO_FIFO_DATA_OUT_Z_L 0x7DU 1099 #define LSM6DSO_FIFO_DATA_OUT_Z_H 0x7EU 1100 #define LSM6DSO_PAGE_SEL 0x02U 1101 typedef struct 1102 { 1103 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1104 uint8_t not_used_01 : 4; 1105 uint8_t page_sel : 4; 1106 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1107 uint8_t page_sel : 4; 1108 uint8_t not_used_01 : 4; 1109 #endif /* DRV_BYTE_ORDER */ 1110 } lsm6dso_page_sel_t; 1111 1112 #define LSM6DSO_EMB_FUNC_EN_A 0x04U 1113 typedef struct 1114 { 1115 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1116 uint8_t not_used_01 : 3; 1117 uint8_t pedo_en : 1; 1118 uint8_t tilt_en : 1; 1119 uint8_t sign_motion_en : 1; 1120 uint8_t not_used_02 : 2; 1121 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1122 uint8_t not_used_02 : 2; 1123 uint8_t sign_motion_en : 1; 1124 uint8_t tilt_en : 1; 1125 uint8_t pedo_en : 1; 1126 uint8_t not_used_01 : 3; 1127 #endif /* DRV_BYTE_ORDER */ 1128 } lsm6dso_emb_func_en_a_t; 1129 1130 #define LSM6DSO_EMB_FUNC_EN_B 0x05U 1131 typedef struct 1132 { 1133 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1134 uint8_t fsm_en : 1; 1135 uint8_t not_used_01 : 2; 1136 uint8_t fifo_compr_en : 1; 1137 uint8_t pedo_adv_en : 1; 1138 uint8_t not_used_02 : 3; 1139 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1140 uint8_t not_used_02 : 3; 1141 uint8_t pedo_adv_en : 1; 1142 uint8_t fifo_compr_en : 1; 1143 uint8_t not_used_01 : 2; 1144 uint8_t fsm_en : 1; 1145 #endif /* DRV_BYTE_ORDER */ 1146 } lsm6dso_emb_func_en_b_t; 1147 1148 #define LSM6DSO_PAGE_ADDRESS 0x08U 1149 typedef struct 1150 { 1151 uint8_t page_addr : 8; 1152 } lsm6dso_page_address_t; 1153 1154 #define LSM6DSO_PAGE_VALUE 0x09U 1155 typedef struct 1156 { 1157 uint8_t page_value : 8; 1158 } lsm6dso_page_value_t; 1159 1160 #define LSM6DSO_EMB_FUNC_INT1 0x0AU 1161 typedef struct 1162 { 1163 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1164 uint8_t not_used_01 : 3; 1165 uint8_t int1_step_detector : 1; 1166 uint8_t int1_tilt : 1; 1167 uint8_t int1_sig_mot : 1; 1168 uint8_t not_used_02 : 1; 1169 uint8_t int1_fsm_lc : 1; 1170 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1171 uint8_t int1_fsm_lc : 1; 1172 uint8_t not_used_02 : 1; 1173 uint8_t int1_sig_mot : 1; 1174 uint8_t int1_tilt : 1; 1175 uint8_t int1_step_detector : 1; 1176 uint8_t not_used_01 : 3; 1177 #endif /* DRV_BYTE_ORDER */ 1178 } lsm6dso_emb_func_int1_t; 1179 1180 #define LSM6DSO_FSM_INT1_A 0x0BU 1181 typedef struct 1182 { 1183 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1184 uint8_t int1_fsm1 : 1; 1185 uint8_t int1_fsm2 : 1; 1186 uint8_t int1_fsm3 : 1; 1187 uint8_t int1_fsm4 : 1; 1188 uint8_t int1_fsm5 : 1; 1189 uint8_t int1_fsm6 : 1; 1190 uint8_t int1_fsm7 : 1; 1191 uint8_t int1_fsm8 : 1; 1192 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1193 uint8_t int1_fsm8 : 1; 1194 uint8_t int1_fsm7 : 1; 1195 uint8_t int1_fsm6 : 1; 1196 uint8_t int1_fsm5 : 1; 1197 uint8_t int1_fsm4 : 1; 1198 uint8_t int1_fsm3 : 1; 1199 uint8_t int1_fsm2 : 1; 1200 uint8_t int1_fsm1 : 1; 1201 #endif /* DRV_BYTE_ORDER */ 1202 } lsm6dso_fsm_int1_a_t; 1203 1204 #define LSM6DSO_FSM_INT1_B 0x0CU 1205 typedef struct 1206 { 1207 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1208 uint8_t int1_fsm9 : 1; 1209 uint8_t int1_fsm10 : 1; 1210 uint8_t int1_fsm11 : 1; 1211 uint8_t int1_fsm12 : 1; 1212 uint8_t int1_fsm13 : 1; 1213 uint8_t int1_fsm14 : 1; 1214 uint8_t int1_fsm15 : 1; 1215 uint8_t int1_fsm16 : 1; 1216 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1217 uint8_t int1_fsm16 : 1; 1218 uint8_t int1_fsm15 : 1; 1219 uint8_t int1_fsm14 : 1; 1220 uint8_t int1_fsm13 : 1; 1221 uint8_t int1_fsm12 : 1; 1222 uint8_t int1_fsm11 : 1; 1223 uint8_t int1_fsm10 : 1; 1224 uint8_t int1_fsm9 : 1; 1225 #endif /* DRV_BYTE_ORDER */ 1226 } lsm6dso_fsm_int1_b_t; 1227 1228 #define LSM6DSO_EMB_FUNC_INT2 0x0EU 1229 typedef struct 1230 { 1231 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1232 uint8_t not_used_01 : 3; 1233 uint8_t int2_step_detector : 1; 1234 uint8_t int2_tilt : 1; 1235 uint8_t int2_sig_mot : 1; 1236 uint8_t not_used_02 : 1; 1237 uint8_t int2_fsm_lc : 1; 1238 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1239 uint8_t int2_fsm_lc : 1; 1240 uint8_t not_used_02 : 1; 1241 uint8_t int2_sig_mot : 1; 1242 uint8_t int2_tilt : 1; 1243 uint8_t int2_step_detector : 1; 1244 uint8_t not_used_01 : 3; 1245 #endif /* DRV_BYTE_ORDER */ 1246 } lsm6dso_emb_func_int2_t; 1247 1248 #define LSM6DSO_FSM_INT2_A 0x0FU 1249 typedef struct 1250 { 1251 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1252 uint8_t int2_fsm1 : 1; 1253 uint8_t int2_fsm2 : 1; 1254 uint8_t int2_fsm3 : 1; 1255 uint8_t int2_fsm4 : 1; 1256 uint8_t int2_fsm5 : 1; 1257 uint8_t int2_fsm6 : 1; 1258 uint8_t int2_fsm7 : 1; 1259 uint8_t int2_fsm8 : 1; 1260 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1261 uint8_t int2_fsm8 : 1; 1262 uint8_t int2_fsm7 : 1; 1263 uint8_t int2_fsm6 : 1; 1264 uint8_t int2_fsm5 : 1; 1265 uint8_t int2_fsm4 : 1; 1266 uint8_t int2_fsm3 : 1; 1267 uint8_t int2_fsm2 : 1; 1268 uint8_t int2_fsm1 : 1; 1269 #endif /* DRV_BYTE_ORDER */ 1270 } lsm6dso_fsm_int2_a_t; 1271 1272 #define LSM6DSO_FSM_INT2_B 0x10U 1273 typedef struct 1274 { 1275 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1276 uint8_t int2_fsm9 : 1; 1277 uint8_t int2_fsm10 : 1; 1278 uint8_t int2_fsm11 : 1; 1279 uint8_t int2_fsm12 : 1; 1280 uint8_t int2_fsm13 : 1; 1281 uint8_t int2_fsm14 : 1; 1282 uint8_t int2_fsm15 : 1; 1283 uint8_t int2_fsm16 : 1; 1284 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1285 uint8_t int2_fsm16 : 1; 1286 uint8_t int2_fsm15 : 1; 1287 uint8_t int2_fsm14 : 1; 1288 uint8_t int2_fsm13 : 1; 1289 uint8_t int2_fsm12 : 1; 1290 uint8_t int2_fsm11 : 1; 1291 uint8_t int2_fsm10 : 1; 1292 uint8_t int2_fsm9 : 1; 1293 #endif /* DRV_BYTE_ORDER */ 1294 } lsm6dso_fsm_int2_b_t; 1295 1296 #define LSM6DSO_EMB_FUNC_STATUS 0x12U 1297 typedef struct 1298 { 1299 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1300 uint8_t not_used_01 : 3; 1301 uint8_t is_step_det : 1; 1302 uint8_t is_tilt : 1; 1303 uint8_t is_sigmot : 1; 1304 uint8_t not_used_02 : 1; 1305 uint8_t is_fsm_lc : 1; 1306 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1307 uint8_t is_fsm_lc : 1; 1308 uint8_t not_used_02 : 1; 1309 uint8_t is_sigmot : 1; 1310 uint8_t is_tilt : 1; 1311 uint8_t is_step_det : 1; 1312 uint8_t not_used_01 : 3; 1313 #endif /* DRV_BYTE_ORDER */ 1314 } lsm6dso_emb_func_status_t; 1315 1316 #define LSM6DSO_FSM_STATUS_A 0x13U 1317 typedef struct 1318 { 1319 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1320 uint8_t is_fsm1 : 1; 1321 uint8_t is_fsm2 : 1; 1322 uint8_t is_fsm3 : 1; 1323 uint8_t is_fsm4 : 1; 1324 uint8_t is_fsm5 : 1; 1325 uint8_t is_fsm6 : 1; 1326 uint8_t is_fsm7 : 1; 1327 uint8_t is_fsm8 : 1; 1328 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1329 uint8_t is_fsm8 : 1; 1330 uint8_t is_fsm7 : 1; 1331 uint8_t is_fsm6 : 1; 1332 uint8_t is_fsm5 : 1; 1333 uint8_t is_fsm4 : 1; 1334 uint8_t is_fsm3 : 1; 1335 uint8_t is_fsm2 : 1; 1336 uint8_t is_fsm1 : 1; 1337 #endif /* DRV_BYTE_ORDER */ 1338 } lsm6dso_fsm_status_a_t; 1339 1340 #define LSM6DSO_FSM_STATUS_B 0x14U 1341 typedef struct 1342 { 1343 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1344 uint8_t is_fsm9 : 1; 1345 uint8_t is_fsm10 : 1; 1346 uint8_t is_fsm11 : 1; 1347 uint8_t is_fsm12 : 1; 1348 uint8_t is_fsm13 : 1; 1349 uint8_t is_fsm14 : 1; 1350 uint8_t is_fsm15 : 1; 1351 uint8_t is_fsm16 : 1; 1352 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1353 uint8_t is_fsm16 : 1; 1354 uint8_t is_fsm15 : 1; 1355 uint8_t is_fsm14 : 1; 1356 uint8_t is_fsm13 : 1; 1357 uint8_t is_fsm12 : 1; 1358 uint8_t is_fsm11 : 1; 1359 uint8_t is_fsm10 : 1; 1360 uint8_t is_fsm9 : 1; 1361 #endif /* DRV_BYTE_ORDER */ 1362 } lsm6dso_fsm_status_b_t; 1363 1364 #define LSM6DSO_PAGE_RW 0x17U 1365 typedef struct 1366 { 1367 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1368 uint8_t not_used_01 : 5; 1369 uint8_t page_rw : 2; /* page_write + page_read */ 1370 uint8_t emb_func_lir : 1; 1371 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1372 uint8_t emb_func_lir : 1; 1373 uint8_t page_rw : 2; /* page_write + page_read */ 1374 uint8_t not_used_01 : 5; 1375 #endif /* DRV_BYTE_ORDER */ 1376 } lsm6dso_page_rw_t; 1377 1378 #define LSM6DSO_EMB_FUNC_FIFO_CFG 0x44U 1379 typedef struct 1380 { 1381 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1382 uint8_t not_used_00 : 6; 1383 uint8_t pedo_fifo_en : 1; 1384 uint8_t not_used_01 : 1; 1385 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1386 uint8_t not_used_01 : 1; 1387 uint8_t pedo_fifo_en : 1; 1388 uint8_t not_used_00 : 6; 1389 #endif /* DRV_BYTE_ORDER */ 1390 } lsm6dso_emb_func_fifo_cfg_t; 1391 1392 #define LSM6DSO_FSM_ENABLE_A 0x46U 1393 typedef struct 1394 { 1395 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1396 uint8_t fsm1_en : 1; 1397 uint8_t fsm2_en : 1; 1398 uint8_t fsm3_en : 1; 1399 uint8_t fsm4_en : 1; 1400 uint8_t fsm5_en : 1; 1401 uint8_t fsm6_en : 1; 1402 uint8_t fsm7_en : 1; 1403 uint8_t fsm8_en : 1; 1404 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1405 uint8_t fsm8_en : 1; 1406 uint8_t fsm7_en : 1; 1407 uint8_t fsm6_en : 1; 1408 uint8_t fsm5_en : 1; 1409 uint8_t fsm4_en : 1; 1410 uint8_t fsm3_en : 1; 1411 uint8_t fsm2_en : 1; 1412 uint8_t fsm1_en : 1; 1413 #endif /* DRV_BYTE_ORDER */ 1414 } lsm6dso_fsm_enable_a_t; 1415 1416 #define LSM6DSO_FSM_ENABLE_B 0x47U 1417 typedef struct 1418 { 1419 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1420 uint8_t fsm9_en : 1; 1421 uint8_t fsm10_en : 1; 1422 uint8_t fsm11_en : 1; 1423 uint8_t fsm12_en : 1; 1424 uint8_t fsm13_en : 1; 1425 uint8_t fsm14_en : 1; 1426 uint8_t fsm15_en : 1; 1427 uint8_t fsm16_en : 1; 1428 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1429 uint8_t fsm16_en : 1; 1430 uint8_t fsm15_en : 1; 1431 uint8_t fsm14_en : 1; 1432 uint8_t fsm13_en : 1; 1433 uint8_t fsm12_en : 1; 1434 uint8_t fsm11_en : 1; 1435 uint8_t fsm10_en : 1; 1436 uint8_t fsm9_en : 1; 1437 #endif /* DRV_BYTE_ORDER */ 1438 } lsm6dso_fsm_enable_b_t; 1439 1440 #define LSM6DSO_FSM_LONG_COUNTER_L 0x48U 1441 #define LSM6DSO_FSM_LONG_COUNTER_H 0x49U 1442 #define LSM6DSO_FSM_LONG_COUNTER_CLEAR 0x4AU 1443 typedef struct 1444 { 1445 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1446 uint8_t fsm_lc_clr : 1447 2; /* fsm_lc_cleared + fsm_lc_clear */ 1448 uint8_t not_used_01 : 6; 1449 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1450 uint8_t not_used_01 : 6; 1451 uint8_t fsm_lc_clr : 1452 2; /* fsm_lc_cleared + fsm_lc_clear */ 1453 #endif /* DRV_BYTE_ORDER */ 1454 } lsm6dso_fsm_long_counter_clear_t; 1455 1456 #define LSM6DSO_FSM_OUTS1 0x4CU 1457 typedef struct 1458 { 1459 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1460 uint8_t n_v : 1; 1461 uint8_t p_v : 1; 1462 uint8_t n_z : 1; 1463 uint8_t p_z : 1; 1464 uint8_t n_y : 1; 1465 uint8_t p_y : 1; 1466 uint8_t n_x : 1; 1467 uint8_t p_x : 1; 1468 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1469 uint8_t p_x : 1; 1470 uint8_t n_x : 1; 1471 uint8_t p_y : 1; 1472 uint8_t n_y : 1; 1473 uint8_t p_z : 1; 1474 uint8_t n_z : 1; 1475 uint8_t p_v : 1; 1476 uint8_t n_v : 1; 1477 #endif /* DRV_BYTE_ORDER */ 1478 } lsm6dso_fsm_outs1_t; 1479 1480 #define LSM6DSO_FSM_OUTS2 0x4DU 1481 typedef struct 1482 { 1483 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1484 uint8_t n_v : 1; 1485 uint8_t p_v : 1; 1486 uint8_t n_z : 1; 1487 uint8_t p_z : 1; 1488 uint8_t n_y : 1; 1489 uint8_t p_y : 1; 1490 uint8_t n_x : 1; 1491 uint8_t p_x : 1; 1492 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1493 uint8_t p_x : 1; 1494 uint8_t n_x : 1; 1495 uint8_t p_y : 1; 1496 uint8_t n_y : 1; 1497 uint8_t p_z : 1; 1498 uint8_t n_z : 1; 1499 uint8_t p_v : 1; 1500 uint8_t n_v : 1; 1501 #endif /* DRV_BYTE_ORDER */ 1502 } lsm6dso_fsm_outs2_t; 1503 1504 #define LSM6DSO_FSM_OUTS3 0x4EU 1505 typedef struct 1506 { 1507 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1508 uint8_t n_v : 1; 1509 uint8_t p_v : 1; 1510 uint8_t n_z : 1; 1511 uint8_t p_z : 1; 1512 uint8_t n_y : 1; 1513 uint8_t p_y : 1; 1514 uint8_t n_x : 1; 1515 uint8_t p_x : 1; 1516 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1517 uint8_t p_x : 1; 1518 uint8_t n_x : 1; 1519 uint8_t p_y : 1; 1520 uint8_t n_y : 1; 1521 uint8_t p_z : 1; 1522 uint8_t n_z : 1; 1523 uint8_t p_v : 1; 1524 uint8_t n_v : 1; 1525 #endif /* DRV_BYTE_ORDER */ 1526 } lsm6dso_fsm_outs3_t; 1527 1528 #define LSM6DSO_FSM_OUTS4 0x4FU 1529 typedef struct 1530 { 1531 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1532 uint8_t n_v : 1; 1533 uint8_t p_v : 1; 1534 uint8_t n_z : 1; 1535 uint8_t p_z : 1; 1536 uint8_t n_y : 1; 1537 uint8_t p_y : 1; 1538 uint8_t n_x : 1; 1539 uint8_t p_x : 1; 1540 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1541 uint8_t p_x : 1; 1542 uint8_t n_x : 1; 1543 uint8_t p_y : 1; 1544 uint8_t n_y : 1; 1545 uint8_t p_z : 1; 1546 uint8_t n_z : 1; 1547 uint8_t p_v : 1; 1548 uint8_t n_v : 1; 1549 #endif /* DRV_BYTE_ORDER */ 1550 } lsm6dso_fsm_outs4_t; 1551 1552 #define LSM6DSO_FSM_OUTS5 0x50U 1553 typedef struct 1554 { 1555 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1556 uint8_t n_v : 1; 1557 uint8_t p_v : 1; 1558 uint8_t n_z : 1; 1559 uint8_t p_z : 1; 1560 uint8_t n_y : 1; 1561 uint8_t p_y : 1; 1562 uint8_t n_x : 1; 1563 uint8_t p_x : 1; 1564 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1565 uint8_t p_x : 1; 1566 uint8_t n_x : 1; 1567 uint8_t p_y : 1; 1568 uint8_t n_y : 1; 1569 uint8_t p_z : 1; 1570 uint8_t n_z : 1; 1571 uint8_t p_v : 1; 1572 uint8_t n_v : 1; 1573 #endif /* DRV_BYTE_ORDER */ 1574 } lsm6dso_fsm_outs5_t; 1575 1576 #define LSM6DSO_FSM_OUTS6 0x51U 1577 typedef struct 1578 { 1579 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1580 uint8_t n_v : 1; 1581 uint8_t p_v : 1; 1582 uint8_t n_z : 1; 1583 uint8_t p_z : 1; 1584 uint8_t n_y : 1; 1585 uint8_t p_y : 1; 1586 uint8_t n_x : 1; 1587 uint8_t p_x : 1; 1588 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1589 uint8_t p_x : 1; 1590 uint8_t n_x : 1; 1591 uint8_t p_y : 1; 1592 uint8_t n_y : 1; 1593 uint8_t p_z : 1; 1594 uint8_t n_z : 1; 1595 uint8_t p_v : 1; 1596 uint8_t n_v : 1; 1597 #endif /* DRV_BYTE_ORDER */ 1598 } lsm6dso_fsm_outs6_t; 1599 1600 #define LSM6DSO_FSM_OUTS7 0x52U 1601 typedef struct 1602 { 1603 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1604 uint8_t n_v : 1; 1605 uint8_t p_v : 1; 1606 uint8_t n_z : 1; 1607 uint8_t p_z : 1; 1608 uint8_t n_y : 1; 1609 uint8_t p_y : 1; 1610 uint8_t n_x : 1; 1611 uint8_t p_x : 1; 1612 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1613 uint8_t p_x : 1; 1614 uint8_t n_x : 1; 1615 uint8_t p_y : 1; 1616 uint8_t n_y : 1; 1617 uint8_t p_z : 1; 1618 uint8_t n_z : 1; 1619 uint8_t p_v : 1; 1620 uint8_t n_v : 1; 1621 #endif /* DRV_BYTE_ORDER */ 1622 } lsm6dso_fsm_outs7_t; 1623 1624 #define LSM6DSO_FSM_OUTS8 0x53U 1625 typedef struct 1626 { 1627 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1628 uint8_t n_v : 1; 1629 uint8_t p_v : 1; 1630 uint8_t n_z : 1; 1631 uint8_t p_z : 1; 1632 uint8_t n_y : 1; 1633 uint8_t p_y : 1; 1634 uint8_t n_x : 1; 1635 uint8_t p_x : 1; 1636 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1637 uint8_t p_x : 1; 1638 uint8_t n_x : 1; 1639 uint8_t p_y : 1; 1640 uint8_t n_y : 1; 1641 uint8_t p_z : 1; 1642 uint8_t n_z : 1; 1643 uint8_t p_v : 1; 1644 uint8_t n_v : 1; 1645 #endif /* DRV_BYTE_ORDER */ 1646 } lsm6dso_fsm_outs8_t; 1647 1648 #define LSM6DSO_FSM_OUTS9 0x54U 1649 typedef struct 1650 { 1651 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1652 uint8_t n_v : 1; 1653 uint8_t p_v : 1; 1654 uint8_t n_z : 1; 1655 uint8_t p_z : 1; 1656 uint8_t n_y : 1; 1657 uint8_t p_y : 1; 1658 uint8_t n_x : 1; 1659 uint8_t p_x : 1; 1660 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1661 uint8_t p_x : 1; 1662 uint8_t n_x : 1; 1663 uint8_t p_y : 1; 1664 uint8_t n_y : 1; 1665 uint8_t p_z : 1; 1666 uint8_t n_z : 1; 1667 uint8_t p_v : 1; 1668 uint8_t n_v : 1; 1669 #endif /* DRV_BYTE_ORDER */ 1670 } lsm6dso_fsm_outs9_t; 1671 1672 #define LSM6DSO_FSM_OUTS10 0x55U 1673 typedef struct 1674 { 1675 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1676 uint8_t n_v : 1; 1677 uint8_t p_v : 1; 1678 uint8_t n_z : 1; 1679 uint8_t p_z : 1; 1680 uint8_t n_y : 1; 1681 uint8_t p_y : 1; 1682 uint8_t n_x : 1; 1683 uint8_t p_x : 1; 1684 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1685 uint8_t p_x : 1; 1686 uint8_t n_x : 1; 1687 uint8_t p_y : 1; 1688 uint8_t n_y : 1; 1689 uint8_t p_z : 1; 1690 uint8_t n_z : 1; 1691 uint8_t p_v : 1; 1692 uint8_t n_v : 1; 1693 #endif /* DRV_BYTE_ORDER */ 1694 } lsm6dso_fsm_outs10_t; 1695 1696 #define LSM6DSO_FSM_OUTS11 0x56U 1697 typedef struct 1698 { 1699 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1700 uint8_t n_v : 1; 1701 uint8_t p_v : 1; 1702 uint8_t n_z : 1; 1703 uint8_t p_z : 1; 1704 uint8_t n_y : 1; 1705 uint8_t p_y : 1; 1706 uint8_t n_x : 1; 1707 uint8_t p_x : 1; 1708 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1709 uint8_t p_x : 1; 1710 uint8_t n_x : 1; 1711 uint8_t p_y : 1; 1712 uint8_t n_y : 1; 1713 uint8_t p_z : 1; 1714 uint8_t n_z : 1; 1715 uint8_t p_v : 1; 1716 uint8_t n_v : 1; 1717 #endif /* DRV_BYTE_ORDER */ 1718 } lsm6dso_fsm_outs11_t; 1719 1720 #define LSM6DSO_FSM_OUTS12 0x57U 1721 typedef struct 1722 { 1723 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1724 uint8_t n_v : 1; 1725 uint8_t p_v : 1; 1726 uint8_t n_z : 1; 1727 uint8_t p_z : 1; 1728 uint8_t n_y : 1; 1729 uint8_t p_y : 1; 1730 uint8_t n_x : 1; 1731 uint8_t p_x : 1; 1732 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1733 uint8_t p_x : 1; 1734 uint8_t n_x : 1; 1735 uint8_t p_y : 1; 1736 uint8_t n_y : 1; 1737 uint8_t p_z : 1; 1738 uint8_t n_z : 1; 1739 uint8_t p_v : 1; 1740 uint8_t n_v : 1; 1741 #endif /* DRV_BYTE_ORDER */ 1742 } lsm6dso_fsm_outs12_t; 1743 1744 #define LSM6DSO_FSM_OUTS13 0x58U 1745 typedef struct 1746 { 1747 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1748 uint8_t n_v : 1; 1749 uint8_t p_v : 1; 1750 uint8_t n_z : 1; 1751 uint8_t p_z : 1; 1752 uint8_t n_y : 1; 1753 uint8_t p_y : 1; 1754 uint8_t n_x : 1; 1755 uint8_t p_x : 1; 1756 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1757 uint8_t p_x : 1; 1758 uint8_t n_x : 1; 1759 uint8_t p_y : 1; 1760 uint8_t n_y : 1; 1761 uint8_t p_z : 1; 1762 uint8_t n_z : 1; 1763 uint8_t p_v : 1; 1764 uint8_t n_v : 1; 1765 #endif /* DRV_BYTE_ORDER */ 1766 } lsm6dso_fsm_outs13_t; 1767 1768 #define LSM6DSO_FSM_OUTS14 0x59U 1769 typedef struct 1770 { 1771 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1772 uint8_t n_v : 1; 1773 uint8_t p_v : 1; 1774 uint8_t n_z : 1; 1775 uint8_t p_z : 1; 1776 uint8_t n_y : 1; 1777 uint8_t p_y : 1; 1778 uint8_t n_x : 1; 1779 uint8_t p_x : 1; 1780 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1781 uint8_t p_x : 1; 1782 uint8_t n_x : 1; 1783 uint8_t p_y : 1; 1784 uint8_t n_y : 1; 1785 uint8_t p_z : 1; 1786 uint8_t n_z : 1; 1787 uint8_t p_v : 1; 1788 uint8_t n_v : 1; 1789 #endif /* DRV_BYTE_ORDER */ 1790 } lsm6dso_fsm_outs14_t; 1791 1792 #define LSM6DSO_FSM_OUTS15 0x5AU 1793 typedef struct 1794 { 1795 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1796 uint8_t n_v : 1; 1797 uint8_t p_v : 1; 1798 uint8_t n_z : 1; 1799 uint8_t p_z : 1; 1800 uint8_t n_y : 1; 1801 uint8_t p_y : 1; 1802 uint8_t n_x : 1; 1803 uint8_t p_x : 1; 1804 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1805 uint8_t p_x : 1; 1806 uint8_t n_x : 1; 1807 uint8_t p_y : 1; 1808 uint8_t n_y : 1; 1809 uint8_t p_z : 1; 1810 uint8_t n_z : 1; 1811 uint8_t p_v : 1; 1812 uint8_t n_v : 1; 1813 #endif /* DRV_BYTE_ORDER */ 1814 } lsm6dso_fsm_outs15_t; 1815 1816 #define LSM6DSO_FSM_OUTS16 0x5BU 1817 typedef struct 1818 { 1819 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1820 uint8_t n_v : 1; 1821 uint8_t p_v : 1; 1822 uint8_t n_z : 1; 1823 uint8_t p_z : 1; 1824 uint8_t n_y : 1; 1825 uint8_t p_y : 1; 1826 uint8_t n_x : 1; 1827 uint8_t p_x : 1; 1828 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1829 uint8_t p_x : 1; 1830 uint8_t n_x : 1; 1831 uint8_t p_y : 1; 1832 uint8_t n_y : 1; 1833 uint8_t p_z : 1; 1834 uint8_t n_z : 1; 1835 uint8_t p_v : 1; 1836 uint8_t n_v : 1; 1837 #endif /* DRV_BYTE_ORDER */ 1838 } lsm6dso_fsm_outs16_t; 1839 1840 #define LSM6DSO_EMB_FUNC_ODR_CFG_B 0x5FU 1841 typedef struct 1842 { 1843 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1844 uint8_t not_used_01 : 3; 1845 uint8_t fsm_odr : 2; 1846 uint8_t not_used_02 : 3; 1847 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1848 uint8_t not_used_02 : 3; 1849 uint8_t fsm_odr : 2; 1850 uint8_t not_used_01 : 3; 1851 #endif /* DRV_BYTE_ORDER */ 1852 } lsm6dso_emb_func_odr_cfg_b_t; 1853 1854 #define LSM6DSO_STEP_COUNTER_L 0x62U 1855 #define LSM6DSO_STEP_COUNTER_H 0x63U 1856 #define LSM6DSO_EMB_FUNC_SRC 0x64U 1857 typedef struct 1858 { 1859 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1860 uint8_t not_used_01 : 2; 1861 uint8_t stepcounter_bit_set : 1; 1862 uint8_t step_overflow : 1; 1863 uint8_t step_count_delta_ia : 1; 1864 uint8_t step_detected : 1; 1865 uint8_t not_used_02 : 1; 1866 uint8_t pedo_rst_step : 1; 1867 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1868 uint8_t pedo_rst_step : 1; 1869 uint8_t not_used_02 : 1; 1870 uint8_t step_detected : 1; 1871 uint8_t step_count_delta_ia : 1; 1872 uint8_t step_overflow : 1; 1873 uint8_t stepcounter_bit_set : 1; 1874 uint8_t not_used_01 : 2; 1875 #endif /* DRV_BYTE_ORDER */ 1876 } lsm6dso_emb_func_src_t; 1877 1878 #define LSM6DSO_EMB_FUNC_INIT_A 0x66U 1879 typedef struct 1880 { 1881 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1882 uint8_t not_used_01 : 3; 1883 uint8_t step_det_init : 1; 1884 uint8_t tilt_init : 1; 1885 uint8_t sig_mot_init : 1; 1886 uint8_t not_used_02 : 2; 1887 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1888 uint8_t not_used_02 : 2; 1889 uint8_t sig_mot_init : 1; 1890 uint8_t tilt_init : 1; 1891 uint8_t step_det_init : 1; 1892 uint8_t not_used_01 : 3; 1893 #endif /* DRV_BYTE_ORDER */ 1894 } lsm6dso_emb_func_init_a_t; 1895 1896 #define LSM6DSO_EMB_FUNC_INIT_B 0x67U 1897 typedef struct 1898 { 1899 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1900 uint8_t fsm_init : 1; 1901 uint8_t not_used_01 : 2; 1902 uint8_t fifo_compr_init : 1; 1903 uint8_t not_used_02 : 4; 1904 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1905 uint8_t not_used_02 : 4; 1906 uint8_t fifo_compr_init : 1; 1907 uint8_t not_used_01 : 2; 1908 uint8_t fsm_init : 1; 1909 #endif /* DRV_BYTE_ORDER */ 1910 } lsm6dso_emb_func_init_b_t; 1911 1912 #define LSM6DSO_MAG_SENSITIVITY_L 0xBAU 1913 #define LSM6DSO_MAG_SENSITIVITY_H 0xBBU 1914 #define LSM6DSO_MAG_OFFX_L 0xC0U 1915 #define LSM6DSO_MAG_OFFX_H 0xC1U 1916 #define LSM6DSO_MAG_OFFY_L 0xC2U 1917 #define LSM6DSO_MAG_OFFY_H 0xC3U 1918 #define LSM6DSO_MAG_OFFZ_L 0xC4U 1919 #define LSM6DSO_MAG_OFFZ_H 0xC5U 1920 #define LSM6DSO_MAG_SI_XX_L 0xC6U 1921 #define LSM6DSO_MAG_SI_XX_H 0xC7U 1922 #define LSM6DSO_MAG_SI_XY_L 0xC8U 1923 #define LSM6DSO_MAG_SI_XY_H 0xC9U 1924 #define LSM6DSO_MAG_SI_XZ_L 0xCAU 1925 #define LSM6DSO_MAG_SI_XZ_H 0xCBU 1926 #define LSM6DSO_MAG_SI_YY_L 0xCCU 1927 #define LSM6DSO_MAG_SI_YY_H 0xCDU 1928 #define LSM6DSO_MAG_SI_YZ_L 0xCEU 1929 #define LSM6DSO_MAG_SI_YZ_H 0xCFU 1930 #define LSM6DSO_MAG_SI_ZZ_L 0xD0U 1931 #define LSM6DSO_MAG_SI_ZZ_H 0xD1U 1932 #define LSM6DSO_MAG_CFG_A 0xD4U 1933 typedef struct 1934 { 1935 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1936 uint8_t mag_z_axis : 3; 1937 uint8_t not_used_01 : 1; 1938 uint8_t mag_y_axis : 3; 1939 uint8_t not_used_02 : 1; 1940 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1941 uint8_t not_used_02 : 1; 1942 uint8_t mag_y_axis : 3; 1943 uint8_t not_used_01 : 1; 1944 uint8_t mag_z_axis : 3; 1945 #endif /* DRV_BYTE_ORDER */ 1946 } lsm6dso_mag_cfg_a_t; 1947 1948 #define LSM6DSO_MAG_CFG_B 0xD5U 1949 typedef struct 1950 { 1951 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1952 uint8_t mag_x_axis : 3; 1953 uint8_t not_used_01 : 5; 1954 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1955 uint8_t not_used_01 : 5; 1956 uint8_t mag_x_axis : 3; 1957 #endif /* DRV_BYTE_ORDER */ 1958 } lsm6dso_mag_cfg_b_t; 1959 1960 #define LSM6DSO_FSM_LC_TIMEOUT_L 0x17AU 1961 #define LSM6DSO_FSM_LC_TIMEOUT_H 0x17BU 1962 #define LSM6DSO_FSM_PROGRAMS 0x17CU 1963 #define LSM6DSO_FSM_START_ADD_L 0x17EU 1964 #define LSM6DSO_FSM_START_ADD_H 0x17FU 1965 #define LSM6DSO_PEDO_CMD_REG 0x183U 1966 typedef struct 1967 { 1968 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1969 uint8_t ad_det_en : 1; 1970 uint8_t not_used_01 : 1; 1971 uint8_t fp_rejection_en : 1; 1972 uint8_t carry_count_en : 1; 1973 uint8_t not_used_02 : 4; 1974 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1975 uint8_t not_used_02 : 4; 1976 uint8_t carry_count_en : 1; 1977 uint8_t fp_rejection_en : 1; 1978 uint8_t not_used_01 : 1; 1979 uint8_t ad_det_en : 1; 1980 #endif /* DRV_BYTE_ORDER */ 1981 } lsm6dso_pedo_cmd_reg_t; 1982 1983 #define LSM6DSO_PEDO_DEB_STEPS_CONF 0x184U 1984 #define LSM6DSO_PEDO_SC_DELTAT_L 0x1D0U 1985 #define LSM6DSO_PEDO_SC_DELTAT_H 0x1D1U 1986 #define LSM6DSO_SENSOR_HUB_1 0x02U 1987 typedef struct 1988 { 1989 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1990 uint8_t bit0 : 1; 1991 uint8_t bit1 : 1; 1992 uint8_t bit2 : 1; 1993 uint8_t bit3 : 1; 1994 uint8_t bit4 : 1; 1995 uint8_t bit5 : 1; 1996 uint8_t bit6 : 1; 1997 uint8_t bit7 : 1; 1998 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1999 uint8_t bit7 : 1; 2000 uint8_t bit6 : 1; 2001 uint8_t bit5 : 1; 2002 uint8_t bit4 : 1; 2003 uint8_t bit3 : 1; 2004 uint8_t bit2 : 1; 2005 uint8_t bit1 : 1; 2006 uint8_t bit0 : 1; 2007 #endif /* DRV_BYTE_ORDER */ 2008 } lsm6dso_sensor_hub_1_t; 2009 2010 #define LSM6DSO_SENSOR_HUB_2 0x03U 2011 typedef struct 2012 { 2013 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2014 uint8_t bit0 : 1; 2015 uint8_t bit1 : 1; 2016 uint8_t bit2 : 1; 2017 uint8_t bit3 : 1; 2018 uint8_t bit4 : 1; 2019 uint8_t bit5 : 1; 2020 uint8_t bit6 : 1; 2021 uint8_t bit7 : 1; 2022 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2023 uint8_t bit7 : 1; 2024 uint8_t bit6 : 1; 2025 uint8_t bit5 : 1; 2026 uint8_t bit4 : 1; 2027 uint8_t bit3 : 1; 2028 uint8_t bit2 : 1; 2029 uint8_t bit1 : 1; 2030 uint8_t bit0 : 1; 2031 #endif /* DRV_BYTE_ORDER */ 2032 } lsm6dso_sensor_hub_2_t; 2033 2034 #define LSM6DSO_SENSOR_HUB_3 0x04U 2035 typedef struct 2036 { 2037 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2038 uint8_t bit0 : 1; 2039 uint8_t bit1 : 1; 2040 uint8_t bit2 : 1; 2041 uint8_t bit3 : 1; 2042 uint8_t bit4 : 1; 2043 uint8_t bit5 : 1; 2044 uint8_t bit6 : 1; 2045 uint8_t bit7 : 1; 2046 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2047 uint8_t bit7 : 1; 2048 uint8_t bit6 : 1; 2049 uint8_t bit5 : 1; 2050 uint8_t bit4 : 1; 2051 uint8_t bit3 : 1; 2052 uint8_t bit2 : 1; 2053 uint8_t bit1 : 1; 2054 uint8_t bit0 : 1; 2055 #endif /* DRV_BYTE_ORDER */ 2056 } lsm6dso_sensor_hub_3_t; 2057 2058 #define LSM6DSO_SENSOR_HUB_4 0x05U 2059 typedef struct 2060 { 2061 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2062 uint8_t bit0 : 1; 2063 uint8_t bit1 : 1; 2064 uint8_t bit2 : 1; 2065 uint8_t bit3 : 1; 2066 uint8_t bit4 : 1; 2067 uint8_t bit5 : 1; 2068 uint8_t bit6 : 1; 2069 uint8_t bit7 : 1; 2070 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2071 uint8_t bit7 : 1; 2072 uint8_t bit6 : 1; 2073 uint8_t bit5 : 1; 2074 uint8_t bit4 : 1; 2075 uint8_t bit3 : 1; 2076 uint8_t bit2 : 1; 2077 uint8_t bit1 : 1; 2078 uint8_t bit0 : 1; 2079 #endif /* DRV_BYTE_ORDER */ 2080 } lsm6dso_sensor_hub_4_t; 2081 2082 #define LSM6DSO_SENSOR_HUB_5 0x06U 2083 typedef struct 2084 { 2085 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2086 uint8_t bit0 : 1; 2087 uint8_t bit1 : 1; 2088 uint8_t bit2 : 1; 2089 uint8_t bit3 : 1; 2090 uint8_t bit4 : 1; 2091 uint8_t bit5 : 1; 2092 uint8_t bit6 : 1; 2093 uint8_t bit7 : 1; 2094 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2095 uint8_t bit7 : 1; 2096 uint8_t bit6 : 1; 2097 uint8_t bit5 : 1; 2098 uint8_t bit4 : 1; 2099 uint8_t bit3 : 1; 2100 uint8_t bit2 : 1; 2101 uint8_t bit1 : 1; 2102 uint8_t bit0 : 1; 2103 #endif /* DRV_BYTE_ORDER */ 2104 } lsm6dso_sensor_hub_5_t; 2105 2106 #define LSM6DSO_SENSOR_HUB_6 0x07U 2107 typedef struct 2108 { 2109 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2110 uint8_t bit0 : 1; 2111 uint8_t bit1 : 1; 2112 uint8_t bit2 : 1; 2113 uint8_t bit3 : 1; 2114 uint8_t bit4 : 1; 2115 uint8_t bit5 : 1; 2116 uint8_t bit6 : 1; 2117 uint8_t bit7 : 1; 2118 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2119 uint8_t bit7 : 1; 2120 uint8_t bit6 : 1; 2121 uint8_t bit5 : 1; 2122 uint8_t bit4 : 1; 2123 uint8_t bit3 : 1; 2124 uint8_t bit2 : 1; 2125 uint8_t bit1 : 1; 2126 uint8_t bit0 : 1; 2127 #endif /* DRV_BYTE_ORDER */ 2128 } lsm6dso_sensor_hub_6_t; 2129 2130 #define LSM6DSO_SENSOR_HUB_7 0x08U 2131 typedef struct 2132 { 2133 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2134 uint8_t bit0 : 1; 2135 uint8_t bit1 : 1; 2136 uint8_t bit2 : 1; 2137 uint8_t bit3 : 1; 2138 uint8_t bit4 : 1; 2139 uint8_t bit5 : 1; 2140 uint8_t bit6 : 1; 2141 uint8_t bit7 : 1; 2142 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2143 uint8_t bit7 : 1; 2144 uint8_t bit6 : 1; 2145 uint8_t bit5 : 1; 2146 uint8_t bit4 : 1; 2147 uint8_t bit3 : 1; 2148 uint8_t bit2 : 1; 2149 uint8_t bit1 : 1; 2150 uint8_t bit0 : 1; 2151 #endif /* DRV_BYTE_ORDER */ 2152 } lsm6dso_sensor_hub_7_t; 2153 2154 #define LSM6DSO_SENSOR_HUB_8 0x09U 2155 typedef struct 2156 { 2157 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2158 uint8_t bit0 : 1; 2159 uint8_t bit1 : 1; 2160 uint8_t bit2 : 1; 2161 uint8_t bit3 : 1; 2162 uint8_t bit4 : 1; 2163 uint8_t bit5 : 1; 2164 uint8_t bit6 : 1; 2165 uint8_t bit7 : 1; 2166 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2167 uint8_t bit7 : 1; 2168 uint8_t bit6 : 1; 2169 uint8_t bit5 : 1; 2170 uint8_t bit4 : 1; 2171 uint8_t bit3 : 1; 2172 uint8_t bit2 : 1; 2173 uint8_t bit1 : 1; 2174 uint8_t bit0 : 1; 2175 #endif /* DRV_BYTE_ORDER */ 2176 } lsm6dso_sensor_hub_8_t; 2177 2178 #define LSM6DSO_SENSOR_HUB_9 0x0AU 2179 typedef struct 2180 { 2181 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2182 uint8_t bit0 : 1; 2183 uint8_t bit1 : 1; 2184 uint8_t bit2 : 1; 2185 uint8_t bit3 : 1; 2186 uint8_t bit4 : 1; 2187 uint8_t bit5 : 1; 2188 uint8_t bit6 : 1; 2189 uint8_t bit7 : 1; 2190 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2191 uint8_t bit7 : 1; 2192 uint8_t bit6 : 1; 2193 uint8_t bit5 : 1; 2194 uint8_t bit4 : 1; 2195 uint8_t bit3 : 1; 2196 uint8_t bit2 : 1; 2197 uint8_t bit1 : 1; 2198 uint8_t bit0 : 1; 2199 #endif /* DRV_BYTE_ORDER */ 2200 } lsm6dso_sensor_hub_9_t; 2201 2202 #define LSM6DSO_SENSOR_HUB_10 0x0BU 2203 typedef struct 2204 { 2205 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2206 uint8_t bit0 : 1; 2207 uint8_t bit1 : 1; 2208 uint8_t bit2 : 1; 2209 uint8_t bit3 : 1; 2210 uint8_t bit4 : 1; 2211 uint8_t bit5 : 1; 2212 uint8_t bit6 : 1; 2213 uint8_t bit7 : 1; 2214 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2215 uint8_t bit7 : 1; 2216 uint8_t bit6 : 1; 2217 uint8_t bit5 : 1; 2218 uint8_t bit4 : 1; 2219 uint8_t bit3 : 1; 2220 uint8_t bit2 : 1; 2221 uint8_t bit1 : 1; 2222 uint8_t bit0 : 1; 2223 #endif /* DRV_BYTE_ORDER */ 2224 } lsm6dso_sensor_hub_10_t; 2225 2226 #define LSM6DSO_SENSOR_HUB_11 0x0CU 2227 typedef struct 2228 { 2229 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2230 uint8_t bit0 : 1; 2231 uint8_t bit1 : 1; 2232 uint8_t bit2 : 1; 2233 uint8_t bit3 : 1; 2234 uint8_t bit4 : 1; 2235 uint8_t bit5 : 1; 2236 uint8_t bit6 : 1; 2237 uint8_t bit7 : 1; 2238 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2239 uint8_t bit7 : 1; 2240 uint8_t bit6 : 1; 2241 uint8_t bit5 : 1; 2242 uint8_t bit4 : 1; 2243 uint8_t bit3 : 1; 2244 uint8_t bit2 : 1; 2245 uint8_t bit1 : 1; 2246 uint8_t bit0 : 1; 2247 #endif /* DRV_BYTE_ORDER */ 2248 } lsm6dso_sensor_hub_11_t; 2249 2250 #define LSM6DSO_SENSOR_HUB_12 0x0DU 2251 typedef struct 2252 { 2253 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2254 uint8_t bit0 : 1; 2255 uint8_t bit1 : 1; 2256 uint8_t bit2 : 1; 2257 uint8_t bit3 : 1; 2258 uint8_t bit4 : 1; 2259 uint8_t bit5 : 1; 2260 uint8_t bit6 : 1; 2261 uint8_t bit7 : 1; 2262 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2263 uint8_t bit7 : 1; 2264 uint8_t bit6 : 1; 2265 uint8_t bit5 : 1; 2266 uint8_t bit4 : 1; 2267 uint8_t bit3 : 1; 2268 uint8_t bit2 : 1; 2269 uint8_t bit1 : 1; 2270 uint8_t bit0 : 1; 2271 #endif /* DRV_BYTE_ORDER */ 2272 } lsm6dso_sensor_hub_12_t; 2273 2274 #define LSM6DSO_SENSOR_HUB_13 0x0EU 2275 typedef struct 2276 { 2277 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2278 uint8_t bit0 : 1; 2279 uint8_t bit1 : 1; 2280 uint8_t bit2 : 1; 2281 uint8_t bit3 : 1; 2282 uint8_t bit4 : 1; 2283 uint8_t bit5 : 1; 2284 uint8_t bit6 : 1; 2285 uint8_t bit7 : 1; 2286 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2287 uint8_t bit7 : 1; 2288 uint8_t bit6 : 1; 2289 uint8_t bit5 : 1; 2290 uint8_t bit4 : 1; 2291 uint8_t bit3 : 1; 2292 uint8_t bit2 : 1; 2293 uint8_t bit1 : 1; 2294 uint8_t bit0 : 1; 2295 #endif /* DRV_BYTE_ORDER */ 2296 } lsm6dso_sensor_hub_13_t; 2297 2298 #define LSM6DSO_SENSOR_HUB_14 0x0FU 2299 typedef struct 2300 { 2301 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2302 uint8_t bit0 : 1; 2303 uint8_t bit1 : 1; 2304 uint8_t bit2 : 1; 2305 uint8_t bit3 : 1; 2306 uint8_t bit4 : 1; 2307 uint8_t bit5 : 1; 2308 uint8_t bit6 : 1; 2309 uint8_t bit7 : 1; 2310 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2311 uint8_t bit7 : 1; 2312 uint8_t bit6 : 1; 2313 uint8_t bit5 : 1; 2314 uint8_t bit4 : 1; 2315 uint8_t bit3 : 1; 2316 uint8_t bit2 : 1; 2317 uint8_t bit1 : 1; 2318 uint8_t bit0 : 1; 2319 #endif /* DRV_BYTE_ORDER */ 2320 } lsm6dso_sensor_hub_14_t; 2321 2322 #define LSM6DSO_SENSOR_HUB_15 0x10U 2323 typedef struct 2324 { 2325 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2326 uint8_t bit0 : 1; 2327 uint8_t bit1 : 1; 2328 uint8_t bit2 : 1; 2329 uint8_t bit3 : 1; 2330 uint8_t bit4 : 1; 2331 uint8_t bit5 : 1; 2332 uint8_t bit6 : 1; 2333 uint8_t bit7 : 1; 2334 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2335 uint8_t bit7 : 1; 2336 uint8_t bit6 : 1; 2337 uint8_t bit5 : 1; 2338 uint8_t bit4 : 1; 2339 uint8_t bit3 : 1; 2340 uint8_t bit2 : 1; 2341 uint8_t bit1 : 1; 2342 uint8_t bit0 : 1; 2343 #endif /* DRV_BYTE_ORDER */ 2344 } lsm6dso_sensor_hub_15_t; 2345 2346 #define LSM6DSO_SENSOR_HUB_16 0x11U 2347 typedef struct 2348 { 2349 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2350 uint8_t bit0 : 1; 2351 uint8_t bit1 : 1; 2352 uint8_t bit2 : 1; 2353 uint8_t bit3 : 1; 2354 uint8_t bit4 : 1; 2355 uint8_t bit5 : 1; 2356 uint8_t bit6 : 1; 2357 uint8_t bit7 : 1; 2358 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2359 uint8_t bit7 : 1; 2360 uint8_t bit6 : 1; 2361 uint8_t bit5 : 1; 2362 uint8_t bit4 : 1; 2363 uint8_t bit3 : 1; 2364 uint8_t bit2 : 1; 2365 uint8_t bit1 : 1; 2366 uint8_t bit0 : 1; 2367 #endif /* DRV_BYTE_ORDER */ 2368 } lsm6dso_sensor_hub_16_t; 2369 2370 #define LSM6DSO_SENSOR_HUB_17 0x12U 2371 typedef struct 2372 { 2373 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2374 uint8_t bit0 : 1; 2375 uint8_t bit1 : 1; 2376 uint8_t bit2 : 1; 2377 uint8_t bit3 : 1; 2378 uint8_t bit4 : 1; 2379 uint8_t bit5 : 1; 2380 uint8_t bit6 : 1; 2381 uint8_t bit7 : 1; 2382 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2383 uint8_t bit7 : 1; 2384 uint8_t bit6 : 1; 2385 uint8_t bit5 : 1; 2386 uint8_t bit4 : 1; 2387 uint8_t bit3 : 1; 2388 uint8_t bit2 : 1; 2389 uint8_t bit1 : 1; 2390 uint8_t bit0 : 1; 2391 #endif /* DRV_BYTE_ORDER */ 2392 } lsm6dso_sensor_hub_17_t; 2393 2394 #define LSM6DSO_SENSOR_HUB_18 0x13U 2395 typedef struct 2396 { 2397 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2398 uint8_t bit0 : 1; 2399 uint8_t bit1 : 1; 2400 uint8_t bit2 : 1; 2401 uint8_t bit3 : 1; 2402 uint8_t bit4 : 1; 2403 uint8_t bit5 : 1; 2404 uint8_t bit6 : 1; 2405 uint8_t bit7 : 1; 2406 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2407 uint8_t bit7 : 1; 2408 uint8_t bit6 : 1; 2409 uint8_t bit5 : 1; 2410 uint8_t bit4 : 1; 2411 uint8_t bit3 : 1; 2412 uint8_t bit2 : 1; 2413 uint8_t bit1 : 1; 2414 uint8_t bit0 : 1; 2415 #endif /* DRV_BYTE_ORDER */ 2416 } lsm6dso_sensor_hub_18_t; 2417 2418 #define LSM6DSO_MASTER_CONFIG 0x14U 2419 typedef struct 2420 { 2421 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2422 uint8_t aux_sens_on : 2; 2423 uint8_t master_on : 1; 2424 uint8_t shub_pu_en : 1; 2425 uint8_t pass_through_mode : 1; 2426 uint8_t start_config : 1; 2427 uint8_t write_once : 1; 2428 uint8_t rst_master_regs : 1; 2429 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2430 uint8_t rst_master_regs : 1; 2431 uint8_t write_once : 1; 2432 uint8_t start_config : 1; 2433 uint8_t pass_through_mode : 1; 2434 uint8_t shub_pu_en : 1; 2435 uint8_t master_on : 1; 2436 uint8_t aux_sens_on : 2; 2437 #endif /* DRV_BYTE_ORDER */ 2438 } lsm6dso_master_config_t; 2439 2440 #define LSM6DSO_SLV0_ADD 0x15U 2441 typedef struct 2442 { 2443 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2444 uint8_t rw_0 : 1; 2445 uint8_t slave0 : 7; 2446 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2447 uint8_t slave0 : 7; 2448 uint8_t rw_0 : 1; 2449 #endif /* DRV_BYTE_ORDER */ 2450 } lsm6dso_slv0_add_t; 2451 2452 #define LSM6DSO_SLV0_SUBADD 0x16U 2453 typedef struct 2454 { 2455 uint8_t slave0_reg : 8; 2456 } lsm6dso_slv0_subadd_t; 2457 2458 #define LSM6DSO_SLV0_CONFIG 0x17U 2459 typedef struct 2460 { 2461 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2462 uint8_t slave0_numop : 3; 2463 uint8_t batch_ext_sens_0_en : 1; 2464 uint8_t not_used_01 : 2; 2465 uint8_t shub_odr : 2; 2466 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2467 uint8_t shub_odr : 2; 2468 uint8_t not_used_01 : 2; 2469 uint8_t batch_ext_sens_0_en : 1; 2470 uint8_t slave0_numop : 3; 2471 #endif /* DRV_BYTE_ORDER */ 2472 } lsm6dso_slv0_config_t; 2473 2474 #define LSM6DSO_SLV1_ADD 0x18U 2475 typedef struct 2476 { 2477 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2478 uint8_t r_1 : 1; 2479 uint8_t slave1_add : 7; 2480 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2481 uint8_t slave1_add : 7; 2482 uint8_t r_1 : 1; 2483 #endif /* DRV_BYTE_ORDER */ 2484 } lsm6dso_slv1_add_t; 2485 2486 #define LSM6DSO_SLV1_SUBADD 0x19U 2487 typedef struct 2488 { 2489 uint8_t slave1_reg : 8; 2490 } lsm6dso_slv1_subadd_t; 2491 2492 #define LSM6DSO_SLV1_CONFIG 0x1AU 2493 typedef struct 2494 { 2495 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2496 uint8_t slave1_numop : 3; 2497 uint8_t batch_ext_sens_1_en : 1; 2498 uint8_t not_used_01 : 4; 2499 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2500 uint8_t not_used_01 : 4; 2501 uint8_t batch_ext_sens_1_en : 1; 2502 uint8_t slave1_numop : 3; 2503 #endif /* DRV_BYTE_ORDER */ 2504 } lsm6dso_slv1_config_t; 2505 2506 #define LSM6DSO_SLV2_ADD 0x1BU 2507 typedef struct 2508 { 2509 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2510 uint8_t r_2 : 1; 2511 uint8_t slave2_add : 7; 2512 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2513 uint8_t slave2_add : 7; 2514 uint8_t r_2 : 1; 2515 #endif /* DRV_BYTE_ORDER */ 2516 } lsm6dso_slv2_add_t; 2517 2518 #define LSM6DSO_SLV2_SUBADD 0x1CU 2519 typedef struct 2520 { 2521 uint8_t slave2_reg : 8; 2522 } lsm6dso_slv2_subadd_t; 2523 2524 #define LSM6DSO_SLV2_CONFIG 0x1DU 2525 typedef struct 2526 { 2527 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2528 uint8_t slave2_numop : 3; 2529 uint8_t batch_ext_sens_2_en : 1; 2530 uint8_t not_used_01 : 4; 2531 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2532 uint8_t not_used_01 : 4; 2533 uint8_t batch_ext_sens_2_en : 1; 2534 uint8_t slave2_numop : 3; 2535 #endif /* DRV_BYTE_ORDER */ 2536 } lsm6dso_slv2_config_t; 2537 2538 #define LSM6DSO_SLV3_ADD 0x1EU 2539 typedef struct 2540 { 2541 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2542 uint8_t r_3 : 1; 2543 uint8_t slave3_add : 7; 2544 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2545 uint8_t slave3_add : 7; 2546 uint8_t r_3 : 1; 2547 #endif /* DRV_BYTE_ORDER */ 2548 } lsm6dso_slv3_add_t; 2549 2550 #define LSM6DSO_SLV3_SUBADD 0x1FU 2551 typedef struct 2552 { 2553 uint8_t slave3_reg : 8; 2554 } lsm6dso_slv3_subadd_t; 2555 2556 #define LSM6DSO_SLV3_CONFIG 0x20U 2557 typedef struct 2558 { 2559 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2560 uint8_t slave3_numop : 3; 2561 uint8_t batch_ext_sens_3_en : 1; 2562 uint8_t not_used_01 : 4; 2563 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2564 uint8_t not_used_01 : 4; 2565 uint8_t batch_ext_sens_3_en : 1; 2566 uint8_t slave3_numop : 3; 2567 #endif /* DRV_BYTE_ORDER */ 2568 } lsm6dso_slv3_config_t; 2569 2570 #define LSM6DSO_DATAWRITE_SLV0 0x21U 2571 typedef struct 2572 { 2573 uint8_t slave0_dataw : 8; 2574 } lsm6dso_datawrite_src_mode_sub_slv0_t; 2575 2576 #define LSM6DSO_STATUS_MASTER 0x22U 2577 typedef struct 2578 { 2579 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2580 uint8_t sens_hub_endop : 1; 2581 uint8_t not_used_01 : 2; 2582 uint8_t slave0_nack : 1; 2583 uint8_t slave1_nack : 1; 2584 uint8_t slave2_nack : 1; 2585 uint8_t slave3_nack : 1; 2586 uint8_t wr_once_done : 1; 2587 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2588 uint8_t wr_once_done : 1; 2589 uint8_t slave3_nack : 1; 2590 uint8_t slave2_nack : 1; 2591 uint8_t slave1_nack : 1; 2592 uint8_t slave0_nack : 1; 2593 uint8_t not_used_01 : 2; 2594 uint8_t sens_hub_endop : 1; 2595 #endif /* DRV_BYTE_ORDER */ 2596 } lsm6dso_status_master_t; 2597 2598 #define LSM6DSO_START_FSM_ADD 0x0400U 2599 2600 /** 2601 * @defgroup LSM6DSO_Register_Union 2602 * @brief This union group all the registers having a bit-field 2603 * description. 2604 * This union is useful but it's not needed by the driver. 2605 * 2606 * REMOVING this union you are compliant with: 2607 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 2608 * 2609 * @{ 2610 * 2611 */ 2612 typedef union 2613 { 2614 lsm6dso_func_cfg_access_t func_cfg_access; 2615 lsm6dso_pin_ctrl_t pin_ctrl; 2616 lsm6dso_fifo_ctrl1_t fifo_ctrl1; 2617 lsm6dso_fifo_ctrl2_t fifo_ctrl2; 2618 lsm6dso_fifo_ctrl3_t fifo_ctrl3; 2619 lsm6dso_fifo_ctrl4_t fifo_ctrl4; 2620 lsm6dso_counter_bdr_reg1_t counter_bdr_reg1; 2621 lsm6dso_counter_bdr_reg2_t counter_bdr_reg2; 2622 lsm6dso_int1_ctrl_t int1_ctrl; 2623 lsm6dso_int2_ctrl_t int2_ctrl; 2624 lsm6dso_ctrl1_xl_t ctrl1_xl; 2625 lsm6dso_ctrl2_g_t ctrl2_g; 2626 lsm6dso_ctrl3_c_t ctrl3_c; 2627 lsm6dso_ctrl4_c_t ctrl4_c; 2628 lsm6dso_ctrl5_c_t ctrl5_c; 2629 lsm6dso_ctrl6_c_t ctrl6_c; 2630 lsm6dso_ctrl7_g_t ctrl7_g; 2631 lsm6dso_ctrl8_xl_t ctrl8_xl; 2632 lsm6dso_ctrl9_xl_t ctrl9_xl; 2633 lsm6dso_ctrl10_c_t ctrl10_c; 2634 lsm6dso_all_int_src_t all_int_src; 2635 lsm6dso_wake_up_src_t wake_up_src; 2636 lsm6dso_tap_src_t tap_src; 2637 lsm6dso_d6d_src_t d6d_src; 2638 lsm6dso_status_reg_t status_reg; 2639 lsm6dso_status_spiaux_t status_spiaux; 2640 lsm6dso_fifo_status1_t fifo_status1; 2641 lsm6dso_fifo_status2_t fifo_status2; 2642 lsm6dso_tap_cfg0_t tap_cfg0; 2643 lsm6dso_tap_cfg1_t tap_cfg1; 2644 lsm6dso_tap_cfg2_t tap_cfg2; 2645 lsm6dso_tap_ths_6d_t tap_ths_6d; 2646 lsm6dso_int_dur2_t int_dur2; 2647 lsm6dso_wake_up_ths_t wake_up_ths; 2648 lsm6dso_wake_up_dur_t wake_up_dur; 2649 lsm6dso_free_fall_t free_fall; 2650 lsm6dso_md1_cfg_t md1_cfg; 2651 lsm6dso_md2_cfg_t md2_cfg; 2652 lsm6dso_i3c_bus_avb_t i3c_bus_avb; 2653 lsm6dso_internal_freq_fine_t internal_freq_fine; 2654 lsm6dso_int_ois_t int_ois; 2655 lsm6dso_ctrl1_ois_t ctrl1_ois; 2656 lsm6dso_ctrl2_ois_t ctrl2_ois; 2657 lsm6dso_ctrl3_ois_t ctrl3_ois; 2658 lsm6dso_fifo_data_out_tag_t fifo_data_out_tag; 2659 lsm6dso_page_sel_t page_sel; 2660 lsm6dso_emb_func_en_a_t emb_func_en_a; 2661 lsm6dso_emb_func_en_b_t emb_func_en_b; 2662 lsm6dso_page_address_t page_address; 2663 lsm6dso_page_value_t page_value; 2664 lsm6dso_emb_func_int1_t emb_func_int1; 2665 lsm6dso_fsm_int1_a_t fsm_int1_a; 2666 lsm6dso_fsm_int1_b_t fsm_int1_b; 2667 lsm6dso_emb_func_int2_t emb_func_int2; 2668 lsm6dso_fsm_int2_a_t fsm_int2_a; 2669 lsm6dso_fsm_int2_b_t fsm_int2_b; 2670 lsm6dso_emb_func_status_t emb_func_status; 2671 lsm6dso_fsm_status_a_t fsm_status_a; 2672 lsm6dso_fsm_status_b_t fsm_status_b; 2673 lsm6dso_page_rw_t page_rw; 2674 lsm6dso_emb_func_fifo_cfg_t emb_func_fifo_cfg; 2675 lsm6dso_fsm_enable_a_t fsm_enable_a; 2676 lsm6dso_fsm_enable_b_t fsm_enable_b; 2677 lsm6dso_fsm_long_counter_clear_t fsm_long_counter_clear; 2678 lsm6dso_fsm_outs1_t fsm_outs1; 2679 lsm6dso_fsm_outs2_t fsm_outs2; 2680 lsm6dso_fsm_outs3_t fsm_outs3; 2681 lsm6dso_fsm_outs4_t fsm_outs4; 2682 lsm6dso_fsm_outs5_t fsm_outs5; 2683 lsm6dso_fsm_outs6_t fsm_outs6; 2684 lsm6dso_fsm_outs7_t fsm_outs7; 2685 lsm6dso_fsm_outs8_t fsm_outs8; 2686 lsm6dso_fsm_outs9_t fsm_outs9; 2687 lsm6dso_fsm_outs10_t fsm_outs10; 2688 lsm6dso_fsm_outs11_t fsm_outs11; 2689 lsm6dso_fsm_outs12_t fsm_outs12; 2690 lsm6dso_fsm_outs13_t fsm_outs13; 2691 lsm6dso_fsm_outs14_t fsm_outs14; 2692 lsm6dso_fsm_outs15_t fsm_outs15; 2693 lsm6dso_fsm_outs16_t fsm_outs16; 2694 lsm6dso_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; 2695 lsm6dso_emb_func_src_t emb_func_src; 2696 lsm6dso_emb_func_init_a_t emb_func_init_a; 2697 lsm6dso_emb_func_init_b_t emb_func_init_b; 2698 lsm6dso_mag_cfg_a_t mag_cfg_a; 2699 lsm6dso_mag_cfg_b_t mag_cfg_b; 2700 lsm6dso_pedo_cmd_reg_t pedo_cmd_reg; 2701 lsm6dso_sensor_hub_1_t sensor_hub_1; 2702 lsm6dso_sensor_hub_2_t sensor_hub_2; 2703 lsm6dso_sensor_hub_3_t sensor_hub_3; 2704 lsm6dso_sensor_hub_4_t sensor_hub_4; 2705 lsm6dso_sensor_hub_5_t sensor_hub_5; 2706 lsm6dso_sensor_hub_6_t sensor_hub_6; 2707 lsm6dso_sensor_hub_7_t sensor_hub_7; 2708 lsm6dso_sensor_hub_8_t sensor_hub_8; 2709 lsm6dso_sensor_hub_9_t sensor_hub_9; 2710 lsm6dso_sensor_hub_10_t sensor_hub_10; 2711 lsm6dso_sensor_hub_11_t sensor_hub_11; 2712 lsm6dso_sensor_hub_12_t sensor_hub_12; 2713 lsm6dso_sensor_hub_13_t sensor_hub_13; 2714 lsm6dso_sensor_hub_14_t sensor_hub_14; 2715 lsm6dso_sensor_hub_15_t sensor_hub_15; 2716 lsm6dso_sensor_hub_16_t sensor_hub_16; 2717 lsm6dso_sensor_hub_17_t sensor_hub_17; 2718 lsm6dso_sensor_hub_18_t sensor_hub_18; 2719 lsm6dso_master_config_t master_config; 2720 lsm6dso_slv0_add_t slv0_add; 2721 lsm6dso_slv0_subadd_t slv0_subadd; 2722 lsm6dso_slv0_config_t slv0_config; 2723 lsm6dso_slv1_add_t slv1_add; 2724 lsm6dso_slv1_subadd_t slv1_subadd; 2725 lsm6dso_slv1_config_t slv1_config; 2726 lsm6dso_slv2_add_t slv2_add; 2727 lsm6dso_slv2_subadd_t slv2_subadd; 2728 lsm6dso_slv2_config_t slv2_config; 2729 lsm6dso_slv3_add_t slv3_add; 2730 lsm6dso_slv3_subadd_t slv3_subadd; 2731 lsm6dso_slv3_config_t slv3_config; 2732 lsm6dso_datawrite_src_mode_sub_slv0_t datawrite_src_mode_sub_slv0; 2733 lsm6dso_status_master_t status_master; 2734 bitwise_t bitwise; 2735 uint8_t byte; 2736 } lsm6dso_reg_t; 2737 2738 /** 2739 * @} 2740 * 2741 */ 2742 2743 float_t lsm6dso_from_fs2_to_mg(int16_t lsb); 2744 float_t lsm6dso_from_fs4_to_mg(int16_t lsb); 2745 float_t lsm6dso_from_fs8_to_mg(int16_t lsb); 2746 float_t lsm6dso_from_fs16_to_mg(int16_t lsb); 2747 2748 float_t lsm6dso_from_fs125_to_mdps(int16_t lsb); 2749 float_t lsm6dso_from_fs500_to_mdps(int16_t lsb); 2750 float_t lsm6dso_from_fs250_to_mdps(int16_t lsb); 2751 float_t lsm6dso_from_fs1000_to_mdps(int16_t lsb); 2752 float_t lsm6dso_from_fs2000_to_mdps(int16_t lsb); 2753 2754 float_t lsm6dso_from_lsb_to_celsius(int16_t lsb); 2755 2756 float_t lsm6dso_from_lsb_to_nsec(int16_t lsb); 2757 2758 typedef enum 2759 { 2760 LSM6DSO_2g = 0, 2761 LSM6DSO_16g = 1, /* if XL_FS_MODE = '1' -> LSM6DSO_2g */ 2762 LSM6DSO_4g = 2, 2763 LSM6DSO_8g = 3, 2764 } lsm6dso_fs_xl_t; 2765 int32_t lsm6dso_xl_full_scale_set(stmdev_ctx_t *ctx, 2766 lsm6dso_fs_xl_t val); 2767 int32_t lsm6dso_xl_full_scale_get(stmdev_ctx_t *ctx, 2768 lsm6dso_fs_xl_t *val); 2769 2770 typedef enum 2771 { 2772 LSM6DSO_XL_ODR_OFF = 0, 2773 LSM6DSO_XL_ODR_12Hz5 = 1, 2774 LSM6DSO_XL_ODR_26Hz = 2, 2775 LSM6DSO_XL_ODR_52Hz = 3, 2776 LSM6DSO_XL_ODR_104Hz = 4, 2777 LSM6DSO_XL_ODR_208Hz = 5, 2778 LSM6DSO_XL_ODR_417Hz = 6, 2779 LSM6DSO_XL_ODR_833Hz = 7, 2780 LSM6DSO_XL_ODR_1667Hz = 8, 2781 LSM6DSO_XL_ODR_3333Hz = 9, 2782 LSM6DSO_XL_ODR_6667Hz = 10, 2783 LSM6DSO_XL_ODR_1Hz6 = 11, /* (low power only) */ 2784 } lsm6dso_odr_xl_t; 2785 int32_t lsm6dso_xl_data_rate_set(stmdev_ctx_t *ctx, 2786 lsm6dso_odr_xl_t val); 2787 int32_t lsm6dso_xl_data_rate_get(stmdev_ctx_t *ctx, 2788 lsm6dso_odr_xl_t *val); 2789 2790 typedef enum 2791 { 2792 LSM6DSO_250dps = 0, 2793 LSM6DSO_125dps = 1, 2794 LSM6DSO_500dps = 2, 2795 LSM6DSO_1000dps = 4, 2796 LSM6DSO_2000dps = 6, 2797 } lsm6dso_fs_g_t; 2798 int32_t lsm6dso_gy_full_scale_set(stmdev_ctx_t *ctx, 2799 lsm6dso_fs_g_t val); 2800 int32_t lsm6dso_gy_full_scale_get(stmdev_ctx_t *ctx, 2801 lsm6dso_fs_g_t *val); 2802 2803 typedef enum 2804 { 2805 LSM6DSO_GY_ODR_OFF = 0, 2806 LSM6DSO_GY_ODR_12Hz5 = 1, 2807 LSM6DSO_GY_ODR_26Hz = 2, 2808 LSM6DSO_GY_ODR_52Hz = 3, 2809 LSM6DSO_GY_ODR_104Hz = 4, 2810 LSM6DSO_GY_ODR_208Hz = 5, 2811 LSM6DSO_GY_ODR_417Hz = 6, 2812 LSM6DSO_GY_ODR_833Hz = 7, 2813 LSM6DSO_GY_ODR_1667Hz = 8, 2814 LSM6DSO_GY_ODR_3333Hz = 9, 2815 LSM6DSO_GY_ODR_6667Hz = 10, 2816 } lsm6dso_odr_g_t; 2817 int32_t lsm6dso_gy_data_rate_set(stmdev_ctx_t *ctx, 2818 lsm6dso_odr_g_t val); 2819 int32_t lsm6dso_gy_data_rate_get(stmdev_ctx_t *ctx, 2820 lsm6dso_odr_g_t *val); 2821 2822 int32_t lsm6dso_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); 2823 int32_t lsm6dso_block_data_update_get(stmdev_ctx_t *ctx, 2824 uint8_t *val); 2825 2826 typedef enum 2827 { 2828 LSM6DSO_LSb_1mg = 0, 2829 LSM6DSO_LSb_16mg = 1, 2830 } lsm6dso_usr_off_w_t; 2831 int32_t lsm6dso_xl_offset_weight_set(stmdev_ctx_t *ctx, 2832 lsm6dso_usr_off_w_t val); 2833 int32_t lsm6dso_xl_offset_weight_get(stmdev_ctx_t *ctx, 2834 lsm6dso_usr_off_w_t *val); 2835 2836 typedef enum 2837 { 2838 LSM6DSO_HIGH_PERFORMANCE_MD = 0, 2839 LSM6DSO_LOW_NORMAL_POWER_MD = 1, 2840 LSM6DSO_ULTRA_LOW_POWER_MD = 2, 2841 } lsm6dso_xl_hm_mode_t; 2842 int32_t lsm6dso_xl_power_mode_set(stmdev_ctx_t *ctx, 2843 lsm6dso_xl_hm_mode_t val); 2844 int32_t lsm6dso_xl_power_mode_get(stmdev_ctx_t *ctx, 2845 lsm6dso_xl_hm_mode_t *val); 2846 2847 typedef enum 2848 { 2849 LSM6DSO_GY_HIGH_PERFORMANCE = 0, 2850 LSM6DSO_GY_NORMAL = 1, 2851 } lsm6dso_g_hm_mode_t; 2852 int32_t lsm6dso_gy_power_mode_set(stmdev_ctx_t *ctx, 2853 lsm6dso_g_hm_mode_t val); 2854 int32_t lsm6dso_gy_power_mode_get(stmdev_ctx_t *ctx, 2855 lsm6dso_g_hm_mode_t *val); 2856 2857 int32_t lsm6dso_status_reg_get(stmdev_ctx_t *ctx, 2858 lsm6dso_status_reg_t *val); 2859 2860 int32_t lsm6dso_xl_flag_data_ready_get(stmdev_ctx_t *ctx, 2861 uint8_t *val); 2862 2863 int32_t lsm6dso_gy_flag_data_ready_get(stmdev_ctx_t *ctx, 2864 uint8_t *val); 2865 2866 int32_t lsm6dso_temp_flag_data_ready_get(stmdev_ctx_t *ctx, 2867 uint8_t *val); 2868 2869 int32_t lsm6dso_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff); 2870 int32_t lsm6dso_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff); 2871 2872 int32_t lsm6dso_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff); 2873 int32_t lsm6dso_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff); 2874 2875 int32_t lsm6dso_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff); 2876 int32_t lsm6dso_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff); 2877 2878 int32_t lsm6dso_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val); 2879 int32_t lsm6dso_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val); 2880 2881 int32_t lsm6dso_timestamp_rst(stmdev_ctx_t *ctx); 2882 2883 int32_t lsm6dso_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); 2884 int32_t lsm6dso_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); 2885 2886 int32_t lsm6dso_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val); 2887 2888 typedef enum 2889 { 2890 LSM6DSO_NO_ROUND = 0, 2891 LSM6DSO_ROUND_XL = 1, 2892 LSM6DSO_ROUND_GY = 2, 2893 LSM6DSO_ROUND_GY_XL = 3, 2894 } lsm6dso_rounding_t; 2895 int32_t lsm6dso_rounding_mode_set(stmdev_ctx_t *ctx, 2896 lsm6dso_rounding_t val); 2897 int32_t lsm6dso_rounding_mode_get(stmdev_ctx_t *ctx, 2898 lsm6dso_rounding_t *val); 2899 2900 int32_t lsm6dso_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); 2901 2902 int32_t lsm6dso_angular_rate_raw_get(stmdev_ctx_t *ctx, 2903 int16_t *val); 2904 2905 int32_t lsm6dso_acceleration_raw_get(stmdev_ctx_t *ctx, 2906 int16_t *val); 2907 2908 int32_t lsm6dso_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff); 2909 2910 int32_t lsm6dso_number_of_steps_get(stmdev_ctx_t *ctx, uint16_t *val); 2911 2912 int32_t lsm6dso_steps_reset(stmdev_ctx_t *ctx); 2913 2914 int32_t lsm6dso_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val); 2915 int32_t lsm6dso_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val); 2916 2917 typedef enum 2918 { 2919 LSM6DSO_USER_BANK = 0, 2920 LSM6DSO_SENSOR_HUB_BANK = 1, 2921 LSM6DSO_EMBEDDED_FUNC_BANK = 2, 2922 } lsm6dso_reg_access_t; 2923 int32_t lsm6dso_mem_bank_set(stmdev_ctx_t *ctx, 2924 lsm6dso_reg_access_t val); 2925 int32_t lsm6dso_mem_bank_get(stmdev_ctx_t *ctx, 2926 lsm6dso_reg_access_t *val); 2927 2928 int32_t lsm6dso_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t address, 2929 uint8_t *val); 2930 int32_t lsm6dso_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t address, 2931 uint8_t *val); 2932 int32_t lsm6dso_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, 2933 uint8_t *buf, uint8_t len); 2934 int32_t lsm6dso_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, 2935 uint8_t *val); 2936 2937 typedef enum 2938 { 2939 LSM6DSO_DRDY_LATCHED = 0, 2940 LSM6DSO_DRDY_PULSED = 1, 2941 } lsm6dso_dataready_pulsed_t; 2942 int32_t lsm6dso_data_ready_mode_set(stmdev_ctx_t *ctx, 2943 lsm6dso_dataready_pulsed_t val); 2944 int32_t lsm6dso_data_ready_mode_get(stmdev_ctx_t *ctx, 2945 lsm6dso_dataready_pulsed_t *val); 2946 2947 int32_t lsm6dso_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); 2948 2949 int32_t lsm6dso_reset_set(stmdev_ctx_t *ctx, uint8_t val); 2950 int32_t lsm6dso_reset_get(stmdev_ctx_t *ctx, uint8_t *val); 2951 2952 int32_t lsm6dso_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); 2953 int32_t lsm6dso_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); 2954 2955 int32_t lsm6dso_boot_set(stmdev_ctx_t *ctx, uint8_t val); 2956 int32_t lsm6dso_boot_get(stmdev_ctx_t *ctx, uint8_t *val); 2957 2958 typedef enum 2959 { 2960 LSM6DSO_XL_ST_DISABLE = 0, 2961 LSM6DSO_XL_ST_POSITIVE = 1, 2962 LSM6DSO_XL_ST_NEGATIVE = 2, 2963 } lsm6dso_st_xl_t; 2964 int32_t lsm6dso_xl_self_test_set(stmdev_ctx_t *ctx, 2965 lsm6dso_st_xl_t val); 2966 int32_t lsm6dso_xl_self_test_get(stmdev_ctx_t *ctx, 2967 lsm6dso_st_xl_t *val); 2968 2969 typedef enum 2970 { 2971 LSM6DSO_GY_ST_DISABLE = 0, 2972 LSM6DSO_GY_ST_POSITIVE = 1, 2973 LSM6DSO_GY_ST_NEGATIVE = 3, 2974 } lsm6dso_st_g_t; 2975 int32_t lsm6dso_gy_self_test_set(stmdev_ctx_t *ctx, 2976 lsm6dso_st_g_t val); 2977 int32_t lsm6dso_gy_self_test_get(stmdev_ctx_t *ctx, 2978 lsm6dso_st_g_t *val); 2979 2980 int32_t lsm6dso_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val); 2981 int32_t lsm6dso_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val); 2982 2983 int32_t lsm6dso_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val); 2984 int32_t lsm6dso_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val); 2985 2986 int32_t lsm6dso_filter_settling_mask_set(stmdev_ctx_t *ctx, 2987 uint8_t val); 2988 int32_t lsm6dso_filter_settling_mask_get(stmdev_ctx_t *ctx, 2989 uint8_t *val); 2990 2991 typedef enum 2992 { 2993 LSM6DSO_ULTRA_LIGHT = 0, 2994 LSM6DSO_VERY_LIGHT = 1, 2995 LSM6DSO_LIGHT = 2, 2996 LSM6DSO_MEDIUM = 3, 2997 LSM6DSO_STRONG = 4, /* not available for data rate > 1k670Hz */ 2998 LSM6DSO_VERY_STRONG = 5, /* not available for data rate > 1k670Hz */ 2999 LSM6DSO_AGGRESSIVE = 6, /* not available for data rate > 1k670Hz */ 3000 LSM6DSO_XTREME = 7, /* not available for data rate > 1k670Hz */ 3001 } lsm6dso_ftype_t; 3002 int32_t lsm6dso_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, 3003 lsm6dso_ftype_t val); 3004 int32_t lsm6dso_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, 3005 lsm6dso_ftype_t *val); 3006 3007 int32_t lsm6dso_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val); 3008 int32_t lsm6dso_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val); 3009 3010 typedef enum 3011 { 3012 LSM6DSO_HP_PATH_DISABLE_ON_OUT = 0x00, 3013 LSM6DSO_SLOPE_ODR_DIV_4 = 0x10, 3014 LSM6DSO_HP_ODR_DIV_10 = 0x11, 3015 LSM6DSO_HP_ODR_DIV_20 = 0x12, 3016 LSM6DSO_HP_ODR_DIV_45 = 0x13, 3017 LSM6DSO_HP_ODR_DIV_100 = 0x14, 3018 LSM6DSO_HP_ODR_DIV_200 = 0x15, 3019 LSM6DSO_HP_ODR_DIV_400 = 0x16, 3020 LSM6DSO_HP_ODR_DIV_800 = 0x17, 3021 LSM6DSO_HP_REF_MD_ODR_DIV_10 = 0x31, 3022 LSM6DSO_HP_REF_MD_ODR_DIV_20 = 0x32, 3023 LSM6DSO_HP_REF_MD_ODR_DIV_45 = 0x33, 3024 LSM6DSO_HP_REF_MD_ODR_DIV_100 = 0x34, 3025 LSM6DSO_HP_REF_MD_ODR_DIV_200 = 0x35, 3026 LSM6DSO_HP_REF_MD_ODR_DIV_400 = 0x36, 3027 LSM6DSO_HP_REF_MD_ODR_DIV_800 = 0x37, 3028 LSM6DSO_LP_ODR_DIV_10 = 0x01, 3029 LSM6DSO_LP_ODR_DIV_20 = 0x02, 3030 LSM6DSO_LP_ODR_DIV_45 = 0x03, 3031 LSM6DSO_LP_ODR_DIV_100 = 0x04, 3032 LSM6DSO_LP_ODR_DIV_200 = 0x05, 3033 LSM6DSO_LP_ODR_DIV_400 = 0x06, 3034 LSM6DSO_LP_ODR_DIV_800 = 0x07, 3035 } lsm6dso_hp_slope_xl_en_t; 3036 int32_t lsm6dso_xl_hp_path_on_out_set(stmdev_ctx_t *ctx, 3037 lsm6dso_hp_slope_xl_en_t val); 3038 int32_t lsm6dso_xl_hp_path_on_out_get(stmdev_ctx_t *ctx, 3039 lsm6dso_hp_slope_xl_en_t *val); 3040 3041 int32_t lsm6dso_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val); 3042 int32_t lsm6dso_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val); 3043 3044 typedef enum 3045 { 3046 LSM6DSO_USE_SLOPE = 0, 3047 LSM6DSO_USE_HPF = 1, 3048 } lsm6dso_slope_fds_t; 3049 int32_t lsm6dso_xl_hp_path_internal_set(stmdev_ctx_t *ctx, 3050 lsm6dso_slope_fds_t val); 3051 int32_t lsm6dso_xl_hp_path_internal_get(stmdev_ctx_t *ctx, 3052 lsm6dso_slope_fds_t *val); 3053 3054 typedef enum 3055 { 3056 LSM6DSO_HP_FILTER_NONE = 0x00, 3057 LSM6DSO_HP_FILTER_16mHz = 0x80, 3058 LSM6DSO_HP_FILTER_65mHz = 0x81, 3059 LSM6DSO_HP_FILTER_260mHz = 0x82, 3060 LSM6DSO_HP_FILTER_1Hz04 = 0x83, 3061 } lsm6dso_hpm_g_t; 3062 int32_t lsm6dso_gy_hp_path_internal_set(stmdev_ctx_t *ctx, 3063 lsm6dso_hpm_g_t val); 3064 int32_t lsm6dso_gy_hp_path_internal_get(stmdev_ctx_t *ctx, 3065 lsm6dso_hpm_g_t *val); 3066 3067 typedef enum 3068 { 3069 LSM6DSO_AUX_PULL_UP_DISC = 0, 3070 LSM6DSO_AUX_PULL_UP_CONNECT = 1, 3071 } lsm6dso_ois_pu_dis_t; 3072 int32_t lsm6dso_aux_sdo_ocs_mode_set(stmdev_ctx_t *ctx, 3073 lsm6dso_ois_pu_dis_t val); 3074 int32_t lsm6dso_aux_sdo_ocs_mode_get(stmdev_ctx_t *ctx, 3075 lsm6dso_ois_pu_dis_t *val); 3076 3077 typedef enum 3078 { 3079 LSM6DSO_AUX_ON = 1, 3080 LSM6DSO_AUX_ON_BY_AUX_INTERFACE = 0, 3081 } lsm6dso_ois_on_t; 3082 int32_t lsm6dso_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx, 3083 lsm6dso_ois_on_t val); 3084 int32_t lsm6dso_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx, 3085 lsm6dso_ois_on_t *val); 3086 3087 typedef enum 3088 { 3089 LSM6DSO_USE_SAME_XL_FS = 0, 3090 LSM6DSO_USE_DIFFERENT_XL_FS = 1, 3091 } lsm6dso_xl_fs_mode_t; 3092 int32_t lsm6dso_aux_xl_fs_mode_set(stmdev_ctx_t *ctx, 3093 lsm6dso_xl_fs_mode_t val); 3094 int32_t lsm6dso_aux_xl_fs_mode_get(stmdev_ctx_t *ctx, 3095 lsm6dso_xl_fs_mode_t *val); 3096 3097 int32_t lsm6dso_aux_status_reg_get(stmdev_ctx_t *ctx, 3098 lsm6dso_status_spiaux_t *val); 3099 3100 int32_t lsm6dso_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx, 3101 uint8_t *val); 3102 3103 int32_t lsm6dso_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx, 3104 uint8_t *val); 3105 3106 int32_t lsm6dso_aux_gy_flag_settling_get(stmdev_ctx_t *ctx, 3107 uint8_t *val); 3108 3109 typedef enum 3110 { 3111 LSM6DSO_AUX_XL_DISABLE = 0, 3112 LSM6DSO_AUX_XL_POS = 1, 3113 LSM6DSO_AUX_XL_NEG = 2, 3114 } lsm6dso_st_xl_ois_t; 3115 int32_t lsm6dso_aux_xl_self_test_set(stmdev_ctx_t *ctx, 3116 lsm6dso_st_xl_ois_t val); 3117 int32_t lsm6dso_aux_xl_self_test_get(stmdev_ctx_t *ctx, 3118 lsm6dso_st_xl_ois_t *val); 3119 3120 typedef enum 3121 { 3122 LSM6DSO_AUX_DEN_ACTIVE_LOW = 0, 3123 LSM6DSO_AUX_DEN_ACTIVE_HIGH = 1, 3124 } lsm6dso_den_lh_ois_t; 3125 int32_t lsm6dso_aux_den_polarity_set(stmdev_ctx_t *ctx, 3126 lsm6dso_den_lh_ois_t val); 3127 int32_t lsm6dso_aux_den_polarity_get(stmdev_ctx_t *ctx, 3128 lsm6dso_den_lh_ois_t *val); 3129 3130 typedef enum 3131 { 3132 LSM6DSO_AUX_DEN_DISABLE = 0, 3133 LSM6DSO_AUX_DEN_LEVEL_LATCH = 3, 3134 LSM6DSO_AUX_DEN_LEVEL_TRIG = 2, 3135 } lsm6dso_lvl2_ois_t; 3136 int32_t lsm6dso_aux_den_mode_set(stmdev_ctx_t *ctx, 3137 lsm6dso_lvl2_ois_t val); 3138 int32_t lsm6dso_aux_den_mode_get(stmdev_ctx_t *ctx, 3139 lsm6dso_lvl2_ois_t *val); 3140 3141 int32_t lsm6dso_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val); 3142 int32_t lsm6dso_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val); 3143 3144 typedef enum 3145 { 3146 LSM6DSO_AUX_DISABLE = 0, 3147 LSM6DSO_MODE_3_GY = 1, 3148 LSM6DSO_MODE_4_GY_XL = 3, 3149 } lsm6dso_ois_en_spi2_t; 3150 int32_t lsm6dso_aux_mode_set(stmdev_ctx_t *ctx, 3151 lsm6dso_ois_en_spi2_t val); 3152 int32_t lsm6dso_aux_mode_get(stmdev_ctx_t *ctx, 3153 lsm6dso_ois_en_spi2_t *val); 3154 3155 typedef enum 3156 { 3157 LSM6DSO_250dps_AUX = 0, 3158 LSM6DSO_125dps_AUX = 1, 3159 LSM6DSO_500dps_AUX = 2, 3160 LSM6DSO_1000dps_AUX = 4, 3161 LSM6DSO_2000dps_AUX = 6, 3162 } lsm6dso_fs_g_ois_t; 3163 int32_t lsm6dso_aux_gy_full_scale_set(stmdev_ctx_t *ctx, 3164 lsm6dso_fs_g_ois_t val); 3165 int32_t lsm6dso_aux_gy_full_scale_get(stmdev_ctx_t *ctx, 3166 lsm6dso_fs_g_ois_t *val); 3167 3168 typedef enum 3169 { 3170 LSM6DSO_AUX_SPI_4_WIRE = 0, 3171 LSM6DSO_AUX_SPI_3_WIRE = 1, 3172 } lsm6dso_sim_ois_t; 3173 int32_t lsm6dso_aux_spi_mode_set(stmdev_ctx_t *ctx, 3174 lsm6dso_sim_ois_t val); 3175 int32_t lsm6dso_aux_spi_mode_get(stmdev_ctx_t *ctx, 3176 lsm6dso_sim_ois_t *val); 3177 3178 typedef enum 3179 { 3180 LSM6DSO_351Hz39 = 0, 3181 LSM6DSO_236Hz63 = 1, 3182 LSM6DSO_172Hz70 = 2, 3183 LSM6DSO_937Hz91 = 3, 3184 } lsm6dso_ftype_ois_t; 3185 int32_t lsm6dso_aux_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, 3186 lsm6dso_ftype_ois_t val); 3187 int32_t lsm6dso_aux_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, 3188 lsm6dso_ftype_ois_t *val); 3189 3190 typedef enum 3191 { 3192 LSM6DSO_AUX_HP_DISABLE = 0x00, 3193 LSM6DSO_AUX_HP_Hz016 = 0x10, 3194 LSM6DSO_AUX_HP_Hz065 = 0x11, 3195 LSM6DSO_AUX_HP_Hz260 = 0x12, 3196 LSM6DSO_AUX_HP_1Hz040 = 0x13, 3197 } lsm6dso_hpm_ois_t; 3198 int32_t lsm6dso_aux_gy_hp_bandwidth_set(stmdev_ctx_t *ctx, 3199 lsm6dso_hpm_ois_t val); 3200 int32_t lsm6dso_aux_gy_hp_bandwidth_get(stmdev_ctx_t *ctx, 3201 lsm6dso_hpm_ois_t *val); 3202 3203 typedef enum 3204 { 3205 LSM6DSO_ENABLE_CLAMP = 0, 3206 LSM6DSO_DISABLE_CLAMP = 1, 3207 } lsm6dso_st_ois_clampdis_t; 3208 int32_t lsm6dso_aux_gy_clamp_set(stmdev_ctx_t *ctx, 3209 lsm6dso_st_ois_clampdis_t val); 3210 int32_t lsm6dso_aux_gy_clamp_get(stmdev_ctx_t *ctx, 3211 lsm6dso_st_ois_clampdis_t *val); 3212 3213 typedef enum 3214 { 3215 LSM6DSO_AUX_GY_DISABLE = 0, 3216 LSM6DSO_AUX_GY_POS = 1, 3217 LSM6DSO_AUX_GY_NEG = 3, 3218 } lsm6dso_st_ois_t; 3219 int32_t lsm6dso_aux_gy_self_test_set(stmdev_ctx_t *ctx, 3220 lsm6dso_st_ois_t val); 3221 int32_t lsm6dso_aux_gy_self_test_get(stmdev_ctx_t *ctx, 3222 lsm6dso_st_ois_t *val); 3223 3224 typedef enum 3225 { 3226 LSM6DSO_289Hz = 0, 3227 LSM6DSO_258Hz = 1, 3228 LSM6DSO_120Hz = 2, 3229 LSM6DSO_65Hz2 = 3, 3230 LSM6DSO_33Hz2 = 4, 3231 LSM6DSO_16Hz6 = 5, 3232 LSM6DSO_8Hz30 = 6, 3233 LSM6DSO_4Hz15 = 7, 3234 } lsm6dso_filter_xl_conf_ois_t; 3235 int32_t lsm6dso_aux_xl_bandwidth_set(stmdev_ctx_t *ctx, 3236 lsm6dso_filter_xl_conf_ois_t val); 3237 int32_t lsm6dso_aux_xl_bandwidth_get(stmdev_ctx_t *ctx, 3238 lsm6dso_filter_xl_conf_ois_t *val); 3239 3240 typedef enum 3241 { 3242 LSM6DSO_AUX_2g = 0, 3243 LSM6DSO_AUX_16g = 1, 3244 LSM6DSO_AUX_4g = 2, 3245 LSM6DSO_AUX_8g = 3, 3246 } lsm6dso_fs_xl_ois_t; 3247 int32_t lsm6dso_aux_xl_full_scale_set(stmdev_ctx_t *ctx, 3248 lsm6dso_fs_xl_ois_t val); 3249 int32_t lsm6dso_aux_xl_full_scale_get(stmdev_ctx_t *ctx, 3250 lsm6dso_fs_xl_ois_t *val); 3251 3252 typedef enum 3253 { 3254 LSM6DSO_PULL_UP_DISC = 0, 3255 LSM6DSO_PULL_UP_CONNECT = 1, 3256 } lsm6dso_sdo_pu_en_t; 3257 int32_t lsm6dso_sdo_sa0_mode_set(stmdev_ctx_t *ctx, 3258 lsm6dso_sdo_pu_en_t val); 3259 int32_t lsm6dso_sdo_sa0_mode_get(stmdev_ctx_t *ctx, 3260 lsm6dso_sdo_pu_en_t *val); 3261 3262 typedef enum 3263 { 3264 LSM6DSO_SPI_4_WIRE = 0, 3265 LSM6DSO_SPI_3_WIRE = 1, 3266 } lsm6dso_sim_t; 3267 int32_t lsm6dso_spi_mode_set(stmdev_ctx_t *ctx, lsm6dso_sim_t val); 3268 int32_t lsm6dso_spi_mode_get(stmdev_ctx_t *ctx, lsm6dso_sim_t *val); 3269 3270 typedef enum 3271 { 3272 LSM6DSO_I2C_ENABLE = 0, 3273 LSM6DSO_I2C_DISABLE = 1, 3274 } lsm6dso_i2c_disable_t; 3275 int32_t lsm6dso_i2c_interface_set(stmdev_ctx_t *ctx, 3276 lsm6dso_i2c_disable_t val); 3277 int32_t lsm6dso_i2c_interface_get(stmdev_ctx_t *ctx, 3278 lsm6dso_i2c_disable_t *val); 3279 3280 typedef enum 3281 { 3282 LSM6DSO_I3C_DISABLE = 0x80, 3283 LSM6DSO_I3C_ENABLE_T_50us = 0x00, 3284 LSM6DSO_I3C_ENABLE_T_2us = 0x01, 3285 LSM6DSO_I3C_ENABLE_T_1ms = 0x02, 3286 LSM6DSO_I3C_ENABLE_T_25ms = 0x03, 3287 } lsm6dso_i3c_disable_t; 3288 int32_t lsm6dso_i3c_disable_set(stmdev_ctx_t *ctx, 3289 lsm6dso_i3c_disable_t val); 3290 int32_t lsm6dso_i3c_disable_get(stmdev_ctx_t *ctx, 3291 lsm6dso_i3c_disable_t *val); 3292 3293 typedef enum 3294 { 3295 LSM6DSO_PULL_DOWN_DISC = 0, 3296 LSM6DSO_PULL_DOWN_CONNECT = 1, 3297 } lsm6dso_int1_pd_en_t; 3298 int32_t lsm6dso_int1_mode_set(stmdev_ctx_t *ctx, 3299 lsm6dso_int1_pd_en_t val); 3300 int32_t lsm6dso_int1_mode_get(stmdev_ctx_t *ctx, 3301 lsm6dso_int1_pd_en_t *val); 3302 3303 typedef enum 3304 { 3305 LSM6DSO_PUSH_PULL = 0, 3306 LSM6DSO_OPEN_DRAIN = 1, 3307 } lsm6dso_pp_od_t; 3308 int32_t lsm6dso_pin_mode_set(stmdev_ctx_t *ctx, lsm6dso_pp_od_t val); 3309 int32_t lsm6dso_pin_mode_get(stmdev_ctx_t *ctx, lsm6dso_pp_od_t *val); 3310 3311 typedef enum 3312 { 3313 LSM6DSO_ACTIVE_HIGH = 0, 3314 LSM6DSO_ACTIVE_LOW = 1, 3315 } lsm6dso_h_lactive_t; 3316 int32_t lsm6dso_pin_polarity_set(stmdev_ctx_t *ctx, 3317 lsm6dso_h_lactive_t val); 3318 int32_t lsm6dso_pin_polarity_get(stmdev_ctx_t *ctx, 3319 lsm6dso_h_lactive_t *val); 3320 3321 int32_t lsm6dso_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); 3322 int32_t lsm6dso_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); 3323 3324 typedef enum 3325 { 3326 LSM6DSO_ALL_INT_PULSED = 0, 3327 LSM6DSO_BASE_LATCHED_EMB_PULSED = 1, 3328 LSM6DSO_BASE_PULSED_EMB_LATCHED = 2, 3329 LSM6DSO_ALL_INT_LATCHED = 3, 3330 } lsm6dso_lir_t; 3331 int32_t lsm6dso_int_notification_set(stmdev_ctx_t *ctx, 3332 lsm6dso_lir_t val); 3333 int32_t lsm6dso_int_notification_get(stmdev_ctx_t *ctx, 3334 lsm6dso_lir_t *val); 3335 3336 typedef enum 3337 { 3338 LSM6DSO_LSb_FS_DIV_64 = 0, 3339 LSM6DSO_LSb_FS_DIV_256 = 1, 3340 } lsm6dso_wake_ths_w_t; 3341 int32_t lsm6dso_wkup_ths_weight_set(stmdev_ctx_t *ctx, 3342 lsm6dso_wake_ths_w_t val); 3343 int32_t lsm6dso_wkup_ths_weight_get(stmdev_ctx_t *ctx, 3344 lsm6dso_wake_ths_w_t *val); 3345 3346 int32_t lsm6dso_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val); 3347 int32_t lsm6dso_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); 3348 3349 int32_t lsm6dso_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, 3350 uint8_t val); 3351 int32_t lsm6dso_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, 3352 uint8_t *val); 3353 3354 int32_t lsm6dso_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val); 3355 int32_t lsm6dso_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 3356 3357 int32_t lsm6dso_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val); 3358 int32_t lsm6dso_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val); 3359 3360 typedef enum 3361 { 3362 LSM6DSO_DRIVE_SLEEP_CHG_EVENT = 0, 3363 LSM6DSO_DRIVE_SLEEP_STATUS = 1, 3364 } lsm6dso_sleep_status_on_int_t; 3365 int32_t lsm6dso_act_pin_notification_set(stmdev_ctx_t *ctx, 3366 lsm6dso_sleep_status_on_int_t val); 3367 int32_t lsm6dso_act_pin_notification_get(stmdev_ctx_t *ctx, 3368 lsm6dso_sleep_status_on_int_t *val); 3369 3370 typedef enum 3371 { 3372 LSM6DSO_XL_AND_GY_NOT_AFFECTED = 0, 3373 LSM6DSO_XL_12Hz5_GY_NOT_AFFECTED = 1, 3374 LSM6DSO_XL_12Hz5_GY_SLEEP = 2, 3375 LSM6DSO_XL_12Hz5_GY_PD = 3, 3376 } lsm6dso_inact_en_t; 3377 int32_t lsm6dso_act_mode_set(stmdev_ctx_t *ctx, 3378 lsm6dso_inact_en_t val); 3379 int32_t lsm6dso_act_mode_get(stmdev_ctx_t *ctx, 3380 lsm6dso_inact_en_t *val); 3381 3382 int32_t lsm6dso_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val); 3383 int32_t lsm6dso_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 3384 3385 int32_t lsm6dso_tap_detection_on_z_set(stmdev_ctx_t *ctx, 3386 uint8_t val); 3387 int32_t lsm6dso_tap_detection_on_z_get(stmdev_ctx_t *ctx, 3388 uint8_t *val); 3389 3390 int32_t lsm6dso_tap_detection_on_y_set(stmdev_ctx_t *ctx, 3391 uint8_t val); 3392 int32_t lsm6dso_tap_detection_on_y_get(stmdev_ctx_t *ctx, 3393 uint8_t *val); 3394 3395 int32_t lsm6dso_tap_detection_on_x_set(stmdev_ctx_t *ctx, 3396 uint8_t val); 3397 int32_t lsm6dso_tap_detection_on_x_get(stmdev_ctx_t *ctx, 3398 uint8_t *val); 3399 3400 int32_t lsm6dso_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val); 3401 int32_t lsm6dso_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val); 3402 3403 typedef enum 3404 { 3405 LSM6DSO_XYZ = 0, 3406 LSM6DSO_YXZ = 1, 3407 LSM6DSO_XZY = 2, 3408 LSM6DSO_ZYX = 3, 3409 LSM6DSO_YZX = 5, 3410 LSM6DSO_ZXY = 6, 3411 } lsm6dso_tap_priority_t; 3412 int32_t lsm6dso_tap_axis_priority_set(stmdev_ctx_t *ctx, 3413 lsm6dso_tap_priority_t val); 3414 int32_t lsm6dso_tap_axis_priority_get(stmdev_ctx_t *ctx, 3415 lsm6dso_tap_priority_t *val); 3416 3417 int32_t lsm6dso_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val); 3418 int32_t lsm6dso_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val); 3419 3420 int32_t lsm6dso_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val); 3421 int32_t lsm6dso_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val); 3422 3423 int32_t lsm6dso_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val); 3424 int32_t lsm6dso_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val); 3425 3426 int32_t lsm6dso_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val); 3427 int32_t lsm6dso_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val); 3428 3429 int32_t lsm6dso_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val); 3430 int32_t lsm6dso_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 3431 3432 typedef enum 3433 { 3434 LSM6DSO_ONLY_SINGLE = 0, 3435 LSM6DSO_BOTH_SINGLE_DOUBLE = 1, 3436 } lsm6dso_single_double_tap_t; 3437 int32_t lsm6dso_tap_mode_set(stmdev_ctx_t *ctx, 3438 lsm6dso_single_double_tap_t val); 3439 int32_t lsm6dso_tap_mode_get(stmdev_ctx_t *ctx, 3440 lsm6dso_single_double_tap_t *val); 3441 3442 typedef enum 3443 { 3444 LSM6DSO_DEG_80 = 0, 3445 LSM6DSO_DEG_70 = 1, 3446 LSM6DSO_DEG_60 = 2, 3447 LSM6DSO_DEG_50 = 3, 3448 } lsm6dso_sixd_ths_t; 3449 int32_t lsm6dso_6d_threshold_set(stmdev_ctx_t *ctx, 3450 lsm6dso_sixd_ths_t val); 3451 int32_t lsm6dso_6d_threshold_get(stmdev_ctx_t *ctx, 3452 lsm6dso_sixd_ths_t *val); 3453 3454 int32_t lsm6dso_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val); 3455 int32_t lsm6dso_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val); 3456 3457 typedef enum 3458 { 3459 LSM6DSO_FF_TSH_156mg = 0, 3460 LSM6DSO_FF_TSH_219mg = 1, 3461 LSM6DSO_FF_TSH_250mg = 2, 3462 LSM6DSO_FF_TSH_312mg = 3, 3463 LSM6DSO_FF_TSH_344mg = 4, 3464 LSM6DSO_FF_TSH_406mg = 5, 3465 LSM6DSO_FF_TSH_469mg = 6, 3466 LSM6DSO_FF_TSH_500mg = 7, 3467 } lsm6dso_ff_ths_t; 3468 int32_t lsm6dso_ff_threshold_set(stmdev_ctx_t *ctx, 3469 lsm6dso_ff_ths_t val); 3470 int32_t lsm6dso_ff_threshold_get(stmdev_ctx_t *ctx, 3471 lsm6dso_ff_ths_t *val); 3472 3473 int32_t lsm6dso_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val); 3474 int32_t lsm6dso_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 3475 3476 int32_t lsm6dso_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val); 3477 int32_t lsm6dso_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val); 3478 3479 int32_t lsm6dso_compression_algo_init_set(stmdev_ctx_t *ctx, 3480 uint8_t val); 3481 int32_t lsm6dso_compression_algo_init_get(stmdev_ctx_t *ctx, 3482 uint8_t *val); 3483 3484 typedef enum 3485 { 3486 LSM6DSO_CMP_DISABLE = 0x00, 3487 LSM6DSO_CMP_ALWAYS = 0x04, 3488 LSM6DSO_CMP_8_TO_1 = 0x05, 3489 LSM6DSO_CMP_16_TO_1 = 0x06, 3490 LSM6DSO_CMP_32_TO_1 = 0x07, 3491 } lsm6dso_uncoptr_rate_t; 3492 int32_t lsm6dso_compression_algo_set(stmdev_ctx_t *ctx, 3493 lsm6dso_uncoptr_rate_t val); 3494 int32_t lsm6dso_compression_algo_get(stmdev_ctx_t *ctx, 3495 lsm6dso_uncoptr_rate_t *val); 3496 3497 int32_t lsm6dso_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, 3498 uint8_t val); 3499 int32_t lsm6dso_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, 3500 uint8_t *val); 3501 3502 int32_t lsm6dso_compression_algo_real_time_set(stmdev_ctx_t *ctx, 3503 uint8_t val); 3504 int32_t lsm6dso_compression_algo_real_time_get(stmdev_ctx_t *ctx, 3505 uint8_t *val); 3506 3507 int32_t lsm6dso_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val); 3508 int32_t lsm6dso_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val); 3509 3510 typedef enum 3511 { 3512 LSM6DSO_XL_NOT_BATCHED = 0, 3513 LSM6DSO_XL_BATCHED_AT_12Hz5 = 1, 3514 LSM6DSO_XL_BATCHED_AT_26Hz = 2, 3515 LSM6DSO_XL_BATCHED_AT_52Hz = 3, 3516 LSM6DSO_XL_BATCHED_AT_104Hz = 4, 3517 LSM6DSO_XL_BATCHED_AT_208Hz = 5, 3518 LSM6DSO_XL_BATCHED_AT_417Hz = 6, 3519 LSM6DSO_XL_BATCHED_AT_833Hz = 7, 3520 LSM6DSO_XL_BATCHED_AT_1667Hz = 8, 3521 LSM6DSO_XL_BATCHED_AT_3333Hz = 9, 3522 LSM6DSO_XL_BATCHED_AT_6667Hz = 10, 3523 LSM6DSO_XL_BATCHED_AT_6Hz5 = 11, 3524 } lsm6dso_bdr_xl_t; 3525 int32_t lsm6dso_fifo_xl_batch_set(stmdev_ctx_t *ctx, 3526 lsm6dso_bdr_xl_t val); 3527 int32_t lsm6dso_fifo_xl_batch_get(stmdev_ctx_t *ctx, 3528 lsm6dso_bdr_xl_t *val); 3529 3530 typedef enum 3531 { 3532 LSM6DSO_GY_NOT_BATCHED = 0, 3533 LSM6DSO_GY_BATCHED_AT_12Hz5 = 1, 3534 LSM6DSO_GY_BATCHED_AT_26Hz = 2, 3535 LSM6DSO_GY_BATCHED_AT_52Hz = 3, 3536 LSM6DSO_GY_BATCHED_AT_104Hz = 4, 3537 LSM6DSO_GY_BATCHED_AT_208Hz = 5, 3538 LSM6DSO_GY_BATCHED_AT_417Hz = 6, 3539 LSM6DSO_GY_BATCHED_AT_833Hz = 7, 3540 LSM6DSO_GY_BATCHED_AT_1667Hz = 8, 3541 LSM6DSO_GY_BATCHED_AT_3333Hz = 9, 3542 LSM6DSO_GY_BATCHED_AT_6667Hz = 10, 3543 LSM6DSO_GY_BATCHED_AT_6Hz5 = 11, 3544 } lsm6dso_bdr_gy_t; 3545 int32_t lsm6dso_fifo_gy_batch_set(stmdev_ctx_t *ctx, 3546 lsm6dso_bdr_gy_t val); 3547 int32_t lsm6dso_fifo_gy_batch_get(stmdev_ctx_t *ctx, 3548 lsm6dso_bdr_gy_t *val); 3549 3550 typedef enum 3551 { 3552 LSM6DSO_BYPASS_MODE = 0, 3553 LSM6DSO_FIFO_MODE = 1, 3554 LSM6DSO_STREAM_TO_FIFO_MODE = 3, 3555 LSM6DSO_BYPASS_TO_STREAM_MODE = 4, 3556 LSM6DSO_STREAM_MODE = 6, 3557 LSM6DSO_BYPASS_TO_FIFO_MODE = 7, 3558 } lsm6dso_fifo_mode_t; 3559 int32_t lsm6dso_fifo_mode_set(stmdev_ctx_t *ctx, 3560 lsm6dso_fifo_mode_t val); 3561 int32_t lsm6dso_fifo_mode_get(stmdev_ctx_t *ctx, 3562 lsm6dso_fifo_mode_t *val); 3563 3564 typedef enum 3565 { 3566 LSM6DSO_TEMP_NOT_BATCHED = 0, 3567 LSM6DSO_TEMP_BATCHED_AT_1Hz6 = 1, 3568 LSM6DSO_TEMP_BATCHED_AT_12Hz5 = 2, 3569 LSM6DSO_TEMP_BATCHED_AT_52Hz = 3, 3570 } lsm6dso_odr_t_batch_t; 3571 int32_t lsm6dso_fifo_temp_batch_set(stmdev_ctx_t *ctx, 3572 lsm6dso_odr_t_batch_t val); 3573 int32_t lsm6dso_fifo_temp_batch_get(stmdev_ctx_t *ctx, 3574 lsm6dso_odr_t_batch_t *val); 3575 3576 typedef enum 3577 { 3578 LSM6DSO_NO_DECIMATION = 0, 3579 LSM6DSO_DEC_1 = 1, 3580 LSM6DSO_DEC_8 = 2, 3581 LSM6DSO_DEC_32 = 3, 3582 } lsm6dso_odr_ts_batch_t; 3583 int32_t lsm6dso_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, 3584 lsm6dso_odr_ts_batch_t val); 3585 int32_t lsm6dso_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, 3586 lsm6dso_odr_ts_batch_t *val); 3587 3588 typedef enum 3589 { 3590 LSM6DSO_XL_BATCH_EVENT = 0, 3591 LSM6DSO_GYRO_BATCH_EVENT = 1, 3592 } lsm6dso_trig_counter_bdr_t; 3593 3594 typedef enum 3595 { 3596 LSM6DSO_GYRO_NC_TAG = 1, 3597 LSM6DSO_XL_NC_TAG, 3598 LSM6DSO_TEMPERATURE_TAG, 3599 LSM6DSO_TIMESTAMP_TAG, 3600 LSM6DSO_CFG_CHANGE_TAG, 3601 LSM6DSO_XL_NC_T_2_TAG, 3602 LSM6DSO_XL_NC_T_1_TAG, 3603 LSM6DSO_XL_2XC_TAG, 3604 LSM6DSO_XL_3XC_TAG, 3605 LSM6DSO_GYRO_NC_T_2_TAG, 3606 LSM6DSO_GYRO_NC_T_1_TAG, 3607 LSM6DSO_GYRO_2XC_TAG, 3608 LSM6DSO_GYRO_3XC_TAG, 3609 LSM6DSO_SENSORHUB_SLAVE0_TAG, 3610 LSM6DSO_SENSORHUB_SLAVE1_TAG, 3611 LSM6DSO_SENSORHUB_SLAVE2_TAG, 3612 LSM6DSO_SENSORHUB_SLAVE3_TAG, 3613 LSM6DSO_STEP_COUNTER_TAG, 3614 LSM6DSO_GAME_ROTATION_TAG, 3615 LSM6DSO_GEOMAG_ROTATION_TAG, 3616 LSM6DSO_ROTATION_TAG, 3617 LSM6DSO_SENSORHUB_NACK_TAG = 0x19, 3618 } lsm6dso_fifo_tag_t; 3619 int32_t lsm6dso_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx, 3620 lsm6dso_trig_counter_bdr_t val); 3621 int32_t lsm6dso_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx, 3622 lsm6dso_trig_counter_bdr_t *val); 3623 3624 int32_t lsm6dso_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val); 3625 int32_t lsm6dso_rst_batch_counter_get(stmdev_ctx_t *ctx, 3626 uint8_t *val); 3627 3628 int32_t lsm6dso_batch_counter_threshold_set(stmdev_ctx_t *ctx, 3629 uint16_t val); 3630 int32_t lsm6dso_batch_counter_threshold_get(stmdev_ctx_t *ctx, 3631 uint16_t *val); 3632 3633 int32_t lsm6dso_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val); 3634 3635 int32_t lsm6dso_fifo_status_get(stmdev_ctx_t *ctx, 3636 lsm6dso_fifo_status2_t *val); 3637 3638 int32_t lsm6dso_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val); 3639 3640 int32_t lsm6dso_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); 3641 3642 int32_t lsm6dso_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); 3643 3644 int32_t lsm6dso_fifo_sensor_tag_get(stmdev_ctx_t *ctx, 3645 lsm6dso_fifo_tag_t *val); 3646 3647 int32_t lsm6dso_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val); 3648 int32_t lsm6dso_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val); 3649 3650 int32_t lsm6dso_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val); 3651 int32_t lsm6dso_sh_batch_slave_0_get(stmdev_ctx_t *ctx, uint8_t *val); 3652 3653 int32_t lsm6dso_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val); 3654 int32_t lsm6dso_sh_batch_slave_1_get(stmdev_ctx_t *ctx, uint8_t *val); 3655 3656 int32_t lsm6dso_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val); 3657 int32_t lsm6dso_sh_batch_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val); 3658 3659 int32_t lsm6dso_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val); 3660 int32_t lsm6dso_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val); 3661 3662 typedef enum 3663 { 3664 LSM6DSO_DEN_DISABLE = 0, 3665 LSM6DSO_LEVEL_FIFO = 6, 3666 LSM6DSO_LEVEL_LETCHED = 3, 3667 LSM6DSO_LEVEL_TRIGGER = 2, 3668 LSM6DSO_EDGE_TRIGGER = 4, 3669 } lsm6dso_den_mode_t; 3670 int32_t lsm6dso_den_mode_set(stmdev_ctx_t *ctx, 3671 lsm6dso_den_mode_t val); 3672 int32_t lsm6dso_den_mode_get(stmdev_ctx_t *ctx, 3673 lsm6dso_den_mode_t *val); 3674 3675 typedef enum 3676 { 3677 LSM6DSO_DEN_ACT_LOW = 0, 3678 LSM6DSO_DEN_ACT_HIGH = 1, 3679 } lsm6dso_den_lh_t; 3680 int32_t lsm6dso_den_polarity_set(stmdev_ctx_t *ctx, 3681 lsm6dso_den_lh_t val); 3682 int32_t lsm6dso_den_polarity_get(stmdev_ctx_t *ctx, 3683 lsm6dso_den_lh_t *val); 3684 3685 typedef enum 3686 { 3687 LSM6DSO_STAMP_IN_GY_DATA = 0, 3688 LSM6DSO_STAMP_IN_XL_DATA = 1, 3689 LSM6DSO_STAMP_IN_GY_XL_DATA = 2, 3690 } lsm6dso_den_xl_g_t; 3691 int32_t lsm6dso_den_enable_set(stmdev_ctx_t *ctx, 3692 lsm6dso_den_xl_g_t val); 3693 int32_t lsm6dso_den_enable_get(stmdev_ctx_t *ctx, 3694 lsm6dso_den_xl_g_t *val); 3695 3696 int32_t lsm6dso_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val); 3697 int32_t lsm6dso_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val); 3698 3699 int32_t lsm6dso_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val); 3700 int32_t lsm6dso_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val); 3701 3702 int32_t lsm6dso_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val); 3703 int32_t lsm6dso_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val); 3704 3705 typedef enum 3706 { 3707 LSM6DSO_PEDO_BASE_MODE = 0x00, 3708 LSM6DSO_FALSE_STEP_REJ = 0x10, 3709 LSM6DSO_FALSE_STEP_REJ_ADV_MODE = 0x30, 3710 } lsm6dso_pedo_md_t; 3711 int32_t lsm6dso_pedo_sens_set(stmdev_ctx_t *ctx, 3712 lsm6dso_pedo_md_t val); 3713 int32_t lsm6dso_pedo_sens_get(stmdev_ctx_t *ctx, 3714 lsm6dso_pedo_md_t *val); 3715 3716 int32_t lsm6dso_pedo_step_detect_get(stmdev_ctx_t *ctx, uint8_t *val); 3717 3718 int32_t lsm6dso_pedo_debounce_steps_set(stmdev_ctx_t *ctx, 3719 uint8_t *buff); 3720 int32_t lsm6dso_pedo_debounce_steps_get(stmdev_ctx_t *ctx, 3721 uint8_t *buff); 3722 3723 int32_t lsm6dso_pedo_steps_period_set(stmdev_ctx_t *ctx, 3724 uint16_t val); 3725 int32_t lsm6dso_pedo_steps_period_get(stmdev_ctx_t *ctx, 3726 uint16_t *val); 3727 3728 typedef enum 3729 { 3730 LSM6DSO_EVERY_STEP = 0, 3731 LSM6DSO_COUNT_OVERFLOW = 1, 3732 } lsm6dso_carry_count_en_t; 3733 int32_t lsm6dso_pedo_int_mode_set(stmdev_ctx_t *ctx, 3734 lsm6dso_carry_count_en_t val); 3735 int32_t lsm6dso_pedo_int_mode_get(stmdev_ctx_t *ctx, 3736 lsm6dso_carry_count_en_t *val); 3737 3738 int32_t lsm6dso_motion_flag_data_ready_get(stmdev_ctx_t *ctx, 3739 uint8_t *val); 3740 3741 int32_t lsm6dso_tilt_flag_data_ready_get(stmdev_ctx_t *ctx, 3742 uint8_t *val); 3743 3744 int32_t lsm6dso_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val); 3745 int32_t lsm6dso_mag_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val); 3746 3747 int32_t lsm6dso_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val); 3748 int32_t lsm6dso_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val); 3749 3750 int32_t lsm6dso_mag_soft_iron_set(stmdev_ctx_t *ctx, int16_t *val); 3751 int32_t lsm6dso_mag_soft_iron_get(stmdev_ctx_t *ctx, int16_t *val); 3752 3753 typedef enum 3754 { 3755 LSM6DSO_Z_EQ_Y = 0, 3756 LSM6DSO_Z_EQ_MIN_Y = 1, 3757 LSM6DSO_Z_EQ_X = 2, 3758 LSM6DSO_Z_EQ_MIN_X = 3, 3759 LSM6DSO_Z_EQ_MIN_Z = 4, 3760 LSM6DSO_Z_EQ_Z = 5, 3761 } lsm6dso_mag_z_axis_t; 3762 int32_t lsm6dso_mag_z_orient_set(stmdev_ctx_t *ctx, 3763 lsm6dso_mag_z_axis_t val); 3764 int32_t lsm6dso_mag_z_orient_get(stmdev_ctx_t *ctx, 3765 lsm6dso_mag_z_axis_t *val); 3766 3767 typedef enum 3768 { 3769 LSM6DSO_Y_EQ_Y = 0, 3770 LSM6DSO_Y_EQ_MIN_Y = 1, 3771 LSM6DSO_Y_EQ_X = 2, 3772 LSM6DSO_Y_EQ_MIN_X = 3, 3773 LSM6DSO_Y_EQ_MIN_Z = 4, 3774 LSM6DSO_Y_EQ_Z = 5, 3775 } lsm6dso_mag_y_axis_t; 3776 int32_t lsm6dso_mag_y_orient_set(stmdev_ctx_t *ctx, 3777 lsm6dso_mag_y_axis_t val); 3778 int32_t lsm6dso_mag_y_orient_get(stmdev_ctx_t *ctx, 3779 lsm6dso_mag_y_axis_t *val); 3780 3781 typedef enum 3782 { 3783 LSM6DSO_X_EQ_Y = 0, 3784 LSM6DSO_X_EQ_MIN_Y = 1, 3785 LSM6DSO_X_EQ_X = 2, 3786 LSM6DSO_X_EQ_MIN_X = 3, 3787 LSM6DSO_X_EQ_MIN_Z = 4, 3788 LSM6DSO_X_EQ_Z = 5, 3789 } lsm6dso_mag_x_axis_t; 3790 int32_t lsm6dso_mag_x_orient_set(stmdev_ctx_t *ctx, 3791 lsm6dso_mag_x_axis_t val); 3792 int32_t lsm6dso_mag_x_orient_get(stmdev_ctx_t *ctx, 3793 lsm6dso_mag_x_axis_t *val); 3794 3795 int32_t lsm6dso_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, 3796 uint8_t *val); 3797 3798 typedef struct 3799 { 3800 lsm6dso_fsm_enable_a_t fsm_enable_a; 3801 lsm6dso_fsm_enable_b_t fsm_enable_b; 3802 } lsm6dso_emb_fsm_enable_t; 3803 int32_t lsm6dso_fsm_enable_set(stmdev_ctx_t *ctx, 3804 lsm6dso_emb_fsm_enable_t *val); 3805 int32_t lsm6dso_fsm_enable_get(stmdev_ctx_t *ctx, 3806 lsm6dso_emb_fsm_enable_t *val); 3807 3808 int32_t lsm6dso_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val); 3809 int32_t lsm6dso_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val); 3810 3811 typedef enum 3812 { 3813 LSM6DSO_LC_NORMAL = 0, 3814 LSM6DSO_LC_CLEAR = 1, 3815 LSM6DSO_LC_CLEAR_DONE = 2, 3816 } lsm6dso_fsm_lc_clr_t; 3817 int32_t lsm6dso_long_clr_set(stmdev_ctx_t *ctx, 3818 lsm6dso_fsm_lc_clr_t val); 3819 int32_t lsm6dso_long_clr_get(stmdev_ctx_t *ctx, 3820 lsm6dso_fsm_lc_clr_t *val); 3821 3822 typedef struct 3823 { 3824 lsm6dso_fsm_outs1_t fsm_outs1; 3825 lsm6dso_fsm_outs2_t fsm_outs2; 3826 lsm6dso_fsm_outs3_t fsm_outs3; 3827 lsm6dso_fsm_outs4_t fsm_outs4; 3828 lsm6dso_fsm_outs5_t fsm_outs5; 3829 lsm6dso_fsm_outs6_t fsm_outs6; 3830 lsm6dso_fsm_outs7_t fsm_outs7; 3831 lsm6dso_fsm_outs8_t fsm_outs8; 3832 lsm6dso_fsm_outs9_t fsm_outs9; 3833 lsm6dso_fsm_outs10_t fsm_outs10; 3834 lsm6dso_fsm_outs11_t fsm_outs11; 3835 lsm6dso_fsm_outs12_t fsm_outs12; 3836 lsm6dso_fsm_outs13_t fsm_outs13; 3837 lsm6dso_fsm_outs14_t fsm_outs14; 3838 lsm6dso_fsm_outs15_t fsm_outs15; 3839 lsm6dso_fsm_outs16_t fsm_outs16; 3840 } lsm6dso_fsm_out_t; 3841 int32_t lsm6dso_fsm_out_get(stmdev_ctx_t *ctx, 3842 lsm6dso_fsm_out_t *val); 3843 3844 typedef enum 3845 { 3846 LSM6DSO_ODR_FSM_12Hz5 = 0, 3847 LSM6DSO_ODR_FSM_26Hz = 1, 3848 LSM6DSO_ODR_FSM_52Hz = 2, 3849 LSM6DSO_ODR_FSM_104Hz = 3, 3850 } lsm6dso_fsm_odr_t; 3851 int32_t lsm6dso_fsm_data_rate_set(stmdev_ctx_t *ctx, 3852 lsm6dso_fsm_odr_t val); 3853 int32_t lsm6dso_fsm_data_rate_get(stmdev_ctx_t *ctx, 3854 lsm6dso_fsm_odr_t *val); 3855 3856 int32_t lsm6dso_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val); 3857 int32_t lsm6dso_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val); 3858 3859 int32_t lsm6dso_long_cnt_int_value_set(stmdev_ctx_t *ctx, 3860 uint16_t val); 3861 int32_t lsm6dso_long_cnt_int_value_get(stmdev_ctx_t *ctx, 3862 uint16_t *val); 3863 3864 int32_t lsm6dso_fsm_number_of_programs_set(stmdev_ctx_t *ctx, 3865 uint8_t val); 3866 int32_t lsm6dso_fsm_number_of_programs_get(stmdev_ctx_t *ctx, 3867 uint8_t *val); 3868 3869 int32_t lsm6dso_fsm_start_address_set(stmdev_ctx_t *ctx, 3870 uint16_t val); 3871 int32_t lsm6dso_fsm_start_address_get(stmdev_ctx_t *ctx, 3872 uint16_t *val); 3873 3874 int32_t lsm6dso_sh_read_data_raw_get(stmdev_ctx_t *ctx, uint8_t *val, 3875 uint8_t len); 3876 3877 typedef enum 3878 { 3879 LSM6DSO_SLV_0 = 0, 3880 LSM6DSO_SLV_0_1 = 1, 3881 LSM6DSO_SLV_0_1_2 = 2, 3882 LSM6DSO_SLV_0_1_2_3 = 3, 3883 } lsm6dso_aux_sens_on_t; 3884 int32_t lsm6dso_sh_slave_connected_set(stmdev_ctx_t *ctx, 3885 lsm6dso_aux_sens_on_t val); 3886 int32_t lsm6dso_sh_slave_connected_get(stmdev_ctx_t *ctx, 3887 lsm6dso_aux_sens_on_t *val); 3888 3889 int32_t lsm6dso_sh_master_set(stmdev_ctx_t *ctx, uint8_t val); 3890 int32_t lsm6dso_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val); 3891 3892 typedef enum 3893 { 3894 LSM6DSO_EXT_PULL_UP = 0, 3895 LSM6DSO_INTERNAL_PULL_UP = 1, 3896 } lsm6dso_shub_pu_en_t; 3897 int32_t lsm6dso_sh_pin_mode_set(stmdev_ctx_t *ctx, 3898 lsm6dso_shub_pu_en_t val); 3899 int32_t lsm6dso_sh_pin_mode_get(stmdev_ctx_t *ctx, 3900 lsm6dso_shub_pu_en_t *val); 3901 3902 int32_t lsm6dso_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val); 3903 int32_t lsm6dso_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val); 3904 3905 typedef enum 3906 { 3907 LSM6DSO_EXT_ON_INT2_PIN = 1, 3908 LSM6DSO_XL_GY_DRDY = 0, 3909 } lsm6dso_start_config_t; 3910 int32_t lsm6dso_sh_syncro_mode_set(stmdev_ctx_t *ctx, 3911 lsm6dso_start_config_t val); 3912 int32_t lsm6dso_sh_syncro_mode_get(stmdev_ctx_t *ctx, 3913 lsm6dso_start_config_t *val); 3914 3915 typedef enum 3916 { 3917 LSM6DSO_EACH_SH_CYCLE = 0, 3918 LSM6DSO_ONLY_FIRST_CYCLE = 1, 3919 } lsm6dso_write_once_t; 3920 int32_t lsm6dso_sh_write_mode_set(stmdev_ctx_t *ctx, 3921 lsm6dso_write_once_t val); 3922 int32_t lsm6dso_sh_write_mode_get(stmdev_ctx_t *ctx, 3923 lsm6dso_write_once_t *val); 3924 3925 int32_t lsm6dso_sh_reset_set(stmdev_ctx_t *ctx); 3926 int32_t lsm6dso_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val); 3927 3928 typedef enum 3929 { 3930 LSM6DSO_SH_ODR_104Hz = 0, 3931 LSM6DSO_SH_ODR_52Hz = 1, 3932 LSM6DSO_SH_ODR_26Hz = 2, 3933 LSM6DSO_SH_ODR_13Hz = 3, 3934 } lsm6dso_shub_odr_t; 3935 int32_t lsm6dso_sh_data_rate_set(stmdev_ctx_t *ctx, 3936 lsm6dso_shub_odr_t val); 3937 int32_t lsm6dso_sh_data_rate_get(stmdev_ctx_t *ctx, 3938 lsm6dso_shub_odr_t *val); 3939 3940 typedef struct 3941 { 3942 uint8_t slv0_add; 3943 uint8_t slv0_subadd; 3944 uint8_t slv0_data; 3945 } lsm6dso_sh_cfg_write_t; 3946 int32_t lsm6dso_sh_cfg_write(stmdev_ctx_t *ctx, 3947 lsm6dso_sh_cfg_write_t *val); 3948 3949 typedef struct 3950 { 3951 uint8_t slv_add; 3952 uint8_t slv_subadd; 3953 uint8_t slv_len; 3954 } lsm6dso_sh_cfg_read_t; 3955 int32_t lsm6dso_sh_slv0_cfg_read(stmdev_ctx_t *ctx, 3956 lsm6dso_sh_cfg_read_t *val); 3957 int32_t lsm6dso_sh_slv1_cfg_read(stmdev_ctx_t *ctx, 3958 lsm6dso_sh_cfg_read_t *val); 3959 int32_t lsm6dso_sh_slv2_cfg_read(stmdev_ctx_t *ctx, 3960 lsm6dso_sh_cfg_read_t *val); 3961 int32_t lsm6dso_sh_slv3_cfg_read(stmdev_ctx_t *ctx, 3962 lsm6dso_sh_cfg_read_t *val); 3963 3964 int32_t lsm6dso_sh_status_get(stmdev_ctx_t *ctx, 3965 lsm6dso_status_master_t *val); 3966 3967 3968 typedef struct 3969 { 3970 uint8_t ui; 3971 uint8_t aux; 3972 } lsm6dso_id_t; 3973 int32_t lsm6dso_id_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, 3974 lsm6dso_id_t *val); 3975 3976 typedef enum 3977 { 3978 LSM6DSO_SEL_BY_HW = 0x00, /* bus mode select by HW (SPI 3W disable) */ 3979 LSM6DSO_SPI_4W = 0x06, /* Only SPI: SDO / SDI separated pins */ 3980 LSM6DSO_SPI_3W = 0x07, /* Only SPI: SDO / SDI share the same pin */ 3981 LSM6DSO_I2C = 0x04, /* Only I2C */ 3982 LSM6DSO_I3C_T_50us = 0x02, /* I3C: available time equal to 50 us */ 3983 LSM6DSO_I3C_T_2us = 0x12, /* I3C: available time equal to 2 us */ 3984 LSM6DSO_I3C_T_1ms = 0x22, /* I3C: available time equal to 1 ms */ 3985 LSM6DSO_I3C_T_25ms = 0x32, /* I3C: available time equal to 25 ms */ 3986 } lsm6dso_ui_bus_md_t; 3987 3988 typedef enum 3989 { 3990 LSM6DSO_SPI_4W_AUX = 0x00, 3991 LSM6DSO_SPI_3W_AUX = 0x01, 3992 } lsm6dso_aux_bus_md_t; 3993 3994 typedef struct 3995 { 3996 lsm6dso_ui_bus_md_t ui_bus_md; 3997 lsm6dso_aux_bus_md_t aux_bus_md; 3998 } lsm6dso_bus_mode_t; 3999 int32_t lsm6dso_bus_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, 4000 lsm6dso_bus_mode_t val); 4001 int32_t lsm6dso_bus_mode_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, 4002 lsm6dso_bus_mode_t *val); 4003 4004 typedef enum 4005 { 4006 LSM6DSO_DRV_RDY = 0x00, /* Initialize the device for driver usage */ 4007 LSM6DSO_BOOT = 0x01, /* Restore calib. param. ( it takes 10ms ) */ 4008 LSM6DSO_RESET = 0x02, /* Reset configuration registers */ 4009 LSM6DSO_FIFO_COMP = 0x04, /* FIFO compression initialization request. */ 4010 LSM6DSO_FSM = 0x08, /* Finite State Machine initialization request */ 4011 LSM6DSO_PEDO = 0x20, /* Pedometer algo initialization request. */ 4012 LSM6DSO_TILT = 0x40, /* Tilt algo initialization request */ 4013 LSM6DSO_SMOTION = 0x80, /* Significant Motion initialization request */ 4014 } lsm6dso_init_t; 4015 int32_t lsm6dso_init_set(stmdev_ctx_t *ctx, lsm6dso_init_t val); 4016 4017 typedef struct 4018 { 4019 uint8_t sw_reset : 4020 1; /* Restoring configuration registers */ 4021 uint8_t boot : 1; /* Restoring calibration parameters */ 4022 uint8_t drdy_xl : 1; /* Accelerometer data ready */ 4023 uint8_t drdy_g : 1; /* Gyroscope data ready */ 4024 uint8_t drdy_temp : 1; /* Temperature data ready */ 4025 uint8_t ois_drdy_xl : 1; /* Accelerometer data ready on OIS */ 4026 uint8_t ois_drdy_g : 1; /* Gyroscope data ready on OIS */ 4027 uint8_t ois_gyro_settling : 4028 1; /* Gyroscope is in the settling phase */ 4029 } lsm6dso_status_t; 4030 int32_t lsm6dso_status_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, 4031 lsm6dso_status_t *val); 4032 4033 typedef struct 4034 { 4035 uint8_t sdo_sa0_pull_up : 1; /* 1 = pull-up on SDO/SA0 pin */ 4036 uint8_t aux_sdo_ocs_pull_up : 4037 1; /* 1 = pull-up on OCS_Aux/SDO_Aux pins */ 4038 uint8_t int1_int2_push_pull : 1; /* 1 = push-pull / 0 = open-drain*/ 4039 uint8_t int1_pull_down : 4040 1; /* 1 = pull-down always disabled (0=auto) */ 4041 } lsm6dso_pin_conf_t; 4042 int32_t lsm6dso_pin_conf_set(stmdev_ctx_t *ctx, 4043 lsm6dso_pin_conf_t val); 4044 int32_t lsm6dso_pin_conf_get(stmdev_ctx_t *ctx, 4045 lsm6dso_pin_conf_t *val); 4046 4047 typedef struct 4048 { 4049 uint8_t active_low : 1; /* 1 = active low / 0 = active high */ 4050 uint8_t base_latched : 4051 1; /* base functions are: FF, WU, 6D, Tap, Act/Inac */ 4052 uint8_t emb_latched : 4053 1; /* emb functions are: Pedo, Tilt, SMot, Timestamp */ 4054 } lsm6dso_int_mode_t; 4055 int32_t lsm6dso_interrupt_mode_set(stmdev_ctx_t *ctx, 4056 lsm6dso_int_mode_t val); 4057 int32_t lsm6dso_interrupt_mode_get(stmdev_ctx_t *ctx, 4058 lsm6dso_int_mode_t *val); 4059 4060 typedef struct 4061 { 4062 uint8_t drdy_xl : 1; /* Accelerometer data ready */ 4063 uint8_t drdy_g : 1; /* Gyroscope data ready */ 4064 uint8_t drdy_temp : 4065 1; /* Temperature data ready (1 = int2 pin disable) */ 4066 uint8_t boot : 1; /* Restoring calibration parameters */ 4067 uint8_t fifo_th : 1; /* FIFO threshold reached */ 4068 uint8_t fifo_ovr : 1; /* FIFO overrun */ 4069 uint8_t fifo_full : 1; /* FIFO full */ 4070 uint8_t fifo_bdr : 1; /* FIFO Batch counter threshold reached */ 4071 uint8_t den_flag : 4072 1; /* external trigger level recognition (DEN) */ 4073 uint8_t sh_endop : 1; /* sensor hub end operation */ 4074 uint8_t timestamp : 4075 1; /* timestamp overflow (1 = int2 pin disable) */ 4076 uint8_t six_d : 1; /* orientation change (6D/4D detection) */ 4077 uint8_t double_tap : 1; /* double-tap event */ 4078 uint8_t free_fall : 1; /* free fall event */ 4079 uint8_t wake_up : 1; /* wake up event */ 4080 uint8_t single_tap : 1; /* single-tap event */ 4081 uint8_t sleep_change : 4082 1; /* Act/Inact (or Vice-versa) status changed */ 4083 uint8_t step_detector : 1; /* Step detected */ 4084 uint8_t tilt : 1; /* Relative tilt event detected */ 4085 uint8_t sig_mot : 1; /* "significant motion" event detected */ 4086 uint8_t fsm_lc : 4087 1; /* fsm long counter timeout interrupt event */ 4088 uint8_t fsm1 : 1; /* fsm 1 interrupt event */ 4089 uint8_t fsm2 : 1; /* fsm 2 interrupt event */ 4090 uint8_t fsm3 : 1; /* fsm 3 interrupt event */ 4091 uint8_t fsm4 : 1; /* fsm 4 interrupt event */ 4092 uint8_t fsm5 : 1; /* fsm 5 interrupt event */ 4093 uint8_t fsm6 : 1; /* fsm 6 interrupt event */ 4094 uint8_t fsm7 : 1; /* fsm 7 interrupt event */ 4095 uint8_t fsm8 : 1; /* fsm 8 interrupt event */ 4096 uint8_t fsm9 : 1; /* fsm 9 interrupt event */ 4097 uint8_t fsm10 : 1; /* fsm 10 interrupt event */ 4098 uint8_t fsm11 : 1; /* fsm 11 interrupt event */ 4099 uint8_t fsm12 : 1; /* fsm 12 interrupt event */ 4100 uint8_t fsm13 : 1; /* fsm 13 interrupt event */ 4101 uint8_t fsm14 : 1; /* fsm 14 interrupt event */ 4102 uint8_t fsm15 : 1; /* fsm 15 interrupt event */ 4103 uint8_t fsm16 : 1; /* fsm 16 interrupt event */ 4104 uint8_t mlc1 : 1; /* mlc 1 interrupt event */ 4105 uint8_t mlc2 : 1; /* mlc 2 interrupt event */ 4106 uint8_t mlc3 : 1; /* mlc 3 interrupt event */ 4107 uint8_t mlc4 : 1; /* mlc 4 interrupt event */ 4108 uint8_t mlc5 : 1; /* mlc 5 interrupt event */ 4109 uint8_t mlc6 : 1; /* mlc 6 interrupt event */ 4110 uint8_t mlc7 : 1; /* mlc 7 interrupt event */ 4111 uint8_t mlc8 : 1; /* mlc 8 interrupt event */ 4112 } lsm6dso_pin_int1_route_t; 4113 4114 int32_t lsm6dso_pin_int1_route_set(stmdev_ctx_t *ctx, 4115 lsm6dso_pin_int1_route_t val); 4116 int32_t lsm6dso_pin_int1_route_get(stmdev_ctx_t *ctx, 4117 lsm6dso_pin_int1_route_t *val); 4118 4119 typedef struct 4120 { 4121 uint8_t drdy_ois : 1; /* OIS chain data ready */ 4122 uint8_t drdy_xl : 1; /* Accelerometer data ready */ 4123 uint8_t drdy_g : 1; /* Gyroscope data ready */ 4124 uint8_t drdy_temp : 1; /* Temperature data ready */ 4125 uint8_t fifo_th : 1; /* FIFO threshold reached */ 4126 uint8_t fifo_ovr : 1; /* FIFO overrun */ 4127 uint8_t fifo_full : 1; /* FIFO full */ 4128 uint8_t fifo_bdr : 1; /* FIFO Batch counter threshold reached */ 4129 uint8_t timestamp : 1; /* timestamp overflow */ 4130 uint8_t six_d : 1; /* orientation change (6D/4D detection) */ 4131 uint8_t double_tap : 1; /* double-tap event */ 4132 uint8_t free_fall : 1; /* free fall event */ 4133 uint8_t wake_up : 1; /* wake up event */ 4134 uint8_t single_tap : 1; /* single-tap event */ 4135 uint8_t sleep_change : 4136 1; /* Act/Inact (or Vice-versa) status changed */ 4137 uint8_t step_detector : 1; /* Step detected */ 4138 uint8_t tilt : 1; /* Relative tilt event detected */ 4139 uint8_t sig_mot : 1; /* "significant motion" event detected */ 4140 uint8_t fsm_lc : 4141 1; /* fsm long counter timeout interrupt event */ 4142 uint8_t fsm1 : 1; /* fsm 1 interrupt event */ 4143 uint8_t fsm2 : 1; /* fsm 2 interrupt event */ 4144 uint8_t fsm3 : 1; /* fsm 3 interrupt event */ 4145 uint8_t fsm4 : 1; /* fsm 4 interrupt event */ 4146 uint8_t fsm5 : 1; /* fsm 5 interrupt event */ 4147 uint8_t fsm6 : 1; /* fsm 6 interrupt event */ 4148 uint8_t fsm7 : 1; /* fsm 7 interrupt event */ 4149 uint8_t fsm8 : 1; /* fsm 8 interrupt event */ 4150 uint8_t fsm9 : 1; /* fsm 9 interrupt event */ 4151 uint8_t fsm10 : 1; /* fsm 10 interrupt event */ 4152 uint8_t fsm11 : 1; /* fsm 11 interrupt event */ 4153 uint8_t fsm12 : 1; /* fsm 12 interrupt event */ 4154 uint8_t fsm13 : 1; /* fsm 13 interrupt event */ 4155 uint8_t fsm14 : 1; /* fsm 14 interrupt event */ 4156 uint8_t fsm15 : 1; /* fsm 15 interrupt event */ 4157 uint8_t fsm16 : 1; /* fsm 16 interrupt event */ 4158 uint8_t mlc1 : 1; /* mlc 1 interrupt event */ 4159 uint8_t mlc2 : 1; /* mlc 2 interrupt event */ 4160 uint8_t mlc3 : 1; /* mlc 3 interrupt event */ 4161 uint8_t mlc4 : 1; /* mlc 4 interrupt event */ 4162 uint8_t mlc5 : 1; /* mlc 5 interrupt event */ 4163 uint8_t mlc6 : 1; /* mlc 6 interrupt event */ 4164 uint8_t mlc7 : 1; /* mlc 7 interrupt event */ 4165 uint8_t mlc8 : 1; /* mlc 8 interrupt event */ 4166 } lsm6dso_pin_int2_route_t; 4167 4168 int32_t lsm6dso_pin_int2_route_set(stmdev_ctx_t *ctx, 4169 stmdev_ctx_t *aux_ctx, 4170 lsm6dso_pin_int2_route_t val); 4171 int32_t lsm6dso_pin_int2_route_get(stmdev_ctx_t *ctx, 4172 stmdev_ctx_t *aux_ctx, 4173 lsm6dso_pin_int2_route_t *val); 4174 4175 typedef struct 4176 { 4177 uint8_t drdy_xl : 1; /* Accelerometer data ready */ 4178 uint8_t drdy_g : 1; /* Gyroscope data ready */ 4179 uint8_t drdy_temp : 1; /* Temperature data ready */ 4180 uint8_t den_flag : 4181 1; /* external trigger level recognition (DEN) */ 4182 uint8_t timestamp : 4183 1; /* timestamp overflow (1 = int2 pin disable) */ 4184 uint8_t free_fall : 1; /* free fall event */ 4185 uint8_t wake_up : 1; /* wake up event */ 4186 uint8_t wake_up_z : 1; /* wake up on Z axis event */ 4187 uint8_t wake_up_y : 1; /* wake up on Y axis event */ 4188 uint8_t wake_up_x : 1; /* wake up on X axis event */ 4189 uint8_t single_tap : 1; /* single-tap event */ 4190 uint8_t double_tap : 1; /* double-tap event */ 4191 uint8_t tap_z : 1; /* single-tap on Z axis event */ 4192 uint8_t tap_y : 1; /* single-tap on Y axis event */ 4193 uint8_t tap_x : 1; /* single-tap on X axis event */ 4194 uint8_t tap_sign : 1; /* sign of tap event (0-pos / 1-neg) */ 4195 uint8_t six_d : 4196 1; /* orientation change (6D/4D detection) */ 4197 uint8_t six_d_xl : 4198 1; /* X-axis low 6D/4D event (under threshold) */ 4199 uint8_t six_d_xh : 4200 1; /* X-axis high 6D/4D event (over threshold) */ 4201 uint8_t six_d_yl : 4202 1; /* Y-axis low 6D/4D event (under threshold) */ 4203 uint8_t six_d_yh : 4204 1; /* Y-axis high 6D/4D event (over threshold) */ 4205 uint8_t six_d_zl : 4206 1; /* Z-axis low 6D/4D event (under threshold) */ 4207 uint8_t six_d_zh : 4208 1; /* Z-axis high 6D/4D event (over threshold) */ 4209 uint8_t sleep_change : 4210 1; /* Act/Inact (or Vice-versa) status changed */ 4211 uint8_t sleep_state : 4212 1; /* Act/Inact status flag (0-Act / 1-Inact) */ 4213 uint8_t step_detector : 1; /* Step detected */ 4214 uint8_t tilt : 1; /* Relative tilt event detected */ 4215 uint8_t sig_mot : 4216 1; /* "significant motion" event detected */ 4217 uint8_t fsm_lc : 4218 1; /* fsm long counter timeout interrupt event */ 4219 uint8_t fsm1 : 1; /* fsm 1 interrupt event */ 4220 uint8_t fsm2 : 1; /* fsm 2 interrupt event */ 4221 uint8_t fsm3 : 1; /* fsm 3 interrupt event */ 4222 uint8_t fsm4 : 1; /* fsm 4 interrupt event */ 4223 uint8_t fsm5 : 1; /* fsm 5 interrupt event */ 4224 uint8_t fsm6 : 1; /* fsm 6 interrupt event */ 4225 uint8_t fsm7 : 1; /* fsm 7 interrupt event */ 4226 uint8_t fsm8 : 1; /* fsm 8 interrupt event */ 4227 uint8_t fsm9 : 1; /* fsm 9 interrupt event */ 4228 uint8_t fsm10 : 1; /* fsm 10 interrupt event */ 4229 uint8_t fsm11 : 1; /* fsm 11 interrupt event */ 4230 uint8_t fsm12 : 1; /* fsm 12 interrupt event */ 4231 uint8_t fsm13 : 1; /* fsm 13 interrupt event */ 4232 uint8_t fsm14 : 1; /* fsm 14 interrupt event */ 4233 uint8_t fsm15 : 1; /* fsm 15 interrupt event */ 4234 uint8_t fsm16 : 1; /* fsm 16 interrupt event */ 4235 uint8_t mlc1 : 1; /* mlc 1 interrupt event */ 4236 uint8_t mlc2 : 1; /* mlc 2 interrupt event */ 4237 uint8_t mlc3 : 1; /* mlc 3 interrupt event */ 4238 uint8_t mlc4 : 1; /* mlc 4 interrupt event */ 4239 uint8_t mlc5 : 1; /* mlc 5 interrupt event */ 4240 uint8_t mlc6 : 1; /* mlc 6 interrupt event */ 4241 uint8_t mlc7 : 1; /* mlc 7 interrupt event */ 4242 uint8_t mlc8 : 1; /* mlc 8 interrupt event */ 4243 uint8_t sh_endop : 1; /* sensor hub end operation */ 4244 uint8_t sh_slave0_nack : 4245 1; /* Not acknowledge on sensor hub slave 0 */ 4246 uint8_t sh_slave1_nack : 4247 1; /* Not acknowledge on sensor hub slave 1 */ 4248 uint8_t sh_slave2_nack : 4249 1; /* Not acknowledge on sensor hub slave 2 */ 4250 uint8_t sh_slave3_nack : 4251 1; /* Not acknowledge on sensor hub slave 3 */ 4252 uint8_t sh_wr_once : 4253 1; /* "WRITE_ONCE" end on sensor hub slave 0 */ 4254 uint16_t fifo_diff : 4255 10; /* Number of unread sensor data in FIFO*/ 4256 uint8_t fifo_ovr_latched : 1; /* Latched FIFO overrun status */ 4257 uint8_t fifo_bdr : 4258 1; /* FIFO Batch counter threshold reached */ 4259 uint8_t fifo_full : 1; /* FIFO full */ 4260 uint8_t fifo_ovr : 1; /* FIFO overrun */ 4261 uint8_t fifo_th : 1; /* FIFO threshold reached */ 4262 } lsm6dso_all_sources_t; 4263 int32_t lsm6dso_all_sources_get(stmdev_ctx_t *ctx, 4264 lsm6dso_all_sources_t *val); 4265 4266 typedef struct 4267 { 4268 uint8_t odr_fine_tune; 4269 } dev_cal_t; 4270 int32_t lsm6dso_calibration_get(stmdev_ctx_t *ctx, dev_cal_t *val); 4271 4272 typedef enum 4273 { 4274 LSM6DSO_XL_UI_OFF = 0x00, /* in power down */ 4275 LSM6DSO_XL_UI_1Hz6_LP = 0x1B, /* @1Hz6 (low power) */ 4276 LSM6DSO_XL_UI_1Hz6_ULP = 0x2B, /* @1Hz6 (ultra low/Gy, OIS imu off) */ 4277 LSM6DSO_XL_UI_12Hz5_HP = 0x01, /* @12Hz5 (high performance) */ 4278 LSM6DSO_XL_UI_12Hz5_LP = 0x11, /* @12Hz5 (low power) */ 4279 LSM6DSO_XL_UI_12Hz5_ULP = 0x21, /* @12Hz5 (ultra low/Gy, OIS imu off) */ 4280 LSM6DSO_XL_UI_26Hz_HP = 0x02, /* @26Hz (high performance) */ 4281 LSM6DSO_XL_UI_26Hz_LP = 0x12, /* @26Hz (low power) */ 4282 LSM6DSO_XL_UI_26Hz_ULP = 0x22, /* @26Hz (ultra low/Gy, OIS imu off) */ 4283 LSM6DSO_XL_UI_52Hz_HP = 0x03, /* @52Hz (high performance) */ 4284 LSM6DSO_XL_UI_52Hz_LP = 0x13, /* @52Hz (low power) */ 4285 LSM6DSO_XL_UI_52Hz_ULP = 0x23, /* @52Hz (ultra low/Gy, OIS imu off) */ 4286 LSM6DSO_XL_UI_104Hz_HP = 0x04, /* @104Hz (high performance) */ 4287 LSM6DSO_XL_UI_104Hz_NM = 0x14, /* @104Hz (normal mode) */ 4288 LSM6DSO_XL_UI_104Hz_ULP = 0x24, /* @104Hz (ultra low/Gy, OIS imu off) */ 4289 LSM6DSO_XL_UI_208Hz_HP = 0x05, /* @208Hz (high performance) */ 4290 LSM6DSO_XL_UI_208Hz_NM = 0x15, /* @208Hz (normal mode) */ 4291 LSM6DSO_XL_UI_208Hz_ULP = 0x25, /* @208Hz (ultra low/Gy, OIS imu off) */ 4292 LSM6DSO_XL_UI_416Hz_HP = 0x06, /* @416Hz (high performance) */ 4293 LSM6DSO_XL_UI_833Hz_HP = 0x07, /* @833Hz (high performance) */ 4294 LSM6DSO_XL_UI_1667Hz_HP = 0x08, /* @1kHz66 (high performance) */ 4295 LSM6DSO_XL_UI_3333Hz_HP = 0x09, /* @3kHz33 (high performance) */ 4296 LSM6DSO_XL_UI_6667Hz_HP = 0x0A, /* @6kHz66 (high performance) */ 4297 } lsm6dso_odr_xl_ui_t; 4298 4299 typedef enum 4300 { 4301 LSM6DSO_XL_UI_2g = 0, 4302 LSM6DSO_XL_UI_4g = 2, 4303 LSM6DSO_XL_UI_8g = 3, 4304 LSM6DSO_XL_UI_16g = 1, /* OIS full scale is also forced to be 16g */ 4305 } lsm6dso_fs_xl_ui_t; 4306 4307 typedef enum 4308 { 4309 LSM6DSO_GY_UI_OFF = 0x00, /* gy in power down */ 4310 LSM6DSO_GY_UI_12Hz5_LP = 0x11, /* gy @12Hz5 (low power) */ 4311 LSM6DSO_GY_UI_12Hz5_HP = 0x01, /* gy @12Hz5 (high performance) */ 4312 LSM6DSO_GY_UI_26Hz_LP = 0x12, /* gy @26Hz (low power) */ 4313 LSM6DSO_GY_UI_26Hz_HP = 0x02, /* gy @26Hz (high performance) */ 4314 LSM6DSO_GY_UI_52Hz_LP = 0x13, /* gy @52Hz (low power) */ 4315 LSM6DSO_GY_UI_52Hz_HP = 0x03, /* gy @52Hz (high performance) */ 4316 LSM6DSO_GY_UI_104Hz_NM = 0x14, /* gy @104Hz (low power) */ 4317 LSM6DSO_GY_UI_104Hz_HP = 0x04, /* gy @104Hz (high performance) */ 4318 LSM6DSO_GY_UI_208Hz_NM = 0x15, /* gy @208Hz (low power) */ 4319 LSM6DSO_GY_UI_208Hz_HP = 0x05, /* gy @208Hz (high performance) */ 4320 LSM6DSO_GY_UI_416Hz_HP = 0x06, /* gy @416Hz (high performance) */ 4321 LSM6DSO_GY_UI_833Hz_HP = 0x07, /* gy @833Hz (high performance) */ 4322 LSM6DSO_GY_UI_1667Hz_HP = 0x08, /* gy @1kHz66 (high performance) */ 4323 LSM6DSO_GY_UI_3333Hz_HP = 0x09, /* gy @3kHz33 (high performance) */ 4324 LSM6DSO_GY_UI_6667Hz_HP = 0x0A, /* gy @6kHz66 (high performance) */ 4325 } lsm6dso_odr_g_ui_t; 4326 4327 typedef enum 4328 { 4329 LSM6DSO_GY_UI_250dps = 0, 4330 LSM6DSO_GY_UI_125dps = 1, 4331 LSM6DSO_GY_UI_500dps = 2, 4332 LSM6DSO_GY_UI_1000dps = 4, 4333 LSM6DSO_GY_UI_2000dps = 6, 4334 } lsm6dso_fs_g_ui_t; 4335 4336 typedef enum 4337 { 4338 LSM6DSO_OIS_ONLY_AUX = 0x00, /* Auxiliary SPI full control */ 4339 LSM6DSO_OIS_MIXED = 0x01, /* Enabling by UI / read-config by AUX */ 4340 } lsm6dso_ctrl_md_t; 4341 4342 typedef enum 4343 { 4344 LSM6DSO_XL_OIS_OFF = 0x00, /* in power down */ 4345 LSM6DSO_XL_OIS_6667Hz_HP = 0x01, /* @6kHz OIS imu active/NO ULP on UI */ 4346 } lsm6dso_odr_xl_ois_noaux_t; 4347 4348 typedef enum 4349 { 4350 LSM6DSO_XL_OIS_2g = 0, 4351 LSM6DSO_XL_OIS_4g = 2, 4352 LSM6DSO_XL_OIS_8g = 3, 4353 LSM6DSO_XL_OIS_16g = 1, /* UI full scale is also forced to be 16g */ 4354 } lsm6dso_fs_xl_ois_noaux_t; 4355 4356 typedef enum 4357 { 4358 LSM6DSO_GY_OIS_OFF = 0x00, /* in power down */ 4359 LSM6DSO_GY_OIS_6667Hz_HP = 0x01, /* @6kHz No Ultra Low Power*/ 4360 } lsm6dso_odr_g_ois_noaux_t; 4361 4362 typedef enum 4363 { 4364 LSM6DSO_GY_OIS_250dps = 0, 4365 LSM6DSO_GY_OIS_125dps = 1, 4366 LSM6DSO_GY_OIS_500dps = 2, 4367 LSM6DSO_GY_OIS_1000dps = 4, 4368 LSM6DSO_GY_OIS_2000dps = 6, 4369 } lsm6dso_fs_g_ois_noaux_t; 4370 4371 typedef enum 4372 { 4373 LSM6DSO_FSM_DISABLE = 0x00, 4374 LSM6DSO_FSM_XL = 0x01, 4375 LSM6DSO_FSM_GY = 0x02, 4376 LSM6DSO_FSM_XL_GY = 0x03, 4377 } lsm6dso_sens_fsm_t; 4378 4379 typedef enum 4380 { 4381 LSM6DSO_FSM_12Hz5 = 0x00, 4382 LSM6DSO_FSM_26Hz = 0x01, 4383 LSM6DSO_FSM_52Hz = 0x02, 4384 LSM6DSO_FSM_104Hz = 0x03, 4385 } lsm6dso_odr_fsm_t; 4386 4387 typedef struct 4388 { 4389 struct 4390 { 4391 struct 4392 { 4393 lsm6dso_odr_xl_ui_t odr; 4394 lsm6dso_fs_xl_ui_t fs; 4395 } xl; 4396 struct 4397 { 4398 lsm6dso_odr_g_ui_t odr; 4399 lsm6dso_fs_g_ui_t fs; 4400 } gy; 4401 } ui; 4402 struct 4403 { 4404 lsm6dso_ctrl_md_t ctrl_md; 4405 struct 4406 { 4407 lsm6dso_odr_xl_ois_noaux_t odr; 4408 lsm6dso_fs_xl_ois_noaux_t fs; 4409 } xl; 4410 struct 4411 { 4412 lsm6dso_odr_g_ois_noaux_t odr; 4413 lsm6dso_fs_g_ois_noaux_t fs; 4414 } gy; 4415 } ois; 4416 struct 4417 { 4418 lsm6dso_sens_fsm_t sens; 4419 lsm6dso_odr_fsm_t odr; 4420 } fsm; 4421 } lsm6dso_md_t; 4422 int32_t lsm6dso_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, 4423 lsm6dso_md_t *val); 4424 int32_t lsm6dso_mode_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, 4425 lsm6dso_md_t *val); 4426 typedef struct 4427 { 4428 struct 4429 { 4430 struct 4431 { 4432 float_t mg[3]; 4433 int16_t raw[3]; 4434 } xl; 4435 struct 4436 { 4437 float_t mdps[3]; 4438 int16_t raw[3]; 4439 } gy; 4440 struct 4441 { 4442 float_t deg_c; 4443 int16_t raw; 4444 } heat; 4445 } ui; 4446 struct 4447 { 4448 struct 4449 { 4450 float_t mg[3]; 4451 int16_t raw[3]; 4452 } xl; 4453 struct 4454 { 4455 float_t mdps[3]; 4456 int16_t raw[3]; 4457 } gy; 4458 } ois; 4459 } lsm6dso_data_t; 4460 int32_t lsm6dso_data_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, 4461 lsm6dso_md_t *md, lsm6dso_data_t *data); 4462 4463 typedef struct 4464 { 4465 uint8_t sig_mot : 1; /* significant motion */ 4466 uint8_t tilt : 1; /* tilt detection */ 4467 uint8_t step : 1; /* step counter/detector */ 4468 uint8_t step_adv : 1; /* step counter advanced mode */ 4469 uint8_t fsm : 1; /* finite state machine */ 4470 uint8_t fifo_compr : 1; /* FIFO compression */ 4471 } lsm6dso_emb_sens_t; 4472 int32_t lsm6dso_embedded_sens_set(stmdev_ctx_t *ctx, 4473 lsm6dso_emb_sens_t *emb_sens); 4474 int32_t lsm6dso_embedded_sens_get(stmdev_ctx_t *ctx, 4475 lsm6dso_emb_sens_t *emb_sens); 4476 int32_t lsm6dso_embedded_sens_off(stmdev_ctx_t *ctx); 4477 4478 /** 4479 * @} 4480 * 4481 */ 4482 4483 #ifdef __cplusplus 4484 } 4485 #endif 4486 4487 #endif /*LSM6DSO_DRIVER_H */ 4488 4489 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 4490
