1 /**
2 ******************************************************************************
3 * @file lsm6dso16is_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LSM6DSO16IS driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lsm6dso16is_reg.h"
21
22 /**
23 * @defgroup LSM6DSO16IS
24 * @brief This file provides a set of functions needed to drive the
25 * lsm6dso16is enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup Interfaces functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx communication interface handler.(ptr)
43 * @param reg first register address to read.
44 * @param data buffer for data read.(ptr)
45 * @param len number of consecutive register to read.
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lsm6dso16is_read_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lsm6dso16is_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 ret = ctx->read_reg(ctx->handle, reg, data, len);
56
57 return ret;
58 }
59
60 /**
61 * @brief Write generic device register
62 *
63 * @param ctx communication interface handler.(ptr)
64 * @param reg first register address to write.
65 * @param data the buffer contains data to be written.(ptr)
66 * @param len number of consecutive register to write.
67 * @retval interface status (MANDATORY: return 0 -> no Error)
68 *
69 */
lsm6dso16is_write_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)70 int32_t __weak lsm6dso16is_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
71 uint8_t *data,
72 uint16_t len)
73 {
74 int32_t ret;
75
76 ret = ctx->write_reg(ctx->handle, reg, data, len);
77
78 return ret;
79 }
80
81 /**
82 * @}
83 *
84 */
85
86 /**
87 * @defgroup LSM6DSO16IS_Sensitivity
88 * @brief These functions convert raw-data into engineering units.
89 * @{
90 *
91 */
92
lsm6dso16is_from_fs2g_to_mg(int16_t lsb)93 float_t lsm6dso16is_from_fs2g_to_mg(int16_t lsb)
94 {
95 return ((float_t)lsb * 0.061f);
96 }
97
lsm6dso16is_from_fs4g_to_mg(int16_t lsb)98 float_t lsm6dso16is_from_fs4g_to_mg(int16_t lsb)
99 {
100 return ((float_t)lsb * 0.122f);
101 }
102
lsm6dso16is_from_fs8g_to_mg(int16_t lsb)103 float_t lsm6dso16is_from_fs8g_to_mg(int16_t lsb)
104 {
105 return ((float_t)lsb * 0.244f);
106 }
107
lsm6dso16is_from_fs16g_to_mg(int16_t lsb)108 float_t lsm6dso16is_from_fs16g_to_mg(int16_t lsb)
109 {
110 return ((float_t)lsb * 0.488f);
111 }
112
lsm6dso16is_from_fs125dps_to_mdps(int16_t lsb)113 float_t lsm6dso16is_from_fs125dps_to_mdps(int16_t lsb)
114 {
115 return ((float_t)lsb * 4.375f);
116 }
117
lsm6dso16is_from_fs250dps_to_mdps(int16_t lsb)118 float_t lsm6dso16is_from_fs250dps_to_mdps(int16_t lsb)
119 {
120 return ((float_t)lsb * 8.75f);
121 }
122
lsm6dso16is_from_fs500dps_to_mdps(int16_t lsb)123 float_t lsm6dso16is_from_fs500dps_to_mdps(int16_t lsb)
124 {
125 return ((float_t)lsb * 17.50f);
126 }
127
lsm6dso16is_from_fs1000dps_to_mdps(int16_t lsb)128 float_t lsm6dso16is_from_fs1000dps_to_mdps(int16_t lsb)
129 {
130 return ((float_t)lsb * 35.0f);
131 }
132
lsm6dso16is_from_fs2000dps_to_mdps(int16_t lsb)133 float_t lsm6dso16is_from_fs2000dps_to_mdps(int16_t lsb)
134 {
135 return ((float_t)lsb * 70.0f);
136 }
137
lsm6dso16is_from_lsb_to_celsius(int16_t lsb)138 float_t lsm6dso16is_from_lsb_to_celsius(int16_t lsb)
139 {
140 return (((float_t)lsb / 256.0f) + 25.0f);
141 }
142
143 /**
144 * @defgroup Common
145 * @brief Common
146 * @{/
147 *
148 */
149
150 /**
151 * @brief Difference in percentage of the effective ODR (and timestamp rate)
152 * with respect to the typical.[set]
153 * Step: 0.15%. 8-bit format, 2's complement.
154 *
155 * @param ctx Read / write interface definitions.(ptr)
156 * @param val Change the values of freq_fine in reg INTERNAL_FREQ_FINE
157 * @retval Interface status (MANDATORY: return 0 -> no Error).
158 *
159 */
lsm6dso16is_odr_cal_reg_set(stmdev_ctx_t * ctx,uint8_t val)160 int32_t lsm6dso16is_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val)
161 {
162 lsm6dso16is_internal_freq_fine_t internal_freq_fine;
163 int32_t ret;
164
165 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_INTERNAL_FREQ_FINE,
166 (uint8_t *)&internal_freq_fine, 1);
167
168 if (ret == 0)
169 {
170 internal_freq_fine.freq_fine = (uint8_t)val;
171 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_INTERNAL_FREQ_FINE,
172 (uint8_t *)&internal_freq_fine, 1);
173 }
174
175 return ret;
176 }
177
178 /**
179 * @brief Difference in percentage of the effective ODR (and timestamp rate)
180 * with respect to the typical.[get]
181 * Step: 0.15%. 8-bit format, 2's complement.
182 *
183 * @param ctx Read / write interface definitions.(ptr)
184 * @param val Change the values of freq_fine in reg INTERNAL_FREQ_FINE
185 * @retval Interface status (MANDATORY: return 0 -> no Error).
186 *
187 */
lsm6dso16is_odr_cal_reg_get(stmdev_ctx_t * ctx,uint8_t * val)188 int32_t lsm6dso16is_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val)
189 {
190 lsm6dso16is_internal_freq_fine_t internal_freq_fine;
191 int32_t ret;
192
193 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_INTERNAL_FREQ_FINE,
194 (uint8_t *)&internal_freq_fine, 1);
195 *val = internal_freq_fine.freq_fine;
196
197 return ret;
198 }
199
200 /**
201 * @brief Change memory bank.[set]
202 *
203 * @param ctx read / write interface definitions
204 * @param val MAIN_MEM_BANK, EMBED_FUNC_MEM_BANK, SENSOR_HUB_MEM_BANK, ISPU_MEM_BANK,
205 * @retval interface status (MANDATORY: return 0 -> no Error)
206 *
207 */
lsm6dso16is_mem_bank_set(stmdev_ctx_t * ctx,lsm6dso16is_mem_bank_t val)208 int32_t lsm6dso16is_mem_bank_set(stmdev_ctx_t *ctx, lsm6dso16is_mem_bank_t val)
209 {
210 lsm6dso16is_func_cfg_access_t func_cfg_access;
211 int32_t ret;
212
213 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
214
215 if (ret == 0)
216 {
217 func_cfg_access.shub_reg_access = (val == LSM6DSO16IS_SENSOR_HUB_MEM_BANK) ? 0x1U : 0x0U;
218 func_cfg_access.ispu_reg_access = (val == LSM6DSO16IS_ISPU_MEM_BANK) ? 0x1U : 0x0U;
219 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
220 }
221
222 return ret;
223 }
224
225 /**
226 * @brief Change memory bank.[get]
227 *
228 * @param ctx read / write interface definitions
229 * @param val MAIN_MEM_BANK, EMBED_FUNC_MEM_BANK, SENSOR_HUB_MEM_BANK, ISPU_MEM_BANK,
230 * @retval interface status (MANDATORY: return 0 -> no Error)
231 *
232 */
lsm6dso16is_mem_bank_get(stmdev_ctx_t * ctx,lsm6dso16is_mem_bank_t * val)233 int32_t lsm6dso16is_mem_bank_get(stmdev_ctx_t *ctx, lsm6dso16is_mem_bank_t *val)
234 {
235 lsm6dso16is_func_cfg_access_t func_cfg_access;
236 int32_t ret;
237
238 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
239
240 if (func_cfg_access.shub_reg_access == 1U)
241 {
242 *val = LSM6DSO16IS_SENSOR_HUB_MEM_BANK;
243 }
244 else if (func_cfg_access.ispu_reg_access == 1U)
245 {
246 *val = LSM6DSO16IS_ISPU_MEM_BANK;
247 }
248 else
249 {
250 *val = LSM6DSO16IS_MAIN_MEM_BANK;
251 }
252
253 return ret;
254 }
255
256 /**
257 * @brief Enables pulsed data-ready mode (~75 us).[set]
258 *
259 * @param ctx read / write interface definitions
260 * @param val DRDY_LATCHED, DRDY_PULSED,
261 * @retval interface status (MANDATORY: return 0 -> no Error)
262 *
263 */
lsm6dso16is_data_ready_mode_set(stmdev_ctx_t * ctx,lsm6dso16is_data_ready_mode_t val)264 int32_t lsm6dso16is_data_ready_mode_set(stmdev_ctx_t *ctx,
265 lsm6dso16is_data_ready_mode_t val)
266 {
267 lsm6dso16is_drdy_pulsed_reg_t drdy_pulsed_reg;
268 int32_t ret;
269
270 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_DRDY_PULSED_REG, (uint8_t *)&drdy_pulsed_reg, 1);
271
272 if (ret == 0)
273 {
274 drdy_pulsed_reg.drdy_pulsed = ((uint8_t)val & 0x1U);
275 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_DRDY_PULSED_REG, (uint8_t *)&drdy_pulsed_reg, 1);
276 }
277
278 return ret;
279 }
280
281 /**
282 * @brief Enables pulsed data-ready mode (~75 us).[get]
283 *
284 * @param ctx read / write interface definitions
285 * @param val DRDY_LATCHED, DRDY_PULSED,
286 * @retval interface status (MANDATORY: return 0 -> no Error)
287 *
288 */
lsm6dso16is_data_ready_mode_get(stmdev_ctx_t * ctx,lsm6dso16is_data_ready_mode_t * val)289 int32_t lsm6dso16is_data_ready_mode_get(stmdev_ctx_t *ctx,
290 lsm6dso16is_data_ready_mode_t *val)
291 {
292 lsm6dso16is_drdy_pulsed_reg_t drdy_pulsed_reg;
293 int32_t ret;
294
295 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_DRDY_PULSED_REG, (uint8_t *)&drdy_pulsed_reg, 1);
296
297 switch ((drdy_pulsed_reg.drdy_pulsed))
298 {
299 case LSM6DSO16IS_DRDY_LATCHED:
300 *val = LSM6DSO16IS_DRDY_LATCHED;
301 break;
302
303 case LSM6DSO16IS_DRDY_PULSED:
304 *val = LSM6DSO16IS_DRDY_PULSED;
305 break;
306
307 default:
308 *val = LSM6DSO16IS_DRDY_LATCHED;
309 break;
310 }
311 return ret;
312 }
313
314 /**
315 * @brief Device ID.[get]
316 *
317 * @param ctx read / write interface definitions
318 * @param val Device ID.
319 * @retval interface status (MANDATORY: return 0 -> no Error)
320 *
321 */
lsm6dso16is_device_id_get(stmdev_ctx_t * ctx,uint8_t * val)322 int32_t lsm6dso16is_device_id_get(stmdev_ctx_t *ctx, uint8_t *val)
323 {
324 int32_t ret;
325
326 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_WHO_AM_I, (uint8_t *)val, 1);
327
328 return ret;
329 }
330
331 /**
332 * @brief Software reset. Restore the default values in user registers.[set]
333 *
334 * @param ctx Read / write interface definitions.(ptr)
335 * @retval Interface status (MANDATORY: return 0 -> no Error).
336 *
337 */
lsm6dso16is_software_reset(stmdev_ctx_t * ctx)338 int32_t lsm6dso16is_software_reset(stmdev_ctx_t *ctx)
339 {
340 lsm6dso16is_ctrl3_c_t ctrl3_c;
341 int32_t ret;
342
343 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
344
345 if (ret == 0)
346 {
347 ret += lsm6dso16is_xl_data_rate_set(ctx, LSM6DSO16IS_XL_ODR_OFF);
348 ret += lsm6dso16is_gy_data_rate_set(ctx, LSM6DSO16IS_GY_ODR_OFF);
349
350 ctrl3_c.sw_reset = PROPERTY_ENABLE;
351 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
352
353 do {
354 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
355 } while (ret == 0 && ctrl3_c.sw_reset == PROPERTY_ENABLE);
356 }
357
358 return ret;
359 }
360
361 /**
362 * @brief Reboot memory content. Reload the calibration parameters.[set]
363 *
364 * @param ctx Read / write interface definitions.(ptr)
365 * @param val Change the values of boot in reg CTRL_REG1
366 * @retval Interface status (MANDATORY: return 0 -> no Error).
367 *
368 */
lsm6dso16is_boot_set(stmdev_ctx_t * ctx,uint8_t val)369 int32_t lsm6dso16is_boot_set(stmdev_ctx_t *ctx, uint8_t val)
370 {
371 lsm6dso16is_ctrl3_c_t ctrl3_c;
372 int32_t ret;
373
374 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
375
376 if (ret == 0)
377 {
378 ctrl3_c.boot = val;
379 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
380 }
381
382 return ret;
383 }
384
385 /**
386 * @brief Reboot memory content. Reload the calibration parameters.[get]
387 *
388 * @param ctx Read / write interface definitions.(ptr)
389 * @param val Get the values of boot in reg CTRL_REG1.(ptr)
390 * @retval Interface status (MANDATORY: return 0 -> no Error).
391 *
392 */
lsm6dso16is_boot_get(stmdev_ctx_t * ctx,uint8_t * val)393 int32_t lsm6dso16is_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
394 {
395 lsm6dso16is_ctrl3_c_t ctrl3_c;
396 int32_t ret;
397
398 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
399 *val = ctrl3_c.boot;
400
401 return ret;
402 }
403
404 /**
405 * @brief Enable disable high-performance mode[set]
406 *
407 * @param ctx read / write interface definitions
408 * @param val HIGH_PERFOMANCE_MODE_ENABLED, HIGH_PERFOMANCE_MODE_DISABLED,
409 * @retval interface status (MANDATORY: return 0 -> no Error)
410 *
411 */
lsm6dso16is_xl_hm_mode_set(stmdev_ctx_t * ctx,lsm6dso16is_hm_mode_t val)412 int32_t lsm6dso16is_xl_hm_mode_set(stmdev_ctx_t *ctx, lsm6dso16is_hm_mode_t val)
413 {
414 lsm6dso16is_ctrl6_c_t ctrl6_c;
415 int32_t ret;
416
417 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
418
419 if (ret == 0)
420 {
421 ctrl6_c.xl_hm_mode = ((uint8_t)val & 0x1U);
422 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
423 }
424
425 return ret;
426 }
427
428 /**
429 * @brief Enable disable high-performance mode[get]
430 *
431 * @param ctx read / write interface definitions
432 * @param val HIGH_PERFOMANCE_MODE_ENABLED, HIGH_PERFOMANCE_MODE_DISABLED,
433 * @retval interface status (MANDATORY: return 0 -> no Error)
434 *
435 */
lsm6dso16is_xl_hm_mode_get(stmdev_ctx_t * ctx,lsm6dso16is_hm_mode_t * val)436 int32_t lsm6dso16is_xl_hm_mode_get(stmdev_ctx_t *ctx,
437 lsm6dso16is_hm_mode_t *val)
438 {
439 lsm6dso16is_ctrl6_c_t ctrl6_c;
440 int32_t ret;
441
442 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
443
444 switch ((ctrl6_c.xl_hm_mode))
445 {
446 case LSM6DSO16IS_HIGH_PERFOMANCE_MODE_ENABLED:
447 *val = LSM6DSO16IS_HIGH_PERFOMANCE_MODE_ENABLED;
448 break;
449
450 case LSM6DSO16IS_HIGH_PERFOMANCE_MODE_DISABLED:
451 *val = LSM6DSO16IS_HIGH_PERFOMANCE_MODE_DISABLED;
452 break;
453
454 default:
455 *val = LSM6DSO16IS_HIGH_PERFOMANCE_MODE_ENABLED;
456 break;
457 }
458 return ret;
459 }
460
461 /**
462 * @brief Accelerometer full-scale selection.[set]
463 *
464 * @param ctx read / write interface definitions
465 * @param val 2g, 4g, 8g, 16g,
466 * @retval interface status (MANDATORY: return 0 -> no Error)
467 *
468 */
lsm6dso16is_xl_full_scale_set(stmdev_ctx_t * ctx,lsm6dso16is_xl_full_scale_t val)469 int32_t lsm6dso16is_xl_full_scale_set(stmdev_ctx_t *ctx,
470 lsm6dso16is_xl_full_scale_t val)
471 {
472 lsm6dso16is_ctrl1_xl_t ctrl1_xl;
473 int32_t ret;
474
475 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
476
477 if (ret == 0)
478 {
479 ctrl1_xl.fs_xl = ((uint8_t)val & 0x3U);
480 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
481 }
482
483 return ret;
484 }
485
486 /**
487 * @brief Accelerometer full-scale selection.[get]
488 *
489 * @param ctx read / write interface definitions
490 * @param val 2g, 4g, 8g, 16g,
491 * @retval interface status (MANDATORY: return 0 -> no Error)
492 *
493 */
lsm6dso16is_xl_full_scale_get(stmdev_ctx_t * ctx,lsm6dso16is_xl_full_scale_t * val)494 int32_t lsm6dso16is_xl_full_scale_get(stmdev_ctx_t *ctx,
495 lsm6dso16is_xl_full_scale_t *val)
496 {
497 lsm6dso16is_ctrl1_xl_t ctrl1_xl;
498 int32_t ret;
499
500 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
501
502 switch ((ctrl1_xl.fs_xl))
503 {
504 case LSM6DSO16IS_2g:
505 *val = LSM6DSO16IS_2g;
506 break;
507
508 case LSM6DSO16IS_4g:
509 *val = LSM6DSO16IS_4g;
510 break;
511
512 case LSM6DSO16IS_8g:
513 *val = LSM6DSO16IS_8g;
514 break;
515
516 case LSM6DSO16IS_16g:
517 *val = LSM6DSO16IS_16g;
518 break;
519
520 default:
521 *val = LSM6DSO16IS_2g;
522 break;
523 }
524 return ret;
525 }
526
527 /**
528 * @brief Accelerometer output data rate (ODR) selection.[set]
529 *
530 * @param ctx read / write interface definitions
531 * @param val XL_ODR_OFF, XL_ODR_AT_1Hz875, XL_ODR_AT_7Hz5, XL_ODR_AT_15Hz, XL_ODR_AT_30Hz, XL_ODR_AT_60Hz, XL_ODR_AT_120Hz, XL_ODR_AT_240Hz, XL_ODR_AT_480Hz, XL_ODR_AT_960Hz, XL_ODR_AT_1920Hz, XL_ODR_AT_3840Hz, XL_ODR_AT_7680Hz,
532 * @retval interface status (MANDATORY: return 0 -> no Error)
533 *
534 */
lsm6dso16is_xl_data_rate_set(stmdev_ctx_t * ctx,lsm6dso16is_xl_data_rate_t val)535 int32_t lsm6dso16is_xl_data_rate_set(stmdev_ctx_t *ctx,
536 lsm6dso16is_xl_data_rate_t val)
537 {
538 lsm6dso16is_ctrl1_xl_t ctrl1_xl;
539 int32_t ret;
540
541 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
542
543 if (ret == 0)
544 {
545 if (((uint8_t)val & 0x10U) == 0x10U)
546 {
547 ret += lsm6dso16is_xl_hm_mode_set(ctx,
548 LSM6DSO16IS_HIGH_PERFOMANCE_MODE_DISABLED);
549 }
550 else
551 {
552 ret += lsm6dso16is_xl_hm_mode_set(ctx,
553 LSM6DSO16IS_HIGH_PERFOMANCE_MODE_ENABLED);
554 }
555
556 ctrl1_xl.odr_xl = ((uint8_t)val & 0xfU);
557 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL1_XL, (uint8_t *)&ctrl1_xl,
558 1);
559 }
560
561 return ret;
562 }
563
564 /**
565 * @brief Accelerometer output data rate (ODR) selection.[get]
566 *
567 * @param ctx read / write interface definitions
568 * @param val XL_ODR_OFF, XL_ODR_AT_1Hz875, XL_ODR_AT_7Hz5, XL_ODR_AT_15Hz, XL_ODR_AT_30Hz, XL_ODR_AT_60Hz, XL_ODR_AT_120Hz, XL_ODR_AT_240Hz, XL_ODR_AT_480Hz, XL_ODR_AT_960Hz, XL_ODR_AT_1920Hz, XL_ODR_AT_3840Hz, XL_ODR_AT_7680Hz,
569 * @retval interface status (MANDATORY: return 0 -> no Error)
570 *
571 */
lsm6dso16is_xl_data_rate_get(stmdev_ctx_t * ctx,lsm6dso16is_xl_data_rate_t * val)572 int32_t lsm6dso16is_xl_data_rate_get(stmdev_ctx_t *ctx,
573 lsm6dso16is_xl_data_rate_t *val)
574 {
575 lsm6dso16is_ctrl1_xl_t ctrl1_xl;
576 lsm6dso16is_ctrl6_c_t ctrl6_c;
577 int32_t ret;
578
579 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
580 if (ret == 0)
581 {
582 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
583 }
584
585 switch ((ctrl6_c.xl_hm_mode << 4) | (ctrl1_xl.odr_xl))
586 {
587 case LSM6DSO16IS_XL_ODR_OFF:
588 *val = LSM6DSO16IS_XL_ODR_OFF;
589 break;
590
591 case LSM6DSO16IS_XL_ODR_AT_12Hz5_HP:
592 *val = LSM6DSO16IS_XL_ODR_AT_12Hz5_HP;
593 break;
594
595 case LSM6DSO16IS_XL_ODR_AT_26H_HP:
596 *val = LSM6DSO16IS_XL_ODR_AT_26H_HP;
597 break;
598
599 case LSM6DSO16IS_XL_ODR_AT_52Hz_HP:
600 *val = LSM6DSO16IS_XL_ODR_AT_52Hz_HP;
601 break;
602
603 case LSM6DSO16IS_XL_ODR_AT_104Hz_HP:
604 *val = LSM6DSO16IS_XL_ODR_AT_104Hz_HP;
605 break;
606
607 case LSM6DSO16IS_XL_ODR_AT_208Hz_HP:
608 *val = LSM6DSO16IS_XL_ODR_AT_208Hz_HP;
609 break;
610
611 case LSM6DSO16IS_XL_ODR_AT_416Hz_HP:
612 *val = LSM6DSO16IS_XL_ODR_AT_416Hz_HP;
613 break;
614
615 case LSM6DSO16IS_XL_ODR_AT_833Hz_HP:
616 *val = LSM6DSO16IS_XL_ODR_AT_833Hz_HP;
617 break;
618
619 case LSM6DSO16IS_XL_ODR_AT_1667Hz_HP:
620 *val = LSM6DSO16IS_XL_ODR_AT_1667Hz_HP;
621 break;
622
623 case LSM6DSO16IS_XL_ODR_AT_3333Hz_HP:
624 *val = LSM6DSO16IS_XL_ODR_AT_3333Hz_HP;
625 break;
626
627 case LSM6DSO16IS_XL_ODR_AT_6667Hz_HP:
628 *val = LSM6DSO16IS_XL_ODR_AT_6667Hz_HP;
629 break;
630
631 case LSM6DSO16IS_XL_ODR_AT_12Hz5_LP:
632 *val = LSM6DSO16IS_XL_ODR_AT_12Hz5_LP;
633 break;
634
635 case LSM6DSO16IS_XL_ODR_AT_26H_LP:
636 *val = LSM6DSO16IS_XL_ODR_AT_26H_LP;
637 break;
638
639 case LSM6DSO16IS_XL_ODR_AT_52Hz_LP:
640 *val = LSM6DSO16IS_XL_ODR_AT_52Hz_LP;
641 break;
642
643 case LSM6DSO16IS_XL_ODR_AT_104Hz_LP:
644 *val = LSM6DSO16IS_XL_ODR_AT_104Hz_LP;
645 break;
646
647 case LSM6DSO16IS_XL_ODR_AT_208Hz_LP:
648 *val = LSM6DSO16IS_XL_ODR_AT_208Hz_LP;
649 break;
650
651 case LSM6DSO16IS_XL_ODR_AT_416Hz_LP:
652 *val = LSM6DSO16IS_XL_ODR_AT_416Hz_LP;
653 break;
654
655 case LSM6DSO16IS_XL_ODR_AT_833Hz_LP:
656 *val = LSM6DSO16IS_XL_ODR_AT_833Hz_LP;
657 break;
658
659 case LSM6DSO16IS_XL_ODR_AT_1667Hz_LP:
660 *val = LSM6DSO16IS_XL_ODR_AT_1667Hz_LP;
661 break;
662
663 case LSM6DSO16IS_XL_ODR_AT_3333Hz_LP:
664 *val = LSM6DSO16IS_XL_ODR_AT_3333Hz_LP;
665 break;
666
667 case LSM6DSO16IS_XL_ODR_AT_6667Hz_LP:
668 *val = LSM6DSO16IS_XL_ODR_AT_6667Hz_LP;
669 break;
670
671 case LSM6DSO16IS_XL_ODR_AT_1Hz6_LP:
672 *val = LSM6DSO16IS_XL_ODR_AT_1Hz6_LP;
673 break;
674
675 default:
676 *val = LSM6DSO16IS_XL_ODR_OFF;
677 break;
678 }
679 return ret;
680 }
681
682 /**
683 * @brief Enable disable high-performance mode[set]
684 *
685 * @param ctx read / write interface definitions
686 * @param val HIGH_PERFOMANCE_MODE_ENABLED, HIGH_PERFOMANCE_MODE_DISABLED,
687 * @retval interface status (MANDATORY: return 0 -> no Error)
688 *
689 */
lsm6dso16is_gy_hm_mode_set(stmdev_ctx_t * ctx,lsm6dso16is_hm_mode_t val)690 int32_t lsm6dso16is_gy_hm_mode_set(stmdev_ctx_t *ctx, lsm6dso16is_hm_mode_t val)
691 {
692 lsm6dso16is_ctrl7_g_t ctrl7_g;
693 int32_t ret;
694
695 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
696
697 if (ret == 0)
698 {
699 ctrl7_g.g_hm_mode = ((uint8_t)val & 0x1U);
700 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
701 }
702
703 return ret;
704 }
705
706 /**
707 * @brief Enable disable high-performance mode[get]
708 *
709 * @param ctx read / write interface definitions
710 * @param val HIGH_PERFOMANCE_MODE_ENABLED, HIGH_PERFOMANCE_MODE_DISABLED,
711 * @retval interface status (MANDATORY: return 0 -> no Error)
712 *
713 */
lsm6dso16is_gy_hm_mode_get(stmdev_ctx_t * ctx,lsm6dso16is_hm_mode_t * val)714 int32_t lsm6dso16is_gy_hm_mode_get(stmdev_ctx_t *ctx,
715 lsm6dso16is_hm_mode_t *val)
716 {
717 lsm6dso16is_ctrl7_g_t ctrl7_g;
718 int32_t ret;
719
720 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
721
722 switch ((ctrl7_g.g_hm_mode))
723 {
724 case LSM6DSO16IS_HIGH_PERFOMANCE_MODE_ENABLED:
725 *val = LSM6DSO16IS_HIGH_PERFOMANCE_MODE_ENABLED;
726 break;
727
728 case LSM6DSO16IS_HIGH_PERFOMANCE_MODE_DISABLED:
729 *val = LSM6DSO16IS_HIGH_PERFOMANCE_MODE_DISABLED;
730 break;
731
732 default:
733 *val = LSM6DSO16IS_HIGH_PERFOMANCE_MODE_ENABLED;
734 break;
735 }
736 return ret;
737 }
738
739 /**
740 * @brief Gyroscope full-scale selection[set]
741 *
742 * @param ctx read / write interface definitions
743 * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps,
744 * @retval interface status (MANDATORY: return 0 -> no Error)
745 *
746 */
lsm6dso16is_gy_full_scale_set(stmdev_ctx_t * ctx,lsm6dso16is_gy_full_scale_t val)747 int32_t lsm6dso16is_gy_full_scale_set(stmdev_ctx_t *ctx,
748 lsm6dso16is_gy_full_scale_t val)
749 {
750 lsm6dso16is_ctrl2_g_t ctrl2_g;
751 int32_t ret;
752
753 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
754
755 if (ret == 0)
756 {
757 ctrl2_g.fs_g = ((uint8_t)val & 0x3U);
758 ctrl2_g.fs_125 = ((uint8_t)val >> 4);
759 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
760 }
761
762 return ret;
763 }
764
765 /**
766 * @brief Gyroscope full-scale selection[get]
767 *
768 * @param ctx read / write interface definitions
769 * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps,
770 * @retval interface status (MANDATORY: return 0 -> no Error)
771 *
772 */
lsm6dso16is_gy_full_scale_get(stmdev_ctx_t * ctx,lsm6dso16is_gy_full_scale_t * val)773 int32_t lsm6dso16is_gy_full_scale_get(stmdev_ctx_t *ctx,
774 lsm6dso16is_gy_full_scale_t *val)
775 {
776 lsm6dso16is_ctrl2_g_t ctrl2_g;
777 int32_t ret;
778
779 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
780
781 switch ((ctrl2_g.fs_125 << 4) | (ctrl2_g.fs_g))
782 {
783 case LSM6DSO16IS_125dps:
784 *val = LSM6DSO16IS_125dps;
785 break;
786
787 case LSM6DSO16IS_250dps:
788 *val = LSM6DSO16IS_250dps;
789 break;
790
791 case LSM6DSO16IS_500dps:
792 *val = LSM6DSO16IS_500dps;
793 break;
794
795 case LSM6DSO16IS_1000dps:
796 *val = LSM6DSO16IS_1000dps;
797 break;
798
799 case LSM6DSO16IS_2000dps:
800 *val = LSM6DSO16IS_2000dps;
801 break;
802
803 default:
804 *val = LSM6DSO16IS_125dps;
805 break;
806 }
807 return ret;
808 }
809
810 /**
811 * @brief Gyroscope output data rate (ODR) selection.[set]
812 *
813 * @param ctx read / write interface definitions
814 * @param val GY_ODR_OFF, GY_ODR_AT_7Hz5, GY_ODR_AT_15Hz, GY_ODR_AT_30Hz, GY_ODR_AT_60Hz, GY_ODR_AT_120Hz, GY_ODR_AT_240Hz, GY_ODR_AT_480Hz, GY_ODR_AT_960Hz, GY_ODR_AT_1920Hz, GY_ODR_AT_3840Hz, GY_ODR_AT_7680Hz,
815 * @retval interface status (MANDATORY: return 0 -> no Error)
816 *
817 */
lsm6dso16is_gy_data_rate_set(stmdev_ctx_t * ctx,lsm6dso16is_gy_data_rate_t val)818 int32_t lsm6dso16is_gy_data_rate_set(stmdev_ctx_t *ctx,
819 lsm6dso16is_gy_data_rate_t val)
820 {
821 lsm6dso16is_ctrl2_g_t ctrl2_g;
822 int32_t ret;
823
824 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
825
826 if (ret == 0)
827 {
828 if (((uint8_t)val & 0x10U) == 0x10U)
829 {
830 ret += lsm6dso16is_gy_hm_mode_set(ctx,
831 LSM6DSO16IS_HIGH_PERFOMANCE_MODE_DISABLED);
832 }
833 else
834 {
835 ret += lsm6dso16is_gy_hm_mode_set(ctx,
836 LSM6DSO16IS_HIGH_PERFOMANCE_MODE_ENABLED);
837 }
838
839 ctrl2_g.odr_g = ((uint8_t)val & 0xfU);
840 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
841 }
842
843 return ret;
844 }
845
846 /**
847 * @brief Gyroscope output data rate (ODR) selection.[get]
848 *
849 * @param ctx read / write interface definitions
850 * @param val GY_ODR_OFF, GY_ODR_AT_7Hz5, GY_ODR_AT_15Hz, GY_ODR_AT_30Hz, GY_ODR_AT_60Hz, GY_ODR_AT_120Hz, GY_ODR_AT_240Hz, GY_ODR_AT_480Hz, GY_ODR_AT_960Hz, GY_ODR_AT_1920Hz, GY_ODR_AT_3840Hz, GY_ODR_AT_7680Hz,
851 * @retval interface status (MANDATORY: return 0 -> no Error)
852 *
853 */
lsm6dso16is_gy_data_rate_get(stmdev_ctx_t * ctx,lsm6dso16is_gy_data_rate_t * val)854 int32_t lsm6dso16is_gy_data_rate_get(stmdev_ctx_t *ctx,
855 lsm6dso16is_gy_data_rate_t *val)
856 {
857 lsm6dso16is_ctrl2_g_t ctrl2_g;
858 lsm6dso16is_ctrl7_g_t ctrl7_g;
859 int32_t ret;
860
861 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
862 if (ret == 0)
863 {
864 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
865 }
866
867 switch ((ctrl7_g.g_hm_mode << 4) | (ctrl2_g.odr_g))
868 {
869 case LSM6DSO16IS_GY_ODR_OFF:
870 *val = LSM6DSO16IS_GY_ODR_OFF;
871 break;
872
873 case LSM6DSO16IS_GY_ODR_AT_12Hz5_HP:
874 *val = LSM6DSO16IS_GY_ODR_AT_12Hz5_HP;
875 break;
876
877 case LSM6DSO16IS_GY_ODR_AT_26H_HP:
878 *val = LSM6DSO16IS_GY_ODR_AT_26H_HP;
879 break;
880
881 case LSM6DSO16IS_GY_ODR_AT_52Hz_HP:
882 *val = LSM6DSO16IS_GY_ODR_AT_52Hz_HP;
883 break;
884
885 case LSM6DSO16IS_GY_ODR_AT_104Hz_HP:
886 *val = LSM6DSO16IS_GY_ODR_AT_104Hz_HP;
887 break;
888
889 case LSM6DSO16IS_GY_ODR_AT_208Hz_HP:
890 *val = LSM6DSO16IS_GY_ODR_AT_208Hz_HP;
891 break;
892
893 case LSM6DSO16IS_GY_ODR_AT_416Hz_HP:
894 *val = LSM6DSO16IS_GY_ODR_AT_416Hz_HP;
895 break;
896
897 case LSM6DSO16IS_GY_ODR_AT_833Hz_HP:
898 *val = LSM6DSO16IS_GY_ODR_AT_833Hz_HP;
899 break;
900
901 case LSM6DSO16IS_GY_ODR_AT_1667Hz_HP:
902 *val = LSM6DSO16IS_GY_ODR_AT_1667Hz_HP;
903 break;
904
905 case LSM6DSO16IS_GY_ODR_AT_3333Hz_HP:
906 *val = LSM6DSO16IS_GY_ODR_AT_3333Hz_HP;
907 break;
908
909 case LSM6DSO16IS_GY_ODR_AT_6667Hz_HP:
910 *val = LSM6DSO16IS_GY_ODR_AT_6667Hz_HP;
911 break;
912
913 case LSM6DSO16IS_GY_ODR_AT_12Hz5_LP:
914 *val = LSM6DSO16IS_GY_ODR_AT_12Hz5_LP;
915 break;
916
917 case LSM6DSO16IS_GY_ODR_AT_26H_LP:
918 *val = LSM6DSO16IS_GY_ODR_AT_26H_LP;
919 break;
920
921 case LSM6DSO16IS_GY_ODR_AT_52Hz_LP:
922 *val = LSM6DSO16IS_GY_ODR_AT_52Hz_LP;
923 break;
924
925 case LSM6DSO16IS_GY_ODR_AT_104Hz_LP:
926 *val = LSM6DSO16IS_GY_ODR_AT_104Hz_LP;
927 break;
928
929 case LSM6DSO16IS_GY_ODR_AT_208Hz_LP:
930 *val = LSM6DSO16IS_GY_ODR_AT_208Hz_LP;
931 break;
932
933 case LSM6DSO16IS_GY_ODR_AT_416Hz_LP:
934 *val = LSM6DSO16IS_GY_ODR_AT_416Hz_LP;
935 break;
936
937 case LSM6DSO16IS_GY_ODR_AT_833Hz_LP:
938 *val = LSM6DSO16IS_GY_ODR_AT_833Hz_LP;
939 break;
940
941 case LSM6DSO16IS_GY_ODR_AT_1667Hz_LP:
942 *val = LSM6DSO16IS_GY_ODR_AT_1667Hz_LP;
943 break;
944
945 case LSM6DSO16IS_GY_ODR_AT_3333Hz_LP:
946 *val = LSM6DSO16IS_GY_ODR_AT_3333Hz_LP;
947 break;
948
949 case LSM6DSO16IS_GY_ODR_AT_6667Hz_LP:
950 *val = LSM6DSO16IS_GY_ODR_AT_6667Hz_LP;
951 break;
952
953 default:
954 *val = LSM6DSO16IS_GY_ODR_OFF;
955 break;
956 }
957
958 return ret;
959 }
960
961 /**
962 * @brief Register address automatically incremented during a multiple byte access with a serial interface (enable by default).[set]
963 *
964 * @param ctx read / write interface definitions
965 * @param val Register address automatically incremented during a multiple byte access with a serial interface (enable by default).
966 * @retval interface status (MANDATORY: return 0 -> no Error)
967 *
968 */
lsm6dso16is_auto_increment_set(stmdev_ctx_t * ctx,uint8_t val)969 int32_t lsm6dso16is_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
970 {
971 lsm6dso16is_ctrl3_c_t ctrl3_c;
972 int32_t ret;
973
974 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
975
976 if (ret == 0)
977 {
978 ctrl3_c.if_inc = val;
979 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
980 }
981
982 return ret;
983 }
984
985 /**
986 * @brief Register address automatically incremented during a multiple byte access with a serial interface (enable by default).[get]
987 *
988 * @param ctx read / write interface definitions
989 * @param val Register address automatically incremented during a multiple byte access with a serial interface (enable by default).
990 * @retval interface status (MANDATORY: return 0 -> no Error)
991 *
992 */
lsm6dso16is_auto_increment_get(stmdev_ctx_t * ctx,uint8_t * val)993 int32_t lsm6dso16is_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
994 {
995 lsm6dso16is_ctrl3_c_t ctrl3_c;
996 int32_t ret;
997
998 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
999
1000 *val = ctrl3_c.if_inc;
1001
1002 return ret;
1003 }
1004
1005 /**
1006 * @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [set]
1007 *
1008 * @param ctx read / write interface definitions
1009 * @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read).
1010 * @retval interface status (MANDATORY: return 0 -> no Error)
1011 *
1012 */
lsm6dso16is_block_data_update_set(stmdev_ctx_t * ctx,uint8_t val)1013 int32_t lsm6dso16is_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
1014 {
1015 lsm6dso16is_ctrl3_c_t ctrl3_c;
1016 int32_t ret;
1017
1018 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1019
1020 if (ret == 0)
1021 {
1022 ctrl3_c.bdu = val;
1023 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1024 }
1025
1026 return ret;
1027 }
1028
1029 /**
1030 * @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [get]
1031 *
1032 * @param ctx read / write interface definitions
1033 * @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read).
1034 * @retval interface status (MANDATORY: return 0 -> no Error)
1035 *
1036 */
lsm6dso16is_block_data_update_get(stmdev_ctx_t * ctx,uint8_t * val)1037 int32_t lsm6dso16is_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
1038 {
1039 lsm6dso16is_ctrl3_c_t ctrl3_c;
1040 int32_t ret;
1041
1042 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1043
1044 *val = ctrl3_c.bdu;
1045
1046 return ret;
1047 }
1048
1049 /**
1050 * @brief Enables gyroscope sleep mode[set]
1051 *
1052 * @param ctx read / write interface definitions
1053 * @param val SLEEP_G_ENABLE, SLEEP_G_DISABLE,
1054 * @retval interface status (MANDATORY: return 0 -> no Error)
1055 *
1056 */
lsm6dso16is_sleep_set(stmdev_ctx_t * ctx,lsm6dso16is_sleep_t val)1057 int32_t lsm6dso16is_sleep_set(stmdev_ctx_t *ctx, lsm6dso16is_sleep_t val)
1058 {
1059 lsm6dso16is_ctrl4_c_t ctrl4_c;
1060 int32_t ret;
1061
1062 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
1063
1064 if (ret == 0)
1065 {
1066 ctrl4_c.sleep_g = ((uint8_t)val & 0x1U);
1067 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
1068 }
1069
1070 return ret;
1071 }
1072
1073 /**
1074 * @brief Enables gyroscope sleep mode[get]
1075 *
1076 * @param ctx read / write interface definitions
1077 * @param val SLEEP_G_ENABLE, SLEEP_G_DISABLE,
1078 * @retval interface status (MANDATORY: return 0 -> no Error)
1079 *
1080 */
lsm6dso16is_sleep_get(stmdev_ctx_t * ctx,lsm6dso16is_sleep_t * val)1081 int32_t lsm6dso16is_sleep_get(stmdev_ctx_t *ctx, lsm6dso16is_sleep_t *val)
1082 {
1083 lsm6dso16is_ctrl4_c_t ctrl4_c;
1084 int32_t ret;
1085
1086 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
1087
1088 switch ((ctrl4_c.sleep_g))
1089 {
1090 case LSM6DSO16IS_SLEEP_G_ENABLE:
1091 *val = LSM6DSO16IS_SLEEP_G_ENABLE;
1092 break;
1093
1094 case LSM6DSO16IS_SLEEP_G_DISABLE:
1095 *val = LSM6DSO16IS_SLEEP_G_DISABLE;
1096 break;
1097
1098 default:
1099 *val = LSM6DSO16IS_SLEEP_G_ENABLE;
1100 break;
1101 }
1102 return ret;
1103 }
1104
1105 /**
1106 * @brief Accelerometer self-test selection.[set]
1107 *
1108 * @param ctx read / write interface definitions
1109 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1110 * @retval interface status (MANDATORY: return 0 -> no Error)
1111 *
1112 */
lsm6dso16is_xl_self_test_set(stmdev_ctx_t * ctx,lsm6dso16is_xl_self_test_t val)1113 int32_t lsm6dso16is_xl_self_test_set(stmdev_ctx_t *ctx,
1114 lsm6dso16is_xl_self_test_t val)
1115 {
1116 lsm6dso16is_ctrl5_c_t ctrl5_c;
1117 int32_t ret;
1118
1119 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1120
1121 if (ret == 0)
1122 {
1123 ctrl5_c.st_xl = ((uint8_t)val & 0x3U);
1124 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1125 }
1126
1127 return ret;
1128 }
1129
1130 /**
1131 * @brief Accelerometer self-test selection.[get]
1132 *
1133 * @param ctx read / write interface definitions
1134 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1135 * @retval interface status (MANDATORY: return 0 -> no Error)
1136 *
1137 */
lsm6dso16is_xl_self_test_get(stmdev_ctx_t * ctx,lsm6dso16is_xl_self_test_t * val)1138 int32_t lsm6dso16is_xl_self_test_get(stmdev_ctx_t *ctx,
1139 lsm6dso16is_xl_self_test_t *val)
1140 {
1141 lsm6dso16is_ctrl5_c_t ctrl5_c;
1142 int32_t ret;
1143
1144 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1145
1146 switch ((ctrl5_c.st_xl))
1147 {
1148 case LSM6DSO16IS_XL_ST_DISABLE:
1149 *val = LSM6DSO16IS_XL_ST_DISABLE;
1150 break;
1151
1152 case LSM6DSO16IS_XL_ST_POSITIVE:
1153 *val = LSM6DSO16IS_XL_ST_POSITIVE;
1154 break;
1155
1156 case LSM6DSO16IS_XL_ST_NEGATIVE:
1157 *val = LSM6DSO16IS_XL_ST_NEGATIVE;
1158 break;
1159
1160 default:
1161 *val = LSM6DSO16IS_XL_ST_DISABLE;
1162 break;
1163 }
1164 return ret;
1165 }
1166
1167 /**
1168 * @brief Gyroscope self-test selection.[set]
1169 *
1170 * @param ctx read / write interface definitions
1171 * @param val GY_ST_DISABLE, GY_ST_POSITIVE, GY_ST_NEGATIVE,
1172 * @retval interface status (MANDATORY: return 0 -> no Error)
1173 *
1174 */
lsm6dso16is_gy_self_test_set(stmdev_ctx_t * ctx,lsm6dso16is_gy_self_test_t val)1175 int32_t lsm6dso16is_gy_self_test_set(stmdev_ctx_t *ctx,
1176 lsm6dso16is_gy_self_test_t val)
1177 {
1178 lsm6dso16is_ctrl5_c_t ctrl5_c;
1179 int32_t ret;
1180
1181 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1182
1183 if (ret == 0)
1184 {
1185 ctrl5_c.st_g = ((uint8_t)val & 0x3U);
1186 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1187 }
1188
1189 return ret;
1190 }
1191
1192 /**
1193 * @brief Gyroscope self-test selection.[get]
1194 *
1195 * @param ctx read / write interface definitions
1196 * @param val GY_ST_DISABLE, GY_ST_POSITIVE, GY_ST_NEGATIVE,
1197 * @retval interface status (MANDATORY: return 0 -> no Error)
1198 *
1199 */
lsm6dso16is_gy_self_test_get(stmdev_ctx_t * ctx,lsm6dso16is_gy_self_test_t * val)1200 int32_t lsm6dso16is_gy_self_test_get(stmdev_ctx_t *ctx,
1201 lsm6dso16is_gy_self_test_t *val)
1202 {
1203 lsm6dso16is_ctrl5_c_t ctrl5_c;
1204 int32_t ret;
1205
1206 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1207
1208 switch ((ctrl5_c.st_g))
1209 {
1210 case LSM6DSO16IS_GY_ST_DISABLE:
1211 *val = LSM6DSO16IS_GY_ST_DISABLE;
1212 break;
1213
1214 case LSM6DSO16IS_GY_ST_POSITIVE:
1215 *val = LSM6DSO16IS_GY_ST_POSITIVE;
1216 break;
1217
1218 case LSM6DSO16IS_GY_ST_NEGATIVE:
1219 *val = LSM6DSO16IS_GY_ST_NEGATIVE;
1220 break;
1221
1222 default:
1223 *val = LSM6DSO16IS_GY_ST_DISABLE;
1224 break;
1225 }
1226 return ret;
1227 }
1228
1229 /**
1230 * @defgroup Serial Interfaces
1231 * @brief Serial Interfaces
1232 * @{/
1233 *
1234 */
1235 /**
1236 * @brief Enables pull-up on SDO pin of UI (User Interface).[set]
1237 *
1238 * @param ctx read / write interface definitions
1239 * @param val Enables pull-up on SDO pin of UI (User Interface).
1240 * @retval interface status (MANDATORY: return 0 -> no Error)
1241 *
1242 */
lsm6dso16is_ui_sdo_pull_up_set(stmdev_ctx_t * ctx,uint8_t val)1243 int32_t lsm6dso16is_ui_sdo_pull_up_set(stmdev_ctx_t *ctx, uint8_t val)
1244 {
1245 lsm6dso16is_pin_ctrl_t pin_ctrl;
1246 int32_t ret;
1247
1248 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
1249
1250 if (ret == 0)
1251 {
1252 pin_ctrl.sdo_pu_en = val;
1253 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
1254 }
1255
1256 return ret;
1257 }
1258
1259 /**
1260 * @brief Enables pull-up on SDO pin of UI (User Interface).[get]
1261 *
1262 * @param ctx read / write interface definitions
1263 * @param val Enables pull-up on SDO pin of UI (User Interface).
1264 * @retval interface status (MANDATORY: return 0 -> no Error)
1265 *
1266 */
lsm6dso16is_ui_sdo_pull_up_get(stmdev_ctx_t * ctx,uint8_t * val)1267 int32_t lsm6dso16is_ui_sdo_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val)
1268 {
1269 lsm6dso16is_pin_ctrl_t pin_ctrl;
1270 int32_t ret;
1271
1272 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
1273
1274 *val = pin_ctrl.sdo_pu_en;
1275
1276 return ret;
1277 }
1278
1279 /**
1280 * @brief SPI Serial Interface Mode selection.[set]
1281 *
1282 * @param ctx read / write interface definitions
1283 * @param val SPI_4_WIRE, SPI_3_WIRE,
1284 * @retval interface status (MANDATORY: return 0 -> no Error)
1285 *
1286 */
lsm6dso16is_spi_mode_set(stmdev_ctx_t * ctx,lsm6dso16is_spi_mode_t val)1287 int32_t lsm6dso16is_spi_mode_set(stmdev_ctx_t *ctx, lsm6dso16is_spi_mode_t val)
1288 {
1289 lsm6dso16is_ctrl3_c_t ctrl3_c;
1290 int32_t ret;
1291
1292 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1293
1294 if (ret == 0)
1295 {
1296 ctrl3_c.sim = ((uint8_t)val & 0x1U);
1297 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1298 }
1299
1300 return ret;
1301 }
1302
1303 /**
1304 * @brief SPI Serial Interface Mode selection.[get]
1305 *
1306 * @param ctx read / write interface definitions
1307 * @param val SPI_4_WIRE, SPI_3_WIRE,
1308 * @retval interface status (MANDATORY: return 0 -> no Error)
1309 *
1310 */
lsm6dso16is_spi_mode_get(stmdev_ctx_t * ctx,lsm6dso16is_spi_mode_t * val)1311 int32_t lsm6dso16is_spi_mode_get(stmdev_ctx_t *ctx, lsm6dso16is_spi_mode_t *val)
1312 {
1313 lsm6dso16is_ctrl3_c_t ctrl3_c;
1314 int32_t ret;
1315
1316 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1317
1318 switch ((ctrl3_c.sim))
1319 {
1320 case LSM6DSO16IS_SPI_4_WIRE:
1321 *val = LSM6DSO16IS_SPI_4_WIRE;
1322 break;
1323
1324 case LSM6DSO16IS_SPI_3_WIRE:
1325 *val = LSM6DSO16IS_SPI_3_WIRE;
1326 break;
1327
1328 default:
1329 *val = LSM6DSO16IS_SPI_4_WIRE;
1330 break;
1331 }
1332 return ret;
1333 }
1334
1335 /**
1336 * @brief Disables I2C on UI (User Interface).[set]
1337 *
1338 * @param ctx read / write interface definitions
1339 * @param val I2C_ENABLE, I2C_DISABLE,
1340 * @retval interface status (MANDATORY: return 0 -> no Error)
1341 *
1342 */
lsm6dso16is_ui_i2c_mode_set(stmdev_ctx_t * ctx,lsm6dso16is_ui_i2c_mode_t val)1343 int32_t lsm6dso16is_ui_i2c_mode_set(stmdev_ctx_t *ctx,
1344 lsm6dso16is_ui_i2c_mode_t val)
1345 {
1346 lsm6dso16is_ctrl4_c_t ctrl4_c;
1347 int32_t ret;
1348
1349 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
1350
1351 if (ret == 0)
1352 {
1353 ctrl4_c.i2c_disable = ((uint8_t)val & 0x1U);
1354 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
1355 }
1356
1357 return ret;
1358 }
1359
1360 /**
1361 * @brief Disables I2C on UI (User Interface).[get]
1362 *
1363 * @param ctx read / write interface definitions
1364 * @param val I2C_ENABLE, I2C_DISABLE,
1365 * @retval interface status (MANDATORY: return 0 -> no Error)
1366 *
1367 */
lsm6dso16is_ui_i2c_mode_get(stmdev_ctx_t * ctx,lsm6dso16is_ui_i2c_mode_t * val)1368 int32_t lsm6dso16is_ui_i2c_mode_get(stmdev_ctx_t *ctx,
1369 lsm6dso16is_ui_i2c_mode_t *val)
1370 {
1371 lsm6dso16is_ctrl4_c_t ctrl4_c;
1372 int32_t ret;
1373
1374 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
1375
1376 switch ((ctrl4_c.i2c_disable))
1377 {
1378 case LSM6DSO16IS_I2C_ENABLE:
1379 *val = LSM6DSO16IS_I2C_ENABLE;
1380 break;
1381
1382 case LSM6DSO16IS_I2C_DISABLE:
1383 *val = LSM6DSO16IS_I2C_DISABLE;
1384 break;
1385
1386 default:
1387 *val = LSM6DSO16IS_I2C_ENABLE;
1388 break;
1389 }
1390 return ret;
1391 }
1392
1393 /**
1394 * @}
1395 *
1396 */
1397
1398 /**
1399 * @defgroup Timestamp
1400 * @brief Timestamp
1401 * @{/
1402 *
1403 */
1404 /**
1405 * @brief Enables timestamp counter.[set]
1406 *
1407 * @param ctx read / write interface definitions
1408 * @param val Enables timestamp counter.
1409 * @retval interface status (MANDATORY: return 0 -> no Error)
1410 *
1411 */
lsm6dso16is_timestamp_set(stmdev_ctx_t * ctx,uint8_t val)1412 int32_t lsm6dso16is_timestamp_set(stmdev_ctx_t *ctx, uint8_t val)
1413 {
1414 lsm6dso16is_ctrl10_c_t ctrl10_c;
1415 int32_t ret;
1416
1417 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
1418
1419 if (ret == 0)
1420 {
1421 ctrl10_c.timestamp_en = val;
1422 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
1423 }
1424
1425 return ret;
1426 }
1427
1428 /**
1429 * @brief Enables timestamp counter.[get]
1430 *
1431 * @param ctx read / write interface definitions
1432 * @param val Enables timestamp counter.
1433 * @retval interface status (MANDATORY: return 0 -> no Error)
1434 *
1435 */
lsm6dso16is_timestamp_get(stmdev_ctx_t * ctx,uint8_t * val)1436 int32_t lsm6dso16is_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val)
1437 {
1438 lsm6dso16is_ctrl10_c_t ctrl10_c;
1439 int32_t ret;
1440
1441 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
1442
1443 *val = ctrl10_c.timestamp_en;
1444
1445 return ret;
1446 }
1447
1448 /**
1449 * @brief Timestamp data output.[get]
1450 *
1451 * @param ctx read / write interface definitions
1452 * @param val Timestamp data output.
1453 * @retval interface status (MANDATORY: return 0 -> no Error)
1454 *
1455 */
lsm6dso16is_timestamp_raw_get(stmdev_ctx_t * ctx,uint32_t * val)1456 int32_t lsm6dso16is_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val)
1457 {
1458 uint8_t buff[4];
1459 int32_t ret;
1460
1461 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_TIMESTAMP0, &buff[0], 4);
1462
1463 *val = (uint32_t)buff[3];
1464 *val = (*val * 256U) + (uint32_t)buff[2];
1465 *val = (*val * 256U) + (uint32_t)buff[1];
1466 *val = (*val * 256U) + (uint32_t)buff[0];
1467
1468 return ret;
1469 }
1470
1471 /**
1472 * @}
1473 *
1474 */
1475
1476 /**
1477 * @brief Get the status of all the interrupt sources.[get]
1478 *
1479 * @param ctx read / write interface definitions
1480 * @param val Get the status of all the interrupt sources.
1481 * @retval interface status (MANDATORY: return 0 -> no Error)
1482 *
1483 */
lsm6dso16is_all_sources_get(stmdev_ctx_t * ctx,lsm6dso16is_all_sources_t * val)1484 int32_t lsm6dso16is_all_sources_get(stmdev_ctx_t *ctx,
1485 lsm6dso16is_all_sources_t *val)
1486 {
1487 lsm6dso16is_status_reg_t status_reg;
1488 lsm6dso16is_status_master_mainpage_t status_sh;
1489 uint32_t status_ispu;
1490 int32_t ret;
1491
1492 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_STATUS_REG, (uint8_t *)&status_reg, 1);
1493 if (ret == 0)
1494 {
1495 val->drdy_xl = status_reg.xlda;
1496 val->drdy_gy = status_reg.gda;
1497 val->drdy_temp = status_reg.tda;
1498 }
1499
1500 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_STATUS_MASTER_MAINPAGE, (uint8_t *)&status_sh, 1);
1501 if (ret == 0)
1502 {
1503 val->sh_endop = status_sh.sens_hub_endop;
1504 val->sh_slave0_nack = status_sh.sens_hub_endop;
1505 val->sh_slave1_nack = status_sh.sens_hub_endop;
1506 val->sh_slave2_nack = status_sh.sens_hub_endop;
1507 val->sh_slave3_nack = status_sh.sens_hub_endop;
1508 val->sh_wr_once = status_sh.sens_hub_endop;
1509 }
1510
1511 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_INT_STATUS0_MAINPAGE, (uint8_t *)&status_ispu, 4);
1512 if (ret == 0)
1513 {
1514 val->ispu = status_ispu;
1515 }
1516
1517 return ret;
1518 }
1519
1520 /**
1521 * @brief The STATUS_REG register is read by the primary interface.[get]
1522 *
1523 * @param ctx Read / write interface definitions.(ptr)
1524 * @param val Get register STATUS_REG
1525 * @retval Interface status (MANDATORY: return 0 -> no Error).
1526 *
1527 */
lsm6dso16is_status_reg_get(stmdev_ctx_t * ctx,lsm6dso16is_status_reg_t * val)1528 int32_t lsm6dso16is_status_reg_get(stmdev_ctx_t *ctx,
1529 lsm6dso16is_status_reg_t *val)
1530 {
1531 int32_t ret;
1532 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_STATUS_REG, (uint8_t *) val, 1);
1533
1534 return ret;
1535 }
1536
1537 /**
1538 * @brief Accelerometer new data available.[get]
1539 *
1540 * @param ctx Read / write interface definitions.(ptr)
1541 * @param val Change the values of xlda in reg STATUS_REG
1542 * @retval Interface status (MANDATORY: return 0 -> no Error).
1543 *
1544 */
lsm6dso16is_xl_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)1545 int32_t lsm6dso16is_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
1546 uint8_t *val)
1547 {
1548 lsm6dso16is_status_reg_t status_reg;
1549 int32_t ret;
1550 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_STATUS_REG,
1551 (uint8_t *)&status_reg, 1);
1552 *val = status_reg.xlda;
1553
1554 return ret;
1555 }
1556
1557 /**
1558 * @brief Gyroscope new data available.[get]
1559 *
1560 * @param ctx Read / write interface definitions.(ptr)
1561 * @param val Change the values of gda in reg STATUS_REG
1562 * @retval Interface status (MANDATORY: return 0 -> no Error).
1563 *
1564 */
lsm6dso16is_gy_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)1565 int32_t lsm6dso16is_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
1566 uint8_t *val)
1567 {
1568 lsm6dso16is_status_reg_t status_reg;
1569 int32_t ret;
1570 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_STATUS_REG,
1571 (uint8_t *)&status_reg, 1);
1572 *val = status_reg.gda;
1573
1574 return ret;
1575 }
1576
1577 /**
1578 * @brief Temperature new data available.[get]
1579 *
1580 * @param ctx Read / write interface definitions.(ptr)
1581 * @param val Change the values of tda in reg STATUS_REG
1582 * @retval Interface status (MANDATORY: return 0 -> no Error).
1583 *
1584 */
lsm6dso16is_temp_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)1585 int32_t lsm6dso16is_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
1586 uint8_t *val)
1587 {
1588 lsm6dso16is_status_reg_t status_reg;
1589 int32_t ret;
1590 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_STATUS_REG,
1591 (uint8_t *)&status_reg, 1);
1592 *val = status_reg.tda;
1593
1594 return ret;
1595 }
1596
1597 /**
1598 * @brief Temperature data output register[get]
1599 *
1600 * @param ctx read / write interface definitions
1601 * @param val Temperature data output register
1602 * @retval interface status (MANDATORY: return 0 -> no Error)
1603 *
1604 */
lsm6dso16is_temperature_raw_get(stmdev_ctx_t * ctx,int16_t * val)1605 int32_t lsm6dso16is_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
1606 {
1607 uint8_t buff[2];
1608 int32_t ret;
1609
1610 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_OUT_TEMP_L, &buff[0], 2);
1611 *val = (int16_t)buff[1];
1612 *val = (*val * 256) + (int16_t)buff[0];
1613
1614 return ret;
1615 }
1616
1617 /**
1618 * @brief Angular rate sensor.[get]
1619 *
1620 * @param ctx read / write interface definitions
1621 * @param val Angular rate sensor.
1622 * @retval interface status (MANDATORY: return 0 -> no Error)
1623 *
1624 */
lsm6dso16is_angular_rate_raw_get(stmdev_ctx_t * ctx,int16_t * val)1625 int32_t lsm6dso16is_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val)
1626 {
1627 uint8_t buff[6];
1628 int32_t ret;
1629
1630 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_OUTX_L_G, buff, 6);
1631 val[0] = (int16_t)buff[1];
1632 val[0] = (val[0] * 256) + (int16_t)buff[0];
1633 val[1] = (int16_t)buff[3];
1634 val[1] = (val[1] * 256) + (int16_t)buff[2];
1635 val[2] = (int16_t)buff[5];
1636 val[2] = (val[2] * 256) + (int16_t)buff[4];
1637
1638 return ret;
1639 }
1640
1641 /**
1642 * @brief Linear acceleration sensor.[get]
1643 *
1644 * @param ctx read / write interface definitions
1645 * @param val Linear acceleration sensor.
1646 * @retval interface status (MANDATORY: return 0 -> no Error)
1647 *
1648 */
lsm6dso16is_acceleration_raw_get(stmdev_ctx_t * ctx,int16_t * val)1649 int32_t lsm6dso16is_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
1650 {
1651 uint8_t buff[6];
1652 int32_t ret;
1653
1654 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_OUTX_L_A, buff, 6);
1655 val[0] = (int16_t)buff[1];
1656 val[0] = (val[0] * 256) + (int16_t)buff[0];
1657 val[1] = (int16_t)buff[3];
1658 val[1] = (val[1] * 256) + (int16_t)buff[2];
1659 val[2] = (int16_t)buff[5];
1660 val[2] = (val[2] * 256) + (int16_t)buff[4];
1661
1662 return ret;
1663 }
1664
1665 /**
1666 * @}
1667 *
1668 */
1669
1670 /**
1671 * @defgroup Interrupt PINs
1672 * @brief Interrupt PINs
1673 * @{/
1674 *
1675 */
1676 /**
1677 * @brief It routes interrupt signals on INT 1 pin.[set]
1678 *
1679 * @param ctx read / write interface definitions
1680 * @param val It routes interrupt signals on INT 1 pin.
1681 * @retval interface status (MANDATORY: return 0 -> no Error)
1682 *
1683 */
lsm6dso16is_pin_int1_route_set(stmdev_ctx_t * ctx,lsm6dso16is_pin_int1_route_t val)1684 int32_t lsm6dso16is_pin_int1_route_set(stmdev_ctx_t *ctx,
1685 lsm6dso16is_pin_int1_route_t val)
1686 {
1687 lsm6dso16is_int1_ctrl_t int1_ctrl;
1688 lsm6dso16is_md1_cfg_t md1_cfg;
1689 int32_t ret;
1690
1691 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
1692 if (ret == 0)
1693 {
1694 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MD1_CFG, (uint8_t *)&md1_cfg, 1);
1695 }
1696
1697 if (ret == 0)
1698 {
1699 int1_ctrl.int1_drdy_xl = val.drdy_xl;
1700 int1_ctrl.int1_drdy_g = val.drdy_gy;
1701 int1_ctrl.int1_boot = val.boot;
1702 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_INT1_CTRL, (uint8_t *)&int1_ctrl,
1703 1);
1704
1705 md1_cfg.int1_shub = val.sh_endop;
1706 md1_cfg.int1_ispu = val.ispu;
1707 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_MD1_CFG, (uint8_t *)&md1_cfg, 1);
1708 }
1709
1710 return ret;
1711 }
1712
1713 /**
1714 * @brief It routes interrupt signals on INT 1 pin.[get]
1715 *
1716 * @param ctx read / write interface definitions
1717 * @param val It routes interrupt signals on INT 1 pin.
1718 * @retval interface status (MANDATORY: return 0 -> no Error)
1719 *
1720 */
lsm6dso16is_pin_int1_route_get(stmdev_ctx_t * ctx,lsm6dso16is_pin_int1_route_t * val)1721 int32_t lsm6dso16is_pin_int1_route_get(stmdev_ctx_t *ctx,
1722 lsm6dso16is_pin_int1_route_t *val)
1723 {
1724 lsm6dso16is_int1_ctrl_t int1_ctrl;
1725 lsm6dso16is_md1_cfg_t md1_cfg;
1726 int32_t ret;
1727
1728 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
1729 if (ret == 0)
1730 {
1731 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MD1_CFG, (uint8_t *)&md1_cfg, 1);
1732 }
1733
1734 if (ret == 0)
1735 {
1736 val->drdy_xl = int1_ctrl.int1_drdy_xl;
1737 val->drdy_gy = int1_ctrl.int1_drdy_g;
1738 val->boot = int1_ctrl.int1_boot;
1739 val->sh_endop = md1_cfg.int1_shub;
1740 val->ispu = md1_cfg.int1_ispu;
1741 }
1742
1743 return ret;
1744 }
1745
1746 /**
1747 * @brief It routes interrupt signals on INT 2 pin.[set]
1748 *
1749 * @param ctx read / write interface definitions
1750 * @param val It routes interrupt signals on INT 2 pin.
1751 * @retval interface status (MANDATORY: return 0 -> no Error)
1752 *
1753 */
lsm6dso16is_pin_int2_route_set(stmdev_ctx_t * ctx,lsm6dso16is_pin_int2_route_t val)1754 int32_t lsm6dso16is_pin_int2_route_set(stmdev_ctx_t *ctx,
1755 lsm6dso16is_pin_int2_route_t val)
1756 {
1757 lsm6dso16is_int2_ctrl_t int2_ctrl;
1758 lsm6dso16is_md2_cfg_t md2_cfg;
1759 int32_t ret;
1760
1761 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
1762 if (ret == 0)
1763 {
1764 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MD2_CFG, (uint8_t *)&md2_cfg, 1);
1765 }
1766
1767 if (ret == 0)
1768 {
1769 int2_ctrl.int2_drdy_xl = val.drdy_xl;
1770 int2_ctrl.int2_drdy_g = val.drdy_gy;
1771 int2_ctrl.int2_drdy_temp = val.drdy_temp;
1772 int2_ctrl.int2_sleep_ispu = val.ispu_sleep;
1773 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_INT2_CTRL, (uint8_t *)&int2_ctrl,
1774 1);
1775
1776 md2_cfg.int2_ispu = val.ispu;
1777 md2_cfg.int2_timestamp = val.timestamp;
1778 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_MD2_CFG, (uint8_t *)&md2_cfg, 1);
1779 }
1780
1781 return ret;
1782 }
1783
1784 /**
1785 * @brief It routes interrupt signals on INT 2 pin.[get]
1786 *
1787 * @param ctx read / write interface definitions
1788 * @param val It routes interrupt signals on INT 2 pin.
1789 * @retval interface status (MANDATORY: return 0 -> no Error)
1790 *
1791 */
lsm6dso16is_pin_int2_route_get(stmdev_ctx_t * ctx,lsm6dso16is_pin_int2_route_t * val)1792 int32_t lsm6dso16is_pin_int2_route_get(stmdev_ctx_t *ctx,
1793 lsm6dso16is_pin_int2_route_t *val)
1794 {
1795 lsm6dso16is_int2_ctrl_t int2_ctrl;
1796 lsm6dso16is_md2_cfg_t md2_cfg;
1797 int32_t ret;
1798
1799 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
1800 if (ret == 0)
1801 {
1802 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MD2_CFG, (uint8_t *)&md2_cfg, 1);
1803 }
1804
1805 if (ret == 0)
1806 {
1807 val->drdy_xl = int2_ctrl.int2_drdy_xl;
1808 val->drdy_gy = int2_ctrl.int2_drdy_g;
1809 val->drdy_temp = int2_ctrl.int2_drdy_temp;
1810 val->ispu_sleep = int2_ctrl.int2_sleep_ispu;
1811 val->ispu = md2_cfg.int2_ispu;
1812 val->timestamp = md2_cfg.int2_timestamp;
1813 }
1814
1815 return ret;
1816 }
1817
1818 /**
1819 * @brief Push-pull/open-drain selection on INT1 and INT2 pins.[set]
1820 *
1821 * @param ctx read / write interface definitions
1822 * @param val PUSH_PULL, OPEN_DRAIN,
1823 * @retval interface status (MANDATORY: return 0 -> no Error)
1824 *
1825 */
lsm6dso16is_int_pin_mode_set(stmdev_ctx_t * ctx,lsm6dso16is_int_pin_mode_t val)1826 int32_t lsm6dso16is_int_pin_mode_set(stmdev_ctx_t *ctx,
1827 lsm6dso16is_int_pin_mode_t val)
1828 {
1829 lsm6dso16is_ctrl3_c_t ctrl3_c;
1830 int32_t ret;
1831
1832 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1833
1834 if (ret == 0)
1835 {
1836 ctrl3_c.pp_od = ((uint8_t)val & 0x1U);
1837 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1838 }
1839
1840 return ret;
1841 }
1842
1843 /**
1844 * @brief Push-pull/open-drain selection on INT1 and INT2 pins.[get]
1845 *
1846 * @param ctx read / write interface definitions
1847 * @param val PUSH_PULL, OPEN_DRAIN,
1848 * @retval interface status (MANDATORY: return 0 -> no Error)
1849 *
1850 */
lsm6dso16is_int_pin_mode_get(stmdev_ctx_t * ctx,lsm6dso16is_int_pin_mode_t * val)1851 int32_t lsm6dso16is_int_pin_mode_get(stmdev_ctx_t *ctx,
1852 lsm6dso16is_int_pin_mode_t *val)
1853 {
1854 lsm6dso16is_ctrl3_c_t ctrl3_c;
1855 int32_t ret;
1856
1857 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1858
1859 switch ((ctrl3_c.pp_od))
1860 {
1861 case LSM6DSO16IS_PUSH_PULL:
1862 *val = LSM6DSO16IS_PUSH_PULL;
1863 break;
1864
1865 case LSM6DSO16IS_OPEN_DRAIN:
1866 *val = LSM6DSO16IS_OPEN_DRAIN;
1867 break;
1868
1869 default:
1870 *val = LSM6DSO16IS_PUSH_PULL;
1871 break;
1872 }
1873 return ret;
1874 }
1875
1876 /**
1877 * @brief Interrupt activation level.[set]
1878 *
1879 * @param ctx read / write interface definitions
1880 * @param val ACTIVE_HIGH, ACTIVE_LOW,
1881 * @retval interface status (MANDATORY: return 0 -> no Error)
1882 *
1883 */
lsm6dso16is_pin_polarity_set(stmdev_ctx_t * ctx,lsm6dso16is_pin_polarity_t val)1884 int32_t lsm6dso16is_pin_polarity_set(stmdev_ctx_t *ctx,
1885 lsm6dso16is_pin_polarity_t val)
1886 {
1887 lsm6dso16is_ctrl3_c_t ctrl3_c;
1888 int32_t ret;
1889
1890 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1891
1892 if (ret == 0)
1893 {
1894 ctrl3_c.h_lactive = ((uint8_t)val & 0x1U);
1895 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1896 }
1897
1898 return ret;
1899 }
1900
1901 /**
1902 * @brief Interrupt activation level.[get]
1903 *
1904 * @param ctx read / write interface definitions
1905 * @param val ACTIVE_HIGH, ACTIVE_LOW,
1906 * @retval interface status (MANDATORY: return 0 -> no Error)
1907 *
1908 */
lsm6dso16is_pin_polarity_get(stmdev_ctx_t * ctx,lsm6dso16is_pin_polarity_t * val)1909 int32_t lsm6dso16is_pin_polarity_get(stmdev_ctx_t *ctx,
1910 lsm6dso16is_pin_polarity_t *val)
1911 {
1912 lsm6dso16is_ctrl3_c_t ctrl3_c;
1913 int32_t ret;
1914
1915 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1916
1917 switch ((ctrl3_c.h_lactive))
1918 {
1919 case LSM6DSO16IS_ACTIVE_HIGH:
1920 *val = LSM6DSO16IS_ACTIVE_HIGH;
1921 break;
1922
1923 case LSM6DSO16IS_ACTIVE_LOW:
1924 *val = LSM6DSO16IS_ACTIVE_LOW;
1925 break;
1926
1927 default:
1928 *val = LSM6DSO16IS_ACTIVE_HIGH;
1929 break;
1930 }
1931 return ret;
1932 }
1933
1934 /**
1935 * @}
1936 *
1937 */
1938
1939 /**
1940 * @defgroup Sensor hub
1941 * @brief This section groups all the functions that manage the
1942 * sensor hub.
1943 * @{
1944 *
1945 */
1946
1947 /**
1948 * @brief Sensor hub output registers.[get]
1949 *
1950 * @param ctx read / write interface definitions
1951 * @param val Sensor hub output registers.
1952 * @retval interface status (MANDATORY: return 0 -> no Error)
1953 *
1954 */
lsm6dso16is_sh_read_data_raw_get(stmdev_ctx_t * ctx,lsm6dso16is_emb_sh_read_t * val,uint8_t len)1955 int32_t lsm6dso16is_sh_read_data_raw_get(stmdev_ctx_t *ctx,
1956 lsm6dso16is_emb_sh_read_t *val,
1957 uint8_t len)
1958 {
1959 int32_t ret;
1960
1961 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK);
1962 if (ret == 0)
1963 {
1964 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_SENSOR_HUB_1, (uint8_t *) val,
1965 len);
1966 }
1967 if (ret == 0)
1968 {
1969 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
1970 }
1971
1972
1973 return ret;
1974 }
1975
1976 /**
1977 * @brief Number of external sensors to be read by the sensor hub.[set]
1978 *
1979 * @param ctx read / write interface definitions
1980 * @param val SLV_0, SLV_0_1, SLV_0_1_2, SLV_0_1_2_3,
1981 * @retval interface status (MANDATORY: return 0 -> no Error)
1982 *
1983 */
lsm6dso16is_sh_slave_connected_set(stmdev_ctx_t * ctx,lsm6dso16is_sh_slave_connected_t val)1984 int32_t lsm6dso16is_sh_slave_connected_set(stmdev_ctx_t *ctx,
1985 lsm6dso16is_sh_slave_connected_t val)
1986 {
1987 lsm6dso16is_master_config_t master_config;
1988 int32_t ret;
1989
1990 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK);
1991 if (ret == 0)
1992 {
1993 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
1994 }
1995
1996 if (ret == 0)
1997 {
1998 master_config.aux_sens_on = (uint8_t)val & 0x3U;
1999 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2000 }
2001 if (ret == 0)
2002 {
2003 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
2004 }
2005
2006 return ret;
2007 }
2008
2009 /**
2010 * @brief Number of external sensors to be read by the sensor hub.[get]
2011 *
2012 * @param ctx read / write interface definitions
2013 * @param val SLV_0, SLV_0_1, SLV_0_1_2, SLV_0_1_2_3,
2014 * @retval interface status (MANDATORY: return 0 -> no Error)
2015 *
2016 */
lsm6dso16is_sh_slave_connected_get(stmdev_ctx_t * ctx,lsm6dso16is_sh_slave_connected_t * val)2017 int32_t lsm6dso16is_sh_slave_connected_get(stmdev_ctx_t *ctx,
2018 lsm6dso16is_sh_slave_connected_t *val)
2019 {
2020 lsm6dso16is_master_config_t master_config;
2021 int32_t ret;
2022
2023 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK);
2024 if (ret == 0)
2025 {
2026 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2027 }
2028 if (ret == 0)
2029 {
2030 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
2031 }
2032
2033 switch (master_config.aux_sens_on)
2034 {
2035 case LSM6DSO16IS_SLV_0:
2036 *val = LSM6DSO16IS_SLV_0;
2037 break;
2038
2039 case LSM6DSO16IS_SLV_0_1:
2040 *val = LSM6DSO16IS_SLV_0_1;
2041 break;
2042
2043 case LSM6DSO16IS_SLV_0_1_2:
2044 *val = LSM6DSO16IS_SLV_0_1_2;
2045 break;
2046
2047 case LSM6DSO16IS_SLV_0_1_2_3:
2048 *val = LSM6DSO16IS_SLV_0_1_2_3;
2049 break;
2050
2051 default:
2052 *val = LSM6DSO16IS_SLV_0;
2053 break;
2054 }
2055 return ret;
2056 }
2057
2058 /**
2059 * @brief Sensor hub I2C master enable.[set]
2060 *
2061 * @param ctx read / write interface definitions
2062 * @param val Sensor hub I2C master enable.
2063 * @retval interface status (MANDATORY: return 0 -> no Error)
2064 *
2065 */
lsm6dso16is_sh_master_set(stmdev_ctx_t * ctx,uint8_t val)2066 int32_t lsm6dso16is_sh_master_set(stmdev_ctx_t *ctx, uint8_t val)
2067 {
2068 lsm6dso16is_master_config_t master_config;
2069 int32_t ret;
2070
2071 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK);
2072 if (ret == 0)
2073 {
2074 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2075 }
2076
2077 if (ret == 0)
2078 {
2079 master_config.master_on = val;
2080 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2081 }
2082 if (ret == 0)
2083 {
2084 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
2085 }
2086
2087 return ret;
2088 }
2089
2090 /**
2091 * @brief Sensor hub I2C master enable.[get]
2092 *
2093 * @param ctx read / write interface definitions
2094 * @param val Sensor hub I2C master enable.
2095 * @retval interface status (MANDATORY: return 0 -> no Error)
2096 *
2097 */
lsm6dso16is_sh_master_get(stmdev_ctx_t * ctx,uint8_t * val)2098 int32_t lsm6dso16is_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val)
2099 {
2100 lsm6dso16is_master_config_t master_config;
2101 int32_t ret;
2102
2103 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK);
2104 if (ret == 0)
2105 {
2106 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2107 }
2108
2109 *val = master_config.master_on;
2110
2111 if (ret == 0)
2112 {
2113 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
2114 }
2115
2116 return ret;
2117 }
2118
2119 /**
2120 * @brief Sensor Hub master I2C pull-up enable.[set]
2121 *
2122 * @param ctx read / write interface definitions
2123 * @param val Sensor Hub master I2C pull-up enable.
2124 * @retval interface status (MANDATORY: return 0 -> no Error)
2125 *
2126 */
lsm6dso16is_sh_master_interface_pull_up_set(stmdev_ctx_t * ctx,uint8_t val)2127 int32_t lsm6dso16is_sh_master_interface_pull_up_set(stmdev_ctx_t *ctx,
2128 uint8_t val)
2129 {
2130 lsm6dso16is_master_config_t master_config;
2131 int32_t ret;
2132
2133 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK);
2134 if (ret == 0)
2135 {
2136 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2137 }
2138
2139 if (ret == 0)
2140 {
2141 master_config.shub_pu_en = val;
2142 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2143 }
2144
2145 if (ret == 0)
2146 {
2147 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
2148 }
2149
2150 return ret;
2151 }
2152
2153 /**
2154 * @brief Sensor Hub master I2C pull-up enable.[get]
2155 *
2156 * @param ctx read / write interface definitions
2157 * @param val Sensor Hub master I2C pull-up enable.
2158 * @retval interface status (MANDATORY: return 0 -> no Error)
2159 *
2160 */
lsm6dso16is_sh_master_interface_pull_up_get(stmdev_ctx_t * ctx,uint8_t * val)2161 int32_t lsm6dso16is_sh_master_interface_pull_up_get(stmdev_ctx_t *ctx,
2162 uint8_t *val)
2163 {
2164 lsm6dso16is_master_config_t master_config;
2165 int32_t ret;
2166
2167 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK);
2168 if (ret == 0)
2169 {
2170 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2171 }
2172
2173 *val = master_config.shub_pu_en;
2174
2175 if (ret == 0)
2176 {
2177 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
2178 }
2179
2180 return ret;
2181 }
2182
2183 /**
2184 * @brief I2C interface pass-through.[set]
2185 *
2186 * @param ctx Read / write interface definitions.(ptr)
2187 * @param val Change the values of pass_through_mode in reg MASTER_CONFIG
2188 * @retval Interface status (MANDATORY: return 0 -> no Error).
2189 *
2190 */
lsm6dso16is_sh_pass_through_set(stmdev_ctx_t * ctx,uint8_t val)2191 int32_t lsm6dso16is_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val)
2192 {
2193 lsm6dso16is_master_config_t master_config;
2194 int32_t ret;
2195
2196 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK);
2197
2198 if (ret == 0)
2199 {
2200 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG,
2201 (uint8_t *)&master_config, 1);
2202 }
2203
2204 if (ret == 0)
2205 {
2206 master_config.pass_through_mode = (uint8_t)val;
2207 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_MASTER_CONFIG,
2208 (uint8_t *)&master_config, 1);
2209 }
2210
2211 if (ret == 0)
2212 {
2213 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
2214 }
2215
2216 return ret;
2217 }
2218
2219 /**
2220 * @brief I2C interface pass-through.[get]
2221 *
2222 * @param ctx Read / write interface definitions.(ptr)
2223 * @param val Change the values of pass_through_mode in reg MASTER_CONFIG
2224 * @retval Interface status (MANDATORY: return 0 -> no Error).
2225 *
2226 */
lsm6dso16is_sh_pass_through_get(stmdev_ctx_t * ctx,uint8_t * val)2227 int32_t lsm6dso16is_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val)
2228 {
2229 lsm6dso16is_master_config_t master_config;
2230 int32_t ret;
2231
2232 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK);
2233
2234 if (ret == 0)
2235 {
2236 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG,
2237 (uint8_t *)&master_config, 1);
2238 }
2239
2240 if (ret == 0)
2241 {
2242 *val = master_config.pass_through_mode;
2243 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
2244 }
2245
2246 return ret;
2247 }
2248
2249 /**
2250 * @brief Sensor hub trigger signal selection.[set]
2251 *
2252 * @param ctx read / write interface definitions
2253 * @param val SH_TRG_XL_GY_DRDY, SH_TRIG_INT2,
2254 * @retval interface status (MANDATORY: return 0 -> no Error)
2255 *
2256 */
lsm6dso16is_sh_syncro_mode_set(stmdev_ctx_t * ctx,lsm6dso16is_sh_syncro_mode_t val)2257 int32_t lsm6dso16is_sh_syncro_mode_set(stmdev_ctx_t *ctx,
2258 lsm6dso16is_sh_syncro_mode_t val)
2259 {
2260 lsm6dso16is_master_config_t master_config;
2261 int32_t ret;
2262
2263 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK);
2264 if (ret == 0)
2265 {
2266 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2267 }
2268
2269 if (ret == 0)
2270 {
2271 master_config.start_config = (uint8_t)val & 0x01U;
2272 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2273 }
2274 if (ret == 0)
2275 {
2276 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
2277 }
2278
2279 return ret;
2280 }
2281
2282 /**
2283 * @brief Sensor hub trigger signal selection.[get]
2284 *
2285 * @param ctx read / write interface definitions
2286 * @param val SH_TRG_XL_GY_DRDY, SH_TRIG_INT2,
2287 * @retval interface status (MANDATORY: return 0 -> no Error)
2288 *
2289 */
lsm6dso16is_sh_syncro_mode_get(stmdev_ctx_t * ctx,lsm6dso16is_sh_syncro_mode_t * val)2290 int32_t lsm6dso16is_sh_syncro_mode_get(stmdev_ctx_t *ctx,
2291 lsm6dso16is_sh_syncro_mode_t *val)
2292 {
2293 lsm6dso16is_master_config_t master_config;
2294 int32_t ret;
2295
2296 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK);
2297 if (ret == 0)
2298 {
2299 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2300 }
2301 if (ret == 0)
2302 {
2303 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
2304 }
2305
2306 switch (master_config.start_config)
2307 {
2308 case LSM6DSO16IS_SH_TRG_XL_GY_DRDY:
2309 *val = LSM6DSO16IS_SH_TRG_XL_GY_DRDY;
2310 break;
2311
2312 case LSM6DSO16IS_SH_TRIG_INT2:
2313 *val = LSM6DSO16IS_SH_TRIG_INT2;
2314 break;
2315
2316 default:
2317 *val = LSM6DSO16IS_SH_TRG_XL_GY_DRDY;
2318 break;
2319 }
2320 return ret;
2321 }
2322
2323 /**
2324 * @brief Slave 0 write operation is performed only at the first sensor hub cycle.[set]
2325 *
2326 * @param ctx read / write interface definitions
2327 * @param val EACH_SH_CYCLE, ONLY_FIRST_CYCLE,
2328 * @retval interface status (MANDATORY: return 0 -> no Error)
2329 *
2330 */
lsm6dso16is_sh_write_mode_set(stmdev_ctx_t * ctx,lsm6dso16is_sh_write_mode_t val)2331 int32_t lsm6dso16is_sh_write_mode_set(stmdev_ctx_t *ctx,
2332 lsm6dso16is_sh_write_mode_t val)
2333 {
2334 lsm6dso16is_master_config_t master_config;
2335 int32_t ret;
2336
2337 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK);
2338 if (ret == 0)
2339 {
2340 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2341 }
2342
2343 if (ret == 0)
2344 {
2345 master_config.write_once = (uint8_t)val & 0x01U;
2346 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2347 }
2348 if (ret == 0)
2349 {
2350 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
2351 }
2352
2353 return ret;
2354 }
2355
2356 /**
2357 * @brief Slave 0 write operation is performed only at the first sensor hub cycle.[get]
2358 *
2359 * @param ctx read / write interface definitions
2360 * @param val EACH_SH_CYCLE, ONLY_FIRST_CYCLE,
2361 * @retval interface status (MANDATORY: return 0 -> no Error)
2362 *
2363 */
lsm6dso16is_sh_write_mode_get(stmdev_ctx_t * ctx,lsm6dso16is_sh_write_mode_t * val)2364 int32_t lsm6dso16is_sh_write_mode_get(stmdev_ctx_t *ctx,
2365 lsm6dso16is_sh_write_mode_t *val)
2366 {
2367 lsm6dso16is_master_config_t master_config;
2368 int32_t ret;
2369
2370 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK);
2371 if (ret == 0)
2372 {
2373 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2374 }
2375 if (ret == 0)
2376 {
2377 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
2378 }
2379
2380
2381 switch (master_config.write_once)
2382 {
2383 case LSM6DSO16IS_EACH_SH_CYCLE:
2384 *val = LSM6DSO16IS_EACH_SH_CYCLE;
2385 break;
2386
2387 case LSM6DSO16IS_ONLY_FIRST_CYCLE:
2388 *val = LSM6DSO16IS_ONLY_FIRST_CYCLE;
2389 break;
2390
2391 default:
2392 *val = LSM6DSO16IS_EACH_SH_CYCLE;
2393 break;
2394 }
2395 return ret;
2396 }
2397
2398 /**
2399 * @brief Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’.[set]
2400 *
2401 * @param ctx read / write interface definitions
2402 * @param val Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’.
2403 * @retval interface status (MANDATORY: return 0 -> no Error)
2404 *
2405 */
lsm6dso16is_sh_reset_set(stmdev_ctx_t * ctx,uint8_t val)2406 int32_t lsm6dso16is_sh_reset_set(stmdev_ctx_t *ctx, uint8_t val)
2407 {
2408 lsm6dso16is_master_config_t master_config;
2409 int32_t ret;
2410
2411 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK);
2412 if (ret == 0)
2413 {
2414 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2415 }
2416
2417 if (ret == 0)
2418 {
2419 master_config.rst_master_regs = val;
2420 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2421 }
2422 if (ret == 0)
2423 {
2424 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
2425 }
2426
2427 return ret;
2428 }
2429
2430 /**
2431 * @brief Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’.[get]
2432 *
2433 * @param ctx read / write interface definitions
2434 * @param val Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’.
2435 * @retval interface status (MANDATORY: return 0 -> no Error)
2436 *
2437 */
lsm6dso16is_sh_reset_get(stmdev_ctx_t * ctx,uint8_t * val)2438 int32_t lsm6dso16is_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
2439 {
2440 lsm6dso16is_master_config_t master_config;
2441 int32_t ret;
2442
2443 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK);
2444 if (ret == 0)
2445 {
2446 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2447 }
2448
2449 *val = master_config.rst_master_regs;
2450
2451 if (ret == 0)
2452 {
2453 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
2454 }
2455
2456 return ret;
2457 }
2458
2459 /**
2460 * @brief Configure slave 0 for perform a write.[set]
2461 *
2462 * @param ctx read / write interface definitions
2463 * @param val a structure that contain
2464 * - uint8_t slv1_add; 8 bit i2c device address
2465 * - uint8_t slv1_subadd; 8 bit register device address
2466 * - uint8_t slv1_data; 8 bit data to write
2467 * @retval interface status (MANDATORY: return 0 -> no Error)
2468 *
2469 */
lsm6dso16is_sh_cfg_write(stmdev_ctx_t * ctx,lsm6dso16is_sh_cfg_write_t * val)2470 int32_t lsm6dso16is_sh_cfg_write(stmdev_ctx_t *ctx,
2471 lsm6dso16is_sh_cfg_write_t *val)
2472 {
2473 lsm6dso16is_slv0_add_t reg;
2474 int32_t ret;
2475
2476 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK);
2477 if (ret == 0)
2478 {
2479 reg.slave0_add = val->slv0_add;
2480 reg.rw_0 = 0;
2481 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLV0_ADD, (uint8_t *)®, 1);
2482 }
2483
2484 if (ret == 0)
2485 {
2486 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLV0_SUBADD,
2487 &(val->slv0_subadd), 1);
2488 }
2489
2490 if (ret == 0)
2491 {
2492 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_DATAWRITE_SLV0,
2493 &(val->slv0_data), 1);
2494 }
2495
2496 if (ret == 0)
2497 {
2498 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
2499 }
2500
2501 return ret;
2502 }
2503
2504 /**
2505 * @brief Rate at which the master communicates.[set]
2506 *
2507 * @param ctx read / write interface definitions
2508 * @param val SH_12_5Hz, SH_26Hz, SH_52Hz, SH_104Hz
2509 * @retval interface status (MANDATORY: return 0 -> no Error)
2510 *
2511 */
lsm6dso16is_sh_data_rate_set(stmdev_ctx_t * ctx,lsm6dso16is_sh_data_rate_t val)2512 int32_t lsm6dso16is_sh_data_rate_set(stmdev_ctx_t *ctx,
2513 lsm6dso16is_sh_data_rate_t val)
2514 {
2515 lsm6dso16is_slv0_config_t slv0_config;
2516 int32_t ret;
2517
2518 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK);
2519 if (ret == 0)
2520 {
2521 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_SLAVE0_CONFIG, (uint8_t *)&slv0_config, 1);
2522 }
2523
2524 if (ret == 0)
2525 {
2526 slv0_config.shub_odr = (uint8_t)val & 0x07U;
2527 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLAVE0_CONFIG, (uint8_t *)&slv0_config, 1);
2528 }
2529 if (ret == 0)
2530 {
2531 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
2532 }
2533
2534 return ret;
2535 }
2536
2537 /**
2538 * @brief Rate at which the master communicates.[get]
2539 *
2540 * @param ctx read / write interface definitions
2541 * @param val SH_12_5Hz, SH_26Hz, SH_52Hz, SH_104Hz
2542 * @retval interface status (MANDATORY: return 0 -> no Error)
2543 *
2544 */
lsm6dso16is_sh_data_rate_get(stmdev_ctx_t * ctx,lsm6dso16is_sh_data_rate_t * val)2545 int32_t lsm6dso16is_sh_data_rate_get(stmdev_ctx_t *ctx,
2546 lsm6dso16is_sh_data_rate_t *val)
2547 {
2548 lsm6dso16is_slv0_config_t slv0_config;
2549 int32_t ret;
2550
2551 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK);
2552 if (ret == 0)
2553 {
2554 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_SLAVE0_CONFIG, (uint8_t *)&slv0_config, 1);
2555 }
2556 if (ret == 0)
2557 {
2558 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
2559 }
2560
2561 switch (slv0_config.shub_odr)
2562 {
2563 case LSM6DSO16IS_SH_12_5Hz:
2564 *val = LSM6DSO16IS_SH_12_5Hz;
2565 break;
2566
2567 case LSM6DSO16IS_SH_26Hz:
2568 *val = LSM6DSO16IS_SH_26Hz;
2569 break;
2570
2571 case LSM6DSO16IS_SH_52Hz:
2572 *val = LSM6DSO16IS_SH_52Hz;
2573 break;
2574
2575 case LSM6DSO16IS_SH_104Hz:
2576 *val = LSM6DSO16IS_SH_104Hz;
2577 break;
2578
2579 default:
2580 *val = LSM6DSO16IS_SH_12_5Hz;
2581 break;
2582 }
2583 return ret;
2584 }
2585
2586 /**
2587 * @brief Configure slave 0 for perform a read.[set]
2588 *
2589 * @param ctx read / write interface definitions
2590 * @param val Structure that contain
2591 * - uint8_t slv1_add; 8 bit i2c device address
2592 * - uint8_t slv1_subadd; 8 bit register device address
2593 * - uint8_t slv1_len; num of bit to read
2594 * @retval interface status (MANDATORY: return 0 -> no Error)
2595 *
2596 */
lsm6dso16is_sh_slv0_cfg_read(stmdev_ctx_t * ctx,lsm6dso16is_sh_cfg_read_t * val)2597 int32_t lsm6dso16is_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
2598 lsm6dso16is_sh_cfg_read_t *val)
2599 {
2600 lsm6dso16is_slv0_add_t slv0_add;
2601 lsm6dso16is_slv0_config_t slv0_config;
2602 int32_t ret;
2603
2604 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK);
2605
2606 if (ret == 0)
2607 {
2608 slv0_add.slave0_add = val->slv_add;
2609 slv0_add.rw_0 = 1;
2610 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLV0_ADD, (uint8_t *)&slv0_add, 1);
2611 }
2612
2613 if (ret == 0)
2614 {
2615 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLV0_SUBADD,
2616 &(val->slv_subadd), 1);
2617 }
2618
2619 if (ret == 0)
2620 {
2621 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_SLAVE0_CONFIG,
2622 (uint8_t *)&slv0_config, 1);
2623 }
2624
2625 if (ret == 0)
2626 {
2627 slv0_config.slave0_numop = val->slv_len;
2628 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLAVE0_CONFIG,
2629 (uint8_t *)&slv0_config, 1);
2630 }
2631
2632 if (ret == 0)
2633 {
2634 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
2635 }
2636
2637 return ret;
2638 }
2639
2640 /**
2641 * @brief Configure slave 0 for perform a write/read.[set]
2642 *
2643 * @param ctx read / write interface definitions
2644 * @param val Structure that contain
2645 * - uint8_t slv1_add; 8 bit i2c device address
2646 * - uint8_t slv1_subadd; 8 bit register device address
2647 * - uint8_t slv1_len; num of bit to read
2648 * @retval interface status (MANDATORY: return 0 -> no Error)
2649 *
2650 */
lsm6dso16is_sh_slv1_cfg_read(stmdev_ctx_t * ctx,lsm6dso16is_sh_cfg_read_t * val)2651 int32_t lsm6dso16is_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
2652 lsm6dso16is_sh_cfg_read_t *val)
2653 {
2654 lsm6dso16is_slv1_add_t slv1_add;
2655 lsm6dso16is_slv1_config_t slv1_config;
2656 int32_t ret;
2657
2658 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK);
2659
2660 if (ret == 0)
2661 {
2662 slv1_add.slave1_add = val->slv_add;
2663 slv1_add.r_1 = 1;
2664 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLV1_ADD, (uint8_t *)&slv1_add, 1);
2665 }
2666
2667 if (ret == 0)
2668 {
2669 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLV1_SUBADD,
2670 &(val->slv_subadd), 1);
2671 }
2672
2673 if (ret == 0)
2674 {
2675 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_SLAVE1_CONFIG,
2676 (uint8_t *)&slv1_config, 1);
2677 }
2678
2679 if (ret == 0)
2680 {
2681 slv1_config.slave1_numop = val->slv_len;
2682 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLAVE1_CONFIG,
2683 (uint8_t *)&slv1_config, 1);
2684 }
2685
2686 if (ret == 0)
2687 {
2688 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
2689 }
2690
2691 return ret;
2692 }
2693
2694 /**
2695 * @brief Configure slave 0 for perform a write/read.[set]
2696 *
2697 * @param ctx read / write interface definitions
2698 * @param val Structure that contain
2699 * - uint8_t slv2_add; 8 bit i2c device address
2700 * - uint8_t slv2_subadd; 8 bit register device address
2701 * - uint8_t slv2_len; num of bit to read
2702 * @retval interface status (MANDATORY: return 0 -> no Error)
2703 *
2704 */
lsm6dso16is_sh_slv2_cfg_read(stmdev_ctx_t * ctx,lsm6dso16is_sh_cfg_read_t * val)2705 int32_t lsm6dso16is_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
2706 lsm6dso16is_sh_cfg_read_t *val)
2707 {
2708 lsm6dso16is_slv2_add_t slv2_add;
2709 lsm6dso16is_slv2_config_t slv2_config;
2710 int32_t ret;
2711
2712 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK);
2713
2714 if (ret == 0)
2715 {
2716 slv2_add.slave2_add = val->slv_add;
2717 slv2_add.r_2 = 1;
2718 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLV2_ADD, (uint8_t *)&slv2_add, 1);
2719 }
2720
2721 if (ret == 0)
2722 {
2723 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLV2_SUBADD,
2724 &(val->slv_subadd), 1);
2725 }
2726
2727 if (ret == 0)
2728 {
2729 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_SLAVE2_CONFIG,
2730 (uint8_t *)&slv2_config, 1);
2731 }
2732
2733 if (ret == 0)
2734 {
2735 slv2_config.slave2_numop = val->slv_len;
2736 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLAVE2_CONFIG,
2737 (uint8_t *)&slv2_config, 1);
2738 }
2739
2740 if (ret == 0)
2741 {
2742 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
2743 }
2744
2745 return ret;
2746 }
2747
2748 /**
2749 * @brief Configure slave 0 for perform a write/read.[set]
2750 *
2751 * @param ctx read / write interface definitions
2752 * @param val Structure that contain
2753 * - uint8_t slv3_add; 8 bit i2c device address
2754 * - uint8_t slv3_subadd; 8 bit register device address
2755 * - uint8_t slv3_len; num of bit to read
2756 * @retval interface status (MANDATORY: return 0 -> no Error)
2757 *
2758 */
lsm6dso16is_sh_slv3_cfg_read(stmdev_ctx_t * ctx,lsm6dso16is_sh_cfg_read_t * val)2759 int32_t lsm6dso16is_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
2760 lsm6dso16is_sh_cfg_read_t *val)
2761 {
2762 lsm6dso16is_slv3_add_t slv3_add;
2763 lsm6dso16is_slv3_config_t slv3_config;
2764 int32_t ret;
2765
2766 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK);
2767
2768 if (ret == 0)
2769 {
2770 slv3_add.slave3_add = val->slv_add;
2771 slv3_add.r_3 = 1;
2772 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLV3_ADD, (uint8_t *)&slv3_add, 1);
2773 }
2774
2775 if (ret == 0)
2776 {
2777 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLV3_SUBADD,
2778 &(val->slv_subadd), 1);
2779 }
2780
2781 if (ret == 0)
2782 {
2783 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_SLAVE3_CONFIG,
2784 (uint8_t *)&slv3_config, 1);
2785 }
2786
2787 if (ret == 0)
2788 {
2789 slv3_config.slave3_numop = val->slv_len;
2790 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLAVE3_CONFIG,
2791 (uint8_t *)&slv3_config, 1);
2792 }
2793
2794 if (ret == 0)
2795 {
2796 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
2797 }
2798
2799 return ret;
2800 }
2801
2802 /**
2803 * @}
2804 *
2805 */
2806
2807 /**
2808 * @defgroup ispu
2809 * @brief ispu
2810 * @{/
2811 *
2812 */
2813 /**
2814 * @brief Software reset of ISPU core.[set]
2815 *
2816 * @param ctx read / write interface definitions
2817 * @param val Software reset of ISPU core.
2818 * @retval interface status (MANDATORY: return 0 -> no Error)
2819 *
2820 */
lsm6dso16is_ispu_reset_set(stmdev_ctx_t * ctx,uint8_t val)2821 int32_t lsm6dso16is_ispu_reset_set(stmdev_ctx_t *ctx, uint8_t val)
2822 {
2823 lsm6dso16is_func_cfg_access_t func_cfg_access;
2824 int32_t ret;
2825
2826 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
2827
2828 if (ret == 0)
2829 {
2830 func_cfg_access.sw_reset_ispu = val;
2831 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
2832 }
2833
2834 return ret;
2835 }
2836
2837 /**
2838 * @brief Software reset of ISPU core.[get]
2839 *
2840 * @param ctx read / write interface definitions
2841 * @param val Software reset of ISPU core.
2842 * @retval interface status (MANDATORY: return 0 -> no Error)
2843 *
2844 */
lsm6dso16is_ispu_reset_get(stmdev_ctx_t * ctx,uint8_t * val)2845 int32_t lsm6dso16is_ispu_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
2846 {
2847 lsm6dso16is_func_cfg_access_t func_cfg_access;
2848 int32_t ret;
2849
2850 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
2851
2852 *val = func_cfg_access.sw_reset_ispu;
2853
2854
2855 return ret;
2856 }
2857
lsm6dso16is_ispu_clock_set(stmdev_ctx_t * ctx,lsm6dso16is_ispu_clock_sel_t val)2858 int32_t lsm6dso16is_ispu_clock_set(stmdev_ctx_t *ctx,
2859 lsm6dso16is_ispu_clock_sel_t val)
2860 {
2861 lsm6dso16is_ctrl10_c_t ctrl10_c;
2862 int32_t ret;
2863
2864 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
2865
2866 if (ret == 0)
2867 {
2868 ctrl10_c.ispu_clk_sel = (uint8_t)val;
2869 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL10_C, (uint8_t *)&ctrl10_c,
2870 1);
2871 }
2872
2873 return ret;
2874 }
2875
lsm6dso16is_ispu_clock_get(stmdev_ctx_t * ctx,lsm6dso16is_ispu_clock_sel_t * val)2876 int32_t lsm6dso16is_ispu_clock_get(stmdev_ctx_t *ctx,
2877 lsm6dso16is_ispu_clock_sel_t *val)
2878 {
2879 lsm6dso16is_ctrl10_c_t ctrl10_c;
2880 int32_t ret;
2881
2882 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
2883
2884 switch (ctrl10_c.ispu_clk_sel)
2885 {
2886 default:
2887 case 0:
2888 *val = LSM6DSO16IS_ISPU_CLK_5MHz;
2889 break;
2890 case 1:
2891 *val = LSM6DSO16IS_ISPU_CLK_10MHz;
2892 break;
2893 }
2894
2895 return ret;
2896 }
2897
2898 /**
2899 * @brief ISPU irq rate selection.[set]
2900 *
2901 * @param ctx read / write interface definitions
2902 * @param val ISPU_ODR_OFF, ISPU_ODR_AT_12Hz5, ISPU_ODR_AT_26Hz, ISPU_ODR_AT_52Hz,
2903 * ISPU_ODR_AT_104Hz, ISPU_ODR_AT_208Hz, ISPU_ODR_AT_417Hz, ISPU_ODR_AT_833Hz,
2904 * ISPU_ODR_AT_1667Hz, ISPU_ODR_AT_3333Hz, ISPU_ODR_AT_6667Hz
2905 * @retval interface status (MANDATORY: return 0 -> no Error)
2906 *
2907 */
lsm6dso16is_ispu_data_rate_set(stmdev_ctx_t * ctx,lsm6dso16is_ispu_data_rate_t val)2908 int32_t lsm6dso16is_ispu_data_rate_set(stmdev_ctx_t *ctx,
2909 lsm6dso16is_ispu_data_rate_t val)
2910 {
2911 lsm6dso16is_ctrl9_c_t ctrl9_c;
2912 int32_t ret;
2913
2914 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL9_C, (uint8_t *)&ctrl9_c, 1);
2915
2916 if (ret == 0)
2917 {
2918 ctrl9_c.ispu_rate = ((uint8_t)val & 0xfU);
2919 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL9_C, (uint8_t *)&ctrl9_c, 1);
2920 }
2921
2922 return ret;
2923 }
2924
2925 /**
2926 * @brief ISPU irq rate selection.[get]
2927 *
2928 * @param ctx read / write interface definitions
2929 * @param val ISPU_ODR_OFF, ISPU_ODR_AT_12Hz5, ISPU_ODR_AT_26Hz, ISPU_ODR_AT_52Hz,
2930 * ISPU_ODR_AT_104Hz, ISPU_ODR_AT_208Hz, ISPU_ODR_AT_417Hz, ISPU_ODR_AT_833Hz,
2931 * ISPU_ODR_AT_1667Hz, ISPU_ODR_AT_3333Hz, ISPU_ODR_AT_6667Hz
2932 * @retval interface status (MANDATORY: return 0 -> no Error)
2933 *
2934 */
lsm6dso16is_ispu_data_rate_get(stmdev_ctx_t * ctx,lsm6dso16is_ispu_data_rate_t * val)2935 int32_t lsm6dso16is_ispu_data_rate_get(stmdev_ctx_t *ctx,
2936 lsm6dso16is_ispu_data_rate_t *val)
2937 {
2938 lsm6dso16is_ctrl9_c_t ctrl9_c;
2939 int32_t ret;
2940
2941 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL9_C, (uint8_t *)&ctrl9_c, 1);
2942
2943 switch ((ctrl9_c.ispu_rate))
2944 {
2945 case LSM6DSO16IS_ISPU_ODR_OFF:
2946 *val = LSM6DSO16IS_ISPU_ODR_OFF;
2947 break;
2948
2949 case LSM6DSO16IS_ISPU_ODR_AT_12Hz5:
2950 *val = LSM6DSO16IS_ISPU_ODR_AT_12Hz5;
2951 break;
2952
2953 case LSM6DSO16IS_ISPU_ODR_AT_26Hz:
2954 *val = LSM6DSO16IS_ISPU_ODR_AT_26Hz;
2955 break;
2956
2957 case LSM6DSO16IS_ISPU_ODR_AT_52Hz:
2958 *val = LSM6DSO16IS_ISPU_ODR_AT_52Hz;
2959 break;
2960
2961 case LSM6DSO16IS_ISPU_ODR_AT_104Hz:
2962 *val = LSM6DSO16IS_ISPU_ODR_AT_104Hz;
2963 break;
2964
2965 case LSM6DSO16IS_ISPU_ODR_AT_208Hz:
2966 *val = LSM6DSO16IS_ISPU_ODR_AT_208Hz;
2967 break;
2968
2969 case LSM6DSO16IS_ISPU_ODR_AT_416Hz:
2970 *val = LSM6DSO16IS_ISPU_ODR_AT_416Hz;
2971 break;
2972
2973 case LSM6DSO16IS_ISPU_ODR_AT_833Hz:
2974 *val = LSM6DSO16IS_ISPU_ODR_AT_833Hz;
2975 break;
2976
2977 case LSM6DSO16IS_ISPU_ODR_AT_1667Hz:
2978 *val = LSM6DSO16IS_ISPU_ODR_AT_1667Hz;
2979 break;
2980
2981 case LSM6DSO16IS_ISPU_ODR_AT_3333Hz:
2982 *val = LSM6DSO16IS_ISPU_ODR_AT_3333Hz;
2983 break;
2984
2985 case LSM6DSO16IS_ISPU_ODR_AT_6667Hz:
2986 *val = LSM6DSO16IS_ISPU_ODR_AT_6667Hz;
2987 break;
2988
2989 default:
2990 *val = LSM6DSO16IS_ISPU_ODR_OFF;
2991 break;
2992 }
2993 return ret;
2994 }
2995
2996 /**
2997 * @brief ISPU bdu selection.[set]
2998 *
2999 * @param ctx read / write interface definitions
3000 * @param val ISPU_BDU_OFF, ISPU_BDU_ON_2B_4B, ISPU_BDU_ON_2B_2B, ISPU_BDU_ON_4B_4B,
3001 * @retval interface status (MANDATORY: return 0 -> no Error)
3002 *
3003 */
lsm6dso16is_ispu_bdu_set(stmdev_ctx_t * ctx,lsm6dso16is_ispu_bdu_t val)3004 int32_t lsm6dso16is_ispu_bdu_set(stmdev_ctx_t *ctx, lsm6dso16is_ispu_bdu_t val)
3005 {
3006 lsm6dso16is_ctrl9_c_t ctrl9_c;
3007 int32_t ret;
3008
3009 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL9_C, (uint8_t *)&ctrl9_c, 1);
3010
3011 if (ret == 0)
3012 {
3013 ctrl9_c.ispu_bdu = ((uint8_t)val & 0x3U);
3014 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL9_C, (uint8_t *)&ctrl9_c, 1);
3015 }
3016
3017 return ret;
3018 }
3019
3020 /**
3021 * @brief ISPU bdu selection.[get]
3022 *
3023 * @param ctx read / write interface definitions
3024 * @param val ISPU_BDU_OFF, ISPU_BDU_ON_2B_4B, ISPU_BDU_ON_2B_2B, ISPU_BDU_ON_4B_4B,
3025 * @retval interface status (MANDATORY: return 0 -> no Error)
3026 *
3027 */
lsm6dso16is_ispu_bdu_get(stmdev_ctx_t * ctx,lsm6dso16is_ispu_bdu_t * val)3028 int32_t lsm6dso16is_ispu_bdu_get(stmdev_ctx_t *ctx, lsm6dso16is_ispu_bdu_t *val)
3029 {
3030 lsm6dso16is_ctrl9_c_t ctrl9_c;
3031 int32_t ret;
3032
3033 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL9_C, (uint8_t *)&ctrl9_c, 1);
3034
3035 switch ((ctrl9_c.ispu_rate))
3036 {
3037 case LSM6DSO16IS_ISPU_BDU_OFF:
3038 *val = LSM6DSO16IS_ISPU_BDU_OFF;
3039 break;
3040
3041 case LSM6DSO16IS_ISPU_BDU_ON_2B_4B:
3042 *val = LSM6DSO16IS_ISPU_BDU_ON_2B_4B;
3043 break;
3044
3045 case LSM6DSO16IS_ISPU_BDU_ON_2B_2B:
3046 *val = LSM6DSO16IS_ISPU_BDU_ON_2B_2B;
3047 break;
3048
3049 case LSM6DSO16IS_ISPU_BDU_ON_4B_4B:
3050 *val = LSM6DSO16IS_ISPU_BDU_ON_4B_4B;
3051 break;
3052
3053 default:
3054 *val = LSM6DSO16IS_ISPU_BDU_OFF;
3055 break;
3056 }
3057 return ret;
3058 }
3059
3060 /**
3061 * @brief Generic Interrupt Flags from ISPU.[get]
3062 *
3063 * @param ctx read / write interface definitions
3064 * @param val Generic Interrupt Flags from ISPU.
3065 * @retval interface status (MANDATORY: return 0 -> no Error)
3066 *
3067 */
lsm6dso16is_ia_ispu_get(stmdev_ctx_t * ctx,uint32_t * val)3068 int32_t lsm6dso16is_ia_ispu_get(stmdev_ctx_t *ctx, uint32_t *val)
3069 {
3070 uint8_t buff[4];
3071 int32_t ret;
3072
3073 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_INT_STATUS0_MAINPAGE, &buff[0], 4);
3074
3075 *val = (uint32_t)buff[3];
3076 *val = (*val * 256U) + (uint32_t)buff[2];
3077 *val = (*val * 256U) + (uint32_t)buff[1];
3078 *val = (*val * 256U) + (uint32_t)buff[0];
3079
3080 return ret;
3081 }
3082
3083 /**
3084 * @brief General purpose input configuration register for ISPU[set]
3085 *
3086 * @param ctx read / write interface definitions
3087 * @param offset offset from ISPU_DUMMY_CFG_1 register
3088 * @param val General purpose input configuration register for ISPU
3089 * @param len number of bytes to write
3090 * @retval interface status (MANDATORY: return 0 -> no Error)
3091 *
3092 */
lsm6dso16is_ispu_write_dummy_cfg(stmdev_ctx_t * ctx,uint8_t offset,uint8_t * val,uint8_t len)3093 int32_t lsm6dso16is_ispu_write_dummy_cfg(stmdev_ctx_t *ctx, uint8_t offset,
3094 uint8_t *val, uint8_t len)
3095 {
3096 int32_t ret;
3097
3098 /* check if we are writing outside of the range */
3099 if (LSM6DSO16IS_ISPU_DUMMY_CFG_1_L + offset + len >
3100 LSM6DSO16IS_ISPU_DUMMY_CFG_4_H)
3101 {
3102 return -1;
3103 }
3104
3105 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_DUMMY_CFG_1_L + offset, val, len);
3106
3107 return ret;
3108 }
3109
3110 /**
3111 * @brief General purpose input configuration register for ISPU[set]
3112 *
3113 * @param ctx read / write interface definitions
3114 * @param offset offset from ISPU_DUMMY_CFG_1 register
3115 * @param val General purpose input configuration register for ISPU
3116 * @param len number of bytes to write
3117 * @retval interface status (MANDATORY: return 0 -> no Error)
3118 *
3119 */
lsm6dso16is_ispu_ready_dummy_cfg(stmdev_ctx_t * ctx,uint8_t offset,uint8_t * val,uint8_t len)3120 int32_t lsm6dso16is_ispu_ready_dummy_cfg(stmdev_ctx_t *ctx, uint8_t offset,
3121 uint8_t *val, uint8_t len)
3122 {
3123 int32_t ret;
3124
3125 /* check if we are reading outside of the range */
3126 if (LSM6DSO16IS_ISPU_DUMMY_CFG_1_L + offset + len >
3127 LSM6DSO16IS_ISPU_DUMMY_CFG_4_H)
3128 {
3129 return -1;
3130 }
3131
3132 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_DUMMY_CFG_1_L + offset, val, len);
3133
3134 return ret;
3135 }
3136
3137 /**
3138 * @brief Boot ISPU core[set]
3139 *
3140 * @param ctx read / write interface definitions
3141 * @param val Boot ISPU core
3142 * @retval interface status (MANDATORY: return 0 -> no Error)
3143 *
3144 */
lsm6dso16is_ispu_boot_set(stmdev_ctx_t * ctx,lsm6dso16is_ispu_boot_latched_t val)3145 int32_t lsm6dso16is_ispu_boot_set(stmdev_ctx_t *ctx,
3146 lsm6dso16is_ispu_boot_latched_t val)
3147 {
3148 lsm6dso16is_ispu_config_t ispu_config;
3149 int32_t ret;
3150
3151 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK);
3152
3153 if (ret == 0)
3154 {
3155 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_CONFIG,
3156 (uint8_t *)&ispu_config, 1);
3157 }
3158
3159 if (ret == 0)
3160 {
3161 ispu_config.ispu_rst_n = (uint8_t)val;
3162 ispu_config.clk_dis = (uint8_t)val;
3163 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_CONFIG,
3164 (uint8_t *)&ispu_config,
3165 1);
3166 }
3167
3168 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
3169
3170 return ret;
3171 }
3172
3173 /**
3174 * @brief Boot ISPU core[get]
3175 *
3176 * @param ctx read / write interface definitions
3177 * @param val Boot ISPU core
3178 * @retval interface status (MANDATORY: return 0 -> no Error)
3179 *
3180 */
lsm6dso16is_ispu_boot_get(stmdev_ctx_t * ctx,lsm6dso16is_ispu_boot_latched_t * val)3181 int32_t lsm6dso16is_ispu_boot_get(stmdev_ctx_t *ctx,
3182 lsm6dso16is_ispu_boot_latched_t *val)
3183 {
3184 lsm6dso16is_ispu_config_t ispu_config;
3185 int32_t ret;
3186
3187 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK);
3188
3189 if (ret == 0)
3190 {
3191 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_CONFIG,
3192 (uint8_t *)&ispu_config, 1);
3193 }
3194
3195 *val = LSM6DSO16IS_ISPU_TURN_OFF;
3196 if (ispu_config.ispu_rst_n == 1U || ispu_config.clk_dis == 1U)
3197 {
3198 *val = LSM6DSO16IS_ISPU_TURN_ON;
3199 }
3200
3201 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
3202
3203 return ret;
3204 }
3205
3206 /**
3207 * @brief Enables latched ISPU interrupt.[set]
3208 *
3209 * @param ctx read / write interface definitions
3210 * @param val ISPU_INT_PULSED, ISPU_INT_LATCHED,
3211 * @retval interface status (MANDATORY: return 0 -> no Error)
3212 *
3213 */
lsm6dso16is_ispu_int_latched_set(stmdev_ctx_t * ctx,lsm6dso16is_ispu_int_latched_t val)3214 int32_t lsm6dso16is_ispu_int_latched_set(stmdev_ctx_t *ctx,
3215 lsm6dso16is_ispu_int_latched_t val)
3216 {
3217 lsm6dso16is_ispu_config_t ispu_config;
3218 int32_t ret;
3219
3220 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK);
3221
3222 if (ret == 0)
3223 {
3224 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_CONFIG,
3225 (uint8_t *)&ispu_config, 1);
3226 }
3227
3228 if (ret == 0)
3229 {
3230 ispu_config.latched = ((uint8_t)val & 0x1U);
3231 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_CONFIG,
3232 (uint8_t *)&ispu_config,
3233 1);
3234 }
3235
3236 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
3237
3238 return ret;
3239 }
3240
3241 /**
3242 * @brief Enables latched ISPU interrupt.[get]
3243 *
3244 * @param ctx read / write interface definitions
3245 * @param val ISPU_INT_PULSED, ISPU_INT_LATCHED,
3246 * @retval interface status (MANDATORY: return 0 -> no Error)
3247 *
3248 */
lsm6dso16is_ispu_int_latched_get(stmdev_ctx_t * ctx,lsm6dso16is_ispu_int_latched_t * val)3249 int32_t lsm6dso16is_ispu_int_latched_get(stmdev_ctx_t *ctx,
3250 lsm6dso16is_ispu_int_latched_t *val)
3251 {
3252 lsm6dso16is_ispu_config_t ispu_config;
3253 int32_t ret;
3254
3255 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK);
3256
3257 if (ret == 0)
3258 {
3259 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_CONFIG,
3260 (uint8_t *)&ispu_config, 1);
3261 }
3262
3263 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
3264
3265 switch ((ispu_config.latched))
3266 {
3267 case LSM6DSO16IS_ISPU_INT_PULSED:
3268 *val = LSM6DSO16IS_ISPU_INT_PULSED;
3269 break;
3270
3271 case LSM6DSO16IS_ISPU_INT_LATCHED:
3272 *val = LSM6DSO16IS_ISPU_INT_LATCHED;
3273 break;
3274
3275 default:
3276 *val = LSM6DSO16IS_ISPU_INT_PULSED;
3277 break;
3278 }
3279 return ret;
3280 }
3281
3282 /**
3283 * @brief returns ISPU boot status
3284 *
3285 * @param ctx read / write interface definitions
3286 * @param val LSM6DSO16IS_ISPU_BOOT_IN_PROGRESS, LSM6DSO16IS_ISPU_BOOT_ENDED
3287 * @retval interface status (MANDATORY: return 0 -> no Error)
3288 *
3289 */
lsm6dso16is_ispu_get_boot_status(stmdev_ctx_t * ctx,lsm6dso16is_ispu_boot_end_t * val)3290 int32_t lsm6dso16is_ispu_get_boot_status(stmdev_ctx_t *ctx,
3291 lsm6dso16is_ispu_boot_end_t *val)
3292 {
3293 lsm6dso16is_ispu_status_t ispu_boot_status;
3294 int32_t ret;
3295
3296 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK);
3297 if (ret == 0)
3298 {
3299 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_STATUS,
3300 (uint8_t *)&ispu_boot_status, 1);
3301 *val = (lsm6dso16is_ispu_boot_end_t)ispu_boot_status.boot_end;
3302 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
3303 }
3304
3305 return ret;
3306 }
3307
lsm6dso16is_ispu_sel_memory_addr(stmdev_ctx_t * ctx,uint16_t mem_addr)3308 static int32_t lsm6dso16is_ispu_sel_memory_addr(stmdev_ctx_t *ctx, uint16_t mem_addr)
3309 {
3310 uint8_t mem_addr_l, mem_addr_h;
3311 int32_t ret = 0;
3312
3313 mem_addr_l = (uint8_t)(mem_addr & 0xFFU);
3314 mem_addr_h = (uint8_t)(mem_addr / 256U);
3315 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_MEM_ADDR1,
3316 (uint8_t *)&mem_addr_h, 1);
3317 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_MEM_ADDR0,
3318 (uint8_t *)&mem_addr_l, 1);
3319
3320 return ret;
3321 }
3322
3323 /**
3324 * @brief ISPU write memory
3325 *
3326 * @param ctx read / write interface definitions
3327 * @param mem_sel LSM6DSO16IS_ISPU_DATA_RAM_MEMORY, LSM6DSO16IS_ISPU_PROGRAM_RAM_MEMORY
3328 * @param mem_addr memory address
3329 * @param mem_data memory data
3330 * @param len data length
3331 * @retval interface status (MANDATORY: return 0 -> no Error)
3332 *
3333 */
lsm6dso16is_ispu_write_memory(stmdev_ctx_t * ctx,lsm6dso16is_ispu_memory_type_t mem_sel,uint16_t mem_addr,uint8_t * mem_data,uint16_t len)3334 int32_t lsm6dso16is_ispu_write_memory(stmdev_ctx_t *ctx,
3335 lsm6dso16is_ispu_memory_type_t mem_sel,
3336 uint16_t mem_addr, uint8_t *mem_data, uint16_t len)
3337 {
3338 lsm6dso16is_ispu_mem_sel_t ispu_mem_sel;
3339 int32_t ret;
3340 uint16_t i;
3341
3342 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK);
3343 if (ret == 0)
3344 {
3345 /* select memory to be written */
3346 ispu_mem_sel.read_mem_en = 0;
3347 ispu_mem_sel.mem_sel = (uint8_t)mem_sel;
3348 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_MEM_SEL, (uint8_t *)&ispu_mem_sel, 1);
3349
3350 if (mem_sel == LSM6DSO16IS_ISPU_PROGRAM_RAM_MEMORY)
3351 {
3352 uint16_t addr_s[4] = {0U, 0U, 0U, 0U};
3353 uint16_t len_s[4] = {0U, 0U, 0U, 0U};
3354 uint8_t j = 0;
3355 uint16_t k;
3356
3357 addr_s[0] = mem_addr;
3358 for (i = 0, k = 0; i < len; i++, k++)
3359 {
3360 if ((mem_addr + i == 0x2000U) || (mem_addr + i == 0x4000U) || (mem_addr + i == 0x6000U))
3361 {
3362 len_s[j++] = k;
3363 addr_s[j] = mem_addr + i;
3364 k = 0;
3365 }
3366 }
3367 len_s[j++] = k;
3368
3369 for (i = 0, k = 0; i < j; k+=len_s[i], i++)
3370 {
3371 ret += lsm6dso16is_ispu_sel_memory_addr(ctx, addr_s[i]);
3372 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_MEM_DATA, &mem_data[k], len_s[i]);
3373 }
3374 } else {
3375 /* select memory address */
3376 ret += lsm6dso16is_ispu_sel_memory_addr(ctx, mem_addr);
3377 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_MEM_DATA, &mem_data[0], len);
3378 }
3379 }
3380
3381 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
3382
3383 return ret;
3384 }
3385
3386 /**
3387 * @brief ISPU read memory
3388 *
3389 * @param ctx read / write interface definitions
3390 * @param mem_sel LSM6DSO16IS_ISPU_DATA_RAM_MEMORY, LSM6DSO16IS_ISPU_PROGRAM_RAM_MEMORY
3391 * @param mem_addr memory address
3392 * @param mem_data memory data
3393 * @param len data length
3394 * @retval interface status (MANDATORY: return 0 -> no Error)
3395 *
3396 */
lsm6dso16is_ispu_read_memory(stmdev_ctx_t * ctx,lsm6dso16is_ispu_memory_type_t mem_sel,uint16_t mem_addr,uint8_t * mem_data,uint16_t len)3397 int32_t lsm6dso16is_ispu_read_memory(stmdev_ctx_t *ctx,
3398 lsm6dso16is_ispu_memory_type_t mem_sel,
3399 uint16_t mem_addr, uint8_t *mem_data, uint16_t len)
3400 {
3401 lsm6dso16is_ispu_mem_sel_t ispu_mem_sel;
3402 int32_t ret;
3403 uint8_t dummy;
3404
3405 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK);
3406 if (ret == 0)
3407 {
3408 /* select memory to be read */
3409 ispu_mem_sel.read_mem_en = 1;
3410 ispu_mem_sel.mem_sel = (uint8_t)mem_sel;
3411 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_MEM_SEL, (uint8_t *)&ispu_mem_sel, 1);
3412
3413 /* select memory address */
3414 ret += lsm6dso16is_ispu_sel_memory_addr(ctx, mem_addr);
3415 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_MEM_DATA, &dummy, 1);
3416
3417 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_MEM_DATA, &mem_data[0], len);
3418 }
3419
3420 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
3421
3422 return ret;
3423 }
3424
3425 /**
3426 * @brief ISPU write flags (IF2S)
3427 *
3428 * @param ctx read / write interface definitions
3429 * @param data ISPU flags
3430 * @retval interface status (MANDATORY: return 0 -> no Error)
3431 *
3432 */
lsm6dso16is_ispu_write_flags(stmdev_ctx_t * ctx,uint16_t data)3433 int32_t lsm6dso16is_ispu_write_flags(stmdev_ctx_t *ctx, uint16_t data)
3434 {
3435 lsm6dso16is_ispu_if2s_flag_l_t flag_l;
3436 lsm6dso16is_ispu_if2s_flag_h_t flag_h;
3437 int32_t ret;
3438
3439 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK);
3440 if (ret == 0)
3441 {
3442 /* write the flags */
3443 flag_h.if2s = (uint8_t)(data / 256U);
3444 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_IF2S_FLAG_H,
3445 (uint8_t *)&flag_h,
3446 1);
3447 flag_l.if2s = (uint8_t)(data & 0xffU);
3448 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_IF2S_FLAG_L,
3449 (uint8_t *)&flag_l,
3450 1);
3451 }
3452
3453 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
3454
3455 return ret;
3456 }
3457
3458 /**
3459 * @brief ISPU read flags (S2IF)
3460 *
3461 * @param ctx read / write interface definitions
3462 * @param data ISPU flags
3463 * @retval interface status (MANDATORY: return 0 -> no Error)
3464 *
3465 */
lsm6dso16is_ispu_read_flags(stmdev_ctx_t * ctx,uint16_t * data)3466 int32_t lsm6dso16is_ispu_read_flags(stmdev_ctx_t *ctx, uint16_t *data)
3467 {
3468 uint8_t buff[2];
3469 int32_t ret;
3470
3471 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK);
3472 if (ret == 0)
3473 {
3474 /* read the flags */
3475 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_S2IF_FLAG_L, buff, 2);
3476 data[0] = (uint16_t)buff[1];
3477 data[0] = (data[0] * 256U) + (uint16_t)buff[0];
3478 }
3479
3480 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
3481
3482 return ret;
3483 }
3484
3485 /**
3486 * @brief ISPU clear flags (S2IF)
3487 *
3488 * @param ctx read / write interface definitions
3489 * @retval interface status (MANDATORY: return 0 -> no Error)
3490 *
3491 */
lsm6dso16is_ispu_clear_flags(stmdev_ctx_t * ctx)3492 int32_t lsm6dso16is_ispu_clear_flags(stmdev_ctx_t *ctx)
3493 {
3494 uint8_t data = 1;
3495 int32_t ret;
3496
3497 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK);
3498
3499 if (ret == 0)
3500 {
3501 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_S2IF_FLAG_H, &data, 1);
3502 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
3503 }
3504
3505 return ret;
3506 }
3507
3508 /**
3509 * @brief ISPU DOUT registers.[get]
3510 *
3511 * @param ctx read / write interface definitions
3512 * @param val ISPU DOUT output registers.
3513 * @retval interface status (MANDATORY: return 0 -> no Error)
3514 *
3515 */
lsm6dso16is_ispu_read_data_raw_get(stmdev_ctx_t * ctx,uint8_t * val,uint8_t len)3516 int32_t lsm6dso16is_ispu_read_data_raw_get(stmdev_ctx_t *ctx,
3517 uint8_t *val,
3518 uint8_t len)
3519 {
3520 int32_t ret;
3521
3522 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK);
3523 if (ret == 0)
3524 {
3525 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_DOUT_00_L, (uint8_t *) val,
3526 len);
3527 }
3528
3529 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
3530
3531 return ret;
3532 }
3533
3534 /**
3535 * @brief ISPU int1_ctrl.[get]
3536 *
3537 * @param ctx read / write interface definitions
3538 * @param val ISPU int1_ctrl register value
3539 * @retval interface status (MANDATORY: return 0 -> no Error)
3540 *
3541 */
lsm6dso16is_ispu_int1_ctrl_get(stmdev_ctx_t * ctx,uint32_t * val)3542 int32_t lsm6dso16is_ispu_int1_ctrl_get(stmdev_ctx_t *ctx, uint32_t *val)
3543 {
3544 uint8_t buff[4];
3545 int32_t ret;
3546
3547 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK);
3548 if (ret == 0)
3549 {
3550 /* read int1_ctrl reg */
3551 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_INT1_CTRL0, &buff[0], 4);
3552
3553 *val = (uint32_t)buff[3];
3554 *val = (*val * 256U) + (uint32_t)buff[2];
3555 *val = (*val * 256U) + (uint32_t)buff[1];
3556 *val = (*val * 256U) + (uint32_t)buff[0];
3557 }
3558
3559 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
3560
3561 return ret;
3562 }
3563
3564 /**
3565 * @brief ISPU int1_ctrl.[set]
3566 *
3567 * @param ctx read / write interface definitions
3568 * @param val ISPU int1_ctrl register value
3569 * @retval interface status (MANDATORY: return 0 -> no Error)
3570 *
3571 */
lsm6dso16is_ispu_int1_ctrl_set(stmdev_ctx_t * ctx,uint32_t val)3572 int32_t lsm6dso16is_ispu_int1_ctrl_set(stmdev_ctx_t *ctx, uint32_t val)
3573 {
3574 lsm6dso16is_ispu_int1_ctrl0_t int1_ctrl0;
3575 lsm6dso16is_ispu_int1_ctrl1_t int1_ctrl1;
3576 lsm6dso16is_ispu_int1_ctrl2_t int1_ctrl2;
3577 lsm6dso16is_ispu_int1_ctrl3_t int1_ctrl3;
3578 int32_t ret;
3579
3580 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK);
3581 if (ret == 0)
3582 {
3583 /* write the int1_ctrl reg */
3584 int1_ctrl3.ispu_int1_ctrl = (uint8_t)((val >> 24) & 0xffU);
3585 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_INT1_CTRL3,
3586 (uint8_t *)&int1_ctrl3,
3587 1);
3588
3589 int1_ctrl2.ispu_int1_ctrl = (uint8_t)((val >> 16) & 0xffU);
3590 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_INT1_CTRL2,
3591 (uint8_t *)&int1_ctrl2,
3592 1);
3593
3594 int1_ctrl1.ispu_int1_ctrl = (uint8_t)((val >> 8) & 0xffU);
3595 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_INT1_CTRL1,
3596 (uint8_t *)&int1_ctrl1,
3597 1);
3598
3599 int1_ctrl0.ispu_int1_ctrl = (uint8_t)(val & 0xffU);
3600 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_INT1_CTRL0,
3601 (uint8_t *)&int1_ctrl0,
3602 1);
3603 }
3604
3605 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
3606
3607 return ret;
3608 }
3609
3610 /**
3611 * @brief ISPU int2_ctrl.[get]
3612 *
3613 * @param ctx read / write interface definitions
3614 * @param val ISPU int2_ctrl register value
3615 * @retval interface status (MANDATORY: return 0 -> no Error)
3616 *
3617 */
lsm6dso16is_ispu_int2_ctrl_get(stmdev_ctx_t * ctx,uint32_t * val)3618 int32_t lsm6dso16is_ispu_int2_ctrl_get(stmdev_ctx_t *ctx, uint32_t *val)
3619 {
3620 uint8_t buff[4];
3621 int32_t ret;
3622
3623 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK);
3624 if (ret == 0)
3625 {
3626 /* read int2_ctrl reg */
3627 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_INT2_CTRL0, &buff[0], 4);
3628
3629 *val = (uint32_t)buff[3];
3630 *val = (*val * 256U) + (uint32_t)buff[2];
3631 *val = (*val * 256U) + (uint32_t)buff[1];
3632 *val = (*val * 256U) + (uint32_t)buff[0];
3633 }
3634
3635 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
3636
3637 return ret;
3638 }
3639
3640 /**
3641 * @brief ISPU int2_ctrl.[set]
3642 *
3643 * @param ctx read / write interface definitions
3644 * @param val ISPU int2_ctrl register value
3645 * @retval interface status (MANDATORY: return 0 -> no Error)
3646 *
3647 */
lsm6dso16is_ispu_int2_ctrl_set(stmdev_ctx_t * ctx,uint32_t val)3648 int32_t lsm6dso16is_ispu_int2_ctrl_set(stmdev_ctx_t *ctx, uint32_t val)
3649 {
3650 lsm6dso16is_ispu_int2_ctrl0_t int2_ctrl0;
3651 lsm6dso16is_ispu_int2_ctrl1_t int2_ctrl1;
3652 lsm6dso16is_ispu_int2_ctrl2_t int2_ctrl2;
3653 lsm6dso16is_ispu_int2_ctrl3_t int2_ctrl3;
3654 int32_t ret;
3655
3656 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK);
3657 if (ret == 0)
3658 {
3659 /* write the int2_ctrl reg */
3660 int2_ctrl3.ispu_int2_ctrl = (uint8_t)((val >> 24) & 0xffU);
3661 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_INT2_CTRL3,
3662 (uint8_t *)&int2_ctrl3,
3663 1);
3664
3665 int2_ctrl2.ispu_int2_ctrl = (uint8_t)((val >> 16) & 0xffU);
3666 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_INT2_CTRL2,
3667 (uint8_t *)&int2_ctrl2,
3668 1);
3669
3670 int2_ctrl1.ispu_int2_ctrl = (uint8_t)((val >> 8) & 0xffU);
3671 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_INT2_CTRL1,
3672 (uint8_t *)&int2_ctrl1,
3673 1);
3674
3675 int2_ctrl0.ispu_int2_ctrl = (uint8_t)(val & 0xffU);
3676 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_INT2_CTRL0,
3677 (uint8_t *)&int2_ctrl0,
3678 1);
3679 }
3680
3681 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
3682
3683 return ret;
3684 }
3685
3686 /**
3687 * @brief ISPU int_status.[get]
3688 *
3689 * @param ctx read / write interface definitions
3690 * @param val ISPU int2_status register value
3691 * @retval interface status (MANDATORY: return 0 -> no Error)
3692 *
3693 */
lsm6dso16is_ispu_int_status_get(stmdev_ctx_t * ctx,uint32_t * val)3694 int32_t lsm6dso16is_ispu_int_status_get(stmdev_ctx_t *ctx, uint32_t *val)
3695 {
3696 uint8_t buff[4];
3697 int32_t ret;
3698
3699 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK);
3700 if (ret == 0)
3701 {
3702 /* read int2_ctrl reg */
3703 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_INT_STATUS0, &buff[0], 4);
3704
3705 *val = (uint32_t)buff[3];
3706 *val = (*val * 256U) + (uint32_t)buff[2];
3707 *val = (*val * 256U) + (uint32_t)buff[1];
3708 *val = (*val * 256U) + (uint32_t)buff[0];
3709 }
3710
3711 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
3712
3713 return ret;
3714 }
3715
3716 /**
3717 * @brief ISPU algo.[get]
3718 *
3719 * @param ctx read / write interface definitions
3720 * @param val ISPU algo register value
3721 * @retval interface status (MANDATORY: return 0 -> no Error)
3722 *
3723 */
lsm6dso16is_ispu_algo_get(stmdev_ctx_t * ctx,uint32_t * val)3724 int32_t lsm6dso16is_ispu_algo_get(stmdev_ctx_t *ctx, uint32_t *val)
3725 {
3726 uint8_t buff[4];
3727 int32_t ret;
3728
3729 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK);
3730 if (ret == 0)
3731 {
3732 /* read int2_ctrl reg */
3733 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_ALGO0, &buff[0], 4);
3734
3735 *val = (uint32_t)buff[3];
3736 *val = (*val * 256U) + (uint32_t)buff[2];
3737 *val = (*val * 256U) + (uint32_t)buff[1];
3738 *val = (*val * 256U) + (uint32_t)buff[0];
3739 }
3740
3741 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
3742
3743 return ret;
3744 }
3745
3746 /**
3747 * @brief ISPU algo.[set]
3748 *
3749 * @param ctx read / write interface definitions
3750 * @param val ISPU algo register value
3751 * @retval interface status (MANDATORY: return 0 -> no Error)
3752 *
3753 */
lsm6dso16is_ispu_algo_set(stmdev_ctx_t * ctx,uint32_t val)3754 int32_t lsm6dso16is_ispu_algo_set(stmdev_ctx_t *ctx, uint32_t val)
3755 {
3756 lsm6dso16is_ispu_algo0_t algo0;
3757 lsm6dso16is_ispu_algo1_t algo1;
3758 lsm6dso16is_ispu_algo2_t algo2;
3759 lsm6dso16is_ispu_algo3_t algo3;
3760 int32_t ret;
3761
3762 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK);
3763 if (ret == 0)
3764 {
3765 /* write the algo reg */
3766 algo3.ispu_algo = (uint8_t)((val >> 24) & 0xffU);
3767 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_ALGO3, (uint8_t *)&algo3, 1);
3768
3769 algo2.ispu_algo = (uint8_t)((val >> 16) & 0xffU);
3770 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_ALGO2, (uint8_t *)&algo2, 1);
3771
3772 algo1.ispu_algo = (uint8_t)((val >> 8) & 0xffU);
3773 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_ALGO1, (uint8_t *)&algo1, 1);
3774
3775 algo0.ispu_algo = (uint8_t)(val & 0xffU);
3776 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_ALGO0, (uint8_t *)&algo0, 1);
3777 }
3778
3779 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
3780
3781 return ret;
3782 }
3783
3784 /**
3785 * @}
3786 *
3787 */
3788
