1 /**
2 ******************************************************************************
3 * @file lis3mdl_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LIS3MDL driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lis3mdl_reg.h"
21
22 /**
23 * @defgroup LIS3MDL
24 * @brief This file provides a set of functions needed to drive the
25 * lis3mdl enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup LIS3MDL_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lis3mdl_read_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lis3mdl_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 ret = ctx->read_reg(ctx->handle, reg, data, len);
56
57 return ret;
58 }
59
60 /**
61 * @brief Write generic device register
62 *
63 * @param ctx read / write interface definitions(ptr)
64 * @param reg register to write
65 * @param data pointer to data to write in register reg(ptr)
66 * @param len number of consecutive register to write
67 * @retval interface status (MANDATORY: return 0 -> no Error)
68 *
69 */
lis3mdl_write_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)70 int32_t __weak lis3mdl_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
71 uint8_t *data,
72 uint16_t len)
73 {
74 int32_t ret;
75
76 ret = ctx->write_reg(ctx->handle, reg, data, len);
77
78 return ret;
79 }
80
81 /**
82 * @}
83 *
84 */
85
86 /**
87 * @defgroup LIS3MDL_Sensitivity
88 * @brief These functions convert raw-data into engineering units.
89 * @{
90 *
91 */
92
lis3mdl_from_fs4_to_gauss(int16_t lsb)93 float_t lis3mdl_from_fs4_to_gauss(int16_t lsb)
94 {
95 return ((float_t)lsb / 6842.0f);
96 }
97
lis3mdl_from_fs8_to_gauss(int16_t lsb)98 float_t lis3mdl_from_fs8_to_gauss(int16_t lsb)
99 {
100 return ((float_t)lsb / 3421.0f);
101 }
102
lis3mdl_from_fs12_to_gauss(int16_t lsb)103 float_t lis3mdl_from_fs12_to_gauss(int16_t lsb)
104 {
105 return ((float_t)lsb / 2281.0f);
106 }
107
lis3mdl_from_fs16_to_gauss(int16_t lsb)108 float_t lis3mdl_from_fs16_to_gauss(int16_t lsb)
109 {
110 return ((float_t)lsb / 1711.0f);
111 }
112
lis3mdl_from_lsb_to_celsius(int16_t lsb)113 float_t lis3mdl_from_lsb_to_celsius(int16_t lsb)
114 {
115 return ((float_t)lsb / 8.0f) + (25.0f);
116 }
117
118 /**
119 * @}
120 *
121 */
122
123 /**
124 * @defgroup LIS3MDL_Data_Generation
125 * @brief This section group all the functions concerning
126 * data generation
127 * @{
128 *
129 */
130
131 /**
132 * @brief Output data rate selection.[set]
133 *
134 * @param ctx read / write interface definitions(ptr)
135 * @param val change the values of om in reg CTRL_REG1
136 * @retval interface status (MANDATORY: return 0 -> no Error)
137 *
138 */
lis3mdl_data_rate_set(stmdev_ctx_t * ctx,lis3mdl_om_t val)139 int32_t lis3mdl_data_rate_set(stmdev_ctx_t *ctx, lis3mdl_om_t val)
140 {
141 lis3mdl_ctrl_reg1_t ctrl_reg1;
142 lis3mdl_ctrl_reg4_t ctrl_reg4;
143 int32_t ret;
144
145 ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
146
147 if (ret == 0)
148 {
149 ctrl_reg1.om = (uint8_t)val;
150 ret = lis3mdl_write_reg(ctx, LIS3MDL_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
151 }
152
153 if (ret == 0)
154 {
155 /* set mode also for z axis, ctrl_reg4 -> omz */
156 ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
157 }
158
159 if (ret == 0)
160 {
161 ctrl_reg4.omz = (uint8_t)(((uint8_t) val >> 4) & 0x03U);
162 ret = lis3mdl_write_reg(ctx, LIS3MDL_CTRL_REG4,
163 (uint8_t *)&ctrl_reg4, 1);
164 }
165
166 return ret;
167 }
168
169 /**
170 * @brief Output data rate selection[get]
171 *
172 * @param ctx read / write interface definitions(ptr)
173 * @param val Get the values of om in reg CTRL_REG1(ptr)
174 * @retval interface status (MANDATORY: return 0 -> no Error)
175 *
176 */
lis3mdl_data_rate_get(stmdev_ctx_t * ctx,lis3mdl_om_t * val)177 int32_t lis3mdl_data_rate_get(stmdev_ctx_t *ctx, lis3mdl_om_t *val)
178 {
179 lis3mdl_ctrl_reg1_t ctrl_reg1;
180 int32_t ret;
181
182 /* z axis, ctrl_reg4 -> omz is aligned with x/y axis ctrl_reg1 -> om*/
183 ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
184
185 switch (ctrl_reg1.om)
186 {
187 case LIS3MDL_LP_Hz625:
188 *val = LIS3MDL_LP_Hz625;
189 break;
190
191 case LIS3MDL_LP_1kHz:
192 *val = LIS3MDL_LP_1kHz;
193 break;
194
195 case LIS3MDL_MP_560Hz:
196 *val = LIS3MDL_MP_560Hz;
197 break;
198
199 case LIS3MDL_HP_300Hz:
200 *val = LIS3MDL_HP_300Hz;
201 break;
202
203 case LIS3MDL_UHP_155Hz:
204 *val = LIS3MDL_UHP_155Hz;
205 break;
206
207 case LIS3MDL_LP_1Hz25:
208 *val = LIS3MDL_LP_1Hz25;
209 break;
210
211 case LIS3MDL_LP_2Hz5:
212 *val = LIS3MDL_LP_2Hz5;
213 break;
214
215 case LIS3MDL_LP_5Hz:
216 *val = LIS3MDL_LP_5Hz;
217 break;
218
219 case LIS3MDL_LP_10Hz:
220 *val = LIS3MDL_LP_10Hz;
221 break;
222
223 case LIS3MDL_LP_20Hz:
224 *val = LIS3MDL_LP_20Hz;
225 break;
226
227 case LIS3MDL_LP_40Hz:
228 *val = LIS3MDL_LP_40Hz;
229 break;
230
231 case LIS3MDL_LP_80Hz:
232 *val = LIS3MDL_LP_80Hz;
233 break;
234
235 case LIS3MDL_MP_1Hz25:
236 *val = LIS3MDL_MP_1Hz25;
237 break;
238
239 case LIS3MDL_MP_2Hz5:
240 *val = LIS3MDL_MP_2Hz5;
241 break;
242
243 case LIS3MDL_MP_5Hz:
244 *val = LIS3MDL_MP_5Hz;
245 break;
246
247 case LIS3MDL_MP_10Hz:
248 *val = LIS3MDL_MP_10Hz;
249 break;
250
251 case LIS3MDL_MP_20Hz:
252 *val = LIS3MDL_MP_20Hz;
253 break;
254
255 case LIS3MDL_MP_40Hz:
256 *val = LIS3MDL_MP_40Hz;
257 break;
258
259 case LIS3MDL_MP_80Hz:
260 *val = LIS3MDL_MP_80Hz;
261 break;
262
263 case LIS3MDL_HP_1Hz25:
264 *val = LIS3MDL_HP_1Hz25;
265 break;
266
267 case LIS3MDL_HP_2Hz5:
268 *val = LIS3MDL_HP_2Hz5;
269 break;
270
271 case LIS3MDL_HP_5Hz:
272 *val = LIS3MDL_HP_5Hz;
273 break;
274
275 case LIS3MDL_HP_10Hz:
276 *val = LIS3MDL_HP_10Hz;
277 break;
278
279 case LIS3MDL_HP_20Hz:
280 *val = LIS3MDL_HP_20Hz;
281 break;
282
283 case LIS3MDL_HP_40Hz:
284 *val = LIS3MDL_HP_40Hz;
285 break;
286
287 case LIS3MDL_HP_80Hz:
288 *val = LIS3MDL_HP_80Hz;
289 break;
290
291 case LIS3MDL_UHP_1Hz25:
292 *val = LIS3MDL_UHP_1Hz25;
293 break;
294
295 case LIS3MDL_UHP_2Hz5:
296 *val = LIS3MDL_UHP_2Hz5;
297 break;
298
299 case LIS3MDL_UHP_5Hz:
300 *val = LIS3MDL_UHP_5Hz;
301 break;
302
303 case LIS3MDL_UHP_10Hz:
304 *val = LIS3MDL_UHP_10Hz;
305 break;
306
307 case LIS3MDL_UHP_20Hz:
308 *val = LIS3MDL_UHP_20Hz;
309 break;
310
311 case LIS3MDL_UHP_40Hz:
312 *val = LIS3MDL_UHP_40Hz;
313 break;
314
315 case LIS3MDL_UHP_80Hz:
316 *val = LIS3MDL_UHP_80Hz;
317 break;
318
319 default:
320 *val = LIS3MDL_UHP_80Hz;
321 break;
322 }
323
324 return ret;
325 }
326
327 /**
328 * @brief Temperature sensor enable[set]
329 *
330 * @param ctx read / write interface definitions(ptr)
331 * @param val change the values of temp_en in reg CTRL_REG1
332 * @retval interface status (MANDATORY: return 0 -> no Error)
333 *
334 */
lis3mdl_temperature_meas_set(stmdev_ctx_t * ctx,uint8_t val)335 int32_t lis3mdl_temperature_meas_set(stmdev_ctx_t *ctx, uint8_t val)
336 {
337 lis3mdl_ctrl_reg1_t ctrl_reg1;
338 int32_t ret;
339
340 ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
341
342 if (ret == 0)
343 {
344 ctrl_reg1.temp_en = val;
345 ret = lis3mdl_write_reg(ctx, LIS3MDL_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
346 }
347
348 return ret;
349 }
350
351 /**
352 * @brief Temperature sensor enable[get]
353 *
354 * @param ctx read / write interface definitions(ptr)
355 * @param val change the values of temp_en in reg CTRL_REG1(ptr)
356 * @retval interface status (MANDATORY: return 0 -> no Error)
357 *
358 */
lis3mdl_temperature_meas_get(stmdev_ctx_t * ctx,uint8_t * val)359 int32_t lis3mdl_temperature_meas_get(stmdev_ctx_t *ctx, uint8_t *val)
360 {
361 lis3mdl_ctrl_reg1_t ctrl_reg1;
362 int32_t ret;
363
364 ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
365 *val = (uint8_t)ctrl_reg1.temp_en;
366
367 return ret;
368 }
369
370 /**
371 * @brief Full-scale configuration[set]
372 *
373 * @param ctx read / write interface definitions(ptr)
374 * @param val change the values of fs in reg CTRL_REG2
375 * @retval interface status (MANDATORY: return 0 -> no Error)
376 *
377 */
lis3mdl_full_scale_set(stmdev_ctx_t * ctx,lis3mdl_fs_t val)378 int32_t lis3mdl_full_scale_set(stmdev_ctx_t *ctx, lis3mdl_fs_t val)
379 {
380 lis3mdl_ctrl_reg2_t ctrl_reg2;
381 int32_t ret;
382
383 ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
384
385 if (ret == 0)
386 {
387 ctrl_reg2.fs = (uint8_t)val;
388 ret = lis3mdl_write_reg(ctx, LIS3MDL_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
389 }
390
391 return ret;
392 }
393
394 /**
395 * @brief Full-scale configuration[get]
396 *
397 * @param ctx read / write interface definitions(ptr)
398 * @param val get the values of fs in reg CTRL_REG2(ptr)
399 * @retval interface status (MANDATORY: return 0 -> no Error)
400 *
401 */
lis3mdl_full_scale_get(stmdev_ctx_t * ctx,lis3mdl_fs_t * val)402 int32_t lis3mdl_full_scale_get(stmdev_ctx_t *ctx, lis3mdl_fs_t *val)
403 {
404 lis3mdl_ctrl_reg2_t ctrl_reg2;
405 int32_t ret;
406
407 ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
408
409 switch (ctrl_reg2.fs)
410 {
411 case LIS3MDL_4_GAUSS:
412 *val = LIS3MDL_4_GAUSS;
413 break;
414
415 case LIS3MDL_8_GAUSS:
416 *val = LIS3MDL_8_GAUSS;
417 break;
418
419 case LIS3MDL_12_GAUSS:
420 *val = LIS3MDL_12_GAUSS;
421 break;
422
423 case LIS3MDL_16_GAUSS:
424 *val = LIS3MDL_16_GAUSS;
425 break;
426
427 default:
428 *val = LIS3MDL_4_GAUSS;
429 break;
430 }
431
432 return ret;
433 }
434
435 /**
436 * @brief Operating mode selection[set]
437 *
438 * @param ctx read / write interface definitions(ptr)
439 * @param val change the values of md in reg CTRL_REG3
440 * @retval interface status (MANDATORY: return 0 -> no Error)
441 *
442 */
lis3mdl_operating_mode_set(stmdev_ctx_t * ctx,lis3mdl_md_t val)443 int32_t lis3mdl_operating_mode_set(stmdev_ctx_t *ctx,
444 lis3mdl_md_t val)
445 {
446 lis3mdl_ctrl_reg3_t ctrl_reg3;
447 int32_t ret;
448
449 ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
450
451 if (ret == 0)
452 {
453 ctrl_reg3.md = (uint8_t)val;
454 ret = lis3mdl_write_reg(ctx, LIS3MDL_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
455 }
456
457 return ret;
458 }
459
460 /**
461 * @brief Operating mode selection[get]
462 *
463 * @param ctx read / write interface definitions(ptr)
464 * @param val Get the values of md in reg CTRL_REG3(ptr)
465 * @retval interface status (MANDATORY: return 0 -> no Error)
466 *
467 */
lis3mdl_operating_mode_get(stmdev_ctx_t * ctx,lis3mdl_md_t * val)468 int32_t lis3mdl_operating_mode_get(stmdev_ctx_t *ctx,
469 lis3mdl_md_t *val)
470 {
471 lis3mdl_ctrl_reg3_t ctrl_reg3;
472 int32_t ret;
473
474 ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
475
476 switch (ctrl_reg3.md)
477 {
478 case LIS3MDL_CONTINUOUS_MODE:
479 *val = LIS3MDL_CONTINUOUS_MODE;
480 break;
481
482 case LIS3MDL_SINGLE_TRIGGER:
483 *val = LIS3MDL_SINGLE_TRIGGER;
484 break;
485
486 case LIS3MDL_POWER_DOWN:
487 *val = LIS3MDL_POWER_DOWN;
488 break;
489
490 default:
491 *val = LIS3MDL_POWER_DOWN;
492 break;
493 }
494
495 return ret;
496 }
497
498 /**
499 * @brief If this bit is high, device is set in low power to 0.625 Hz[set]
500 *
501 * @param ctx read / write interface definitions(ptr)
502 * @param val change the values of lp in reg CTRL_REG3
503 * @retval interface status (MANDATORY: return 0 -> no Error)
504 *
505 */
lis3mdl_fast_low_power_set(stmdev_ctx_t * ctx,uint8_t val)506 int32_t lis3mdl_fast_low_power_set(stmdev_ctx_t *ctx, uint8_t val)
507 {
508 lis3mdl_ctrl_reg3_t ctrl_reg3;
509 int32_t ret;
510
511 ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
512
513 if (ret == 0)
514 {
515 ctrl_reg3.lp = val;
516 ret = lis3mdl_write_reg(ctx, LIS3MDL_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
517 }
518
519 return ret;
520 }
521
522 /**
523 * @brief If this bit is high, device is set in low power to 0.625 Hz[get]
524 *
525 * @param ctx read / write interface definitions(ptr)
526 * @param val change the values of lp in reg CTRL_REG3(ptr)
527 * @retval interface status (MANDATORY: return 0 -> no Error)
528 *
529 */
lis3mdl_fast_low_power_get(stmdev_ctx_t * ctx,uint8_t * val)530 int32_t lis3mdl_fast_low_power_get(stmdev_ctx_t *ctx, uint8_t *val)
531 {
532 lis3mdl_ctrl_reg3_t ctrl_reg3;
533 int32_t ret;
534
535 ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
536 *val = (uint8_t)ctrl_reg3.lp;
537
538 return ret;
539 }
540
541 /**
542 * @brief Block data update[set]
543 *
544 * @param ctx read / write interface definitions(ptr)
545 * @param val change the values of bdu in reg CTRL_REG5
546 * @retval interface status (MANDATORY: return 0 -> no Error)
547 *
548 */
lis3mdl_block_data_update_set(stmdev_ctx_t * ctx,uint8_t val)549 int32_t lis3mdl_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
550 {
551 lis3mdl_ctrl_reg5_t ctrl_reg5;
552 int32_t ret;
553
554 ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
555
556 if (ret == 0)
557 {
558 ctrl_reg5.bdu = val;
559 ret = lis3mdl_write_reg(ctx, LIS3MDL_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
560 }
561
562 return ret;
563 }
564
565 /**
566 * @brief Block data update[get]
567 *
568 * @param ctx read / write interface definitions(ptr)
569 * @param val change the values of bdu in reg CTRL_REG5(ptr)
570 * @retval interface status (MANDATORY: return 0 -> no Error)
571 *
572 */
lis3mdl_block_data_update_get(stmdev_ctx_t * ctx,uint8_t * val)573 int32_t lis3mdl_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
574 {
575 lis3mdl_ctrl_reg5_t ctrl_reg5;
576 int32_t ret;
577
578 ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
579 *val = (uint8_t)ctrl_reg5.bdu;
580
581 return ret;
582 }
583
584 /**
585 * @brief fast_read allows reading the high part of DATA OUT only in order
586 * to increase reading efficiency[set]
587 *
588 * @param ctx read / write interface definitions(ptr)
589 * @param val change the values of fast_read in reg CTRL_REG5
590 * @retval interface status (MANDATORY: return 0 -> no Error)
591 *
592 */
lis3mdl_high_part_cycle_set(stmdev_ctx_t * ctx,uint8_t val)593 int32_t lis3mdl_high_part_cycle_set(stmdev_ctx_t *ctx, uint8_t val)
594 {
595 lis3mdl_ctrl_reg5_t ctrl_reg5;
596 int32_t ret;
597
598 ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
599
600 if (ret == 0)
601 {
602 ctrl_reg5.fast_read = val;
603 ret = lis3mdl_write_reg(ctx, LIS3MDL_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
604 }
605
606 return ret;
607 }
608
609 /**
610 * @brief fast_read allows reading the high part of DATA OUT only in order
611 * to increase reading efficiency[get]
612 *
613 * @param ctx read / write interface definitions(ptr)
614 * @param val change the values of fast_read in reg CTRL_REG5(ptr)
615 * @retval interface status (MANDATORY: return 0 -> no Error)
616 *
617 */
lis3mdl_high_part_cycle_get(stmdev_ctx_t * ctx,uint8_t * val)618 int32_t lis3mdl_high_part_cycle_get(stmdev_ctx_t *ctx, uint8_t *val)
619 {
620 lis3mdl_ctrl_reg5_t ctrl_reg5;
621 int32_t ret;
622
623 ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
624 *val = (uint8_t)ctrl_reg5.fast_read;
625
626 return ret;
627 }
628
629 /**
630 * @brief Magnetic set of data available[get]
631 *
632 * @param ctx read / write interface definitions(ptr)
633 * @param val change the values of zyxda in reg STATUS_REG(ptr)
634 * @retval interface status (MANDATORY: return 0 -> no Error)
635 *
636 */
lis3mdl_mag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)637 int32_t lis3mdl_mag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
638 {
639 lis3mdl_status_reg_t status_reg;
640 int32_t ret;
641
642 ret = lis3mdl_read_reg(ctx, LIS3MDL_STATUS_REG,
643 (uint8_t *)&status_reg, 1);
644 *val = (uint8_t)status_reg.zyxda;
645
646 return ret;
647 }
648
649 /**
650 * @brief Magnetic set of data overrun[get]
651 *
652 * @param ctx read / write interface definitions(ptr)
653 * @param val change the values of zyxor in reg STATUS_REG(ptr)
654 * @retval interface status (MANDATORY: return 0 -> no Error)
655 *
656 */
lis3mdl_mag_data_ovr_get(stmdev_ctx_t * ctx,uint8_t * val)657 int32_t lis3mdl_mag_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
658 {
659 lis3mdl_status_reg_t status_reg;
660 int32_t ret;
661
662 ret = lis3mdl_read_reg(ctx, LIS3MDL_STATUS_REG,
663 (uint8_t *)&status_reg, 1);
664 *val = (uint8_t)status_reg.zyxor;
665
666 return ret;
667 }
668 /**
669 * @brief Magnetic output value[get]
670 *
671 * @param ctx read / write interface definitions(ptr)
672 * @param val buffer that stores data read(ptr)
673 * @retval interface status (MANDATORY: return 0 -> no Error)
674 *
675 */
lis3mdl_magnetic_raw_get(stmdev_ctx_t * ctx,int16_t * val)676 int32_t lis3mdl_magnetic_raw_get(stmdev_ctx_t *ctx, int16_t *val)
677 {
678 uint8_t buff[6];
679 int32_t ret;
680
681 ret = lis3mdl_read_reg(ctx, LIS3MDL_OUT_X_L, (uint8_t *) buff, 6);
682 val[0] = (int16_t)buff[1];
683 val[0] = (val[0] * 256) + (int16_t)buff[0];
684 val[1] = (int16_t)buff[3];
685 val[1] = (val[1] * 256) + (int16_t)buff[2];
686 val[2] = (int16_t)buff[5];
687 val[2] = (val[2] * 256) + (int16_t)buff[4];
688
689 return ret;
690 }
691 /**
692 * @brief Temperature output value[get]
693 *
694 * @param ctx read / write interface definitions(ptr)
695 * @param val buffer that stores data read(ptr)
696 * @retval interface status (MANDATORY: return 0 -> no Error)
697 *
698 */
lis3mdl_temperature_raw_get(stmdev_ctx_t * ctx,int16_t * val)699 int32_t lis3mdl_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
700 {
701 uint8_t buff[2];
702 int32_t ret;
703
704 ret = lis3mdl_read_reg(ctx, LIS3MDL_TEMP_OUT_L, (uint8_t *) buff, 2);
705 *val = (int16_t)buff[1];
706 *val = (*val * 256) + (int16_t)buff[0];
707
708 return ret;
709 }
710
711 /**
712 * @}
713 *
714 */
715
716 /**
717 * @defgroup LIS3MDL_Common
718 * @brief This section group common useful functions
719 * @{
720 *
721 */
722
723 /**
724 * @brief Device Who am I[get]
725 *
726 * @param ctx read / write interface definitions(ptr)
727 * @param val buffer that stores data read(ptr)
728 * @retval interface status (MANDATORY: return 0 -> no Error)
729 *
730 */
lis3mdl_device_id_get(stmdev_ctx_t * ctx,uint8_t * buff)731 int32_t lis3mdl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
732 {
733 int32_t ret;
734
735 ret = lis3mdl_read_reg(ctx, LIS3MDL_WHO_AM_I, (uint8_t *) buff, 1);
736
737 return ret;
738 }
739 /**
740 * @brief Self test[set]
741 *
742 * @param ctx read / write interface definitions(ptr)
743 * @param val change the values of st in reg CTRL_REG1
744 * @retval interface status (MANDATORY: return 0 -> no Error)
745 *
746 */
lis3mdl_self_test_set(stmdev_ctx_t * ctx,uint8_t val)747 int32_t lis3mdl_self_test_set(stmdev_ctx_t *ctx, uint8_t val)
748 {
749 lis3mdl_ctrl_reg1_t ctrl_reg1;
750 int32_t ret;
751
752 ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
753
754 if (ret == 0)
755 {
756 ctrl_reg1.st = (uint8_t)val;
757 ret = lis3mdl_write_reg(ctx, LIS3MDL_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
758 }
759
760 return ret;
761 }
762
763 /**
764 * @brief Self_test[get]
765 *
766 * @param ctx read / write interface definitions(ptr)
767 * @param val change the values of st in reg CTRL_REG1(ptr)
768 * @retval interface status (MANDATORY: return 0 -> no Error)
769 *
770 */
lis3mdl_self_test_get(stmdev_ctx_t * ctx,uint8_t * val)771 int32_t lis3mdl_self_test_get(stmdev_ctx_t *ctx, uint8_t *val)
772 {
773 lis3mdl_ctrl_reg1_t ctrl_reg1;
774 int32_t ret;
775
776 ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
777 *val = (uint8_t)ctrl_reg1.st;
778
779 return ret;
780 }
781
782 /**
783 * @brief Software reset. Restore the default values in user registers[set]
784 *
785 * @param ctx read / write interface definitions(ptr)
786 * @param val change the values of soft_rst in reg CTRL_REG2
787 * @retval interface status (MANDATORY: return 0 -> no Error)
788 *
789 */
lis3mdl_reset_set(stmdev_ctx_t * ctx,uint8_t val)790 int32_t lis3mdl_reset_set(stmdev_ctx_t *ctx, uint8_t val)
791 {
792 lis3mdl_ctrl_reg2_t ctrl_reg2;
793 int32_t ret;
794
795 ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
796
797 if (ret == 0)
798 {
799 ctrl_reg2.soft_rst = val;
800 ret = lis3mdl_write_reg(ctx, LIS3MDL_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
801 }
802
803 return ret;
804 }
805
806 /**
807 * @brief Software reset. Restore the default values in user registers[get]
808 *
809 * @param ctx read / write interface definitions(ptr)
810 * @param val change the values of soft_rst in reg CTRL_REG2(ptr)
811 * @retval interface status (MANDATORY: return 0 -> no Error)
812 *
813 */
lis3mdl_reset_get(stmdev_ctx_t * ctx,uint8_t * val)814 int32_t lis3mdl_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
815 {
816 lis3mdl_ctrl_reg2_t ctrl_reg2;
817 int32_t ret;
818
819 ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
820 *val = (uint8_t)ctrl_reg2.soft_rst;
821
822 return ret;
823 }
824
825 /**
826 * @brief Reboot memory content. Reload the calibration parameters[set]
827 *
828 * @param ctx read / write interface definitions(ptr)
829 * @param val change the values of reboot in reg CTRL_REG2
830 * @retval interface status (MANDATORY: return 0 -> no Error)
831 *
832 */
lis3mdl_boot_set(stmdev_ctx_t * ctx,uint8_t val)833 int32_t lis3mdl_boot_set(stmdev_ctx_t *ctx, uint8_t val)
834 {
835 lis3mdl_ctrl_reg2_t ctrl_reg2;
836 int32_t ret;
837
838 ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
839
840 if (ret == 0)
841 {
842 ctrl_reg2.reboot = val;
843 ret = lis3mdl_write_reg(ctx, LIS3MDL_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
844 }
845
846 return ret;
847 }
848
849 /**
850 * @brief Reboot memory content. Reload the calibration parameters[get]
851 *
852 * @param ctx read / write interface definitions(ptr)
853 * @param val change the values of reboot in reg CTRL_REG2(ptr)
854 * @retval interface status (MANDATORY: return 0 -> no Error)
855 *
856 */
lis3mdl_boot_get(stmdev_ctx_t * ctx,uint8_t * val)857 int32_t lis3mdl_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
858 {
859 lis3mdl_ctrl_reg2_t ctrl_reg2;
860 int32_t ret;
861
862 ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
863 *val = (uint8_t)ctrl_reg2.reboot;
864
865 return ret;
866 }
867
868 /**
869 * @brief Big/Little Endian data selection[set]
870 *
871 * @param ctx read / write interface definitions(ptr)
872 * @param val change the values of ble in reg CTRL_REG4
873 * @retval interface status (MANDATORY: return 0 -> no Error)
874 *
875 */
lis3mdl_data_format_set(stmdev_ctx_t * ctx,lis3mdl_ble_t val)876 int32_t lis3mdl_data_format_set(stmdev_ctx_t *ctx, lis3mdl_ble_t val)
877 {
878 lis3mdl_ctrl_reg4_t ctrl_reg4;
879 int32_t ret;
880
881 ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
882
883 if (ret == 0)
884 {
885 ctrl_reg4.ble = (uint8_t)val;
886 ret = lis3mdl_write_reg(ctx, LIS3MDL_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
887 }
888
889 return ret;
890 }
891
892 /**
893 * @brief Big/Little Endian data selection[get]
894 *
895 * @param ctx read / write interface definitions(ptr)
896 * @param val Get the values of ble in reg CTRL_REG4(ptr)
897 * @retval interface status (MANDATORY: return 0 -> no Error)
898 *
899 */
lis3mdl_data_format_get(stmdev_ctx_t * ctx,lis3mdl_ble_t * val)900 int32_t lis3mdl_data_format_get(stmdev_ctx_t *ctx, lis3mdl_ble_t *val)
901 {
902 lis3mdl_ctrl_reg4_t ctrl_reg4;
903 int32_t ret;
904
905 ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
906
907 switch (ctrl_reg4.ble)
908 {
909 case LIS3MDL_LSB_AT_LOW_ADD:
910 *val = LIS3MDL_LSB_AT_LOW_ADD;
911 break;
912
913 case LIS3MDL_MSB_AT_LOW_ADD:
914 *val = LIS3MDL_MSB_AT_LOW_ADD;
915 break;
916
917 default:
918 *val = LIS3MDL_LSB_AT_LOW_ADD;
919 break;
920 }
921
922 return ret;
923 }
924
925 /**
926 * @brief Status register[get]
927 *
928 * @param ctx read / write interface definitions(ptr)
929 * @param val Registers STATUS_REG(ptr)
930 * @retval interface status (MANDATORY: return 0 -> no Error)
931 *
932 */
lis3mdl_status_get(stmdev_ctx_t * ctx,lis3mdl_status_reg_t * val)933 int32_t lis3mdl_status_get(stmdev_ctx_t *ctx,
934 lis3mdl_status_reg_t *val)
935 {
936 return lis3mdl_read_reg(ctx, LIS3MDL_STATUS_REG, (uint8_t *) val, 1);
937 }
938 /**
939 * @}
940 *
941 */
942
943 /**
944 * @defgroup LIS3MDL_interrupts
945 * @brief This section group all the functions that manage interrupts
946 * @{
947 *
948 */
949
950 /**
951 * @brief Interrupt configuration register[set]
952 *
953 * @param ctx read / write interface definitions(ptr)
954 * @param val Registers INT_CFG(ptr)
955 * @retval interface status (MANDATORY: return 0 -> no Error)
956 *
957 */
lis3mdl_int_config_set(stmdev_ctx_t * ctx,lis3mdl_int_cfg_t * val)958 int32_t lis3mdl_int_config_set(stmdev_ctx_t *ctx,
959 lis3mdl_int_cfg_t *val)
960 {
961 return lis3mdl_write_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *) val, 1);
962 }
963
964 /**
965 * @brief Interrupt configuration register[get]
966 *
967 * @param ctx read / write interface definitions(ptr)
968 * @param val Registers INT_CFG(ptr)
969 * @retval interface status (MANDATORY: return 0 -> no Error)
970 *
971 */
lis3mdl_int_config_get(stmdev_ctx_t * ctx,lis3mdl_int_cfg_t * val)972 int32_t lis3mdl_int_config_get(stmdev_ctx_t *ctx,
973 lis3mdl_int_cfg_t *val)
974 {
975 return lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *) val, 1);
976 }
977 /**
978 * @brief Interrupt enable on INT pin[set]
979 *
980 * @param ctx read / write interface definitions(ptr)
981 * @param val change the values of ien in reg INT_CFG
982 * @retval interface status (MANDATORY: return 0 -> no Error)
983 *
984 */
lis3mdl_int_generation_set(stmdev_ctx_t * ctx,uint8_t val)985 int32_t lis3mdl_int_generation_set(stmdev_ctx_t *ctx, uint8_t val)
986 {
987 lis3mdl_int_cfg_t int_cfg;
988 int32_t ret;
989
990 ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *)&int_cfg, 1);
991
992 if (ret == 0)
993 {
994 int_cfg.ien = val;
995 ret = lis3mdl_write_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *)&int_cfg, 1);
996 }
997
998 return ret;
999 }
1000
1001 /**
1002 * @brief Interrupt enable on INT pin[get]
1003 *
1004 * @param ctx read / write interface definitions(ptr)
1005 * @param val change the values of ien in reg INT_CFG(ptr)
1006 * @retval interface status (MANDATORY: return 0 -> no Error)
1007 *
1008 */
lis3mdl_int_generation_get(stmdev_ctx_t * ctx,uint8_t * val)1009 int32_t lis3mdl_int_generation_get(stmdev_ctx_t *ctx, uint8_t *val)
1010 {
1011 lis3mdl_int_cfg_t int_cfg;
1012 int32_t ret;
1013
1014 ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *)&int_cfg, 1);
1015 *val = (uint8_t)int_cfg.ien;
1016
1017 return ret;
1018 }
1019
1020 /**
1021 * @brief Interrupt request to the INT_SOURCE (25h) register
1022 * mode (pulsed / latched)[set]
1023 *
1024 * @param ctx read / write interface definitions(ptr)
1025 * @param val change the values of lir in reg INT_CFG
1026 * @retval interface status (MANDATORY: return 0 -> no Error)
1027 *
1028 */
lis3mdl_int_notification_mode_set(stmdev_ctx_t * ctx,lis3mdl_lir_t val)1029 int32_t lis3mdl_int_notification_mode_set(stmdev_ctx_t *ctx,
1030 lis3mdl_lir_t val)
1031 {
1032 lis3mdl_int_cfg_t int_cfg;
1033 int32_t ret;
1034
1035 ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *)&int_cfg, 1);
1036
1037 if (ret == 0)
1038 {
1039 int_cfg.lir = (uint8_t)val;
1040 ret = lis3mdl_write_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *)&int_cfg, 1);
1041 }
1042
1043 return ret;
1044 }
1045
1046 /**
1047 * @brief Interrupt request to the INT_SOURCE (25h) register
1048 * mode (pulsed / latched)[get]
1049 *
1050 * @param ctx read / write interface definitions(ptr)
1051 * @param val get the values of lir in reg INT_CFG(ptr)
1052 * @retval interface status (MANDATORY: return 0 -> no Error)
1053 *
1054 */
lis3mdl_int_notification_mode_get(stmdev_ctx_t * ctx,lis3mdl_lir_t * val)1055 int32_t lis3mdl_int_notification_mode_get(stmdev_ctx_t *ctx,
1056 lis3mdl_lir_t *val)
1057 {
1058 lis3mdl_int_cfg_t int_cfg;
1059 int32_t ret;
1060
1061 ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *)&int_cfg, 1);
1062
1063 switch (int_cfg.lir)
1064 {
1065 case LIS3MDL_INT_PULSED:
1066 *val = LIS3MDL_INT_PULSED;
1067 break;
1068
1069 case LIS3MDL_INT_LATCHED:
1070 *val = LIS3MDL_INT_LATCHED;
1071 break;
1072
1073 default:
1074 *val = LIS3MDL_INT_PULSED;
1075 break;
1076 }
1077
1078 return ret;
1079 }
1080
1081 /**
1082 * @brief Interrupt active-high/low[set]
1083 *
1084 * @param ctx read / write interface definitions(ptr)
1085 * @param val change the values of iea in reg INT_CFG
1086 * @retval interface status (MANDATORY: return 0 -> no Error)
1087 *
1088 */
lis3mdl_int_polarity_set(stmdev_ctx_t * ctx,lis3mdl_iea_t val)1089 int32_t lis3mdl_int_polarity_set(stmdev_ctx_t *ctx, lis3mdl_iea_t val)
1090 {
1091 lis3mdl_int_cfg_t int_cfg;
1092 int32_t ret;
1093
1094 ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *)&int_cfg, 1);
1095
1096 if (ret == 0)
1097 {
1098 int_cfg.iea = (uint8_t)val;
1099 ret = lis3mdl_write_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *)&int_cfg, 1);
1100 }
1101
1102 return ret;
1103 }
1104
1105 /**
1106 * @brief Interrupt active-high/low[get]
1107 *
1108 * @param ctx read / write interface definitions(ptr)
1109 * @param val get the values of iea in reg INT_CFG(ptr)
1110 * @retval interface status (MANDATORY: return 0 -> no Error)
1111 *
1112 */
lis3mdl_int_polarity_get(stmdev_ctx_t * ctx,lis3mdl_iea_t * val)1113 int32_t lis3mdl_int_polarity_get(stmdev_ctx_t *ctx,
1114 lis3mdl_iea_t *val)
1115 {
1116 lis3mdl_int_cfg_t int_cfg;
1117 int32_t ret;
1118
1119 ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *)&int_cfg, 1);
1120
1121 switch (int_cfg.iea)
1122 {
1123 case LIS3MDL_ACTIVE_HIGH:
1124 *val = LIS3MDL_ACTIVE_HIGH;
1125 break;
1126
1127 case LIS3MDL_ACTIVE_LOW:
1128 *val = LIS3MDL_ACTIVE_LOW;
1129 break;
1130
1131 default:
1132 *val = LIS3MDL_ACTIVE_HIGH;
1133 break;
1134 }
1135
1136 return ret;
1137 }
1138
1139 /**
1140 * @brief Enable interrupt generation on Z-axis[set]
1141 *
1142 * @param ctx read / write interface definitions(ptr)
1143 * @param val change the values of zien in reg INT_CFG
1144 * @retval interface status (MANDATORY: return 0 -> no Error)
1145 *
1146 */
lis3mdl_int_on_z_ax_set(stmdev_ctx_t * ctx,uint8_t val)1147 int32_t lis3mdl_int_on_z_ax_set(stmdev_ctx_t *ctx, uint8_t val)
1148 {
1149 lis3mdl_int_cfg_t int_cfg;
1150 int32_t ret;
1151
1152 ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *)&int_cfg, 1);
1153
1154 if (ret == 0)
1155 {
1156 int_cfg.zien = val;
1157 ret = lis3mdl_write_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *)&int_cfg, 1);
1158 }
1159
1160 return ret;
1161 }
1162
1163 /**
1164 * @brief Enable interrupt generation on Z-axis[get]
1165 *
1166 * @param ctx read / write interface definitions(ptr)
1167 * @param val change the values of zien in reg INT_CFG(ptr)
1168 * @retval interface status (MANDATORY: return 0 -> no Error)
1169 *
1170 */
lis3mdl_int_on_z_ax_get(stmdev_ctx_t * ctx,uint8_t * val)1171 int32_t lis3mdl_int_on_z_ax_get(stmdev_ctx_t *ctx, uint8_t *val)
1172 {
1173 lis3mdl_int_cfg_t int_cfg;
1174 int32_t ret;
1175
1176 ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *)&int_cfg, 1);
1177 *val = (uint8_t)int_cfg.zien;
1178
1179 return ret;
1180 }
1181
1182 /**
1183 * @brief Enable interrupt generation on Y-axis[set]
1184 *
1185 * @param ctx read / write interface definitions(ptr)
1186 * @param val change the values of yien in reg INT_CFG
1187 * @retval interface status (MANDATORY: return 0 -> no Error)
1188 *
1189 */
lis3mdl_int_on_y_ax_set(stmdev_ctx_t * ctx,uint8_t val)1190 int32_t lis3mdl_int_on_y_ax_set(stmdev_ctx_t *ctx, uint8_t val)
1191 {
1192 lis3mdl_int_cfg_t int_cfg;
1193 int32_t ret;
1194
1195 ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *)&int_cfg, 1);
1196
1197 if (ret == 0)
1198 {
1199 int_cfg.yien = val;
1200 ret = lis3mdl_write_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *)&int_cfg, 1);
1201 }
1202
1203 return ret;
1204 }
1205
1206 /**
1207 * @brief Enable interrupt generation on Y-axis[get]
1208 *
1209 * @param ctx read / write interface definitions(ptr)
1210 * @param val change the values of yien in reg INT_CFG(ptr)
1211 * @retval interface status (MANDATORY: return 0 -> no Error)
1212 *
1213 */
lis3mdl_int_on_y_ax_get(stmdev_ctx_t * ctx,uint8_t * val)1214 int32_t lis3mdl_int_on_y_ax_get(stmdev_ctx_t *ctx, uint8_t *val)
1215 {
1216 lis3mdl_int_cfg_t int_cfg;
1217 int32_t ret;
1218
1219 ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *)&int_cfg, 1);
1220 *val = (uint8_t)int_cfg.yien;
1221
1222 return ret;
1223 }
1224
1225 /**
1226 * @brief Enable interrupt generation on X-axis[set]
1227 *
1228 * @param ctx read / write interface definitions(ptr)
1229 * @param val change the values of xien in reg INT_CFG
1230 * @retval interface status (MANDATORY: return 0 -> no Error)
1231 *
1232 */
lis3mdl_int_on_x_ax_set(stmdev_ctx_t * ctx,uint8_t val)1233 int32_t lis3mdl_int_on_x_ax_set(stmdev_ctx_t *ctx, uint8_t val)
1234 {
1235 lis3mdl_int_cfg_t int_cfg;
1236 int32_t ret;
1237
1238 ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *)&int_cfg, 1);
1239
1240 if (ret == 0)
1241 {
1242 int_cfg.xien = val;
1243 ret = lis3mdl_write_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *)&int_cfg, 1);
1244 }
1245
1246 return ret;
1247 }
1248
1249 /**
1250 * @brief Enable interrupt generation on X-axis[get]
1251 *
1252 * @param ctx read / write interface definitions(ptr)
1253 * @param val change the values of xien in reg INT_CFG(ptr)
1254 * @retval interface status (MANDATORY: return 0 -> no Error)
1255 *
1256 */
lis3mdl_int_on_x_ax_get(stmdev_ctx_t * ctx,uint8_t * val)1257 int32_t lis3mdl_int_on_x_ax_get(stmdev_ctx_t *ctx, uint8_t *val)
1258 {
1259 lis3mdl_int_cfg_t int_cfg;
1260 int32_t ret;
1261
1262 ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *)&int_cfg, 1);
1263 *val = (uint8_t)int_cfg.xien;
1264
1265 return ret;
1266 }
1267
1268 /**
1269 * @brief Interrupt source register[get]
1270 *
1271 * @param ctx read / write interface definitions(ptr)
1272 * @param val register INT_SRC(ptr)
1273 * @retval interface status (MANDATORY: return 0 -> no Error)
1274 *
1275 */
lis3mdl_int_source_get(stmdev_ctx_t * ctx,lis3mdl_int_src_t * val)1276 int32_t lis3mdl_int_source_get(stmdev_ctx_t *ctx,
1277 lis3mdl_int_src_t *val)
1278 {
1279 return lis3mdl_read_reg(ctx, LIS3MDL_INT_SRC, (uint8_t *) val, 1);
1280 }
1281
1282 /**
1283 * @brief Interrupt active flag[get]
1284 *
1285 * @param ctx read / write interface definitions(ptr)
1286 * @param val change the values of int in reg INT_SRC(ptr)
1287 * @retval interface status (MANDATORY: return 0 -> no Error)
1288 *
1289 */
lis3mdl_interrupt_event_flag_get(stmdev_ctx_t * ctx,uint8_t * val)1290 int32_t lis3mdl_interrupt_event_flag_get(stmdev_ctx_t *ctx,
1291 uint8_t *val)
1292 {
1293 lis3mdl_int_src_t int_src;
1294 int32_t ret;
1295
1296 ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_SRC, (uint8_t *)&int_src, 1);
1297 *val = (uint8_t)int_src.int_;
1298
1299 return ret;
1300 }
1301
1302 /**
1303 * @brief Internal measurement range overflow on magnetic value[get]
1304 *
1305 * @param ctx read / write interface definitions(ptr)
1306 * @param val change the values of mroi in reg INT_SRC(ptr)
1307 * @retval interface status (MANDATORY: return 0 -> no Error)
1308 *
1309 */
lis3mdl_int_mag_over_range_flag_get(stmdev_ctx_t * ctx,uint8_t * val)1310 int32_t lis3mdl_int_mag_over_range_flag_get(stmdev_ctx_t *ctx,
1311 uint8_t *val)
1312 {
1313 lis3mdl_int_src_t int_src;
1314 int32_t ret;
1315
1316 ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_SRC, (uint8_t *)&int_src, 1);
1317 *val = (uint8_t)int_src.mroi;
1318
1319 return ret;
1320 }
1321
1322 /**
1323 * @brief Value on Z-axis exceeds the threshold on the negative side.[get]
1324 *
1325 * @param ctx read / write interface definitions(ptr)
1326 * @param val change the values of nth_z in reg INT_SRC(ptr)
1327 * @retval interface status (MANDATORY: return 0 -> no Error)
1328 *
1329 */
lis3mdl_int_neg_z_flag_get(stmdev_ctx_t * ctx,uint8_t * val)1330 int32_t lis3mdl_int_neg_z_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
1331 {
1332 lis3mdl_int_src_t int_src;
1333 int32_t ret;
1334
1335 ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_SRC, (uint8_t *)&int_src, 1);
1336 *val = (uint8_t)int_src.nth_z;
1337
1338 return ret;
1339 }
1340
1341 /**
1342 * @brief Value on Y-axis exceeds the threshold on the negative side[get]
1343 *
1344 * @param ctx read / write interface definitions(ptr)
1345 * @param val change the values of nth_y in reg INT_SRC(ptr)
1346 * @retval interface status (MANDATORY: return 0 -> no Error)
1347 *
1348 */
lis3mdl_int_neg_y_flag_get(stmdev_ctx_t * ctx,uint8_t * val)1349 int32_t lis3mdl_int_neg_y_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
1350 {
1351 lis3mdl_int_src_t int_src;
1352 int32_t ret;
1353
1354 ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_SRC, (uint8_t *)&int_src, 1);
1355 *val = (uint8_t)int_src.nth_y;
1356
1357 return ret;
1358 }
1359 /**
1360 * @brief Value on X-axis exceeds the threshold on the negative side[get]
1361 *
1362 * @param ctx read / write interface definitions(ptr)
1363 * @param val change the values of nth_x in reg INT_SRC(ptr)
1364 * @retval interface status (MANDATORY: return 0 -> no Error)
1365 *
1366 */
lis3mdl_int_neg_x_flag_get(stmdev_ctx_t * ctx,uint8_t * val)1367 int32_t lis3mdl_int_neg_x_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
1368 {
1369 lis3mdl_int_src_t int_src;
1370 int32_t ret;
1371
1372 ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_SRC, (uint8_t *)&int_src, 1);
1373 *val = (uint8_t)int_src.nth_x;
1374
1375 return ret;
1376 }
1377 /**
1378 * @brief Value on Z-axis exceeds the threshold on the positive side[get]
1379 *
1380 * @param ctx read / write interface definitions(ptr)
1381 * @param val change the values of pth_z in reg INT_SRC(ptr)
1382 * @retval interface status (MANDATORY: return 0 -> no Error)
1383 *
1384 */
lis3mdl_int_pos_z_flag_get(stmdev_ctx_t * ctx,uint8_t * val)1385 int32_t lis3mdl_int_pos_z_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
1386 {
1387 lis3mdl_int_src_t int_src;
1388 int32_t ret;
1389
1390 ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_SRC, (uint8_t *)&int_src, 1);
1391 *val = (uint8_t)int_src.pth_z;
1392
1393 return ret;
1394 }
1395 /**
1396 * @brief Value on Y-axis exceeds the threshold on the positive side[get]
1397 *
1398 * @param ctx read / write interface definitions(ptr)
1399 * @param val change the values of pth_y in reg INT_SRC(ptr)
1400 * @retval interface status (MANDATORY: return 0 -> no Error)
1401 *
1402 */
lis3mdl_int_pos_y_flag_get(stmdev_ctx_t * ctx,uint8_t * val)1403 int32_t lis3mdl_int_pos_y_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
1404 {
1405 lis3mdl_int_src_t int_src;
1406 int32_t ret;
1407
1408 ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_SRC, (uint8_t *)&int_src, 1);
1409 *val = (uint8_t)int_src.pth_y;
1410
1411 return ret;
1412 }
1413 /**
1414 * @brief Value on X-axis exceeds the threshold on the positive side[get]
1415 *
1416 * @param ctx read / write interface definitions(ptr)
1417 * @param val change the values of pth_x in reg INT_SRC(ptr)
1418 * @retval interface status (MANDATORY: return 0 -> no Error)
1419 *
1420 */
lis3mdl_int_pos_x_flag_get(stmdev_ctx_t * ctx,uint8_t * val)1421 int32_t lis3mdl_int_pos_x_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
1422 {
1423 lis3mdl_int_src_t int_src;
1424 int32_t ret;
1425
1426 ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_SRC, (uint8_t *)&int_src, 1);
1427 *val = (uint8_t)int_src.pth_x;
1428
1429 return ret;
1430 }
1431 /**
1432 * @brief User-defined threshold value for pressure interrupt event[set]
1433 *
1434 * @param ctx read / write interface definitions(ptr)
1435 * @param buff buffer that contains data to write(ptr)
1436 * @retval interface status (MANDATORY: return 0 -> no Error)
1437 *
1438 */
lis3mdl_int_threshold_set(stmdev_ctx_t * ctx,uint16_t val)1439 int32_t lis3mdl_int_threshold_set(stmdev_ctx_t *ctx, uint16_t val)
1440 {
1441 uint8_t buff[2];
1442 int32_t ret;
1443
1444 buff[1] = (uint8_t)(val / 256U);
1445 buff[0] = (uint8_t)(val - (buff[1] * 256U));
1446 ret = lis3mdl_write_reg(ctx, LIS3MDL_INT_THS_L, buff, 2);
1447
1448 return ret;
1449 }
1450
1451 /**
1452 * @brief User-defined threshold value for pressure interrupt event[get]
1453 *
1454 * @param ctx read / write interface definitions(ptr)
1455 * @param buff buffer that stores data read(ptr)
1456 * @retval interface status (MANDATORY: return 0 -> no Error)
1457 *
1458 */
lis3mdl_int_threshold_get(stmdev_ctx_t * ctx,uint16_t * val)1459 int32_t lis3mdl_int_threshold_get(stmdev_ctx_t *ctx, uint16_t *val)
1460 {
1461 uint8_t buff[2];
1462 int32_t ret;
1463
1464 ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_THS_L, buff, 2);
1465 *val = buff[1];
1466 *val = (*val * 256U) + buff[0];
1467
1468 return ret;
1469 }
1470
1471 /**
1472 * @}
1473 *
1474 */
1475
1476 /**
1477 * @defgroup LIS3MDL_Serial_Interface
1478 * @brief This section group all the functions concerning
1479 * serial interface management
1480 * @{
1481 *
1482 */
1483
1484 /**
1485 * @brief SPI Serial Interface Mode selection[set]
1486 *
1487 * @param ctx read / write interface definitions(ptr)
1488 * @param val change the values of sim in reg CTRL_REG3
1489 * @retval interface status (MANDATORY: return 0 -> no Error)
1490 *
1491 */
lis3mdl_spi_mode_set(stmdev_ctx_t * ctx,lis3mdl_sim_t val)1492 int32_t lis3mdl_spi_mode_set(stmdev_ctx_t *ctx, lis3mdl_sim_t val)
1493 {
1494 lis3mdl_ctrl_reg3_t ctrl_reg3;
1495 int32_t ret;
1496
1497 ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
1498
1499 if (ret == 0)
1500 {
1501 ctrl_reg3.sim = (uint8_t)val;
1502 ret = lis3mdl_write_reg(ctx, LIS3MDL_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
1503 }
1504
1505 return ret;
1506 }
1507
1508 /**
1509 * @brief SPI Serial Interface Mode selection[get]
1510 *
1511 * @param ctx read / write interface definitions(ptr)
1512 * @param val get the values of sim in reg CTRL_REG3(ptr)
1513 * @retval interface status (MANDATORY: return 0 -> no Error)
1514 *
1515 */
lis3mdl_spi_mode_get(stmdev_ctx_t * ctx,lis3mdl_sim_t * val)1516 int32_t lis3mdl_spi_mode_get(stmdev_ctx_t *ctx, lis3mdl_sim_t *val)
1517 {
1518 lis3mdl_ctrl_reg3_t ctrl_reg3;
1519 int32_t ret;
1520
1521 ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
1522
1523 switch (ctrl_reg3.sim)
1524 {
1525 case LIS3MDL_SPI_4_WIRE:
1526 *val = LIS3MDL_SPI_4_WIRE;
1527 break;
1528
1529 case LIS3MDL_SPI_3_WIRE:
1530 *val = LIS3MDL_SPI_3_WIRE;
1531 break;
1532
1533 default:
1534 *val = LIS3MDL_SPI_4_WIRE;
1535 break;
1536 }
1537
1538 return ret;
1539 }
1540
1541 /**
1542 * @}
1543 *
1544 */
1545
1546 /**
1547 * @}
1548 *
1549 */
1550
1551 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1552
