1 /*
2 ******************************************************************************
3 * @file lis2duxs12_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LIS2DUXS12 driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lis2duxs12_reg.h"
21
22 /**
23 * @defgroup LIS2DUXS12
24 * @brief This file provides a set of functions needed to drive the
25 * lis2duxs12 sensor.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup LIS2DUXS12_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lis2duxs12_read_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lis2duxs12_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
50 uint16_t len)
51 {
52 int32_t ret;
53 ret = ctx->read_reg(ctx->handle, reg, data, len);
54 return ret;
55 }
56
57 /**
58 * @brief Write generic device register
59 *
60 * @param ctx read / write interface definitions(ptr)
61 * @param reg register to write
62 * @param data pointer to data to write in register reg(ptr)
63 * @param len number of consecutive register to write
64 * @retval interface status (MANDATORY: return 0 -> no Error)
65 *
66 */
lis2duxs12_write_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)67 int32_t __weak lis2duxs12_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
68 uint16_t len)
69 {
70 int32_t ret;
71 ret = ctx->write_reg(ctx->handle, reg, data, len);
72 return ret;
73 }
74
75 /**
76 * @}
77 *
78 */
79
80 /**
81 * @defgroup LIS2DUXS12_Sensitivity
82 * @brief These functions convert raw-data into engineering units.
83 * @{
84 *
85 */
86
lis2duxs12_from_fs2g_to_mg(int16_t lsb)87 float_t lis2duxs12_from_fs2g_to_mg(int16_t lsb)
88 {
89 return (float_t)lsb * 0.061f;
90 }
91
lis2duxs12_from_fs4g_to_mg(int16_t lsb)92 float_t lis2duxs12_from_fs4g_to_mg(int16_t lsb)
93 {
94 return (float_t)lsb * 0.122f;
95 }
96
lis2duxs12_from_fs8g_to_mg(int16_t lsb)97 float_t lis2duxs12_from_fs8g_to_mg(int16_t lsb)
98 {
99 return (float_t)lsb * 0.244f;
100 }
101
lis2duxs12_from_fs16g_to_mg(int16_t lsb)102 float_t lis2duxs12_from_fs16g_to_mg(int16_t lsb)
103 {
104 return (float_t)lsb * 0.488f;
105 }
106
lis2duxs12_from_lsb_to_celsius(int16_t lsb)107 float_t lis2duxs12_from_lsb_to_celsius(int16_t lsb)
108 {
109 return ((float_t)lsb / 355.5f) + 25.0f;
110 }
111
112 /**
113 * @}
114 *
115 */
116
117 /**
118 * @defgroup Common
119 * @brief Common
120 * @{/
121 *
122 */
123 /**
124 * @brief Device ID.[get]
125 *
126 * @param ctx read / write interface definitions
127 * @param val Device ID.
128 * @retval interface status (MANDATORY: return 0 -> no Error)
129 *
130 */
lis2duxs12_device_id_get(stmdev_ctx_t * ctx,uint8_t * val)131 int32_t lis2duxs12_device_id_get(stmdev_ctx_t *ctx, uint8_t *val)
132 {
133 int32_t ret;
134
135 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_WHO_AM_I, val, 1);
136
137 return ret;
138 }
139
140 /**
141 * @brief Configures the bus operating mode.[get]
142 *
143 * @param ctx communication interface handler.(ptr)
144 * @param val configures the bus operating mode.(ptr)
145 * @retval interface status (MANDATORY: return 0 -> no Error)
146 *
147 */
lis2duxs12_init_set(stmdev_ctx_t * ctx,lis2duxs12_init_t val)148 int32_t lis2duxs12_init_set(stmdev_ctx_t *ctx, lis2duxs12_init_t val)
149 {
150 lis2duxs12_ctrl1_t ctrl1;
151 lis2duxs12_ctrl4_t ctrl4;
152 int32_t ret = 0;
153
154 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t*)&ctrl1, 1);
155 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t*)&ctrl4, 1);
156 switch (val) {
157 case LIS2DUXS12_BOOT:
158 ctrl4.boot = PROPERTY_ENABLE;
159 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t*)&ctrl4, 1);
160 break;
161 case LIS2DUXS12_RESET:
162
163 ctrl1.sw_reset = PROPERTY_ENABLE;
164 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t*)&ctrl1, 1);
165 break;
166 case LIS2DUXS12_SENSOR_ONLY_ON:
167 /* no embedded funcs are used */
168 ctrl4.emb_func_en = PROPERTY_DISABLE;
169 ctrl4.bdu = PROPERTY_ENABLE;
170 ctrl1.if_add_inc = PROPERTY_ENABLE;
171 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t*)&ctrl4, 1);
172 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t*)&ctrl1, 1);
173 break;
174 case LIS2DUXS12_SENSOR_EMB_FUNC_ON:
175 /* complete configuration is used */
176 ctrl4.emb_func_en = PROPERTY_ENABLE;
177 ctrl4.bdu = PROPERTY_ENABLE;
178 ctrl1.if_add_inc = PROPERTY_ENABLE;
179 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t*)&ctrl4, 1);
180 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t*)&ctrl1, 1);
181 break;
182 default:
183 ctrl1.sw_reset = PROPERTY_ENABLE;
184 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t*)&ctrl1, 1);
185 break;
186 }
187 return ret;
188 }
189
190 /**
191 * @brief Get the status of the device.[get]
192 *
193 * @param ctx communication interface handler.(ptr)
194 * @param val the status of the device.(ptr)
195 * @retval interface status (MANDATORY: return 0 -> no Error)
196 *
197 */
lis2duxs12_status_get(stmdev_ctx_t * ctx,lis2duxs12_status_t * val)198 int32_t lis2duxs12_status_get(stmdev_ctx_t *ctx, lis2duxs12_status_t *val)
199 {
200 lis2duxs12_status_register_t status_register;
201 lis2duxs12_ctrl1_t ctrl1;
202 lis2duxs12_ctrl4_t ctrl4;
203 int32_t ret;
204
205 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_STATUS,
206 (uint8_t*)&status_register, 1);
207 if (ret == 0) {
208 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t*)&ctrl1, 1);
209 }
210 if (ret == 0) {
211 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t*)&ctrl4, 1);
212 }
213
214 val->sw_reset = ctrl1.sw_reset;
215 val->boot = ctrl4.boot;
216 val->drdy = status_register.drdy;
217
218 return ret;
219 }
220
221 /**
222 * @brief Get the status of the embedded funcs.[get]
223 *
224 * @param ctx communication interface handler.(ptr)
225 * @param val the status of the embedded funcs.(ptr)
226 * @retval interface status (MANDATORY: return 0 -> no Error)
227 *
228 */
lis2duxs12_embedded_status_get(stmdev_ctx_t * ctx,lis2duxs12_embedded_status_t * val)229 int32_t lis2duxs12_embedded_status_get(stmdev_ctx_t *ctx, lis2duxs12_embedded_status_t *val)
230 {
231 lis2duxs12_emb_func_status_t status;
232 int32_t ret;
233
234 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
235 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_STATUS, (uint8_t*)&status, 1);
236 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
237
238 val->is_step_det = status.is_step_det;
239 val->is_tilt = status.is_tilt;
240 val->is_sigmot = status.is_sigmot;
241
242 return ret;
243 }
244
245 /**
246 * @brief Enables pulsed data-ready mode (~75 us).[set]
247 *
248 * @param ctx read / write interface definitions
249 * @param val DRDY_LATCHED, DRDY_PULSED,
250 * @retval interface status (MANDATORY: return 0 -> no Error)
251 *
252 */
lis2duxs12_data_ready_mode_set(stmdev_ctx_t * ctx,lis2duxs12_data_ready_mode_t val)253 int32_t lis2duxs12_data_ready_mode_set(stmdev_ctx_t *ctx, lis2duxs12_data_ready_mode_t val)
254 {
255 lis2duxs12_ctrl1_t ctrl1;
256 int32_t ret;
257
258 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1);
259
260 if (ret == 0)
261 {
262 ctrl1.drdy_pulsed = ((uint8_t)val & 0x1U);
263 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1);
264 }
265
266 return ret;
267 }
268
269 /**
270 * @brief Enables pulsed data-ready mode (~75 us).[get]
271 *
272 * @param ctx read / write interface definitions
273 * @param val DRDY_LATCHED, DRDY_PULSED,
274 * @retval interface status (MANDATORY: return 0 -> no Error)
275 *
276 */
lis2duxs12_data_ready_mode_get(stmdev_ctx_t * ctx,lis2duxs12_data_ready_mode_t * val)277 int32_t lis2duxs12_data_ready_mode_get(stmdev_ctx_t *ctx, lis2duxs12_data_ready_mode_t *val)
278 {
279 lis2duxs12_ctrl1_t ctrl1;
280 int32_t ret;
281
282 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1);
283
284 switch ((ctrl1.drdy_pulsed))
285 {
286 case LIS2DUXS12_DRDY_LATCHED:
287 *val = LIS2DUXS12_DRDY_LATCHED;
288 break;
289
290 case LIS2DUXS12_DRDY_PULSED:
291 *val = LIS2DUXS12_DRDY_PULSED;
292 break;
293
294 default:
295 *val = LIS2DUXS12_DRDY_LATCHED;
296 break;
297 }
298 return ret;
299 }
300
301 /**
302 * @brief Sensor mode.[set]
303 *
304 * @param ctx communication interface handler.(ptr)
305 * @param val set the sensor FS and ODR.(ptr)
306 * @retval interface status (MANDATORY: return 0 -> no Error)
307 *
308 */
lis2duxs12_mode_set(stmdev_ctx_t * ctx,lis2duxs12_md_t * val)309 int32_t lis2duxs12_mode_set(stmdev_ctx_t *ctx, lis2duxs12_md_t *val)
310 {
311 lis2duxs12_ctrl3_t ctrl3;
312 lis2duxs12_ctrl5_t ctrl5;
313 int32_t ret;
314
315 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL5, (uint8_t*)&ctrl5, 1);
316
317 ctrl5.odr = (uint8_t)val->odr & 0xFU;
318 ctrl5.fs = (uint8_t)val->fs;
319 ctrl5.bw = (uint8_t)val->bw;
320
321 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL3, (uint8_t*)&ctrl3, 1);
322
323 ctrl3.hp_en = (((uint8_t)val->odr & 0x10U) != 0U) ? 1U : 0U;
324
325 if (ret == 0) {
326 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL5, (uint8_t*)&ctrl5, 1);
327 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL3, (uint8_t*)&ctrl3, 1);
328 }
329
330 return ret;
331 }
332
333 /**
334 * @brief Sensor mode.[get]
335 *
336 * @param ctx communication interface handler.(ptr)
337 * @param val get the sensor FS and ODR.(ptr)
338 * @retval interface status (MANDATORY: return 0 -> no Error)
339 *
340 */
lis2duxs12_mode_get(stmdev_ctx_t * ctx,lis2duxs12_md_t * val)341 int32_t lis2duxs12_mode_get(stmdev_ctx_t *ctx, lis2duxs12_md_t *val)
342 {
343 lis2duxs12_ctrl3_t ctrl3;
344 lis2duxs12_ctrl5_t ctrl5;
345 int32_t ret;
346
347 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL5, (uint8_t*)&ctrl5, 1);
348 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL3, (uint8_t*)&ctrl3, 1);
349
350 switch (ctrl5.odr) {
351 case LIS2DUXS12_OFF:
352 val->odr = LIS2DUXS12_OFF;
353 break;
354 case LIS2DUXS12_1Hz5_ULP:
355 val->odr = LIS2DUXS12_1Hz5_ULP;
356 break;
357 case LIS2DUXS12_3Hz_ULP:
358 val->odr = LIS2DUXS12_3Hz_ULP;
359 break;
360 case LIS2DUXS12_25Hz_ULP:
361 val->odr = LIS2DUXS12_25Hz_ULP;
362 break;
363 case LIS2DUXS12_6Hz:
364 val->odr = LIS2DUXS12_6Hz;
365 break;
366 case LIS2DUXS12_12Hz5:
367 val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUXS12_12Hz5_HP : LIS2DUXS12_12Hz5;
368 break;
369 case LIS2DUXS12_25Hz:
370 val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUXS12_25Hz_HP : LIS2DUXS12_25Hz;
371 break;
372 case LIS2DUXS12_50Hz:
373 val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUXS12_50Hz_HP : LIS2DUXS12_50Hz;
374 break;
375 case LIS2DUXS12_100Hz:
376 val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUXS12_100Hz_HP : LIS2DUXS12_100Hz;
377 break;
378 case LIS2DUXS12_200Hz:
379 val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUXS12_200Hz_HP : LIS2DUXS12_200Hz;
380 break;
381 case LIS2DUXS12_400Hz:
382 val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUXS12_400Hz_HP : LIS2DUXS12_400Hz;
383 break;
384 case LIS2DUXS12_800Hz:
385 val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUXS12_800Hz_HP : LIS2DUXS12_800Hz;
386 break;
387 case LIS2DUXS12_TRIG_PIN:
388 val->odr = LIS2DUXS12_TRIG_PIN;
389 break;
390 case LIS2DUXS12_TRIG_SW:
391 val->odr = LIS2DUXS12_TRIG_SW;
392 break;
393 default:
394 val->odr = LIS2DUXS12_OFF;
395 break;
396 }
397
398 switch (ctrl5.fs) {
399 case LIS2DUXS12_2g:
400 val->fs = LIS2DUXS12_2g;
401 break;
402 case LIS2DUXS12_4g:
403 val->fs = LIS2DUXS12_4g;
404 break;
405 case LIS2DUXS12_8g:
406 val->fs = LIS2DUXS12_8g;
407 break;
408 case LIS2DUXS12_16g:
409 val->fs = LIS2DUXS12_16g;
410 break;
411 default:
412 val->fs = LIS2DUXS12_2g;
413 break;
414 }
415
416 switch (ctrl5.bw) {
417 case LIS2DUXS12_ODR_div_2:
418 val->bw = LIS2DUXS12_ODR_div_2;
419 break;
420 case LIS2DUXS12_ODR_div_4:
421 val->bw = LIS2DUXS12_ODR_div_4;
422 break;
423 case LIS2DUXS12_ODR_div_8:
424 val->bw = LIS2DUXS12_ODR_div_8;
425 break;
426 case LIS2DUXS12_ODR_div_16:
427 val->bw = LIS2DUXS12_ODR_div_16;
428 break;
429 default:
430 val->bw = LIS2DUXS12_ODR_div_2;
431 break;
432 }
433
434 return ret;
435 }
436
437 /**
438 * @brief Enter deep power down[set]
439 *
440 * @param ctx read / write interface definitions
441 * @param val Enter deep power down
442 * @retval interface status (MANDATORY: return 0 -> no Error)
443 *
444 */
lis2duxs12_enter_deep_power_down(stmdev_ctx_t * ctx,uint8_t val)445 int32_t lis2duxs12_enter_deep_power_down(stmdev_ctx_t *ctx, uint8_t val)
446 {
447 lis2duxs12_sleep_t sleep;
448 int32_t ret;
449
450 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_SLEEP, (uint8_t *)&sleep, 1);
451
452 if (ret == 0)
453 {
454 sleep.deep_pd = val;
455 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_SLEEP, (uint8_t *)&sleep, 1);
456 }
457
458 return ret;
459 }
460
461 /**
462 * @brief Enter soft power down in SPI case[set]
463 *
464 * @param ctx read / write interface definitions
465 * @param val Enter soft power down in SPI case
466 * @retval interface status (MANDATORY: return 0 -> no Error)
467 *
468 */
lis2duxs12_exit_deep_power_down(stmdev_ctx_t * ctx)469 int32_t lis2duxs12_exit_deep_power_down(stmdev_ctx_t *ctx)
470 {
471 lis2duxs12_if_wake_up_t if_wake_up = {0};
472 int32_t ret;
473
474 if_wake_up.soft_pd = PROPERTY_ENABLE;
475 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_IF_WAKE_UP, (uint8_t *)&if_wake_up, 1);
476
477 return ret;
478 }
479
480 /**
481 * @brief Software trigger for One-Shot.[get]
482 *
483 * @param ctx communication interface handler.(ptr)
484 * @param md the sensor conversion parameters.(ptr)
485 * @retval interface status (MANDATORY: return 0 -> no Error)
486 *
487 */
lis2duxs12_trigger_sw(stmdev_ctx_t * ctx,lis2duxs12_md_t * md)488 int32_t lis2duxs12_trigger_sw(stmdev_ctx_t *ctx, lis2duxs12_md_t *md)
489 {
490 lis2duxs12_ctrl4_t ctrl4;
491 int32_t ret = 0;
492
493 if ( md->odr == LIS2DUXS12_TRIG_SW ) {
494 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t*)&ctrl4, 1);
495 ctrl4.soc = PROPERTY_ENABLE;
496 if (ret == 0) {
497 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t*)&ctrl4, 1);
498 }
499 }
500 return ret;
501 }
502
lis2duxs12_all_sources_get(stmdev_ctx_t * ctx,lis2duxs12_all_sources_t * val)503 int32_t lis2duxs12_all_sources_get(stmdev_ctx_t *ctx, lis2duxs12_all_sources_t *val)
504 {
505 lis2duxs12_status_register_t status;
506 int32_t ret;
507
508 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_STATUS, (uint8_t*)&status, 1);
509 val->drdy = status.drdy;
510
511 if (ret == 0 && status.int_global == 0x1U)
512 {
513 lis2duxs12_wake_up_src_t wu_src;
514 lis2duxs12_tap_src_t tap_src;
515 lis2duxs12_sixd_src_t sixd_src;
516
517 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_SIXD_SRC, (uint8_t*)&sixd_src, 1);
518 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_WAKE_UP_SRC, (uint8_t*)&wu_src, 1);
519 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_SRC, (uint8_t*)&tap_src, 1);
520
521 val->six_d = sixd_src.d6d_ia;
522 val->six_d_xl = sixd_src.xl;
523 val->six_d_xh = sixd_src.xh;
524 val->six_d_yl = sixd_src.yl;
525 val->six_d_yh = sixd_src.yh;
526 val->six_d_zl = sixd_src.zl;
527 val->six_d_zh = sixd_src.zh;
528
529 val->wake_up = wu_src.wu_ia;
530 val->wake_up_z = wu_src.z_wu;
531 val->wake_up_y = wu_src.y_wu;
532 val->wake_up_x = wu_src.x_wu;
533 val->free_fall = wu_src.ff_ia;
534 val->sleep_change = wu_src.sleep_change_ia;
535 val->sleep_state = wu_src.sleep_state;
536
537 val->single_tap = tap_src.single_tap_ia;
538 val->double_tap = tap_src.double_tap_ia;
539 val->triple_tap = tap_src.triple_tap_ia;
540 }
541
542 return ret;
543 }
544
545 /**
546 * @brief Accelerometer data.[get]
547 *
548 * @param ctx communication interface handler.(ptr)
549 * @param md the sensor conversion parameters.(ptr)
550 * @param data data retrived from the sensor.(ptr)
551 * @retval interface status (MANDATORY: return 0 -> no Error)
552 *
553 */
lis2duxs12_xl_data_get(stmdev_ctx_t * ctx,lis2duxs12_md_t * md,lis2duxs12_xl_data_t * data)554 int32_t lis2duxs12_xl_data_get(stmdev_ctx_t *ctx, lis2duxs12_md_t *md,
555 lis2duxs12_xl_data_t *data)
556 {
557 uint8_t buff[6];
558 int32_t ret;
559 uint8_t i;
560 uint8_t j;
561
562 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_OUT_X_L, buff, 6);
563
564 /* acceleration conversion */
565 j = 0U;
566 for (i = 0U; i < 3U; i++) {
567 data->raw[i] = (int16_t)buff[j+1U];
568 data->raw[i] = (data->raw[i] * 256) + (int16_t) buff[j];
569 j+=2U;
570 switch ( md->fs ) {
571 case LIS2DUXS12_2g:
572 data->mg[i] =lis2duxs12_from_fs2g_to_mg(data->raw[i]);
573 break;
574 case LIS2DUXS12_4g:
575 data->mg[i] =lis2duxs12_from_fs4g_to_mg(data->raw[i]);
576 break;
577 case LIS2DUXS12_8g:
578 data->mg[i] =lis2duxs12_from_fs8g_to_mg(data->raw[i]);
579 break;
580 case LIS2DUXS12_16g:
581 data->mg[i] =lis2duxs12_from_fs16g_to_mg(data->raw[i]);
582 break;
583 default:
584 data->mg[i] = 0.0f;
585 break;
586 }
587 }
588
589 return ret;
590 }
591
592 /**
593 * @brief OUTT data.[get]
594 *
595 * @param ctx communication interface handler.(ptr)
596 * @param md the sensor conversion parameters.(ptr)
597 * @param data data retrived from the sensor.(ptr)
598 * @retval interface status (MANDATORY: return 0 -> no Error)
599 *
600 */
lis2duxs12_outt_data_get(stmdev_ctx_t * ctx,lis2duxs12_md_t * md,lis2duxs12_outt_data_t * data)601 int32_t lis2duxs12_outt_data_get(stmdev_ctx_t *ctx, lis2duxs12_md_t *md,
602 lis2duxs12_outt_data_t *data)
603 {
604 uint8_t buff[2];
605 int32_t ret;
606
607 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_OUT_T_AH_QVAR_L, buff, 2);
608
609 data->heat.raw = (int16_t)buff[1U];
610 data->heat.raw = (data->heat.raw * 256) + (int16_t) buff[0];
611 /* temperature conversion */
612 data->heat.deg_c = lis2duxs12_from_lsb_to_celsius(data->heat.raw);
613
614 return ret;
615 }
616
617 /**
618 * @brief AH_QVAR data.[get]
619 *
620 * @param ctx communication interface handler.(ptr)
621 * @param md the sensor conversion parameters.(ptr)
622 * @param data data retrived from the sensor.(ptr)
623 * @retval interface status (MANDATORY: return 0 -> no Error)
624 *
625 */
lis2duxs12_ah_qvar_data_get(stmdev_ctx_t * ctx,lis2duxs12_md_t * md,lis2duxs12_ah_qvar_data_t * data)626 int32_t lis2duxs12_ah_qvar_data_get(stmdev_ctx_t *ctx, lis2duxs12_md_t *md,
627 lis2duxs12_ah_qvar_data_t *data)
628 {
629 uint8_t buff[2];
630 int32_t ret;
631
632 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_OUT_T_AH_QVAR_L, buff, 2);
633
634 data->ah_qvar = (int16_t)buff[1U];
635 data->ah_qvar = (data->ah_qvar * 256) + (int16_t) buff[0];
636
637 return ret;
638 }
639
640 /**
641 * @brief Configures the self test.[set]
642 *
643 * @param ctx communication interface handler.(ptr)
644 * @param val self test mode.(ptr)
645 * @retval interface status (MANDATORY: return 0 -> no Error)
646 *
647 */
lis2duxs12_self_test_sign_set(stmdev_ctx_t * ctx,lis2duxs12_xl_self_test_t val)648 int32_t lis2duxs12_self_test_sign_set(stmdev_ctx_t *ctx, lis2duxs12_xl_self_test_t val)
649 {
650 lis2duxs12_ctrl3_t ctrl3;
651 lis2duxs12_wake_up_dur_t wkup_dur;
652 int32_t ret;
653
654 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL3, (uint8_t*)&ctrl3, 1);
655 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_WAKE_UP_DUR, (uint8_t*)&wkup_dur, 1);
656
657 switch (val) {
658 case LIS2DUXS12_XL_ST_POSITIVE:
659 ctrl3.st_sign_x = 1;
660 ctrl3.st_sign_y = 1;
661 wkup_dur.st_sign_z = 0;
662 break;
663
664 case LIS2DUXS12_XL_ST_NEGATIVE:
665 ctrl3.st_sign_x = 0;
666 ctrl3.st_sign_y = 0;
667 wkup_dur.st_sign_z = 1;
668 break;
669
670 case LIS2DUXS12_XL_ST_DISABLE:
671 default:
672 ret = -1;
673 break;
674 }
675
676
677 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL3, (uint8_t*)&ctrl3, 1);
678 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_WAKE_UP_DUR, (uint8_t*)&wkup_dur, 1);
679
680 return ret;
681 }
682
683 /**
684 * @brief Configures the self test.[start]
685 *
686 * @param ctx communication interface handler.(ptr)
687 * @param val valid values 2 (1st step) or 1 (2nd step)
688 * @retval interface status (MANDATORY: return 0 -> no Error)
689 *
690 */
lis2duxs12_self_test_start(stmdev_ctx_t * ctx,uint8_t val)691 int32_t lis2duxs12_self_test_start(stmdev_ctx_t *ctx, uint8_t val)
692 {
693 lis2duxs12_self_test_t self_test;
694 int32_t ret;
695
696 if (val != 1U && val != 2U) {
697 return -1;
698 }
699
700 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_SELF_TEST, (uint8_t*)&self_test, 1);
701 if (ret == 0) {
702 self_test.st = (uint8_t) val;
703 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_SELF_TEST, (uint8_t*)&self_test, 1);
704 }
705 return ret;
706 }
707
708 /**
709 * @brief Configures the self test.[stop]
710 *
711 * @param ctx communication interface handler.(ptr)
712 * @retval interface status (MANDATORY: return 0 -> no Error)
713 *
714 */
lis2duxs12_self_test_stop(stmdev_ctx_t * ctx)715 int32_t lis2duxs12_self_test_stop(stmdev_ctx_t *ctx)
716 {
717 lis2duxs12_self_test_t self_test;
718 int32_t ret;
719
720 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_SELF_TEST, (uint8_t*)&self_test, 1);
721 if (ret == 0) {
722 self_test.st = 0;
723 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_SELF_TEST, (uint8_t*)&self_test, 1);
724 }
725 return ret;
726 }
727
728 /**
729 * @brief Configures I3C bus.[set]
730 *
731 * @param ctx communication interface handler.(ptr)
732 * @param val configuration params
733 * @retval interface status (MANDATORY: return 0 -> no Error)
734 *
735 */
lis2duxs12_i3c_configure_set(stmdev_ctx_t * ctx,lis2duxs12_i3c_cfg_t * val)736 int32_t lis2duxs12_i3c_configure_set(stmdev_ctx_t *ctx, lis2duxs12_i3c_cfg_t *val)
737 {
738 lis2duxs12_i3c_if_ctrl_t i3c_cfg;
739 int32_t ret;
740
741 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_I3C_IF_CTRL, (uint8_t *)&i3c_cfg, 1);
742
743 if (ret == 0)
744 {
745 i3c_cfg.bus_act_sel = (uint8_t)val->bus_act_sel;
746 i3c_cfg.dis_drstdaa = val->drstdaa_en;
747 i3c_cfg.asf_on = val->asf_on;
748 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_I3C_IF_CTRL, (uint8_t *)&i3c_cfg, 1);
749 }
750
751 return ret;
752 }
753
754 /**
755 * @brief Configures I3C bus.[get]
756 *
757 * @param ctx communication interface handler.(ptr)
758 * @param val configuration params
759 * @retval interface status (MANDATORY: return 0 -> no Error)
760 *
lis2duxs12_i3c_configure_get(stmdev_ctx_t * ctx,lis2duxs12_i3c_cfg_t * val)761 */int32_t lis2duxs12_i3c_configure_get(stmdev_ctx_t *ctx, lis2duxs12_i3c_cfg_t *val)
762 {
763 lis2duxs12_i3c_if_ctrl_t i3c_cfg;
764 int32_t ret;
765
766 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_I3C_IF_CTRL, (uint8_t *)&i3c_cfg, 1);
767
768 val->drstdaa_en = i3c_cfg.dis_drstdaa;
769 val->asf_on = i3c_cfg.asf_on;
770
771 switch (val->bus_act_sel) {
772 case LIS2DUXS12_I3C_BUS_AVAIL_TIME_20US:
773 val->bus_act_sel = LIS2DUXS12_I3C_BUS_AVAIL_TIME_20US;
774 break;
775
776 case LIS2DUXS12_I3C_BUS_AVAIL_TIME_50US:
777 val->bus_act_sel = LIS2DUXS12_I3C_BUS_AVAIL_TIME_50US;
778 break;
779
780 case LIS2DUXS12_I3C_BUS_AVAIL_TIME_1MS:
781 val->bus_act_sel = LIS2DUXS12_I3C_BUS_AVAIL_TIME_1MS;
782 break;
783
784 case LIS2DUXS12_I3C_BUS_AVAIL_TIME_25MS:
785 default:
786 val->bus_act_sel = LIS2DUXS12_I3C_BUS_AVAIL_TIME_25MS;
787 break;
788 }
789
790 return ret;
791 }
792
793 /**
794 * @brief Change memory bank.[set]
795 *
796 * @param ctx read / write interface definitions
797 * @param val MAIN_MEM_BANK, EMBED_FUNC_MEM_BANK, SENSOR_HUB_MEM_BANK, STRED_MEM_BANK,
798 * @retval interface status (MANDATORY: return 0 -> no Error)
799 *
800 */
lis2duxs12_mem_bank_set(stmdev_ctx_t * ctx,lis2duxs12_mem_bank_t val)801 int32_t lis2duxs12_mem_bank_set(stmdev_ctx_t *ctx, lis2duxs12_mem_bank_t val)
802 {
803 lis2duxs12_func_cfg_access_t func_cfg_access;
804 int32_t ret;
805
806 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
807
808 if (ret == 0)
809 {
810 func_cfg_access.emb_func_reg_access = ((uint8_t)val & 0x1U);
811 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
812 }
813
814 return ret;
815 }
816
817 /**
818 * @brief Change memory bank.[get]
819 *
820 * @param ctx read / write interface definitions
821 * @param val MAIN_MEM_BANK, EMBED_FUNC_MEM_BANK, SENSOR_HUB_MEM_BANK, STRED_MEM_BANK,
822 * @retval interface status (MANDATORY: return 0 -> no Error)
823 *
824 */
lis2duxs12_mem_bank_get(stmdev_ctx_t * ctx,lis2duxs12_mem_bank_t * val)825 int32_t lis2duxs12_mem_bank_get(stmdev_ctx_t *ctx, lis2duxs12_mem_bank_t *val)
826 {
827 lis2duxs12_func_cfg_access_t func_cfg_access;
828 int32_t ret;
829
830 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
831
832 switch ((func_cfg_access.emb_func_reg_access))
833 {
834 case LIS2DUXS12_MAIN_MEM_BANK:
835 *val = LIS2DUXS12_MAIN_MEM_BANK;
836 break;
837
838 case LIS2DUXS12_EMBED_FUNC_MEM_BANK:
839 *val = LIS2DUXS12_EMBED_FUNC_MEM_BANK;
840 break;
841
842 default:
843 *val = LIS2DUXS12_MAIN_MEM_BANK;
844 break;
845 }
846 return ret;
847 }
848
849 /**
850 * @brief Write buffer in a page.
851 *
852 * @param ctx read / write interface definitions
853 * @param address Address of page register to be written (page number in 8-bit
854 * msb, register address in 8-bit lsb).
855 * @param buf Pointer to data buffer.
856 * @param len Buffer len.
857 * @retval interface status (MANDATORY: return 0 -> no Error)
858 *
859 */
lis2duxs12_ln_pg_write(stmdev_ctx_t * ctx,uint16_t address,uint8_t * buf,uint8_t len)860 int32_t lis2duxs12_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len)
861 {
862 lis2duxs12_page_address_t page_address;
863 lis2duxs12_page_sel_t page_sel;
864 lis2duxs12_page_rw_t page_rw;
865 uint8_t msb;
866 uint8_t lsb;
867 int32_t ret;
868 uint8_t i ;
869
870 msb = ((uint8_t)(address >> 8) & 0x0FU);
871 lsb = (uint8_t)address & 0xFFU;
872
873 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
874
875 if (ret == 0)
876 {
877 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1);
878 page_rw.page_read = PROPERTY_DISABLE;
879 page_rw.page_write = PROPERTY_ENABLE;
880 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1);
881
882 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_SEL, (uint8_t *)&page_sel, 1);
883 page_sel.page_sel = msb;
884 page_sel.not_used0 = 1; // Default value
885 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_SEL, (uint8_t *)&page_sel, 1);
886
887 page_address.page_addr = lsb;
888 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_ADDRESS, (uint8_t *)&page_address, 1);
889
890 for (i = 0; ((i < len) && (ret == 0)); i++)
891 {
892 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_VALUE, &buf[i], 1);
893 lsb++;
894
895 /* Check if page wrap */
896 if (((lsb & 0xFFU) == 0x00U) && (ret == 0))
897 {
898 msb++;
899 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_SEL, (uint8_t *)&page_sel, 1);
900 page_sel.page_sel = msb;
901 page_sel.not_used0 = 1; // Default value
902 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_SEL, (uint8_t *)&page_sel, 1);
903 }
904 }
905
906 page_sel.page_sel = 0;
907 page_sel.not_used0 = 1;// Default value
908 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_SEL, (uint8_t *)&page_sel, 1);
909
910 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1);
911 page_rw.page_read = PROPERTY_DISABLE;
912 page_rw.page_write = PROPERTY_DISABLE;
913 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1);
914 }
915
916 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
917
918 return ret;
919 }
920
921 /**
922 * @brief Read buffer in a page.
923 *
924 * @param ctx read / write interface definitions
925 * @param address Address of page register to be read (page number in 8-bit
926 * msb, register address in 8-bit lsb).
927 * @param buf Pointer to data buffer.
928 * @param len Buffer len.
929 * @retval interface status (MANDATORY: return 0 -> no Error)
930 *
931 */
lis2duxs12_ln_pg_read(stmdev_ctx_t * ctx,uint16_t address,uint8_t * buf,uint8_t len)932 int32_t lis2duxs12_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len)
933 {
934 lis2duxs12_page_address_t page_address;
935 lis2duxs12_page_sel_t page_sel;
936 lis2duxs12_page_rw_t page_rw;
937 uint8_t msb;
938 uint8_t lsb;
939 int32_t ret;
940 uint8_t i ;
941
942 msb = ((uint8_t)(address >> 8) & 0x0FU);
943 lsb = (uint8_t)address & 0xFFU;
944
945 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
946
947 if (ret == 0)
948 {
949 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1);
950 page_rw.page_read = PROPERTY_ENABLE;
951 page_rw.page_write = PROPERTY_DISABLE;
952 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1);
953
954 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_SEL, (uint8_t *)&page_sel, 1);
955 page_sel.page_sel = msb;
956 page_sel.not_used0 = 1; // Default value
957 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_SEL, (uint8_t *)&page_sel, 1);
958
959 page_address.page_addr = lsb;
960 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_ADDRESS, (uint8_t *)&page_address, 1);
961
962 for (i = 0; ((i < len) && (ret == 0)); i++)
963 {
964 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_VALUE, &buf[i], 1);
965 lsb++;
966
967 /* Check if page wrap */
968 if (((lsb & 0xFFU) == 0x00U) && (ret == 0))
969 {
970 msb++;
971 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_SEL, (uint8_t *)&page_sel, 1);
972 page_sel.page_sel = msb;
973 page_sel.not_used0 = 1; // Default value
974 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_SEL, (uint8_t *)&page_sel, 1);
975 }
976 }
977
978 page_sel.page_sel = 0;
979 page_sel.not_used0 = 1;// Default value
980 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_SEL, (uint8_t *)&page_sel, 1);
981
982 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1);
983 page_rw.page_read = PROPERTY_DISABLE;
984 page_rw.page_write = PROPERTY_DISABLE;
985 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1);
986 }
987
988 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
989
990 return ret;
991 }
992
993 /**
994 * @}
995 *
996 */
997
998 /**
999 * @defgroup Interrupt PINs
1000 * @brief Interrupt PINs
1001 * @{/
1002 *
1003 */
1004
1005 /**
1006 * @brief Electrical pin configuration.[set]
1007 *
1008 * @param ctx read / write interface definitions
1009 * @param val the electrical settings for the configurable pins.(ptr)
1010 * @retval interface status (MANDATORY: return 0 -> no Error)
1011 *
1012 */
lis2duxs12_pin_conf_set(stmdev_ctx_t * ctx,lis2duxs12_pin_conf_t * val)1013 int32_t lis2duxs12_pin_conf_set(stmdev_ctx_t *ctx, lis2duxs12_pin_conf_t *val)
1014 {
1015 lis2duxs12_pin_ctrl_t pin_ctrl;
1016 int32_t ret;
1017
1018 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
1019
1020 if (ret == 0)
1021 {
1022 pin_ctrl.cs_pu_dis = ~val->cs_pull_up;
1023 pin_ctrl.pd_dis_int1 = ~val->int1_pull_down;
1024 pin_ctrl.pd_dis_int2 = ~val->int2_pull_down;
1025 pin_ctrl.sda_pu_en = val->sda_pull_up;
1026 pin_ctrl.sdo_pu_en = val->sdo_pull_up;
1027 pin_ctrl.pp_od = ~val->int1_int2_push_pull;
1028
1029 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
1030 }
1031
1032 return ret;
1033 }
1034
1035 /**
1036 * @brief Electrical pin configuration.[get]
1037 *
1038 * @param ctx read / write interface definitions
1039 * @param val the electrical settings for the configurable pins.(ptr)
1040 * @retval interface status (MANDATORY: return 0 -> no Error)
1041 *
1042 */
lis2duxs12_pin_conf_get(stmdev_ctx_t * ctx,lis2duxs12_pin_conf_t * val)1043 int32_t lis2duxs12_pin_conf_get(stmdev_ctx_t *ctx, lis2duxs12_pin_conf_t *val)
1044 {
1045 lis2duxs12_pin_ctrl_t pin_ctrl;
1046 int32_t ret;
1047
1048 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
1049
1050 val->cs_pull_up = ~pin_ctrl.cs_pu_dis;
1051 val->int1_pull_down = ~pin_ctrl.pd_dis_int1;
1052 val->int2_pull_down = ~pin_ctrl.pd_dis_int2;
1053 val->sda_pull_up = pin_ctrl.sda_pu_en;
1054 val->sdo_pull_up = pin_ctrl.sdo_pu_en;
1055 val->int1_int2_push_pull = ~pin_ctrl.pp_od;
1056
1057 return ret;
1058 }
1059
1060 /**
1061 * @brief Interrupt activation level.[set]
1062 *
1063 * @param ctx read / write interface definitions
1064 * @param val ACTIVE_HIGH, ACTIVE_LOW,
1065 * @retval interface status (MANDATORY: return 0 -> no Error)
1066 *
1067 */
lis2duxs12_int_pin_polarity_set(stmdev_ctx_t * ctx,lis2duxs12_int_pin_polarity_t val)1068 int32_t lis2duxs12_int_pin_polarity_set(stmdev_ctx_t *ctx, lis2duxs12_int_pin_polarity_t val)
1069 {
1070 lis2duxs12_pin_ctrl_t pin_ctrl;
1071 int32_t ret;
1072
1073 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
1074
1075 if (ret == 0)
1076 {
1077 pin_ctrl.h_lactive = (uint8_t)val;
1078 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
1079 }
1080
1081 return ret;
1082 }
1083
1084 /**
1085 * @brief Interrupt activation level.[get]
1086 *
1087 * @param ctx read / write interface definitions
1088 * @param val ACTIVE_HIGH, ACTIVE_LOW,
1089 * @retval interface status (MANDATORY: return 0 -> no Error)
1090 *
1091 */
lis2duxs12_int_pin_polarity_get(stmdev_ctx_t * ctx,lis2duxs12_int_pin_polarity_t * val)1092 int32_t lis2duxs12_int_pin_polarity_get(stmdev_ctx_t *ctx, lis2duxs12_int_pin_polarity_t *val)
1093 {
1094 lis2duxs12_pin_ctrl_t pin_ctrl;
1095 int32_t ret;
1096
1097 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
1098
1099 switch ((pin_ctrl.h_lactive))
1100 {
1101 case LIS2DUXS12_ACTIVE_HIGH:
1102 *val = LIS2DUXS12_ACTIVE_HIGH;
1103 break;
1104
1105 case LIS2DUXS12_ACTIVE_LOW:
1106 *val = LIS2DUXS12_ACTIVE_LOW;
1107 break;
1108
1109 default:
1110 *val = LIS2DUXS12_ACTIVE_HIGH;
1111 break;
1112 }
1113 return ret;
1114 }
1115
1116 /**
1117 * @brief SPI mode.[set]
1118 *
1119 * @param ctx read / write interface definitions
1120 * @param val SPI_4_WIRE, SPI_3_WIRE,
1121 * @retval interface status (MANDATORY: return 0 -> no Error)
1122 *
1123 */
lis2duxs12_spi_mode_set(stmdev_ctx_t * ctx,lis2duxs12_spi_mode val)1124 int32_t lis2duxs12_spi_mode_set(stmdev_ctx_t *ctx, lis2duxs12_spi_mode val)
1125 {
1126 lis2duxs12_pin_ctrl_t pin_ctrl;
1127 int32_t ret;
1128
1129 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
1130
1131 if (ret == 0)
1132 {
1133 pin_ctrl.sim = (uint8_t)val;
1134 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
1135 }
1136
1137 return ret;
1138 }
1139
1140 /**
1141 * @brief SPI mode.[get]
1142 *
1143 * @param ctx read / write interface definitions
1144 * @param val SPI_4_WIRE, SPI_3_WIRE,
1145 * @retval interface status (MANDATORY: return 0 -> no Error)
1146 *
1147 */
lis2duxs12_spi_mode_get(stmdev_ctx_t * ctx,lis2duxs12_spi_mode * val)1148 int32_t lis2duxs12_spi_mode_get(stmdev_ctx_t *ctx, lis2duxs12_spi_mode *val)
1149 {
1150 lis2duxs12_pin_ctrl_t pin_ctrl;
1151 int32_t ret;
1152
1153 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
1154
1155 switch ((pin_ctrl.h_lactive))
1156 {
1157 case LIS2DUXS12_SPI_4_WIRE:
1158 *val = LIS2DUXS12_SPI_4_WIRE;
1159 break;
1160
1161 case LIS2DUXS12_SPI_3_WIRE:
1162 *val = LIS2DUXS12_SPI_3_WIRE;
1163 break;
1164
1165 default:
1166 *val = LIS2DUXS12_SPI_4_WIRE;
1167 break;
1168 }
1169 return ret;
1170 }
1171
1172 /**
1173 * @brief routes interrupt signals on INT 1 pin.[set]
1174 *
1175 * @param ctx read / write interface definitions
1176 * @param val routes interrupt signals on INT 1 pin.
1177 * @retval interface status (MANDATORY: return 0 -> no Error)
1178 *
1179 */
lis2duxs12_pin_int1_route_set(stmdev_ctx_t * ctx,lis2duxs12_pin_int_route_t * val)1180 int32_t lis2duxs12_pin_int1_route_set(stmdev_ctx_t *ctx, lis2duxs12_pin_int_route_t *val)
1181 {
1182 lis2duxs12_ctrl1_t ctrl1;
1183 lis2duxs12_ctrl2_t ctrl2;
1184 lis2duxs12_md1_cfg_t md1_cfg;
1185 int32_t ret;
1186
1187 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1);
1188
1189 if (ret == 0)
1190 {
1191 ctrl1.int1_on_res = val->int_on_res;
1192
1193 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1);
1194 }
1195
1196 if (ret == 0)
1197 {
1198 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL2, (uint8_t *)&ctrl2, 1);
1199
1200 if (ret == 0)
1201 {
1202 ctrl2.int1_drdy = val->drdy;
1203 ctrl2.int1_fifo_ovr = val->fifo_ovr;
1204 ctrl2.int1_fifo_th = val->fifo_th;
1205 ctrl2.int1_fifo_full = val->fifo_full;
1206 ctrl2.int1_boot = val->boot;
1207
1208 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL2, (uint8_t *)&ctrl2, 1);
1209 }
1210 }
1211
1212 if (ret == 0)
1213 {
1214 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_MD1_CFG, (uint8_t *)&md1_cfg, 1);
1215
1216 if (ret == 0)
1217 {
1218 md1_cfg.int1_ff = val->free_fall;
1219 md1_cfg.int1_6d = val->six_d;
1220 md1_cfg.int1_tap = val->tap;
1221 md1_cfg.int1_wu = val->wake_up;
1222 md1_cfg.int1_sleep_change = val->sleep_change;
1223 md1_cfg.int1_emb_func = val->emb_function;
1224 md1_cfg.int1_timestamp = val->timestamp;
1225
1226 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_MD1_CFG, (uint8_t *)&md1_cfg, 1);
1227 }
1228 }
1229
1230 return ret;
1231 }
1232
1233 /**
1234 * @brief routes interrupt signals on INT 1 pin.[get]
1235 *
1236 * @param ctx read / write interface definitions
1237 * @param val Get interrupt signals routing on INT 1 pin.
1238 * @retval interface status (MANDATORY: return 0 -> no Error)
1239 *
1240 */
lis2duxs12_pin_int1_route_get(stmdev_ctx_t * ctx,lis2duxs12_pin_int_route_t * val)1241 int32_t lis2duxs12_pin_int1_route_get(stmdev_ctx_t *ctx, lis2duxs12_pin_int_route_t *val)
1242 {
1243 lis2duxs12_ctrl1_t ctrl1;
1244 lis2duxs12_ctrl2_t ctrl2;
1245 lis2duxs12_md1_cfg_t md1_cfg;
1246 int32_t ret;
1247
1248 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1);
1249 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL2, (uint8_t *)&ctrl2, 1);
1250 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_MD1_CFG, (uint8_t *)&md1_cfg, 1);
1251
1252 if (ret == 0)
1253 {
1254 val->int_on_res = ctrl1.int1_on_res;
1255 val->drdy = ctrl2.int1_drdy;
1256 val->fifo_ovr = ctrl2.int1_fifo_ovr;
1257 val->fifo_th = ctrl2.int1_fifo_th;
1258 val->fifo_full = ctrl2.int1_fifo_full;
1259 val->boot = ctrl2.int1_boot;
1260 val->free_fall = md1_cfg.int1_ff;
1261 val->six_d = md1_cfg.int1_6d;
1262 val->tap = md1_cfg.int1_tap;
1263 val->wake_up = md1_cfg.int1_wu;
1264 val->sleep_change = md1_cfg.int1_sleep_change;
1265 val->emb_function = md1_cfg.int1_emb_func;
1266 val->timestamp = md1_cfg.int1_timestamp;
1267 }
1268
1269 return ret;
1270 }
1271
1272 /**
1273 * @brief routes embedded func interrupt signals on INT 1 pin.[set]
1274 *
1275 * @param ctx read / write interface definitions
1276 * @param val routes embedded func interrupt signals on INT 1 pin.
1277 * @retval interface status (MANDATORY: return 0 -> no Error)
1278 *
1279 */
lis2duxs12_emb_pin_int1_route_set(stmdev_ctx_t * ctx,lis2duxs12_emb_pin_int_route_t * val)1280 int32_t lis2duxs12_emb_pin_int1_route_set(stmdev_ctx_t *ctx,
1281 lis2duxs12_emb_pin_int_route_t *val)
1282 {
1283 lis2duxs12_emb_func_int1_t emb_func_int1;
1284 lis2duxs12_md1_cfg_t md1_cfg;
1285 int32_t ret;
1286
1287 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
1288 if (ret == 0)
1289 {
1290 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1);
1291 }
1292
1293 if (ret == 0)
1294 {
1295 emb_func_int1.int1_tilt = val->tilt;
1296 emb_func_int1.int1_sig_mot = val->sig_mot;
1297 emb_func_int1.int1_step_det = val->step_det;
1298 emb_func_int1.int1_fsm_lc = val->fsm_lc;
1299
1300 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1);
1301 }
1302 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
1303
1304 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_MD1_CFG, (uint8_t *)&md1_cfg, 1);
1305 if (ret == 0)
1306 {
1307 md1_cfg.int1_emb_func = 1;
1308 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_MD1_CFG, (uint8_t *)&md1_cfg, 1);
1309 }
1310
1311 return ret;
1312 }
1313
1314 /**
1315 * @brief routes embedded func interrupt signals on INT 1 pin.[get]
1316 *
1317 * @param ctx read / write interface definitions
1318 * @param val routes embedded func interrupt signals on INT 1 pin.
1319 * @retval interface status (MANDATORY: return 0 -> no Error)
1320 *
1321 */
lis2duxs12_emb_pin_int1_route_get(stmdev_ctx_t * ctx,lis2duxs12_emb_pin_int_route_t * val)1322 int32_t lis2duxs12_emb_pin_int1_route_get(stmdev_ctx_t *ctx,
1323 lis2duxs12_emb_pin_int_route_t *val)
1324 {
1325 lis2duxs12_emb_func_int1_t emb_func_int1;
1326 int32_t ret;
1327
1328 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
1329 if (ret == 0)
1330 {
1331 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1);
1332 }
1333
1334 if (ret == 0)
1335 {
1336 val->tilt = emb_func_int1.int1_tilt;
1337 val->sig_mot = emb_func_int1.int1_sig_mot;
1338 val->step_det = emb_func_int1.int1_step_det;
1339 val->fsm_lc = emb_func_int1.int1_fsm_lc;
1340 }
1341 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
1342
1343 return ret;
1344 }
1345
1346 /**
1347 * @brief routes interrupt signals on INT 2 pin.[set]
1348 *
1349 * @param ctx read / write interface definitions
1350 * @param val routes interrupt signals on INT 2 pin.
1351 * @retval interface status (MANDATORY: return 0 -> no Error)
1352 *
1353 */
lis2duxs12_pin_int2_route_set(stmdev_ctx_t * ctx,lis2duxs12_pin_int_route_t * val)1354 int32_t lis2duxs12_pin_int2_route_set(stmdev_ctx_t *ctx, lis2duxs12_pin_int_route_t *val)
1355 {
1356 lis2duxs12_ctrl3_t ctrl3;
1357 lis2duxs12_md2_cfg_t md2_cfg;
1358 int32_t ret;
1359
1360 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL2, (uint8_t *)&ctrl3, 1);
1361
1362 if (ret == 0)
1363 {
1364 ctrl3.int2_drdy = val->drdy;
1365 ctrl3.int2_fifo_ovr = val->fifo_ovr;
1366 ctrl3.int2_fifo_th = val->fifo_th;
1367 ctrl3.int2_fifo_full = val->fifo_full;
1368 ctrl3.int2_boot = val->boot;
1369
1370 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL3, (uint8_t *)&ctrl3, 1);
1371 }
1372
1373 if (ret == 0)
1374 {
1375 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_MD2_CFG, (uint8_t *)&md2_cfg, 1);
1376
1377 if (ret == 0)
1378 {
1379 md2_cfg.int2_ff = val->free_fall;
1380 md2_cfg.int2_6d = val->six_d;
1381 md2_cfg.int2_tap = val->tap;
1382 md2_cfg.int2_wu = val->wake_up;
1383 md2_cfg.int2_sleep_change = val->sleep_change;
1384 md2_cfg.int2_emb_func = val->emb_function;
1385 md2_cfg.int2_timestamp = val->timestamp;
1386
1387 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_MD2_CFG, (uint8_t *)&md2_cfg, 1);
1388 }
1389 }
1390
1391 return ret;
1392 }
1393
1394 /**
1395 * @brief routes interrupt signals on INT 2 pin.[get]
1396 *
1397 * @param ctx read / write interface definitions
1398 * @param val Get interrupt signals routing on INT 2 pin.
1399 * @retval interface status (MANDATORY: return 0 -> no Error)
1400 *
1401 */
lis2duxs12_pin_int2_route_get(stmdev_ctx_t * ctx,lis2duxs12_pin_int_route_t * val)1402 int32_t lis2duxs12_pin_int2_route_get(stmdev_ctx_t *ctx, lis2duxs12_pin_int_route_t *val)
1403 {
1404 lis2duxs12_ctrl3_t ctrl3;
1405 lis2duxs12_md2_cfg_t md2_cfg;
1406 int32_t ret;
1407
1408 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL2, (uint8_t *)&ctrl3, 1);
1409 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_MD1_CFG, (uint8_t *)&md2_cfg, 1);
1410
1411 if (ret == 0)
1412 {
1413 val->drdy = ctrl3.int2_drdy;
1414 val->fifo_ovr = ctrl3.int2_fifo_ovr;
1415 val->fifo_th = ctrl3.int2_fifo_th;
1416 val->fifo_full = ctrl3.int2_fifo_full;
1417 val->boot = ctrl3.int2_boot;
1418 val->free_fall = md2_cfg.int2_ff;
1419 val->six_d = md2_cfg.int2_6d;
1420 val->tap = md2_cfg.int2_tap;
1421 val->wake_up = md2_cfg.int2_wu;
1422 val->sleep_change = md2_cfg.int2_sleep_change;
1423 val->emb_function = md2_cfg.int2_emb_func;
1424 val->timestamp = md2_cfg.int2_timestamp;
1425 }
1426
1427 return ret;
1428 }
1429
1430 /**
1431 * @brief routes embedded func interrupt signals on INT 2 pin.[set]
1432 *
1433 * @param ctx read / write interface definitions
1434 * @param val routes embedded func interrupt signals on INT 2 pin.
1435 * @retval interface status (MANDATORY: return 0 -> no Error)
1436 *
1437 */
lis2duxs12_emb_pin_int2_route_set(stmdev_ctx_t * ctx,lis2duxs12_emb_pin_int_route_t * val)1438 int32_t lis2duxs12_emb_pin_int2_route_set(stmdev_ctx_t *ctx,
1439 lis2duxs12_emb_pin_int_route_t *val)
1440 {
1441 lis2duxs12_emb_func_int2_t emb_func_int2;
1442 lis2duxs12_md2_cfg_t md2_cfg;
1443 int32_t ret;
1444
1445 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
1446 if (ret == 0)
1447 {
1448 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1);
1449 }
1450
1451 if (ret == 0)
1452 {
1453 emb_func_int2.int2_tilt = val->tilt;
1454 emb_func_int2.int2_sig_mot = val->sig_mot;
1455 emb_func_int2.int2_step_det = val->step_det;
1456 emb_func_int2.int2_fsm_lc = val->fsm_lc;
1457
1458 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1);
1459 }
1460 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
1461
1462 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_MD2_CFG, (uint8_t *)&md2_cfg, 1);
1463 if (ret == 0)
1464 {
1465 md2_cfg.int2_emb_func = 1;
1466 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_MD2_CFG, (uint8_t *)&md2_cfg, 1);
1467 }
1468
1469 return ret;
1470 }
1471
1472 /**
1473 * @brief routes embedded func interrupt signals on INT 2 pin.[get]
1474 *
1475 * @param ctx read / write interface definitions
1476 * @param val routes embedded func interrupt signals on INT 2 pin.
1477 * @retval interface status (MANDATORY: return 0 -> no Error)
1478 *
1479 */
lis2duxs12_emb_pin_int2_route_get(stmdev_ctx_t * ctx,lis2duxs12_emb_pin_int_route_t * val)1480 int32_t lis2duxs12_emb_pin_int2_route_get(stmdev_ctx_t *ctx,
1481 lis2duxs12_emb_pin_int_route_t *val)
1482 {
1483 lis2duxs12_emb_func_int2_t emb_func_int2;
1484 int32_t ret;
1485
1486 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
1487 if (ret == 0)
1488 {
1489 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1);
1490 }
1491
1492 if (ret == 0)
1493 {
1494 val->tilt = emb_func_int2.int2_tilt;
1495 val->sig_mot = emb_func_int2.int2_sig_mot;
1496 val->step_det = emb_func_int2.int2_step_det;
1497 val->fsm_lc = emb_func_int2.int2_fsm_lc;
1498 }
1499 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
1500
1501 return ret;
1502 }
1503
1504 /**
1505 * @brief Interrupt configuration mode.[set]
1506 *
1507 * @param ctx read / write interface definitions
1508 * @param val INT_DISABLED, INT_LEVEL, INT_LATCHED
1509 * @retval interface status (MANDATORY: return 0 -> no Error)
1510 *
1511 */
lis2duxs12_int_config_set(stmdev_ctx_t * ctx,lis2duxs12_int_config_t * val)1512 int32_t lis2duxs12_int_config_set(stmdev_ctx_t *ctx, lis2duxs12_int_config_t *val)
1513 {
1514 lis2duxs12_interrupt_cfg_t interrupt_cfg;
1515 int32_t ret;
1516
1517 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_INTERRUPT_CFG, (uint8_t *)&interrupt_cfg, 1);
1518
1519 if (ret == 0)
1520 {
1521 switch (val->int_cfg)
1522 {
1523 case LIS2DUXS12_INT_DISABLED:
1524 interrupt_cfg.interrupts_enable = 0;
1525 break;
1526
1527 case LIS2DUXS12_INT_LEVEL:
1528 interrupt_cfg.interrupts_enable = 1;
1529 interrupt_cfg.lir = 0;
1530 break;
1531
1532 case LIS2DUXS12_INT_LATCHED:
1533 default:
1534 interrupt_cfg.interrupts_enable = 1;
1535 interrupt_cfg.lir = 1;
1536 break;
1537 }
1538
1539 interrupt_cfg.dis_rst_lir_all_int = val->dis_rst_lir_all_int;
1540 interrupt_cfg.sleep_status_on_int = val->sleep_status_on_int;
1541
1542 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_INTERRUPT_CFG, (uint8_t *)&interrupt_cfg, 1);
1543 }
1544
1545 return ret;
1546 }
1547
1548 /**
1549 * @brief Interrupt configuration mode.[get]
1550 *
1551 * @param ctx read / write interface definitions
1552 * @param val INT_DISABLED, INT_LEVEL, INT_LATCHED
1553 * @retval interface status (MANDATORY: return 0 -> no Error)
1554 *
1555 */
lis2duxs12_int_config_get(stmdev_ctx_t * ctx,lis2duxs12_int_config_t * val)1556 int32_t lis2duxs12_int_config_get(stmdev_ctx_t *ctx, lis2duxs12_int_config_t *val)
1557 {
1558 lis2duxs12_interrupt_cfg_t interrupt_cfg;
1559 int32_t ret;
1560
1561 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_INTERRUPT_CFG, (uint8_t *)&interrupt_cfg, 1);
1562
1563 if (ret == 0)
1564 {
1565 val->dis_rst_lir_all_int = interrupt_cfg.dis_rst_lir_all_int;
1566 val->sleep_status_on_int = interrupt_cfg.sleep_status_on_int;
1567
1568 if (interrupt_cfg.interrupts_enable == 0U)
1569 {
1570 val->int_cfg = LIS2DUXS12_INT_DISABLED;
1571 }
1572 else if (interrupt_cfg.lir == 0U)
1573 {
1574 val->int_cfg = LIS2DUXS12_INT_LEVEL;
1575 }
1576 else
1577 {
1578 val->int_cfg = LIS2DUXS12_INT_LATCHED;
1579 }
1580 }
1581
1582 return ret;
1583 }
1584
1585 /**
1586 * @brief Embedded Interrupt configuration mode.[set]
1587 *
1588 * @param ctx read / write interface definitions
1589 * @param val INT_PULSED, INT_LATCHED
1590 * @retval interface status (MANDATORY: return 0 -> no Error)
1591 *
1592 */
lis2duxs12_embedded_int_config_set(stmdev_ctx_t * ctx,lis2duxs12_embedded_int_config_t val)1593 int32_t lis2duxs12_embedded_int_config_set(stmdev_ctx_t *ctx, lis2duxs12_embedded_int_config_t val)
1594 {
1595 lis2duxs12_page_rw_t page_rw;
1596 int32_t ret;
1597
1598 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
1599 if (ret == 0)
1600 {
1601 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1);
1602
1603 switch (val)
1604 {
1605 case LIS2DUXS12_EMBEDDED_INT_LEVEL:
1606 page_rw.emb_func_lir = 0;
1607 break;
1608
1609 case LIS2DUXS12_EMBEDDED_INT_LATCHED:
1610 default:
1611 page_rw.emb_func_lir = 1;
1612 break;
1613 }
1614
1615 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1);
1616 }
1617
1618 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
1619
1620 return ret;
1621 }
1622
1623 /**
1624 * @brief Interrupt configuration mode.[get]
1625 *
1626 * @param ctx read / write interface definitions
1627 * @param val INT_DISABLED, INT_PULSED, INT_LATCHED
1628 * @retval interface status (MANDATORY: return 0 -> no Error)
1629 *
1630 */
lis2duxs12_embedded_int_config_get(stmdev_ctx_t * ctx,lis2duxs12_embedded_int_config_t * val)1631 int32_t lis2duxs12_embedded_int_config_get(stmdev_ctx_t *ctx, lis2duxs12_embedded_int_config_t *val)
1632 {
1633 lis2duxs12_page_rw_t page_rw;
1634 int32_t ret;
1635
1636 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
1637 if (ret == 0)
1638 {
1639 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1);
1640
1641 if (page_rw.emb_func_lir == 0U) {
1642 *val = LIS2DUXS12_EMBEDDED_INT_LEVEL;
1643 } else {
1644 *val = LIS2DUXS12_EMBEDDED_INT_LATCHED;
1645 }
1646 }
1647
1648 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
1649
1650 return ret;
1651 }
1652
1653 /**
1654 * @}
1655 *
1656 */
1657
1658 /**
1659 * @defgroup FIFO
1660 * @brief FIFO
1661 * @{/
1662 *
1663 */
1664
1665 /**
1666 * @brief FIFO mode selection.[set]
1667 *
1668 * @param ctx read / write interface definitions
1669 * @param val BYPASS_MODE, FIFO_MODE, STREAM_TO_FIFO_MODE, BYPASS_TO_STREAM_MODE, STREAM_MODE, BYPASS_TO_FIFO_MODE,
1670 * @retval interface status (MANDATORY: return 0 -> no Error)
1671 *
1672 */
lis2duxs12_fifo_mode_set(stmdev_ctx_t * ctx,lis2duxs12_fifo_mode_t val)1673 int32_t lis2duxs12_fifo_mode_set(stmdev_ctx_t *ctx, lis2duxs12_fifo_mode_t val)
1674 {
1675 lis2duxs12_ctrl4_t ctrl4;
1676 lis2duxs12_fifo_ctrl_t fifo_ctrl;
1677 lis2duxs12_fifo_wtm_t fifo_wtm;
1678 lis2duxs12_fifo_batch_dec_t fifo_batch;
1679 int32_t ret;
1680
1681 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1);
1682 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
1683 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_BATCH_DEC, (uint8_t *)&fifo_batch, 1);
1684 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_WTM, (uint8_t *)&fifo_wtm, 1);
1685
1686 if (ret == 0)
1687 {
1688 /* set FIFO mode */
1689 if (val.operation != LIS2DUXS12_FIFO_OFF)
1690 {
1691 ctrl4.fifo_en = 1;
1692 fifo_ctrl.fifo_mode = ((uint8_t)val.operation & 0x7U);
1693 }
1694 else {
1695 ctrl4.fifo_en = 0;
1696 }
1697
1698 /* set fifo depth (1X/2X) */
1699 fifo_ctrl.fifo_depth = (uint8_t)val.store;
1700
1701 /* Set xl_only_fifo */
1702 fifo_wtm.xl_only_fifo = val.xl_only;
1703
1704 /* set batching info */
1705 if (val.batch.dec_ts != LIS2DUXS12_DEC_TS_OFF)
1706 {
1707 fifo_batch.dec_ts_batch = (uint8_t)val.batch.dec_ts;
1708 fifo_batch.bdr_xl = (uint8_t)val.batch.bdr_xl;
1709 }
1710
1711 fifo_ctrl.cfg_chg_en = val.cfg_change_in_fifo;
1712
1713 /* set watermark */
1714 if (val.watermark > 0U) {
1715 fifo_ctrl.stop_on_fth = 1;
1716 fifo_wtm.fth = val.watermark;
1717 }
1718
1719 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_FIFO_BATCH_DEC, (uint8_t *)&fifo_batch, 1);
1720 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_FIFO_WTM, (uint8_t *)&fifo_wtm, 1);
1721 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
1722 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1);
1723 }
1724
1725 return ret;
1726 }
1727
1728 /**
1729 * @brief FIFO mode selection.[get]
1730 *
1731 * @param ctx read / write interface definitions
1732 * @param val BYPASS_MODE, FIFO_MODE, STREAM_TO_FIFO_MODE, BYPASS_TO_STREAM_MODE, STREAM_MODE, BYPASS_TO_FIFO_MODE,
1733 * @retval interface status (MANDATORY: return 0 -> no Error)
1734 *
1735 */
lis2duxs12_fifo_mode_get(stmdev_ctx_t * ctx,lis2duxs12_fifo_mode_t * val)1736 int32_t lis2duxs12_fifo_mode_get(stmdev_ctx_t *ctx, lis2duxs12_fifo_mode_t *val)
1737 {
1738 lis2duxs12_ctrl4_t ctrl4;
1739 lis2duxs12_fifo_ctrl_t fifo_ctrl;
1740 lis2duxs12_fifo_wtm_t fifo_wtm;
1741 lis2duxs12_fifo_batch_dec_t fifo_batch;
1742 int32_t ret;
1743
1744 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1);
1745 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
1746 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_BATCH_DEC, (uint8_t *)&fifo_batch, 1);
1747 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_WTM, (uint8_t *)&fifo_wtm, 1);
1748
1749 if (ret == 0)
1750 {
1751 /* get FIFO mode */
1752 if (ctrl4.fifo_en == 0U) {
1753 val->operation = LIS2DUXS12_FIFO_OFF;
1754 }
1755 else {
1756 val->operation = (enum operation)fifo_ctrl.fifo_mode;
1757 }
1758 val->cfg_change_in_fifo = fifo_ctrl.cfg_chg_en;
1759
1760 /* get fifo depth (1X/2X) */
1761 val->store = (enum store)fifo_ctrl.fifo_depth;
1762
1763 /* Get xl_only_fifo */
1764 val->xl_only = fifo_wtm.xl_only_fifo;
1765
1766 /* get batching info */
1767 val->batch.dec_ts = (enum dec_ts)fifo_batch.dec_ts_batch;
1768 val->batch.bdr_xl = (enum bdr_xl)fifo_batch.bdr_xl;
1769
1770 /* get watermark */
1771 val->watermark = fifo_wtm.fth;
1772 }
1773
1774 return ret;
1775 }
1776
1777 /**
1778 * @brief Number of unread sensor data (TAG + 6 bytes) stored in FIFO.[get]
1779 *
1780 * @param ctx read / write interface definitions
1781 * @param val Number of unread sensor data (TAG + 6 bytes) stored in FIFO.
1782 * @retval interface status (MANDATORY: return 0 -> no Error)
1783 *
1784 */
lis2duxs12_fifo_data_level_get(stmdev_ctx_t * ctx,uint16_t * val)1785 int32_t lis2duxs12_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val)
1786 {
1787 uint8_t buff;
1788 int32_t ret;
1789
1790 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_STATUS2, &buff, 1);
1791
1792 *val = buff;
1793
1794 return ret;
1795 }
1796
lis2duxs12_fifo_wtm_flag_get(stmdev_ctx_t * ctx,uint8_t * val)1797 int32_t lis2duxs12_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
1798 {
1799 lis2duxs12_fifo_status1_t fifo_status1;
1800 int32_t ret;
1801
1802 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_STATUS1, (uint8_t *)&fifo_status1, 1);
1803
1804 *val = fifo_status1.fifo_wtm_ia;
1805
1806 return ret;
1807 }
1808
lis2duxs12_fifo_sensor_tag_get(stmdev_ctx_t * ctx,lis2duxs12_fifo_sensor_tag_t * val)1809 int32_t lis2duxs12_fifo_sensor_tag_get(stmdev_ctx_t *ctx, lis2duxs12_fifo_sensor_tag_t *val)
1810 {
1811 lis2duxs12_fifo_data_out_tag_t fifo_tag;
1812 int32_t ret;
1813
1814 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_DATA_OUT_TAG, (uint8_t *)&fifo_tag, 1);
1815
1816 *val = (lis2duxs12_fifo_sensor_tag_t) fifo_tag.tag_sensor;
1817
1818 return ret;
1819 }
1820
lis2duxs12_fifo_out_raw_get(stmdev_ctx_t * ctx,uint8_t * buff)1821 int32_t lis2duxs12_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
1822 {
1823 int32_t ret;
1824
1825 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_DATA_OUT_X_L, buff, 6);
1826
1827 return ret;
1828 }
1829
lis2duxs12_fifo_data_get(stmdev_ctx_t * ctx,lis2duxs12_md_t * md,lis2duxs12_fifo_mode_t * fmd,lis2duxs12_fifo_data_t * data)1830 int32_t lis2duxs12_fifo_data_get(stmdev_ctx_t *ctx, lis2duxs12_md_t *md,
1831 lis2duxs12_fifo_mode_t *fmd,
1832 lis2duxs12_fifo_data_t *data)
1833 {
1834 lis2duxs12_fifo_data_out_tag_t fifo_tag;
1835 uint8_t fifo_raw[6];
1836 int32_t ret, i;
1837
1838 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_DATA_OUT_TAG, (uint8_t *)&fifo_tag, 1);
1839 data->tag = fifo_tag.tag_sensor;
1840
1841 switch (fifo_tag.tag_sensor) {
1842 case LIS2DUXS12_XL_ONLY_2X_TAG:
1843 case LIS2DUXS12_XL_ONLY_2X_TAG_2ND:
1844 /* A FIFO sample consists of 2X 8-bits 3-axis XL at ODR/2 */
1845 ret = lis2duxs12_fifo_out_raw_get(ctx, fifo_raw);
1846 for (i = 0; i < 3; i++) {
1847 data->xl[0].raw[i] = (int16_t)fifo_raw[i] * 256;
1848 data->xl[1].raw[i] = (int16_t)fifo_raw[3 + i] * 256;
1849 }
1850 break;
1851 case LIS2DUXS12_XL_AND_QVAR:
1852 case LIS2DUXS12_XL_TEMP_TAG:
1853 ret = lis2duxs12_fifo_out_raw_get(ctx, fifo_raw);
1854 if (fmd->xl_only == 0x0U) {
1855 /* A FIFO sample consists of 12-bits 3-axis XL + T at ODR*/
1856 data->xl[0].raw[0] = (int16_t)fifo_raw[0];
1857 data->xl[0].raw[0] = (data->xl[0].raw[0] + (int16_t)fifo_raw[1] * 256) * 16;
1858 data->xl[0].raw[1] = (int16_t)fifo_raw[1] / 16;
1859 data->xl[0].raw[1] = (data->xl[0].raw[1] + ((int16_t)fifo_raw[2] * 16)) * 16;
1860 data->xl[0].raw[2] = (int16_t)fifo_raw[3];
1861 data->xl[0].raw[2] = data->xl[0].raw[2] + ((int16_t)fifo_raw[4] * 256) * 16;
1862 data->heat.raw = (int16_t)fifo_raw[4] / 16;
1863 data->heat.raw = (data->heat.raw + ((int16_t)fifo_raw[5] * 16)) * 16;
1864 if (fifo_tag.tag_sensor == (uint8_t)LIS2DUXS12_XL_TEMP_TAG) {
1865 data->heat.deg_c = lis2duxs12_from_lsb_to_celsius(data->heat.raw);
1866 } else {
1867 data->ah_qvar = data->heat.raw;
1868 }
1869 } else {
1870 /* A FIFO sample consists of 16-bits 3-axis XL at ODR */
1871 data->xl[0].raw[0] = (int16_t)fifo_raw[0] + (int16_t)fifo_raw[1] * 256;
1872 data->xl[0].raw[1] = (int16_t)fifo_raw[1] + (int16_t)fifo_raw[3] * 256;
1873 data->xl[0].raw[2] = (int16_t)fifo_raw[2] + (int16_t)fifo_raw[5] * 256;
1874 }
1875 break;
1876 case LIS2DUXS12_TIMESTAMP_TAG:
1877 ret = lis2duxs12_fifo_out_raw_get(ctx, fifo_raw);
1878
1879 data->cfg_chg.cfg_change = fifo_raw[0] >> 7;
1880 data->cfg_chg.odr = (fifo_raw[0] >> 3) & 0xFU;
1881 data->cfg_chg.bw = (fifo_raw[0] >> 1) & 0x3U;
1882 data->cfg_chg.lp_hp = fifo_raw[0] & 0x1U;
1883 data->cfg_chg.qvar_en = fifo_raw[1] >> 7;
1884 data->cfg_chg.fs = (fifo_raw[1] >> 5) & 0x3U;
1885 data->cfg_chg.dec_ts = (fifo_raw[1] >> 3) & 0x3U;
1886 data->cfg_chg.odr_xl_batch = fifo_raw[1] & 0x7U;
1887
1888 data->cfg_chg.timestamp = fifo_raw[5];
1889 data->cfg_chg.timestamp = (data->cfg_chg.timestamp * 256U) + fifo_raw[4];
1890 data->cfg_chg.timestamp = (data->cfg_chg.timestamp * 256U) + fifo_raw[3];
1891 data->cfg_chg.timestamp = (data->cfg_chg.timestamp * 256U) + fifo_raw[2];
1892 break;
1893
1894 case LIS2DUXS12_STEP_COUNTER_TAG:
1895 ret = lis2duxs12_fifo_out_raw_get(ctx, fifo_raw);
1896
1897 data->pedo.steps = fifo_raw[1];
1898 data->pedo.steps = (data->pedo.steps * 256U) + fifo_raw[0];
1899
1900 data->pedo.timestamp = fifo_raw[5];
1901 data->pedo.timestamp = (data->pedo.timestamp * 256U) + fifo_raw[4];
1902 data->pedo.timestamp = (data->pedo.timestamp * 256U) + fifo_raw[3];
1903 data->pedo.timestamp = (data->pedo.timestamp * 256U) + fifo_raw[2];
1904
1905 break;
1906
1907 case LIS2DUXS12_FIFO_EMPTY:
1908 default:
1909 break;
1910 }
1911
1912 for (i = 0; i < 3; i++) {
1913 switch ( md->fs ) {
1914 case LIS2DUXS12_2g:
1915 data->xl[0].mg[i] =lis2duxs12_from_fs2g_to_mg(data->xl[0].raw[i]);
1916 data->xl[1].mg[i] =lis2duxs12_from_fs2g_to_mg(data->xl[1].raw[i]);
1917 break;
1918 case LIS2DUXS12_4g:
1919 data->xl[0].mg[i] =lis2duxs12_from_fs4g_to_mg(data->xl[0].raw[i]);
1920 data->xl[1].mg[i] =lis2duxs12_from_fs4g_to_mg(data->xl[1].raw[i]);
1921 break;
1922 case LIS2DUXS12_8g:
1923 data->xl[0].mg[i] =lis2duxs12_from_fs8g_to_mg(data->xl[0].raw[i]);
1924 data->xl[1].mg[i] =lis2duxs12_from_fs8g_to_mg(data->xl[1].raw[i]);
1925 break;
1926 case LIS2DUXS12_16g:
1927 data->xl[0].mg[i] =lis2duxs12_from_fs16g_to_mg(data->xl[0].raw[i]);
1928 data->xl[1].mg[i] =lis2duxs12_from_fs16g_to_mg(data->xl[1].raw[i]);
1929 break;
1930 default:
1931 data->xl[0].mg[i] = 0.0f;
1932 data->xl[1].mg[i] = 0.0f;
1933 break;
1934 }
1935 }
1936
1937 return ret;
1938 }
1939
1940 /**
1941 * @brief Enables AH_QVAR chain.[set]
1942 *
1943 * @param ctx read / write interface definitions
1944 * @param val Enables and configures AH_QVAR chain.
1945 * @retval interface status (MANDATORY: return 0 -> no Error)
1946 *
1947 */
lis2duxs12_ah_qvar_mode_set(stmdev_ctx_t * ctx,lis2duxs12_ah_qvar_mode_t val)1948 int32_t lis2duxs12_ah_qvar_mode_set(stmdev_ctx_t *ctx,
1949 lis2duxs12_ah_qvar_mode_t val)
1950 {
1951 lis2duxs12_ah_qvar_cfg_t ah_qvar_cfg;
1952 int32_t ret;
1953
1954 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_AH_QVAR_CFG, (uint8_t *)&ah_qvar_cfg, 1);
1955 if (ret == 0)
1956 {
1957 ah_qvar_cfg.ah_qvar_gain = (uint8_t)val.ah_qvar_gain;
1958 ah_qvar_cfg.ah_qvar_c_zin = (uint8_t)val.ah_qvar_zin;
1959 ah_qvar_cfg.ah_qvar_notch_cutoff = (uint8_t)val.ah_qvar_notch;
1960 ah_qvar_cfg.ah_qvar_notch_en = val.ah_qvar_notch_en;
1961 ah_qvar_cfg.ah_qvar_en = val.ah_qvar_en;
1962 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_AH_QVAR_CFG, (uint8_t *)&ah_qvar_cfg, 1);
1963 }
1964
1965 return ret;
1966 }
1967
1968 /**
1969 * @brief Enables AH_QVAR chain.[get]
1970 *
1971 * @param ctx read / write interface definitions
1972 * @param val Enables and configures AH_QVAR chain.
1973 * @retval interface status (MANDATORY: return 0 -> no Error)
1974 *
1975 */
lis2duxs12_ah_qvar_mode_get(stmdev_ctx_t * ctx,lis2duxs12_ah_qvar_mode_t * val)1976 int32_t lis2duxs12_ah_qvar_mode_get(stmdev_ctx_t *ctx,
1977 lis2duxs12_ah_qvar_mode_t *val)
1978 {
1979 lis2duxs12_ah_qvar_cfg_t ah_qvar_cfg;
1980 int32_t ret;
1981
1982 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_AH_QVAR_CFG, (uint8_t *)&ah_qvar_cfg, 1);
1983
1984 switch (ah_qvar_cfg.ah_qvar_gain)
1985 {
1986 case LIS2DUXS12_GAIN_0_5:
1987 val->ah_qvar_gain = LIS2DUXS12_GAIN_0_5;
1988 break;
1989
1990 case LIS2DUXS12_GAIN_1:
1991 val->ah_qvar_gain = LIS2DUXS12_GAIN_1;
1992 break;
1993
1994 case LIS2DUXS12_GAIN_2:
1995 val->ah_qvar_gain = LIS2DUXS12_GAIN_2;
1996 break;
1997
1998 case LIS2DUXS12_GAIN_4:
1999 default:
2000 val->ah_qvar_gain = LIS2DUXS12_GAIN_4;
2001 break;
2002 }
2003
2004 switch (ah_qvar_cfg.ah_qvar_c_zin)
2005 {
2006 case LIS2DUXS12_520MOhm:
2007 val->ah_qvar_zin = LIS2DUXS12_520MOhm;
2008 break;
2009
2010 case LIS2DUXS12_175MOhm:
2011 val->ah_qvar_zin = LIS2DUXS12_175MOhm;
2012 break;
2013
2014 case LIS2DUXS12_310MOhm:
2015 val->ah_qvar_zin = LIS2DUXS12_310MOhm;
2016 break;
2017
2018 case LIS2DUXS12_75MOhm:
2019 default:
2020 val->ah_qvar_zin = LIS2DUXS12_75MOhm;
2021 break;
2022 }
2023
2024 switch (ah_qvar_cfg.ah_qvar_notch_cutoff)
2025 {
2026 case LIS2DUXS12_NOTCH_50HZ:
2027 val->ah_qvar_notch = LIS2DUXS12_NOTCH_50HZ;
2028 break;
2029
2030 case LIS2DUXS12_NOTCH_60HZ:
2031 default:
2032 val->ah_qvar_notch = LIS2DUXS12_NOTCH_60HZ;
2033 break;
2034 }
2035
2036 val->ah_qvar_notch_en = ah_qvar_cfg.ah_qvar_notch_en;
2037 val->ah_qvar_en = ah_qvar_cfg.ah_qvar_en;
2038
2039 return ret;
2040 }
2041
2042 /**
2043 * @defgroup Step Counter (Pedometer)
2044 * @brief Step Counter (Pedometer)
2045 * @{/
2046 *
2047 */
2048 /**
2049 * @brief Step counter mode[set]
2050 *
2051 * @param ctx read / write interface definitions
2052 * @param val Step counter mode
2053 * @retval interface status (MANDATORY: return 0 -> no Error)
2054 *
2055 */
lis2duxs12_stpcnt_mode_set(stmdev_ctx_t * ctx,lis2duxs12_stpcnt_mode_t val)2056 int32_t lis2duxs12_stpcnt_mode_set(stmdev_ctx_t *ctx, lis2duxs12_stpcnt_mode_t val)
2057 {
2058 lis2duxs12_emb_func_en_a_t emb_func_en_a;
2059 lis2duxs12_emb_func_en_b_t emb_func_en_b;
2060 lis2duxs12_emb_func_fifo_en_t emb_func_fifo_en;
2061 lis2duxs12_pedo_cmd_reg_t pedo_cmd_reg;
2062 int32_t ret;
2063
2064 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
2065 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
2066 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
2067 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_FIFO_EN, (uint8_t *)&emb_func_fifo_en, 1);
2068
2069 if ((val.false_step_rej == PROPERTY_ENABLE) && ((emb_func_en_a.mlc_before_fsm_en & emb_func_en_b.mlc_en) == PROPERTY_DISABLE))
2070 {
2071 emb_func_en_a.mlc_before_fsm_en = PROPERTY_ENABLE;
2072 }
2073
2074 emb_func_fifo_en.step_counter_fifo_en = val.step_counter_in_fifo;
2075 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_FIFO_EN, (uint8_t *)&emb_func_fifo_en, 1);
2076
2077 emb_func_en_a.pedo_en = val.step_counter_enable;
2078 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
2079
2080 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
2081 ret += lis2duxs12_ln_pg_read(ctx, LIS2DUXS12_EMB_ADV_PG_0 + LIS2DUXS12_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1);
2082
2083 if (ret == 0)
2084 {
2085 pedo_cmd_reg.fp_rejection_en = val.false_step_rej;
2086 ret += lis2duxs12_ln_pg_write(ctx, LIS2DUXS12_EMB_ADV_PG_0 + LIS2DUXS12_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1);
2087 }
2088
2089 return ret;
2090 }
2091
2092 /**
2093 * @brief Step counter mode[get]
2094 *
2095 * @param ctx read / write interface definitions
2096 * @param val Step counter mode
2097 * @retval interface status (MANDATORY: return 0 -> no Error)
2098 *
2099 */
lis2duxs12_stpcnt_mode_get(stmdev_ctx_t * ctx,lis2duxs12_stpcnt_mode_t * val)2100 int32_t lis2duxs12_stpcnt_mode_get(stmdev_ctx_t *ctx, lis2duxs12_stpcnt_mode_t *val)
2101 {
2102 lis2duxs12_emb_func_en_a_t emb_func_en_a;
2103 lis2duxs12_pedo_cmd_reg_t pedo_cmd_reg;
2104 int32_t ret;
2105
2106 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
2107 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
2108 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
2109
2110 ret += lis2duxs12_ln_pg_read(ctx, LIS2DUXS12_EMB_ADV_PG_0 + LIS2DUXS12_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1);
2111 val->false_step_rej = pedo_cmd_reg.fp_rejection_en;
2112 val->step_counter_enable = emb_func_en_a.pedo_en;
2113
2114 return ret;
2115 }
2116
2117 /**
2118 * @brief Step counter output, number of detected steps.[get]
2119 *
2120 * @param ctx read / write interface definitions
2121 * @param val Step counter output, number of detected steps.
2122 * @retval interface status (MANDATORY: return 0 -> no Error)
2123 *
2124 */
lis2duxs12_stpcnt_steps_get(stmdev_ctx_t * ctx,uint16_t * val)2125 int32_t lis2duxs12_stpcnt_steps_get(stmdev_ctx_t *ctx, uint16_t *val)
2126 {
2127 uint8_t buff[2];
2128 int32_t ret;
2129
2130 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
2131 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_STEP_COUNTER_L, &buff[0], 2);
2132 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
2133
2134 *val = buff[1];
2135 *val = (*val * 256U) + buff[0];
2136
2137 return ret;
2138 }
2139
2140 /**
2141 * @brief Reset step counter.[set]
2142 *
2143 * @param ctx read / write interface definitions
2144 * @param val Reset step counter.
2145 * @retval interface status (MANDATORY: return 0 -> no Error)
2146 *
2147 */
lis2duxs12_stpcnt_rst_step_set(stmdev_ctx_t * ctx)2148 int32_t lis2duxs12_stpcnt_rst_step_set(stmdev_ctx_t *ctx)
2149 {
2150 lis2duxs12_emb_func_src_t emb_func_src;
2151 int32_t ret;
2152
2153 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
2154 if (ret == 0)
2155 {
2156 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1);
2157 emb_func_src.pedo_rst_step = 1;
2158 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1);
2159 }
2160
2161 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
2162
2163 return ret;
2164 }
2165
2166 /**
2167 * @brief Pedometer debounce configuration.[set]
2168 *
2169 * @param ctx read / write interface definitions
2170 * @param val Pedometer debounce configuration.
2171 * @retval interface status (MANDATORY: return 0 -> no Error)
2172 *
2173 */
lis2duxs12_stpcnt_debounce_set(stmdev_ctx_t * ctx,uint8_t val)2174 int32_t lis2duxs12_stpcnt_debounce_set(stmdev_ctx_t *ctx, uint8_t val)
2175 {
2176 lis2duxs12_pedo_deb_steps_conf_t pedo_deb_steps_conf;
2177 int32_t ret;
2178
2179 pedo_deb_steps_conf.deb_step = val;
2180 ret = lis2duxs12_ln_pg_write(ctx, LIS2DUXS12_EMB_ADV_PG_0 + LIS2DUXS12_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1);
2181
2182 return ret;
2183 }
2184
2185 /**
2186 * @brief Pedometer debounce configuration.[get]
2187 *
2188 * @param ctx read / write interface definitions
2189 * @param val Pedometer debounce configuration.
2190 * @retval interface status (MANDATORY: return 0 -> no Error)
2191 *
2192 */
lis2duxs12_stpcnt_debounce_get(stmdev_ctx_t * ctx,uint8_t * val)2193 int32_t lis2duxs12_stpcnt_debounce_get(stmdev_ctx_t *ctx, uint8_t *val)
2194 {
2195 lis2duxs12_pedo_deb_steps_conf_t pedo_deb_steps_conf;
2196 int32_t ret;
2197
2198 ret = lis2duxs12_ln_pg_read(ctx, LIS2DUXS12_EMB_ADV_PG_0 + LIS2DUXS12_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1);
2199 *val = pedo_deb_steps_conf.deb_step;
2200
2201 return ret;
2202 }
2203
2204 /**
2205 * @brief Time period register for step detection on delta time.[set]
2206 *
2207 * @param ctx read / write interface definitions
2208 * @param val Time period register for step detection on delta time.
2209 * @retval interface status (MANDATORY: return 0 -> no Error)
2210 *
2211 */
lis2duxs12_stpcnt_period_set(stmdev_ctx_t * ctx,uint16_t val)2212 int32_t lis2duxs12_stpcnt_period_set(stmdev_ctx_t *ctx, uint16_t val)
2213 {
2214 uint8_t buff[2];
2215 int32_t ret;
2216
2217 buff[1] = (uint8_t)(val / 256U);
2218 buff[0] = (uint8_t)(val - (buff[1] * 256U));
2219
2220 ret = lis2duxs12_ln_pg_write(ctx, LIS2DUXS12_EMB_ADV_PG_0 + LIS2DUXS12_PEDO_SC_DELTAT_L, (uint8_t *)buff, 2);
2221
2222 return ret;
2223 }
2224
2225 /**
2226 * @brief Time period register for step detection on delta time.[get]
2227 *
2228 * @param ctx read / write interface definitions
2229 * @param val Time period register for step detection on delta time.
2230 * @retval interface status (MANDATORY: return 0 -> no Error)
2231 *
2232 */
lis2duxs12_stpcnt_period_get(stmdev_ctx_t * ctx,uint16_t * val)2233 int32_t lis2duxs12_stpcnt_period_get(stmdev_ctx_t *ctx, uint16_t *val)
2234 {
2235 uint8_t buff[2];
2236 int32_t ret;
2237
2238 ret = lis2duxs12_ln_pg_read(ctx, LIS2DUXS12_EMB_ADV_PG_0 + LIS2DUXS12_PEDO_SC_DELTAT_L, (uint8_t *)buff, 2);
2239 *val = buff[1];
2240 *val = (*val * 256U) + buff[0];
2241
2242 return ret;
2243 }
2244
2245 /**
2246 * @}
2247 *
2248 */
2249
2250 /**
2251 * @defgroup Tilt
2252 * @brief Tilt
2253 * @{/
2254 *
2255 */
2256 /**
2257 * @brief Tilt calculation.[set]
2258 *
2259 * @param ctx read / write interface definitions
2260 * @param val Tilt calculation.
2261 * @retval interface status (MANDATORY: return 0 -> no Error)
2262 *
2263 */
lis2duxs12_tilt_mode_set(stmdev_ctx_t * ctx,uint8_t val)2264 int32_t lis2duxs12_tilt_mode_set(stmdev_ctx_t *ctx, uint8_t val)
2265 {
2266 lis2duxs12_emb_func_en_a_t emb_func_en_a;
2267 int32_t ret;
2268
2269 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
2270 if (ret == 0)
2271 {
2272 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
2273 emb_func_en_a.tilt_en = val;
2274 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
2275 }
2276
2277 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
2278
2279 return ret;
2280 }
2281
2282 /**
2283 * @brief Tilt calculation.[get]
2284 *
2285 * @param ctx read / write interface definitions
2286 * @param val Tilt calculation.
2287 * @retval interface status (MANDATORY: return 0 -> no Error)
2288 *
2289 */
lis2duxs12_tilt_mode_get(stmdev_ctx_t * ctx,uint8_t * val)2290 int32_t lis2duxs12_tilt_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
2291 {
2292 lis2duxs12_emb_func_en_a_t emb_func_en_a;
2293 int32_t ret;
2294
2295 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
2296 if (ret == 0)
2297 {
2298 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
2299 *val = emb_func_en_a.tilt_en;
2300 }
2301
2302 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
2303
2304 return ret;
2305 }
2306
2307 /**
2308 * @}
2309 *
2310 */
2311
2312 /**
2313 * @defgroup Significant motion detection
2314 * @brief Significant motion detection
2315 * @{/
2316 *
2317 */
2318 /**
2319 * @brief Enables significant motion detection function.[set]
2320 *
2321 * @param ctx read / write interface definitions
2322 * @param val Enables significant motion detection function.
2323 * @retval interface status (MANDATORY: return 0 -> no Error)
2324 *
2325 */
lis2duxs12_sigmot_mode_set(stmdev_ctx_t * ctx,uint8_t val)2326 int32_t lis2duxs12_sigmot_mode_set(stmdev_ctx_t *ctx, uint8_t val)
2327 {
2328 lis2duxs12_emb_func_en_a_t emb_func_en_a;
2329 int32_t ret;
2330
2331 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
2332 if (ret == 0)
2333 {
2334 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
2335 emb_func_en_a.sign_motion_en = val;
2336 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
2337 }
2338
2339 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
2340
2341 return ret;
2342 }
2343
2344 /**
2345 * @brief Enables significant motion detection function.[get]
2346 *
2347 * @param ctx read / write interface definitions
2348 * @param val Enables significant motion detection function.
2349 * @retval interface status (MANDATORY: return 0 -> no Error)
2350 *
2351 */
lis2duxs12_sigmot_mode_get(stmdev_ctx_t * ctx,uint8_t * val)2352 int32_t lis2duxs12_sigmot_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
2353 {
2354 lis2duxs12_emb_func_en_a_t emb_func_en_a;
2355 int32_t ret;
2356
2357 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
2358 if (ret == 0)
2359 {
2360 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
2361 *val = emb_func_en_a.sign_motion_en;
2362 }
2363
2364 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
2365
2366 return ret;
2367 }
2368
2369 /**
2370 * @}
2371 *
2372 */
2373
2374
2375 /**
2376 * @defgroup Free Fall
2377 * @brief Free Fall
2378 * @{/
2379 *
2380 */
2381 /**
2382 * @brief Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time[set]
2383 *
2384 * @param ctx read / write interface definitions
2385 * @param val Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time
2386 * @retval interface status (MANDATORY: return 0 -> no Error)
2387 *
2388 */
lis2duxs12_ff_duration_set(stmdev_ctx_t * ctx,uint8_t val)2389 int32_t lis2duxs12_ff_duration_set(stmdev_ctx_t *ctx, uint8_t val)
2390 {
2391 lis2duxs12_wake_up_dur_t wake_up_dur;
2392 lis2duxs12_free_fall_t free_fall;
2393 int32_t ret;
2394
2395 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
2396
2397 if (ret == 0)
2398 {
2399 wake_up_dur.ff_dur = (val >> 5) & 0x1U;
2400 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
2401 }
2402
2403 if (ret == 0)
2404 {
2405 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FREE_FALL, (uint8_t *)&free_fall, 1);
2406 free_fall.ff_dur = val & 0x1FU;
2407 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_FREE_FALL, (uint8_t *)&free_fall, 1);
2408 }
2409
2410 return ret;
2411 }
2412
2413 /**
2414 * @brief Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time[get]
2415 *
2416 * @param ctx read / write interface definitions
2417 * @param val Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time
2418 * @retval interface status (MANDATORY: return 0 -> no Error)
2419 *
2420 */
lis2duxs12_ff_duration_get(stmdev_ctx_t * ctx,uint8_t * val)2421 int32_t lis2duxs12_ff_duration_get(stmdev_ctx_t *ctx, uint8_t *val)
2422 {
2423 lis2duxs12_wake_up_dur_t wake_up_dur;
2424 lis2duxs12_free_fall_t free_fall;
2425 int32_t ret;
2426
2427 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
2428
2429 if (ret == 0)
2430 {
2431 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FREE_FALL, (uint8_t *)&free_fall, 1);
2432 }
2433
2434 *val = (wake_up_dur.ff_dur << 5) | free_fall.ff_dur;
2435
2436 return ret;
2437 }
2438
2439 /**
2440 * @brief Free fall threshold setting.[set]
2441 *
2442 * @param ctx read / write interface definitions
2443 * @param val 156_mg, 219_mg, 250_mg, 312_mg, 344_mg, 406_mg, 469_mg, 500_mg,
2444 * @retval interface status (MANDATORY: return 0 -> no Error)
2445 *
2446 */
lis2duxs12_ff_thresholds_set(stmdev_ctx_t * ctx,lis2duxs12_ff_thresholds_t val)2447 int32_t lis2duxs12_ff_thresholds_set(stmdev_ctx_t *ctx, lis2duxs12_ff_thresholds_t val)
2448 {
2449 lis2duxs12_free_fall_t free_fall;
2450 int32_t ret;
2451
2452 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FREE_FALL, (uint8_t *)&free_fall, 1);
2453 free_fall.ff_ths = ((uint8_t)val & 0x7U);
2454 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_FREE_FALL, (uint8_t *)&free_fall, 1);
2455
2456 return ret;
2457 }
2458
2459 /**
2460 * @brief Free fall threshold setting.[get]
2461 *
2462 * @param ctx read / write interface definitions
2463 * @param val 156_mg, 219_mg, 250_mg, 312_mg, 344_mg, 406_mg, 469_mg, 500_mg,
2464 * @retval interface status (MANDATORY: return 0 -> no Error)
2465 *
2466 */
lis2duxs12_ff_thresholds_get(stmdev_ctx_t * ctx,lis2duxs12_ff_thresholds_t * val)2467 int32_t lis2duxs12_ff_thresholds_get(stmdev_ctx_t *ctx, lis2duxs12_ff_thresholds_t *val)
2468 {
2469 lis2duxs12_free_fall_t free_fall;
2470 int32_t ret;
2471
2472 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FREE_FALL, (uint8_t *)&free_fall, 1);
2473
2474 switch (free_fall.ff_ths)
2475 {
2476 case LIS2DUXS12_156_mg:
2477 *val = LIS2DUXS12_156_mg;
2478 break;
2479
2480 case LIS2DUXS12_219_mg:
2481 *val = LIS2DUXS12_219_mg;
2482 break;
2483
2484 case LIS2DUXS12_250_mg:
2485 *val = LIS2DUXS12_250_mg;
2486 break;
2487
2488 case LIS2DUXS12_312_mg:
2489 *val = LIS2DUXS12_312_mg;
2490 break;
2491
2492 case LIS2DUXS12_344_mg:
2493 *val = LIS2DUXS12_344_mg;
2494 break;
2495
2496 case LIS2DUXS12_406_mg:
2497 *val = LIS2DUXS12_406_mg;
2498 break;
2499
2500 case LIS2DUXS12_469_mg:
2501 *val = LIS2DUXS12_469_mg;
2502 break;
2503
2504 case LIS2DUXS12_500_mg:
2505 *val = LIS2DUXS12_500_mg;
2506 break;
2507
2508 default:
2509 *val = LIS2DUXS12_156_mg;
2510 break;
2511 }
2512 return ret;
2513 }
2514
2515 /**
2516 * @}
2517 *
2518 */
2519
2520
2521 /**
2522 * @defgroup Orientation 6D (and 4D)
2523 * @brief Orientation 6D (and 4D)
2524 * @{/
2525 *
2526 */
2527 /**
2528 * @brief configuration for 4D/6D function.[set]
2529 *
2530 * @param ctx read / write interface definitions
2531 * @param val 4D/6D, DEG_80, DEG_70, DEG_60, DEG_50,
2532 * @retval interface status (MANDATORY: return 0 -> no Error)
2533 *
2534 */
lis2duxs12_sixd_config_set(stmdev_ctx_t * ctx,lis2duxs12_sixd_config_t val)2535 int32_t lis2duxs12_sixd_config_set(stmdev_ctx_t *ctx, lis2duxs12_sixd_config_t val)
2536 {
2537 lis2duxs12_sixd_t sixd;
2538 int32_t ret;
2539
2540 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_SIXD, (uint8_t *)&sixd, 1);
2541
2542 if (ret == 0)
2543 {
2544 sixd.d4d_en = ((uint8_t)val.mode);
2545 sixd.d6d_ths = ((uint8_t)val.threshold);
2546 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_SIXD, (uint8_t *)&sixd, 1);
2547 }
2548
2549 return ret;
2550 }
2551
2552 /**
2553 * @brief configuration for 4D/6D function.[get]
2554 *
2555 * @param ctx read / write interface definitions
2556 * @param val 4D/6D, DEG_80, DEG_70, DEG_60, DEG_50,
2557 * @retval interface status (MANDATORY: return 0 -> no Error)
2558 *
2559 */
lis2duxs12_sixd_config_get(stmdev_ctx_t * ctx,lis2duxs12_sixd_config_t * val)2560 int32_t lis2duxs12_sixd_config_get(stmdev_ctx_t *ctx, lis2duxs12_sixd_config_t *val)
2561 {
2562 lis2duxs12_sixd_t sixd;
2563 int32_t ret;
2564
2565 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_SIXD, (uint8_t *)&sixd, 1);
2566
2567 val->mode = (enum mode)sixd.d4d_en;
2568
2569 switch ((sixd.d6d_ths))
2570 {
2571 case LIS2DUXS12_DEG_80:
2572 val->threshold = LIS2DUXS12_DEG_80;
2573 break;
2574
2575 case LIS2DUXS12_DEG_70:
2576 val->threshold = LIS2DUXS12_DEG_70;
2577 break;
2578
2579 case LIS2DUXS12_DEG_60:
2580 val->threshold = LIS2DUXS12_DEG_60;
2581 break;
2582
2583 case LIS2DUXS12_DEG_50:
2584 val->threshold = LIS2DUXS12_DEG_50;
2585 break;
2586
2587 default:
2588 val->threshold = LIS2DUXS12_DEG_80;
2589 break;
2590 }
2591
2592 return ret;
2593 }
2594
2595 /**
2596 * @}
2597 *
2598 */
2599
2600 /**
2601 * @defgroup wakeup configuration
2602 * @brief wakeup configuration
2603 * @{/
2604 *
2605 */
2606
2607 /**
2608 * @brief configuration for wakeup function.[set]
2609 *
2610 * @param ctx read / write interface definitions
2611 * @param val threshold, duration, ...
2612 * @retval interface status (MANDATORY: return 0 -> no Error)
2613 *
2614 */
lis2duxs12_wakeup_config_set(stmdev_ctx_t * ctx,lis2duxs12_wakeup_config_t val)2615 int32_t lis2duxs12_wakeup_config_set(stmdev_ctx_t *ctx, lis2duxs12_wakeup_config_t val)
2616 {
2617 lis2duxs12_wake_up_ths_t wup_ths;
2618 lis2duxs12_wake_up_dur_t wup_dur;
2619 lis2duxs12_wake_up_dur_ext_t wup_dur_ext;
2620 lis2duxs12_interrupt_cfg_t int_cfg;
2621 lis2duxs12_ctrl1_t ctrl1;
2622 lis2duxs12_ctrl4_t ctrl4;
2623 int32_t ret;
2624
2625 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_WAKE_UP_THS, (uint8_t *)&wup_ths, 1);
2626 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_WAKE_UP_DUR, (uint8_t *)&wup_dur, 1);
2627 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_WAKE_UP_DUR_EXT, (uint8_t *)&wup_dur_ext, 1);
2628 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_INTERRUPT_CFG, (uint8_t *)&int_cfg, 1);
2629 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1);
2630 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1);
2631
2632 if (ret == 0)
2633 {
2634 wup_dur.wake_dur = (uint8_t)val.wake_dur & 0x3U;
2635 wup_dur_ext.wu_dur_extended = (uint8_t)val.wake_dur >> 2;
2636 wup_dur.sleep_dur = val.sleep_dur;
2637
2638 int_cfg.wake_ths_w = val.wake_ths_weight;
2639 wup_ths.wk_ths = val.wake_ths;
2640 wup_ths.sleep_on = (uint8_t)val.wake_enable;
2641 ctrl4.inact_odr = (uint8_t)val.inact_odr;
2642
2643 if (val.wake_enable == LIS2DUXS12_SLEEP_ON) {
2644 ctrl1.wu_x_en = 1;
2645 ctrl1.wu_y_en = 1;
2646 ctrl1.wu_z_en = 1;
2647 } else {
2648 ctrl1.wu_x_en = 0;
2649 ctrl1.wu_y_en = 0;
2650 ctrl1.wu_z_en = 0;
2651 }
2652
2653 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_WAKE_UP_THS, (uint8_t *)&wup_ths, 1);
2654 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_WAKE_UP_DUR, (uint8_t *)&wup_dur, 1);
2655 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_WAKE_UP_DUR_EXT, (uint8_t *)&wup_dur_ext, 1);
2656 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_INTERRUPT_CFG, (uint8_t *)&int_cfg, 1);
2657 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1);
2658 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1);
2659 }
2660
2661 return ret;
2662 }
2663
2664 /**
2665 * @brief configuration for wakeup function.[get]
2666 *
2667 * @param ctx read / write interface definitions
2668 * @param val threshold, duration, ...
2669 * @retval interface status (MANDATORY: return 0 -> no Error)
2670 *
2671 */
lis2duxs12_wakeup_config_get(stmdev_ctx_t * ctx,lis2duxs12_wakeup_config_t * val)2672 int32_t lis2duxs12_wakeup_config_get(stmdev_ctx_t *ctx, lis2duxs12_wakeup_config_t *val)
2673 {
2674 lis2duxs12_wake_up_ths_t wup_ths;
2675 lis2duxs12_wake_up_dur_t wup_dur;
2676 lis2duxs12_wake_up_dur_ext_t wup_dur_ext;
2677 lis2duxs12_interrupt_cfg_t int_cfg;
2678 lis2duxs12_ctrl4_t ctrl4;
2679 int32_t ret;
2680
2681 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_WAKE_UP_THS, (uint8_t *)&wup_ths, 1);
2682 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_WAKE_UP_DUR, (uint8_t *)&wup_dur, 1);
2683 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_WAKE_UP_DUR_EXT, (uint8_t *)&wup_dur_ext, 1);
2684 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_INTERRUPT_CFG, (uint8_t *)&int_cfg, 1);
2685 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1);
2686
2687 if (ret == 0)
2688 {
2689 switch(wup_dur.wake_dur) {
2690 case 0x0:
2691 val->wake_dur = (wup_dur_ext.wu_dur_extended == 1U) ?
2692 LIS2DUXS12_3_ODR : LIS2DUXS12_0_ODR;
2693 break;
2694
2695 case 0x1:
2696 val->wake_dur = (wup_dur_ext.wu_dur_extended == 1U) ?
2697 LIS2DUXS12_7_ODR : LIS2DUXS12_1_ODR;
2698 break;
2699
2700 case 0x2:
2701 val->wake_dur = (wup_dur_ext.wu_dur_extended == 1U) ?
2702 LIS2DUXS12_11_ODR : LIS2DUXS12_2_ODR;
2703 break;
2704
2705 case 0x3:
2706 default:
2707 val->wake_dur = LIS2DUXS12_15_ODR;
2708 break;
2709 }
2710
2711 val->sleep_dur = wup_dur.sleep_dur;
2712
2713 val->wake_ths_weight = int_cfg.wake_ths_w;
2714 val->wake_ths = wup_ths.wk_ths;
2715 val->wake_enable = (enum wake_enable)wup_ths.sleep_on;
2716 val->inact_odr = (enum inact_odr)ctrl4.inact_odr;
2717 }
2718
2719 return ret;
2720 }
2721
2722 /**
2723 * @}
2724 *
2725 */
2726
lis2duxs12_tap_config_set(stmdev_ctx_t * ctx,lis2duxs12_tap_config_t val)2727 int32_t lis2duxs12_tap_config_set(stmdev_ctx_t *ctx, lis2duxs12_tap_config_t val)
2728 {
2729 lis2duxs12_tap_cfg0_t tap_cfg0;
2730 lis2duxs12_tap_cfg1_t tap_cfg1;
2731 lis2duxs12_tap_cfg2_t tap_cfg2;
2732 lis2duxs12_tap_cfg3_t tap_cfg3;
2733 lis2duxs12_tap_cfg4_t tap_cfg4;
2734 lis2duxs12_tap_cfg5_t tap_cfg5;
2735 lis2duxs12_tap_cfg6_t tap_cfg6;
2736 int32_t ret;
2737
2738 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2739 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
2740 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
2741 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_CFG3, (uint8_t *)&tap_cfg3, 1);
2742 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_CFG4, (uint8_t *)&tap_cfg4, 1);
2743 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_CFG5, (uint8_t *)&tap_cfg5, 1);
2744 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_CFG6, (uint8_t *)&tap_cfg6, 1);
2745
2746 if (ret == 0)
2747 {
2748 tap_cfg0.axis = (uint8_t)val.axis;
2749 tap_cfg0.invert_t = val.inverted_peak_time;
2750 tap_cfg1.pre_still_ths = val.pre_still_ths;
2751 tap_cfg3.post_still_ths = val.post_still_ths;
2752 tap_cfg1.post_still_t = val.post_still_time & 0xFU;
2753 tap_cfg2.post_still_t = val.post_still_time >> 4;
2754 tap_cfg2.wait_t = val.shock_wait_time;
2755 tap_cfg3.latency_t = val.latency;
2756 tap_cfg4.wait_end_latency = val.wait_end_latency;
2757 tap_cfg4.peak_ths = val.peak_ths;
2758 tap_cfg5.rebound_t = val.rebound;
2759 tap_cfg5.single_tap_en = val.single_tap_on;
2760 tap_cfg5.double_tap_en = val.double_tap_on;
2761 tap_cfg5.triple_tap_en = val.triple_tap_on;
2762 tap_cfg6.pre_still_st = val.pre_still_start;
2763 tap_cfg6.pre_still_n = val.pre_still_n;
2764
2765 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2766 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
2767 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
2768 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_TAP_CFG3, (uint8_t *)&tap_cfg3, 1);
2769 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_TAP_CFG4, (uint8_t *)&tap_cfg4, 1);
2770 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_TAP_CFG5, (uint8_t *)&tap_cfg5, 1);
2771 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_TAP_CFG6, (uint8_t *)&tap_cfg6, 1);
2772 }
2773
2774 return ret;
2775 }
2776
lis2duxs12_tap_config_get(stmdev_ctx_t * ctx,lis2duxs12_tap_config_t * val)2777 int32_t lis2duxs12_tap_config_get(stmdev_ctx_t *ctx, lis2duxs12_tap_config_t *val)
2778 {
2779 lis2duxs12_tap_cfg0_t tap_cfg0;
2780 lis2duxs12_tap_cfg1_t tap_cfg1;
2781 lis2duxs12_tap_cfg2_t tap_cfg2;
2782 lis2duxs12_tap_cfg3_t tap_cfg3;
2783 lis2duxs12_tap_cfg4_t tap_cfg4;
2784 lis2duxs12_tap_cfg5_t tap_cfg5;
2785 lis2duxs12_tap_cfg6_t tap_cfg6;
2786 int32_t ret;
2787
2788 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2789 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
2790 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
2791 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_CFG3, (uint8_t *)&tap_cfg3, 1);
2792 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_CFG4, (uint8_t *)&tap_cfg4, 1);
2793 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_CFG5, (uint8_t *)&tap_cfg5, 1);
2794 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_CFG6, (uint8_t *)&tap_cfg6, 1);
2795
2796 if (ret == 0)
2797 {
2798 val->axis = (enum axis)tap_cfg0.axis;
2799 val->inverted_peak_time = tap_cfg0.invert_t;
2800 val->pre_still_ths = tap_cfg1.pre_still_ths;
2801 val->post_still_ths = tap_cfg3.post_still_ths;
2802 val->post_still_time = (tap_cfg2.post_still_t << 4) | tap_cfg1.post_still_t;
2803 val->shock_wait_time = tap_cfg2.wait_t;
2804 val->latency = tap_cfg3.latency_t;
2805 val->wait_end_latency = tap_cfg4.wait_end_latency;
2806 val->peak_ths = tap_cfg4.peak_ths;
2807 val->rebound = tap_cfg5.rebound_t;
2808 val->single_tap_on = tap_cfg5.single_tap_en;
2809 val->double_tap_on = tap_cfg5.double_tap_en;
2810 val->triple_tap_on = tap_cfg5.triple_tap_en;
2811 val->pre_still_start = tap_cfg6.pre_still_st;
2812 val->pre_still_n = tap_cfg6.pre_still_n;
2813 }
2814
2815 return ret;
2816 }
2817
2818 /**
2819 * @}
2820 *
2821 */
2822
2823 /**
2824 * @defgroup lis2duxs12_Timestamp
2825 * @brief This section groups all the functions that manage the
2826 * timestamp generation.
2827 * @{
2828 *
2829 */
2830
2831 /**
2832 * @brief Enables timestamp counter.[set]
2833 *
2834 * @param ctx Read / write interface definitions.(ptr)
2835 * @param val Change the values of timestamp_en in reg INTERRUPT_CFG
2836 * @retval Interface status (MANDATORY: return 0 -> no Error).
2837 *
2838 */
lis2duxs12_timestamp_set(stmdev_ctx_t * ctx,uint8_t val)2839 int32_t lis2duxs12_timestamp_set(stmdev_ctx_t *ctx, uint8_t val)
2840 {
2841 lis2duxs12_interrupt_cfg_t int_cfg;
2842 int32_t ret;
2843
2844 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_INTERRUPT_CFG, (uint8_t *)&int_cfg, 1);
2845
2846 if (ret == 0)
2847 {
2848 int_cfg.timestamp_en = (uint8_t)val;
2849 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_INTERRUPT_CFG, (uint8_t *)&int_cfg, 1);
2850 }
2851
2852 return ret;
2853 }
2854
2855 /**
2856 * @brief Enables timestamp counter.[get]
2857 *
2858 * @param ctx Read / write interface definitions.(ptr)
2859 * @param val Change the values of timestamp_en in reg INTERRUPT_CFG
2860 * @retval Interface status (MANDATORY: return 0 -> no Error).
2861 *
2862 */
lis2duxs12_timestamp_get(stmdev_ctx_t * ctx,uint8_t * val)2863 int32_t lis2duxs12_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val)
2864 {
2865 lis2duxs12_interrupt_cfg_t int_cfg;
2866 int32_t ret;
2867
2868 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_INTERRUPT_CFG, (uint8_t *)&int_cfg, 1);
2869 *val = int_cfg.timestamp_en;
2870
2871 return ret;
2872 }
2873
2874 /**
2875 * @brief Timestamp first data output register (r).
2876 * The value is expressed as a 32-bit word and the bit resolution
2877 * is 10 us.[get]
2878 *
2879 * @param ctx Read / write interface definitions.(ptr)
2880 * @param buff Buffer that stores data read
2881 * @retval Interface status (MANDATORY: return 0 -> no Error).
2882 *
2883 */
lis2duxs12_timestamp_raw_get(stmdev_ctx_t * ctx,uint32_t * val)2884 int32_t lis2duxs12_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val)
2885 {
2886 uint8_t buff[4];
2887 int32_t ret;
2888
2889 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_TIMESTAMP0, buff, 4);
2890 *val = buff[3];
2891 *val = (*val * 256U) + buff[2];
2892 *val = (*val * 256U) + buff[1];
2893 *val = (*val * 256U) + buff[0];
2894
2895 return ret;
2896 }
2897
2898 /**
2899 * @}
2900 *
2901 */
2902
2903 /**
2904 * @defgroup LIS2DUXS12_finite_state_machine
2905 * @brief This section groups all the functions that manage the
2906 * state_machine.
2907 * @{
2908 *
2909 */
2910
2911 /**
2912 * @brief Interrupt status bit for FSM long counter timeout interrupt
2913 * event.[get]
2914 *
2915 * @param ctx Read / write interface definitions.(ptr)
2916 * @param val Change the values of is_fsm_lc in reg EMB_FUNC_STATUS
2917 * @retval Interface status (MANDATORY: return 0 -> no Error).
2918 *
2919 */
lis2duxs12_long_cnt_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)2920 int32_t lis2duxs12_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx,
2921 uint8_t *val)
2922 {
2923 lis2duxs12_emb_func_status_t emb_func_status;
2924 int32_t ret;
2925
2926 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
2927
2928 if (ret == 0)
2929 {
2930 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_STATUS,
2931 (uint8_t *)&emb_func_status, 1);
2932
2933 *val = emb_func_status.is_fsm_lc;
2934 }
2935
2936 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
2937
2938 return ret;
2939 }
2940
2941 /**
2942 * @brief Embedded final state machine functions mode.[set]
2943 *
2944 * @param ctx Read / write interface definitions.(ptr)
2945 * @param val Change the values of fsm_en in reg EMB_FUNC_EN_B
2946 * @retval Interface status (MANDATORY: return 0 -> no Error).
2947 *
2948 */
lis2duxs12_emb_fsm_en_set(stmdev_ctx_t * ctx,uint8_t val)2949 int32_t lis2duxs12_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val)
2950 {
2951 int32_t ret;
2952
2953 lis2duxs12_emb_func_en_b_t emb_func_en_b;
2954 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
2955
2956 if (ret == 0)
2957 {
2958 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B,
2959 (uint8_t *)&emb_func_en_b, 1);
2960
2961 emb_func_en_b.fsm_en = (uint8_t)val;
2962
2963 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B,
2964 (uint8_t *)&emb_func_en_b, 1);
2965 }
2966
2967 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
2968
2969 return ret;
2970 }
2971
2972 /**
2973 * @brief Embedded final state machine functions mode.[get]
2974 *
2975 * @param ctx Read / write interface definitions.(ptr)
2976 * @param val Get the values of fsm_en in reg EMB_FUNC_EN_B
2977 * @retval Interface status (MANDATORY: return 0 -> no Error).
2978 *
2979 */
lis2duxs12_emb_fsm_en_get(stmdev_ctx_t * ctx,uint8_t * val)2980 int32_t lis2duxs12_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val)
2981 {
2982 int32_t ret;
2983
2984 lis2duxs12_emb_func_en_b_t emb_func_en_b;
2985 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
2986
2987 if (ret == 0)
2988 {
2989 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B,
2990 (uint8_t *)&emb_func_en_b, 1);
2991
2992 *val = emb_func_en_b.fsm_en;
2993
2994 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B,
2995 (uint8_t *)&emb_func_en_b, 1);
2996 }
2997
2998 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
2999
3000 return ret;
3001 }
3002
3003 /**
3004 * @brief Embedded final state machine functions mode.[set]
3005 *
3006 * @param ctx Read / write interface definitions.(ptr)
3007 * @param val Structure of registers from FSM_ENABLE_A to FSM_ENABLE_B
3008 * @retval Interface status (MANDATORY: return 0 -> no Error).
3009 *
3010 */
lis2duxs12_fsm_enable_set(stmdev_ctx_t * ctx,lis2duxs12_emb_fsm_enable_t * val)3011 int32_t lis2duxs12_fsm_enable_set(stmdev_ctx_t *ctx,
3012 lis2duxs12_emb_fsm_enable_t *val)
3013 {
3014 lis2duxs12_emb_func_en_b_t emb_func_en_b;
3015 int32_t ret;
3016
3017 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
3018
3019 if (ret == 0)
3020 {
3021 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_FSM_ENABLE,
3022 (uint8_t *)&val->fsm_enable, 1);
3023 }
3024
3025 if (ret == 0)
3026 {
3027 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B,
3028 (uint8_t *)&emb_func_en_b, 1);
3029
3030 if ((val->fsm_enable.fsm1_en |
3031 val->fsm_enable.fsm2_en |
3032 val->fsm_enable.fsm3_en |
3033 val->fsm_enable.fsm4_en |
3034 val->fsm_enable.fsm5_en |
3035 val->fsm_enable.fsm6_en |
3036 val->fsm_enable.fsm7_en |
3037 val->fsm_enable.fsm8_en) != PROPERTY_DISABLE)
3038 {
3039 emb_func_en_b.fsm_en = PROPERTY_ENABLE;
3040 }
3041 else
3042 {
3043 emb_func_en_b.fsm_en = PROPERTY_DISABLE;
3044 }
3045
3046 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B,
3047 (uint8_t *)&emb_func_en_b, 1);
3048 }
3049
3050 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
3051
3052 return ret;
3053 }
3054
3055 /**
3056 * @brief Embedded final state machine functions mode.[get]
3057 *
3058 * @param ctx Read / write interface definitions.(ptr)
3059 * @param val Structure of registers from FSM_ENABLE_A to FSM_ENABLE_B
3060 * @retval Interface status (MANDATORY: return 0 -> no Error).
3061 *
3062 */
lis2duxs12_fsm_enable_get(stmdev_ctx_t * ctx,lis2duxs12_emb_fsm_enable_t * val)3063 int32_t lis2duxs12_fsm_enable_get(stmdev_ctx_t *ctx,
3064 lis2duxs12_emb_fsm_enable_t *val)
3065 {
3066 int32_t ret;
3067
3068 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
3069
3070 if (ret == 0)
3071 {
3072 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FSM_ENABLE,
3073 (uint8_t *)&val->fsm_enable, 1);
3074 }
3075
3076 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
3077
3078 return ret;
3079 }
3080
3081 /**
3082 * @brief FSM long counter status register. Long counter value is an
3083 * unsigned integer value (16-bit format).[set]
3084 *
3085 * @param ctx Read / write interface definitions.(ptr)
3086 * @param buff Buffer that contains data to write
3087 * @retval Interface status (MANDATORY: return 0 -> no Error).
3088 *
3089 */
lis2duxs12_long_cnt_set(stmdev_ctx_t * ctx,uint16_t val)3090 int32_t lis2duxs12_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val)
3091 {
3092 uint8_t buff[2];
3093 int32_t ret;
3094
3095 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
3096
3097 if (ret == 0)
3098 {
3099 buff[1] = (uint8_t)(val / 256U);
3100 buff[0] = (uint8_t)(val - (buff[1] * 256U));
3101 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_FSM_LONG_COUNTER_L, buff, 2);
3102 }
3103
3104 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
3105
3106 return ret;
3107 }
3108
3109 /**
3110 * @brief FSM long counter status register. Long counter value is an
3111 * unsigned integer value (16-bit format).[get]
3112 *
3113 * @param ctx Read / write interface definitions.(ptr)
3114 * @param buff Buffer that stores data read
3115 * @retval Interface status (MANDATORY: return 0 -> no Error).
3116 *
3117 */
lis2duxs12_long_cnt_get(stmdev_ctx_t * ctx,uint16_t * val)3118 int32_t lis2duxs12_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val)
3119 {
3120 uint8_t buff[2];
3121 int32_t ret;
3122
3123 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
3124
3125 if (ret == 0)
3126 {
3127 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FSM_LONG_COUNTER_L, buff, 2);
3128 *val = buff[1];
3129 *val = (*val * 256U) + buff[0];
3130 }
3131
3132 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
3133
3134 return ret;
3135 }
3136
3137 /**
3138 * @brief FSM status.[get]
3139 *
3140 * @param ctx read / write interface definitions
3141 * @param val register FSM_STATUS_MAINPAGE
3142 *
3143 */
lis2duxs12_fsm_status_get(stmdev_ctx_t * ctx,lis2duxs12_fsm_status_mainpage_t * val)3144 int32_t lis2duxs12_fsm_status_get(stmdev_ctx_t *ctx,
3145 lis2duxs12_fsm_status_mainpage_t *val)
3146 {
3147 return lis2duxs12_read_reg(ctx, LIS2DUXS12_FSM_STATUS_MAINPAGE,
3148 (uint8_t *) val, 1);
3149 }
3150
3151 /**
3152 * @brief FSM output registers.[get]
3153 *
3154 * @param ctx Read / write interface definitions.(ptr)
3155 * @param val Structure of registers from FSM_OUTS1 to FSM_OUTS16
3156 * @retval Interface status (MANDATORY: return 0 -> no Error).
3157 *
3158 */
lis2duxs12_fsm_out_get(stmdev_ctx_t * ctx,uint8_t * val)3159 int32_t lis2duxs12_fsm_out_get(stmdev_ctx_t *ctx, uint8_t *val)
3160 {
3161 int32_t ret;
3162
3163 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
3164
3165 if (ret == 0)
3166 {
3167 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FSM_OUTS1, val, 8);
3168 }
3169
3170 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
3171
3172 return ret;
3173 }
3174
3175 /**
3176 * @brief Finite State Machine ODR configuration.[set]
3177 *
3178 * @param ctx Read / write interface definitions.(ptr)
3179 * @param val Change the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
3180 * @retval Interface status (MANDATORY: return 0 -> no Error).
3181 *
3182 */
lis2duxs12_fsm_data_rate_set(stmdev_ctx_t * ctx,lis2duxs12_fsm_val_odr_t val)3183 int32_t lis2duxs12_fsm_data_rate_set(stmdev_ctx_t *ctx,
3184 lis2duxs12_fsm_val_odr_t val)
3185 {
3186 lis2duxs12_fsm_odr_t fsm_odr_reg;
3187 int32_t ret;
3188
3189 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
3190
3191 if (ret == 0)
3192 {
3193 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FSM_ODR,
3194 (uint8_t *)&fsm_odr_reg, 1);
3195
3196 fsm_odr_reg.fsm_odr = (uint8_t)val;
3197 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_FSM_ODR,
3198 (uint8_t *)&fsm_odr_reg, 1);
3199 }
3200
3201 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
3202
3203 return ret;
3204 }
3205
3206 /**
3207 * @brief Finite State Machine ODR configuration.[get]
3208 *
3209 * @param ctx Read / write interface definitions.(ptr)
3210 * @param val Get the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
3211 * @retval Interface status (MANDATORY: return 0 -> no Error).
3212 *
3213 */
lis2duxs12_fsm_data_rate_get(stmdev_ctx_t * ctx,lis2duxs12_fsm_val_odr_t * val)3214 int32_t lis2duxs12_fsm_data_rate_get(stmdev_ctx_t *ctx,
3215 lis2duxs12_fsm_val_odr_t *val)
3216 {
3217 lis2duxs12_fsm_odr_t fsm_odr_reg;
3218 int32_t ret;
3219
3220 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
3221
3222 if (ret == 0)
3223 {
3224 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FSM_ODR,
3225 (uint8_t *)&fsm_odr_reg, 1);
3226 }
3227
3228 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
3229
3230 switch (fsm_odr_reg.fsm_odr)
3231 {
3232 case LIS2DUXS12_ODR_FSM_12Hz5:
3233 *val = LIS2DUXS12_ODR_FSM_12Hz5;
3234 break;
3235
3236 case LIS2DUXS12_ODR_FSM_25Hz:
3237 *val = LIS2DUXS12_ODR_FSM_25Hz;
3238 break;
3239
3240 case LIS2DUXS12_ODR_FSM_50Hz:
3241 *val = LIS2DUXS12_ODR_FSM_50Hz;
3242 break;
3243
3244 case LIS2DUXS12_ODR_FSM_100Hz:
3245 *val = LIS2DUXS12_ODR_FSM_100Hz;
3246 break;
3247
3248 case LIS2DUXS12_ODR_FSM_200Hz:
3249 *val = LIS2DUXS12_ODR_FSM_200Hz;
3250 break;
3251
3252 case LIS2DUXS12_ODR_FSM_400Hz:
3253 *val = LIS2DUXS12_ODR_FSM_400Hz;
3254 break;
3255
3256 case LIS2DUXS12_ODR_FSM_800Hz:
3257 *val = LIS2DUXS12_ODR_FSM_800Hz;
3258 break;
3259
3260 default:
3261 *val = LIS2DUXS12_ODR_FSM_12Hz5;
3262 break;
3263 }
3264
3265 return ret;
3266 }
3267
3268 /**
3269 * @brief FSM initialization request.[set]
3270 *
3271 * @param ctx Read / write interface definitions.(ptr)
3272 * @param val Change the values of fsm_init in reg FSM_INIT
3273 * @retval Interface status (MANDATORY: return 0 -> no Error).
3274 *
3275 */
lis2duxs12_fsm_init_set(stmdev_ctx_t * ctx,uint8_t val)3276 int32_t lis2duxs12_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val)
3277 {
3278 lis2duxs12_emb_func_init_b_t emb_func_init_b;
3279 int32_t ret;
3280
3281 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
3282
3283 if (ret == 0)
3284 {
3285 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_INIT_B,
3286 (uint8_t *)&emb_func_init_b, 1);
3287
3288 emb_func_init_b.fsm_init = (uint8_t)val;
3289
3290 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_INIT_B,
3291 (uint8_t *)&emb_func_init_b, 1);
3292 }
3293
3294 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
3295
3296 return ret;
3297 }
3298
3299 /**
3300 * @brief FSM initialization request.[get]
3301 *
3302 * @param ctx Read / write interface definitions.(ptr)
3303 * @param val Change the values of fsm_init in reg FSM_INIT
3304 * @retval Interface status (MANDATORY: return 0 -> no Error).
3305 *
3306 */
lis2duxs12_fsm_init_get(stmdev_ctx_t * ctx,uint8_t * val)3307 int32_t lis2duxs12_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val)
3308 {
3309 lis2duxs12_emb_func_init_b_t emb_func_init_b;
3310 int32_t ret;
3311
3312 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
3313
3314 if (ret == 0)
3315 {
3316 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_INIT_B,
3317 (uint8_t *)&emb_func_init_b, 1);
3318
3319 *val = emb_func_init_b.fsm_init;
3320 }
3321
3322 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
3323
3324 return ret;
3325 }
3326
3327 /**
3328 * @brief FSM long counter timeout register (r/w). The long counter
3329 * timeout value is an unsigned integer value (16-bit format).
3330 * When the long counter value reached this value, the FSM
3331 * generates an interrupt.[set]
3332 *
3333 * @param ctx Read / write interface definitions.(ptr)
3334 * @param buff Buffer that contains data to write
3335 * @retval Interface status (MANDATORY: return 0 -> no Error).
3336 *
3337 */
lis2duxs12_long_cnt_int_value_set(stmdev_ctx_t * ctx,uint16_t val)3338 int32_t lis2duxs12_long_cnt_int_value_set(stmdev_ctx_t *ctx,
3339 uint16_t val)
3340 {
3341 uint8_t buff[2];
3342 int32_t ret;
3343
3344 buff[1] = (uint8_t)(val / 256U);
3345 buff[0] = (uint8_t)(val - (buff[1] * 256U));
3346 ret = lis2duxs12_ln_pg_write(ctx, LIS2DUXS12_FSM_LC_TIMEOUT_L, buff, 2);
3347
3348 return ret;
3349 }
3350
3351 /**
3352 * @brief FSM long counter timeout register (r/w). The long counter
3353 * timeout value is an unsigned integer value (16-bit format).
3354 * When the long counter value reached this value, the FSM generates
3355 * an interrupt.[get]
3356 *
3357 * @param ctx Read / write interface definitions.(ptr)
3358 * @param buff Buffer that stores data read
3359 * @retval Interface status (MANDATORY: return 0 -> no Error).
3360 *
3361 */
lis2duxs12_long_cnt_int_value_get(stmdev_ctx_t * ctx,uint16_t * val)3362 int32_t lis2duxs12_long_cnt_int_value_get(stmdev_ctx_t *ctx,
3363 uint16_t *val)
3364 {
3365 uint8_t buff[2];
3366 int32_t ret;
3367
3368 ret = lis2duxs12_ln_pg_read(ctx, LIS2DUXS12_FSM_LC_TIMEOUT_L, buff, 2);
3369 *val = buff[1];
3370 *val = (*val * 256U) + buff[0];
3371
3372 return ret;
3373 }
3374
3375 /**
3376 * @brief FSM number of programs register.[set]
3377 *
3378 * @param ctx Read / write interface definitions.(ptr)
3379 * @param buff Buffer that contains data to write
3380 * @retval Interface status (MANDATORY: return 0 -> no Error).
3381 *
3382 */
lis2duxs12_fsm_number_of_programs_set(stmdev_ctx_t * ctx,uint8_t * buff)3383 int32_t lis2duxs12_fsm_number_of_programs_set(stmdev_ctx_t *ctx,
3384 uint8_t *buff)
3385 {
3386 int32_t ret;
3387
3388 ret = lis2duxs12_ln_pg_write(ctx, LIS2DUXS12_FSM_PROGRAMS, buff, 2);
3389
3390 return ret;
3391 }
3392
3393 /**
3394 * @brief FSM number of programs register.[get]
3395 *
3396 * @param ctx Read / write interface definitions.(ptr)
3397 * @param buff Buffer that stores data read
3398 * @retval Interface status (MANDATORY: return 0 -> no Error).
3399 *
3400 */
lis2duxs12_fsm_number_of_programs_get(stmdev_ctx_t * ctx,uint8_t * buff)3401 int32_t lis2duxs12_fsm_number_of_programs_get(stmdev_ctx_t *ctx,
3402 uint8_t *buff)
3403 {
3404 int32_t ret;
3405
3406 ret = lis2duxs12_ln_pg_read(ctx, LIS2DUXS12_FSM_PROGRAMS, buff, 2);
3407
3408 return ret;
3409 }
3410
3411 /**
3412 * @brief FSM start address register (r/w). First available address is
3413 * 0x033C.[set]
3414 *
3415 * @param ctx Read / write interface definitions.(ptr)
3416 * @param buff Buffer that contains data to write
3417 * @retval Interface status (MANDATORY: return 0 -> no Error).
3418 *
3419 */
lis2duxs12_fsm_start_address_set(stmdev_ctx_t * ctx,uint16_t val)3420 int32_t lis2duxs12_fsm_start_address_set(stmdev_ctx_t *ctx,
3421 uint16_t val)
3422 {
3423 uint8_t buff[2];
3424 int32_t ret;
3425
3426 buff[1] = (uint8_t)(val / 256U);
3427 buff[0] = (uint8_t)(val - (buff[1] * 256U));
3428 ret = lis2duxs12_ln_pg_write(ctx, LIS2DUXS12_FSM_START_ADD_L, buff, 2);
3429
3430 return ret;
3431 }
3432
3433 /**
3434 * @brief FSM start address register (r/w). First available address
3435 * is 0x033C.[get]
3436 *
3437 * @param ctx Read / write interface definitions.(ptr)
3438 * @param buff Buffer that stores data read
3439 * @retval Interface status (MANDATORY: return 0 -> no Error).
3440 *
3441 */
lis2duxs12_fsm_start_address_get(stmdev_ctx_t * ctx,uint16_t * val)3442 int32_t lis2duxs12_fsm_start_address_get(stmdev_ctx_t *ctx,
3443 uint16_t *val)
3444 {
3445 uint8_t buff[2];
3446 int32_t ret;
3447
3448 ret = lis2duxs12_ln_pg_read(ctx, LIS2DUXS12_FSM_START_ADD_L, buff, 2);
3449 *val = buff[1];
3450 *val = (*val * 256U) + buff[0];
3451
3452 return ret;
3453 }
3454
3455 /**
3456 * @}
3457 *
3458 */
3459
3460 /**
3461 * @addtogroup Machine Learning Core
3462 * @brief This section group all the functions concerning the
3463 * usage of Machine Learning Core
3464 * @{
3465 *
3466 */
3467
3468 /**
3469 * @brief Enable Machine Learning Core.[set]
3470 *
3471 * @param ctx read / write interface definitions
3472 * @param val change the values of mlc_en in
3473 * reg EMB_FUNC_EN_B and mlc_before_fsm_en
3474 * in EMB_FUNC_INIT_A
3475 *
3476 */
lis2duxs12_mlc_set(stmdev_ctx_t * ctx,lis2duxs12_mlc_mode_t val)3477 int32_t lis2duxs12_mlc_set(stmdev_ctx_t *ctx, lis2duxs12_mlc_mode_t val)
3478 {
3479 lis2duxs12_emb_func_en_a_t emb_en_a;
3480 lis2duxs12_emb_func_en_b_t emb_en_b;
3481 int32_t ret;
3482
3483 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
3484
3485 if (ret == 0)
3486 {
3487 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1);
3488 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1);
3489
3490 switch(val)
3491 {
3492 case LIS2DUXS12_MLC_OFF:
3493 emb_en_a.mlc_before_fsm_en = 0;
3494 emb_en_b.mlc_en = 0;
3495 break;
3496 case LIS2DUXS12_MLC_ON:
3497 emb_en_a.mlc_before_fsm_en = 0;
3498 emb_en_b.mlc_en = 1;
3499 break;
3500 case LIS2DUXS12_MLC_ON_BEFORE_FSM:
3501 emb_en_a.mlc_before_fsm_en = 1;
3502 emb_en_b.mlc_en = 0;
3503 break;
3504 default:
3505 break;
3506 }
3507
3508 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1);
3509 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1);
3510 }
3511
3512 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
3513
3514 return ret;
3515 }
3516
3517 /**
3518 * @brief Enable Machine Learning Core.[get]
3519 *
3520 * @param ctx read / write interface definitions
3521 * @param val get the values of mlc_en in
3522 * reg EMB_FUNC_EN_B and mlc_before_fsm_en
3523 * in EMB_FUNC_INIT_A
3524 *
3525 */
lis2duxs12_mlc_get(stmdev_ctx_t * ctx,lis2duxs12_mlc_mode_t * val)3526 int32_t lis2duxs12_mlc_get(stmdev_ctx_t *ctx, lis2duxs12_mlc_mode_t *val)
3527 {
3528 lis2duxs12_emb_func_en_a_t emb_en_a;
3529 lis2duxs12_emb_func_en_b_t emb_en_b;
3530 int32_t ret;
3531
3532 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
3533
3534 if (ret == 0)
3535 {
3536 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1);
3537 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1);
3538
3539 if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 0U)
3540 {
3541 *val = LIS2DUXS12_MLC_OFF;
3542 }
3543 else if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 1U)
3544 {
3545 *val = LIS2DUXS12_MLC_ON;
3546 }
3547 else if (emb_en_a.mlc_before_fsm_en == 1U)
3548 {
3549 *val = LIS2DUXS12_MLC_ON_BEFORE_FSM;
3550 }
3551 else
3552 {
3553 /* Do nothing */
3554 }
3555 }
3556
3557 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
3558
3559 return ret;
3560 }
3561
3562 /**
3563 * @brief Machine Learning Core status register[get]
3564 *
3565 * @param ctx read / write interface definitions
3566 * @param val register MLC_STATUS_MAINPAGE
3567 *
3568 */
lis2duxs12_mlc_status_get(stmdev_ctx_t * ctx,lis2duxs12_mlc_status_mainpage_t * val)3569 int32_t lis2duxs12_mlc_status_get(stmdev_ctx_t *ctx,
3570 lis2duxs12_mlc_status_mainpage_t *val)
3571 {
3572 return lis2duxs12_read_reg(ctx, LIS2DUXS12_MLC_STATUS_MAINPAGE,
3573 (uint8_t *) val, 1);
3574 }
3575
3576 /**
3577 * @brief prgsens_out: [get] Output value of all MLCx decision trees.
3578 *
3579 * @param ctx_t *ctx: read / write interface definitions
3580 * @param uint8_t * : buffer that stores data read
3581 *
3582 */
lis2duxs12_mlc_out_get(stmdev_ctx_t * ctx,uint8_t * buff)3583 int32_t lis2duxs12_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff)
3584 {
3585 int32_t ret;
3586
3587 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
3588
3589 if (ret == 0)
3590 {
3591 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_MLC1_SRC, buff, 4);
3592 }
3593
3594 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
3595
3596 return ret;
3597 }
3598
3599 /**
3600 * @brief Machine Learning Core data rate selection.[set]
3601 *
3602 * @param ctx read / write interface definitions
3603 * @param val get the values of mlc_odr in
3604 * reg EMB_FUNC_ODR_CFG_C
3605 *
3606 */
lis2duxs12_mlc_data_rate_set(stmdev_ctx_t * ctx,lis2duxs12_mlc_odr_val_t val)3607 int32_t lis2duxs12_mlc_data_rate_set(stmdev_ctx_t *ctx,
3608 lis2duxs12_mlc_odr_val_t val)
3609 {
3610 lis2duxs12_mlc_odr_t reg;
3611 int32_t ret;
3612
3613 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
3614
3615 if (ret == 0)
3616 {
3617 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_MLC_ODR, (uint8_t *)®, 1);
3618 reg.mlc_odr = (uint8_t)val;
3619 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_MLC_ODR, (uint8_t *)®, 1);
3620 }
3621
3622 if (ret == 0)
3623 {
3624 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
3625 }
3626
3627 return ret;
3628 }
3629
3630 /**
3631 * @brief Machine Learning Core data rate selection.[get]
3632 *
3633 * @param ctx read / write interface definitions
3634 * @param val change the values of mlc_odr in
3635 * reg EMB_FUNC_ODR_CFG_C
3636 *
3637 */
lis2duxs12_mlc_data_rate_get(stmdev_ctx_t * ctx,lis2duxs12_mlc_odr_val_t * val)3638 int32_t lis2duxs12_mlc_data_rate_get(stmdev_ctx_t *ctx,
3639 lis2duxs12_mlc_odr_val_t *val)
3640 {
3641 lis2duxs12_mlc_odr_t reg;
3642 int32_t ret;
3643
3644 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
3645
3646 if (ret == 0)
3647 {
3648 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_MLC_ODR, (uint8_t *)®, 1);
3649
3650 switch (reg.mlc_odr)
3651 {
3652 case LIS2DUXS12_ODR_PRGS_12Hz5:
3653 *val = LIS2DUXS12_ODR_PRGS_12Hz5;
3654 break;
3655
3656 case LIS2DUXS12_ODR_PRGS_25Hz:
3657 *val = LIS2DUXS12_ODR_PRGS_25Hz;
3658 break;
3659
3660 case LIS2DUXS12_ODR_PRGS_50Hz:
3661 *val = LIS2DUXS12_ODR_PRGS_50Hz;
3662 break;
3663
3664 case LIS2DUXS12_ODR_PRGS_100Hz:
3665 *val = LIS2DUXS12_ODR_PRGS_100Hz;
3666 break;
3667
3668 case LIS2DUXS12_ODR_PRGS_200Hz:
3669 *val = LIS2DUXS12_ODR_PRGS_200Hz;
3670 break;
3671
3672 default:
3673 *val = LIS2DUXS12_ODR_PRGS_12Hz5;
3674 break;
3675 }
3676 }
3677
3678 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
3679
3680 return ret;
3681 }
3682
3683 /**
3684 * @}
3685 *
3686 */
3687
3688 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
3689
