1 /** 2 ****************************************************************************** 3 * @file lsm6dso_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * lsm6dso_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef LSM6DSO_REGS_H 23 #define LSM6DSO_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup LSM6DSO 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 115 typedef struct 116 { 117 /** Component mandatory fields **/ 118 stmdev_write_ptr write_reg; 119 stmdev_read_ptr read_reg; 120 /** Customizable optional pointer **/ 121 void *handle; 122 } stmdev_ctx_t; 123 124 /** 125 * @} 126 * 127 */ 128 129 #endif /* MEMS_SHARED_TYPES */ 130 131 #ifndef MEMS_UCF_SHARED_TYPES 132 #define MEMS_UCF_SHARED_TYPES 133 134 /** @defgroup Generic address-data structure definition 135 * @brief This structure is useful to load a predefined configuration 136 * of a sensor. 137 * You can create a sensor configuration by your own or using 138 * Unico / Unicleo tools available on STMicroelectronics 139 * web site. 140 * 141 * @{ 142 * 143 */ 144 145 typedef struct 146 { 147 uint8_t address; 148 uint8_t data; 149 } ucf_line_t; 150 151 /** 152 * @} 153 * 154 */ 155 156 #endif /* MEMS_UCF_SHARED_TYPES */ 157 158 /** 159 * @} 160 * 161 */ 162 163 /** @defgroup LSM6DSO_Infos 164 * @{ 165 * 166 */ 167 168 /** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ 169 #define LSM6DSO_I2C_ADD_L 0xD5 170 #define LSM6DSO_I2C_ADD_H 0xD7 171 172 /** Device Identification (Who am I) **/ 173 #define LSM6DSO_ID 0x6C 174 175 /** 176 * @} 177 * 178 */ 179 180 #define LSM6DSO_FUNC_CFG_ACCESS 0x01U 181 typedef struct 182 { 183 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 184 uint8_t not_used_01 : 6; 185 uint8_t reg_access : 186 2; /* shub_reg_access + func_cfg_access */ 187 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 188 uint8_t reg_access : 189 2; /* shub_reg_access + func_cfg_access */ 190 uint8_t not_used_01 : 6; 191 #endif /* DRV_BYTE_ORDER */ 192 } lsm6dso_func_cfg_access_t; 193 194 #define LSM6DSO_PIN_CTRL 0x02U 195 typedef struct 196 { 197 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 198 uint8_t not_used_01 : 6; 199 uint8_t sdo_pu_en : 1; 200 uint8_t ois_pu_dis : 1; 201 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 202 uint8_t ois_pu_dis : 1; 203 uint8_t sdo_pu_en : 1; 204 uint8_t not_used_01 : 6; 205 #endif /* DRV_BYTE_ORDER */ 206 } lsm6dso_pin_ctrl_t; 207 208 #define LSM6DSO_FIFO_CTRL1 0x07U 209 typedef struct 210 { 211 uint8_t wtm : 8; 212 } lsm6dso_fifo_ctrl1_t; 213 214 #define LSM6DSO_FIFO_CTRL2 0x08U 215 typedef struct 216 { 217 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 218 uint8_t wtm : 1; 219 uint8_t uncoptr_rate : 2; 220 uint8_t not_used_01 : 1; 221 uint8_t odrchg_en : 1; 222 uint8_t not_used_02 : 1; 223 uint8_t fifo_compr_rt_en : 1; 224 uint8_t stop_on_wtm : 1; 225 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 226 uint8_t stop_on_wtm : 1; 227 uint8_t fifo_compr_rt_en : 1; 228 uint8_t not_used_02 : 1; 229 uint8_t odrchg_en : 1; 230 uint8_t not_used_01 : 1; 231 uint8_t uncoptr_rate : 2; 232 uint8_t wtm : 1; 233 #endif /* DRV_BYTE_ORDER */ 234 } lsm6dso_fifo_ctrl2_t; 235 236 #define LSM6DSO_FIFO_CTRL3 0x09U 237 typedef struct 238 { 239 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 240 uint8_t bdr_xl : 4; 241 uint8_t bdr_gy : 4; 242 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 243 uint8_t bdr_gy : 4; 244 uint8_t bdr_xl : 4; 245 #endif /* DRV_BYTE_ORDER */ 246 } lsm6dso_fifo_ctrl3_t; 247 248 #define LSM6DSO_FIFO_CTRL4 0x0AU 249 typedef struct 250 { 251 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 252 uint8_t fifo_mode : 3; 253 uint8_t not_used_01 : 1; 254 uint8_t odr_t_batch : 2; 255 uint8_t odr_ts_batch : 2; 256 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 257 uint8_t odr_ts_batch : 2; 258 uint8_t odr_t_batch : 2; 259 uint8_t not_used_01 : 1; 260 uint8_t fifo_mode : 3; 261 #endif /* DRV_BYTE_ORDER */ 262 } lsm6dso_fifo_ctrl4_t; 263 264 #define LSM6DSO_COUNTER_BDR_REG1 0x0BU 265 typedef struct 266 { 267 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 268 uint8_t cnt_bdr_th : 3; 269 uint8_t not_used_01 : 2; 270 uint8_t trig_counter_bdr : 1; 271 uint8_t rst_counter_bdr : 1; 272 uint8_t dataready_pulsed : 1; 273 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 274 uint8_t dataready_pulsed : 1; 275 uint8_t rst_counter_bdr : 1; 276 uint8_t trig_counter_bdr : 1; 277 uint8_t not_used_01 : 2; 278 uint8_t cnt_bdr_th : 3; 279 #endif /* DRV_BYTE_ORDER */ 280 } lsm6dso_counter_bdr_reg1_t; 281 282 #define LSM6DSO_COUNTER_BDR_REG2 0x0CU 283 typedef struct 284 { 285 uint8_t cnt_bdr_th : 8; 286 } lsm6dso_counter_bdr_reg2_t; 287 288 #define LSM6DSO_INT1_CTRL 0x0D 289 typedef struct 290 { 291 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 292 uint8_t int1_drdy_xl : 1; 293 uint8_t int1_drdy_g : 1; 294 uint8_t int1_boot : 1; 295 uint8_t int1_fifo_th : 1; 296 uint8_t int1_fifo_ovr : 1; 297 uint8_t int1_fifo_full : 1; 298 uint8_t int1_cnt_bdr : 1; 299 uint8_t den_drdy_flag : 1; 300 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 301 uint8_t den_drdy_flag : 1; 302 uint8_t int1_cnt_bdr : 1; 303 uint8_t int1_fifo_full : 1; 304 uint8_t int1_fifo_ovr : 1; 305 uint8_t int1_fifo_th : 1; 306 uint8_t int1_boot : 1; 307 uint8_t int1_drdy_g : 1; 308 uint8_t int1_drdy_xl : 1; 309 #endif /* DRV_BYTE_ORDER */ 310 } lsm6dso_int1_ctrl_t; 311 312 #define LSM6DSO_INT2_CTRL 0x0EU 313 typedef struct 314 { 315 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 316 uint8_t int2_drdy_xl : 1; 317 uint8_t int2_drdy_g : 1; 318 uint8_t int2_drdy_temp : 1; 319 uint8_t int2_fifo_th : 1; 320 uint8_t int2_fifo_ovr : 1; 321 uint8_t int2_fifo_full : 1; 322 uint8_t int2_cnt_bdr : 1; 323 uint8_t not_used_01 : 1; 324 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 325 uint8_t not_used_01 : 1; 326 uint8_t int2_cnt_bdr : 1; 327 uint8_t int2_fifo_full : 1; 328 uint8_t int2_fifo_ovr : 1; 329 uint8_t int2_fifo_th : 1; 330 uint8_t int2_drdy_temp : 1; 331 uint8_t int2_drdy_g : 1; 332 uint8_t int2_drdy_xl : 1; 333 #endif /* DRV_BYTE_ORDER */ 334 } lsm6dso_int2_ctrl_t; 335 336 #define LSM6DSO_WHO_AM_I 0x0FU 337 #define LSM6DSO_CTRL1_XL 0x10U 338 typedef struct 339 { 340 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 341 uint8_t not_used_01 : 1; 342 uint8_t lpf2_xl_en : 1; 343 uint8_t fs_xl : 2; 344 uint8_t odr_xl : 4; 345 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 346 uint8_t odr_xl : 4; 347 uint8_t fs_xl : 2; 348 uint8_t lpf2_xl_en : 1; 349 uint8_t not_used_01 : 1; 350 #endif /* DRV_BYTE_ORDER */ 351 } lsm6dso_ctrl1_xl_t; 352 353 #define LSM6DSO_CTRL2_G 0x11U 354 typedef struct 355 { 356 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 357 uint8_t not_used_01 : 1; 358 uint8_t fs_g : 3; /* fs_125 + fs_g */ 359 uint8_t odr_g : 4; 360 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 361 uint8_t odr_g : 4; 362 uint8_t fs_g : 3; /* fs_125 + fs_g */ 363 uint8_t not_used_01 : 1; 364 #endif /* DRV_BYTE_ORDER */ 365 } lsm6dso_ctrl2_g_t; 366 367 #define LSM6DSO_CTRL3_C 0x12U 368 typedef struct 369 { 370 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 371 uint8_t sw_reset : 1; 372 uint8_t not_used_01 : 1; 373 uint8_t if_inc : 1; 374 uint8_t sim : 1; 375 uint8_t pp_od : 1; 376 uint8_t h_lactive : 1; 377 uint8_t bdu : 1; 378 uint8_t boot : 1; 379 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 380 uint8_t boot : 1; 381 uint8_t bdu : 1; 382 uint8_t h_lactive : 1; 383 uint8_t pp_od : 1; 384 uint8_t sim : 1; 385 uint8_t if_inc : 1; 386 uint8_t not_used_01 : 1; 387 uint8_t sw_reset : 1; 388 #endif /* DRV_BYTE_ORDER */ 389 } lsm6dso_ctrl3_c_t; 390 391 #define LSM6DSO_CTRL4_C 0x13U 392 typedef struct 393 { 394 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 395 uint8_t not_used_01 : 1; 396 uint8_t lpf1_sel_g : 1; 397 uint8_t i2c_disable : 1; 398 uint8_t drdy_mask : 1; 399 uint8_t not_used_02 : 1; 400 uint8_t int2_on_int1 : 1; 401 uint8_t sleep_g : 1; 402 uint8_t not_used_03 : 1; 403 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 404 uint8_t not_used_03 : 1; 405 uint8_t sleep_g : 1; 406 uint8_t int2_on_int1 : 1; 407 uint8_t not_used_02 : 1; 408 uint8_t drdy_mask : 1; 409 uint8_t i2c_disable : 1; 410 uint8_t lpf1_sel_g : 1; 411 uint8_t not_used_01 : 1; 412 #endif /* DRV_BYTE_ORDER */ 413 } lsm6dso_ctrl4_c_t; 414 415 #define LSM6DSO_CTRL5_C 0x14U 416 typedef struct 417 { 418 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 419 uint8_t st_xl : 2; 420 uint8_t st_g : 2; 421 uint8_t not_used_01 : 1; 422 uint8_t rounding : 2; 423 uint8_t xl_ulp_en : 1; 424 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 425 uint8_t xl_ulp_en : 1; 426 uint8_t rounding : 2; 427 uint8_t not_used_01 : 1; 428 uint8_t st_g : 2; 429 uint8_t st_xl : 2; 430 #endif /* DRV_BYTE_ORDER */ 431 } lsm6dso_ctrl5_c_t; 432 433 #define LSM6DSO_CTRL6_C 0x15U 434 typedef struct 435 { 436 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 437 uint8_t ftype : 3; 438 uint8_t usr_off_w : 1; 439 uint8_t xl_hm_mode : 1; 440 uint8_t den_mode : 441 3; /* trig_en + lvl1_en + lvl2_en */ 442 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 443 uint8_t den_mode : 444 3; /* trig_en + lvl1_en + lvl2_en */ 445 uint8_t xl_hm_mode : 1; 446 uint8_t usr_off_w : 1; 447 uint8_t ftype : 3; 448 #endif /* DRV_BYTE_ORDER */ 449 } lsm6dso_ctrl6_c_t; 450 451 #define LSM6DSO_CTRL7_G 0x16U 452 typedef struct 453 { 454 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 455 uint8_t ois_on : 1; 456 uint8_t usr_off_on_out : 1; 457 uint8_t ois_on_en : 1; 458 uint8_t not_used_01 : 1; 459 uint8_t hpm_g : 2; 460 uint8_t hp_en_g : 1; 461 uint8_t g_hm_mode : 1; 462 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 463 uint8_t g_hm_mode : 1; 464 uint8_t hp_en_g : 1; 465 uint8_t hpm_g : 2; 466 uint8_t not_used_01 : 1; 467 uint8_t ois_on_en : 1; 468 uint8_t usr_off_on_out : 1; 469 uint8_t ois_on : 1; 470 #endif /* DRV_BYTE_ORDER */ 471 } lsm6dso_ctrl7_g_t; 472 473 #define LSM6DSO_CTRL8_XL 0x17U 474 typedef struct 475 { 476 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 477 uint8_t low_pass_on_6d : 1; 478 uint8_t xl_fs_mode : 1; 479 uint8_t hp_slope_xl_en : 1; 480 uint8_t fastsettl_mode_xl : 1; 481 uint8_t hp_ref_mode_xl : 1; 482 uint8_t hpcf_xl : 3; 483 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 484 uint8_t hpcf_xl : 3; 485 uint8_t hp_ref_mode_xl : 1; 486 uint8_t fastsettl_mode_xl : 1; 487 uint8_t hp_slope_xl_en : 1; 488 uint8_t xl_fs_mode : 1; 489 uint8_t low_pass_on_6d : 1; 490 #endif /* DRV_BYTE_ORDER */ 491 } lsm6dso_ctrl8_xl_t; 492 493 #define LSM6DSO_CTRL9_XL 0x18U 494 typedef struct 495 { 496 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 497 uint8_t not_used_01 : 1; 498 uint8_t i3c_disable : 1; 499 uint8_t den_lh : 1; 500 uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */ 501 uint8_t den_z : 1; 502 uint8_t den_y : 1; 503 uint8_t den_x : 1; 504 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 505 uint8_t den_x : 1; 506 uint8_t den_y : 1; 507 uint8_t den_z : 1; 508 uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */ 509 uint8_t den_lh : 1; 510 uint8_t i3c_disable : 1; 511 uint8_t not_used_01 : 1; 512 #endif /* DRV_BYTE_ORDER */ 513 } lsm6dso_ctrl9_xl_t; 514 515 #define LSM6DSO_CTRL10_C 0x19U 516 typedef struct 517 { 518 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 519 uint8_t not_used_01 : 5; 520 uint8_t timestamp_en : 1; 521 uint8_t not_used_02 : 2; 522 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 523 uint8_t not_used_02 : 2; 524 uint8_t timestamp_en : 1; 525 uint8_t not_used_01 : 5; 526 #endif /* DRV_BYTE_ORDER */ 527 } lsm6dso_ctrl10_c_t; 528 529 #define LSM6DSO_ALL_INT_SRC 0x1AU 530 typedef struct 531 { 532 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 533 uint8_t ff_ia : 1; 534 uint8_t wu_ia : 1; 535 uint8_t single_tap : 1; 536 uint8_t double_tap : 1; 537 uint8_t d6d_ia : 1; 538 uint8_t sleep_change_ia : 1; 539 uint8_t not_used_01 : 1; 540 uint8_t timestamp_endcount : 1; 541 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 542 uint8_t timestamp_endcount : 1; 543 uint8_t not_used_01 : 1; 544 uint8_t sleep_change_ia : 1; 545 uint8_t d6d_ia : 1; 546 uint8_t double_tap : 1; 547 uint8_t single_tap : 1; 548 uint8_t wu_ia : 1; 549 uint8_t ff_ia : 1; 550 #endif /* DRV_BYTE_ORDER */ 551 } lsm6dso_all_int_src_t; 552 553 #define LSM6DSO_WAKE_UP_SRC 0x1BU 554 typedef struct 555 { 556 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 557 uint8_t z_wu : 1; 558 uint8_t y_wu : 1; 559 uint8_t x_wu : 1; 560 uint8_t wu_ia : 1; 561 uint8_t sleep_state : 1; 562 uint8_t ff_ia : 1; 563 uint8_t sleep_change_ia : 1; 564 uint8_t not_used_01 : 1; 565 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 566 uint8_t not_used_01 : 1; 567 uint8_t sleep_change_ia : 1; 568 uint8_t ff_ia : 1; 569 uint8_t sleep_state : 1; 570 uint8_t wu_ia : 1; 571 uint8_t x_wu : 1; 572 uint8_t y_wu : 1; 573 uint8_t z_wu : 1; 574 #endif /* DRV_BYTE_ORDER */ 575 } lsm6dso_wake_up_src_t; 576 577 #define LSM6DSO_TAP_SRC 0x1CU 578 typedef struct 579 { 580 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 581 uint8_t z_tap : 1; 582 uint8_t y_tap : 1; 583 uint8_t x_tap : 1; 584 uint8_t tap_sign : 1; 585 uint8_t double_tap : 1; 586 uint8_t single_tap : 1; 587 uint8_t tap_ia : 1; 588 uint8_t not_used_02 : 1; 589 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 590 uint8_t not_used_02 : 1; 591 uint8_t tap_ia : 1; 592 uint8_t single_tap : 1; 593 uint8_t double_tap : 1; 594 uint8_t tap_sign : 1; 595 uint8_t x_tap : 1; 596 uint8_t y_tap : 1; 597 uint8_t z_tap : 1; 598 #endif /* DRV_BYTE_ORDER */ 599 } lsm6dso_tap_src_t; 600 601 #define LSM6DSO_D6D_SRC 0x1DU 602 typedef struct 603 { 604 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 605 uint8_t xl : 1; 606 uint8_t xh : 1; 607 uint8_t yl : 1; 608 uint8_t yh : 1; 609 uint8_t zl : 1; 610 uint8_t zh : 1; 611 uint8_t d6d_ia : 1; 612 uint8_t den_drdy : 1; 613 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 614 uint8_t den_drdy : 1; 615 uint8_t d6d_ia : 1; 616 uint8_t zh : 1; 617 uint8_t zl : 1; 618 uint8_t yh : 1; 619 uint8_t yl : 1; 620 uint8_t xh : 1; 621 uint8_t xl : 1; 622 #endif /* DRV_BYTE_ORDER */ 623 } lsm6dso_d6d_src_t; 624 625 #define LSM6DSO_STATUS_REG 0x1EU 626 typedef struct 627 { 628 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 629 uint8_t xlda : 1; 630 uint8_t gda : 1; 631 uint8_t tda : 1; 632 uint8_t not_used_01 : 5; 633 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 634 uint8_t not_used_01 : 5; 635 uint8_t tda : 1; 636 uint8_t gda : 1; 637 uint8_t xlda : 1; 638 #endif /* DRV_BYTE_ORDER */ 639 } lsm6dso_status_reg_t; 640 641 #define LSM6DSO_STATUS_SPIAUX 0x1EU 642 typedef struct 643 { 644 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 645 uint8_t xlda : 1; 646 uint8_t gda : 1; 647 uint8_t gyro_settling : 1; 648 uint8_t not_used_01 : 5; 649 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 650 uint8_t not_used_01 : 5; 651 uint8_t gyro_settling : 1; 652 uint8_t gda : 1; 653 uint8_t xlda : 1; 654 #endif /* DRV_BYTE_ORDER */ 655 } lsm6dso_status_spiaux_t; 656 657 #define LSM6DSO_OUT_TEMP_L 0x20U 658 #define LSM6DSO_OUT_TEMP_H 0x21U 659 #define LSM6DSO_OUTX_L_G 0x22U 660 #define LSM6DSO_OUTX_H_G 0x23U 661 #define LSM6DSO_OUTY_L_G 0x24U 662 #define LSM6DSO_OUTY_H_G 0x25U 663 #define LSM6DSO_OUTZ_L_G 0x26U 664 #define LSM6DSO_OUTZ_H_G 0x27U 665 #define LSM6DSO_OUTX_L_A 0x28U 666 #define LSM6DSO_OUTX_H_A 0x29U 667 #define LSM6DSO_OUTY_L_A 0x2AU 668 #define LSM6DSO_OUTY_H_A 0x2BU 669 #define LSM6DSO_OUTZ_L_A 0x2CU 670 #define LSM6DSO_OUTZ_H_A 0x2DU 671 #define LSM6DSO_EMB_FUNC_STATUS_MAINPAGE 0x35U 672 typedef struct 673 { 674 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 675 uint8_t not_used_01 : 3; 676 uint8_t is_step_det : 1; 677 uint8_t is_tilt : 1; 678 uint8_t is_sigmot : 1; 679 uint8_t not_used_02 : 1; 680 uint8_t is_fsm_lc : 1; 681 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 682 uint8_t is_fsm_lc : 1; 683 uint8_t not_used_02 : 1; 684 uint8_t is_sigmot : 1; 685 uint8_t is_tilt : 1; 686 uint8_t is_step_det : 1; 687 uint8_t not_used_01 : 3; 688 #endif /* DRV_BYTE_ORDER */ 689 } lsm6dso_emb_func_status_mainpage_t; 690 691 #define LSM6DSO_FSM_STATUS_A_MAINPAGE 0x36U 692 typedef struct 693 { 694 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 695 uint8_t is_fsm1 : 1; 696 uint8_t is_fsm2 : 1; 697 uint8_t is_fsm3 : 1; 698 uint8_t is_fsm4 : 1; 699 uint8_t is_fsm5 : 1; 700 uint8_t is_fsm6 : 1; 701 uint8_t is_fsm7 : 1; 702 uint8_t is_fsm8 : 1; 703 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 704 uint8_t is_fsm8 : 1; 705 uint8_t is_fsm7 : 1; 706 uint8_t is_fsm6 : 1; 707 uint8_t is_fsm5 : 1; 708 uint8_t is_fsm4 : 1; 709 uint8_t is_fsm3 : 1; 710 uint8_t is_fsm2 : 1; 711 uint8_t is_fsm1 : 1; 712 #endif /* DRV_BYTE_ORDER */ 713 } lsm6dso_fsm_status_a_mainpage_t; 714 715 #define LSM6DSO_FSM_STATUS_B_MAINPAGE 0x37U 716 typedef struct 717 { 718 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 719 uint8_t is_fsm9 : 1; 720 uint8_t is_fsm10 : 1; 721 uint8_t is_fsm11 : 1; 722 uint8_t is_fsm12 : 1; 723 uint8_t is_fsm13 : 1; 724 uint8_t is_fsm14 : 1; 725 uint8_t is_fsm15 : 1; 726 uint8_t is_fsm16 : 1; 727 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 728 uint8_t is_fsm16 : 1; 729 uint8_t is_fsm15 : 1; 730 uint8_t is_fsm14 : 1; 731 uint8_t is_fsm13 : 1; 732 uint8_t is_fsm12 : 1; 733 uint8_t is_fsm11 : 1; 734 uint8_t is_fsm10 : 1; 735 uint8_t is_fsm9 : 1; 736 #endif /* DRV_BYTE_ORDER */ 737 } lsm6dso_fsm_status_b_mainpage_t; 738 739 #define LSM6DSO_STATUS_MASTER_MAINPAGE 0x39U 740 typedef struct 741 { 742 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 743 uint8_t sens_hub_endop : 1; 744 uint8_t not_used_01 : 2; 745 uint8_t slave0_nack : 1; 746 uint8_t slave1_nack : 1; 747 uint8_t slave2_nack : 1; 748 uint8_t slave3_nack : 1; 749 uint8_t wr_once_done : 1; 750 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 751 uint8_t wr_once_done : 1; 752 uint8_t slave3_nack : 1; 753 uint8_t slave2_nack : 1; 754 uint8_t slave1_nack : 1; 755 uint8_t slave0_nack : 1; 756 uint8_t not_used_01 : 2; 757 uint8_t sens_hub_endop : 1; 758 #endif /* DRV_BYTE_ORDER */ 759 } lsm6dso_status_master_mainpage_t; 760 761 #define LSM6DSO_FIFO_STATUS1 0x3AU 762 typedef struct 763 { 764 uint8_t diff_fifo : 8; 765 } lsm6dso_fifo_status1_t; 766 767 #define LSM6DSO_FIFO_STATUS2 0x3B 768 typedef struct 769 { 770 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 771 uint8_t diff_fifo : 2; 772 uint8_t not_used_01 : 1; 773 uint8_t over_run_latched : 1; 774 uint8_t counter_bdr_ia : 1; 775 uint8_t fifo_full_ia : 1; 776 uint8_t fifo_ovr_ia : 1; 777 uint8_t fifo_wtm_ia : 1; 778 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 779 uint8_t fifo_wtm_ia : 1; 780 uint8_t fifo_ovr_ia : 1; 781 uint8_t fifo_full_ia : 1; 782 uint8_t counter_bdr_ia : 1; 783 uint8_t over_run_latched : 1; 784 uint8_t not_used_01 : 1; 785 uint8_t diff_fifo : 2; 786 #endif /* DRV_BYTE_ORDER */ 787 } lsm6dso_fifo_status2_t; 788 789 #define LSM6DSO_TIMESTAMP0 0x40U 790 #define LSM6DSO_TIMESTAMP1 0x41U 791 #define LSM6DSO_TIMESTAMP2 0x42U 792 #define LSM6DSO_TIMESTAMP3 0x43U 793 #define LSM6DSO_TAP_CFG0 0x56U 794 typedef struct 795 { 796 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 797 uint8_t lir : 1; 798 uint8_t tap_z_en : 1; 799 uint8_t tap_y_en : 1; 800 uint8_t tap_x_en : 1; 801 uint8_t slope_fds : 1; 802 uint8_t sleep_status_on_int : 1; 803 uint8_t int_clr_on_read : 1; 804 uint8_t not_used_01 : 1; 805 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 806 uint8_t not_used_01 : 1; 807 uint8_t int_clr_on_read : 1; 808 uint8_t sleep_status_on_int : 1; 809 uint8_t slope_fds : 1; 810 uint8_t tap_x_en : 1; 811 uint8_t tap_y_en : 1; 812 uint8_t tap_z_en : 1; 813 uint8_t lir : 1; 814 #endif /* DRV_BYTE_ORDER */ 815 } lsm6dso_tap_cfg0_t; 816 817 #define LSM6DSO_TAP_CFG1 0x57U 818 typedef struct 819 { 820 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 821 uint8_t tap_ths_x : 5; 822 uint8_t tap_priority : 3; 823 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 824 uint8_t tap_priority : 3; 825 uint8_t tap_ths_x : 5; 826 #endif /* DRV_BYTE_ORDER */ 827 } lsm6dso_tap_cfg1_t; 828 829 #define LSM6DSO_TAP_CFG2 0x58U 830 typedef struct 831 { 832 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 833 uint8_t tap_ths_y : 5; 834 uint8_t inact_en : 2; 835 uint8_t interrupts_enable : 1; 836 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 837 uint8_t interrupts_enable : 1; 838 uint8_t inact_en : 2; 839 uint8_t tap_ths_y : 5; 840 #endif /* DRV_BYTE_ORDER */ 841 } lsm6dso_tap_cfg2_t; 842 843 #define LSM6DSO_TAP_THS_6D 0x59U 844 typedef struct 845 { 846 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 847 uint8_t tap_ths_z : 5; 848 uint8_t sixd_ths : 2; 849 uint8_t d4d_en : 1; 850 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 851 uint8_t d4d_en : 1; 852 uint8_t sixd_ths : 2; 853 uint8_t tap_ths_z : 5; 854 #endif /* DRV_BYTE_ORDER */ 855 } lsm6dso_tap_ths_6d_t; 856 857 #define LSM6DSO_INT_DUR2 0x5AU 858 typedef struct 859 { 860 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 861 uint8_t shock : 2; 862 uint8_t quiet : 2; 863 uint8_t dur : 4; 864 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 865 uint8_t dur : 4; 866 uint8_t quiet : 2; 867 uint8_t shock : 2; 868 #endif /* DRV_BYTE_ORDER */ 869 } lsm6dso_int_dur2_t; 870 871 #define LSM6DSO_WAKE_UP_THS 0x5BU 872 typedef struct 873 { 874 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 875 uint8_t wk_ths : 6; 876 uint8_t usr_off_on_wu : 1; 877 uint8_t single_double_tap : 1; 878 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 879 uint8_t single_double_tap : 1; 880 uint8_t usr_off_on_wu : 1; 881 uint8_t wk_ths : 6; 882 #endif /* DRV_BYTE_ORDER */ 883 } lsm6dso_wake_up_ths_t; 884 885 #define LSM6DSO_WAKE_UP_DUR 0x5CU 886 typedef struct 887 { 888 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 889 uint8_t sleep_dur : 4; 890 uint8_t wake_ths_w : 1; 891 uint8_t wake_dur : 2; 892 uint8_t ff_dur : 1; 893 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 894 uint8_t ff_dur : 1; 895 uint8_t wake_dur : 2; 896 uint8_t wake_ths_w : 1; 897 uint8_t sleep_dur : 4; 898 #endif /* DRV_BYTE_ORDER */ 899 } lsm6dso_wake_up_dur_t; 900 901 #define LSM6DSO_FREE_FALL 0x5DU 902 typedef struct 903 { 904 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 905 uint8_t ff_ths : 3; 906 uint8_t ff_dur : 5; 907 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 908 uint8_t ff_dur : 5; 909 uint8_t ff_ths : 3; 910 #endif /* DRV_BYTE_ORDER */ 911 } lsm6dso_free_fall_t; 912 913 #define LSM6DSO_MD1_CFG 0x5EU 914 typedef struct 915 { 916 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 917 uint8_t int1_shub : 1; 918 uint8_t int1_emb_func : 1; 919 uint8_t int1_6d : 1; 920 uint8_t int1_double_tap : 1; 921 uint8_t int1_ff : 1; 922 uint8_t int1_wu : 1; 923 uint8_t int1_single_tap : 1; 924 uint8_t int1_sleep_change : 1; 925 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 926 uint8_t int1_sleep_change : 1; 927 uint8_t int1_single_tap : 1; 928 uint8_t int1_wu : 1; 929 uint8_t int1_ff : 1; 930 uint8_t int1_double_tap : 1; 931 uint8_t int1_6d : 1; 932 uint8_t int1_emb_func : 1; 933 uint8_t int1_shub : 1; 934 #endif /* DRV_BYTE_ORDER */ 935 } lsm6dso_md1_cfg_t; 936 937 #define LSM6DSO_MD2_CFG 0x5FU 938 typedef struct 939 { 940 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 941 uint8_t int2_timestamp : 1; 942 uint8_t int2_emb_func : 1; 943 uint8_t int2_6d : 1; 944 uint8_t int2_double_tap : 1; 945 uint8_t int2_ff : 1; 946 uint8_t int2_wu : 1; 947 uint8_t int2_single_tap : 1; 948 uint8_t int2_sleep_change : 1; 949 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 950 uint8_t int2_sleep_change : 1; 951 uint8_t int2_single_tap : 1; 952 uint8_t int2_wu : 1; 953 uint8_t int2_ff : 1; 954 uint8_t int2_double_tap : 1; 955 uint8_t int2_6d : 1; 956 uint8_t int2_emb_func : 1; 957 uint8_t int2_timestamp : 1; 958 #endif /* DRV_BYTE_ORDER */ 959 } lsm6dso_md2_cfg_t; 960 961 #define LSM6DSO_I3C_BUS_AVB 0x62U 962 typedef struct 963 { 964 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 965 uint8_t pd_dis_int1 : 1; 966 uint8_t not_used_01 : 2; 967 uint8_t i3c_bus_avb_sel : 2; 968 uint8_t not_used_02 : 3; 969 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 970 uint8_t not_used_02 : 3; 971 uint8_t i3c_bus_avb_sel : 2; 972 uint8_t not_used_01 : 2; 973 uint8_t pd_dis_int1 : 1; 974 #endif /* DRV_BYTE_ORDER */ 975 } lsm6dso_i3c_bus_avb_t; 976 977 #define LSM6DSO_INTERNAL_FREQ_FINE 0x63U 978 typedef struct 979 { 980 uint8_t freq_fine : 8; 981 } lsm6dso_internal_freq_fine_t; 982 983 #define LSM6DSO_INT_OIS 0x6FU 984 typedef struct 985 { 986 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 987 uint8_t st_xl_ois : 2; 988 uint8_t not_used_01 : 3; 989 uint8_t den_lh_ois : 1; 990 uint8_t lvl2_ois : 1; 991 uint8_t int2_drdy_ois : 1; 992 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 993 uint8_t int2_drdy_ois : 1; 994 uint8_t lvl2_ois : 1; 995 uint8_t den_lh_ois : 1; 996 uint8_t not_used_01 : 3; 997 uint8_t st_xl_ois : 2; 998 #endif /* DRV_BYTE_ORDER */ 999 } lsm6dso_int_ois_t; 1000 1001 #define LSM6DSO_CTRL1_OIS 0x70U 1002 typedef struct 1003 { 1004 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1005 uint8_t ois_en_spi2 : 1; 1006 uint8_t fs_g_ois : 3; /* fs_125_ois + fs[1:0]_g_ois */ 1007 uint8_t mode4_en : 1; 1008 uint8_t sim_ois : 1; 1009 uint8_t lvl1_ois : 1; 1010 uint8_t not_used_01 : 1; 1011 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1012 uint8_t not_used_01 : 1; 1013 uint8_t lvl1_ois : 1; 1014 uint8_t sim_ois : 1; 1015 uint8_t mode4_en : 1; 1016 uint8_t fs_g_ois : 3; /* fs_125_ois + fs[1:0]_g_ois */ 1017 uint8_t ois_en_spi2 : 1; 1018 #endif /* DRV_BYTE_ORDER */ 1019 } lsm6dso_ctrl1_ois_t; 1020 1021 #define LSM6DSO_CTRL2_OIS 0x71U 1022 typedef struct 1023 { 1024 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1025 uint8_t hp_en_ois : 1; 1026 uint8_t ftype_ois : 2; 1027 uint8_t not_used_01 : 1; 1028 uint8_t hpm_ois : 2; 1029 uint8_t not_used_02 : 2; 1030 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1031 uint8_t not_used_02 : 2; 1032 uint8_t hpm_ois : 2; 1033 uint8_t not_used_01 : 1; 1034 uint8_t ftype_ois : 2; 1035 uint8_t hp_en_ois : 1; 1036 #endif /* DRV_BYTE_ORDER */ 1037 } lsm6dso_ctrl2_ois_t; 1038 1039 #define LSM6DSO_CTRL3_OIS 0x72U 1040 typedef struct 1041 { 1042 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1043 uint8_t st_ois_clampdis : 1; 1044 uint8_t st_ois : 2; 1045 uint8_t filter_xl_conf_ois : 3; 1046 uint8_t fs_xl_ois : 2; 1047 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1048 uint8_t fs_xl_ois : 2; 1049 uint8_t filter_xl_conf_ois : 3; 1050 uint8_t st_ois : 2; 1051 uint8_t st_ois_clampdis : 1; 1052 #endif /* DRV_BYTE_ORDER */ 1053 } lsm6dso_ctrl3_ois_t; 1054 1055 #define LSM6DSO_X_OFS_USR 0x73U 1056 #define LSM6DSO_Y_OFS_USR 0x74U 1057 #define LSM6DSO_Z_OFS_USR 0x75U 1058 #define LSM6DSO_FIFO_DATA_OUT_TAG 0x78U 1059 typedef struct 1060 { 1061 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1062 uint8_t tag_parity : 1; 1063 uint8_t tag_cnt : 2; 1064 uint8_t tag_sensor : 5; 1065 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1066 uint8_t tag_sensor : 5; 1067 uint8_t tag_cnt : 2; 1068 uint8_t tag_parity : 1; 1069 #endif /* DRV_BYTE_ORDER */ 1070 } lsm6dso_fifo_data_out_tag_t; 1071 1072 #define LSM6DSO_FIFO_DATA_OUT_X_L 0x79U 1073 #define LSM6DSO_FIFO_DATA_OUT_X_H 0x7AU 1074 #define LSM6DSO_FIFO_DATA_OUT_Y_L 0x7BU 1075 #define LSM6DSO_FIFO_DATA_OUT_Y_H 0x7CU 1076 #define LSM6DSO_FIFO_DATA_OUT_Z_L 0x7DU 1077 #define LSM6DSO_FIFO_DATA_OUT_Z_H 0x7EU 1078 #define LSM6DSO_PAGE_SEL 0x02U 1079 typedef struct 1080 { 1081 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1082 uint8_t not_used_01 : 4; 1083 uint8_t page_sel : 4; 1084 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1085 uint8_t page_sel : 4; 1086 uint8_t not_used_01 : 4; 1087 #endif /* DRV_BYTE_ORDER */ 1088 } lsm6dso_page_sel_t; 1089 1090 #define LSM6DSO_EMB_FUNC_EN_A 0x04U 1091 typedef struct 1092 { 1093 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1094 uint8_t not_used_01 : 3; 1095 uint8_t pedo_en : 1; 1096 uint8_t tilt_en : 1; 1097 uint8_t sign_motion_en : 1; 1098 uint8_t not_used_02 : 2; 1099 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1100 uint8_t not_used_02 : 2; 1101 uint8_t sign_motion_en : 1; 1102 uint8_t tilt_en : 1; 1103 uint8_t pedo_en : 1; 1104 uint8_t not_used_01 : 3; 1105 #endif /* DRV_BYTE_ORDER */ 1106 } lsm6dso_emb_func_en_a_t; 1107 1108 #define LSM6DSO_EMB_FUNC_EN_B 0x05U 1109 typedef struct 1110 { 1111 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1112 uint8_t fsm_en : 1; 1113 uint8_t not_used_01 : 2; 1114 uint8_t fifo_compr_en : 1; 1115 uint8_t pedo_adv_en : 1; 1116 uint8_t not_used_02 : 3; 1117 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1118 uint8_t not_used_02 : 3; 1119 uint8_t pedo_adv_en : 1; 1120 uint8_t fifo_compr_en : 1; 1121 uint8_t not_used_01 : 2; 1122 uint8_t fsm_en : 1; 1123 #endif /* DRV_BYTE_ORDER */ 1124 } lsm6dso_emb_func_en_b_t; 1125 1126 #define LSM6DSO_PAGE_ADDRESS 0x08U 1127 typedef struct 1128 { 1129 uint8_t page_addr : 8; 1130 } lsm6dso_page_address_t; 1131 1132 #define LSM6DSO_PAGE_VALUE 0x09U 1133 typedef struct 1134 { 1135 uint8_t page_value : 8; 1136 } lsm6dso_page_value_t; 1137 1138 #define LSM6DSO_EMB_FUNC_INT1 0x0AU 1139 typedef struct 1140 { 1141 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1142 uint8_t not_used_01 : 3; 1143 uint8_t int1_step_detector : 1; 1144 uint8_t int1_tilt : 1; 1145 uint8_t int1_sig_mot : 1; 1146 uint8_t not_used_02 : 1; 1147 uint8_t int1_fsm_lc : 1; 1148 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1149 uint8_t int1_fsm_lc : 1; 1150 uint8_t not_used_02 : 1; 1151 uint8_t int1_sig_mot : 1; 1152 uint8_t int1_tilt : 1; 1153 uint8_t int1_step_detector : 1; 1154 uint8_t not_used_01 : 3; 1155 #endif /* DRV_BYTE_ORDER */ 1156 } lsm6dso_emb_func_int1_t; 1157 1158 #define LSM6DSO_FSM_INT1_A 0x0BU 1159 typedef struct 1160 { 1161 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1162 uint8_t int1_fsm1 : 1; 1163 uint8_t int1_fsm2 : 1; 1164 uint8_t int1_fsm3 : 1; 1165 uint8_t int1_fsm4 : 1; 1166 uint8_t int1_fsm5 : 1; 1167 uint8_t int1_fsm6 : 1; 1168 uint8_t int1_fsm7 : 1; 1169 uint8_t int1_fsm8 : 1; 1170 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1171 uint8_t int1_fsm8 : 1; 1172 uint8_t int1_fsm7 : 1; 1173 uint8_t int1_fsm6 : 1; 1174 uint8_t int1_fsm5 : 1; 1175 uint8_t int1_fsm4 : 1; 1176 uint8_t int1_fsm3 : 1; 1177 uint8_t int1_fsm2 : 1; 1178 uint8_t int1_fsm1 : 1; 1179 #endif /* DRV_BYTE_ORDER */ 1180 } lsm6dso_fsm_int1_a_t; 1181 1182 #define LSM6DSO_FSM_INT1_B 0x0CU 1183 typedef struct 1184 { 1185 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1186 uint8_t int1_fsm9 : 1; 1187 uint8_t int1_fsm10 : 1; 1188 uint8_t int1_fsm11 : 1; 1189 uint8_t int1_fsm12 : 1; 1190 uint8_t int1_fsm13 : 1; 1191 uint8_t int1_fsm14 : 1; 1192 uint8_t int1_fsm15 : 1; 1193 uint8_t int1_fsm16 : 1; 1194 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1195 uint8_t int1_fsm16 : 1; 1196 uint8_t int1_fsm15 : 1; 1197 uint8_t int1_fsm14 : 1; 1198 uint8_t int1_fsm13 : 1; 1199 uint8_t int1_fsm12 : 1; 1200 uint8_t int1_fsm11 : 1; 1201 uint8_t int1_fsm10 : 1; 1202 uint8_t int1_fsm9 : 1; 1203 #endif /* DRV_BYTE_ORDER */ 1204 } lsm6dso_fsm_int1_b_t; 1205 1206 #define LSM6DSO_EMB_FUNC_INT2 0x0EU 1207 typedef struct 1208 { 1209 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1210 uint8_t not_used_01 : 3; 1211 uint8_t int2_step_detector : 1; 1212 uint8_t int2_tilt : 1; 1213 uint8_t int2_sig_mot : 1; 1214 uint8_t not_used_02 : 1; 1215 uint8_t int2_fsm_lc : 1; 1216 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1217 uint8_t int2_fsm_lc : 1; 1218 uint8_t not_used_02 : 1; 1219 uint8_t int2_sig_mot : 1; 1220 uint8_t int2_tilt : 1; 1221 uint8_t int2_step_detector : 1; 1222 uint8_t not_used_01 : 3; 1223 #endif /* DRV_BYTE_ORDER */ 1224 } lsm6dso_emb_func_int2_t; 1225 1226 #define LSM6DSO_FSM_INT2_A 0x0FU 1227 typedef struct 1228 { 1229 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1230 uint8_t int2_fsm1 : 1; 1231 uint8_t int2_fsm2 : 1; 1232 uint8_t int2_fsm3 : 1; 1233 uint8_t int2_fsm4 : 1; 1234 uint8_t int2_fsm5 : 1; 1235 uint8_t int2_fsm6 : 1; 1236 uint8_t int2_fsm7 : 1; 1237 uint8_t int2_fsm8 : 1; 1238 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1239 uint8_t int2_fsm8 : 1; 1240 uint8_t int2_fsm7 : 1; 1241 uint8_t int2_fsm6 : 1; 1242 uint8_t int2_fsm5 : 1; 1243 uint8_t int2_fsm4 : 1; 1244 uint8_t int2_fsm3 : 1; 1245 uint8_t int2_fsm2 : 1; 1246 uint8_t int2_fsm1 : 1; 1247 #endif /* DRV_BYTE_ORDER */ 1248 } lsm6dso_fsm_int2_a_t; 1249 1250 #define LSM6DSO_FSM_INT2_B 0x10U 1251 typedef struct 1252 { 1253 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1254 uint8_t int2_fsm9 : 1; 1255 uint8_t int2_fsm10 : 1; 1256 uint8_t int2_fsm11 : 1; 1257 uint8_t int2_fsm12 : 1; 1258 uint8_t int2_fsm13 : 1; 1259 uint8_t int2_fsm14 : 1; 1260 uint8_t int2_fsm15 : 1; 1261 uint8_t int2_fsm16 : 1; 1262 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1263 uint8_t int2_fsm16 : 1; 1264 uint8_t int2_fsm15 : 1; 1265 uint8_t int2_fsm14 : 1; 1266 uint8_t int2_fsm13 : 1; 1267 uint8_t int2_fsm12 : 1; 1268 uint8_t int2_fsm11 : 1; 1269 uint8_t int2_fsm10 : 1; 1270 uint8_t int2_fsm9 : 1; 1271 #endif /* DRV_BYTE_ORDER */ 1272 } lsm6dso_fsm_int2_b_t; 1273 1274 #define LSM6DSO_EMB_FUNC_STATUS 0x12U 1275 typedef struct 1276 { 1277 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1278 uint8_t not_used_01 : 3; 1279 uint8_t is_step_det : 1; 1280 uint8_t is_tilt : 1; 1281 uint8_t is_sigmot : 1; 1282 uint8_t not_used_02 : 1; 1283 uint8_t is_fsm_lc : 1; 1284 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1285 uint8_t is_fsm_lc : 1; 1286 uint8_t not_used_02 : 1; 1287 uint8_t is_sigmot : 1; 1288 uint8_t is_tilt : 1; 1289 uint8_t is_step_det : 1; 1290 uint8_t not_used_01 : 3; 1291 #endif /* DRV_BYTE_ORDER */ 1292 } lsm6dso_emb_func_status_t; 1293 1294 #define LSM6DSO_FSM_STATUS_A 0x13U 1295 typedef struct 1296 { 1297 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1298 uint8_t is_fsm1 : 1; 1299 uint8_t is_fsm2 : 1; 1300 uint8_t is_fsm3 : 1; 1301 uint8_t is_fsm4 : 1; 1302 uint8_t is_fsm5 : 1; 1303 uint8_t is_fsm6 : 1; 1304 uint8_t is_fsm7 : 1; 1305 uint8_t is_fsm8 : 1; 1306 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1307 uint8_t is_fsm8 : 1; 1308 uint8_t is_fsm7 : 1; 1309 uint8_t is_fsm6 : 1; 1310 uint8_t is_fsm5 : 1; 1311 uint8_t is_fsm4 : 1; 1312 uint8_t is_fsm3 : 1; 1313 uint8_t is_fsm2 : 1; 1314 uint8_t is_fsm1 : 1; 1315 #endif /* DRV_BYTE_ORDER */ 1316 } lsm6dso_fsm_status_a_t; 1317 1318 #define LSM6DSO_FSM_STATUS_B 0x14U 1319 typedef struct 1320 { 1321 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1322 uint8_t is_fsm9 : 1; 1323 uint8_t is_fsm10 : 1; 1324 uint8_t is_fsm11 : 1; 1325 uint8_t is_fsm12 : 1; 1326 uint8_t is_fsm13 : 1; 1327 uint8_t is_fsm14 : 1; 1328 uint8_t is_fsm15 : 1; 1329 uint8_t is_fsm16 : 1; 1330 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1331 uint8_t is_fsm16 : 1; 1332 uint8_t is_fsm15 : 1; 1333 uint8_t is_fsm14 : 1; 1334 uint8_t is_fsm13 : 1; 1335 uint8_t is_fsm12 : 1; 1336 uint8_t is_fsm11 : 1; 1337 uint8_t is_fsm10 : 1; 1338 uint8_t is_fsm9 : 1; 1339 #endif /* DRV_BYTE_ORDER */ 1340 } lsm6dso_fsm_status_b_t; 1341 1342 #define LSM6DSO_PAGE_RW 0x17U 1343 typedef struct 1344 { 1345 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1346 uint8_t not_used_01 : 5; 1347 uint8_t page_rw : 2; /* page_write + page_read */ 1348 uint8_t emb_func_lir : 1; 1349 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1350 uint8_t emb_func_lir : 1; 1351 uint8_t page_rw : 2; /* page_write + page_read */ 1352 uint8_t not_used_01 : 5; 1353 #endif /* DRV_BYTE_ORDER */ 1354 } lsm6dso_page_rw_t; 1355 1356 #define LSM6DSO_EMB_FUNC_FIFO_CFG 0x44U 1357 typedef struct 1358 { 1359 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1360 uint8_t not_used_00 : 6; 1361 uint8_t pedo_fifo_en : 1; 1362 uint8_t not_used_01 : 1; 1363 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1364 uint8_t not_used_01 : 1; 1365 uint8_t pedo_fifo_en : 1; 1366 uint8_t not_used_00 : 6; 1367 #endif /* DRV_BYTE_ORDER */ 1368 } lsm6dso_emb_func_fifo_cfg_t; 1369 1370 #define LSM6DSO_FSM_ENABLE_A 0x46U 1371 typedef struct 1372 { 1373 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1374 uint8_t fsm1_en : 1; 1375 uint8_t fsm2_en : 1; 1376 uint8_t fsm3_en : 1; 1377 uint8_t fsm4_en : 1; 1378 uint8_t fsm5_en : 1; 1379 uint8_t fsm6_en : 1; 1380 uint8_t fsm7_en : 1; 1381 uint8_t fsm8_en : 1; 1382 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1383 uint8_t fsm8_en : 1; 1384 uint8_t fsm7_en : 1; 1385 uint8_t fsm6_en : 1; 1386 uint8_t fsm5_en : 1; 1387 uint8_t fsm4_en : 1; 1388 uint8_t fsm3_en : 1; 1389 uint8_t fsm2_en : 1; 1390 uint8_t fsm1_en : 1; 1391 #endif /* DRV_BYTE_ORDER */ 1392 } lsm6dso_fsm_enable_a_t; 1393 1394 #define LSM6DSO_FSM_ENABLE_B 0x47U 1395 typedef struct 1396 { 1397 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1398 uint8_t fsm9_en : 1; 1399 uint8_t fsm10_en : 1; 1400 uint8_t fsm11_en : 1; 1401 uint8_t fsm12_en : 1; 1402 uint8_t fsm13_en : 1; 1403 uint8_t fsm14_en : 1; 1404 uint8_t fsm15_en : 1; 1405 uint8_t fsm16_en : 1; 1406 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1407 uint8_t fsm16_en : 1; 1408 uint8_t fsm15_en : 1; 1409 uint8_t fsm14_en : 1; 1410 uint8_t fsm13_en : 1; 1411 uint8_t fsm12_en : 1; 1412 uint8_t fsm11_en : 1; 1413 uint8_t fsm10_en : 1; 1414 uint8_t fsm9_en : 1; 1415 #endif /* DRV_BYTE_ORDER */ 1416 } lsm6dso_fsm_enable_b_t; 1417 1418 #define LSM6DSO_FSM_LONG_COUNTER_L 0x48U 1419 #define LSM6DSO_FSM_LONG_COUNTER_H 0x49U 1420 #define LSM6DSO_FSM_LONG_COUNTER_CLEAR 0x4AU 1421 typedef struct 1422 { 1423 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1424 uint8_t fsm_lc_clr : 1425 2; /* fsm_lc_cleared + fsm_lc_clear */ 1426 uint8_t not_used_01 : 6; 1427 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1428 uint8_t not_used_01 : 6; 1429 uint8_t fsm_lc_clr : 1430 2; /* fsm_lc_cleared + fsm_lc_clear */ 1431 #endif /* DRV_BYTE_ORDER */ 1432 } lsm6dso_fsm_long_counter_clear_t; 1433 1434 #define LSM6DSO_FSM_OUTS1 0x4CU 1435 typedef struct 1436 { 1437 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1438 uint8_t n_v : 1; 1439 uint8_t p_v : 1; 1440 uint8_t n_z : 1; 1441 uint8_t p_z : 1; 1442 uint8_t n_y : 1; 1443 uint8_t p_y : 1; 1444 uint8_t n_x : 1; 1445 uint8_t p_x : 1; 1446 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1447 uint8_t p_x : 1; 1448 uint8_t n_x : 1; 1449 uint8_t p_y : 1; 1450 uint8_t n_y : 1; 1451 uint8_t p_z : 1; 1452 uint8_t n_z : 1; 1453 uint8_t p_v : 1; 1454 uint8_t n_v : 1; 1455 #endif /* DRV_BYTE_ORDER */ 1456 } lsm6dso_fsm_outs1_t; 1457 1458 #define LSM6DSO_FSM_OUTS2 0x4DU 1459 typedef struct 1460 { 1461 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1462 uint8_t n_v : 1; 1463 uint8_t p_v : 1; 1464 uint8_t n_z : 1; 1465 uint8_t p_z : 1; 1466 uint8_t n_y : 1; 1467 uint8_t p_y : 1; 1468 uint8_t n_x : 1; 1469 uint8_t p_x : 1; 1470 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1471 uint8_t p_x : 1; 1472 uint8_t n_x : 1; 1473 uint8_t p_y : 1; 1474 uint8_t n_y : 1; 1475 uint8_t p_z : 1; 1476 uint8_t n_z : 1; 1477 uint8_t p_v : 1; 1478 uint8_t n_v : 1; 1479 #endif /* DRV_BYTE_ORDER */ 1480 } lsm6dso_fsm_outs2_t; 1481 1482 #define LSM6DSO_FSM_OUTS3 0x4EU 1483 typedef struct 1484 { 1485 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1486 uint8_t n_v : 1; 1487 uint8_t p_v : 1; 1488 uint8_t n_z : 1; 1489 uint8_t p_z : 1; 1490 uint8_t n_y : 1; 1491 uint8_t p_y : 1; 1492 uint8_t n_x : 1; 1493 uint8_t p_x : 1; 1494 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1495 uint8_t p_x : 1; 1496 uint8_t n_x : 1; 1497 uint8_t p_y : 1; 1498 uint8_t n_y : 1; 1499 uint8_t p_z : 1; 1500 uint8_t n_z : 1; 1501 uint8_t p_v : 1; 1502 uint8_t n_v : 1; 1503 #endif /* DRV_BYTE_ORDER */ 1504 } lsm6dso_fsm_outs3_t; 1505 1506 #define LSM6DSO_FSM_OUTS4 0x4FU 1507 typedef struct 1508 { 1509 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1510 uint8_t n_v : 1; 1511 uint8_t p_v : 1; 1512 uint8_t n_z : 1; 1513 uint8_t p_z : 1; 1514 uint8_t n_y : 1; 1515 uint8_t p_y : 1; 1516 uint8_t n_x : 1; 1517 uint8_t p_x : 1; 1518 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1519 uint8_t p_x : 1; 1520 uint8_t n_x : 1; 1521 uint8_t p_y : 1; 1522 uint8_t n_y : 1; 1523 uint8_t p_z : 1; 1524 uint8_t n_z : 1; 1525 uint8_t p_v : 1; 1526 uint8_t n_v : 1; 1527 #endif /* DRV_BYTE_ORDER */ 1528 } lsm6dso_fsm_outs4_t; 1529 1530 #define LSM6DSO_FSM_OUTS5 0x50U 1531 typedef struct 1532 { 1533 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1534 uint8_t n_v : 1; 1535 uint8_t p_v : 1; 1536 uint8_t n_z : 1; 1537 uint8_t p_z : 1; 1538 uint8_t n_y : 1; 1539 uint8_t p_y : 1; 1540 uint8_t n_x : 1; 1541 uint8_t p_x : 1; 1542 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1543 uint8_t p_x : 1; 1544 uint8_t n_x : 1; 1545 uint8_t p_y : 1; 1546 uint8_t n_y : 1; 1547 uint8_t p_z : 1; 1548 uint8_t n_z : 1; 1549 uint8_t p_v : 1; 1550 uint8_t n_v : 1; 1551 #endif /* DRV_BYTE_ORDER */ 1552 } lsm6dso_fsm_outs5_t; 1553 1554 #define LSM6DSO_FSM_OUTS6 0x51U 1555 typedef struct 1556 { 1557 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1558 uint8_t n_v : 1; 1559 uint8_t p_v : 1; 1560 uint8_t n_z : 1; 1561 uint8_t p_z : 1; 1562 uint8_t n_y : 1; 1563 uint8_t p_y : 1; 1564 uint8_t n_x : 1; 1565 uint8_t p_x : 1; 1566 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1567 uint8_t p_x : 1; 1568 uint8_t n_x : 1; 1569 uint8_t p_y : 1; 1570 uint8_t n_y : 1; 1571 uint8_t p_z : 1; 1572 uint8_t n_z : 1; 1573 uint8_t p_v : 1; 1574 uint8_t n_v : 1; 1575 #endif /* DRV_BYTE_ORDER */ 1576 } lsm6dso_fsm_outs6_t; 1577 1578 #define LSM6DSO_FSM_OUTS7 0x52U 1579 typedef struct 1580 { 1581 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1582 uint8_t n_v : 1; 1583 uint8_t p_v : 1; 1584 uint8_t n_z : 1; 1585 uint8_t p_z : 1; 1586 uint8_t n_y : 1; 1587 uint8_t p_y : 1; 1588 uint8_t n_x : 1; 1589 uint8_t p_x : 1; 1590 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1591 uint8_t p_x : 1; 1592 uint8_t n_x : 1; 1593 uint8_t p_y : 1; 1594 uint8_t n_y : 1; 1595 uint8_t p_z : 1; 1596 uint8_t n_z : 1; 1597 uint8_t p_v : 1; 1598 uint8_t n_v : 1; 1599 #endif /* DRV_BYTE_ORDER */ 1600 } lsm6dso_fsm_outs7_t; 1601 1602 #define LSM6DSO_FSM_OUTS8 0x53U 1603 typedef struct 1604 { 1605 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1606 uint8_t n_v : 1; 1607 uint8_t p_v : 1; 1608 uint8_t n_z : 1; 1609 uint8_t p_z : 1; 1610 uint8_t n_y : 1; 1611 uint8_t p_y : 1; 1612 uint8_t n_x : 1; 1613 uint8_t p_x : 1; 1614 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1615 uint8_t p_x : 1; 1616 uint8_t n_x : 1; 1617 uint8_t p_y : 1; 1618 uint8_t n_y : 1; 1619 uint8_t p_z : 1; 1620 uint8_t n_z : 1; 1621 uint8_t p_v : 1; 1622 uint8_t n_v : 1; 1623 #endif /* DRV_BYTE_ORDER */ 1624 } lsm6dso_fsm_outs8_t; 1625 1626 #define LSM6DSO_FSM_OUTS9 0x54U 1627 typedef struct 1628 { 1629 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1630 uint8_t n_v : 1; 1631 uint8_t p_v : 1; 1632 uint8_t n_z : 1; 1633 uint8_t p_z : 1; 1634 uint8_t n_y : 1; 1635 uint8_t p_y : 1; 1636 uint8_t n_x : 1; 1637 uint8_t p_x : 1; 1638 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1639 uint8_t p_x : 1; 1640 uint8_t n_x : 1; 1641 uint8_t p_y : 1; 1642 uint8_t n_y : 1; 1643 uint8_t p_z : 1; 1644 uint8_t n_z : 1; 1645 uint8_t p_v : 1; 1646 uint8_t n_v : 1; 1647 #endif /* DRV_BYTE_ORDER */ 1648 } lsm6dso_fsm_outs9_t; 1649 1650 #define LSM6DSO_FSM_OUTS10 0x55U 1651 typedef struct 1652 { 1653 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1654 uint8_t n_v : 1; 1655 uint8_t p_v : 1; 1656 uint8_t n_z : 1; 1657 uint8_t p_z : 1; 1658 uint8_t n_y : 1; 1659 uint8_t p_y : 1; 1660 uint8_t n_x : 1; 1661 uint8_t p_x : 1; 1662 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1663 uint8_t p_x : 1; 1664 uint8_t n_x : 1; 1665 uint8_t p_y : 1; 1666 uint8_t n_y : 1; 1667 uint8_t p_z : 1; 1668 uint8_t n_z : 1; 1669 uint8_t p_v : 1; 1670 uint8_t n_v : 1; 1671 #endif /* DRV_BYTE_ORDER */ 1672 } lsm6dso_fsm_outs10_t; 1673 1674 #define LSM6DSO_FSM_OUTS11 0x56U 1675 typedef struct 1676 { 1677 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1678 uint8_t n_v : 1; 1679 uint8_t p_v : 1; 1680 uint8_t n_z : 1; 1681 uint8_t p_z : 1; 1682 uint8_t n_y : 1; 1683 uint8_t p_y : 1; 1684 uint8_t n_x : 1; 1685 uint8_t p_x : 1; 1686 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1687 uint8_t p_x : 1; 1688 uint8_t n_x : 1; 1689 uint8_t p_y : 1; 1690 uint8_t n_y : 1; 1691 uint8_t p_z : 1; 1692 uint8_t n_z : 1; 1693 uint8_t p_v : 1; 1694 uint8_t n_v : 1; 1695 #endif /* DRV_BYTE_ORDER */ 1696 } lsm6dso_fsm_outs11_t; 1697 1698 #define LSM6DSO_FSM_OUTS12 0x57U 1699 typedef struct 1700 { 1701 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1702 uint8_t n_v : 1; 1703 uint8_t p_v : 1; 1704 uint8_t n_z : 1; 1705 uint8_t p_z : 1; 1706 uint8_t n_y : 1; 1707 uint8_t p_y : 1; 1708 uint8_t n_x : 1; 1709 uint8_t p_x : 1; 1710 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1711 uint8_t p_x : 1; 1712 uint8_t n_x : 1; 1713 uint8_t p_y : 1; 1714 uint8_t n_y : 1; 1715 uint8_t p_z : 1; 1716 uint8_t n_z : 1; 1717 uint8_t p_v : 1; 1718 uint8_t n_v : 1; 1719 #endif /* DRV_BYTE_ORDER */ 1720 } lsm6dso_fsm_outs12_t; 1721 1722 #define LSM6DSO_FSM_OUTS13 0x58U 1723 typedef struct 1724 { 1725 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1726 uint8_t n_v : 1; 1727 uint8_t p_v : 1; 1728 uint8_t n_z : 1; 1729 uint8_t p_z : 1; 1730 uint8_t n_y : 1; 1731 uint8_t p_y : 1; 1732 uint8_t n_x : 1; 1733 uint8_t p_x : 1; 1734 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1735 uint8_t p_x : 1; 1736 uint8_t n_x : 1; 1737 uint8_t p_y : 1; 1738 uint8_t n_y : 1; 1739 uint8_t p_z : 1; 1740 uint8_t n_z : 1; 1741 uint8_t p_v : 1; 1742 uint8_t n_v : 1; 1743 #endif /* DRV_BYTE_ORDER */ 1744 } lsm6dso_fsm_outs13_t; 1745 1746 #define LSM6DSO_FSM_OUTS14 0x59U 1747 typedef struct 1748 { 1749 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1750 uint8_t n_v : 1; 1751 uint8_t p_v : 1; 1752 uint8_t n_z : 1; 1753 uint8_t p_z : 1; 1754 uint8_t n_y : 1; 1755 uint8_t p_y : 1; 1756 uint8_t n_x : 1; 1757 uint8_t p_x : 1; 1758 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1759 uint8_t p_x : 1; 1760 uint8_t n_x : 1; 1761 uint8_t p_y : 1; 1762 uint8_t n_y : 1; 1763 uint8_t p_z : 1; 1764 uint8_t n_z : 1; 1765 uint8_t p_v : 1; 1766 uint8_t n_v : 1; 1767 #endif /* DRV_BYTE_ORDER */ 1768 } lsm6dso_fsm_outs14_t; 1769 1770 #define LSM6DSO_FSM_OUTS15 0x5AU 1771 typedef struct 1772 { 1773 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1774 uint8_t n_v : 1; 1775 uint8_t p_v : 1; 1776 uint8_t n_z : 1; 1777 uint8_t p_z : 1; 1778 uint8_t n_y : 1; 1779 uint8_t p_y : 1; 1780 uint8_t n_x : 1; 1781 uint8_t p_x : 1; 1782 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1783 uint8_t p_x : 1; 1784 uint8_t n_x : 1; 1785 uint8_t p_y : 1; 1786 uint8_t n_y : 1; 1787 uint8_t p_z : 1; 1788 uint8_t n_z : 1; 1789 uint8_t p_v : 1; 1790 uint8_t n_v : 1; 1791 #endif /* DRV_BYTE_ORDER */ 1792 } lsm6dso_fsm_outs15_t; 1793 1794 #define LSM6DSO_FSM_OUTS16 0x5BU 1795 typedef struct 1796 { 1797 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1798 uint8_t n_v : 1; 1799 uint8_t p_v : 1; 1800 uint8_t n_z : 1; 1801 uint8_t p_z : 1; 1802 uint8_t n_y : 1; 1803 uint8_t p_y : 1; 1804 uint8_t n_x : 1; 1805 uint8_t p_x : 1; 1806 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1807 uint8_t p_x : 1; 1808 uint8_t n_x : 1; 1809 uint8_t p_y : 1; 1810 uint8_t n_y : 1; 1811 uint8_t p_z : 1; 1812 uint8_t n_z : 1; 1813 uint8_t p_v : 1; 1814 uint8_t n_v : 1; 1815 #endif /* DRV_BYTE_ORDER */ 1816 } lsm6dso_fsm_outs16_t; 1817 1818 #define LSM6DSO_EMB_FUNC_ODR_CFG_B 0x5FU 1819 typedef struct 1820 { 1821 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1822 uint8_t not_used_01 : 3; 1823 uint8_t fsm_odr : 2; 1824 uint8_t not_used_02 : 3; 1825 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1826 uint8_t not_used_02 : 3; 1827 uint8_t fsm_odr : 2; 1828 uint8_t not_used_01 : 3; 1829 #endif /* DRV_BYTE_ORDER */ 1830 } lsm6dso_emb_func_odr_cfg_b_t; 1831 1832 #define LSM6DSO_STEP_COUNTER_L 0x62U 1833 #define LSM6DSO_STEP_COUNTER_H 0x63U 1834 #define LSM6DSO_EMB_FUNC_SRC 0x64U 1835 typedef struct 1836 { 1837 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1838 uint8_t not_used_01 : 2; 1839 uint8_t stepcounter_bit_set : 1; 1840 uint8_t step_overflow : 1; 1841 uint8_t step_count_delta_ia : 1; 1842 uint8_t step_detected : 1; 1843 uint8_t not_used_02 : 1; 1844 uint8_t pedo_rst_step : 1; 1845 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1846 uint8_t pedo_rst_step : 1; 1847 uint8_t not_used_02 : 1; 1848 uint8_t step_detected : 1; 1849 uint8_t step_count_delta_ia : 1; 1850 uint8_t step_overflow : 1; 1851 uint8_t stepcounter_bit_set : 1; 1852 uint8_t not_used_01 : 2; 1853 #endif /* DRV_BYTE_ORDER */ 1854 } lsm6dso_emb_func_src_t; 1855 1856 #define LSM6DSO_EMB_FUNC_INIT_A 0x66U 1857 typedef struct 1858 { 1859 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1860 uint8_t not_used_01 : 3; 1861 uint8_t step_det_init : 1; 1862 uint8_t tilt_init : 1; 1863 uint8_t sig_mot_init : 1; 1864 uint8_t not_used_02 : 2; 1865 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1866 uint8_t not_used_02 : 2; 1867 uint8_t sig_mot_init : 1; 1868 uint8_t tilt_init : 1; 1869 uint8_t step_det_init : 1; 1870 uint8_t not_used_01 : 3; 1871 #endif /* DRV_BYTE_ORDER */ 1872 } lsm6dso_emb_func_init_a_t; 1873 1874 #define LSM6DSO_EMB_FUNC_INIT_B 0x67U 1875 typedef struct 1876 { 1877 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1878 uint8_t fsm_init : 1; 1879 uint8_t not_used_01 : 2; 1880 uint8_t fifo_compr_init : 1; 1881 uint8_t not_used_02 : 4; 1882 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1883 uint8_t not_used_02 : 4; 1884 uint8_t fifo_compr_init : 1; 1885 uint8_t not_used_01 : 2; 1886 uint8_t fsm_init : 1; 1887 #endif /* DRV_BYTE_ORDER */ 1888 } lsm6dso_emb_func_init_b_t; 1889 1890 #define LSM6DSO_MAG_SENSITIVITY_L 0xBAU 1891 #define LSM6DSO_MAG_SENSITIVITY_H 0xBBU 1892 #define LSM6DSO_MAG_OFFX_L 0xC0U 1893 #define LSM6DSO_MAG_OFFX_H 0xC1U 1894 #define LSM6DSO_MAG_OFFY_L 0xC2U 1895 #define LSM6DSO_MAG_OFFY_H 0xC3U 1896 #define LSM6DSO_MAG_OFFZ_L 0xC4U 1897 #define LSM6DSO_MAG_OFFZ_H 0xC5U 1898 #define LSM6DSO_MAG_SI_XX_L 0xC6U 1899 #define LSM6DSO_MAG_SI_XX_H 0xC7U 1900 #define LSM6DSO_MAG_SI_XY_L 0xC8U 1901 #define LSM6DSO_MAG_SI_XY_H 0xC9U 1902 #define LSM6DSO_MAG_SI_XZ_L 0xCAU 1903 #define LSM6DSO_MAG_SI_XZ_H 0xCBU 1904 #define LSM6DSO_MAG_SI_YY_L 0xCCU 1905 #define LSM6DSO_MAG_SI_YY_H 0xCDU 1906 #define LSM6DSO_MAG_SI_YZ_L 0xCEU 1907 #define LSM6DSO_MAG_SI_YZ_H 0xCFU 1908 #define LSM6DSO_MAG_SI_ZZ_L 0xD0U 1909 #define LSM6DSO_MAG_SI_ZZ_H 0xD1U 1910 #define LSM6DSO_MAG_CFG_A 0xD4U 1911 typedef struct 1912 { 1913 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1914 uint8_t mag_z_axis : 3; 1915 uint8_t not_used_01 : 1; 1916 uint8_t mag_y_axis : 3; 1917 uint8_t not_used_02 : 1; 1918 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1919 uint8_t not_used_02 : 1; 1920 uint8_t mag_y_axis : 3; 1921 uint8_t not_used_01 : 1; 1922 uint8_t mag_z_axis : 3; 1923 #endif /* DRV_BYTE_ORDER */ 1924 } lsm6dso_mag_cfg_a_t; 1925 1926 #define LSM6DSO_MAG_CFG_B 0xD5U 1927 typedef struct 1928 { 1929 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1930 uint8_t mag_x_axis : 3; 1931 uint8_t not_used_01 : 5; 1932 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1933 uint8_t not_used_01 : 5; 1934 uint8_t mag_x_axis : 3; 1935 #endif /* DRV_BYTE_ORDER */ 1936 } lsm6dso_mag_cfg_b_t; 1937 1938 #define LSM6DSO_FSM_LC_TIMEOUT_L 0x17AU 1939 #define LSM6DSO_FSM_LC_TIMEOUT_H 0x17BU 1940 #define LSM6DSO_FSM_PROGRAMS 0x17CU 1941 #define LSM6DSO_FSM_START_ADD_L 0x17EU 1942 #define LSM6DSO_FSM_START_ADD_H 0x17FU 1943 #define LSM6DSO_PEDO_CMD_REG 0x183U 1944 typedef struct 1945 { 1946 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1947 uint8_t ad_det_en : 1; 1948 uint8_t not_used_01 : 1; 1949 uint8_t fp_rejection_en : 1; 1950 uint8_t carry_count_en : 1; 1951 uint8_t not_used_02 : 4; 1952 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1953 uint8_t not_used_02 : 4; 1954 uint8_t carry_count_en : 1; 1955 uint8_t fp_rejection_en : 1; 1956 uint8_t not_used_01 : 1; 1957 uint8_t ad_det_en : 1; 1958 #endif /* DRV_BYTE_ORDER */ 1959 } lsm6dso_pedo_cmd_reg_t; 1960 1961 #define LSM6DSO_PEDO_DEB_STEPS_CONF 0x184U 1962 #define LSM6DSO_PEDO_SC_DELTAT_L 0x1D0U 1963 #define LSM6DSO_PEDO_SC_DELTAT_H 0x1D1U 1964 #define LSM6DSO_SENSOR_HUB_1 0x02U 1965 typedef struct 1966 { 1967 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1968 uint8_t bit0 : 1; 1969 uint8_t bit1 : 1; 1970 uint8_t bit2 : 1; 1971 uint8_t bit3 : 1; 1972 uint8_t bit4 : 1; 1973 uint8_t bit5 : 1; 1974 uint8_t bit6 : 1; 1975 uint8_t bit7 : 1; 1976 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1977 uint8_t bit7 : 1; 1978 uint8_t bit6 : 1; 1979 uint8_t bit5 : 1; 1980 uint8_t bit4 : 1; 1981 uint8_t bit3 : 1; 1982 uint8_t bit2 : 1; 1983 uint8_t bit1 : 1; 1984 uint8_t bit0 : 1; 1985 #endif /* DRV_BYTE_ORDER */ 1986 } lsm6dso_sensor_hub_1_t; 1987 1988 #define LSM6DSO_SENSOR_HUB_2 0x03U 1989 typedef struct 1990 { 1991 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1992 uint8_t bit0 : 1; 1993 uint8_t bit1 : 1; 1994 uint8_t bit2 : 1; 1995 uint8_t bit3 : 1; 1996 uint8_t bit4 : 1; 1997 uint8_t bit5 : 1; 1998 uint8_t bit6 : 1; 1999 uint8_t bit7 : 1; 2000 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2001 uint8_t bit7 : 1; 2002 uint8_t bit6 : 1; 2003 uint8_t bit5 : 1; 2004 uint8_t bit4 : 1; 2005 uint8_t bit3 : 1; 2006 uint8_t bit2 : 1; 2007 uint8_t bit1 : 1; 2008 uint8_t bit0 : 1; 2009 #endif /* DRV_BYTE_ORDER */ 2010 } lsm6dso_sensor_hub_2_t; 2011 2012 #define LSM6DSO_SENSOR_HUB_3 0x04U 2013 typedef struct 2014 { 2015 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2016 uint8_t bit0 : 1; 2017 uint8_t bit1 : 1; 2018 uint8_t bit2 : 1; 2019 uint8_t bit3 : 1; 2020 uint8_t bit4 : 1; 2021 uint8_t bit5 : 1; 2022 uint8_t bit6 : 1; 2023 uint8_t bit7 : 1; 2024 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2025 uint8_t bit7 : 1; 2026 uint8_t bit6 : 1; 2027 uint8_t bit5 : 1; 2028 uint8_t bit4 : 1; 2029 uint8_t bit3 : 1; 2030 uint8_t bit2 : 1; 2031 uint8_t bit1 : 1; 2032 uint8_t bit0 : 1; 2033 #endif /* DRV_BYTE_ORDER */ 2034 } lsm6dso_sensor_hub_3_t; 2035 2036 #define LSM6DSO_SENSOR_HUB_4 0x05U 2037 typedef struct 2038 { 2039 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2040 uint8_t bit0 : 1; 2041 uint8_t bit1 : 1; 2042 uint8_t bit2 : 1; 2043 uint8_t bit3 : 1; 2044 uint8_t bit4 : 1; 2045 uint8_t bit5 : 1; 2046 uint8_t bit6 : 1; 2047 uint8_t bit7 : 1; 2048 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2049 uint8_t bit7 : 1; 2050 uint8_t bit6 : 1; 2051 uint8_t bit5 : 1; 2052 uint8_t bit4 : 1; 2053 uint8_t bit3 : 1; 2054 uint8_t bit2 : 1; 2055 uint8_t bit1 : 1; 2056 uint8_t bit0 : 1; 2057 #endif /* DRV_BYTE_ORDER */ 2058 } lsm6dso_sensor_hub_4_t; 2059 2060 #define LSM6DSO_SENSOR_HUB_5 0x06U 2061 typedef struct 2062 { 2063 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2064 uint8_t bit0 : 1; 2065 uint8_t bit1 : 1; 2066 uint8_t bit2 : 1; 2067 uint8_t bit3 : 1; 2068 uint8_t bit4 : 1; 2069 uint8_t bit5 : 1; 2070 uint8_t bit6 : 1; 2071 uint8_t bit7 : 1; 2072 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2073 uint8_t bit7 : 1; 2074 uint8_t bit6 : 1; 2075 uint8_t bit5 : 1; 2076 uint8_t bit4 : 1; 2077 uint8_t bit3 : 1; 2078 uint8_t bit2 : 1; 2079 uint8_t bit1 : 1; 2080 uint8_t bit0 : 1; 2081 #endif /* DRV_BYTE_ORDER */ 2082 } lsm6dso_sensor_hub_5_t; 2083 2084 #define LSM6DSO_SENSOR_HUB_6 0x07U 2085 typedef struct 2086 { 2087 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2088 uint8_t bit0 : 1; 2089 uint8_t bit1 : 1; 2090 uint8_t bit2 : 1; 2091 uint8_t bit3 : 1; 2092 uint8_t bit4 : 1; 2093 uint8_t bit5 : 1; 2094 uint8_t bit6 : 1; 2095 uint8_t bit7 : 1; 2096 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2097 uint8_t bit7 : 1; 2098 uint8_t bit6 : 1; 2099 uint8_t bit5 : 1; 2100 uint8_t bit4 : 1; 2101 uint8_t bit3 : 1; 2102 uint8_t bit2 : 1; 2103 uint8_t bit1 : 1; 2104 uint8_t bit0 : 1; 2105 #endif /* DRV_BYTE_ORDER */ 2106 } lsm6dso_sensor_hub_6_t; 2107 2108 #define LSM6DSO_SENSOR_HUB_7 0x08U 2109 typedef struct 2110 { 2111 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2112 uint8_t bit0 : 1; 2113 uint8_t bit1 : 1; 2114 uint8_t bit2 : 1; 2115 uint8_t bit3 : 1; 2116 uint8_t bit4 : 1; 2117 uint8_t bit5 : 1; 2118 uint8_t bit6 : 1; 2119 uint8_t bit7 : 1; 2120 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2121 uint8_t bit7 : 1; 2122 uint8_t bit6 : 1; 2123 uint8_t bit5 : 1; 2124 uint8_t bit4 : 1; 2125 uint8_t bit3 : 1; 2126 uint8_t bit2 : 1; 2127 uint8_t bit1 : 1; 2128 uint8_t bit0 : 1; 2129 #endif /* DRV_BYTE_ORDER */ 2130 } lsm6dso_sensor_hub_7_t; 2131 2132 #define LSM6DSO_SENSOR_HUB_8 0x09U 2133 typedef struct 2134 { 2135 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2136 uint8_t bit0 : 1; 2137 uint8_t bit1 : 1; 2138 uint8_t bit2 : 1; 2139 uint8_t bit3 : 1; 2140 uint8_t bit4 : 1; 2141 uint8_t bit5 : 1; 2142 uint8_t bit6 : 1; 2143 uint8_t bit7 : 1; 2144 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2145 uint8_t bit7 : 1; 2146 uint8_t bit6 : 1; 2147 uint8_t bit5 : 1; 2148 uint8_t bit4 : 1; 2149 uint8_t bit3 : 1; 2150 uint8_t bit2 : 1; 2151 uint8_t bit1 : 1; 2152 uint8_t bit0 : 1; 2153 #endif /* DRV_BYTE_ORDER */ 2154 } lsm6dso_sensor_hub_8_t; 2155 2156 #define LSM6DSO_SENSOR_HUB_9 0x0AU 2157 typedef struct 2158 { 2159 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2160 uint8_t bit0 : 1; 2161 uint8_t bit1 : 1; 2162 uint8_t bit2 : 1; 2163 uint8_t bit3 : 1; 2164 uint8_t bit4 : 1; 2165 uint8_t bit5 : 1; 2166 uint8_t bit6 : 1; 2167 uint8_t bit7 : 1; 2168 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2169 uint8_t bit7 : 1; 2170 uint8_t bit6 : 1; 2171 uint8_t bit5 : 1; 2172 uint8_t bit4 : 1; 2173 uint8_t bit3 : 1; 2174 uint8_t bit2 : 1; 2175 uint8_t bit1 : 1; 2176 uint8_t bit0 : 1; 2177 #endif /* DRV_BYTE_ORDER */ 2178 } lsm6dso_sensor_hub_9_t; 2179 2180 #define LSM6DSO_SENSOR_HUB_10 0x0BU 2181 typedef struct 2182 { 2183 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2184 uint8_t bit0 : 1; 2185 uint8_t bit1 : 1; 2186 uint8_t bit2 : 1; 2187 uint8_t bit3 : 1; 2188 uint8_t bit4 : 1; 2189 uint8_t bit5 : 1; 2190 uint8_t bit6 : 1; 2191 uint8_t bit7 : 1; 2192 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2193 uint8_t bit7 : 1; 2194 uint8_t bit6 : 1; 2195 uint8_t bit5 : 1; 2196 uint8_t bit4 : 1; 2197 uint8_t bit3 : 1; 2198 uint8_t bit2 : 1; 2199 uint8_t bit1 : 1; 2200 uint8_t bit0 : 1; 2201 #endif /* DRV_BYTE_ORDER */ 2202 } lsm6dso_sensor_hub_10_t; 2203 2204 #define LSM6DSO_SENSOR_HUB_11 0x0CU 2205 typedef struct 2206 { 2207 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2208 uint8_t bit0 : 1; 2209 uint8_t bit1 : 1; 2210 uint8_t bit2 : 1; 2211 uint8_t bit3 : 1; 2212 uint8_t bit4 : 1; 2213 uint8_t bit5 : 1; 2214 uint8_t bit6 : 1; 2215 uint8_t bit7 : 1; 2216 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2217 uint8_t bit7 : 1; 2218 uint8_t bit6 : 1; 2219 uint8_t bit5 : 1; 2220 uint8_t bit4 : 1; 2221 uint8_t bit3 : 1; 2222 uint8_t bit2 : 1; 2223 uint8_t bit1 : 1; 2224 uint8_t bit0 : 1; 2225 #endif /* DRV_BYTE_ORDER */ 2226 } lsm6dso_sensor_hub_11_t; 2227 2228 #define LSM6DSO_SENSOR_HUB_12 0x0DU 2229 typedef struct 2230 { 2231 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2232 uint8_t bit0 : 1; 2233 uint8_t bit1 : 1; 2234 uint8_t bit2 : 1; 2235 uint8_t bit3 : 1; 2236 uint8_t bit4 : 1; 2237 uint8_t bit5 : 1; 2238 uint8_t bit6 : 1; 2239 uint8_t bit7 : 1; 2240 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2241 uint8_t bit7 : 1; 2242 uint8_t bit6 : 1; 2243 uint8_t bit5 : 1; 2244 uint8_t bit4 : 1; 2245 uint8_t bit3 : 1; 2246 uint8_t bit2 : 1; 2247 uint8_t bit1 : 1; 2248 uint8_t bit0 : 1; 2249 #endif /* DRV_BYTE_ORDER */ 2250 } lsm6dso_sensor_hub_12_t; 2251 2252 #define LSM6DSO_SENSOR_HUB_13 0x0EU 2253 typedef struct 2254 { 2255 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2256 uint8_t bit0 : 1; 2257 uint8_t bit1 : 1; 2258 uint8_t bit2 : 1; 2259 uint8_t bit3 : 1; 2260 uint8_t bit4 : 1; 2261 uint8_t bit5 : 1; 2262 uint8_t bit6 : 1; 2263 uint8_t bit7 : 1; 2264 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2265 uint8_t bit7 : 1; 2266 uint8_t bit6 : 1; 2267 uint8_t bit5 : 1; 2268 uint8_t bit4 : 1; 2269 uint8_t bit3 : 1; 2270 uint8_t bit2 : 1; 2271 uint8_t bit1 : 1; 2272 uint8_t bit0 : 1; 2273 #endif /* DRV_BYTE_ORDER */ 2274 } lsm6dso_sensor_hub_13_t; 2275 2276 #define LSM6DSO_SENSOR_HUB_14 0x0FU 2277 typedef struct 2278 { 2279 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2280 uint8_t bit0 : 1; 2281 uint8_t bit1 : 1; 2282 uint8_t bit2 : 1; 2283 uint8_t bit3 : 1; 2284 uint8_t bit4 : 1; 2285 uint8_t bit5 : 1; 2286 uint8_t bit6 : 1; 2287 uint8_t bit7 : 1; 2288 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2289 uint8_t bit7 : 1; 2290 uint8_t bit6 : 1; 2291 uint8_t bit5 : 1; 2292 uint8_t bit4 : 1; 2293 uint8_t bit3 : 1; 2294 uint8_t bit2 : 1; 2295 uint8_t bit1 : 1; 2296 uint8_t bit0 : 1; 2297 #endif /* DRV_BYTE_ORDER */ 2298 } lsm6dso_sensor_hub_14_t; 2299 2300 #define LSM6DSO_SENSOR_HUB_15 0x10U 2301 typedef struct 2302 { 2303 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2304 uint8_t bit0 : 1; 2305 uint8_t bit1 : 1; 2306 uint8_t bit2 : 1; 2307 uint8_t bit3 : 1; 2308 uint8_t bit4 : 1; 2309 uint8_t bit5 : 1; 2310 uint8_t bit6 : 1; 2311 uint8_t bit7 : 1; 2312 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2313 uint8_t bit7 : 1; 2314 uint8_t bit6 : 1; 2315 uint8_t bit5 : 1; 2316 uint8_t bit4 : 1; 2317 uint8_t bit3 : 1; 2318 uint8_t bit2 : 1; 2319 uint8_t bit1 : 1; 2320 uint8_t bit0 : 1; 2321 #endif /* DRV_BYTE_ORDER */ 2322 } lsm6dso_sensor_hub_15_t; 2323 2324 #define LSM6DSO_SENSOR_HUB_16 0x11U 2325 typedef struct 2326 { 2327 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2328 uint8_t bit0 : 1; 2329 uint8_t bit1 : 1; 2330 uint8_t bit2 : 1; 2331 uint8_t bit3 : 1; 2332 uint8_t bit4 : 1; 2333 uint8_t bit5 : 1; 2334 uint8_t bit6 : 1; 2335 uint8_t bit7 : 1; 2336 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2337 uint8_t bit7 : 1; 2338 uint8_t bit6 : 1; 2339 uint8_t bit5 : 1; 2340 uint8_t bit4 : 1; 2341 uint8_t bit3 : 1; 2342 uint8_t bit2 : 1; 2343 uint8_t bit1 : 1; 2344 uint8_t bit0 : 1; 2345 #endif /* DRV_BYTE_ORDER */ 2346 } lsm6dso_sensor_hub_16_t; 2347 2348 #define LSM6DSO_SENSOR_HUB_17 0x12U 2349 typedef struct 2350 { 2351 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2352 uint8_t bit0 : 1; 2353 uint8_t bit1 : 1; 2354 uint8_t bit2 : 1; 2355 uint8_t bit3 : 1; 2356 uint8_t bit4 : 1; 2357 uint8_t bit5 : 1; 2358 uint8_t bit6 : 1; 2359 uint8_t bit7 : 1; 2360 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2361 uint8_t bit7 : 1; 2362 uint8_t bit6 : 1; 2363 uint8_t bit5 : 1; 2364 uint8_t bit4 : 1; 2365 uint8_t bit3 : 1; 2366 uint8_t bit2 : 1; 2367 uint8_t bit1 : 1; 2368 uint8_t bit0 : 1; 2369 #endif /* DRV_BYTE_ORDER */ 2370 } lsm6dso_sensor_hub_17_t; 2371 2372 #define LSM6DSO_SENSOR_HUB_18 0x13U 2373 typedef struct 2374 { 2375 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2376 uint8_t bit0 : 1; 2377 uint8_t bit1 : 1; 2378 uint8_t bit2 : 1; 2379 uint8_t bit3 : 1; 2380 uint8_t bit4 : 1; 2381 uint8_t bit5 : 1; 2382 uint8_t bit6 : 1; 2383 uint8_t bit7 : 1; 2384 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2385 uint8_t bit7 : 1; 2386 uint8_t bit6 : 1; 2387 uint8_t bit5 : 1; 2388 uint8_t bit4 : 1; 2389 uint8_t bit3 : 1; 2390 uint8_t bit2 : 1; 2391 uint8_t bit1 : 1; 2392 uint8_t bit0 : 1; 2393 #endif /* DRV_BYTE_ORDER */ 2394 } lsm6dso_sensor_hub_18_t; 2395 2396 #define LSM6DSO_MASTER_CONFIG 0x14U 2397 typedef struct 2398 { 2399 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2400 uint8_t aux_sens_on : 2; 2401 uint8_t master_on : 1; 2402 uint8_t shub_pu_en : 1; 2403 uint8_t pass_through_mode : 1; 2404 uint8_t start_config : 1; 2405 uint8_t write_once : 1; 2406 uint8_t rst_master_regs : 1; 2407 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2408 uint8_t rst_master_regs : 1; 2409 uint8_t write_once : 1; 2410 uint8_t start_config : 1; 2411 uint8_t pass_through_mode : 1; 2412 uint8_t shub_pu_en : 1; 2413 uint8_t master_on : 1; 2414 uint8_t aux_sens_on : 2; 2415 #endif /* DRV_BYTE_ORDER */ 2416 } lsm6dso_master_config_t; 2417 2418 #define LSM6DSO_SLV0_ADD 0x15U 2419 typedef struct 2420 { 2421 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2422 uint8_t rw_0 : 1; 2423 uint8_t slave0 : 7; 2424 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2425 uint8_t slave0 : 7; 2426 uint8_t rw_0 : 1; 2427 #endif /* DRV_BYTE_ORDER */ 2428 } lsm6dso_slv0_add_t; 2429 2430 #define LSM6DSO_SLV0_SUBADD 0x16U 2431 typedef struct 2432 { 2433 uint8_t slave0_reg : 8; 2434 } lsm6dso_slv0_subadd_t; 2435 2436 #define LSM6DSO_SLV0_CONFIG 0x17U 2437 typedef struct 2438 { 2439 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2440 uint8_t slave0_numop : 3; 2441 uint8_t batch_ext_sens_0_en : 1; 2442 uint8_t not_used_01 : 2; 2443 uint8_t shub_odr : 2; 2444 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2445 uint8_t shub_odr : 2; 2446 uint8_t not_used_01 : 2; 2447 uint8_t batch_ext_sens_0_en : 1; 2448 uint8_t slave0_numop : 3; 2449 #endif /* DRV_BYTE_ORDER */ 2450 } lsm6dso_slv0_config_t; 2451 2452 #define LSM6DSO_SLV1_ADD 0x18U 2453 typedef struct 2454 { 2455 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2456 uint8_t r_1 : 1; 2457 uint8_t slave1_add : 7; 2458 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2459 uint8_t slave1_add : 7; 2460 uint8_t r_1 : 1; 2461 #endif /* DRV_BYTE_ORDER */ 2462 } lsm6dso_slv1_add_t; 2463 2464 #define LSM6DSO_SLV1_SUBADD 0x19U 2465 typedef struct 2466 { 2467 uint8_t slave1_reg : 8; 2468 } lsm6dso_slv1_subadd_t; 2469 2470 #define LSM6DSO_SLV1_CONFIG 0x1AU 2471 typedef struct 2472 { 2473 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2474 uint8_t slave1_numop : 3; 2475 uint8_t batch_ext_sens_1_en : 1; 2476 uint8_t not_used_01 : 4; 2477 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2478 uint8_t not_used_01 : 4; 2479 uint8_t batch_ext_sens_1_en : 1; 2480 uint8_t slave1_numop : 3; 2481 #endif /* DRV_BYTE_ORDER */ 2482 } lsm6dso_slv1_config_t; 2483 2484 #define LSM6DSO_SLV2_ADD 0x1BU 2485 typedef struct 2486 { 2487 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2488 uint8_t r_2 : 1; 2489 uint8_t slave2_add : 7; 2490 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2491 uint8_t slave2_add : 7; 2492 uint8_t r_2 : 1; 2493 #endif /* DRV_BYTE_ORDER */ 2494 } lsm6dso_slv2_add_t; 2495 2496 #define LSM6DSO_SLV2_SUBADD 0x1CU 2497 typedef struct 2498 { 2499 uint8_t slave2_reg : 8; 2500 } lsm6dso_slv2_subadd_t; 2501 2502 #define LSM6DSO_SLV2_CONFIG 0x1DU 2503 typedef struct 2504 { 2505 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2506 uint8_t slave2_numop : 3; 2507 uint8_t batch_ext_sens_2_en : 1; 2508 uint8_t not_used_01 : 4; 2509 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2510 uint8_t not_used_01 : 4; 2511 uint8_t batch_ext_sens_2_en : 1; 2512 uint8_t slave2_numop : 3; 2513 #endif /* DRV_BYTE_ORDER */ 2514 } lsm6dso_slv2_config_t; 2515 2516 #define LSM6DSO_SLV3_ADD 0x1EU 2517 typedef struct 2518 { 2519 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2520 uint8_t r_3 : 1; 2521 uint8_t slave3_add : 7; 2522 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2523 uint8_t slave3_add : 7; 2524 uint8_t r_3 : 1; 2525 #endif /* DRV_BYTE_ORDER */ 2526 } lsm6dso_slv3_add_t; 2527 2528 #define LSM6DSO_SLV3_SUBADD 0x1FU 2529 typedef struct 2530 { 2531 uint8_t slave3_reg : 8; 2532 } lsm6dso_slv3_subadd_t; 2533 2534 #define LSM6DSO_SLV3_CONFIG 0x20U 2535 typedef struct 2536 { 2537 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2538 uint8_t slave3_numop : 3; 2539 uint8_t batch_ext_sens_3_en : 1; 2540 uint8_t not_used_01 : 4; 2541 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2542 uint8_t not_used_01 : 4; 2543 uint8_t batch_ext_sens_3_en : 1; 2544 uint8_t slave3_numop : 3; 2545 #endif /* DRV_BYTE_ORDER */ 2546 } lsm6dso_slv3_config_t; 2547 2548 #define LSM6DSO_DATAWRITE_SLV0 0x21U 2549 typedef struct 2550 { 2551 uint8_t slave0_dataw : 8; 2552 } lsm6dso_datawrite_src_mode_sub_slv0_t; 2553 2554 #define LSM6DSO_STATUS_MASTER 0x22U 2555 typedef struct 2556 { 2557 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2558 uint8_t sens_hub_endop : 1; 2559 uint8_t not_used_01 : 2; 2560 uint8_t slave0_nack : 1; 2561 uint8_t slave1_nack : 1; 2562 uint8_t slave2_nack : 1; 2563 uint8_t slave3_nack : 1; 2564 uint8_t wr_once_done : 1; 2565 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2566 uint8_t wr_once_done : 1; 2567 uint8_t slave3_nack : 1; 2568 uint8_t slave2_nack : 1; 2569 uint8_t slave1_nack : 1; 2570 uint8_t slave0_nack : 1; 2571 uint8_t not_used_01 : 2; 2572 uint8_t sens_hub_endop : 1; 2573 #endif /* DRV_BYTE_ORDER */ 2574 } lsm6dso_status_master_t; 2575 2576 #define LSM6DSO_START_FSM_ADD 0x0400U 2577 2578 /** 2579 * @defgroup LSM6DSO_Register_Union 2580 * @brief This union group all the registers having a bit-field 2581 * description. 2582 * This union is useful but it's not needed by the driver. 2583 * 2584 * REMOVING this union you are compliant with: 2585 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 2586 * 2587 * @{ 2588 * 2589 */ 2590 typedef union 2591 { 2592 lsm6dso_func_cfg_access_t func_cfg_access; 2593 lsm6dso_pin_ctrl_t pin_ctrl; 2594 lsm6dso_fifo_ctrl1_t fifo_ctrl1; 2595 lsm6dso_fifo_ctrl2_t fifo_ctrl2; 2596 lsm6dso_fifo_ctrl3_t fifo_ctrl3; 2597 lsm6dso_fifo_ctrl4_t fifo_ctrl4; 2598 lsm6dso_counter_bdr_reg1_t counter_bdr_reg1; 2599 lsm6dso_counter_bdr_reg2_t counter_bdr_reg2; 2600 lsm6dso_int1_ctrl_t int1_ctrl; 2601 lsm6dso_int2_ctrl_t int2_ctrl; 2602 lsm6dso_ctrl1_xl_t ctrl1_xl; 2603 lsm6dso_ctrl2_g_t ctrl2_g; 2604 lsm6dso_ctrl3_c_t ctrl3_c; 2605 lsm6dso_ctrl4_c_t ctrl4_c; 2606 lsm6dso_ctrl5_c_t ctrl5_c; 2607 lsm6dso_ctrl6_c_t ctrl6_c; 2608 lsm6dso_ctrl7_g_t ctrl7_g; 2609 lsm6dso_ctrl8_xl_t ctrl8_xl; 2610 lsm6dso_ctrl9_xl_t ctrl9_xl; 2611 lsm6dso_ctrl10_c_t ctrl10_c; 2612 lsm6dso_all_int_src_t all_int_src; 2613 lsm6dso_wake_up_src_t wake_up_src; 2614 lsm6dso_tap_src_t tap_src; 2615 lsm6dso_d6d_src_t d6d_src; 2616 lsm6dso_status_reg_t status_reg; 2617 lsm6dso_status_spiaux_t status_spiaux; 2618 lsm6dso_fifo_status1_t fifo_status1; 2619 lsm6dso_fifo_status2_t fifo_status2; 2620 lsm6dso_tap_cfg0_t tap_cfg0; 2621 lsm6dso_tap_cfg1_t tap_cfg1; 2622 lsm6dso_tap_cfg2_t tap_cfg2; 2623 lsm6dso_tap_ths_6d_t tap_ths_6d; 2624 lsm6dso_int_dur2_t int_dur2; 2625 lsm6dso_wake_up_ths_t wake_up_ths; 2626 lsm6dso_wake_up_dur_t wake_up_dur; 2627 lsm6dso_free_fall_t free_fall; 2628 lsm6dso_md1_cfg_t md1_cfg; 2629 lsm6dso_md2_cfg_t md2_cfg; 2630 lsm6dso_i3c_bus_avb_t i3c_bus_avb; 2631 lsm6dso_internal_freq_fine_t internal_freq_fine; 2632 lsm6dso_int_ois_t int_ois; 2633 lsm6dso_ctrl1_ois_t ctrl1_ois; 2634 lsm6dso_ctrl2_ois_t ctrl2_ois; 2635 lsm6dso_ctrl3_ois_t ctrl3_ois; 2636 lsm6dso_fifo_data_out_tag_t fifo_data_out_tag; 2637 lsm6dso_page_sel_t page_sel; 2638 lsm6dso_emb_func_en_a_t emb_func_en_a; 2639 lsm6dso_emb_func_en_b_t emb_func_en_b; 2640 lsm6dso_page_address_t page_address; 2641 lsm6dso_page_value_t page_value; 2642 lsm6dso_emb_func_int1_t emb_func_int1; 2643 lsm6dso_fsm_int1_a_t fsm_int1_a; 2644 lsm6dso_fsm_int1_b_t fsm_int1_b; 2645 lsm6dso_emb_func_int2_t emb_func_int2; 2646 lsm6dso_fsm_int2_a_t fsm_int2_a; 2647 lsm6dso_fsm_int2_b_t fsm_int2_b; 2648 lsm6dso_emb_func_status_t emb_func_status; 2649 lsm6dso_fsm_status_a_t fsm_status_a; 2650 lsm6dso_fsm_status_b_t fsm_status_b; 2651 lsm6dso_page_rw_t page_rw; 2652 lsm6dso_emb_func_fifo_cfg_t emb_func_fifo_cfg; 2653 lsm6dso_fsm_enable_a_t fsm_enable_a; 2654 lsm6dso_fsm_enable_b_t fsm_enable_b; 2655 lsm6dso_fsm_long_counter_clear_t fsm_long_counter_clear; 2656 lsm6dso_fsm_outs1_t fsm_outs1; 2657 lsm6dso_fsm_outs2_t fsm_outs2; 2658 lsm6dso_fsm_outs3_t fsm_outs3; 2659 lsm6dso_fsm_outs4_t fsm_outs4; 2660 lsm6dso_fsm_outs5_t fsm_outs5; 2661 lsm6dso_fsm_outs6_t fsm_outs6; 2662 lsm6dso_fsm_outs7_t fsm_outs7; 2663 lsm6dso_fsm_outs8_t fsm_outs8; 2664 lsm6dso_fsm_outs9_t fsm_outs9; 2665 lsm6dso_fsm_outs10_t fsm_outs10; 2666 lsm6dso_fsm_outs11_t fsm_outs11; 2667 lsm6dso_fsm_outs12_t fsm_outs12; 2668 lsm6dso_fsm_outs13_t fsm_outs13; 2669 lsm6dso_fsm_outs14_t fsm_outs14; 2670 lsm6dso_fsm_outs15_t fsm_outs15; 2671 lsm6dso_fsm_outs16_t fsm_outs16; 2672 lsm6dso_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; 2673 lsm6dso_emb_func_src_t emb_func_src; 2674 lsm6dso_emb_func_init_a_t emb_func_init_a; 2675 lsm6dso_emb_func_init_b_t emb_func_init_b; 2676 lsm6dso_mag_cfg_a_t mag_cfg_a; 2677 lsm6dso_mag_cfg_b_t mag_cfg_b; 2678 lsm6dso_pedo_cmd_reg_t pedo_cmd_reg; 2679 lsm6dso_sensor_hub_1_t sensor_hub_1; 2680 lsm6dso_sensor_hub_2_t sensor_hub_2; 2681 lsm6dso_sensor_hub_3_t sensor_hub_3; 2682 lsm6dso_sensor_hub_4_t sensor_hub_4; 2683 lsm6dso_sensor_hub_5_t sensor_hub_5; 2684 lsm6dso_sensor_hub_6_t sensor_hub_6; 2685 lsm6dso_sensor_hub_7_t sensor_hub_7; 2686 lsm6dso_sensor_hub_8_t sensor_hub_8; 2687 lsm6dso_sensor_hub_9_t sensor_hub_9; 2688 lsm6dso_sensor_hub_10_t sensor_hub_10; 2689 lsm6dso_sensor_hub_11_t sensor_hub_11; 2690 lsm6dso_sensor_hub_12_t sensor_hub_12; 2691 lsm6dso_sensor_hub_13_t sensor_hub_13; 2692 lsm6dso_sensor_hub_14_t sensor_hub_14; 2693 lsm6dso_sensor_hub_15_t sensor_hub_15; 2694 lsm6dso_sensor_hub_16_t sensor_hub_16; 2695 lsm6dso_sensor_hub_17_t sensor_hub_17; 2696 lsm6dso_sensor_hub_18_t sensor_hub_18; 2697 lsm6dso_master_config_t master_config; 2698 lsm6dso_slv0_add_t slv0_add; 2699 lsm6dso_slv0_subadd_t slv0_subadd; 2700 lsm6dso_slv0_config_t slv0_config; 2701 lsm6dso_slv1_add_t slv1_add; 2702 lsm6dso_slv1_subadd_t slv1_subadd; 2703 lsm6dso_slv1_config_t slv1_config; 2704 lsm6dso_slv2_add_t slv2_add; 2705 lsm6dso_slv2_subadd_t slv2_subadd; 2706 lsm6dso_slv2_config_t slv2_config; 2707 lsm6dso_slv3_add_t slv3_add; 2708 lsm6dso_slv3_subadd_t slv3_subadd; 2709 lsm6dso_slv3_config_t slv3_config; 2710 lsm6dso_datawrite_src_mode_sub_slv0_t datawrite_src_mode_sub_slv0; 2711 lsm6dso_status_master_t status_master; 2712 bitwise_t bitwise; 2713 uint8_t byte; 2714 } lsm6dso_reg_t; 2715 2716 /** 2717 * @} 2718 * 2719 */ 2720 2721 int32_t lsm6dso_read_reg(stmdev_ctx_t *ctx, uint8_t reg, 2722 uint8_t *data, 2723 uint16_t len); 2724 int32_t lsm6dso_write_reg(stmdev_ctx_t *ctx, uint8_t reg, 2725 uint8_t *data, 2726 uint16_t len); 2727 2728 float_t lsm6dso_from_fs2_to_mg(int16_t lsb); 2729 float_t lsm6dso_from_fs4_to_mg(int16_t lsb); 2730 float_t lsm6dso_from_fs8_to_mg(int16_t lsb); 2731 float_t lsm6dso_from_fs16_to_mg(int16_t lsb); 2732 2733 float_t lsm6dso_from_fs125_to_mdps(int16_t lsb); 2734 float_t lsm6dso_from_fs500_to_mdps(int16_t lsb); 2735 float_t lsm6dso_from_fs250_to_mdps(int16_t lsb); 2736 float_t lsm6dso_from_fs1000_to_mdps(int16_t lsb); 2737 float_t lsm6dso_from_fs2000_to_mdps(int16_t lsb); 2738 2739 float_t lsm6dso_from_lsb_to_celsius(int16_t lsb); 2740 2741 float_t lsm6dso_from_lsb_to_nsec(int16_t lsb); 2742 2743 typedef enum 2744 { 2745 LSM6DSO_2g = 0, 2746 LSM6DSO_16g = 1, /* if XL_FS_MODE = ‘1’ -> LSM6DSO_2g */ 2747 LSM6DSO_4g = 2, 2748 LSM6DSO_8g = 3, 2749 } lsm6dso_fs_xl_t; 2750 int32_t lsm6dso_xl_full_scale_set(stmdev_ctx_t *ctx, 2751 lsm6dso_fs_xl_t val); 2752 int32_t lsm6dso_xl_full_scale_get(stmdev_ctx_t *ctx, 2753 lsm6dso_fs_xl_t *val); 2754 2755 typedef enum 2756 { 2757 LSM6DSO_XL_ODR_OFF = 0, 2758 LSM6DSO_XL_ODR_12Hz5 = 1, 2759 LSM6DSO_XL_ODR_26Hz = 2, 2760 LSM6DSO_XL_ODR_52Hz = 3, 2761 LSM6DSO_XL_ODR_104Hz = 4, 2762 LSM6DSO_XL_ODR_208Hz = 5, 2763 LSM6DSO_XL_ODR_417Hz = 6, 2764 LSM6DSO_XL_ODR_833Hz = 7, 2765 LSM6DSO_XL_ODR_1667Hz = 8, 2766 LSM6DSO_XL_ODR_3333Hz = 9, 2767 LSM6DSO_XL_ODR_6667Hz = 10, 2768 LSM6DSO_XL_ODR_1Hz6 = 11, /* (low power only) */ 2769 } lsm6dso_odr_xl_t; 2770 int32_t lsm6dso_xl_data_rate_set(stmdev_ctx_t *ctx, 2771 lsm6dso_odr_xl_t val); 2772 int32_t lsm6dso_xl_data_rate_get(stmdev_ctx_t *ctx, 2773 lsm6dso_odr_xl_t *val); 2774 2775 typedef enum 2776 { 2777 LSM6DSO_250dps = 0, 2778 LSM6DSO_125dps = 1, 2779 LSM6DSO_500dps = 2, 2780 LSM6DSO_1000dps = 4, 2781 LSM6DSO_2000dps = 6, 2782 } lsm6dso_fs_g_t; 2783 int32_t lsm6dso_gy_full_scale_set(stmdev_ctx_t *ctx, 2784 lsm6dso_fs_g_t val); 2785 int32_t lsm6dso_gy_full_scale_get(stmdev_ctx_t *ctx, 2786 lsm6dso_fs_g_t *val); 2787 2788 typedef enum 2789 { 2790 LSM6DSO_GY_ODR_OFF = 0, 2791 LSM6DSO_GY_ODR_12Hz5 = 1, 2792 LSM6DSO_GY_ODR_26Hz = 2, 2793 LSM6DSO_GY_ODR_52Hz = 3, 2794 LSM6DSO_GY_ODR_104Hz = 4, 2795 LSM6DSO_GY_ODR_208Hz = 5, 2796 LSM6DSO_GY_ODR_417Hz = 6, 2797 LSM6DSO_GY_ODR_833Hz = 7, 2798 LSM6DSO_GY_ODR_1667Hz = 8, 2799 LSM6DSO_GY_ODR_3333Hz = 9, 2800 LSM6DSO_GY_ODR_6667Hz = 10, 2801 } lsm6dso_odr_g_t; 2802 int32_t lsm6dso_gy_data_rate_set(stmdev_ctx_t *ctx, 2803 lsm6dso_odr_g_t val); 2804 int32_t lsm6dso_gy_data_rate_get(stmdev_ctx_t *ctx, 2805 lsm6dso_odr_g_t *val); 2806 2807 int32_t lsm6dso_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); 2808 int32_t lsm6dso_block_data_update_get(stmdev_ctx_t *ctx, 2809 uint8_t *val); 2810 2811 typedef enum 2812 { 2813 LSM6DSO_LSb_1mg = 0, 2814 LSM6DSO_LSb_16mg = 1, 2815 } lsm6dso_usr_off_w_t; 2816 int32_t lsm6dso_xl_offset_weight_set(stmdev_ctx_t *ctx, 2817 lsm6dso_usr_off_w_t val); 2818 int32_t lsm6dso_xl_offset_weight_get(stmdev_ctx_t *ctx, 2819 lsm6dso_usr_off_w_t *val); 2820 2821 typedef enum 2822 { 2823 LSM6DSO_HIGH_PERFORMANCE_MD = 0, 2824 LSM6DSO_LOW_NORMAL_POWER_MD = 1, 2825 LSM6DSO_ULTRA_LOW_POWER_MD = 2, 2826 } lsm6dso_xl_hm_mode_t; 2827 int32_t lsm6dso_xl_power_mode_set(stmdev_ctx_t *ctx, 2828 lsm6dso_xl_hm_mode_t val); 2829 int32_t lsm6dso_xl_power_mode_get(stmdev_ctx_t *ctx, 2830 lsm6dso_xl_hm_mode_t *val); 2831 2832 typedef enum 2833 { 2834 LSM6DSO_GY_HIGH_PERFORMANCE = 0, 2835 LSM6DSO_GY_NORMAL = 1, 2836 } lsm6dso_g_hm_mode_t; 2837 int32_t lsm6dso_gy_power_mode_set(stmdev_ctx_t *ctx, 2838 lsm6dso_g_hm_mode_t val); 2839 int32_t lsm6dso_gy_power_mode_get(stmdev_ctx_t *ctx, 2840 lsm6dso_g_hm_mode_t *val); 2841 2842 int32_t lsm6dso_status_reg_get(stmdev_ctx_t *ctx, 2843 lsm6dso_status_reg_t *val); 2844 2845 int32_t lsm6dso_xl_flag_data_ready_get(stmdev_ctx_t *ctx, 2846 uint8_t *val); 2847 2848 int32_t lsm6dso_gy_flag_data_ready_get(stmdev_ctx_t *ctx, 2849 uint8_t *val); 2850 2851 int32_t lsm6dso_temp_flag_data_ready_get(stmdev_ctx_t *ctx, 2852 uint8_t *val); 2853 2854 int32_t lsm6dso_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff); 2855 int32_t lsm6dso_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff); 2856 2857 int32_t lsm6dso_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff); 2858 int32_t lsm6dso_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff); 2859 2860 int32_t lsm6dso_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff); 2861 int32_t lsm6dso_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff); 2862 2863 int32_t lsm6dso_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val); 2864 int32_t lsm6dso_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val); 2865 2866 int32_t lsm6dso_timestamp_rst(stmdev_ctx_t *ctx); 2867 2868 int32_t lsm6dso_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); 2869 int32_t lsm6dso_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); 2870 2871 int32_t lsm6dso_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val); 2872 2873 typedef enum 2874 { 2875 LSM6DSO_NO_ROUND = 0, 2876 LSM6DSO_ROUND_XL = 1, 2877 LSM6DSO_ROUND_GY = 2, 2878 LSM6DSO_ROUND_GY_XL = 3, 2879 } lsm6dso_rounding_t; 2880 int32_t lsm6dso_rounding_mode_set(stmdev_ctx_t *ctx, 2881 lsm6dso_rounding_t val); 2882 int32_t lsm6dso_rounding_mode_get(stmdev_ctx_t *ctx, 2883 lsm6dso_rounding_t *val); 2884 2885 int32_t lsm6dso_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); 2886 2887 int32_t lsm6dso_angular_rate_raw_get(stmdev_ctx_t *ctx, 2888 int16_t *val); 2889 2890 int32_t lsm6dso_acceleration_raw_get(stmdev_ctx_t *ctx, 2891 int16_t *val); 2892 2893 int32_t lsm6dso_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff); 2894 2895 int32_t lsm6dso_number_of_steps_get(stmdev_ctx_t *ctx, uint16_t *val); 2896 2897 int32_t lsm6dso_steps_reset(stmdev_ctx_t *ctx); 2898 2899 int32_t lsm6dso_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val); 2900 int32_t lsm6dso_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val); 2901 2902 typedef enum 2903 { 2904 LSM6DSO_USER_BANK = 0, 2905 LSM6DSO_SENSOR_HUB_BANK = 1, 2906 LSM6DSO_EMBEDDED_FUNC_BANK = 2, 2907 } lsm6dso_reg_access_t; 2908 int32_t lsm6dso_mem_bank_set(stmdev_ctx_t *ctx, 2909 lsm6dso_reg_access_t val); 2910 int32_t lsm6dso_mem_bank_get(stmdev_ctx_t *ctx, 2911 lsm6dso_reg_access_t *val); 2912 2913 int32_t lsm6dso_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t address, 2914 uint8_t *val); 2915 int32_t lsm6dso_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t address, 2916 uint8_t *val); 2917 int32_t lsm6dso_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, 2918 uint8_t *buf, uint8_t len); 2919 int32_t lsm6dso_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, 2920 uint8_t *val); 2921 2922 typedef enum 2923 { 2924 LSM6DSO_DRDY_LATCHED = 0, 2925 LSM6DSO_DRDY_PULSED = 1, 2926 } lsm6dso_dataready_pulsed_t; 2927 int32_t lsm6dso_data_ready_mode_set(stmdev_ctx_t *ctx, 2928 lsm6dso_dataready_pulsed_t val); 2929 int32_t lsm6dso_data_ready_mode_get(stmdev_ctx_t *ctx, 2930 lsm6dso_dataready_pulsed_t *val); 2931 2932 int32_t lsm6dso_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); 2933 2934 int32_t lsm6dso_reset_set(stmdev_ctx_t *ctx, uint8_t val); 2935 int32_t lsm6dso_reset_get(stmdev_ctx_t *ctx, uint8_t *val); 2936 2937 int32_t lsm6dso_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); 2938 int32_t lsm6dso_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); 2939 2940 int32_t lsm6dso_boot_set(stmdev_ctx_t *ctx, uint8_t val); 2941 int32_t lsm6dso_boot_get(stmdev_ctx_t *ctx, uint8_t *val); 2942 2943 typedef enum 2944 { 2945 LSM6DSO_XL_ST_DISABLE = 0, 2946 LSM6DSO_XL_ST_POSITIVE = 1, 2947 LSM6DSO_XL_ST_NEGATIVE = 2, 2948 } lsm6dso_st_xl_t; 2949 int32_t lsm6dso_xl_self_test_set(stmdev_ctx_t *ctx, 2950 lsm6dso_st_xl_t val); 2951 int32_t lsm6dso_xl_self_test_get(stmdev_ctx_t *ctx, 2952 lsm6dso_st_xl_t *val); 2953 2954 typedef enum 2955 { 2956 LSM6DSO_GY_ST_DISABLE = 0, 2957 LSM6DSO_GY_ST_POSITIVE = 1, 2958 LSM6DSO_GY_ST_NEGATIVE = 3, 2959 } lsm6dso_st_g_t; 2960 int32_t lsm6dso_gy_self_test_set(stmdev_ctx_t *ctx, 2961 lsm6dso_st_g_t val); 2962 int32_t lsm6dso_gy_self_test_get(stmdev_ctx_t *ctx, 2963 lsm6dso_st_g_t *val); 2964 2965 int32_t lsm6dso_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val); 2966 int32_t lsm6dso_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val); 2967 2968 int32_t lsm6dso_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val); 2969 int32_t lsm6dso_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val); 2970 2971 int32_t lsm6dso_filter_settling_mask_set(stmdev_ctx_t *ctx, 2972 uint8_t val); 2973 int32_t lsm6dso_filter_settling_mask_get(stmdev_ctx_t *ctx, 2974 uint8_t *val); 2975 2976 typedef enum 2977 { 2978 LSM6DSO_ULTRA_LIGHT = 0, 2979 LSM6DSO_VERY_LIGHT = 1, 2980 LSM6DSO_LIGHT = 2, 2981 LSM6DSO_MEDIUM = 3, 2982 LSM6DSO_STRONG = 4, /* not available for data rate > 1k670Hz */ 2983 LSM6DSO_VERY_STRONG = 5, /* not available for data rate > 1k670Hz */ 2984 LSM6DSO_AGGRESSIVE = 6, /* not available for data rate > 1k670Hz */ 2985 LSM6DSO_XTREME = 7, /* not available for data rate > 1k670Hz */ 2986 } lsm6dso_ftype_t; 2987 int32_t lsm6dso_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, 2988 lsm6dso_ftype_t val); 2989 int32_t lsm6dso_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, 2990 lsm6dso_ftype_t *val); 2991 2992 int32_t lsm6dso_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val); 2993 int32_t lsm6dso_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val); 2994 2995 typedef enum 2996 { 2997 LSM6DSO_HP_PATH_DISABLE_ON_OUT = 0x00, 2998 LSM6DSO_SLOPE_ODR_DIV_4 = 0x10, 2999 LSM6DSO_HP_ODR_DIV_10 = 0x11, 3000 LSM6DSO_HP_ODR_DIV_20 = 0x12, 3001 LSM6DSO_HP_ODR_DIV_45 = 0x13, 3002 LSM6DSO_HP_ODR_DIV_100 = 0x14, 3003 LSM6DSO_HP_ODR_DIV_200 = 0x15, 3004 LSM6DSO_HP_ODR_DIV_400 = 0x16, 3005 LSM6DSO_HP_ODR_DIV_800 = 0x17, 3006 LSM6DSO_HP_REF_MD_ODR_DIV_10 = 0x31, 3007 LSM6DSO_HP_REF_MD_ODR_DIV_20 = 0x32, 3008 LSM6DSO_HP_REF_MD_ODR_DIV_45 = 0x33, 3009 LSM6DSO_HP_REF_MD_ODR_DIV_100 = 0x34, 3010 LSM6DSO_HP_REF_MD_ODR_DIV_200 = 0x35, 3011 LSM6DSO_HP_REF_MD_ODR_DIV_400 = 0x36, 3012 LSM6DSO_HP_REF_MD_ODR_DIV_800 = 0x37, 3013 LSM6DSO_LP_ODR_DIV_10 = 0x01, 3014 LSM6DSO_LP_ODR_DIV_20 = 0x02, 3015 LSM6DSO_LP_ODR_DIV_45 = 0x03, 3016 LSM6DSO_LP_ODR_DIV_100 = 0x04, 3017 LSM6DSO_LP_ODR_DIV_200 = 0x05, 3018 LSM6DSO_LP_ODR_DIV_400 = 0x06, 3019 LSM6DSO_LP_ODR_DIV_800 = 0x07, 3020 } lsm6dso_hp_slope_xl_en_t; 3021 int32_t lsm6dso_xl_hp_path_on_out_set(stmdev_ctx_t *ctx, 3022 lsm6dso_hp_slope_xl_en_t val); 3023 int32_t lsm6dso_xl_hp_path_on_out_get(stmdev_ctx_t *ctx, 3024 lsm6dso_hp_slope_xl_en_t *val); 3025 3026 int32_t lsm6dso_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val); 3027 int32_t lsm6dso_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val); 3028 3029 typedef enum 3030 { 3031 LSM6DSO_USE_SLOPE = 0, 3032 LSM6DSO_USE_HPF = 1, 3033 } lsm6dso_slope_fds_t; 3034 int32_t lsm6dso_xl_hp_path_internal_set(stmdev_ctx_t *ctx, 3035 lsm6dso_slope_fds_t val); 3036 int32_t lsm6dso_xl_hp_path_internal_get(stmdev_ctx_t *ctx, 3037 lsm6dso_slope_fds_t *val); 3038 3039 typedef enum 3040 { 3041 LSM6DSO_HP_FILTER_NONE = 0x00, 3042 LSM6DSO_HP_FILTER_16mHz = 0x80, 3043 LSM6DSO_HP_FILTER_65mHz = 0x81, 3044 LSM6DSO_HP_FILTER_260mHz = 0x82, 3045 LSM6DSO_HP_FILTER_1Hz04 = 0x83, 3046 } lsm6dso_hpm_g_t; 3047 int32_t lsm6dso_gy_hp_path_internal_set(stmdev_ctx_t *ctx, 3048 lsm6dso_hpm_g_t val); 3049 int32_t lsm6dso_gy_hp_path_internal_get(stmdev_ctx_t *ctx, 3050 lsm6dso_hpm_g_t *val); 3051 3052 typedef enum 3053 { 3054 LSM6DSO_AUX_PULL_UP_DISC = 0, 3055 LSM6DSO_AUX_PULL_UP_CONNECT = 1, 3056 } lsm6dso_ois_pu_dis_t; 3057 int32_t lsm6dso_aux_sdo_ocs_mode_set(stmdev_ctx_t *ctx, 3058 lsm6dso_ois_pu_dis_t val); 3059 int32_t lsm6dso_aux_sdo_ocs_mode_get(stmdev_ctx_t *ctx, 3060 lsm6dso_ois_pu_dis_t *val); 3061 3062 typedef enum 3063 { 3064 LSM6DSO_AUX_ON = 1, 3065 LSM6DSO_AUX_ON_BY_AUX_INTERFACE = 0, 3066 } lsm6dso_ois_on_t; 3067 int32_t lsm6dso_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx, 3068 lsm6dso_ois_on_t val); 3069 int32_t lsm6dso_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx, 3070 lsm6dso_ois_on_t *val); 3071 3072 typedef enum 3073 { 3074 LSM6DSO_USE_SAME_XL_FS = 0, 3075 LSM6DSO_USE_DIFFERENT_XL_FS = 1, 3076 } lsm6dso_xl_fs_mode_t; 3077 int32_t lsm6dso_aux_xl_fs_mode_set(stmdev_ctx_t *ctx, 3078 lsm6dso_xl_fs_mode_t val); 3079 int32_t lsm6dso_aux_xl_fs_mode_get(stmdev_ctx_t *ctx, 3080 lsm6dso_xl_fs_mode_t *val); 3081 3082 int32_t lsm6dso_aux_status_reg_get(stmdev_ctx_t *ctx, 3083 lsm6dso_status_spiaux_t *val); 3084 3085 int32_t lsm6dso_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx, 3086 uint8_t *val); 3087 3088 int32_t lsm6dso_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx, 3089 uint8_t *val); 3090 3091 int32_t lsm6dso_aux_gy_flag_settling_get(stmdev_ctx_t *ctx, 3092 uint8_t *val); 3093 3094 typedef enum 3095 { 3096 LSM6DSO_AUX_XL_DISABLE = 0, 3097 LSM6DSO_AUX_XL_POS = 1, 3098 LSM6DSO_AUX_XL_NEG = 2, 3099 } lsm6dso_st_xl_ois_t; 3100 int32_t lsm6dso_aux_xl_self_test_set(stmdev_ctx_t *ctx, 3101 lsm6dso_st_xl_ois_t val); 3102 int32_t lsm6dso_aux_xl_self_test_get(stmdev_ctx_t *ctx, 3103 lsm6dso_st_xl_ois_t *val); 3104 3105 typedef enum 3106 { 3107 LSM6DSO_AUX_DEN_ACTIVE_LOW = 0, 3108 LSM6DSO_AUX_DEN_ACTIVE_HIGH = 1, 3109 } lsm6dso_den_lh_ois_t; 3110 int32_t lsm6dso_aux_den_polarity_set(stmdev_ctx_t *ctx, 3111 lsm6dso_den_lh_ois_t val); 3112 int32_t lsm6dso_aux_den_polarity_get(stmdev_ctx_t *ctx, 3113 lsm6dso_den_lh_ois_t *val); 3114 3115 typedef enum 3116 { 3117 LSM6DSO_AUX_DEN_DISABLE = 0, 3118 LSM6DSO_AUX_DEN_LEVEL_LATCH = 3, 3119 LSM6DSO_AUX_DEN_LEVEL_TRIG = 2, 3120 } lsm6dso_lvl2_ois_t; 3121 int32_t lsm6dso_aux_den_mode_set(stmdev_ctx_t *ctx, 3122 lsm6dso_lvl2_ois_t val); 3123 int32_t lsm6dso_aux_den_mode_get(stmdev_ctx_t *ctx, 3124 lsm6dso_lvl2_ois_t *val); 3125 3126 int32_t lsm6dso_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val); 3127 int32_t lsm6dso_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val); 3128 3129 typedef enum 3130 { 3131 LSM6DSO_AUX_DISABLE = 0, 3132 LSM6DSO_MODE_3_GY = 1, 3133 LSM6DSO_MODE_4_GY_XL = 3, 3134 } lsm6dso_ois_en_spi2_t; 3135 int32_t lsm6dso_aux_mode_set(stmdev_ctx_t *ctx, 3136 lsm6dso_ois_en_spi2_t val); 3137 int32_t lsm6dso_aux_mode_get(stmdev_ctx_t *ctx, 3138 lsm6dso_ois_en_spi2_t *val); 3139 3140 typedef enum 3141 { 3142 LSM6DSO_250dps_AUX = 0, 3143 LSM6DSO_125dps_AUX = 1, 3144 LSM6DSO_500dps_AUX = 2, 3145 LSM6DSO_1000dps_AUX = 4, 3146 LSM6DSO_2000dps_AUX = 6, 3147 } lsm6dso_fs_g_ois_t; 3148 int32_t lsm6dso_aux_gy_full_scale_set(stmdev_ctx_t *ctx, 3149 lsm6dso_fs_g_ois_t val); 3150 int32_t lsm6dso_aux_gy_full_scale_get(stmdev_ctx_t *ctx, 3151 lsm6dso_fs_g_ois_t *val); 3152 3153 typedef enum 3154 { 3155 LSM6DSO_AUX_SPI_4_WIRE = 0, 3156 LSM6DSO_AUX_SPI_3_WIRE = 1, 3157 } lsm6dso_sim_ois_t; 3158 int32_t lsm6dso_aux_spi_mode_set(stmdev_ctx_t *ctx, 3159 lsm6dso_sim_ois_t val); 3160 int32_t lsm6dso_aux_spi_mode_get(stmdev_ctx_t *ctx, 3161 lsm6dso_sim_ois_t *val); 3162 3163 typedef enum 3164 { 3165 LSM6DSO_351Hz39 = 0, 3166 LSM6DSO_236Hz63 = 1, 3167 LSM6DSO_172Hz70 = 2, 3168 LSM6DSO_937Hz91 = 3, 3169 } lsm6dso_ftype_ois_t; 3170 int32_t lsm6dso_aux_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, 3171 lsm6dso_ftype_ois_t val); 3172 int32_t lsm6dso_aux_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, 3173 lsm6dso_ftype_ois_t *val); 3174 3175 typedef enum 3176 { 3177 LSM6DSO_AUX_HP_DISABLE = 0x00, 3178 LSM6DSO_AUX_HP_Hz016 = 0x10, 3179 LSM6DSO_AUX_HP_Hz065 = 0x11, 3180 LSM6DSO_AUX_HP_Hz260 = 0x12, 3181 LSM6DSO_AUX_HP_1Hz040 = 0x13, 3182 } lsm6dso_hpm_ois_t; 3183 int32_t lsm6dso_aux_gy_hp_bandwidth_set(stmdev_ctx_t *ctx, 3184 lsm6dso_hpm_ois_t val); 3185 int32_t lsm6dso_aux_gy_hp_bandwidth_get(stmdev_ctx_t *ctx, 3186 lsm6dso_hpm_ois_t *val); 3187 3188 typedef enum 3189 { 3190 LSM6DSO_ENABLE_CLAMP = 0, 3191 LSM6DSO_DISABLE_CLAMP = 1, 3192 } lsm6dso_st_ois_clampdis_t; 3193 int32_t lsm6dso_aux_gy_clamp_set(stmdev_ctx_t *ctx, 3194 lsm6dso_st_ois_clampdis_t val); 3195 int32_t lsm6dso_aux_gy_clamp_get(stmdev_ctx_t *ctx, 3196 lsm6dso_st_ois_clampdis_t *val); 3197 3198 typedef enum 3199 { 3200 LSM6DSO_AUX_GY_DISABLE = 0, 3201 LSM6DSO_AUX_GY_POS = 1, 3202 LSM6DSO_AUX_GY_NEG = 3, 3203 } lsm6dso_st_ois_t; 3204 int32_t lsm6dso_aux_gy_self_test_set(stmdev_ctx_t *ctx, 3205 lsm6dso_st_ois_t val); 3206 int32_t lsm6dso_aux_gy_self_test_get(stmdev_ctx_t *ctx, 3207 lsm6dso_st_ois_t *val); 3208 3209 typedef enum 3210 { 3211 LSM6DSO_289Hz = 0, 3212 LSM6DSO_258Hz = 1, 3213 LSM6DSO_120Hz = 2, 3214 LSM6DSO_65Hz2 = 3, 3215 LSM6DSO_33Hz2 = 4, 3216 LSM6DSO_16Hz6 = 5, 3217 LSM6DSO_8Hz30 = 6, 3218 LSM6DSO_4Hz15 = 7, 3219 } lsm6dso_filter_xl_conf_ois_t; 3220 int32_t lsm6dso_aux_xl_bandwidth_set(stmdev_ctx_t *ctx, 3221 lsm6dso_filter_xl_conf_ois_t val); 3222 int32_t lsm6dso_aux_xl_bandwidth_get(stmdev_ctx_t *ctx, 3223 lsm6dso_filter_xl_conf_ois_t *val); 3224 3225 typedef enum 3226 { 3227 LSM6DSO_AUX_2g = 0, 3228 LSM6DSO_AUX_16g = 1, 3229 LSM6DSO_AUX_4g = 2, 3230 LSM6DSO_AUX_8g = 3, 3231 } lsm6dso_fs_xl_ois_t; 3232 int32_t lsm6dso_aux_xl_full_scale_set(stmdev_ctx_t *ctx, 3233 lsm6dso_fs_xl_ois_t val); 3234 int32_t lsm6dso_aux_xl_full_scale_get(stmdev_ctx_t *ctx, 3235 lsm6dso_fs_xl_ois_t *val); 3236 3237 typedef enum 3238 { 3239 LSM6DSO_PULL_UP_DISC = 0, 3240 LSM6DSO_PULL_UP_CONNECT = 1, 3241 } lsm6dso_sdo_pu_en_t; 3242 int32_t lsm6dso_sdo_sa0_mode_set(stmdev_ctx_t *ctx, 3243 lsm6dso_sdo_pu_en_t val); 3244 int32_t lsm6dso_sdo_sa0_mode_get(stmdev_ctx_t *ctx, 3245 lsm6dso_sdo_pu_en_t *val); 3246 3247 typedef enum 3248 { 3249 LSM6DSO_SPI_4_WIRE = 0, 3250 LSM6DSO_SPI_3_WIRE = 1, 3251 } lsm6dso_sim_t; 3252 int32_t lsm6dso_spi_mode_set(stmdev_ctx_t *ctx, lsm6dso_sim_t val); 3253 int32_t lsm6dso_spi_mode_get(stmdev_ctx_t *ctx, lsm6dso_sim_t *val); 3254 3255 typedef enum 3256 { 3257 LSM6DSO_I2C_ENABLE = 0, 3258 LSM6DSO_I2C_DISABLE = 1, 3259 } lsm6dso_i2c_disable_t; 3260 int32_t lsm6dso_i2c_interface_set(stmdev_ctx_t *ctx, 3261 lsm6dso_i2c_disable_t val); 3262 int32_t lsm6dso_i2c_interface_get(stmdev_ctx_t *ctx, 3263 lsm6dso_i2c_disable_t *val); 3264 3265 typedef enum 3266 { 3267 LSM6DSO_I3C_DISABLE = 0x80, 3268 LSM6DSO_I3C_ENABLE_T_50us = 0x00, 3269 LSM6DSO_I3C_ENABLE_T_2us = 0x01, 3270 LSM6DSO_I3C_ENABLE_T_1ms = 0x02, 3271 LSM6DSO_I3C_ENABLE_T_25ms = 0x03, 3272 } lsm6dso_i3c_disable_t; 3273 int32_t lsm6dso_i3c_disable_set(stmdev_ctx_t *ctx, 3274 lsm6dso_i3c_disable_t val); 3275 int32_t lsm6dso_i3c_disable_get(stmdev_ctx_t *ctx, 3276 lsm6dso_i3c_disable_t *val); 3277 3278 typedef enum 3279 { 3280 LSM6DSO_PULL_DOWN_DISC = 0, 3281 LSM6DSO_PULL_DOWN_CONNECT = 1, 3282 } lsm6dso_int1_pd_en_t; 3283 int32_t lsm6dso_int1_mode_set(stmdev_ctx_t *ctx, 3284 lsm6dso_int1_pd_en_t val); 3285 int32_t lsm6dso_int1_mode_get(stmdev_ctx_t *ctx, 3286 lsm6dso_int1_pd_en_t *val); 3287 3288 typedef enum 3289 { 3290 LSM6DSO_PUSH_PULL = 0, 3291 LSM6DSO_OPEN_DRAIN = 1, 3292 } lsm6dso_pp_od_t; 3293 int32_t lsm6dso_pin_mode_set(stmdev_ctx_t *ctx, lsm6dso_pp_od_t val); 3294 int32_t lsm6dso_pin_mode_get(stmdev_ctx_t *ctx, lsm6dso_pp_od_t *val); 3295 3296 typedef enum 3297 { 3298 LSM6DSO_ACTIVE_HIGH = 0, 3299 LSM6DSO_ACTIVE_LOW = 1, 3300 } lsm6dso_h_lactive_t; 3301 int32_t lsm6dso_pin_polarity_set(stmdev_ctx_t *ctx, 3302 lsm6dso_h_lactive_t val); 3303 int32_t lsm6dso_pin_polarity_get(stmdev_ctx_t *ctx, 3304 lsm6dso_h_lactive_t *val); 3305 3306 int32_t lsm6dso_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); 3307 int32_t lsm6dso_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); 3308 3309 typedef enum 3310 { 3311 LSM6DSO_ALL_INT_PULSED = 0, 3312 LSM6DSO_BASE_LATCHED_EMB_PULSED = 1, 3313 LSM6DSO_BASE_PULSED_EMB_LATCHED = 2, 3314 LSM6DSO_ALL_INT_LATCHED = 3, 3315 } lsm6dso_lir_t; 3316 int32_t lsm6dso_int_notification_set(stmdev_ctx_t *ctx, 3317 lsm6dso_lir_t val); 3318 int32_t lsm6dso_int_notification_get(stmdev_ctx_t *ctx, 3319 lsm6dso_lir_t *val); 3320 3321 typedef enum 3322 { 3323 LSM6DSO_LSb_FS_DIV_64 = 0, 3324 LSM6DSO_LSb_FS_DIV_256 = 1, 3325 } lsm6dso_wake_ths_w_t; 3326 int32_t lsm6dso_wkup_ths_weight_set(stmdev_ctx_t *ctx, 3327 lsm6dso_wake_ths_w_t val); 3328 int32_t lsm6dso_wkup_ths_weight_get(stmdev_ctx_t *ctx, 3329 lsm6dso_wake_ths_w_t *val); 3330 3331 int32_t lsm6dso_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val); 3332 int32_t lsm6dso_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); 3333 3334 int32_t lsm6dso_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, 3335 uint8_t val); 3336 int32_t lsm6dso_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, 3337 uint8_t *val); 3338 3339 int32_t lsm6dso_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val); 3340 int32_t lsm6dso_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 3341 3342 int32_t lsm6dso_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val); 3343 int32_t lsm6dso_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val); 3344 3345 typedef enum 3346 { 3347 LSM6DSO_DRIVE_SLEEP_CHG_EVENT = 0, 3348 LSM6DSO_DRIVE_SLEEP_STATUS = 1, 3349 } lsm6dso_sleep_status_on_int_t; 3350 int32_t lsm6dso_act_pin_notification_set(stmdev_ctx_t *ctx, 3351 lsm6dso_sleep_status_on_int_t val); 3352 int32_t lsm6dso_act_pin_notification_get(stmdev_ctx_t *ctx, 3353 lsm6dso_sleep_status_on_int_t *val); 3354 3355 typedef enum 3356 { 3357 LSM6DSO_XL_AND_GY_NOT_AFFECTED = 0, 3358 LSM6DSO_XL_12Hz5_GY_NOT_AFFECTED = 1, 3359 LSM6DSO_XL_12Hz5_GY_SLEEP = 2, 3360 LSM6DSO_XL_12Hz5_GY_PD = 3, 3361 } lsm6dso_inact_en_t; 3362 int32_t lsm6dso_act_mode_set(stmdev_ctx_t *ctx, 3363 lsm6dso_inact_en_t val); 3364 int32_t lsm6dso_act_mode_get(stmdev_ctx_t *ctx, 3365 lsm6dso_inact_en_t *val); 3366 3367 int32_t lsm6dso_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val); 3368 int32_t lsm6dso_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 3369 3370 int32_t lsm6dso_tap_detection_on_z_set(stmdev_ctx_t *ctx, 3371 uint8_t val); 3372 int32_t lsm6dso_tap_detection_on_z_get(stmdev_ctx_t *ctx, 3373 uint8_t *val); 3374 3375 int32_t lsm6dso_tap_detection_on_y_set(stmdev_ctx_t *ctx, 3376 uint8_t val); 3377 int32_t lsm6dso_tap_detection_on_y_get(stmdev_ctx_t *ctx, 3378 uint8_t *val); 3379 3380 int32_t lsm6dso_tap_detection_on_x_set(stmdev_ctx_t *ctx, 3381 uint8_t val); 3382 int32_t lsm6dso_tap_detection_on_x_get(stmdev_ctx_t *ctx, 3383 uint8_t *val); 3384 3385 int32_t lsm6dso_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val); 3386 int32_t lsm6dso_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val); 3387 3388 typedef enum 3389 { 3390 LSM6DSO_XYZ = 0, 3391 LSM6DSO_YXZ = 1, 3392 LSM6DSO_XZY = 2, 3393 LSM6DSO_ZYX = 3, 3394 LSM6DSO_YZX = 5, 3395 LSM6DSO_ZXY = 6, 3396 } lsm6dso_tap_priority_t; 3397 int32_t lsm6dso_tap_axis_priority_set(stmdev_ctx_t *ctx, 3398 lsm6dso_tap_priority_t val); 3399 int32_t lsm6dso_tap_axis_priority_get(stmdev_ctx_t *ctx, 3400 lsm6dso_tap_priority_t *val); 3401 3402 int32_t lsm6dso_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val); 3403 int32_t lsm6dso_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val); 3404 3405 int32_t lsm6dso_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val); 3406 int32_t lsm6dso_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val); 3407 3408 int32_t lsm6dso_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val); 3409 int32_t lsm6dso_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val); 3410 3411 int32_t lsm6dso_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val); 3412 int32_t lsm6dso_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val); 3413 3414 int32_t lsm6dso_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val); 3415 int32_t lsm6dso_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 3416 3417 typedef enum 3418 { 3419 LSM6DSO_ONLY_SINGLE = 0, 3420 LSM6DSO_BOTH_SINGLE_DOUBLE = 1, 3421 } lsm6dso_single_double_tap_t; 3422 int32_t lsm6dso_tap_mode_set(stmdev_ctx_t *ctx, 3423 lsm6dso_single_double_tap_t val); 3424 int32_t lsm6dso_tap_mode_get(stmdev_ctx_t *ctx, 3425 lsm6dso_single_double_tap_t *val); 3426 3427 typedef enum 3428 { 3429 LSM6DSO_DEG_80 = 0, 3430 LSM6DSO_DEG_70 = 1, 3431 LSM6DSO_DEG_60 = 2, 3432 LSM6DSO_DEG_50 = 3, 3433 } lsm6dso_sixd_ths_t; 3434 int32_t lsm6dso_6d_threshold_set(stmdev_ctx_t *ctx, 3435 lsm6dso_sixd_ths_t val); 3436 int32_t lsm6dso_6d_threshold_get(stmdev_ctx_t *ctx, 3437 lsm6dso_sixd_ths_t *val); 3438 3439 int32_t lsm6dso_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val); 3440 int32_t lsm6dso_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val); 3441 3442 typedef enum 3443 { 3444 LSM6DSO_FF_TSH_156mg = 0, 3445 LSM6DSO_FF_TSH_219mg = 1, 3446 LSM6DSO_FF_TSH_250mg = 2, 3447 LSM6DSO_FF_TSH_312mg = 3, 3448 LSM6DSO_FF_TSH_344mg = 4, 3449 LSM6DSO_FF_TSH_406mg = 5, 3450 LSM6DSO_FF_TSH_469mg = 6, 3451 LSM6DSO_FF_TSH_500mg = 7, 3452 } lsm6dso_ff_ths_t; 3453 int32_t lsm6dso_ff_threshold_set(stmdev_ctx_t *ctx, 3454 lsm6dso_ff_ths_t val); 3455 int32_t lsm6dso_ff_threshold_get(stmdev_ctx_t *ctx, 3456 lsm6dso_ff_ths_t *val); 3457 3458 int32_t lsm6dso_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val); 3459 int32_t lsm6dso_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 3460 3461 int32_t lsm6dso_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val); 3462 int32_t lsm6dso_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val); 3463 3464 int32_t lsm6dso_compression_algo_init_set(stmdev_ctx_t *ctx, 3465 uint8_t val); 3466 int32_t lsm6dso_compression_algo_init_get(stmdev_ctx_t *ctx, 3467 uint8_t *val); 3468 3469 typedef enum 3470 { 3471 LSM6DSO_CMP_DISABLE = 0x00, 3472 LSM6DSO_CMP_ALWAYS = 0x04, 3473 LSM6DSO_CMP_8_TO_1 = 0x05, 3474 LSM6DSO_CMP_16_TO_1 = 0x06, 3475 LSM6DSO_CMP_32_TO_1 = 0x07, 3476 } lsm6dso_uncoptr_rate_t; 3477 int32_t lsm6dso_compression_algo_set(stmdev_ctx_t *ctx, 3478 lsm6dso_uncoptr_rate_t val); 3479 int32_t lsm6dso_compression_algo_get(stmdev_ctx_t *ctx, 3480 lsm6dso_uncoptr_rate_t *val); 3481 3482 int32_t lsm6dso_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, 3483 uint8_t val); 3484 int32_t lsm6dso_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, 3485 uint8_t *val); 3486 3487 int32_t lsm6dso_compression_algo_real_time_set(stmdev_ctx_t *ctx, 3488 uint8_t val); 3489 int32_t lsm6dso_compression_algo_real_time_get(stmdev_ctx_t *ctx, 3490 uint8_t *val); 3491 3492 int32_t lsm6dso_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val); 3493 int32_t lsm6dso_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val); 3494 3495 typedef enum 3496 { 3497 LSM6DSO_XL_NOT_BATCHED = 0, 3498 LSM6DSO_XL_BATCHED_AT_12Hz5 = 1, 3499 LSM6DSO_XL_BATCHED_AT_26Hz = 2, 3500 LSM6DSO_XL_BATCHED_AT_52Hz = 3, 3501 LSM6DSO_XL_BATCHED_AT_104Hz = 4, 3502 LSM6DSO_XL_BATCHED_AT_208Hz = 5, 3503 LSM6DSO_XL_BATCHED_AT_417Hz = 6, 3504 LSM6DSO_XL_BATCHED_AT_833Hz = 7, 3505 LSM6DSO_XL_BATCHED_AT_1667Hz = 8, 3506 LSM6DSO_XL_BATCHED_AT_3333Hz = 9, 3507 LSM6DSO_XL_BATCHED_AT_6667Hz = 10, 3508 LSM6DSO_XL_BATCHED_AT_6Hz5 = 11, 3509 } lsm6dso_bdr_xl_t; 3510 int32_t lsm6dso_fifo_xl_batch_set(stmdev_ctx_t *ctx, 3511 lsm6dso_bdr_xl_t val); 3512 int32_t lsm6dso_fifo_xl_batch_get(stmdev_ctx_t *ctx, 3513 lsm6dso_bdr_xl_t *val); 3514 3515 typedef enum 3516 { 3517 LSM6DSO_GY_NOT_BATCHED = 0, 3518 LSM6DSO_GY_BATCHED_AT_12Hz5 = 1, 3519 LSM6DSO_GY_BATCHED_AT_26Hz = 2, 3520 LSM6DSO_GY_BATCHED_AT_52Hz = 3, 3521 LSM6DSO_GY_BATCHED_AT_104Hz = 4, 3522 LSM6DSO_GY_BATCHED_AT_208Hz = 5, 3523 LSM6DSO_GY_BATCHED_AT_417Hz = 6, 3524 LSM6DSO_GY_BATCHED_AT_833Hz = 7, 3525 LSM6DSO_GY_BATCHED_AT_1667Hz = 8, 3526 LSM6DSO_GY_BATCHED_AT_3333Hz = 9, 3527 LSM6DSO_GY_BATCHED_AT_6667Hz = 10, 3528 LSM6DSO_GY_BATCHED_AT_6Hz5 = 11, 3529 } lsm6dso_bdr_gy_t; 3530 int32_t lsm6dso_fifo_gy_batch_set(stmdev_ctx_t *ctx, 3531 lsm6dso_bdr_gy_t val); 3532 int32_t lsm6dso_fifo_gy_batch_get(stmdev_ctx_t *ctx, 3533 lsm6dso_bdr_gy_t *val); 3534 3535 typedef enum 3536 { 3537 LSM6DSO_BYPASS_MODE = 0, 3538 LSM6DSO_FIFO_MODE = 1, 3539 LSM6DSO_STREAM_TO_FIFO_MODE = 3, 3540 LSM6DSO_BYPASS_TO_STREAM_MODE = 4, 3541 LSM6DSO_STREAM_MODE = 6, 3542 LSM6DSO_BYPASS_TO_FIFO_MODE = 7, 3543 } lsm6dso_fifo_mode_t; 3544 int32_t lsm6dso_fifo_mode_set(stmdev_ctx_t *ctx, 3545 lsm6dso_fifo_mode_t val); 3546 int32_t lsm6dso_fifo_mode_get(stmdev_ctx_t *ctx, 3547 lsm6dso_fifo_mode_t *val); 3548 3549 typedef enum 3550 { 3551 LSM6DSO_TEMP_NOT_BATCHED = 0, 3552 LSM6DSO_TEMP_BATCHED_AT_1Hz6 = 1, 3553 LSM6DSO_TEMP_BATCHED_AT_12Hz5 = 2, 3554 LSM6DSO_TEMP_BATCHED_AT_52Hz = 3, 3555 } lsm6dso_odr_t_batch_t; 3556 int32_t lsm6dso_fifo_temp_batch_set(stmdev_ctx_t *ctx, 3557 lsm6dso_odr_t_batch_t val); 3558 int32_t lsm6dso_fifo_temp_batch_get(stmdev_ctx_t *ctx, 3559 lsm6dso_odr_t_batch_t *val); 3560 3561 typedef enum 3562 { 3563 LSM6DSO_NO_DECIMATION = 0, 3564 LSM6DSO_DEC_1 = 1, 3565 LSM6DSO_DEC_8 = 2, 3566 LSM6DSO_DEC_32 = 3, 3567 } lsm6dso_odr_ts_batch_t; 3568 int32_t lsm6dso_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, 3569 lsm6dso_odr_ts_batch_t val); 3570 int32_t lsm6dso_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, 3571 lsm6dso_odr_ts_batch_t *val); 3572 3573 typedef enum 3574 { 3575 LSM6DSO_XL_BATCH_EVENT = 0, 3576 LSM6DSO_GYRO_BATCH_EVENT = 1, 3577 } lsm6dso_trig_counter_bdr_t; 3578 3579 typedef enum 3580 { 3581 LSM6DSO_GYRO_NC_TAG = 1, 3582 LSM6DSO_XL_NC_TAG, 3583 LSM6DSO_TEMPERATURE_TAG, 3584 LSM6DSO_TIMESTAMP_TAG, 3585 LSM6DSO_CFG_CHANGE_TAG, 3586 LSM6DSO_XL_NC_T_2_TAG, 3587 LSM6DSO_XL_NC_T_1_TAG, 3588 LSM6DSO_XL_2XC_TAG, 3589 LSM6DSO_XL_3XC_TAG, 3590 LSM6DSO_GYRO_NC_T_2_TAG, 3591 LSM6DSO_GYRO_NC_T_1_TAG, 3592 LSM6DSO_GYRO_2XC_TAG, 3593 LSM6DSO_GYRO_3XC_TAG, 3594 LSM6DSO_SENSORHUB_SLAVE0_TAG, 3595 LSM6DSO_SENSORHUB_SLAVE1_TAG, 3596 LSM6DSO_SENSORHUB_SLAVE2_TAG, 3597 LSM6DSO_SENSORHUB_SLAVE3_TAG, 3598 LSM6DSO_STEP_CPUNTER_TAG, 3599 LSM6DSO_GAME_ROTATION_TAG, 3600 LSM6DSO_GEOMAG_ROTATION_TAG, 3601 LSM6DSO_ROTATION_TAG, 3602 LSM6DSO_SENSORHUB_NACK_TAG = 0x19, 3603 } lsm6dso_fifo_tag_t; 3604 int32_t lsm6dso_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx, 3605 lsm6dso_trig_counter_bdr_t val); 3606 int32_t lsm6dso_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx, 3607 lsm6dso_trig_counter_bdr_t *val); 3608 3609 int32_t lsm6dso_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val); 3610 int32_t lsm6dso_rst_batch_counter_get(stmdev_ctx_t *ctx, 3611 uint8_t *val); 3612 3613 int32_t lsm6dso_batch_counter_threshold_set(stmdev_ctx_t *ctx, 3614 uint16_t val); 3615 int32_t lsm6dso_batch_counter_threshold_get(stmdev_ctx_t *ctx, 3616 uint16_t *val); 3617 3618 int32_t lsm6dso_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val); 3619 3620 int32_t lsm6dso_fifo_status_get(stmdev_ctx_t *ctx, 3621 lsm6dso_fifo_status2_t *val); 3622 3623 int32_t lsm6dso_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val); 3624 3625 int32_t lsm6dso_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); 3626 3627 int32_t lsm6dso_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); 3628 3629 int32_t lsm6dso_fifo_sensor_tag_get(stmdev_ctx_t *ctx, 3630 lsm6dso_fifo_tag_t *val); 3631 3632 int32_t lsm6dso_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val); 3633 int32_t lsm6dso_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val); 3634 3635 int32_t lsm6dso_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val); 3636 int32_t lsm6dso_sh_batch_slave_0_get(stmdev_ctx_t *ctx, uint8_t *val); 3637 3638 int32_t lsm6dso_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val); 3639 int32_t lsm6dso_sh_batch_slave_1_get(stmdev_ctx_t *ctx, uint8_t *val); 3640 3641 int32_t lsm6dso_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val); 3642 int32_t lsm6dso_sh_batch_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val); 3643 3644 int32_t lsm6dso_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val); 3645 int32_t lsm6dso_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val); 3646 3647 typedef enum 3648 { 3649 LSM6DSO_DEN_DISABLE = 0, 3650 LSM6DSO_LEVEL_FIFO = 6, 3651 LSM6DSO_LEVEL_LETCHED = 3, 3652 LSM6DSO_LEVEL_TRIGGER = 2, 3653 LSM6DSO_EDGE_TRIGGER = 4, 3654 } lsm6dso_den_mode_t; 3655 int32_t lsm6dso_den_mode_set(stmdev_ctx_t *ctx, 3656 lsm6dso_den_mode_t val); 3657 int32_t lsm6dso_den_mode_get(stmdev_ctx_t *ctx, 3658 lsm6dso_den_mode_t *val); 3659 3660 typedef enum 3661 { 3662 LSM6DSO_DEN_ACT_LOW = 0, 3663 LSM6DSO_DEN_ACT_HIGH = 1, 3664 } lsm6dso_den_lh_t; 3665 int32_t lsm6dso_den_polarity_set(stmdev_ctx_t *ctx, 3666 lsm6dso_den_lh_t val); 3667 int32_t lsm6dso_den_polarity_get(stmdev_ctx_t *ctx, 3668 lsm6dso_den_lh_t *val); 3669 3670 typedef enum 3671 { 3672 LSM6DSO_STAMP_IN_GY_DATA = 0, 3673 LSM6DSO_STAMP_IN_XL_DATA = 1, 3674 LSM6DSO_STAMP_IN_GY_XL_DATA = 2, 3675 } lsm6dso_den_xl_g_t; 3676 int32_t lsm6dso_den_enable_set(stmdev_ctx_t *ctx, 3677 lsm6dso_den_xl_g_t val); 3678 int32_t lsm6dso_den_enable_get(stmdev_ctx_t *ctx, 3679 lsm6dso_den_xl_g_t *val); 3680 3681 int32_t lsm6dso_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val); 3682 int32_t lsm6dso_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val); 3683 3684 int32_t lsm6dso_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val); 3685 int32_t lsm6dso_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val); 3686 3687 int32_t lsm6dso_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val); 3688 int32_t lsm6dso_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val); 3689 3690 typedef enum 3691 { 3692 LSM6DSO_PEDO_BASE_MODE = 0x00, 3693 LSM6DSO_FALSE_STEP_REJ = 0x10, 3694 LSM6DSO_FALSE_STEP_REJ_ADV_MODE = 0x30, 3695 } lsm6dso_pedo_md_t; 3696 int32_t lsm6dso_pedo_sens_set(stmdev_ctx_t *ctx, 3697 lsm6dso_pedo_md_t val); 3698 int32_t lsm6dso_pedo_sens_get(stmdev_ctx_t *ctx, 3699 lsm6dso_pedo_md_t *val); 3700 3701 int32_t lsm6dso_pedo_step_detect_get(stmdev_ctx_t *ctx, uint8_t *val); 3702 3703 int32_t lsm6dso_pedo_debounce_steps_set(stmdev_ctx_t *ctx, 3704 uint8_t *buff); 3705 int32_t lsm6dso_pedo_debounce_steps_get(stmdev_ctx_t *ctx, 3706 uint8_t *buff); 3707 3708 int32_t lsm6dso_pedo_steps_period_set(stmdev_ctx_t *ctx, 3709 uint16_t val); 3710 int32_t lsm6dso_pedo_steps_period_get(stmdev_ctx_t *ctx, 3711 uint16_t *val); 3712 3713 typedef enum 3714 { 3715 LSM6DSO_EVERY_STEP = 0, 3716 LSM6DSO_COUNT_OVERFLOW = 1, 3717 } lsm6dso_carry_count_en_t; 3718 int32_t lsm6dso_pedo_int_mode_set(stmdev_ctx_t *ctx, 3719 lsm6dso_carry_count_en_t val); 3720 int32_t lsm6dso_pedo_int_mode_get(stmdev_ctx_t *ctx, 3721 lsm6dso_carry_count_en_t *val); 3722 3723 int32_t lsm6dso_motion_flag_data_ready_get(stmdev_ctx_t *ctx, 3724 uint8_t *val); 3725 3726 int32_t lsm6dso_tilt_flag_data_ready_get(stmdev_ctx_t *ctx, 3727 uint8_t *val); 3728 3729 int32_t lsm6dso_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val); 3730 int32_t lsm6dso_mag_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val); 3731 3732 int32_t lsm6dso_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val); 3733 int32_t lsm6dso_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val); 3734 3735 int32_t lsm6dso_mag_soft_iron_set(stmdev_ctx_t *ctx, int16_t *val); 3736 int32_t lsm6dso_mag_soft_iron_get(stmdev_ctx_t *ctx, int16_t *val); 3737 3738 typedef enum 3739 { 3740 LSM6DSO_Z_EQ_Y = 0, 3741 LSM6DSO_Z_EQ_MIN_Y = 1, 3742 LSM6DSO_Z_EQ_X = 2, 3743 LSM6DSO_Z_EQ_MIN_X = 3, 3744 LSM6DSO_Z_EQ_MIN_Z = 4, 3745 LSM6DSO_Z_EQ_Z = 5, 3746 } lsm6dso_mag_z_axis_t; 3747 int32_t lsm6dso_mag_z_orient_set(stmdev_ctx_t *ctx, 3748 lsm6dso_mag_z_axis_t val); 3749 int32_t lsm6dso_mag_z_orient_get(stmdev_ctx_t *ctx, 3750 lsm6dso_mag_z_axis_t *val); 3751 3752 typedef enum 3753 { 3754 LSM6DSO_Y_EQ_Y = 0, 3755 LSM6DSO_Y_EQ_MIN_Y = 1, 3756 LSM6DSO_Y_EQ_X = 2, 3757 LSM6DSO_Y_EQ_MIN_X = 3, 3758 LSM6DSO_Y_EQ_MIN_Z = 4, 3759 LSM6DSO_Y_EQ_Z = 5, 3760 } lsm6dso_mag_y_axis_t; 3761 int32_t lsm6dso_mag_y_orient_set(stmdev_ctx_t *ctx, 3762 lsm6dso_mag_y_axis_t val); 3763 int32_t lsm6dso_mag_y_orient_get(stmdev_ctx_t *ctx, 3764 lsm6dso_mag_y_axis_t *val); 3765 3766 typedef enum 3767 { 3768 LSM6DSO_X_EQ_Y = 0, 3769 LSM6DSO_X_EQ_MIN_Y = 1, 3770 LSM6DSO_X_EQ_X = 2, 3771 LSM6DSO_X_EQ_MIN_X = 3, 3772 LSM6DSO_X_EQ_MIN_Z = 4, 3773 LSM6DSO_X_EQ_Z = 5, 3774 } lsm6dso_mag_x_axis_t; 3775 int32_t lsm6dso_mag_x_orient_set(stmdev_ctx_t *ctx, 3776 lsm6dso_mag_x_axis_t val); 3777 int32_t lsm6dso_mag_x_orient_get(stmdev_ctx_t *ctx, 3778 lsm6dso_mag_x_axis_t *val); 3779 3780 int32_t lsm6dso_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, 3781 uint8_t *val); 3782 3783 typedef struct 3784 { 3785 lsm6dso_fsm_enable_a_t fsm_enable_a; 3786 lsm6dso_fsm_enable_b_t fsm_enable_b; 3787 } lsm6dso_emb_fsm_enable_t; 3788 int32_t lsm6dso_fsm_enable_set(stmdev_ctx_t *ctx, 3789 lsm6dso_emb_fsm_enable_t *val); 3790 int32_t lsm6dso_fsm_enable_get(stmdev_ctx_t *ctx, 3791 lsm6dso_emb_fsm_enable_t *val); 3792 3793 int32_t lsm6dso_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val); 3794 int32_t lsm6dso_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val); 3795 3796 typedef enum 3797 { 3798 LSM6DSO_LC_NORMAL = 0, 3799 LSM6DSO_LC_CLEAR = 1, 3800 LSM6DSO_LC_CLEAR_DONE = 2, 3801 } lsm6dso_fsm_lc_clr_t; 3802 int32_t lsm6dso_long_clr_set(stmdev_ctx_t *ctx, 3803 lsm6dso_fsm_lc_clr_t val); 3804 int32_t lsm6dso_long_clr_get(stmdev_ctx_t *ctx, 3805 lsm6dso_fsm_lc_clr_t *val); 3806 3807 typedef struct 3808 { 3809 lsm6dso_fsm_outs1_t fsm_outs1; 3810 lsm6dso_fsm_outs2_t fsm_outs2; 3811 lsm6dso_fsm_outs3_t fsm_outs3; 3812 lsm6dso_fsm_outs4_t fsm_outs4; 3813 lsm6dso_fsm_outs5_t fsm_outs5; 3814 lsm6dso_fsm_outs6_t fsm_outs6; 3815 lsm6dso_fsm_outs7_t fsm_outs7; 3816 lsm6dso_fsm_outs8_t fsm_outs8; 3817 lsm6dso_fsm_outs9_t fsm_outs9; 3818 lsm6dso_fsm_outs10_t fsm_outs10; 3819 lsm6dso_fsm_outs11_t fsm_outs11; 3820 lsm6dso_fsm_outs12_t fsm_outs12; 3821 lsm6dso_fsm_outs13_t fsm_outs13; 3822 lsm6dso_fsm_outs14_t fsm_outs14; 3823 lsm6dso_fsm_outs15_t fsm_outs15; 3824 lsm6dso_fsm_outs16_t fsm_outs16; 3825 } lsm6dso_fsm_out_t; 3826 int32_t lsm6dso_fsm_out_get(stmdev_ctx_t *ctx, 3827 lsm6dso_fsm_out_t *val); 3828 3829 typedef enum 3830 { 3831 LSM6DSO_ODR_FSM_12Hz5 = 0, 3832 LSM6DSO_ODR_FSM_26Hz = 1, 3833 LSM6DSO_ODR_FSM_52Hz = 2, 3834 LSM6DSO_ODR_FSM_104Hz = 3, 3835 } lsm6dso_fsm_odr_t; 3836 int32_t lsm6dso_fsm_data_rate_set(stmdev_ctx_t *ctx, 3837 lsm6dso_fsm_odr_t val); 3838 int32_t lsm6dso_fsm_data_rate_get(stmdev_ctx_t *ctx, 3839 lsm6dso_fsm_odr_t *val); 3840 3841 int32_t lsm6dso_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val); 3842 int32_t lsm6dso_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val); 3843 3844 int32_t lsm6dso_long_cnt_int_value_set(stmdev_ctx_t *ctx, 3845 uint16_t val); 3846 int32_t lsm6dso_long_cnt_int_value_get(stmdev_ctx_t *ctx, 3847 uint16_t *val); 3848 3849 int32_t lsm6dso_fsm_number_of_programs_set(stmdev_ctx_t *ctx, 3850 uint8_t val); 3851 int32_t lsm6dso_fsm_number_of_programs_get(stmdev_ctx_t *ctx, 3852 uint8_t *val); 3853 3854 int32_t lsm6dso_fsm_start_address_set(stmdev_ctx_t *ctx, 3855 uint16_t val); 3856 int32_t lsm6dso_fsm_start_address_get(stmdev_ctx_t *ctx, 3857 uint16_t *val); 3858 3859 int32_t lsm6dso_sh_read_data_raw_get(stmdev_ctx_t *ctx, uint8_t *val, 3860 uint8_t len); 3861 3862 typedef enum 3863 { 3864 LSM6DSO_SLV_0 = 0, 3865 LSM6DSO_SLV_0_1 = 1, 3866 LSM6DSO_SLV_0_1_2 = 2, 3867 LSM6DSO_SLV_0_1_2_3 = 3, 3868 } lsm6dso_aux_sens_on_t; 3869 int32_t lsm6dso_sh_slave_connected_set(stmdev_ctx_t *ctx, 3870 lsm6dso_aux_sens_on_t val); 3871 int32_t lsm6dso_sh_slave_connected_get(stmdev_ctx_t *ctx, 3872 lsm6dso_aux_sens_on_t *val); 3873 3874 int32_t lsm6dso_sh_master_set(stmdev_ctx_t *ctx, uint8_t val); 3875 int32_t lsm6dso_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val); 3876 3877 typedef enum 3878 { 3879 LSM6DSO_EXT_PULL_UP = 0, 3880 LSM6DSO_INTERNAL_PULL_UP = 1, 3881 } lsm6dso_shub_pu_en_t; 3882 int32_t lsm6dso_sh_pin_mode_set(stmdev_ctx_t *ctx, 3883 lsm6dso_shub_pu_en_t val); 3884 int32_t lsm6dso_sh_pin_mode_get(stmdev_ctx_t *ctx, 3885 lsm6dso_shub_pu_en_t *val); 3886 3887 int32_t lsm6dso_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val); 3888 int32_t lsm6dso_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val); 3889 3890 typedef enum 3891 { 3892 LSM6DSO_EXT_ON_INT2_PIN = 1, 3893 LSM6DSO_XL_GY_DRDY = 0, 3894 } lsm6dso_start_config_t; 3895 int32_t lsm6dso_sh_syncro_mode_set(stmdev_ctx_t *ctx, 3896 lsm6dso_start_config_t val); 3897 int32_t lsm6dso_sh_syncro_mode_get(stmdev_ctx_t *ctx, 3898 lsm6dso_start_config_t *val); 3899 3900 typedef enum 3901 { 3902 LSM6DSO_EACH_SH_CYCLE = 0, 3903 LSM6DSO_ONLY_FIRST_CYCLE = 1, 3904 } lsm6dso_write_once_t; 3905 int32_t lsm6dso_sh_write_mode_set(stmdev_ctx_t *ctx, 3906 lsm6dso_write_once_t val); 3907 int32_t lsm6dso_sh_write_mode_get(stmdev_ctx_t *ctx, 3908 lsm6dso_write_once_t *val); 3909 3910 int32_t lsm6dso_sh_reset_set(stmdev_ctx_t *ctx); 3911 int32_t lsm6dso_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val); 3912 3913 typedef enum 3914 { 3915 LSM6DSO_SH_ODR_104Hz = 0, 3916 LSM6DSO_SH_ODR_52Hz = 1, 3917 LSM6DSO_SH_ODR_26Hz = 2, 3918 LSM6DSO_SH_ODR_13Hz = 3, 3919 } lsm6dso_shub_odr_t; 3920 int32_t lsm6dso_sh_data_rate_set(stmdev_ctx_t *ctx, 3921 lsm6dso_shub_odr_t val); 3922 int32_t lsm6dso_sh_data_rate_get(stmdev_ctx_t *ctx, 3923 lsm6dso_shub_odr_t *val); 3924 3925 typedef struct 3926 { 3927 uint8_t slv0_add; 3928 uint8_t slv0_subadd; 3929 uint8_t slv0_data; 3930 } lsm6dso_sh_cfg_write_t; 3931 int32_t lsm6dso_sh_cfg_write(stmdev_ctx_t *ctx, 3932 lsm6dso_sh_cfg_write_t *val); 3933 3934 typedef struct 3935 { 3936 uint8_t slv_add; 3937 uint8_t slv_subadd; 3938 uint8_t slv_len; 3939 } lsm6dso_sh_cfg_read_t; 3940 int32_t lsm6dso_sh_slv0_cfg_read(stmdev_ctx_t *ctx, 3941 lsm6dso_sh_cfg_read_t *val); 3942 int32_t lsm6dso_sh_slv1_cfg_read(stmdev_ctx_t *ctx, 3943 lsm6dso_sh_cfg_read_t *val); 3944 int32_t lsm6dso_sh_slv2_cfg_read(stmdev_ctx_t *ctx, 3945 lsm6dso_sh_cfg_read_t *val); 3946 int32_t lsm6dso_sh_slv3_cfg_read(stmdev_ctx_t *ctx, 3947 lsm6dso_sh_cfg_read_t *val); 3948 3949 int32_t lsm6dso_sh_status_get(stmdev_ctx_t *ctx, 3950 lsm6dso_status_master_t *val); 3951 3952 3953 typedef struct 3954 { 3955 uint8_t ui; 3956 uint8_t aux; 3957 } lsm6dso_id_t; 3958 int32_t lsm6dso_id_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, 3959 lsm6dso_id_t *val); 3960 3961 typedef struct 3962 { 3963 enum 3964 { 3965 LSM6DSO_SEL_BY_HW = 0x00, /* bus mode select by HW (SPI 3W disable) */ 3966 LSM6DSO_SPI_4W = 0x06, /* Only SPI: SDO / SDI separated pins */ 3967 LSM6DSO_SPI_3W = 0x07, /* Only SPI: SDO / SDI share the same pin */ 3968 LSM6DSO_I2C = 0x04, /* Only I2C */ 3969 LSM6DSO_I3C_T_50us = 0x02, /* I3C: available time equal to 50 μs */ 3970 LSM6DSO_I3C_T_2us = 0x12, /* I3C: available time equal to 2 μs */ 3971 LSM6DSO_I3C_T_1ms = 0x22, /* I3C: available time equal to 1 ms */ 3972 LSM6DSO_I3C_T_25ms = 0x32, /* I3C: available time equal to 25 ms */ 3973 } ui_bus_md; 3974 enum 3975 { 3976 LSM6DSO_SPI_4W_AUX = 0x00, 3977 LSM6DSO_SPI_3W_AUX = 0x01, 3978 } aux_bus_md; 3979 } lsm6dso_bus_mode_t; 3980 int32_t lsm6dso_bus_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, 3981 lsm6dso_bus_mode_t val); 3982 int32_t lsm6dso_bus_mode_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, 3983 lsm6dso_bus_mode_t *val); 3984 3985 typedef enum 3986 { 3987 LSM6DSO_DRV_RDY = 0x00, /* Initialize the device for driver usage */ 3988 LSM6DSO_BOOT = 0x01, /* Restore calib. param. ( it takes 10ms ) */ 3989 LSM6DSO_RESET = 0x02, /* Reset configuration registers */ 3990 LSM6DSO_FIFO_COMP = 0x04, /* FIFO compression initialization request. */ 3991 LSM6DSO_FSM = 0x08, /* Finite State Machine initialization request */ 3992 LSM6DSO_PEDO = 0x20, /* Pedometer algo initialization request. */ 3993 LSM6DSO_TILT = 0x40, /* Tilt algo initialization request */ 3994 LSM6DSO_SMOTION = 0x80, /* Significant Motion initialization request */ 3995 } lsm6dso_init_t; 3996 int32_t lsm6dso_init_set(stmdev_ctx_t *ctx, lsm6dso_init_t val); 3997 3998 typedef struct 3999 { 4000 uint8_t sw_reset : 4001 1; /* Restoring configuration registers */ 4002 uint8_t boot : 1; /* Restoring calibration parameters */ 4003 uint8_t drdy_xl : 1; /* Accelerometer data ready */ 4004 uint8_t drdy_g : 1; /* Gyroscope data ready */ 4005 uint8_t drdy_temp : 1; /* Temperature data ready */ 4006 uint8_t ois_drdy_xl : 1; /* Accelerometer data ready on OIS */ 4007 uint8_t ois_drdy_g : 1; /* Gyroscope data ready on OIS */ 4008 uint8_t ois_gyro_settling : 4009 1; /* Gyroscope is in the settling phase */ 4010 } lsm6dso_status_t; 4011 int32_t lsm6dso_status_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, 4012 lsm6dso_status_t *val); 4013 4014 typedef struct 4015 { 4016 uint8_t sdo_sa0_pull_up : 1; /* 1 = pull-up on SDO/SA0 pin */ 4017 uint8_t aux_sdo_ocs_pull_up : 4018 1; /* 1 = pull-up on OCS_Aux/SDO_Aux pins */ 4019 uint8_t int1_int2_push_pull : 1; /* 1 = push-pull / 0 = open-drain*/ 4020 uint8_t int1_pull_down : 4021 1; /* 1 = pull-down always disabled (0=auto) */ 4022 } lsm6dso_pin_conf_t; 4023 int32_t lsm6dso_pin_conf_set(stmdev_ctx_t *ctx, 4024 lsm6dso_pin_conf_t val); 4025 int32_t lsm6dso_pin_conf_get(stmdev_ctx_t *ctx, 4026 lsm6dso_pin_conf_t *val); 4027 4028 typedef struct 4029 { 4030 uint8_t active_low : 1; /* 1 = active low / 0 = active high */ 4031 uint8_t base_latched : 4032 1; /* base functions are: FF, WU, 6D, Tap, Act/Inac */ 4033 uint8_t emb_latched : 4034 1; /* emb functions are: Pedo, Tilt, SMot, Timestamp */ 4035 } lsm6dso_int_mode_t; 4036 int32_t lsm6dso_interrupt_mode_set(stmdev_ctx_t *ctx, 4037 lsm6dso_int_mode_t val); 4038 int32_t lsm6dso_interrupt_mode_get(stmdev_ctx_t *ctx, 4039 lsm6dso_int_mode_t *val); 4040 4041 typedef struct 4042 { 4043 uint8_t drdy_xl : 1; /* Accelerometer data ready */ 4044 uint8_t drdy_g : 1; /* Gyroscope data ready */ 4045 uint8_t drdy_temp : 4046 1; /* Temperature data ready (1 = int2 pin disable) */ 4047 uint8_t boot : 1; /* Restoring calibration parameters */ 4048 uint8_t fifo_th : 1; /* FIFO threshold reached */ 4049 uint8_t fifo_ovr : 1; /* FIFO overrun */ 4050 uint8_t fifo_full : 1; /* FIFO full */ 4051 uint8_t fifo_bdr : 1; /* FIFO Batch counter threshold reached */ 4052 uint8_t den_flag : 4053 1; /* external trigger level recognition (DEN) */ 4054 uint8_t sh_endop : 1; /* sensor hub end operation */ 4055 uint8_t timestamp : 4056 1; /* timestamp overflow (1 = int2 pin disable) */ 4057 uint8_t six_d : 1; /* orientation change (6D/4D detection) */ 4058 uint8_t double_tap : 1; /* double-tap event */ 4059 uint8_t free_fall : 1; /* free fall event */ 4060 uint8_t wake_up : 1; /* wake up event */ 4061 uint8_t single_tap : 1; /* single-tap event */ 4062 uint8_t sleep_change : 4063 1; /* Act/Inact (or Vice-versa) status changed */ 4064 uint8_t step_detector : 1; /* Step detected */ 4065 uint8_t tilt : 1; /* Relative tilt event detected */ 4066 uint8_t sig_mot : 1; /* "significant motion" event detected */ 4067 uint8_t fsm_lc : 4068 1; /* fsm long counter timeout interrupt event */ 4069 uint8_t fsm1 : 1; /* fsm 1 interrupt event */ 4070 uint8_t fsm2 : 1; /* fsm 2 interrupt event */ 4071 uint8_t fsm3 : 1; /* fsm 3 interrupt event */ 4072 uint8_t fsm4 : 1; /* fsm 4 interrupt event */ 4073 uint8_t fsm5 : 1; /* fsm 5 interrupt event */ 4074 uint8_t fsm6 : 1; /* fsm 6 interrupt event */ 4075 uint8_t fsm7 : 1; /* fsm 7 interrupt event */ 4076 uint8_t fsm8 : 1; /* fsm 8 interrupt event */ 4077 uint8_t fsm9 : 1; /* fsm 9 interrupt event */ 4078 uint8_t fsm10 : 1; /* fsm 10 interrupt event */ 4079 uint8_t fsm11 : 1; /* fsm 11 interrupt event */ 4080 uint8_t fsm12 : 1; /* fsm 12 interrupt event */ 4081 uint8_t fsm13 : 1; /* fsm 13 interrupt event */ 4082 uint8_t fsm14 : 1; /* fsm 14 interrupt event */ 4083 uint8_t fsm15 : 1; /* fsm 15 interrupt event */ 4084 uint8_t fsm16 : 1; /* fsm 16 interrupt event */ 4085 uint8_t mlc1 : 1; /* mlc 1 interrupt event */ 4086 uint8_t mlc2 : 1; /* mlc 2 interrupt event */ 4087 uint8_t mlc3 : 1; /* mlc 3 interrupt event */ 4088 uint8_t mlc4 : 1; /* mlc 4 interrupt event */ 4089 uint8_t mlc5 : 1; /* mlc 5 interrupt event */ 4090 uint8_t mlc6 : 1; /* mlc 6 interrupt event */ 4091 uint8_t mlc7 : 1; /* mlc 7 interrupt event */ 4092 uint8_t mlc8 : 1; /* mlc 8 interrupt event */ 4093 } lsm6dso_pin_int1_route_t; 4094 4095 int32_t lsm6dso_pin_int1_route_set(stmdev_ctx_t *ctx, 4096 lsm6dso_pin_int1_route_t val); 4097 int32_t lsm6dso_pin_int1_route_get(stmdev_ctx_t *ctx, 4098 lsm6dso_pin_int1_route_t *val); 4099 4100 typedef struct 4101 { 4102 uint8_t drdy_ois : 1; /* OIS chain data ready */ 4103 uint8_t drdy_xl : 1; /* Accelerometer data ready */ 4104 uint8_t drdy_g : 1; /* Gyroscope data ready */ 4105 uint8_t drdy_temp : 1; /* Temperature data ready */ 4106 uint8_t fifo_th : 1; /* FIFO threshold reached */ 4107 uint8_t fifo_ovr : 1; /* FIFO overrun */ 4108 uint8_t fifo_full : 1; /* FIFO full */ 4109 uint8_t fifo_bdr : 1; /* FIFO Batch counter threshold reached */ 4110 uint8_t timestamp : 1; /* timestamp overflow */ 4111 uint8_t six_d : 1; /* orientation change (6D/4D detection) */ 4112 uint8_t double_tap : 1; /* double-tap event */ 4113 uint8_t free_fall : 1; /* free fall event */ 4114 uint8_t wake_up : 1; /* wake up event */ 4115 uint8_t single_tap : 1; /* single-tap event */ 4116 uint8_t sleep_change : 4117 1; /* Act/Inact (or Vice-versa) status changed */ 4118 uint8_t step_detector : 1; /* Step detected */ 4119 uint8_t tilt : 1; /* Relative tilt event detected */ 4120 uint8_t sig_mot : 1; /* "significant motion" event detected */ 4121 uint8_t fsm_lc : 4122 1; /* fsm long counter timeout interrupt event */ 4123 uint8_t fsm1 : 1; /* fsm 1 interrupt event */ 4124 uint8_t fsm2 : 1; /* fsm 2 interrupt event */ 4125 uint8_t fsm3 : 1; /* fsm 3 interrupt event */ 4126 uint8_t fsm4 : 1; /* fsm 4 interrupt event */ 4127 uint8_t fsm5 : 1; /* fsm 5 interrupt event */ 4128 uint8_t fsm6 : 1; /* fsm 6 interrupt event */ 4129 uint8_t fsm7 : 1; /* fsm 7 interrupt event */ 4130 uint8_t fsm8 : 1; /* fsm 8 interrupt event */ 4131 uint8_t fsm9 : 1; /* fsm 9 interrupt event */ 4132 uint8_t fsm10 : 1; /* fsm 10 interrupt event */ 4133 uint8_t fsm11 : 1; /* fsm 11 interrupt event */ 4134 uint8_t fsm12 : 1; /* fsm 12 interrupt event */ 4135 uint8_t fsm13 : 1; /* fsm 13 interrupt event */ 4136 uint8_t fsm14 : 1; /* fsm 14 interrupt event */ 4137 uint8_t fsm15 : 1; /* fsm 15 interrupt event */ 4138 uint8_t fsm16 : 1; /* fsm 16 interrupt event */ 4139 uint8_t mlc1 : 1; /* mlc 1 interrupt event */ 4140 uint8_t mlc2 : 1; /* mlc 2 interrupt event */ 4141 uint8_t mlc3 : 1; /* mlc 3 interrupt event */ 4142 uint8_t mlc4 : 1; /* mlc 4 interrupt event */ 4143 uint8_t mlc5 : 1; /* mlc 5 interrupt event */ 4144 uint8_t mlc6 : 1; /* mlc 6 interrupt event */ 4145 uint8_t mlc7 : 1; /* mlc 7 interrupt event */ 4146 uint8_t mlc8 : 1; /* mlc 8 interrupt event */ 4147 } lsm6dso_pin_int2_route_t; 4148 4149 int32_t lsm6dso_pin_int2_route_set(stmdev_ctx_t *ctx, 4150 stmdev_ctx_t *aux_ctx, 4151 lsm6dso_pin_int2_route_t val); 4152 int32_t lsm6dso_pin_int2_route_get(stmdev_ctx_t *ctx, 4153 stmdev_ctx_t *aux_ctx, 4154 lsm6dso_pin_int2_route_t *val); 4155 4156 typedef struct 4157 { 4158 uint8_t drdy_xl : 1; /* Accelerometer data ready */ 4159 uint8_t drdy_g : 1; /* Gyroscope data ready */ 4160 uint8_t drdy_temp : 1; /* Temperature data ready */ 4161 uint8_t den_flag : 4162 1; /* external trigger level recognition (DEN) */ 4163 uint8_t timestamp : 4164 1; /* timestamp overflow (1 = int2 pin disable) */ 4165 uint8_t free_fall : 1; /* free fall event */ 4166 uint8_t wake_up : 1; /* wake up event */ 4167 uint8_t wake_up_z : 1; /* wake up on Z axis event */ 4168 uint8_t wake_up_y : 1; /* wake up on Y axis event */ 4169 uint8_t wake_up_x : 1; /* wake up on X axis event */ 4170 uint8_t single_tap : 1; /* single-tap event */ 4171 uint8_t double_tap : 1; /* double-tap event */ 4172 uint8_t tap_z : 1; /* single-tap on Z axis event */ 4173 uint8_t tap_y : 1; /* single-tap on Y axis event */ 4174 uint8_t tap_x : 1; /* single-tap on X axis event */ 4175 uint8_t tap_sign : 1; /* sign of tap event (0-pos / 1-neg) */ 4176 uint8_t six_d : 4177 1; /* orientation change (6D/4D detection) */ 4178 uint8_t six_d_xl : 4179 1; /* X-axis low 6D/4D event (under threshold) */ 4180 uint8_t six_d_xh : 4181 1; /* X-axis high 6D/4D event (over threshold) */ 4182 uint8_t six_d_yl : 4183 1; /* Y-axis low 6D/4D event (under threshold) */ 4184 uint8_t six_d_yh : 4185 1; /* Y-axis high 6D/4D event (over threshold) */ 4186 uint8_t six_d_zl : 4187 1; /* Z-axis low 6D/4D event (under threshold) */ 4188 uint8_t six_d_zh : 4189 1; /* Z-axis high 6D/4D event (over threshold) */ 4190 uint8_t sleep_change : 4191 1; /* Act/Inact (or Vice-versa) status changed */ 4192 uint8_t sleep_state : 4193 1; /* Act/Inact status flag (0-Act / 1-Inact) */ 4194 uint8_t step_detector : 1; /* Step detected */ 4195 uint8_t tilt : 1; /* Relative tilt event detected */ 4196 uint8_t sig_mot : 4197 1; /* "significant motion" event detected */ 4198 uint8_t fsm_lc : 4199 1; /* fsm long counter timeout interrupt event */ 4200 uint8_t fsm1 : 1; /* fsm 1 interrupt event */ 4201 uint8_t fsm2 : 1; /* fsm 2 interrupt event */ 4202 uint8_t fsm3 : 1; /* fsm 3 interrupt event */ 4203 uint8_t fsm4 : 1; /* fsm 4 interrupt event */ 4204 uint8_t fsm5 : 1; /* fsm 5 interrupt event */ 4205 uint8_t fsm6 : 1; /* fsm 6 interrupt event */ 4206 uint8_t fsm7 : 1; /* fsm 7 interrupt event */ 4207 uint8_t fsm8 : 1; /* fsm 8 interrupt event */ 4208 uint8_t fsm9 : 1; /* fsm 9 interrupt event */ 4209 uint8_t fsm10 : 1; /* fsm 10 interrupt event */ 4210 uint8_t fsm11 : 1; /* fsm 11 interrupt event */ 4211 uint8_t fsm12 : 1; /* fsm 12 interrupt event */ 4212 uint8_t fsm13 : 1; /* fsm 13 interrupt event */ 4213 uint8_t fsm14 : 1; /* fsm 14 interrupt event */ 4214 uint8_t fsm15 : 1; /* fsm 15 interrupt event */ 4215 uint8_t fsm16 : 1; /* fsm 16 interrupt event */ 4216 uint8_t mlc1 : 1; /* mlc 1 interrupt event */ 4217 uint8_t mlc2 : 1; /* mlc 2 interrupt event */ 4218 uint8_t mlc3 : 1; /* mlc 3 interrupt event */ 4219 uint8_t mlc4 : 1; /* mlc 4 interrupt event */ 4220 uint8_t mlc5 : 1; /* mlc 5 interrupt event */ 4221 uint8_t mlc6 : 1; /* mlc 6 interrupt event */ 4222 uint8_t mlc7 : 1; /* mlc 7 interrupt event */ 4223 uint8_t mlc8 : 1; /* mlc 8 interrupt event */ 4224 uint8_t sh_endop : 1; /* sensor hub end operation */ 4225 uint8_t sh_slave0_nack : 4226 1; /* Not acknowledge on sensor hub slave 0 */ 4227 uint8_t sh_slave1_nack : 4228 1; /* Not acknowledge on sensor hub slave 1 */ 4229 uint8_t sh_slave2_nack : 4230 1; /* Not acknowledge on sensor hub slave 2 */ 4231 uint8_t sh_slave3_nack : 4232 1; /* Not acknowledge on sensor hub slave 3 */ 4233 uint8_t sh_wr_once : 4234 1; /* "WRITE_ONCE" end on sensor hub slave 0 */ 4235 uint16_t fifo_diff : 4236 10; /* Number of unread sensor data in FIFO*/ 4237 uint8_t fifo_ovr_latched : 1; /* Latched FIFO overrun status */ 4238 uint8_t fifo_bdr : 4239 1; /* FIFO Batch counter threshold reached */ 4240 uint8_t fifo_full : 1; /* FIFO full */ 4241 uint8_t fifo_ovr : 1; /* FIFO overrun */ 4242 uint8_t fifo_th : 1; /* FIFO threshold reached */ 4243 } lsm6dso_all_sources_t; 4244 int32_t lsm6dso_all_sources_get(stmdev_ctx_t *ctx, 4245 lsm6dso_all_sources_t *val); 4246 4247 typedef struct 4248 { 4249 uint8_t odr_fine_tune; 4250 } dev_cal_t; 4251 int32_t lsm6dso_calibration_get(stmdev_ctx_t *ctx, dev_cal_t *val); 4252 4253 typedef struct 4254 { 4255 struct 4256 { 4257 struct 4258 { 4259 enum 4260 { 4261 LSM6DSO_XL_UI_OFF = 0x00, /* in power down */ 4262 LSM6DSO_XL_UI_1Hz6_LP = 0x1B, /* @1Hz6 (low power) */ 4263 LSM6DSO_XL_UI_1Hz6_ULP = 0x2B, /* @1Hz6 (ultra low/Gy, OIS imu off) */ 4264 LSM6DSO_XL_UI_12Hz5_HP = 0x01, /* @12Hz5 (high performance) */ 4265 LSM6DSO_XL_UI_12Hz5_LP = 0x11, /* @12Hz5 (low power) */ 4266 LSM6DSO_XL_UI_12Hz5_ULP = 0x21, /* @12Hz5 (ultra low/Gy, OIS imu off) */ 4267 LSM6DSO_XL_UI_26Hz_HP = 0x02, /* @26Hz (high performance) */ 4268 LSM6DSO_XL_UI_26Hz_LP = 0x12, /* @26Hz (low power) */ 4269 LSM6DSO_XL_UI_26Hz_ULP = 0x22, /* @26Hz (ultra low/Gy, OIS imu off) */ 4270 LSM6DSO_XL_UI_52Hz_HP = 0x03, /* @52Hz (high performance) */ 4271 LSM6DSO_XL_UI_52Hz_LP = 0x13, /* @52Hz (low power) */ 4272 LSM6DSO_XL_UI_52Hz_ULP = 0x23, /* @52Hz (ultra low/Gy, OIS imu off) */ 4273 LSM6DSO_XL_UI_104Hz_HP = 0x04, /* @104Hz (high performance) */ 4274 LSM6DSO_XL_UI_104Hz_NM = 0x14, /* @104Hz (normal mode) */ 4275 LSM6DSO_XL_UI_104Hz_ULP = 0x24, /* @104Hz (ultra low/Gy, OIS imu off) */ 4276 LSM6DSO_XL_UI_208Hz_HP = 0x05, /* @208Hz (high performance) */ 4277 LSM6DSO_XL_UI_208Hz_NM = 0x15, /* @208Hz (normal mode) */ 4278 LSM6DSO_XL_UI_208Hz_ULP = 0x25, /* @208Hz (ultra low/Gy, OIS imu off) */ 4279 LSM6DSO_XL_UI_416Hz_HP = 0x06, /* @416Hz (high performance) */ 4280 LSM6DSO_XL_UI_833Hz_HP = 0x07, /* @833Hz (high performance) */ 4281 LSM6DSO_XL_UI_1667Hz_HP = 0x08, /* @1kHz66 (high performance) */ 4282 LSM6DSO_XL_UI_3333Hz_HP = 0x09, /* @3kHz33 (high performance) */ 4283 LSM6DSO_XL_UI_6667Hz_HP = 0x0A, /* @6kHz66 (high performance) */ 4284 } odr; 4285 enum 4286 { 4287 LSM6DSO_XL_UI_2g = 0, 4288 LSM6DSO_XL_UI_4g = 2, 4289 LSM6DSO_XL_UI_8g = 3, 4290 LSM6DSO_XL_UI_16g = 1, /* OIS full scale is also forced to be 16g */ 4291 } fs; 4292 } xl; 4293 struct 4294 { 4295 enum 4296 { 4297 LSM6DSO_GY_UI_OFF = 0x00, /* gy in power down */ 4298 LSM6DSO_GY_UI_12Hz5_LP = 0x11, /* gy @12Hz5 (low power) */ 4299 LSM6DSO_GY_UI_12Hz5_HP = 0x01, /* gy @12Hz5 (high performance) */ 4300 LSM6DSO_GY_UI_26Hz_LP = 0x12, /* gy @26Hz (low power) */ 4301 LSM6DSO_GY_UI_26Hz_HP = 0x02, /* gy @26Hz (high performance) */ 4302 LSM6DSO_GY_UI_52Hz_LP = 0x13, /* gy @52Hz (low power) */ 4303 LSM6DSO_GY_UI_52Hz_HP = 0x03, /* gy @52Hz (high performance) */ 4304 LSM6DSO_GY_UI_104Hz_NM = 0x14, /* gy @104Hz (low power) */ 4305 LSM6DSO_GY_UI_104Hz_HP = 0x04, /* gy @104Hz (high performance) */ 4306 LSM6DSO_GY_UI_208Hz_NM = 0x15, /* gy @208Hz (low power) */ 4307 LSM6DSO_GY_UI_208Hz_HP = 0x05, /* gy @208Hz (high performance) */ 4308 LSM6DSO_GY_UI_416Hz_HP = 0x06, /* gy @416Hz (high performance) */ 4309 LSM6DSO_GY_UI_833Hz_HP = 0x07, /* gy @833Hz (high performance) */ 4310 LSM6DSO_GY_UI_1667Hz_HP = 0x08, /* gy @1kHz66 (high performance) */ 4311 LSM6DSO_GY_UI_3333Hz_HP = 0x09, /* gy @3kHz33 (high performance) */ 4312 LSM6DSO_GY_UI_6667Hz_HP = 0x0A, /* gy @6kHz66 (high performance) */ 4313 } odr; 4314 enum 4315 { 4316 LSM6DSO_GY_UI_250dps = 0, 4317 LSM6DSO_GY_UI_125dps = 1, 4318 LSM6DSO_GY_UI_500dps = 2, 4319 LSM6DSO_GY_UI_1000dps = 4, 4320 LSM6DSO_GY_UI_2000dps = 6, 4321 } fs; 4322 } gy; 4323 } ui; 4324 struct 4325 { 4326 enum 4327 { 4328 LSM6DSO_OIS_ONLY_AUX = 0x00, /* Auxiliary SPI full control */ 4329 LSM6DSO_OIS_MIXED = 0x01, /* Enabling by UI / read-config by AUX */ 4330 } ctrl_md; 4331 struct 4332 { 4333 enum 4334 { 4335 LSM6DSO_XL_OIS_OFF = 0x00, /* in power down */ 4336 LSM6DSO_XL_OIS_6667Hz_HP = 0x01, /* @6kHz OIS imu active/NO ULP on UI */ 4337 } odr; 4338 enum 4339 { 4340 LSM6DSO_XL_OIS_2g = 0, 4341 LSM6DSO_XL_OIS_4g = 2, 4342 LSM6DSO_XL_OIS_8g = 3, 4343 LSM6DSO_XL_OIS_16g = 1, /* UI full scale is also forced to be 16g */ 4344 } fs; 4345 } xl; 4346 struct 4347 { 4348 enum 4349 { 4350 LSM6DSO_GY_OIS_OFF = 0x00, /* in power down */ 4351 LSM6DSO_GY_OIS_6667Hz_HP = 0x01, /* @6kHz No Ultra Low Power*/ 4352 } odr; 4353 enum 4354 { 4355 LSM6DSO_GY_OIS_250dps = 0, 4356 LSM6DSO_GY_OIS_125dps = 1, 4357 LSM6DSO_GY_OIS_500dps = 2, 4358 LSM6DSO_GY_OIS_1000dps = 4, 4359 LSM6DSO_GY_OIS_2000dps = 6, 4360 } fs; 4361 } gy; 4362 } ois; 4363 struct 4364 { 4365 enum 4366 { 4367 LSM6DSO_FSM_DISABLE = 0x00, 4368 LSM6DSO_FSM_XL = 0x01, 4369 LSM6DSO_FSM_GY = 0x02, 4370 LSM6DSO_FSM_XL_GY = 0x03, 4371 } sens; 4372 enum 4373 { 4374 LSM6DSO_FSM_12Hz5 = 0x00, 4375 LSM6DSO_FSM_26Hz = 0x01, 4376 LSM6DSO_FSM_52Hz = 0x02, 4377 LSM6DSO_FSM_104Hz = 0x03, 4378 } odr; 4379 } fsm; 4380 } lsm6dso_md_t; 4381 int32_t lsm6dso_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, 4382 lsm6dso_md_t *val); 4383 int32_t lsm6dso_mode_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, 4384 lsm6dso_md_t *val); 4385 typedef struct 4386 { 4387 struct 4388 { 4389 struct 4390 { 4391 float_t mg[3]; 4392 int16_t raw[3]; 4393 } xl; 4394 struct 4395 { 4396 float_t mdps[3]; 4397 int16_t raw[3]; 4398 } gy; 4399 struct 4400 { 4401 float_t deg_c; 4402 int16_t raw; 4403 } heat; 4404 } ui; 4405 struct 4406 { 4407 struct 4408 { 4409 float_t mg[3]; 4410 int16_t raw[3]; 4411 } xl; 4412 struct 4413 { 4414 float_t mdps[3]; 4415 int16_t raw[3]; 4416 } gy; 4417 } ois; 4418 } lsm6dso_data_t; 4419 int32_t lsm6dso_data_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, 4420 lsm6dso_md_t *md, lsm6dso_data_t *data); 4421 4422 typedef struct 4423 { 4424 uint8_t sig_mot : 1; /* significant motion */ 4425 uint8_t tilt : 1; /* tilt detection */ 4426 uint8_t step : 1; /* step counter/detector */ 4427 uint8_t step_adv : 1; /* step counter advanced mode */ 4428 uint8_t fsm : 1; /* finite state machine */ 4429 uint8_t fifo_compr : 1; /* FIFO compression */ 4430 } lsm6dso_emb_sens_t; 4431 int32_t lsm6dso_embedded_sens_set(stmdev_ctx_t *ctx, 4432 lsm6dso_emb_sens_t *emb_sens); 4433 int32_t lsm6dso_embedded_sens_get(stmdev_ctx_t *ctx, 4434 lsm6dso_emb_sens_t *emb_sens); 4435 int32_t lsm6dso_embedded_sens_off(stmdev_ctx_t *ctx); 4436 4437 /** 4438 * @} 4439 * 4440 */ 4441 4442 #ifdef __cplusplus 4443 } 4444 #endif 4445 4446 #endif /*LSM6DSO_DRIVER_H */ 4447 4448 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 4449
