1 /* ----------------------------------------------------------------------------- 2 * SPDX-License-Identifier: Zlib 3 * Copyright (c) 2013-2014 ARM Ltd. 4 * 5 * This software is provided 'as-is', without any express or implied warranty. 6 * In no event will the authors be held liable for any damages arising from 7 * the use of this software. Permission is granted to anyone to use this 8 * software for any purpose, including commercial applications, and to alter 9 * it and redistribute it freely, subject to the following restrictions: 10 * 11 * 1. The origin of this software must not be misrepresented; you must not 12 * claim that you wrote the original software. If you use this software in 13 * a product, an acknowledgment in the product documentation would be 14 * appreciated but is not required. 15 * 16 * 2. Altered source versions must be plainly marked as such, and must not be 17 * misrepresented as being the original software. 18 * 19 * 3. This notice may not be removed or altered from any source distribution. 20 * 21 * 22 * $Date: 9. Dec 2014 23 * $Revision: V1.00 24 * 25 * Project: SAI (Serial Audio Interface) Driver definitions 26 * -------------------------------------------------------------------------- */ 27 28 /* History: 29 * Version 1.00 30 * Initial release 31 */ 32 33 #ifndef __SAI_H__ 34 #define __SAI_H__ 35 36 #include "rsi_pll.h" 37 #include "rsi_ulpss_clk.h" 38 #include "Driver_SAI.h" 39 #include "rsi_ccp_common.h" 40 41 #include "UDMA.h" 42 43 44 /****** I2S Events *****/ 45 #define RSI_I2S_EVENT_RXDA 0x0 /*!< Receive Data available event */ 46 #define RSI_I2S_EVENT_RXDATA_OVERRUN 0x1 /*!< RX data overrun event */ 47 #define RSI_I2S_EVENT_TRANSMIT_EMPTY 0x2 /*!< TX FIFO empty event */ 48 #define RSI_I2S_EVENT_TXDATA_OVERRUN 0x3 /*!< TX data overrun event */ 49 #define RSI_I2S_EVENT_DMA_ENABLE 0x4 /*!< DMA enable event */ 50 51 /****** I2S Status Flags *****/ 52 #define I2S_STAT_RXDA (1UL << 0) /*!< RXDA interrupt flag */ 53 #define I2S_STAT_RXDATA_OVERRUN (1UL << 1) /*!< RXDO interrupt flag */ 54 #define I2S_STAT_TRANSMIT_EMPTY (1UL << 4) /*!< TXFE interrupt flag */ 55 #define I2S_STAT_TXDATA_OVERRUN (1UL << 5) /*!< TXFO interrupt flag */ 56 57 #define F_RXDA 0x01 58 #define F_RXFO 0x02 59 #define F_TXFE 0x03 60 #define F_TXFO 0x04 61 62 #define F_RXDAM (1UL << 0) 63 #define F_RXFOM (1UL << 1) 64 #define F_TXFEM (1UL << 4) 65 #define F_TXFOM (1UL << 5) 66 67 #define MASTER 0x1 68 #define SLAVE 0x0 69 #define RES_12 0x1 70 #define RES_16 0x2 71 #define RES_20 0x3 72 #define RES_24 0x4 73 74 #define MISC_SOFT_SET_REG_2 (*((uint32_t volatile *)(0x46008000UL + 0x34))) 75 #define CHNL_0 0 76 #define CHNL_1 1 77 78 /* Number of sclk cycles for which the word select 79 line (ws_out) stays in the left or right sample mode */ 80 #define WSS_24_CYCLES 0x1 81 #define WSS_16_CYCLES 0x0 82 #define WSS_32_CYCLES 0x2 83 84 #define SCLKG_12_CYCLES 0x1 85 #define SCLKG_16_CYCLES 0x2 86 #define SCLKG_20_CYCLES 0x3 87 #define SCLKG_24_CYCLES 0x4 88 #define SCLKG_NO_GATE 0x0 89 90 91 #define RX_BLOCK_EN 0x1 92 #define TX_BLOCK_EN 0x1 93 94 #define RES_12_BIT 0x1 95 #define RES_16_BIT 0x2 96 #define RES_20_BIT 0x3 97 #define RES_24_BIT 0x4 98 #define RES_32_BIT 0x5 99 100 #define I2S_FIFO_DEPTH 8 101 #define I2S_TX_TL 7 102 #define I2S_RX_TL 7 103 104 #define MASTER 0x1 105 #define SLAVE 0x0 106 107 #define PCM_EN 1 108 #define PCM_DIS 0 109 #define FSYNC_EN 1 110 #define FSYNC_DIS 0 111 112 #define ULP_I2S_CLK_SEL 8 113 #define ULP_I2S_CLK_DIV_FACT 1 114 #define M4_I2S_CLK_SEL 0 115 #define M4_I2S_CLK_DIV_FACT 0 116 117 /** 118 \brief Macro defines for MISC_SOFT_SET3_REG 119 */ 120 #define PCM_ENA (1UL << 0) 121 #define PCM_FSYNC_START_M (1UL << 1) 122 #define PCM_BIT_RES_8_SET (0 << 2) 123 #define PCM_BIT_RES_12_SET (1 << 2) 124 #define PCM_BIT_RES_16_SET (2 << 2) 125 #define PCM_BIT_RES_24_SET (3 << 2) 126 127 /** 128 \brief Macro defines for MISC_SOFT_CLR3_REG 129 */ 130 #define PCMEN (1UL << 0) 131 #define PCM_FSYNCSTART (1UL << 1) 132 #define PCM_BIT_RES_8_CLR (0 << 2) 133 #define PCM_BIT_RES_12_CLR (1 << 2) 134 #define PCM_BIT_RES_16_CLR (2 << 2) 135 #define PCM_BIT_RES_24_CLR (3 << 2) 136 137 /** 138 \brief Macro defines for MISC_CFG_MISC_CTRL1 139 */ 140 #define I2S_MASTER_SLAVE_MODE (1 << 23) /*!< Sets I2S/ PCM master mode */ 141 #define ARM_SOFT_RESET (1 << 19) 142 143 144 /** 145 \brief Macro defines for ULP_MISC_SOFT_SET_REG 146 */ 147 #define ULP_I2S_CLK_ENABLE (1UL << 6) 148 #define ULP_PCM_FSYNC_START (1UL << 1) 149 #define ULP_PCM_ENABLE (1UL << 0) 150 #define ULP_PCM_BIT_RES_8_SET (0 << 2) 151 #define ULP_PCM_BIT_RES_12_SET (1 << 2) 152 #define ULP_PCM_BIT_RES_16_SET (2 << 2) 153 #define ULP_PCM_BIT_RES_24_SET (3 << 2) 154 155 #define I2S_BLOCKING_XFER 1 156 #define I2S_NONBLOCKING_XFER 0 157 158 // I2S flags 159 #define I2S_FLAG_INITIALIZED (1U) 160 #define I2S_FLAG_POWERED (1U << 1) 161 #define I2S_FLAG_CONFIGURED (1U << 2) 162 163 #define INTR_MASK 1 164 #define INTR_UNMASK 0 165 166 #define I2S_PROTOCOL 0 167 #define PCM_PROTOCOL 1 168 169 170 171 // I2S Stream Information (Run-Time) 172 typedef struct _I2S_STREAM_INFO 173 { 174 uint32_t num; // Total number of data to be transmited/received 175 uint8_t *buf; // Pointer to data buffer 176 uint32_t cnt; // Number of data transmited/receive 177 uint8_t data_bits; // Number of data bits 178 uint8_t master; // Master flag 179 uint8_t residue_num; 180 uint8_t residue_buf[4]; 181 uint8_t residue_cnt; 182 } I2S_STREAM_INFO; 183 184 typedef struct _I2S_STATUS { 185 uint8_t tx_busy; // Transmitter busy flag 186 uint8_t rx_busy; // Receiver busy flag 187 uint8_t tx_underflow; // Transmit data underflow detected (cleared on start of next send operation) 188 uint8_t rx_overflow; // Receive data overflow detected (cleared on start of next receive operation) 189 uint8_t frame_error; // Sync Frame error detected (cleared on start of next send/receive operation) 190 } I2S_STATUS; 191 192 // I2S Information (Run-Time) 193 typedef struct _I2S_INFO 194 { 195 ARM_SAI_SignalEvent_t cb_event; // Event callback 196 I2S_STATUS status; // Status flags 197 I2S_STREAM_INFO tx; // Transmit information 198 I2S_STREAM_INFO rx; // Receive information 199 } I2S_INFO; 200 201 // I2S DMA 202 typedef struct _I2S_DMA 203 { 204 RSI_UDMA_CHA_CONFIG_DATA_T control; 205 uint8_t channel; // DMA Channel number 206 UDMA_SignalEvent_t cb_event; // DMA Event callback 207 } I2S_DMA; 208 209 // I2S Clock Config 210 typedef struct _I2S_CLK 211 { 212 uint8_t clk_src; // I2S Clock Source 213 uint8_t div_fact; // Clock Division factor 214 } I2S_CLK; 215 216 /* Pins Configuration */ 217 typedef const struct _I2S_PIN { 218 uint8_t port; ///< SPI GPIO port 219 uint8_t pin; ///< SPI GPIO pin 220 uint8_t mode; ///< SPI GPIO mode 221 uint8_t pad_sel; ///< SPI GPIO pad selection 222 }I2S_PIN; 223 224 // Input/Output Configuration 225 typedef struct I2S_IO_PINS { 226 I2S_PIN *sclk; 227 I2S_PIN *wsclk; 228 I2S_PIN *din0; 229 I2S_PIN *dout0; 230 I2S_PIN *din1; 231 I2S_PIN *dout1; 232 }I2S_IO; 233 234 // I2S Reseurces definitions 235 typedef struct 236 { 237 ARM_SAI_CAPABILITIES capabilities; // Capabilities 238 I2S0_Type *reg; // Pointer to I2S peripheral 239 IRQn_Type irq_num; // I2S IRQ Number 240 I2S_DMA *dma_tx; // I2S TX DMA configuration 241 I2S_DMA *dma_rx; // I2S RX DMA configuration 242 uint8_t tx_fifo_level; // I2S transmit fifo level 243 uint8_t rx_fifo_level; // I2S receive fifo level 244 uint8_t xfer_chnl; 245 I2S_INFO *info; // Run-Time information 246 uint32_t flags; 247 uint8_t protocol; 248 I2S_CLK *clk; 249 I2S_IO io; 250 } I2S_RESOURCES; 251 void IRQ064_Handler (void); 252 void IRQ014_Handler (void); 253 254 255 #endif /* __DRIVER_SAI_H */ 256
