1 /***************************************************************************//**
2 * @file
3 * @brief Clock management unit (CMU) API
4 *******************************************************************************
5 * # License
6 * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b>
7 *******************************************************************************
8 *
9 * SPDX-License-Identifier: Zlib
10 *
11 * The licensor of this software is Silicon Laboratories Inc.
12 *
13 * This software is provided 'as-is', without any express or implied
14 * warranty. In no event will the authors be held liable for any damages
15 * arising from the use of this software.
16 *
17 * Permission is granted to anyone to use this software for any purpose,
18 * including commercial applications, and to alter it and redistribute it
19 * freely, subject to the following restrictions:
20 *
21 * 1. The origin of this software must not be misrepresented; you must not
22 * claim that you wrote the original software. If you use this software
23 * in a product, an acknowledgment in the product documentation would be
24 * appreciated but is not required.
25 * 2. Altered source versions must be plainly marked as such, and must not be
26 * misrepresented as being the original software.
27 * 3. This notice may not be removed or altered from any source distribution.
28 *
29 ******************************************************************************/
30 #ifndef EM_CMU_H
31 #define EM_CMU_H
32
33 #include "em_device.h"
34 #if defined(CMU_PRESENT)
35
36 #include <stdbool.h>
37 #include "sl_assert.h"
38 #include "em_bus.h"
39 #include "em_cmu_compat.h"
40 #include "em_gpio.h"
41 #include "sl_common.h"
42 #include "sl_enum.h"
43 #include "sl_status.h"
44 #include "sli_em_cmu.h"
45 #ifdef __cplusplus
46 extern "C" {
47 #endif
48
49 /***************************************************************************//**
50 * @addtogroup cmu
51 * @{
52 ******************************************************************************/
53
54 /** Macro to set clock sources in the clock tree. */
55 #define CMU_CLOCK_SELECT_SET(clock, sel) CMU_##clock##_SELECT_##sel
56
57 #if defined(_SILICON_LABS_32B_SERIES_2)
58
59 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
60
61 #if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1)
62 /* Enable register bit positions, for internal use. */
63 #define CMU_EN_BIT_POS 0U
64 #define CMU_EN_BIT_MASK 0x1FU
65
66 /* Enable register ID's for internal use. */
67 #define CMU_NO_EN_REG 0
68 #define CMU_CLKEN0_EN_REG 1
69 #define CMU_CLKEN1_EN_REG 2
70 #if defined(_CMU_CLKEN2_MASK)
71 #define CMU_CLKEN2_EN_REG 3
72 #endif
73 #define CMU_CRYPTOACCCLKCTRL_EN_REG 3
74 #define CMU_EN_REG_POS 5U
75 #define CMU_EN_REG_MASK 0x3U
76
77 /* Clock branch ID's internal use. */
78 #define CMU_CORE_BRANCH 0
79 #define CMU_SYSCLK_BRANCH 1
80 #define CMU_SYSTICK_BRANCH 2
81 #define CMU_HCLK_BRANCH 3
82 #define CMU_EXPCLK_BRANCH 4
83 #define CMU_PCLK_BRANCH 5
84 #define CMU_LSPCLK_BRANCH 6
85 #define CMU_TRACECLK_BRANCH 7
86 #define CMU_EM01GRPACLK_BRANCH 8
87 #if defined(_CMU_EM01GRPBCLKCTRL_MASK)
88 #define CMU_EM01GRPBCLK_BRANCH 9
89 #endif
90 #define CMU_EUART0CLK_BRANCH 10
91 #define CMU_IADCCLK_BRANCH 11
92 #define CMU_EM23GRPACLK_BRANCH 12
93 #define CMU_WDOG0CLK_BRANCH 13
94 #if defined(RTCC_PRESENT)
95 #define CMU_RTCCCLK_BRANCH 14
96 #elif defined(SYSRTC_PRESENT)
97 #define CMU_SYSRTCCLK_BRANCH 14
98 #endif
99 #define CMU_EM4GRPACLK_BRANCH 15
100 #if defined(PDM_PRESENT)
101 #define CMU_PDMREF_BRANCH 16
102 #endif
103 #define CMU_DPLLREFCLK_BRANCH 17
104 #if WDOG_COUNT > 1
105 #define CMU_WDOG1CLK_BRANCH 18
106 #endif
107 #if defined(LCD_PRESENT)
108 #define CMU_LCD_BRANCH 19
109 #endif
110 #if defined(VDAC_PRESENT)
111 #define CMU_VDAC0_BRANCH 20
112 #endif
113 #if defined(PCNT_PRESENT)
114 #define CMU_PCNT_BRANCH 21
115 #endif
116 #if defined(LESENSE_PRESENT)
117 #define CMU_LESENSEHF_BRANCH 22
118 #define CMU_LESENSE_BRANCH 23
119 #endif
120 #if defined(_CMU_EM01GRPCCLKCTRL_MASK)
121 #define CMU_EM01GRPCCLK_BRANCH 24
122 #endif
123 #if defined(VDAC_PRESENT) && (VDAC_COUNT > 1)
124 #define CMU_VDAC1_BRANCH 25
125 #endif
126 #define CMU_CLK_BRANCH_POS 7U
127 #define CMU_CLK_BRANCH_MASK 0x1FU
128 #endif // (_SILICON_LABS_32B_SERIES_2_CONFIG > 1)
129
130 #if defined(_EMU_CMD_EM01VSCALE1_MASK)
131 /* Maximum clock frequency for VSCALE voltages. */
132 #define CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX 40000000UL
133 #endif
134
135 /* Macros for VSCALE for use with the @ref CMU_UpdateWaitStates() API.
136 * NOTE: The values must align with the values in EMU_VScaleEM01_TypeDef for
137 * Series1 parts (highest VSCALE voltage = lowest numerical value). */
138 #define VSCALE_EM01_LOW_POWER 1
139 #define VSCALE_EM01_HIGH_PERFORMANCE 0
140
141 #if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1)
142 #define PLFRCO_PRESENT
143 #endif
144
145 /** @endcond */
146
147 /*******************************************************************************
148 ******************************** ENUMS ************************************
149 ******************************************************************************/
150
151 /** Disable clocks configuration */
152 #if defined(_SILICON_LABS_32B_SERIES_2)
153 #define _CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EM01GRPACLKCTRL */
154 #define CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED (_CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EM01GRPACLKCTRL*/
155 #define _CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EM01GRPBCLKCTRL */
156 #define CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED (_CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EM01GRPBCLKCTRL*/
157 #define _CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EM23GRPACLKCTRL */
158 #define CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED (_CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EM23GRPACLKCTRL*/
159 #define _CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EM4GRPACLKCTRL */
160 #define CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED (_CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EM4GRPACLKCTRL */
161 #define _CMU_WDOG0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_WDOG0CLKCTRL */
162 #define CMU_WDOG0CLKCTRL_CLKSEL_DISABLED (_CMU_WDOG0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_WDOG0CLKCTRL */
163 #define _CMU_WDOG1CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_WDOG1CLKCTRL */
164 #define CMU_WDOG1CLKCTRL_CLKSEL_DISABLED (_CMU_WDOG1CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_WDOG1CLKCTRL */
165 #define _CMU_EUSART0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EUSART0CLKCTRL */
166 #define CMU_EUSART0CLKCTRL_CLKSEL_DISABLED (_CMU_EUSART0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EUSART0CLKCTRL*/
167 #define _CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_SYSRTC0CLKCTRL */
168 #define CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED (_CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_SYSRTC0CLKCTRL */
169 #endif // (_SILICON_LABS_32B_SERIES_2)
170
171 /** Clock divider configuration */
172 typedef uint32_t CMU_ClkDiv_TypeDef;
173
174 /** HFRCODPLL frequency bands */
SL_ENUM_GENERIC(CMU_HFRCODPLLFreq_TypeDef,uint32_t)175 SL_ENUM_GENERIC(CMU_HFRCODPLLFreq_TypeDef, uint32_t) {
176 cmuHFRCODPLLFreq_1M0Hz = 1000000U, /**< 1MHz RC band. */
177 cmuHFRCODPLLFreq_2M0Hz = 2000000U, /**< 2MHz RC band. */
178 cmuHFRCODPLLFreq_4M0Hz = 4000000U, /**< 4MHz RC band. */
179 cmuHFRCODPLLFreq_7M0Hz = 7000000U, /**< 7MHz RC band. */
180 cmuHFRCODPLLFreq_13M0Hz = 13000000U, /**< 13MHz RC band. */
181 cmuHFRCODPLLFreq_16M0Hz = 16000000U, /**< 16MHz RC band. */
182 cmuHFRCODPLLFreq_19M0Hz = 19000000U, /**< 19MHz RC band. */
183 cmuHFRCODPLLFreq_26M0Hz = 26000000U, /**< 26MHz RC band. */
184 cmuHFRCODPLLFreq_32M0Hz = 32000000U, /**< 32MHz RC band. */
185 cmuHFRCODPLLFreq_38M0Hz = 38000000U, /**< 38MHz RC band. */
186 cmuHFRCODPLLFreq_48M0Hz = 48000000U, /**< 48MHz RC band. */
187 cmuHFRCODPLLFreq_56M0Hz = 56000000U, /**< 56MHz RC band. */
188 cmuHFRCODPLLFreq_64M0Hz = 64000000U, /**< 64MHz RC band. */
189 cmuHFRCODPLLFreq_80M0Hz = 80000000U, /**< 80MHz RC band. */
190 #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5)
191 cmuHFRCODPLLFreq_100M0Hz = 100000000U, /**< 100MHz RC band. */
192 #endif
193 cmuHFRCODPLLFreq_UserDefined = 0,
194 };
195
196 #if defined(USBPLL_PRESENT)
197 /** HFXO reference frequency */
SL_ENUM_GENERIC(CMU_HFXORefFreq_TypeDef,uint32_t)198 SL_ENUM_GENERIC(CMU_HFXORefFreq_TypeDef, uint32_t) {
199 cmuHFXORefFreq_38M0Hz = (1UL << _USBPLL_CTRL_DIVR_SHIFT)
200 | (24UL << _USBPLL_CTRL_DIVX_SHIFT)
201 | (19UL << _USBPLL_CTRL_DIVN_SHIFT), /**< 38MHz input frequency. */
202 cmuHFXORefFreq_38M4Hz = (1UL << _USBPLL_CTRL_DIVR_SHIFT)
203 | (25UL << _USBPLL_CTRL_DIVX_SHIFT)
204 | (20UL << _USBPLL_CTRL_DIVN_SHIFT), /**< 38.4MHz input frequency. */
205 cmuHFXORefFreq_39M0Hz = (1UL << _USBPLL_CTRL_DIVR_SHIFT)
206 | (16UL << _USBPLL_CTRL_DIVX_SHIFT)
207 | (13UL << _USBPLL_CTRL_DIVN_SHIFT), /**< 39MHz input frequency. */
208 cmuHFXORefFreq_40M0Hz = (1UL << _USBPLL_CTRL_DIVR_SHIFT)
209 | (24UL << _USBPLL_CTRL_DIVX_SHIFT)
210 | (20UL << _USBPLL_CTRL_DIVN_SHIFT), /**< 40MHz input frequency. */
211 };
212 #endif
213
214 /** HFRCODPLL maximum frequency */
215 #define CMU_HFRCODPLL_MIN cmuHFRCODPLLFreq_1M0Hz
216 /** HFRCODPLL minimum frequency */
217 #define CMU_HFRCODPLL_MAX cmuHFRCODPLLFreq_80M0Hz
218
219 #if defined(HFRCOEM23_PRESENT)
220 /** HFRCOEM23 frequency bands */
SL_ENUM_GENERIC(CMU_HFRCOEM23Freq_TypeDef,uint32_t)221 SL_ENUM_GENERIC(CMU_HFRCOEM23Freq_TypeDef, uint32_t) {
222 cmuHFRCOEM23Freq_1M0Hz = 1000000U, /**< 1MHz RC band. */
223 cmuHFRCOEM23Freq_2M0Hz = 2000000U, /**< 2MHz RC band. */
224 cmuHFRCOEM23Freq_4M0Hz = 4000000U, /**< 4MHz RC band. */
225 cmuHFRCOEM23Freq_13M0Hz = 13000000U, /**< 13MHz RC band. */
226 cmuHFRCOEM23Freq_16M0Hz = 16000000U, /**< 16MHz RC band. */
227 cmuHFRCOEM23Freq_19M0Hz = 19000000U, /**< 19MHz RC band. */
228 cmuHFRCOEM23Freq_26M0Hz = 26000000U, /**< 26MHz RC band. */
229 cmuHFRCOEM23Freq_32M0Hz = 32000000U, /**< 32MHz RC band. */
230 cmuHFRCOEM23Freq_40M0Hz = 40000000U, /**< 40MHz RC band. */
231 cmuHFRCOEM23Freq_UserDefined = 0,
232 };
233
234 /** HFRCOEM23 maximum frequency */
235 #define CMU_HFRCOEM23_MIN cmuHFRCOEM23Freq_1M0Hz
236 /** HFRCOEM23 minimum frequency */
237 #define CMU_HFRCOEM23_MAX cmuHFRCOEM23Freq_40M0Hz
238 #endif // defined(HFRCOEM23_PRESENT)
239
240 #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1)
241 /** Clock points in CMU clock-tree. */
SL_ENUM(CMU_Clock_TypeDef)242 SL_ENUM(CMU_Clock_TypeDef) {
243 /*******************/
244 /* Clock branches */
245 /*******************/
246
247 cmuClock_SYSCLK, /**< System clock. */
248 cmuClock_HCLK, /**< Core and AHB bus interface clock. */
249 cmuClock_EXPCLK, /**< Export clock. */
250 cmuClock_PCLK, /**< Peripheral APB bus interface clock. */
251 cmuClock_LSPCLK, /**< Low speed peripheral APB bus interface clock. */
252 cmuClock_IADCCLK, /**< IADC clock. */
253 cmuClock_EM01GRPACLK, /**< EM01GRPA clock. */
254 cmuClock_EM23GRPACLK, /**< EM23GRPA clock. */
255 cmuClock_EM4GRPACLK, /**< EM4GRPA clock. */
256 cmuClock_WDOG0CLK, /**< WDOG0 clock. */
257 cmuClock_WDOG1CLK, /**< WDOG1 clock. */
258 cmuClock_DPLLREFCLK, /**< DPLL reference clock. */
259 cmuClock_TRACECLK, /**< Debug trace clock. */
260 cmuClock_RTCCCLK, /**< RTCC clock. */
261 cmuClock_HFRCOEM23,
262
263 /*********************/
264 /* Peripheral clocks */
265 /*********************/
266
267 cmuClock_CORE, /**< Cortex-M33 core clock. */
268 cmuClock_SYSTICK, /**< Optional Cortex-M33 SYSTICK clock. */
269 cmuClock_ACMP0, /**< ACMP0 clock. */
270 cmuClock_ACMP1, /**< ACMP1 clock. */
271 cmuClock_BURTC, /**< BURTC clock. */
272 cmuClock_GPCRC, /**< GPCRC clock. */
273 cmuClock_GPIO, /**< GPIO clock. */
274 cmuClock_I2C0, /**< I2C0 clock. */
275 cmuClock_I2C1, /**< I2C1 clock. */
276 cmuClock_IADC0, /**< IADC clock. */
277 cmuClock_LDMA, /**< LDMA clock. */
278 cmuClock_LETIMER0, /**< LETIMER clock. */
279 cmuClock_PRS, /**< PRS clock. */
280 cmuClock_RTCC, /**< RTCC clock. */
281 cmuClock_TIMER0, /**< TIMER0 clock. */
282 cmuClock_TIMER1, /**< TIMER1 clock. */
283 cmuClock_TIMER2, /**< TIMER2 clock. */
284 cmuClock_TIMER3, /**< TIMER3 clock. */
285 cmuClock_USART0, /**< USART0 clock. */
286 cmuClock_USART1, /**< USART1 clock. */
287 cmuClock_USART2, /**< USART2 clock. */
288 cmuClock_WDOG0, /**< WDOG0 clock. */
289 cmuClock_WDOG1, /**< WDOG1 clock. */
290 cmuClock_PDM /**< PDM clock. */
291 };
292 #endif // defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1)
293
294 /** Clock points in CMU clock-tree. */
295 #if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1)
SL_ENUM_GENERIC(CMU_Clock_TypeDef,uint32_t)296 SL_ENUM_GENERIC(CMU_Clock_TypeDef, uint32_t) {
297 /*******************/
298 /* Clock branches */
299 /*******************/
300
301 cmuClock_SYSCLK = (CMU_SYSCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< SYSTEM clock. */
302 cmuClock_SYSTICK = (CMU_SYSTICK_BRANCH << CMU_CLK_BRANCH_POS), /**< SYSTICK clock. */
303 cmuClock_HCLK = (CMU_HCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< Core and AHB bus interface clock. */
304 cmuClock_EXPCLK = (CMU_EXPCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< Export clock. */
305 cmuClock_PCLK = (CMU_PCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< Peripheral APB bus interface clock. */
306 cmuClock_LSPCLK = (CMU_LSPCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< Low speed peripheral APB bus interface clock. */
307 cmuClock_TRACECLK = (CMU_TRACECLK_BRANCH << CMU_CLK_BRANCH_POS), /**< Debug trace. */
308 cmuClock_EM01GRPACLK = (CMU_EM01GRPACLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EM01GRPA clock. */
309 #if defined(PDM_PRESENT)
310 cmuClock_EM01GRPBCLK = (CMU_EM01GRPBCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EM01GRPB clock. */
311 #endif
312 #if defined(_CMU_EM01GRPCCLKCTRL_MASK)
313 cmuClock_EM01GRPCCLK = (CMU_EM01GRPCCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EM01GRPC clock. */
314 #endif
315 #if defined(EUART_PRESENT)
316 cmuClock_EUART0CLK = (CMU_EUART0CLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EUART0 clock. */
317 #elif defined(EUSART_PRESENT)
318 cmuClock_EUSART0CLK = (CMU_EUART0CLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EUSART0 clock. */
319 #endif
320 cmuClock_IADCCLK = (CMU_IADCCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< IADC clock. */
321 cmuClock_EM23GRPACLK = (CMU_EM23GRPACLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EM23GRPA clock. */
322 cmuClock_WDOG0CLK = (CMU_WDOG0CLK_BRANCH << CMU_CLK_BRANCH_POS), /**< WDOG0 clock. */
323 #if WDOG_COUNT > 1
324 cmuClock_WDOG1CLK = (CMU_WDOG1CLK_BRANCH << CMU_CLK_BRANCH_POS), /**< WDOG1 clock. */
325 #endif
326 #if defined(RTCC_PRESENT)
327 cmuClock_RTCCCLK = (CMU_RTCCCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< RTCC clock. */
328 #elif defined(SYSRTC_PRESENT)
329 cmuClock_SYSRTCCLK = (CMU_SYSRTCCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< SYSRTC clock. */
330 #endif
331 cmuClock_EM4GRPACLK = (CMU_EM4GRPACLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EM4GRPA clock. */
332 cmuClock_DPLLREFCLK = (CMU_DPLLREFCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< DPLLREF clock. */
333 #if defined(CRYPTOACC_PRESENT)
334 cmuClock_CRYPTOAES = (CMU_CRYPTOACCCLKCTRL_EN_REG << CMU_EN_REG_POS)
335 | (_CMU_CRYPTOACCCLKCTRL_AESEN_SHIFT << CMU_EN_BIT_POS), /**< CRYPTOAES clock. */
336 cmuClock_CRYPTOPK = (CMU_CRYPTOACCCLKCTRL_EN_REG << CMU_EN_REG_POS)
337 | (_CMU_CRYPTOACCCLKCTRL_PKEN_SHIFT << CMU_EN_BIT_POS), /**< CRYPTOPK clock. */
338 #endif
339 #if defined(LCD_PRESENT)
340 cmuClock_LCDCLK = (CMU_LCD_BRANCH << CMU_CLK_BRANCH_POS), /**< LCD clock. */
341 #endif
342 #if defined(VDAC_PRESENT)
343 cmuClock_VDAC0CLK = (CMU_VDAC0_BRANCH << CMU_CLK_BRANCH_POS), /**< VDAC0 clock. */
344 #if (VDAC_COUNT > 1)
345 cmuClock_VDAC1CLK = (CMU_VDAC1_BRANCH << CMU_CLK_BRANCH_POS), /**< VDAC1 clock. */
346 #endif
347 #endif
348 #if defined(PCNT_PRESENT)
349 cmuClock_PCNT0CLK = (CMU_PCNT_BRANCH << CMU_CLK_BRANCH_POS), /**< PCNT0 clock. */
350 #endif
351 #if defined(LESENSE_PRESENT)
352 cmuClock_LESENSEHFCLK = (CMU_LESENSEHF_BRANCH << CMU_CLK_BRANCH_POS), /**< LESENSE high frequency clock. */
353 cmuClock_LESENSECLK = (CMU_LESENSE_BRANCH << CMU_CLK_BRANCH_POS), /**< LESENSE low frequency clock. */
354 #endif
355
356 cmuClock_CORE = (CMU_CORE_BRANCH << CMU_CLK_BRANCH_POS), /**< Cortex-M33 core clock. */
357 #if defined(PDM_PRESENT)
358 cmuClock_PDMREF = (CMU_PDMREF_BRANCH << CMU_CLK_BRANCH_POS), /**< PDMREF clock. */
359 #endif
360 /*********************/
361 /* Peripheral clocks */
362 /*********************/
363
364 cmuClock_LDMA = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
365 | (_CMU_CLKEN0_LDMA_SHIFT << CMU_EN_BIT_POS), /**< LDMA clock. */
366 cmuClock_LDMAXBAR = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
367 | (_CMU_CLKEN0_LDMAXBAR_SHIFT << CMU_EN_BIT_POS), /**< LDMAXBAR clock. */
368 #if defined(RADIOAES_PRESENT)
369 cmuClock_RADIOAES = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
370 | (_CMU_CLKEN0_RADIOAES_SHIFT << CMU_EN_BIT_POS), /**< RADIOAES clock. */
371 #endif
372 cmuClock_GPCRC = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
373 | (_CMU_CLKEN0_GPCRC_SHIFT << CMU_EN_BIT_POS), /**< GPCRC clock. */
374 cmuClock_TIMER0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
375 | (_CMU_CLKEN0_TIMER0_SHIFT << CMU_EN_BIT_POS), /**< TIMER0 clock. */
376 cmuClock_TIMER1 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
377 | (_CMU_CLKEN0_TIMER1_SHIFT << CMU_EN_BIT_POS), /**< TIMER1 clock. */
378 cmuClock_TIMER2 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
379 | (_CMU_CLKEN0_TIMER2_SHIFT << CMU_EN_BIT_POS), /**< TIMER2 clock. */
380 cmuClock_TIMER3 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
381 | (_CMU_CLKEN0_TIMER3_SHIFT << CMU_EN_BIT_POS), /**< TIMER3 clock. */
382 #if defined(_CMU_CLKEN2_TIMER4_SHIFT)
383 cmuClock_TIMER4 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS)
384 | (_CMU_CLKEN2_TIMER4_SHIFT << CMU_EN_BIT_POS), /**< TIMER4 clock. */
385 #elif defined(_CMU_CLKEN1_TIMER4_SHIFT)
386 cmuClock_TIMER4 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
387 | (_CMU_CLKEN1_TIMER4_SHIFT << CMU_EN_BIT_POS), /**< TIMER4 clock. */
388 #elif defined(_CMU_CLKEN0_TIMER4_SHIFT)
389 cmuClock_TIMER4 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
390 | (_CMU_CLKEN0_TIMER4_SHIFT << CMU_EN_BIT_POS), /**< TIMER4 clock. */
391 #endif
392 #if defined(_CMU_CLKEN2_TIMER5_SHIFT)
393 cmuClock_TIMER5 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS)
394 | (_CMU_CLKEN2_TIMER5_SHIFT << CMU_EN_BIT_POS), /**< TIMER5 clock. */
395 #elif defined(_CMU_CLKEN1_TIMER5_SHIFT)
396 cmuClock_TIMER5 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
397 | (_CMU_CLKEN1_TIMER5_SHIFT << CMU_EN_BIT_POS), /**< TIMER5 clock. */
398 #elif defined(_CMU_CLKEN0_TIMER5_SHIFT)
399 cmuClock_TIMER5 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
400 | (_CMU_CLKEN0_TIMER5_SHIFT << CMU_EN_BIT_POS), /**< TIMER5 clock. */
401 #endif
402 #if defined(_CMU_CLKEN2_TIMER6_SHIFT)
403 cmuClock_TIMER6 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS)
404 | (_CMU_CLKEN2_TIMER6_SHIFT << CMU_EN_BIT_POS), /**< TIMER6 clock. */
405 #elif defined(_CMU_CLKEN1_TIMER6_SHIFT)
406 cmuClock_TIMER6 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
407 | (_CMU_CLKEN1_TIMER6_SHIFT << CMU_EN_BIT_POS), /**< TIMER6 clock. */
408 #elif defined(_CMU_CLKEN0_TIMER6_SHIFT)
409 cmuClock_TIMER6 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
410 | (_CMU_CLKEN0_TIMER6_SHIFT << CMU_EN_BIT_POS), /**< TIMER6 clock. */
411 #endif
412 #if defined(_CMU_CLKEN2_TIMER7_SHIFT)
413 cmuClock_TIMER7 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS)
414 | (_CMU_CLKEN2_TIMER7_SHIFT << CMU_EN_BIT_POS), /**< TIMER7 clock. */
415 #elif defined(_CMU_CLKEN1_TIMER7_SHIFT)
416 cmuClock_TIMER7 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
417 | (_CMU_CLKEN1_TIMER7_SHIFT << CMU_EN_BIT_POS), /**< TIMER7 clock. */
418 #elif defined(_CMU_CLKEN0_TIMER7_SHIFT)
419 cmuClock_TIMER7 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
420 | (_CMU_CLKEN0_TIMER7_SHIFT << CMU_EN_BIT_POS), /**< TIMER7 clock. */
421 #endif
422 #if defined(_CMU_CLKEN2_TIMER8_SHIFT)
423 cmuClock_TIMER8 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS)
424 | (_CMU_CLKEN2_TIMER8_SHIFT << CMU_EN_BIT_POS), /**< TIMER8 clock. */
425 #endif
426 #if defined(_CMU_CLKEN2_TIMER9_SHIFT)
427 cmuClock_TIMER9 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS)
428 | (_CMU_CLKEN2_TIMER9_SHIFT << CMU_EN_BIT_POS), /**< TIMER9 clock. */
429 #endif
430 #if defined(USART_PRESENT) && USART_COUNT > 0
431 cmuClock_USART0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
432 | (_CMU_CLKEN0_USART0_SHIFT << CMU_EN_BIT_POS), /**< USART0 clock. */
433 #endif
434 #if defined(USART_PRESENT) && USART_COUNT > 1
435 #if defined(_CMU_CLKEN0_USART1_SHIFT)
436 cmuClock_USART1 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
437 | (_CMU_CLKEN0_USART1_SHIFT << CMU_EN_BIT_POS), /**< USART1 clock. */
438 #elif defined(_CMU_CLKEN2_USART1_SHIFT)
439 cmuClock_USART1 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS)
440 | (_CMU_CLKEN2_USART1_SHIFT << CMU_EN_BIT_POS), /**< USART1 clock. */
441 #endif
442 #endif /* defined(USART_PRESENT) && USART_COUNT > 1 */
443 #if defined(USART_PRESENT) && USART_COUNT > 2
444 cmuClock_USART2 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS)
445 | (_CMU_CLKEN2_USART2_SHIFT << CMU_EN_BIT_POS), /**< USART2 clock. */
446 #endif /* defined(USART_PRESENT) && USART_COUNT > 2 */
447 #if defined(IADC_PRESENT)
448 cmuClock_IADC0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
449 | (_CMU_CLKEN0_IADC0_SHIFT << CMU_EN_BIT_POS), /**< IADC0 clock. */
450 #endif
451 cmuClock_AMUXCP0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
452 | (_CMU_CLKEN0_AMUXCP0_SHIFT << CMU_EN_BIT_POS), /**< AMUXCP0 clock. */
453 #if defined(LETIMER_PRESENT)
454 cmuClock_LETIMER0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
455 | (_CMU_CLKEN0_LETIMER0_SHIFT << CMU_EN_BIT_POS), /**< LETIMER0 clock. */
456 #endif
457 cmuClock_WDOG0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
458 | (_CMU_CLKEN0_WDOG0_SHIFT << CMU_EN_BIT_POS), /**< WDOG0 clock. */
459 #if WDOG_COUNT > 1
460 cmuClock_WDOG1 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
461 | (_CMU_CLKEN1_WDOG1_SHIFT << CMU_EN_BIT_POS), /**< WDOG1 clock. */
462 #endif
463 #if defined(I2C_PRESENT)
464 cmuClock_I2C0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
465 | (_CMU_CLKEN0_I2C0_SHIFT << CMU_EN_BIT_POS), /**< I2C0 clock. */
466 #if I2C_COUNT > 1
467 cmuClock_I2C1 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
468 | (_CMU_CLKEN0_I2C1_SHIFT << CMU_EN_BIT_POS), /**< I2C1 clock. */
469 #endif /* I2C_COUNT > 1 */
470 #if I2C_COUNT > 2
471 cmuClock_I2C2 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS)
472 | (_CMU_CLKEN2_I2C2_SHIFT << CMU_EN_BIT_POS), /**< I2C2 clock. */
473 #endif /* I2C_COUNT > 2 */
474 #if I2C_COUNT > 3
475 cmuClock_I2C3 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS)
476 | (_CMU_CLKEN2_I2C3_SHIFT << CMU_EN_BIT_POS), /**< I2C3 clock. */
477 #endif /* I2C_COUNT > 3 */
478 #endif /* defined(I2C_PRESENT) */
479 cmuClock_SYSCFG = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
480 | (_CMU_CLKEN0_SYSCFG_SHIFT << CMU_EN_BIT_POS), /**< SYSCFG clock. */
481 cmuClock_DPLL0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
482 | (_CMU_CLKEN0_DPLL0_SHIFT << CMU_EN_BIT_POS), /**< DPLL0 clock. */
483 cmuClock_HFRCO0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
484 | (_CMU_CLKEN0_HFRCO0_SHIFT << CMU_EN_BIT_POS), /**< HFRCO0 clock. */
485 #if defined(HFRCOEM23_PRESENT)
486 cmuClock_HFRCOEM23 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
487 | (_CMU_CLKEN0_HFRCOEM23_SHIFT << CMU_EN_BIT_POS), /**< HFRCOEM23 clock. */
488 #endif
489 #if defined(HFXO_PRESENT)
490 cmuClock_HFXO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
491 | (_CMU_CLKEN0_HFXO0_SHIFT << CMU_EN_BIT_POS), /**< HFXO clock. */
492 #endif
493 cmuClock_FSRCO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
494 | (_CMU_CLKEN0_FSRCO_SHIFT << CMU_EN_BIT_POS), /**< FSRCO clock. */
495 cmuClock_LFRCO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
496 | (_CMU_CLKEN0_LFRCO_SHIFT << CMU_EN_BIT_POS), /**< LFRCO clock. */
497 cmuClock_LFXO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
498 | (_CMU_CLKEN0_LFXO_SHIFT << CMU_EN_BIT_POS), /**< LFXO clock. */
499 cmuClock_ULFRCO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
500 | (_CMU_CLKEN0_ULFRCO_SHIFT << CMU_EN_BIT_POS), /**< ULFRCO clock. */
501 #if defined(EUART_PRESENT)
502 cmuClock_EUART0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
503 | (_CMU_CLKEN0_EUART0_SHIFT << CMU_EN_BIT_POS), /**< EUART0 clock. */
504 #endif
505 #if defined(PDM_PRESENT)
506 cmuClock_PDM = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
507 | (_CMU_CLKEN0_PDM_SHIFT << CMU_EN_BIT_POS), /**< PDM clock. */
508 #endif
509 cmuClock_GPIO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
510 | (_CMU_CLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS), /**< GPIO clock. */
511 cmuClock_PRS = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
512 | (_CMU_CLKEN0_PRS_SHIFT << CMU_EN_BIT_POS), /**< PRS clock. */
513 cmuClock_BURAM = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
514 | (_CMU_CLKEN0_BURAM_SHIFT << CMU_EN_BIT_POS), /**< BURAM clock. */
515 cmuClock_BURTC = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
516 | (_CMU_CLKEN0_BURTC_SHIFT << CMU_EN_BIT_POS), /**< BURTC clock. */
517 #if defined(RTCC_PRESENT)
518 cmuClock_RTCC = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
519 | (_CMU_CLKEN0_RTCC_SHIFT << CMU_EN_BIT_POS), /**< RTCC clock. */
520 #endif
521 cmuClock_DCDC = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
522 | (_CMU_CLKEN0_DCDC_SHIFT << CMU_EN_BIT_POS), /**< DCDC clock. */
523 #if defined(SYSRTC_PRESENT)
524 cmuClock_SYSRTC = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
525 | (_CMU_CLKEN0_SYSRTC0_SHIFT << CMU_EN_BIT_POS), /**< SYSRTC clock. */
526 #endif
527 #if defined(EUSART_PRESENT) && EUSART_COUNT > 0
528 cmuClock_EUSART0 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
529 | (_CMU_CLKEN1_EUSART0_SHIFT << CMU_EN_BIT_POS), /**< EUSART0 clock. */
530 #endif
531 #if defined(EUSART_PRESENT) && EUSART_COUNT > 1
532 cmuClock_EUSART1 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
533 | (_CMU_CLKEN1_EUSART1_SHIFT << CMU_EN_BIT_POS), /**< EUSART1 clock. */
534 #endif
535 #if defined(EUSART_PRESENT) && EUSART_COUNT > 2
536 #if defined(_CMU_CLKEN1_EUSART2_SHIFT)
537 cmuClock_EUSART2 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
538 | (_CMU_CLKEN1_EUSART2_SHIFT << CMU_EN_BIT_POS), /**< EUSART2 clock. */
539 #elif defined(_CMU_CLKEN2_EUSART2_SHIFT)
540 cmuClock_EUSART2 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS)
541 | (_CMU_CLKEN2_EUSART2_SHIFT << CMU_EN_BIT_POS), /**< EUSART2 clock. */
542 #endif
543 #endif /* defined(EUSART_PRESENT) && EUSART_COUNT > 2 */
544 #if defined(EUSART_PRESENT) && EUSART_COUNT > 3
545 #if defined(_CMU_CLKEN1_EUSART3_SHIFT)
546 cmuClock_EUSART3 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
547 | (_CMU_CLKEN1_EUSART3_SHIFT << CMU_EN_BIT_POS), /**< EUSART3 clock. */
548 #elif defined(_CMU_CLKEN2_EUSART3_SHIFT)
549 cmuClock_EUSART3 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS)
550 | (_CMU_CLKEN2_EUSART3_SHIFT << CMU_EN_BIT_POS), /**< EUSART3 clock. */
551 #endif
552 #endif /* defined(EUSART_PRESENT) && EUSART_COUNT > 3 */
553 #if defined(EUSART_PRESENT) && EUSART_COUNT > 4
554 #if defined(_CMU_CLKEN1_EUSART4_SHIFT)
555 cmuClock_EUSART4 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
556 | (_CMU_CLKEN1_EUSART4_SHIFT << CMU_EN_BIT_POS), /**< EUSART4 clock. */
557 #elif defined(_CMU_CLKEN2_EUSART4_SHIFT)
558 cmuClock_EUSART4 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS)
559 | (_CMU_CLKEN2_EUSART4_SHIFT << CMU_EN_BIT_POS), /**< EUSART4 clock. */
560 #endif
561 #endif /* defined(EUSART_PRESENT) && EUSART_COUNT > 4 */
562 #if defined(_CMU_CLKEN1_IFADCDEBUG_SHIFT)
563 cmuClock_IFADCDEBUG = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
564 | (_CMU_CLKEN1_IFADCDEBUG_SHIFT << CMU_EN_BIT_POS), /**< IFADCDEBUG clock. */
565 #endif
566 #if defined(CRYPTOACC_PRESENT)
567 cmuClock_CRYPTOACC = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
568 | (_CMU_CLKEN1_CRYPTOACC_SHIFT << CMU_EN_BIT_POS), /**< CRYPTOACC clock. */
569 #endif
570 #if defined(SEMAILBOX_PRESENT)
571 cmuClock_SEMAILBOX = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
572 | (_CMU_CLKEN1_SEMAILBOXHOST_SHIFT << CMU_EN_BIT_POS), /**< SEMAILBOX clock. */
573 #endif
574 cmuClock_SMU = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
575 | (_CMU_CLKEN1_SMU_SHIFT << CMU_EN_BIT_POS), /**< SMU clock. */
576 #if defined(ICACHE_PRESENT)
577 cmuClock_ICACHE = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
578 | (_CMU_CLKEN1_ICACHE0_SHIFT << CMU_EN_BIT_POS), /**< ICACHE clock. */
579 #endif
580 #if defined(LESENSE_PRESENT)
581 cmuClock_LESENSE = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
582 | (_CMU_CLKEN0_LESENSE_SHIFT << CMU_EN_BIT_POS), /**< LESENSE clock. */
583 #endif
584 #if defined(ACMP_PRESENT)
585 cmuClock_ACMP0 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
586 | (_CMU_CLKEN1_ACMP0_SHIFT << CMU_EN_BIT_POS), /**< ACMP0 clock. */
587 #if ACMP_COUNT > 1
588 cmuClock_ACMP1 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
589 | (_CMU_CLKEN1_ACMP1_SHIFT << CMU_EN_BIT_POS), /**< ACMP1 clock. */
590 #endif
591 #endif
592 #if defined(VDAC_PRESENT)
593 cmuClock_VDAC0 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
594 | (_CMU_CLKEN1_VDAC0_SHIFT << CMU_EN_BIT_POS), /**< VDAC0 clock. */
595 #if (VDAC_COUNT > 1)
596 cmuClock_VDAC1 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
597 | (_CMU_CLKEN1_VDAC1_SHIFT << CMU_EN_BIT_POS), /**< VDAC1 clock. */
598 #endif
599 #endif
600 #if defined(PCNT_PRESENT)
601 cmuClock_PCNT0 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
602 | (_CMU_CLKEN1_PCNT0_SHIFT << CMU_EN_BIT_POS), /**< PCNT0 clock. */
603 #endif
604 #if defined(DMEM_PRESENT)
605 cmuClock_DMEM = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
606 | (_CMU_CLKEN1_DMEM_SHIFT << CMU_EN_BIT_POS), /**< DMEM clock. */
607 #endif
608 #if defined(KEYSCAN_PRESENT)
609 cmuClock_KEYSCAN = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
610 | (_CMU_CLKEN1_KEYSCAN_SHIFT << CMU_EN_BIT_POS), /**< KEYSCAN clock. */
611 #endif
612 #if defined(LCD_PRESENT)
613 cmuClock_LCD = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
614 | (_CMU_CLKEN1_LCD_SHIFT << CMU_EN_BIT_POS), /**< LCD clock. */
615 #endif
616 #if defined(MVP_PRESENT)
617 cmuClock_MVP = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
618 | (_CMU_CLKEN1_MVP_SHIFT << CMU_EN_BIT_POS), /**< MVP clock. */
619 #endif
620 cmuClock_MSC = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
621 | (_CMU_CLKEN1_MSC_SHIFT << CMU_EN_BIT_POS), /**< MSC clock. */
622 #if defined(USB_PRESENT)
623 cmuClock_USB = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
624 | (_CMU_CLKEN1_USB_SHIFT << CMU_EN_BIT_POS), /**< USB clock. */
625 #endif
626 #if defined(ETAMPDET_PRESENT)
627 cmuClock_ETAMPDET = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
628 | (_CMU_CLKEN1_ETAMPDET_SHIFT << CMU_EN_BIT_POS), /**< ETAMPDET clock. */
629 #endif
630 #if defined(RFFPLL_PRESENT)
631 cmuClock_RFFPLL = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
632 | (_CMU_CLKEN1_RFFPLL0_SHIFT << CMU_EN_BIT_POS) /**< RFFPLL clock. */
633 #endif
634 };
635 #endif // (_SILICON_LABS_32B_SERIES_2_CONFIG > 1)
636
637 /** Oscillator types. */
SL_ENUM(CMU_Osc_TypeDef)638 SL_ENUM(CMU_Osc_TypeDef) {
639 cmuOsc_LFXO, /**< Low frequency crystal oscillator. */
640 cmuOsc_LFRCO, /**< Low frequency RC oscillator. */
641 cmuOsc_FSRCO, /**< Fast startup fixed frequency RC oscillator. */
642 cmuOsc_HFXO, /**< High frequency crystal oscillator. */
643 cmuOsc_HFRCODPLL, /**< High frequency RC and DPLL oscillator. */
644 #if defined(HFRCOEM23_PRESENT)
645 cmuOsc_HFRCOEM23, /**< High frequency deep sleep RC oscillator. */
646 #endif
647 cmuOsc_ULFRCO, /**< Ultra low frequency RC oscillator. */
648 };
649
650 #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1)
651 /** Selectable clock sources. */
SL_ENUM_GENERIC(CMU_Select_TypeDef,uint32_t)652 SL_ENUM_GENERIC(CMU_Select_TypeDef, uint32_t) {
653 cmuSelect_Error, /**< Usage error. */
654 cmuSelect_Disabled, /**< Clock selector disabled. */
655 cmuSelect_FSRCO, /**< Fast startup fixed frequency RC oscillator. */
656 cmuSelect_HFXO, /**< High frequency crystal oscillator. */
657 cmuSelect_HFRCODPLL, /**< High frequency RC and DPLL oscillator. */
658 cmuSelect_HFRCOEM23, /**< High frequency deep sleep RC oscillator. */
659 cmuSelect_CLKIN0, /**< External clock input. */
660 cmuSelect_LFXO, /**< Low frequency crystal oscillator. */
661 cmuSelect_LFRCO, /**< Low frequency RC oscillator. */
662 cmuSelect_ULFRCO, /**< Ultra low frequency RC oscillator. */
663 cmuSelect_PCLK, /**< Peripheral APB bus interface clock. */
664 cmuSelect_HCLK, /**< Core and AHB bus interface clock. */
665 cmuSelect_HCLKDIV1024, /**< Prescaled HCLK frequency clock. */
666 cmuSelect_EM01GRPACLK, /**< EM01GRPA clock. */
667 cmuSelect_EM23GRPACLK, /**< EM23GRPA clock. */
668 cmuSelect_EXPCLK, /**< Pin export clock. */
669 cmuSelect_PRS /**< PRS input as clock. */
670 };
671 #endif // defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1)
672
673 #if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1)
674 /** Selectable clock sources. */
SL_ENUM_GENERIC(CMU_Select_TypeDef,uint32_t)675 SL_ENUM_GENERIC(CMU_Select_TypeDef, uint32_t) {
676 cmuSelect_Error, /**< Usage error. */
677 cmuSelect_Disabled, /**< Clock selector disabled. */
678 cmuSelect_FSRCO, /**< Fast startup fixed frequency RC oscillator. */
679 cmuSelect_HFXO, /**< High frequency crystal oscillator. */
680 cmuSelect_HFXORT, /**< Re-timed high frequency crystal oscillator. */
681 cmuSelect_HFRCODPLL, /**< High frequency RC and DPLL oscillator. */
682 cmuSelect_HFRCODPLLRT, /**< Re-timed high frequency RC and DPLL oscillator. */
683 #if defined(HFRCOEM23_PRESENT)
684 cmuSelect_HFRCOEM23, /**< High frequency deep sleep RC oscillator. */
685 #endif
686 cmuSelect_CLKIN0, /**< External clock input. */
687 cmuSelect_LFXO, /**< Low frequency crystal oscillator. */
688 cmuSelect_LFRCO, /**< Low frequency RC oscillator. */
689 #if defined(PLFRCO_PRESENT)
690 cmuSelect_PLFRCO, /**< Precision Low frequency RC oscillator. */
691 #endif
692 cmuSelect_ULFRCO, /**< Ultra low frequency RC oscillator. */
693 cmuSelect_HCLK, /**< Core and AHB bus interface clock. */
694 cmuSelect_SYSCLK, /**< System clock. */
695 cmuSelect_HCLKDIV1024, /**< Prescaled HCLK frequency clock. */
696 cmuSelect_EM01GRPACLK, /**< EM01GRPA clock. */
697 cmuSelect_EM23GRPACLK, /**< EM23GRPA clock. */
698 #if defined(_CMU_EM01GRPCCLKCTRL_MASK)
699 cmuSelect_EM01GRPCCLK, /**< EM01GRPC clock. */
700 #endif
701 cmuSelect_EXPCLK, /**< Pin export clock. */
702 cmuSelect_PRS, /**< PRS input as clock. */
703 #if defined(PCNT_PRESENT)
704 cmuSelect_PCNTEXTCLK, /**< Pulse counter external source or PRS as clock. */
705 #endif
706 cmuSelect_TEMPOSC, /**< Temperature oscillator. */
707 cmuSelect_PFMOSC, /**< PFM oscillator. */
708 cmuSelect_BIASOSC, /**< BIAS oscillator. */
709 #if defined(USBPLL_PRESENT)
710 cmuSelect_USBPLL0, /**< PLL clock for USB. */
711 #endif
712 #if defined(RFFPLL_PRESENT)
713 cmuSelect_RFFPLLSYS /**< Radio frequency friendly PLL system clock source. */
714 #endif
715 };
716 #endif // (_SILICON_LABS_32B_SERIES_2_CONFIG > 1)
717
718 /** DPLL reference clock edge detect selector. */
SL_ENUM(CMU_DPLLEdgeSel_TypeDef)719 SL_ENUM(CMU_DPLLEdgeSel_TypeDef) {
720 cmuDPLLEdgeSel_Fall = 0, /**< Detect falling edge of reference clock. */
721 cmuDPLLEdgeSel_Rise = 1 /**< Detect rising edge of reference clock. */
722 };
723
724 /** DPLL lock mode selector. */
SL_ENUM_GENERIC(CMU_DPLLLockMode_TypeDef,uint32_t)725 SL_ENUM_GENERIC(CMU_DPLLLockMode_TypeDef, uint32_t) {
726 cmuDPLLLockMode_Freq = _DPLL_CFG_MODE_FLL, /**< Frequency lock mode. */
727 cmuDPLLLockMode_Phase = _DPLL_CFG_MODE_PLL /**< Phase lock mode. */
728 };
729
730 /** LFXO oscillator modes. */
SL_ENUM_GENERIC(CMU_LfxoOscMode_TypeDef,uint32_t)731 SL_ENUM_GENERIC(CMU_LfxoOscMode_TypeDef, uint32_t) {
732 cmuLfxoOscMode_Crystal = _LFXO_CFG_MODE_XTAL, /**< Crystal oscillator. */
733 cmuLfxoOscMode_AcCoupledSine = _LFXO_CFG_MODE_BUFEXTCLK, /**< External AC coupled sine. */
734 cmuLfxoOscMode_External = _LFXO_CFG_MODE_DIGEXTCLK, /**< External digital clock. */
735 };
736
737 /** LFXO start-up timeout delay. */
SL_ENUM_GENERIC(CMU_LfxoStartupDelay_TypeDef,uint32_t)738 SL_ENUM_GENERIC(CMU_LfxoStartupDelay_TypeDef, uint32_t) {
739 cmuLfxoStartupDelay_2Cycles = _LFXO_CFG_TIMEOUT_CYCLES2, /**< 2 cycles start-up delay. */
740 cmuLfxoStartupDelay_256Cycles = _LFXO_CFG_TIMEOUT_CYCLES256, /**< 256 cycles start-up delay. */
741 cmuLfxoStartupDelay_1KCycles = _LFXO_CFG_TIMEOUT_CYCLES1K, /**< 1K cycles start-up delay. */
742 cmuLfxoStartupDelay_2KCycles = _LFXO_CFG_TIMEOUT_CYCLES2K, /**< 2K cycles start-up delay. */
743 cmuLfxoStartupDelay_4KCycles = _LFXO_CFG_TIMEOUT_CYCLES4K, /**< 4K cycles start-up delay. */
744 cmuLfxoStartupDelay_8KCycles = _LFXO_CFG_TIMEOUT_CYCLES8K, /**< 8K cycles start-up delay. */
745 cmuLfxoStartupDelay_16KCycles = _LFXO_CFG_TIMEOUT_CYCLES16K, /**< 16K cycles start-up delay. */
746 cmuLfxoStartupDelay_32KCycles = _LFXO_CFG_TIMEOUT_CYCLES32K, /**< 32K cycles start-up delay. */
747 };
748
749 /** HFXO oscillator modes. */
SL_ENUM_GENERIC(CMU_HfxoOscMode_TypeDef,uint32_t)750 SL_ENUM_GENERIC(CMU_HfxoOscMode_TypeDef, uint32_t) {
751 cmuHfxoOscMode_Crystal = _HFXO_CFG_MODE_XTAL, /**< Crystal oscillator. */
752 cmuHfxoOscMode_ExternalSine = _HFXO_CFG_MODE_EXTCLK, /**< External digital clock. */
753 #if defined(_HFXO_CFG_MODE_EXTCLKPKDET)
754 cmuHfxoOscMode_ExternalSinePkDet = _HFXO_CFG_MODE_EXTCLKPKDET, /**< External digital clock with peak detector used. */
755 #endif
756 };
757
758 /** HFXO core bias LSB change timeout. */
SL_ENUM_GENERIC(CMU_HfxoCbLsbTimeout_TypeDef,uint32_t)759 SL_ENUM_GENERIC(CMU_HfxoCbLsbTimeout_TypeDef, uint32_t) {
760 cmuHfxoCbLsbTimeout_8us = _HFXO_XTALCFG_TIMEOUTCBLSB_T8US, /**< 8 us timeout. */
761 cmuHfxoCbLsbTimeout_20us = _HFXO_XTALCFG_TIMEOUTCBLSB_T20US, /**< 20 us timeout. */
762 cmuHfxoCbLsbTimeout_41us = _HFXO_XTALCFG_TIMEOUTCBLSB_T41US, /**< 41 us timeout. */
763 cmuHfxoCbLsbTimeout_62us = _HFXO_XTALCFG_TIMEOUTCBLSB_T62US, /**< 62 us timeout. */
764 cmuHfxoCbLsbTimeout_83us = _HFXO_XTALCFG_TIMEOUTCBLSB_T83US, /**< 83 us timeout. */
765 cmuHfxoCbLsbTimeout_104us = _HFXO_XTALCFG_TIMEOUTCBLSB_T104US, /**< 104 us timeout. */
766 cmuHfxoCbLsbTimeout_125us = _HFXO_XTALCFG_TIMEOUTCBLSB_T125US, /**< 125 us timeout. */
767 cmuHfxoCbLsbTimeout_166us = _HFXO_XTALCFG_TIMEOUTCBLSB_T166US, /**< 166 us timeout. */
768 cmuHfxoCbLsbTimeout_208us = _HFXO_XTALCFG_TIMEOUTCBLSB_T208US, /**< 208 us timeout. */
769 cmuHfxoCbLsbTimeout_250us = _HFXO_XTALCFG_TIMEOUTCBLSB_T250US, /**< 250 us timeout. */
770 cmuHfxoCbLsbTimeout_333us = _HFXO_XTALCFG_TIMEOUTCBLSB_T333US, /**< 333 us timeout. */
771 cmuHfxoCbLsbTimeout_416us = _HFXO_XTALCFG_TIMEOUTCBLSB_T416US, /**< 416 us timeout. */
772 cmuHfxoCbLsbTimeout_833us = _HFXO_XTALCFG_TIMEOUTCBLSB_T833US, /**< 833 us timeout. */
773 cmuHfxoCbLsbTimeout_1250us = _HFXO_XTALCFG_TIMEOUTCBLSB_T1250US, /**< 1250 us timeout. */
774 cmuHfxoCbLsbTimeout_2083us = _HFXO_XTALCFG_TIMEOUTCBLSB_T2083US, /**< 2083 us timeout. */
775 cmuHfxoCbLsbTimeout_3750us = _HFXO_XTALCFG_TIMEOUTCBLSB_T3750US, /**< 3750 us timeout. */
776 };
777
778 /** HFXO steady state timeout. */
SL_ENUM_GENERIC(CMU_HfxoSteadyStateTimeout_TypeDef,uint32_t)779 SL_ENUM_GENERIC(CMU_HfxoSteadyStateTimeout_TypeDef, uint32_t) {
780 cmuHfxoSteadyStateTimeout_16us = _HFXO_XTALCFG_TIMEOUTSTEADY_T16US, /**< 16 us timeout. */
781 cmuHfxoSteadyStateTimeout_41us = _HFXO_XTALCFG_TIMEOUTSTEADY_T41US, /**< 41 us timeout. */
782 cmuHfxoSteadyStateTimeout_83us = _HFXO_XTALCFG_TIMEOUTSTEADY_T83US, /**< 83 us timeout. */
783 cmuHfxoSteadyStateTimeout_125us = _HFXO_XTALCFG_TIMEOUTSTEADY_T125US, /**< 125 us timeout. */
784 cmuHfxoSteadyStateTimeout_166us = _HFXO_XTALCFG_TIMEOUTSTEADY_T166US, /**< 166 us timeout. */
785 cmuHfxoSteadyStateTimeout_208us = _HFXO_XTALCFG_TIMEOUTSTEADY_T208US, /**< 208 us timeout. */
786 cmuHfxoSteadyStateTimeout_250us = _HFXO_XTALCFG_TIMEOUTSTEADY_T250US, /**< 250 us timeout. */
787 cmuHfxoSteadyStateTimeout_333us = _HFXO_XTALCFG_TIMEOUTSTEADY_T333US, /**< 333 us timeout. */
788 cmuHfxoSteadyStateTimeout_416us = _HFXO_XTALCFG_TIMEOUTSTEADY_T416US, /**< 416 us timeout. */
789 cmuHfxoSteadyStateTimeout_500us = _HFXO_XTALCFG_TIMEOUTSTEADY_T500US, /**< 500 us timeout. */
790 cmuHfxoSteadyStateTimeout_666us = _HFXO_XTALCFG_TIMEOUTSTEADY_T666US, /**< 666 us timeout. */
791 cmuHfxoSteadyStateTimeout_833us = _HFXO_XTALCFG_TIMEOUTSTEADY_T833US, /**< 833 us timeout. */
792 cmuHfxoSteadyStateTimeout_1666us = _HFXO_XTALCFG_TIMEOUTSTEADY_T1666US, /**< 1666 us timeout. */
793 cmuHfxoSteadyStateTimeout_2500us = _HFXO_XTALCFG_TIMEOUTSTEADY_T2500US, /**< 2500 us timeout. */
794 cmuHfxoSteadyStateTimeout_4166us = _HFXO_XTALCFG_TIMEOUTSTEADY_T4166US, /**< 4166 us timeout. */
795 #if defined(_HFXO_XTALCFG_TIMEOUTSTEADY_T7500US)
796 cmuHfxoSteadyStateTimeout_7500us = _HFXO_XTALCFG_TIMEOUTSTEADY_T7500US, /**< 7500 us timeout. */
797 #endif
798 };
799
800 /** HFXO core degeneration control. */
SL_ENUM_GENERIC(CMU_HfxoCoreDegen_TypeDef,uint32_t)801 SL_ENUM_GENERIC(CMU_HfxoCoreDegen_TypeDef, uint32_t) {
802 cmuHfxoCoreDegen_None = _HFXO_XTALCTRL_COREDGENANA_NONE, /**< No core degeneration. */
803 cmuHfxoCoreDegen_33 = _HFXO_XTALCTRL_COREDGENANA_DGEN33, /**< Core degeneration control 33. */
804 cmuHfxoCoreDegen_50 = _HFXO_XTALCTRL_COREDGENANA_DGEN50, /**< Core degeneration control 50. */
805 cmuHfxoCoreDegen_100 = _HFXO_XTALCTRL_COREDGENANA_DGEN100, /**< Core degeneration control 100. */
806 };
807
808 /** HFXO XI and XO pin fixed capacitor control. */
SL_ENUM_GENERIC(CMU_HfxoCtuneFixCap_TypeDef,uint32_t)809 SL_ENUM_GENERIC(CMU_HfxoCtuneFixCap_TypeDef, uint32_t) {
810 cmuHfxoCtuneFixCap_None = _HFXO_XTALCTRL_CTUNEFIXANA_NONE, /**< No fixed capacitors. */
811 cmuHfxoCtuneFixCap_Xi = _HFXO_XTALCTRL_CTUNEFIXANA_XI, /**< Fixed capacitor on XI pin. */
812 cmuHfxoCtuneFixCap_Xo = _HFXO_XTALCTRL_CTUNEFIXANA_XO, /**< Fixed capacitor on XO pin. */
813 cmuHfxoCtuneFixCap_Both = _HFXO_XTALCTRL_CTUNEFIXANA_BOTH, /**< Fixed capacitor on both pins. */
814 };
815
816 /** Oscillator precision modes. */
SL_ENUM(CMU_Precision_TypeDef)817 SL_ENUM(CMU_Precision_TypeDef) {
818 cmuPrecisionDefault, /**< Default precision mode. */
819 cmuPrecisionHigh, /**< High precision mode. */
820 };
821
822 /*******************************************************************************
823 ******************************* STRUCTS ***********************************
824 ******************************************************************************/
825
826 /** LFXO initialization structure.
827 * Initialization values should be obtained from a configuration tool,
828 * application note or crystal data sheet. */
829 typedef struct {
830 uint8_t gain; /**< Startup gain. */
831 uint8_t capTune; /**< Internal capacitance tuning. */
832 CMU_LfxoStartupDelay_TypeDef timeout; /**< Startup delay. */
833 CMU_LfxoOscMode_TypeDef mode; /**< Oscillator mode. */
834 bool highAmplitudeEn; /**< High amplitude enable. */
835 bool agcEn; /**< AGC enable. */
836 bool failDetEM4WUEn; /**< EM4 wakeup on failure enable. */
837 bool failDetEn; /**< Oscillator failure detection enable. */
838 bool disOnDemand; /**< Disable on-demand requests. */
839 bool forceEn; /**< Force oscillator enable. */
840 bool regLock; /**< Lock register access. */
841 } CMU_LFXOInit_TypeDef;
842
843 /** Default LFXO initialization values for XTAL mode. */
844 #define CMU_LFXOINIT_DEFAULT \
845 { \
846 1, \
847 38, \
848 cmuLfxoStartupDelay_4KCycles, \
849 cmuLfxoOscMode_Crystal, \
850 false, /* highAmplitudeEn */ \
851 true, /* agcEn */ \
852 false, /* failDetEM4WUEn */ \
853 false, /* failDetEn */ \
854 false, /* DisOndemand */ \
855 false, /* ForceEn */ \
856 false /* Lock registers */ \
857 }
858
859 /** Default LFXO initialization values for external clock mode. */
860 #define CMU_LFXOINIT_EXTERNAL_CLOCK \
861 { \
862 0U, \
863 0U, \
864 cmuLfxoStartupDelay_2Cycles, \
865 cmuLfxoOscMode_External, \
866 false, /* highAmplitudeEn */ \
867 false, /* agcEn */ \
868 false, /* failDetEM4WUEn */ \
869 false, /* failDetEn */ \
870 false, /* DisOndemand */ \
871 false, /* ForceEn */ \
872 false /* Lock registers */ \
873 }
874
875 /** Default LFXO initialization values for external sine mode. */
876 #define CMU_LFXOINIT_EXTERNAL_SINE \
877 { \
878 0U, \
879 0U, \
880 cmuLfxoStartupDelay_2Cycles, \
881 cmuLfxoOscMode_AcCoupledSine, \
882 false, /* highAmplitudeEn */ \
883 false, /* agcEn */ \
884 false, /* failDetEM4WUEn */ \
885 false, /* failDetEn */ \
886 false, /* DisOndemand */ \
887 false, /* ForceEn */ \
888 false /* Lock registers */ \
889 }
890
891 /** HFXO initialization structure.
892 * Initialization values should be obtained from a configuration tool,
893 * application note or crystal data sheet. */
894 typedef struct {
895 CMU_HfxoCbLsbTimeout_TypeDef timeoutCbLsb; /**< Core bias change timeout. */
896 CMU_HfxoSteadyStateTimeout_TypeDef timeoutSteadyFirstLock; /**< Steady state timeout duration for first lock. */
897 CMU_HfxoSteadyStateTimeout_TypeDef timeoutSteady; /**< Steady state timeout duration. */
898 uint8_t ctuneXoStartup; /**< XO pin startup tuning capacitance. */
899 uint8_t ctuneXiStartup; /**< XI pin startup tuning capacitance. */
900 uint8_t coreBiasStartup; /**< Core bias startup current. */
901 uint8_t imCoreBiasStartup; /**< Core bias intermediate startup current. */
902 CMU_HfxoCoreDegen_TypeDef coreDegenAna; /**< Core degeneration control. */
903 CMU_HfxoCtuneFixCap_TypeDef ctuneFixAna; /**< Fixed tuning capacitance on XI/XO. */
904 uint8_t ctuneXoAna; /**< Tuning capacitance on XO. */
905 uint8_t ctuneXiAna; /**< Tuning capacitance on XI. */
906 uint8_t coreBiasAna; /**< Core bias current. */
907 bool enXiDcBiasAna; /**< Enable XI internal DC bias. */
908 CMU_HfxoOscMode_TypeDef mode; /**< Oscillator mode. */
909 bool forceXo2GndAna; /**< Force XO pin to ground. */
910 bool forceXi2GndAna; /**< Force XI pin to ground. */
911 bool disOnDemand; /**< Disable on-demand requests. */
912 bool forceEn; /**< Force oscillator enable. */
913 #if defined(HFXO_CTRL_EM23ONDEMAND)
914 bool em23OnDemand; /**< Enable deep sleep. */
915 #endif
916 bool regLock; /**< Lock register access. */
917 } CMU_HFXOInit_TypeDef;
918
919 #if defined(HFXO_CTRL_EM23ONDEMAND)
920
921 #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \
922 || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8)
923 // See [PM-2871] for details.
924 /** Default configuration of fixed tuning capacitance on XI or XO for EFR32XG23 and EFR32XG28. */
925 #define CMU_HFXOINIT_CTUNEFIXANA_DEFAULT cmuHfxoCtuneFixCap_Xo
926 #elif (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \
927 || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6)) \
928 && defined(_SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT) \
929 && (_SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM == 20)
930 // See [PM-5131] for details.
931 /**
932 * Default configuration of fixed tuning capacitance on XO for EFR32XG24
933 * when high power PA is present and output dBm equal 20 dBm.
934 */
935 #define CMU_HFXOINIT_CTUNEFIXANA_DEFAULT cmuHfxoCtuneFixCap_Xo
936 #elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5)
937 // See [PM-5638] for details.
938 /**
939 * Default configuration of fixed tuning capacitance on XO for EFR32XG25
940 */
941 #define CMU_HFXOINIT_CTUNEFIXANA_DEFAULT cmuHfxoCtuneFixCap_Xo
942 #else
943 /**
944 * Default configuration of fixed tuning capacitance on XO and XI.
945 */
946 #define CMU_HFXOINIT_CTUNEFIXANA_DEFAULT cmuHfxoCtuneFixCap_Both
947 #endif
948
949 /** Default HFXO initialization values for XTAL mode. */
950 #define CMU_HFXOINIT_DEFAULT \
951 { \
952 cmuHfxoCbLsbTimeout_416us, \
953 cmuHfxoSteadyStateTimeout_833us, /* First lock */ \
954 cmuHfxoSteadyStateTimeout_83us, /* Subsequent locks */ \
955 0U, /* ctuneXoStartup */ \
956 0U, /* ctuneXiStartup */ \
957 32U, /* coreBiasStartup */ \
958 32U, /* imCoreBiasStartup */ \
959 cmuHfxoCoreDegen_None, \
960 CMU_HFXOINIT_CTUNEFIXANA_DEFAULT, \
961 _HFXO_XTALCTRL_CTUNEXOANA_DEFAULT, /* ctuneXoAna */ \
962 _HFXO_XTALCTRL_CTUNEXIANA_DEFAULT, /* ctuneXiAna */ \
963 60U, /* coreBiasAna */ \
964 false, /* enXiDcBiasAna */ \
965 cmuHfxoOscMode_Crystal, \
966 false, /* forceXo2GndAna */ \
967 false, /* forceXi2GndAna */ \
968 false, /* DisOndemand */ \
969 false, /* ForceEn */ \
970 false, /* em23OnDemand */ \
971 false /* Lock registers */ \
972 }
973
974 /** Default HFXO initialization values for external sine mode. */
975 #define CMU_HFXOINIT_EXTERNAL_SINE \
976 { \
977 (CMU_HfxoCbLsbTimeout_TypeDef)0, /* timeoutCbLsb */ \
978 (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, first lock */ \
979 (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, subseq. locks */ \
980 0U, /* ctuneXoStartup */ \
981 0U, /* ctuneXiStartup */ \
982 0U, /* coreBiasStartup */ \
983 0U, /* imCoreBiasStartup */ \
984 cmuHfxoCoreDegen_None, \
985 cmuHfxoCtuneFixCap_None, \
986 0U, /* ctuneXoAna */ \
987 0U, /* ctuneXiAna */ \
988 0U, /* coreBiasAna */ \
989 false, /* enXiDcBiasAna, false=DC true=AC coupling of signal */ \
990 cmuHfxoOscMode_ExternalSine, \
991 false, /* forceXo2GndAna */ \
992 false, /* forceXi2GndAna (Never enable in sine mode) */ \
993 false, /* DisOndemand */ \
994 false, /* ForceEn */ \
995 false, /* em23OnDemand */ \
996 false /* Lock registers */ \
997 }
998
999 /** Default HFXO initialization values for external sine mode with peak detector. */
1000 #define CMU_HFXOINIT_EXTERNAL_SINEPKDET \
1001 { \
1002 (CMU_HfxoCbLsbTimeout_TypeDef)0, /* timeoutCbLsb */ \
1003 (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, first lock */ \
1004 (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, subseq. locks */ \
1005 0U, /* ctuneXoStartup */ \
1006 0U, /* ctuneXiStartup */ \
1007 0U, /* coreBiasStartup */ \
1008 0U, /* imCoreBiasStartup */ \
1009 cmuHfxoCoreDegen_None, \
1010 cmuHfxoCtuneFixCap_None, \
1011 0U, /* ctuneXoAna */ \
1012 0U, /* ctuneXiAna */ \
1013 0U, /* coreBiasAna */ \
1014 false, /* enXiDcBiasAna, false=DC true=AC coupling of signal */ \
1015 cmuHfxoOscMode_ExternalSinePkDet, \
1016 false, /* forceXo2GndAna */ \
1017 false, /* forceXi2GndAna (Never enable in sine mode) */ \
1018 false, /* DisOndemand */ \
1019 false, /* ForceEn */ \
1020 false, /* em23OnDemand */ \
1021 false /* Lock registers */ \
1022 }
1023 #else
1024 /** Default HFXO initialization values for XTAL mode. */
1025 #define CMU_HFXOINIT_DEFAULT \
1026 { \
1027 cmuHfxoCbLsbTimeout_416us, \
1028 cmuHfxoSteadyStateTimeout_833us, /* First lock */ \
1029 cmuHfxoSteadyStateTimeout_83us, /* Subsequent locks */ \
1030 0U, /* ctuneXoStartup */ \
1031 0U, /* ctuneXiStartup */ \
1032 32U, /* coreBiasStartup */ \
1033 32U, /* imCoreBiasStartup */ \
1034 cmuHfxoCoreDegen_None, \
1035 cmuHfxoCtuneFixCap_Both, \
1036 _HFXO_XTALCTRL_CTUNEXOANA_DEFAULT, /* ctuneXoAna */ \
1037 _HFXO_XTALCTRL_CTUNEXIANA_DEFAULT, /* ctuneXiAna */ \
1038 60U, /* coreBiasAna */ \
1039 false, /* enXiDcBiasAna */ \
1040 cmuHfxoOscMode_Crystal, \
1041 false, /* forceXo2GndAna */ \
1042 false, /* forceXi2GndAna */ \
1043 false, /* DisOndemand */ \
1044 false, /* ForceEn */ \
1045 false /* Lock registers */ \
1046 }
1047
1048 /** Default HFXO initialization values for external sine mode. */
1049 #define CMU_HFXOINIT_EXTERNAL_SINE \
1050 { \
1051 (CMU_HfxoCbLsbTimeout_TypeDef)0, /* timeoutCbLsb */ \
1052 (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, first lock */ \
1053 (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, subseq. locks */ \
1054 0U, /* ctuneXoStartup */ \
1055 0U, /* ctuneXiStartup */ \
1056 0U, /* coreBiasStartup */ \
1057 0U, /* imCoreBiasStartup */ \
1058 cmuHfxoCoreDegen_None, \
1059 cmuHfxoCtuneFixCap_None, \
1060 0U, /* ctuneXoAna */ \
1061 0U, /* ctuneXiAna */ \
1062 0U, /* coreBiasAna */ \
1063 false, /* enXiDcBiasAna, false=DC true=AC coupling of signal */ \
1064 cmuHfxoOscMode_ExternalSine, \
1065 false, /* forceXo2GndAna */ \
1066 false, /* forceXi2GndAna (Never enable in sine mode) */ \
1067 false, /* DisOndemand */ \
1068 false, /* ForceEn */ \
1069 false /* Lock registers */ \
1070 }
1071
1072 /** Default HFXO initialization values for external sine mode with peak detector. */
1073 #define CMU_HFXOINIT_EXTERNAL_SINEPKDET \
1074 { \
1075 (CMU_HfxoCbLsbTimeout_TypeDef)0, /* timeoutCbLsb */ \
1076 (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, first lock */ \
1077 (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, subseq. locks */ \
1078 0U, /* ctuneXoStartup */ \
1079 0U, /* ctuneXiStartup */ \
1080 0U, /* coreBiasStartup */ \
1081 0U, /* imCoreBiasStartup */ \
1082 cmuHfxoCoreDegen_None, \
1083 cmuHfxoCtuneFixCap_None, \
1084 0U, /* ctuneXoAna */ \
1085 0U, /* ctuneXiAna */ \
1086 0U, /* coreBiasAna */ \
1087 false, /* enXiDcBiasAna, false=DC true=AC coupling of signal */ \
1088 cmuHfxoOscMode_ExternalSinePkDet, \
1089 false, /* forceXo2GndAna */ \
1090 false, /* forceXi2GndAna (Never enable in sine mode) */ \
1091 false, /* DisOndemand */ \
1092 false, /* ForceEn */ \
1093 false /* Lock registers */ \
1094 }
1095 #endif
1096
1097 #if defined(_HFXO_BUFOUTCTRL_MASK)
1098
1099 /** Crystal sharing timeout start up timeout. */
SL_ENUM_GENERIC(CMU_BufoutTimeoutStartup_TypeDef,uint32_t)1100 SL_ENUM_GENERIC(CMU_BufoutTimeoutStartup_TypeDef, uint32_t) {
1101 startupTimeout42Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T42US, /**< Timeout set to 42 us. */
1102 startupTimeout83Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T83US, /**< Timeout set to 83 us. */
1103 startupTimeout108Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T108US, /**< Timeout set to 108 us. */
1104 startupTimeout133Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T133US, /**< Timeout set to 133 us. */
1105 startupTimeout158Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T158US, /**< Timeout set to 158 us. */
1106 startupTimeout183Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T183US, /**< Timeout set to 183 us. */
1107 startupTimeout208Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US, /**< Timeout set to 208 us. */
1108 startupTimeout233Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T233US, /**< Timeout set to 233 us. */
1109 startupTimeout258Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T258US, /**< Timeout set to 258 us. */
1110 startupTimeout283Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T283US, /**< Timeout set to 283 us. */
1111 startupTimeout333Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T333US, /**< Timeout set to 333 us. */
1112 startupTimeout375Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T375US, /**< Timeout set to 375 us. */
1113 startupTimeout417Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T417US, /**< Timeout set to 417 us. */
1114 startupTimeout458Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T458US, /**< Timeout set to 458 us. */
1115 startupTimeout500Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T500US, /**< Timeout set to 500 us. */
1116 startupTimeout667Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T667US, /**< Timeout set to 667 us. */
1117 };
1118
1119 /** Crystal sharing leader initialization structure. */
1120 typedef struct {
1121 bool minimalStartupDelay; /**< If enabled, bufout won't start until timeout expires. */
1122 CMU_BufoutTimeoutStartup_TypeDef timeoutStartup; /**< Wait duration of the oscillator startup sequence to prevent bufout starting too early. */
1123 } CMU_BUFOUTLeaderInit_TypeDef;
1124
1125 /** Default crystal sharing master initialization values. */
1126 #define CMU_HFXO_CRYSTAL_INIT_LEADER_DEFAULT \
1127 { \
1128 true, /* minimalStartupDelay */ \
1129 startupTimeout208Us, /* timeoutStartup */ \
1130 }
1131 #endif
1132
1133 #if defined(_HFXO_CTRL_PRSSTATUSSEL0_MASK)
1134 /** PRS status select output signal. */
SL_ENUM(CMU_PRS_Status_Output_Select_TypeDef)1135 SL_ENUM(CMU_PRS_Status_Output_Select_TypeDef) {
1136 PRS_Status_select_0, /**< PRS status 0 output signal. */
1137 PRS_Status_select_1 /**< PRS status 1 output signal. */
1138 };
1139
1140 /** Crystal sharing follower initialization structure. */
1141 typedef struct {
1142 CMU_PRS_Status_Output_Select_TypeDef prsStatusSelectOutput; /**< PRS status output select. */
1143 bool em23OnDemand; /**< Enable em23 on demand. */
1144 bool regLock; /**< Lock registers. */
1145 } CMU_CrystalSharingFollowerInit_TypeDef;
1146
1147 /** Default crystal sharing follower initialization values. */
1148 #define CMU_HFXO_CRYSTAL_INIT_Follower_DEFAULT \
1149 { \
1150 PRS_Status_select_0, /* prsStatusSelectOutput */ \
1151 true, /* em23OnDemand */ \
1152 false /* regLock */ \
1153 }
1154 #endif
1155
1156 /** DPLL initialization structure.
1157 * Frequency will be Fref*(N+1)/(M+1). */
1158 typedef struct {
1159 uint32_t frequency; /**< PLL frequency value, max 80 MHz. */
1160 uint16_t n; /**< Factor N. 300 <= N <= 4095 */
1161 uint16_t m; /**< Factor M. M <= 4095 */
1162 CMU_Select_TypeDef refClk; /**< Reference clock selector. */
1163 CMU_DPLLEdgeSel_TypeDef edgeSel; /**< Reference clock edge detect selector. */
1164 CMU_DPLLLockMode_TypeDef lockMode; /**< DPLL lock mode selector. */
1165 bool autoRecover; /**< Enable automatic lock recovery. */
1166 bool ditherEn; /**< Enable dither functionality. */
1167 } CMU_DPLLInit_TypeDef;
1168
1169 /**
1170 * DPLL initialization values for 39,998,805 Hz using LFXO as reference
1171 * clock, M=2 and N=3661.
1172 */
1173 #define CMU_DPLL_LFXO_TO_40MHZ \
1174 { \
1175 39998805, /* Target frequency. */ \
1176 3661, /* Factor N. */ \
1177 2, /* Factor M. */ \
1178 cmuSelect_LFXO, /* Select LFXO as reference clock. */ \
1179 cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \
1180 cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \
1181 true, /* Enable automatic lock recovery. */ \
1182 false /* Don't enable dither function. */ \
1183 }
1184
1185 /**
1186 * DPLL initialization values for 76,800,000 Hz using HFXO as reference
1187 * clock, M = 1919, N = 3839
1188 */
1189 #define CMU_DPLL_HFXO_TO_76_8MHZ \
1190 { \
1191 76800000, /* Target frequency. */ \
1192 3839, /* Factor N. */ \
1193 1919, /* Factor M. */ \
1194 cmuSelect_HFXO, /* Select HFXO as reference clock. */ \
1195 cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \
1196 cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \
1197 true, /* Enable automatic lock recovery. */ \
1198 false /* Don't enable dither function. */ \
1199 }
1200
1201 /**
1202 * DPLL initialization values for 80,000,000 Hz using HFXO as reference
1203 * clock, M = 1919, N = 3999.
1204 */
1205 #define CMU_DPLL_HFXO_TO_80MHZ \
1206 { \
1207 80000000, /* Target frequency. */ \
1208 (4000 - 1), /* Factor N. */ \
1209 (1920 - 1), /* Factor M. */ \
1210 cmuSelect_HFXO, /* Select HFXO as reference clock. */ \
1211 cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \
1212 cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \
1213 true, /* Enable automatic lock recovery. */ \
1214 false /* Don't enable dither function. */ \
1215 }
1216
1217 /**
1218 * Default configurations for DPLL initialization. When using this macro
1219 * you need to modify the N and M factor and the desired frequency to match
1220 * the components placed on the board.
1221 */
1222 #define CMU_DPLLINIT_DEFAULT \
1223 { \
1224 80000000, /* Target frequency. */ \
1225 (4000 - 1), /* Factor N. */ \
1226 (1920 - 1), /* Factor M. */ \
1227 cmuSelect_HFXO, /* Select HFXO as reference clock. */ \
1228 cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \
1229 cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \
1230 true, /* Enable automatic lock recovery. */ \
1231 false /* Don't enable dither function. */ \
1232 }
1233
1234 #if defined(USBPLL_PRESENT)
1235 /** USB PLL initialization structure. */
1236 typedef struct {
1237 CMU_HFXORefFreq_TypeDef hfxoRefFreq; /**< HFXO reference frequency. */
1238 bool shuntRegEn; /**< Shunt regulator enable. */
1239 bool disOnDemand; /**< Disable on-demand requests. */
1240 bool forceEn; /**< Force oscillator enable. */
1241 bool regLock; /**< Enable register lock. */
1242 } CMU_USBPLL_Init_TypeDef;
1243
1244 /**
1245 * Default configurations for USB PLL initialization if the HFXO frequency is
1246 * 38 MHz.
1247 */
1248 #define CMU_USBPLL_REFFREQ_38MHZ \
1249 { \
1250 cmuHFXORefFreq_38M0Hz, /* Reference frequency. */ \
1251 false, /* Disable shunt regulator. */ \
1252 false, /* Disable PLL always on. */ \
1253 false, /* Force enable. */ \
1254 true /* Enable register lock. */ \
1255 }
1256
1257 /**
1258 * Default configurations for USB PLL initialization if the HFXO frequency is
1259 * 38.4 MHz.
1260 */
1261 #define CMU_USBPLL_REFFREQ_38_4MHZ \
1262 { \
1263 cmuHFXORefFreq_38M4Hz, /* Reference frequency. */ \
1264 false, /* Disable shunt regulator. */ \
1265 false, /* Disable PLL always on. */ \
1266 false, /* Force enable. */ \
1267 true /* Enable register lock. */ \
1268 }
1269
1270 /**
1271 * Default configurations for USB PLL initialization if the HFXO frequency is
1272 * 39 MHz.
1273 */
1274 #define CMU_USBPLL_REFFREQ_39MHZ \
1275 { \
1276 cmuHFXORefFreq_39M0Hz, /* Reference frequency. */ \
1277 false, /* Disable shunt regulator. */ \
1278 false, /* Disable PLL always on. */ \
1279 false, /* Force enable. */ \
1280 true /* Enable register lock. */ \
1281 }
1282
1283 /**
1284 * Default configurations for USB PLL initialization if the HFXO frequency is
1285 * 40 MHz.
1286 */
1287 #define CMU_USBPLL_REFFREQ_40MHZ \
1288 { \
1289 cmuHFXORefFreq_40M0Hz, /* Reference frequency. */ \
1290 false, /* Disable shunt regulator. */ \
1291 false, /* Disable PLL always on. */ \
1292 false, /* Force enable. */ \
1293 true /* Enable register lock. */ \
1294 }
1295 #endif
1296
1297 #if defined(RFFPLL_PRESENT)
1298 /**
1299 * RFF PLL initialization structure.
1300 * When using this structure you need to modify the X, Y and N factor
1301 * and the desired host target frequency to match the components placed
1302 * on the board (namely the RFFPLL reference clock).
1303 * X, Y, N values for a 39MHz HFXO:
1304 * - Formula for host clock output: frequency = (freq HFXO * dividerN / 2) / dividerY
1305 * - Formula for radio clock output: freq = (freq HFXO * dividerN / 2) / (dividerX / 2)
1306 */
1307 typedef struct {
1308 uint32_t frequency; /**< Host target frequency. */
1309 bool disOnDemand; /**< Disable on-demand requests. */
1310 bool forceEn; /**< Force oscillator enable. */
1311 bool regLock; /**< Enable register lock. */
1312 uint8_t dividerY; /**< Divider Y for digital. */
1313 uint8_t dividerX; /**< Divider X for Radio. */
1314 uint8_t dividerN; /**< Feedback divider N. */
1315 } CMU_RFFPLL_Init_TypeDef;
1316
1317 /** Radio frequency locked loop default initialization values. */
1318 #define CMU_RFFPLL_DEFAULT \
1319 { \
1320 100000000UL, /* Host target frequency. */ \
1321 false, /* Disable on-demand requests. */ \
1322 false, /* Force enable. */ \
1323 true, /* Enable register lock. */ \
1324 _RFFPLL_RFFPLLCTRL1_DIVY_DEFAULT, /* Divider Y for digital. */ \
1325 _RFFPLL_RFFPLLCTRL1_DIVX_DEFAULT, /* Divider X for Radio. */ \
1326 _RFFPLL_RFFPLLCTRL1_DIVN_DEFAULT /* Feedback divider N. */ \
1327 }
1328
1329 /** Radio frequency locked loop initialization values for 97.5MHz. */
1330 #define CMU_RFFPLL_97_5_MHZ_REF_FREQ_39_MHZ \
1331 { \
1332 97500000UL, /* Host target frequency. */ \
1333 false, /* Disable on-demand requests. */ \
1334 false, /* Force enable. */ \
1335 true, /* Enable register lock. */ \
1336 20U, /* Divider Y for digital. */ \
1337 6U, /* Divider X for Radio. */ \
1338 100U /* Feedback divider N. */ \
1339 }
1340 #endif
1341
1342 /*******************************************************************************
1343 ***************************** PROTOTYPES **********************************
1344 ******************************************************************************/
1345 uint32_t CMU_Calibrate(uint32_t cycles,
1346 CMU_Select_TypeDef reference);
1347 void CMU_CalibrateConfig(uint32_t downCycles,
1348 CMU_Select_TypeDef downSel,
1349 CMU_Select_TypeDef upSel);
1350 uint32_t CMU_CalibrateCountGet(void);
1351 void CMU_ClkOutPinConfig(uint32_t clkno,
1352 CMU_Select_TypeDef sel,
1353 CMU_ClkDiv_TypeDef clkdiv,
1354 GPIO_Port_TypeDef port,
1355 unsigned int pin);
1356 CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock);
1357 void CMU_ClockDivSet(CMU_Clock_TypeDef clock,
1358 CMU_ClkDiv_TypeDef div);
1359 #if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1)
1360 void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable);
1361 #endif
1362 uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock);
1363 CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock);
1364 void CMU_ClockSelectSet(CMU_Clock_TypeDef clock,
1365 CMU_Select_TypeDef ref);
1366 uint16_t CMU_LF_ClockPrecisionGet(CMU_Clock_TypeDef clock);
1367 uint16_t CMU_HF_ClockPrecisionGet(CMU_Clock_TypeDef clock);
1368 CMU_HFRCODPLLFreq_TypeDef CMU_HFRCODPLLBandGet(void);
1369 void CMU_HFRCODPLLBandSet(CMU_HFRCODPLLFreq_TypeDef freq);
1370 bool CMU_DPLLLock(const CMU_DPLLInit_TypeDef *init);
1371 #if defined(USBPLL_PRESENT)
1372 void CMU_USBPLLInit(const CMU_USBPLL_Init_TypeDef *pllInit);
1373 __STATIC_INLINE void CMU_WaitUSBPLLLock(void);
1374 #endif
1375 #if defined(RFFPLL_PRESENT)
1376 void CMU_RFFPLLInit(const CMU_RFFPLL_Init_TypeDef *pllInit);
1377 __STATIC_INLINE void CMU_WaitRFFPLLLock(void);
1378 #endif
1379 void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit);
1380 #if defined(HFXO0_BUFOUT)
1381 void CMU_HFXOStartCrystalSharingLeader(const CMU_BUFOUTLeaderInit_TypeDef *bufoutInit,
1382 GPIO_Port_TypeDef port,
1383 unsigned int pin);
1384 #endif
1385 #if defined(_HFXO_CTRL_PRSSTATUSSEL0_MASK)
1386 void CMU_HFXOCrystalSharingFollowerInit(CMU_PRS_Status_Output_Select_TypeDef prsStatusSelectOutput,
1387 unsigned int prsAsyncCh,
1388 GPIO_Port_TypeDef port,
1389 unsigned int pin);
1390 #endif
1391 sl_status_t CMU_HFXOCTuneSet(uint32_t ctune);
1392 uint32_t CMU_HFXOCTuneGet(void);
1393 void CMU_HFXOCTuneDeltaSet(int32_t delta);
1394 int32_t CMU_HFXOCTuneDeltaGet(void);
1395 int32_t CMU_HFXOCTuneCurrentDeltaGet(void);
1396 void CMU_HFXOCoreBiasCurrentCalibrate(void);
1397 void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit);
1398 void CMU_LFXOPrecisionSet(uint16_t precision);
1399 uint16_t CMU_LFXOPrecisionGet(void);
1400 void CMU_HFXOPrecisionSet(uint16_t precision);
1401 uint16_t CMU_HFXOPrecisionGet(void);
1402 #if defined(PLFRCO_PRESENT)
1403 void CMU_LFRCOSetPrecision(CMU_Precision_TypeDef precision);
1404 #endif
1405 uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc);
1406 void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc,
1407 uint32_t val);
1408 void CMU_UpdateWaitStates(uint32_t freq, int vscale);
1409 void CMU_PCNTClockExternalSet(unsigned int instance, bool external);
1410
1411 #if defined(HFRCOEM23_PRESENT)
1412 CMU_HFRCOEM23Freq_TypeDef CMU_HFRCOEM23BandGet(void);
1413 void CMU_HFRCOEM23BandSet(CMU_HFRCOEM23Freq_TypeDef freq);
1414 #endif
1415
1416 #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1)
1417 /***************************************************************************//**
1418 * @brief
1419 * Enable/disable a clock.
1420 *
1421 * @note
1422 * This is a dummy function to solve backward compatibility issues.
1423 *
1424 * @param[in] clock
1425 * The clock to enable/disable.
1426 *
1427 * @param[in] enable
1428 * @li true - enable specified clock.
1429 * @li false - disable specified clock.
1430 ******************************************************************************/
CMU_ClockEnable(CMU_Clock_TypeDef clock,bool enable)1431 __STATIC_INLINE void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable)
1432 {
1433 (void)clock;
1434 (void)enable;
1435 }
1436 #endif
1437
1438 /***************************************************************************//**
1439 * @brief
1440 * Configure continuous calibration mode.
1441 * @param[in] enable
1442 * If true, enables continuous calibration, if false disables continuous
1443 * calibration.
1444 ******************************************************************************/
CMU_CalibrateCont(bool enable)1445 __STATIC_INLINE void CMU_CalibrateCont(bool enable)
1446 {
1447 BUS_RegBitWrite(&CMU->CALCTRL, _CMU_CALCTRL_CONT_SHIFT, (uint32_t)enable);
1448 }
1449
1450 /***************************************************************************//**
1451 * @brief
1452 * Start calibration.
1453 * @note
1454 * This call is usually invoked after @ref CMU_CalibrateConfig() and possibly
1455 * @ref CMU_CalibrateCont().
1456 ******************************************************************************/
CMU_CalibrateStart(void)1457 __STATIC_INLINE void CMU_CalibrateStart(void)
1458 {
1459 CMU->CALCMD = CMU_CALCMD_CALSTART;
1460 }
1461
1462 /***************************************************************************//**
1463 * @brief
1464 * Stop calibration counters.
1465 ******************************************************************************/
CMU_CalibrateStop(void)1466 __STATIC_INLINE void CMU_CalibrateStop(void)
1467 {
1468 CMU->CALCMD = CMU_CALCMD_CALSTOP;
1469 }
1470
1471 /***************************************************************************//**
1472 * @brief
1473 * Unlock the DPLL.
1474 * @note
1475 * The HFRCODPLL oscillator is not turned off.
1476 ******************************************************************************/
CMU_DPLLUnlock(void)1477 __STATIC_INLINE void CMU_DPLLUnlock(void)
1478 {
1479 DPLL0->EN_CLR = DPLL_EN_EN;
1480 #if defined(DPLL_EN_DISABLING)
1481 while ((DPLL0->EN & DPLL_EN_DISABLING) != 0U) {
1482 }
1483 #endif
1484 }
1485
1486 /***************************************************************************//**
1487 * @brief
1488 * Clear one or more pending CMU interrupt flags.
1489 *
1490 * @param[in] flags
1491 * CMU interrupt sources to clear.
1492 ******************************************************************************/
CMU_IntClear(uint32_t flags)1493 __STATIC_INLINE void CMU_IntClear(uint32_t flags)
1494 {
1495 CMU->IF_CLR = flags;
1496 }
1497
1498 /***************************************************************************//**
1499 * @brief
1500 * Disable one or more CMU interrupt sources.
1501 *
1502 * @param[in] flags
1503 * CMU interrupt sources to disable.
1504 ******************************************************************************/
CMU_IntDisable(uint32_t flags)1505 __STATIC_INLINE void CMU_IntDisable(uint32_t flags)
1506 {
1507 CMU->IEN_CLR = flags;
1508 }
1509
1510 /***************************************************************************//**
1511 * @brief
1512 * Enable one or more CMU interrupt sources.
1513 *
1514 * @note
1515 * Depending on the use, a pending interrupt may already be set prior to
1516 * enabling the interrupt. Consider using @ref CMU_IntClear() prior to
1517 * enabling if such a pending interrupt should be ignored.
1518 *
1519 * @param[in] flags
1520 * CMU interrupt sources to enable.
1521 ******************************************************************************/
CMU_IntEnable(uint32_t flags)1522 __STATIC_INLINE void CMU_IntEnable(uint32_t flags)
1523 {
1524 CMU->IEN_SET = flags;
1525 }
1526
1527 /***************************************************************************//**
1528 * @brief
1529 * Get pending CMU interrupt sources.
1530 *
1531 * @return
1532 * CMU interrupt sources pending.
1533 ******************************************************************************/
CMU_IntGet(void)1534 __STATIC_INLINE uint32_t CMU_IntGet(void)
1535 {
1536 return CMU->IF;
1537 }
1538
1539 /***************************************************************************//**
1540 * @brief
1541 * Get enabled and pending CMU interrupt flags.
1542 *
1543 * @details
1544 * Useful for handling more interrupt sources in the same interrupt handler.
1545 *
1546 * @note
1547 * The event bits are not cleared by the use of this function.
1548 *
1549 * @return
1550 * Pending and enabled CMU interrupt sources.
1551 * The return value is the bitwise AND of
1552 * - the enabled interrupt sources in CMU_IEN and
1553 * - the pending interrupt flags CMU_IF
1554 ******************************************************************************/
CMU_IntGetEnabled(void)1555 __STATIC_INLINE uint32_t CMU_IntGetEnabled(void)
1556 {
1557 uint32_t ien;
1558
1559 ien = CMU->IEN;
1560 return CMU->IF & ien;
1561 }
1562
1563 /**************************************************************************//**
1564 * @brief
1565 * Set one or more pending CMU interrupt sources.
1566 *
1567 * @param[in] flags
1568 * CMU interrupt sources to set to pending.
1569 *****************************************************************************/
CMU_IntSet(uint32_t flags)1570 __STATIC_INLINE void CMU_IntSet(uint32_t flags)
1571 {
1572 CMU->IF_SET = flags;
1573 }
1574
1575 /***************************************************************************//**
1576 * @brief
1577 * Lock CMU register access in order to protect registers contents against
1578 * unintended modification.
1579 *
1580 * @details
1581 * See the reference manual for CMU registers that will be
1582 * locked.
1583 *
1584 * @note
1585 * If locking the CMU registers, they must be unlocked prior to using any
1586 * CMU API functions modifying CMU registers protected by the lock.
1587 ******************************************************************************/
CMU_Lock(void)1588 __STATIC_INLINE void CMU_Lock(void)
1589 {
1590 CMU->LOCK = ~CMU_LOCK_LOCKKEY_UNLOCK;
1591 }
1592
1593 /***************************************************************************//**
1594 * @brief
1595 * Enable/disable oscillator.
1596 *
1597 * @note
1598 * This is a dummy function to solve backward compatibility issues.
1599 *
1600 * @param[in] osc
1601 * The oscillator to enable/disable.
1602 *
1603 * @param[in] enable
1604 * @li true - enable specified oscillator.
1605 * @li false - disable specified oscillator.
1606 *
1607 * @param[in] wait
1608 * Only used if @p enable is true.
1609 * @li true - wait for oscillator start-up time to timeout before returning.
1610 * @li false - do not wait for oscillator start-up time to timeout before
1611 * returning.
1612 ******************************************************************************/
CMU_OscillatorEnable(CMU_Osc_TypeDef osc,bool enable,bool wait)1613 __STATIC_INLINE void CMU_OscillatorEnable(CMU_Osc_TypeDef osc,
1614 bool enable,
1615 bool wait)
1616 {
1617 (void)osc;
1618 (void)enable;
1619 (void)wait;
1620 }
1621
1622 /***************************************************************************//**
1623 * @brief
1624 * Unlock CMU register access so that writing to registers is possible.
1625 ******************************************************************************/
CMU_Unlock(void)1626 __STATIC_INLINE void CMU_Unlock(void)
1627 {
1628 CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK;
1629 }
1630
1631 /***************************************************************************//**
1632 * @brief
1633 * Lock WDOG register access in order to protect registers contents against
1634 * unintended modification.
1635 *
1636 * @note
1637 * If locking the WDOG registers, they must be unlocked prior to using any
1638 * emlib API functions modifying registers protected by the lock.
1639 ******************************************************************************/
CMU_WdogLock(void)1640 __STATIC_INLINE void CMU_WdogLock(void)
1641 {
1642 CMU->WDOGLOCK = ~CMU_WDOGLOCK_LOCKKEY_UNLOCK;
1643 }
1644
1645 /***************************************************************************//**
1646 * @brief
1647 * Unlock WDOG register access so that writing to registers is possible.
1648 ******************************************************************************/
CMU_WdogUnlock(void)1649 __STATIC_INLINE void CMU_WdogUnlock(void)
1650 {
1651 CMU->WDOGLOCK = CMU_WDOGLOCK_LOCKKEY_UNLOCK;
1652 }
1653
1654 #if defined(USBPLL_PRESENT)
1655 /***************************************************************************//**
1656 * @brief
1657 * Wait for USB PLL lock and ready.
1658 ******************************************************************************/
CMU_WaitUSBPLLLock()1659 __STATIC_INLINE void CMU_WaitUSBPLLLock()
1660 {
1661 while ((USBPLL0->STATUS & (USBPLL_STATUS_PLLRDY | USBPLL_STATUS_PLLLOCK))
1662 != (USBPLL_STATUS_PLLRDY | USBPLL_STATUS_PLLLOCK)) {
1663 /* Wait for USB PLL lock and ready */
1664 }
1665 }
1666 #endif
1667
1668 #if defined(RFFPLL_PRESENT)
1669 /***************************************************************************//**
1670 * @brief
1671 * Wait for RFF PLL lock and ready.
1672 ******************************************************************************/
CMU_WaitRFFPLLLock()1673 __STATIC_INLINE void CMU_WaitRFFPLLLock()
1674 {
1675 while ((RFFPLL0->STATUS & (RFFPLL_STATUS_RFFPLLRADIORDY | RFFPLL_STATUS_RFFPLLSYSRDY))
1676 != (RFFPLL_STATUS_RFFPLLRADIORDY | RFFPLL_STATUS_RFFPLLSYSRDY)) {
1677 /* Wait for RFF PLL lock and ready. */
1678 }
1679 }
1680 #endif
1681
1682 #else // defined(_SILICON_LABS_32B_SERIES_2)
1683
1684 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
1685
1686 /* Select register IDs for internal use. */
1687 #define CMU_NOSEL_REG 0
1688 #define CMU_HFCLKSEL_REG 1
1689 #define CMU_LFACLKSEL_REG 2
1690 #define CMU_LFBCLKSEL_REG 3
1691 #define CMU_LFCCLKSEL_REG 4
1692 #define CMU_LFECLKSEL_REG 5
1693 #define CMU_DBGCLKSEL_REG 6
1694 #define CMU_USBCCLKSEL_REG 7
1695 #define CMU_ADC0ASYNCSEL_REG 8
1696 #define CMU_ADC1ASYNCSEL_REG 9
1697 #define CMU_SDIOREFSEL_REG 10
1698 #define CMU_QSPI0REFSEL_REG 11
1699 #define CMU_USBRCLKSEL_REG 12
1700 #define CMU_PDMREFSEL_REG 13
1701
1702 #define CMU_SEL_REG_POS 0U
1703 #define CMU_SEL_REG_MASK 0xfU
1704
1705 /* Divisor/prescaler register IDs for internal use. */
1706 #define CMU_NODIV_REG 0
1707 #define CMU_NOPRESC_REG 0
1708 #define CMU_HFPRESC_REG 1
1709 #define CMU_HFCLKDIV_REG 1
1710 #define CMU_HFEXPPRESC_REG 2
1711 #define CMU_HFCLKLEPRESC_REG 3
1712 #define CMU_HFPERPRESC_REG 4
1713 #define CMU_HFPERCLKDIV_REG 4
1714 #define CMU_HFPERPRESCB_REG 5
1715 #define CMU_HFPERPRESCC_REG 6
1716 #define CMU_HFCOREPRESC_REG 7
1717 #define CMU_HFCORECLKDIV_REG 7
1718 #define CMU_LFAPRESC0_REG 8
1719 #define CMU_LFBPRESC0_REG 9
1720 #define CMU_LFEPRESC0_REG 10
1721 #define CMU_ADCASYNCDIV_REG 11
1722 #define CMU_HFBUSPRESC_REG 12
1723 #define CMU_HFCORECLKLEDIV_REG 13
1724
1725 #define CMU_PRESC_REG_POS 4U
1726 #define CMU_DIV_REG_POS CMU_PRESC_REG_POS
1727 #define CMU_PRESC_REG_MASK 0xfU
1728 #define CMU_DIV_REG_MASK CMU_PRESC_REG_MASK
1729
1730 /* Enable register IDs for internal use. */
1731 #define CMU_NO_EN_REG 0
1732 #define CMU_CTRL_EN_REG 1
1733 #define CMU_HFPERCLKDIV_EN_REG 1
1734 #define CMU_HFPERCLKEN0_EN_REG 2
1735 #define CMU_HFCORECLKEN0_EN_REG 3
1736 #define CMU_PDMREF_EN_REG 4
1737 #define CMU_HFBUSCLKEN0_EN_REG 5
1738 #define CMU_LFACLKEN0_EN_REG 6
1739 #define CMU_LFBCLKEN0_EN_REG 7
1740 #define CMU_LFCCLKEN0_EN_REG 8
1741 #define CMU_LFECLKEN0_EN_REG 9
1742 #define CMU_PCNT_EN_REG 10
1743 #define CMU_SDIOREF_EN_REG 11
1744 #define CMU_QSPI0REF_EN_REG 12
1745 #define CMU_QSPI1REF_EN_REG 13
1746 #define CMU_HFPERCLKEN1_EN_REG 14
1747 #define CMU_USBRCLK_EN_REG 15
1748
1749 #define CMU_EN_REG_POS 8U
1750 #define CMU_EN_REG_MASK 0xfU
1751
1752 /* Enable register bit positions, for internal use. */
1753 #define CMU_EN_BIT_POS 12U
1754 #define CMU_EN_BIT_MASK 0x1fU
1755
1756 /* Clock branch bitfield positions, for internal use. */
1757 #define CMU_HF_CLK_BRANCH 0
1758 #define CMU_HFCORE_CLK_BRANCH 1
1759 #define CMU_HFPER_CLK_BRANCH 2
1760 #define CMU_HFPERB_CLK_BRANCH 3
1761 #define CMU_HFPERC_CLK_BRANCH 4
1762 #define CMU_HFBUS_CLK_BRANCH 5
1763 #define CMU_HFEXP_CLK_BRANCH 6
1764 #define CMU_DBG_CLK_BRANCH 7
1765 #define CMU_AUX_CLK_BRANCH 8
1766 #define CMU_RTC_CLK_BRANCH 9
1767 #define CMU_RTCC_CLK_BRANCH 10
1768 #define CMU_LETIMER0_CLK_BRANCH 11
1769 #define CMU_LETIMER1_CLK_BRANCH 12
1770 #define CMU_LEUART0_CLK_BRANCH 13
1771 #define CMU_LEUART1_CLK_BRANCH 14
1772 #define CMU_LFA_CLK_BRANCH 15
1773 #define CMU_LFB_CLK_BRANCH 16
1774 #define CMU_LFC_CLK_BRANCH 17
1775 #define CMU_LFE_CLK_BRANCH 18
1776 #define CMU_USBC_CLK_BRANCH 19
1777 #define CMU_USBLE_CLK_BRANCH 20
1778 #define CMU_LCDPRE_CLK_BRANCH 21
1779 #define CMU_LCD_CLK_BRANCH 22
1780 #define CMU_LESENSE_CLK_BRANCH 23
1781 #define CMU_CSEN_LF_CLK_BRANCH 24
1782 #define CMU_ADC0ASYNC_CLK_BRANCH 25
1783 #define CMU_ADC1ASYNC_CLK_BRANCH 26
1784 #define CMU_SDIOREF_CLK_BRANCH 27
1785 #define CMU_QSPI0REF_CLK_BRANCH 28
1786 #define CMU_USBR_CLK_BRANCH 29
1787 #define CMU_PDMREF_CLK_BRANCH 30
1788 #define CMU_HFLE_CLK_BRANCH 31
1789
1790 #define CMU_CLK_BRANCH_POS 17U
1791 #define CMU_CLK_BRANCH_MASK 0x1fU
1792
1793 #if defined(_EMU_CMD_EM01VSCALE0_MASK)
1794 /* Maximum clock frequency for VSCALE voltages. */
1795 #define CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX 20000000UL
1796 #endif
1797
1798 /* Macros for VSCALE for use with the CMU_UpdateWaitStates(freq, vscale) API.
1799 * NOTE: The values must align with the values in EMU_VScaleEM01_TypeDef for
1800 * Series1 parts (highest VSCALE voltage = lowest numerical value). */
1801 #define VSCALE_EM01_LOW_POWER 2
1802 #define VSCALE_EM01_HIGH_PERFORMANCE 0
1803
1804 #if defined(USB_PRESENT) && defined(_CMU_HFCORECLKEN0_USBC_MASK)
1805 #define USBC_CLOCK_PRESENT
1806 #endif
1807 #if defined(USB_PRESENT) && defined(_CMU_USBCTRL_MASK)
1808 #define USBR_CLOCK_PRESENT
1809 #endif
1810 #if defined(CMU_OSCENCMD_PLFRCOEN)
1811 #define PLFRCO_PRESENT
1812 #endif
1813
1814 /** @endcond */
1815
1816 /*******************************************************************************
1817 ******************************** ENUMS ************************************
1818 ******************************************************************************/
1819
1820 /** Clock divisors. These values are valid for prescalers. */
1821 #define cmuClkDiv_1 1 /**< Divide clock by 1. */
1822 #define cmuClkDiv_2 2 /**< Divide clock by 2. */
1823 #define cmuClkDiv_4 4 /**< Divide clock by 4. */
1824 #define cmuClkDiv_8 8 /**< Divide clock by 8. */
1825 #define cmuClkDiv_16 16 /**< Divide clock by 16. */
1826 #define cmuClkDiv_32 32 /**< Divide clock by 32. */
1827 #define cmuClkDiv_64 64 /**< Divide clock by 64. */
1828 #define cmuClkDiv_128 128 /**< Divide clock by 128. */
1829 #define cmuClkDiv_256 256 /**< Divide clock by 256. */
1830 #define cmuClkDiv_512 512 /**< Divide clock by 512. */
1831 #define cmuClkDiv_1024 1024 /**< Divide clock by 1024. */
1832 #define cmuClkDiv_2048 2048 /**< Divide clock by 2048. */
1833 #define cmuClkDiv_4096 4096 /**< Divide clock by 4096. */
1834 #define cmuClkDiv_8192 8192 /**< Divide clock by 8192. */
1835 #define cmuClkDiv_16384 16384 /**< Divide clock by 16384. */
1836 #define cmuClkDiv_32768 32768 /**< Divide clock by 32768. */
1837
1838 /** Clock divider configuration */
1839 typedef uint32_t CMU_ClkDiv_TypeDef;
1840
1841 #if defined(_SILICON_LABS_32B_SERIES_1)
1842 /** Clockprescaler configuration */
1843 typedef uint32_t CMU_ClkPresc_TypeDef;
1844 #endif
1845
1846 #if defined(_CMU_HFRCOCTRL_BAND_MASK)
1847 /** High-frequency system RCO bands */
1848 SL_ENUM_GENERIC(CMU_HFRCOBand_TypeDef, uint32_t) {
1849 cmuHFRCOBand_1MHz = _CMU_HFRCOCTRL_BAND_1MHZ, /**< 1 MHz HFRCO band */
1850 cmuHFRCOBand_7MHz = _CMU_HFRCOCTRL_BAND_7MHZ, /**< 7 MHz HFRCO band */
1851 cmuHFRCOBand_11MHz = _CMU_HFRCOCTRL_BAND_11MHZ, /**< 11 MHz HFRCO band */
1852 cmuHFRCOBand_14MHz = _CMU_HFRCOCTRL_BAND_14MHZ, /**< 14 MHz HFRCO band */
1853 cmuHFRCOBand_21MHz = _CMU_HFRCOCTRL_BAND_21MHZ, /**< 21 MHz HFRCO band */
1854 #if defined(CMU_HFRCOCTRL_BAND_28MHZ)
1855 cmuHFRCOBand_28MHz = _CMU_HFRCOCTRL_BAND_28MHZ, /**< 28 MHz HFRCO band */
1856 #endif
1857 };
1858 #endif /* _CMU_HFRCOCTRL_BAND_MASK */
1859
1860 #if defined(_CMU_AUXHFRCOCTRL_BAND_MASK)
1861 /** AUX high-frequency RCO bands */
1862 SL_ENUM_GENERIC(CMU_AUXHFRCOBand_TypeDef, uint32_t) {
1863 cmuAUXHFRCOBand_1MHz = _CMU_AUXHFRCOCTRL_BAND_1MHZ, /**< 1 MHz RC band */
1864 cmuAUXHFRCOBand_7MHz = _CMU_AUXHFRCOCTRL_BAND_7MHZ, /**< 7 MHz RC band */
1865 cmuAUXHFRCOBand_11MHz = _CMU_AUXHFRCOCTRL_BAND_11MHZ, /**< 11 MHz RC band */
1866 cmuAUXHFRCOBand_14MHz = _CMU_AUXHFRCOCTRL_BAND_14MHZ, /**< 14 MHz RC band */
1867 cmuAUXHFRCOBand_21MHz = _CMU_AUXHFRCOCTRL_BAND_21MHZ, /**< 21 MHz RC band */
1868 #if defined(CMU_AUXHFRCOCTRL_BAND_28MHZ)
1869 cmuAUXHFRCOBand_28MHz = _CMU_AUXHFRCOCTRL_BAND_28MHZ, /**< 28 MHz RC band */
1870 #endif
1871 };
1872 #endif
1873
1874 #if defined(_CMU_USHFRCOCONF_BAND_MASK)
1875 /** Universal serial high-frequency RC bands */
1876 SL_ENUM_GENERIC(CMU_USHFRCOBand_TypeDef, uint32_t) {
1877 /** 24 MHz RC band. */
1878 cmuUSHFRCOBand_24MHz = _CMU_USHFRCOCONF_BAND_24MHZ,
1879 /** 48 MHz RC band. */
1880 cmuUSHFRCOBand_48MHz = _CMU_USHFRCOCONF_BAND_48MHZ,
1881 };
1882 #endif
1883
1884 #if defined(_CMU_USHFRCOCTRL_FREQRANGE_MASK)
1885 /** High-USHFRCO bands */
1886 SL_ENUM_GENERIC(CMU_USHFRCOFreq_TypeDef, uint32_t) {
1887 cmuUSHFRCOFreq_16M0Hz = 16000000U, /**< 16 MHz RC band */
1888 cmuUSHFRCOFreq_32M0Hz = 32000000U, /**< 32 MHz RC band */
1889 cmuUSHFRCOFreq_48M0Hz = 48000000U, /**< 48 MHz RC band */
1890 cmuUSHFRCOFreq_50M0Hz = 50000000U, /**< 50 MHz RC band */
1891 cmuUSHFRCOFreq_UserDefined = 0,
1892 };
1893 /** USHFRCO minimum frequency */
1894 #define CMU_USHFRCO_MIN cmuUSHFRCOFreq_16M0Hz
1895 /** USHFRCO maximum frequency */
1896 #define CMU_USHFRCO_MAX cmuUSHFRCOFreq_50M0Hz
1897 #endif
1898
1899 #if defined(_CMU_HFRCOCTRL_FREQRANGE_MASK)
1900 /** High-frequency system RCO bands */
1901 SL_ENUM_GENERIC(CMU_HFRCOFreq_TypeDef, uint32_t) {
1902 cmuHFRCOFreq_1M0Hz = 1000000U, /**< 1 MHz RC band */
1903 cmuHFRCOFreq_2M0Hz = 2000000U, /**< 2 MHz RC band */
1904 cmuHFRCOFreq_4M0Hz = 4000000U, /**< 4 MHz RC band */
1905 cmuHFRCOFreq_7M0Hz = 7000000U, /**< 7 MHz RC band */
1906 cmuHFRCOFreq_13M0Hz = 13000000U, /**< 13 MHz RC band */
1907 cmuHFRCOFreq_16M0Hz = 16000000U, /**< 16 MHz RC band */
1908 cmuHFRCOFreq_19M0Hz = 19000000U, /**< 19 MHz RC band */
1909 cmuHFRCOFreq_26M0Hz = 26000000U, /**< 26 MHz RC band */
1910 cmuHFRCOFreq_32M0Hz = 32000000U, /**< 32 MHz RC band */
1911 cmuHFRCOFreq_38M0Hz = 38000000U, /**< 38 MHz RC band */
1912 #if defined(_DEVINFO_HFRCOCAL13_MASK)
1913 cmuHFRCOFreq_48M0Hz = 48000000U, /**< 48 MHz RC band */
1914 #endif
1915 #if defined(_DEVINFO_HFRCOCAL14_MASK)
1916 cmuHFRCOFreq_56M0Hz = 56000000U, /**< 56 MHz RC band */
1917 #endif
1918 #if defined(_DEVINFO_HFRCOCAL15_MASK)
1919 cmuHFRCOFreq_64M0Hz = 64000000U, /**< 64 MHz RC band */
1920 #endif
1921 #if defined(_DEVINFO_HFRCOCAL16_MASK)
1922 cmuHFRCOFreq_72M0Hz = 72000000U, /**< 72 MHz RC band */
1923 #endif
1924 cmuHFRCOFreq_UserDefined = 0,
1925 };
1926
1927 /** HFRCO minimum frequency. */
1928 #define CMU_HFRCO_MIN cmuHFRCOFreq_1M0Hz
1929 #if defined(_DEVINFO_HFRCOCAL16_MASK)
1930 /** HFRCO maximum frequency. */
1931 #define CMU_HFRCO_MAX cmuHFRCOFreq_72M0Hz
1932 #elif defined(_DEVINFO_HFRCOCAL15_MASK)
1933 /** HFRCO maximum frequency. */
1934 #define CMU_HFRCO_MAX cmuHFRCOFreq_64M0Hz
1935 #elif defined(_DEVINFO_HFRCOCAL14_MASK)
1936 /** HFRCO maximum frequency. */
1937 #define CMU_HFRCO_MAX cmuHFRCOFreq_56M0Hz
1938 #elif defined(_DEVINFO_HFRCOCAL13_MASK)
1939 /** HFRCO maximum frequency. */
1940 #define CMU_HFRCO_MAX cmuHFRCOFreq_48M0Hz
1941 #else
1942 /** HFRCO maximum frequency. */
1943 #define CMU_HFRCO_MAX cmuHFRCOFreq_38M0Hz
1944 #endif
1945 #endif
1946
1947 #if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK)
1948 /** AUX high-frequency RCO bands */
1949 SL_ENUM_GENERIC(CMU_AUXHFRCOFreq_TypeDef, uint32_t) {
1950 cmuAUXHFRCOFreq_1M0Hz = 1000000U, /**< 1 MHz RC band */
1951 cmuAUXHFRCOFreq_2M0Hz = 2000000U, /**< 2 MHz RC band */
1952 cmuAUXHFRCOFreq_4M0Hz = 4000000U, /**< 4 MHz RC band */
1953 cmuAUXHFRCOFreq_7M0Hz = 7000000U, /**< 7 MHz RC band */
1954 cmuAUXHFRCOFreq_13M0Hz = 13000000U, /**< 13 MHz RC band */
1955 cmuAUXHFRCOFreq_16M0Hz = 16000000U, /**< 16 MHz RC band */
1956 cmuAUXHFRCOFreq_19M0Hz = 19000000U, /**< 19 MHz RC band */
1957 cmuAUXHFRCOFreq_26M0Hz = 26000000U, /**< 26 MHz RC band */
1958 cmuAUXHFRCOFreq_32M0Hz = 32000000U, /**< 32 MHz RC band */
1959 cmuAUXHFRCOFreq_38M0Hz = 38000000U, /**< 38 MHz RC band */
1960 #if defined(_DEVINFO_AUXHFRCOCAL13_MASK)
1961 cmuAUXHFRCOFreq_48M0Hz = 48000000U, /**< 48 MHz RC band */
1962 #endif
1963 #if defined(_DEVINFO_AUXHFRCOCAL14_MASK)
1964 cmuAUXHFRCOFreq_50M0Hz = 50000000U, /**< 50 MHz RC band */
1965 #endif
1966 cmuAUXHFRCOFreq_UserDefined = 0,
1967 };
1968 /** AUXHFRCO minimum frequency. */
1969 #define CMU_AUXHFRCO_MIN cmuAUXHFRCOFreq_1M0Hz
1970 #if defined(_DEVINFO_AUXHFRCOCAL14_MASK)
1971 /** AUXHFRCO maximum frequency. */
1972 #define CMU_AUXHFRCO_MAX cmuAUXHFRCOFreq_50M0Hz
1973 #elif defined(_DEVINFO_AUXHFRCOCAL13_MASK)
1974 /** AUXHFRCO maximum frequency. */
1975 #define CMU_AUXHFRCO_MAX cmuAUXHFRCOFreq_48M0Hz
1976 #else
1977 /** AUXHFRCO maximum frequency. */
1978 #define CMU_AUXHFRCO_MAX cmuAUXHFRCOFreq_38M0Hz
1979 #endif
1980 #endif
1981
1982 /** Clock points in CMU. See CMU overview in the reference manual. */
1983 SL_ENUM_GENERIC(CMU_Clock_TypeDef, uint32_t) {
1984 /*******************/
1985 /* HF clock branch */
1986 /*******************/
1987
1988 /** High-frequency clock */
1989 #if defined(_CMU_CTRL_HFCLKDIV_MASK) \
1990 || defined(_CMU_HFPRESC_MASK)
1991 cmuClock_HF = (CMU_HFCLKDIV_REG << CMU_DIV_REG_POS)
1992 | (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS)
1993 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
1994 | (0 << CMU_EN_BIT_POS)
1995 | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
1996 #else
1997 cmuClock_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS)
1998 | (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS)
1999 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
2000 | (0 << CMU_EN_BIT_POS)
2001 | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2002 #endif
2003
2004 /** Debug clock */
2005 cmuClock_DBG = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2006 | (CMU_DBGCLKSEL_REG << CMU_SEL_REG_POS)
2007 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
2008 | (0 << CMU_EN_BIT_POS)
2009 | (CMU_DBG_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2010
2011 /** AUX clock */
2012 cmuClock_AUX = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2013 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2014 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
2015 | (0 << CMU_EN_BIT_POS)
2016 | (CMU_AUX_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2017
2018 #if defined(_CMU_HFEXPPRESC_MASK)
2019 /**********************/
2020 /* HF export sub-branch */
2021 /**********************/
2022
2023 /** Export clock */
2024 cmuClock_EXPORT = (CMU_HFEXPPRESC_REG << CMU_PRESC_REG_POS)
2025 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2026 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
2027 | (0 << CMU_EN_BIT_POS)
2028 | (CMU_HFEXP_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2029 #endif
2030
2031 #if defined(_CMU_HFBUSCLKEN0_MASK)
2032 /**********************************/
2033 /* HF bus clock sub-branch */
2034 /**********************************/
2035
2036 /** High-frequency bus clock */
2037 #if defined(_CMU_HFBUSPRESC_MASK)
2038 cmuClock_BUS = (CMU_HFBUSPRESC_REG << CMU_PRESC_REG_POS)
2039 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2040 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
2041 | (0 << CMU_EN_BIT_POS)
2042 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2043 #else
2044 cmuClock_BUS = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
2045 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2046 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
2047 | (0 << CMU_EN_BIT_POS)
2048 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2049 #endif
2050
2051 #if defined(CMU_HFBUSCLKEN0_CRYPTO)
2052 /** Cryptography accelerator clock */
2053 cmuClock_CRYPTO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
2054 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2055 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
2056 | (_CMU_HFBUSCLKEN0_CRYPTO_SHIFT << CMU_EN_BIT_POS)
2057 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2058 #endif
2059
2060 #if defined(CMU_HFBUSCLKEN0_CRYPTO0)
2061 /** Cryptography accelerator 0 clock */
2062 cmuClock_CRYPTO0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
2063 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2064 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
2065 | (_CMU_HFBUSCLKEN0_CRYPTO0_SHIFT << CMU_EN_BIT_POS)
2066 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2067 #endif
2068
2069 #if defined(CMU_HFBUSCLKEN0_CRYPTO1)
2070 /** Cryptography accelerator 1 clock */
2071 cmuClock_CRYPTO1 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
2072 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2073 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
2074 | (_CMU_HFBUSCLKEN0_CRYPTO1_SHIFT << CMU_EN_BIT_POS)
2075 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2076 #endif
2077
2078 #if defined(CMU_HFBUSCLKEN0_LDMA)
2079 /** Direct-memory access controller clock */
2080 cmuClock_LDMA = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
2081 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2082 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
2083 | (_CMU_HFBUSCLKEN0_LDMA_SHIFT << CMU_EN_BIT_POS)
2084 | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2085 #endif
2086
2087 #if defined(CMU_HFBUSCLKEN0_QSPI0)
2088 /** Quad SPI clock */
2089 cmuClock_QSPI0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
2090 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2091 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
2092 | (_CMU_HFBUSCLKEN0_QSPI0_SHIFT << CMU_EN_BIT_POS)
2093 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2094 #endif
2095
2096 #if defined(CMU_HFBUSCLKEN0_GPCRC)
2097 /** General-purpose cyclic redundancy checksum clock */
2098 cmuClock_GPCRC = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
2099 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2100 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
2101 | (_CMU_HFBUSCLKEN0_GPCRC_SHIFT << CMU_EN_BIT_POS)
2102 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2103 #endif
2104
2105 #if defined(CMU_HFBUSCLKEN0_GPIO)
2106 /** General-purpose input/output clock */
2107 cmuClock_GPIO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
2108 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2109 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
2110 | (_CMU_HFBUSCLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS)
2111 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2112 #endif
2113
2114 /** Low-energy clock divided down from HFCLK */
2115 cmuClock_HFLE = (CMU_HFCLKLEPRESC_REG << CMU_PRESC_REG_POS)
2116 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2117 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
2118 | (_CMU_HFBUSCLKEN0_LE_SHIFT << CMU_EN_BIT_POS)
2119 | (CMU_HFLE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2120
2121 #if defined(CMU_HFBUSCLKEN0_PRS)
2122 /** Peripheral reflex system clock */
2123 cmuClock_PRS = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
2124 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2125 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
2126 | (_CMU_HFBUSCLKEN0_PRS_SHIFT << CMU_EN_BIT_POS)
2127 | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2128 #endif
2129 #endif
2130
2131 /**********************************/
2132 /* HF peripheral clock sub-branch */
2133 /**********************************/
2134
2135 /** High-frequency peripheral clock */
2136 #if defined(_CMU_HFPRESC_MASK)
2137 cmuClock_HFPER = (CMU_HFPERPRESC_REG << CMU_PRESC_REG_POS)
2138 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2139 | (CMU_CTRL_EN_REG << CMU_EN_REG_POS)
2140 | (_CMU_CTRL_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS)
2141 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2142 #else
2143 cmuClock_HFPER = (CMU_HFPERCLKDIV_REG << CMU_DIV_REG_POS)
2144 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2145 | (CMU_HFPERCLKDIV_EN_REG << CMU_EN_REG_POS)
2146 | (_CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS)
2147 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2148 #endif
2149
2150 #if defined(_CMU_HFPERPRESCB_MASK)
2151 /** Branch B figh-frequency peripheral clock */
2152 cmuClock_HFPERB = (CMU_HFPERPRESCB_REG << CMU_PRESC_REG_POS)
2153 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2154 | (CMU_CTRL_EN_REG << CMU_EN_REG_POS)
2155 | (_CMU_CTRL_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS)
2156 | (CMU_HFPERB_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2157 #endif
2158
2159 #if defined(_CMU_HFPERPRESCC_MASK)
2160 /** Branch C figh-frequency peripheral clock */
2161 cmuClock_HFPERC = (CMU_HFPERPRESCC_REG << CMU_PRESC_REG_POS)
2162 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2163 | (CMU_CTRL_EN_REG << CMU_EN_REG_POS)
2164 | (_CMU_CTRL_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS)
2165 | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2166 #endif
2167
2168 #if defined(CMU_HFPERCLKEN0_PDM)
2169 /** PDM clock */
2170 cmuClock_PDM = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
2171 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2172 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2173 | (_CMU_HFPERCLKEN0_PDM_SHIFT << CMU_EN_BIT_POS)
2174 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2175 #endif
2176
2177 #if defined(CMU_HFPERCLKEN0_USART0)
2178 /** Universal sync/async receiver/transmitter 0 clock */
2179 cmuClock_USART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2180 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2181 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2182 | (_CMU_HFPERCLKEN0_USART0_SHIFT << CMU_EN_BIT_POS)
2183 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2184 #endif
2185
2186 #if defined(CMU_HFPERCLKEN0_USARTRF0)
2187 /** Universal sync/async receiver/transmitter 0 clock */
2188 cmuClock_USARTRF0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2189 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2190 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2191 | (_CMU_HFPERCLKEN0_USARTRF0_SHIFT << CMU_EN_BIT_POS)
2192 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2193 #endif
2194
2195 #if defined(CMU_HFPERCLKEN0_USARTRF1)
2196 /** Universal sync/async receiver/transmitter 0 clock */
2197 cmuClock_USARTRF1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2198 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2199 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2200 | (_CMU_HFPERCLKEN0_USARTRF1_SHIFT << CMU_EN_BIT_POS)
2201 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2202 #endif
2203
2204 #if defined(CMU_HFPERCLKEN0_USART1)
2205 /** Universal sync/async receiver/transmitter 1 clock */
2206 cmuClock_USART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2207 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2208 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2209 | (_CMU_HFPERCLKEN0_USART1_SHIFT << CMU_EN_BIT_POS)
2210 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2211 #endif
2212
2213 #if defined(CMU_HFPERCLKEN0_USART2)
2214 /** Universal sync/async receiver/transmitter 2 clock */
2215 cmuClock_USART2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2216 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2217 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2218 | (_CMU_HFPERCLKEN0_USART2_SHIFT << CMU_EN_BIT_POS)
2219 #if defined(_CMU_HFPERPRESCB_MASK)
2220 | (CMU_HFPERB_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2221 #else
2222 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2223 #endif
2224 #endif
2225
2226 #if defined(CMU_HFPERCLKEN0_USART3)
2227 /** Universal sync/async receiver/transmitter 3 clock */
2228 cmuClock_USART3 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
2229 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2230 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2231 | (_CMU_HFPERCLKEN0_USART3_SHIFT << CMU_EN_BIT_POS)
2232 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2233 #endif
2234
2235 #if defined(CMU_HFPERCLKEN0_USART4)
2236 /** Universal sync/async receiver/transmitter 4 clock */
2237 cmuClock_USART4 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
2238 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2239 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2240 | (_CMU_HFPERCLKEN0_USART4_SHIFT << CMU_EN_BIT_POS)
2241 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2242 #endif
2243
2244 #if defined(CMU_HFPERCLKEN0_USART5)
2245 /** Universal sync/async receiver/transmitter 5 clock */
2246 cmuClock_USART5 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
2247 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2248 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2249 | (_CMU_HFPERCLKEN0_USART5_SHIFT << CMU_EN_BIT_POS)
2250 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2251 #endif
2252
2253 #if defined(CMU_HFPERCLKEN0_UART0)
2254 /** Universal async receiver/transmitter 0 clock */
2255 cmuClock_UART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2256 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2257 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2258 | (_CMU_HFPERCLKEN0_UART0_SHIFT << CMU_EN_BIT_POS)
2259 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2260 #elif defined(_CMU_HFPERCLKEN1_UART0_MASK)
2261 /** Universal async receiver/transmitter 0 clock */
2262 cmuClock_UART0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
2263 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2264 | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
2265 | (_CMU_HFPERCLKEN1_UART0_SHIFT << CMU_EN_BIT_POS)
2266 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2267 #endif
2268
2269 #if defined(CMU_HFPERCLKEN0_UART1)
2270 /** Universal async receiver/transmitter 1 clock */
2271 cmuClock_UART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2272 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2273 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2274 | (_CMU_HFPERCLKEN0_UART1_SHIFT << CMU_EN_BIT_POS)
2275 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2276 #elif defined(_CMU_HFPERCLKEN1_UART1_MASK)
2277 /** Universal async receiver/transmitter 1 clock */
2278 cmuClock_UART1 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
2279 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2280 | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
2281 | (_CMU_HFPERCLKEN1_UART1_SHIFT << CMU_EN_BIT_POS)
2282 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2283 #endif
2284
2285 #if defined(CMU_HFPERCLKEN0_TIMER0)
2286 /** Timer 0 clock */
2287 cmuClock_TIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2288 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2289 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2290 | (_CMU_HFPERCLKEN0_TIMER0_SHIFT << CMU_EN_BIT_POS)
2291 #if defined(_CMU_HFPERPRESCB_MASK)
2292 | (CMU_HFPERB_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2293 #else
2294 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2295 #endif
2296 #endif
2297
2298 #if defined(CMU_HFPERCLKEN0_TIMER1)
2299 /** Timer 1 clock */
2300 cmuClock_TIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2301 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2302 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2303 | (_CMU_HFPERCLKEN0_TIMER1_SHIFT << CMU_EN_BIT_POS)
2304 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2305 #endif
2306
2307 #if defined(CMU_HFPERCLKEN0_TIMER2)
2308 /** Timer 2 clock */
2309 cmuClock_TIMER2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2310 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2311 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2312 | (_CMU_HFPERCLKEN0_TIMER2_SHIFT << CMU_EN_BIT_POS)
2313 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2314 #endif
2315
2316 #if defined(CMU_HFPERCLKEN0_TIMER3)
2317 /** Timer 3 clock */
2318 cmuClock_TIMER3 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2319 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2320 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2321 | (_CMU_HFPERCLKEN0_TIMER3_SHIFT << CMU_EN_BIT_POS)
2322 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2323 #endif
2324
2325 #if defined(CMU_HFPERCLKEN0_TIMER4)
2326 /** Timer 4 clock */
2327 cmuClock_TIMER4 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2328 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2329 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2330 | (_CMU_HFPERCLKEN0_TIMER4_SHIFT << CMU_EN_BIT_POS)
2331 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2332 #endif
2333
2334 #if defined(CMU_HFPERCLKEN0_TIMER5)
2335 /** Timer 5 clock */
2336 cmuClock_TIMER5 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2337 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2338 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2339 | (_CMU_HFPERCLKEN0_TIMER5_SHIFT << CMU_EN_BIT_POS)
2340 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2341 #endif
2342
2343 #if defined(CMU_HFPERCLKEN0_TIMER6)
2344 /** Timer 6 clock */
2345 cmuClock_TIMER6 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2346 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2347 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2348 | (_CMU_HFPERCLKEN0_TIMER6_SHIFT << CMU_EN_BIT_POS)
2349 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2350 #endif
2351
2352 #if defined(CMU_HFPERCLKEN0_WTIMER0)
2353 /** Wide-timer 0 clock */
2354 cmuClock_WTIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2355 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2356 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2357 | (_CMU_HFPERCLKEN0_WTIMER0_SHIFT << CMU_EN_BIT_POS)
2358 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2359 #elif defined(CMU_HFPERCLKEN1_WTIMER0)
2360 /** Wide-timer 0 clock */
2361 cmuClock_WTIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2362 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2363 | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
2364 | (_CMU_HFPERCLKEN1_WTIMER0_SHIFT << CMU_EN_BIT_POS)
2365 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2366 #endif
2367
2368 #if defined(CMU_HFPERCLKEN0_WTIMER1)
2369 /** Wide-timer 1 clock */
2370 cmuClock_WTIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2371 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2372 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2373 | (_CMU_HFPERCLKEN0_WTIMER1_SHIFT << CMU_EN_BIT_POS)
2374 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2375 #elif defined(CMU_HFPERCLKEN1_WTIMER1)
2376 /** Wide-timer 1 clock */
2377 cmuClock_WTIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2378 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2379 | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
2380 | (_CMU_HFPERCLKEN1_WTIMER1_SHIFT << CMU_EN_BIT_POS)
2381 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2382 #endif
2383
2384 #if defined(CMU_HFPERCLKEN1_WTIMER2)
2385 /** Wide-timer 2 clock */
2386 cmuClock_WTIMER2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2387 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2388 | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
2389 | (_CMU_HFPERCLKEN1_WTIMER2_SHIFT << CMU_EN_BIT_POS)
2390 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2391 #endif
2392
2393 #if defined(CMU_HFPERCLKEN1_WTIMER3)
2394 /** Wide-timer 3 clock */
2395 cmuClock_WTIMER3 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2396 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2397 | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
2398 | (_CMU_HFPERCLKEN1_WTIMER3_SHIFT << CMU_EN_BIT_POS)
2399 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2400 #endif
2401
2402 #if defined(CMU_HFPERCLKEN0_CRYOTIMER)
2403 /** CRYOtimer clock */
2404 cmuClock_CRYOTIMER = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
2405 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2406 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2407 | (_CMU_HFPERCLKEN0_CRYOTIMER_SHIFT << CMU_EN_BIT_POS)
2408 #if defined(_CMU_HFPERPRESCC_MASK)
2409 | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2410 #else
2411 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2412 #endif
2413 #endif
2414
2415 #if defined(CMU_HFPERCLKEN0_ACMP0)
2416 /** Analog comparator 0 clock */
2417 cmuClock_ACMP0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2418 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2419 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2420 | (_CMU_HFPERCLKEN0_ACMP0_SHIFT << CMU_EN_BIT_POS)
2421 #if defined(_CMU_HFPERPRESCC_MASK)
2422 | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2423 #else
2424 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2425 #endif
2426 #endif
2427
2428 #if defined(CMU_HFPERCLKEN0_ACMP1)
2429 /** Analog comparator 1 clock */
2430 cmuClock_ACMP1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2431 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2432 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2433 | (_CMU_HFPERCLKEN0_ACMP1_SHIFT << CMU_EN_BIT_POS)
2434 #if defined(_CMU_HFPERPRESCC_MASK)
2435 | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2436 #else
2437 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2438 #endif
2439 #endif
2440
2441 #if defined(CMU_HFPERCLKEN0_ACMP2)
2442 /** Analog comparator 2 clock */
2443 cmuClock_ACMP2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2444 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2445 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2446 | (_CMU_HFPERCLKEN0_ACMP2_SHIFT << CMU_EN_BIT_POS)
2447 | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2448 #endif
2449
2450 #if defined(CMU_HFPERCLKEN0_ACMP3)
2451 /** Analog comparator 3 clock */
2452 cmuClock_ACMP3 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2453 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2454 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2455 | (_CMU_HFPERCLKEN0_ACMP3_SHIFT << CMU_EN_BIT_POS)
2456 | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2457 #endif
2458
2459 #if defined(CMU_HFPERCLKEN0_PRS)
2460 /** Peripheral-reflex system clock */
2461 cmuClock_PRS = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2462 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2463 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2464 | (_CMU_HFPERCLKEN0_PRS_SHIFT << CMU_EN_BIT_POS)
2465 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2466 #endif
2467
2468 #if defined(CMU_HFPERCLKEN0_DAC0)
2469 /** Digital-to-analog converter 0 clock */
2470 cmuClock_DAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2471 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2472 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2473 | (_CMU_HFPERCLKEN0_DAC0_SHIFT << CMU_EN_BIT_POS)
2474 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2475 #endif
2476
2477 #if defined(CMU_HFPERCLKEN0_VDAC0)
2478 /** Voltage digital-to-analog converter 0 clock */
2479 cmuClock_VDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2480 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2481 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2482 | (_CMU_HFPERCLKEN0_VDAC0_SHIFT << CMU_EN_BIT_POS)
2483 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2484 #elif defined(CMU_HFPERCLKEN1_VDAC0)
2485 /** Voltage digital-to-analog converter 0 clock */
2486 cmuClock_VDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2487 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2488 | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
2489 | (_CMU_HFPERCLKEN1_VDAC0_SHIFT << CMU_EN_BIT_POS)
2490 #if defined(_CMU_HFPERPRESCC_MASK)
2491 | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2492 #else
2493 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2494 #endif
2495 #endif
2496
2497 #if defined(CMU_HFPERCLKEN0_IDAC0)
2498 /** Current digital-to-analog converter 0 clock */
2499 cmuClock_IDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2500 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2501 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2502 | (_CMU_HFPERCLKEN0_IDAC0_SHIFT << CMU_EN_BIT_POS)
2503 #if defined(_CMU_HFPERPRESCC_MASK)
2504 | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2505 #else
2506 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2507 #endif
2508 #endif
2509
2510 #if defined(CMU_HFPERCLKEN0_GPIO)
2511 /** General-purpose input/output clock */
2512 cmuClock_GPIO = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2513 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2514 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2515 | (_CMU_HFPERCLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS)
2516 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2517 #endif
2518
2519 #if defined(CMU_HFPERCLKEN0_VCMP)
2520 /** Voltage comparator clock */
2521 cmuClock_VCMP = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2522 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2523 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2524 | (_CMU_HFPERCLKEN0_VCMP_SHIFT << CMU_EN_BIT_POS)
2525 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2526 #endif
2527
2528 #if defined(CMU_HFPERCLKEN0_ADC0)
2529 /** Analog-to-digital converter 0 clock */
2530 cmuClock_ADC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2531 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2532 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2533 | (_CMU_HFPERCLKEN0_ADC0_SHIFT << CMU_EN_BIT_POS)
2534 #if defined(_CMU_HFPERPRESCC_MASK)
2535 | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2536 #else
2537 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2538 #endif
2539 #endif
2540
2541 #if defined(CMU_HFPERCLKEN0_ADC1)
2542 /** Analog-to-digital converter 1 clock */
2543 cmuClock_ADC1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2544 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2545 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2546 | (_CMU_HFPERCLKEN0_ADC1_SHIFT << CMU_EN_BIT_POS)
2547 | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2548 #endif
2549
2550 #if defined(CMU_HFPERCLKEN0_I2C0)
2551 /** I2C 0 clock */
2552 cmuClock_I2C0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2553 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2554 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2555 | (_CMU_HFPERCLKEN0_I2C0_SHIFT << CMU_EN_BIT_POS)
2556 #if defined(_CMU_HFPERPRESCC_MASK)
2557 | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2558 #else
2559 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2560 #endif
2561 #endif
2562
2563 #if defined(CMU_HFPERCLKEN0_I2C1)
2564 /** I2C 1 clock */
2565 cmuClock_I2C1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2566 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2567 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2568 | (_CMU_HFPERCLKEN0_I2C1_SHIFT << CMU_EN_BIT_POS)
2569 #if defined(_CMU_HFPERPRESCC_MASK)
2570 | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2571 #else
2572 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2573 #endif
2574 #endif
2575
2576 #if defined(CMU_HFPERCLKEN0_I2C2)
2577 /** I2C 2 clock */
2578 cmuClock_I2C2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2579 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2580 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2581 | (_CMU_HFPERCLKEN0_I2C2_SHIFT << CMU_EN_BIT_POS)
2582 | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2583 #endif
2584
2585 #if defined(CMU_HFPERCLKEN0_CSEN)
2586 /** Capacitive Sense HF clock */
2587 cmuClock_CSEN_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2588 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2589 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2590 | (_CMU_HFPERCLKEN0_CSEN_SHIFT << CMU_EN_BIT_POS)
2591 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2592 #elif defined(CMU_HFPERCLKEN1_CSEN)
2593 /** Capacitive Sense HF clock */
2594 cmuClock_CSEN_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2595 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2596 | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
2597 | (_CMU_HFPERCLKEN1_CSEN_SHIFT << CMU_EN_BIT_POS)
2598 | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2599 #endif
2600
2601 #if defined(CMU_HFPERCLKEN0_TRNG0)
2602 /** True random number generator clock */
2603 cmuClock_TRNG0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2604 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2605 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2606 | (_CMU_HFPERCLKEN0_TRNG0_SHIFT << CMU_EN_BIT_POS)
2607 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2608 #endif
2609
2610 #if defined(_CMU_HFPERCLKEN1_CAN0_MASK)
2611 /** Controller Area Network 0 clock */
2612 cmuClock_CAN0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
2613 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2614 | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
2615 | (_CMU_HFPERCLKEN1_CAN0_SHIFT << CMU_EN_BIT_POS)
2616 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2617 #endif
2618
2619 #if defined(_CMU_HFPERCLKEN1_CAN1_MASK)
2620 /** Controller Area Network 1 clock. */
2621 cmuClock_CAN1 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
2622 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2623 | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
2624 | (_CMU_HFPERCLKEN1_CAN1_SHIFT << CMU_EN_BIT_POS)
2625 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2626 #endif
2627
2628 /**********************/
2629 /* HF core sub-branch */
2630 /**********************/
2631
2632 /** Core clock */
2633 cmuClock_CORE = (CMU_HFCORECLKDIV_REG << CMU_DIV_REG_POS)
2634 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2635 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
2636 | (0 << CMU_EN_BIT_POS)
2637 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2638
2639 #if defined(CMU_HFCORECLKEN0_AES)
2640 /** Advanced encryption standard accelerator clock */
2641 cmuClock_AES = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2642 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2643 | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
2644 | (_CMU_HFCORECLKEN0_AES_SHIFT << CMU_EN_BIT_POS)
2645 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2646 #endif
2647
2648 #if defined(CMU_HFCORECLKEN0_DMA)
2649 /** Direct memory access controller clock */
2650 cmuClock_DMA = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2651 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2652 | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
2653 | (_CMU_HFCORECLKEN0_DMA_SHIFT << CMU_EN_BIT_POS)
2654 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2655 #endif
2656
2657 #if defined(CMU_HFCORECLKEN0_LE)
2658 /** Low-energy clock divided down from HFCORECLK */
2659 cmuClock_HFLE = (CMU_HFCORECLKLEDIV_REG << CMU_DIV_REG_POS)
2660 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2661 | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
2662 | (_CMU_HFCORECLKEN0_LE_SHIFT << CMU_EN_BIT_POS)
2663 | (CMU_HFLE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2664 #endif
2665
2666 #if defined(CMU_HFCORECLKEN0_EBI)
2667 /** External bus interface clock */
2668 cmuClock_EBI = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2669 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2670 | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
2671 | (_CMU_HFCORECLKEN0_EBI_SHIFT << CMU_EN_BIT_POS)
2672 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2673 #elif defined(_CMU_HFBUSCLKEN0_EBI_MASK)
2674 /** External bus interface clock */
2675 cmuClock_EBI = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
2676 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2677 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
2678 | (_CMU_HFBUSCLKEN0_EBI_SHIFT << CMU_EN_BIT_POS)
2679 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2680 #endif
2681
2682 #if defined(_CMU_HFBUSCLKEN0_ETH_MASK)
2683 /** Ethernet clock */
2684 cmuClock_ETH = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
2685 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2686 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
2687 | (_CMU_HFBUSCLKEN0_ETH_SHIFT << CMU_EN_BIT_POS)
2688 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2689 #endif
2690
2691 #if defined(_CMU_HFBUSCLKEN0_SDIO_MASK)
2692 /** SDIO clock */
2693 cmuClock_SDIO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
2694 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2695 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
2696 | (_CMU_HFBUSCLKEN0_SDIO_SHIFT << CMU_EN_BIT_POS)
2697 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2698 #endif
2699
2700 #if defined(USBC_CLOCK_PRESENT)
2701 /** USB Core clock */
2702 cmuClock_USBC = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2703 | (CMU_USBCCLKSEL_REG << CMU_SEL_REG_POS)
2704 | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
2705 | (_CMU_HFCORECLKEN0_USBC_SHIFT << CMU_EN_BIT_POS)
2706 | (CMU_USBC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2707 #endif
2708 #if defined (USBR_CLOCK_PRESENT)
2709 /** USB Rate clock */
2710 cmuClock_USBR = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2711 | (CMU_USBRCLKSEL_REG << CMU_SEL_REG_POS)
2712 | (CMU_USBRCLK_EN_REG << CMU_EN_REG_POS)
2713 | (_CMU_USBCTRL_USBCLKEN_SHIFT << CMU_EN_BIT_POS)
2714 | (CMU_USBR_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2715 #endif
2716
2717 #if defined(CMU_HFCORECLKEN0_USB)
2718 /** USB clock */
2719 cmuClock_USB = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2720 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2721 | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
2722 | (_CMU_HFCORECLKEN0_USB_SHIFT << CMU_EN_BIT_POS)
2723 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2724 #elif defined(CMU_HFBUSCLKEN0_USB)
2725 /** USB clock */
2726 cmuClock_USB = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
2727 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2728 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
2729 | (_CMU_HFBUSCLKEN0_USB_SHIFT << CMU_EN_BIT_POS)
2730 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2731 #endif
2732
2733 /***************/
2734 /* LF A branch */
2735 /***************/
2736
2737 /** Low-frequency A clock */
2738 cmuClock_LFA = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2739 | (CMU_LFACLKSEL_REG << CMU_SEL_REG_POS)
2740 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
2741 | (0 << CMU_EN_BIT_POS)
2742 | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2743
2744 #if defined(CMU_LFACLKEN0_RTC)
2745 /** Real time counter clock */
2746 cmuClock_RTC = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)
2747 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2748 | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)
2749 | (_CMU_LFACLKEN0_RTC_SHIFT << CMU_EN_BIT_POS)
2750 | (CMU_RTC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2751 #endif
2752
2753 #if defined(CMU_LFACLKEN0_LETIMER0)
2754 /** Low-energy timer 0 clock */
2755 cmuClock_LETIMER0 = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)
2756 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2757 | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)
2758 | (_CMU_LFACLKEN0_LETIMER0_SHIFT << CMU_EN_BIT_POS)
2759 | (CMU_LETIMER0_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2760 #endif
2761
2762 #if defined(CMU_LFACLKEN0_LETIMER1)
2763 /** Low-energy timer 1 clock */
2764 cmuClock_LETIMER1 = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)
2765 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2766 | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)
2767 | (_CMU_LFACLKEN0_LETIMER1_SHIFT << CMU_EN_BIT_POS)
2768 | (CMU_LETIMER1_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2769 #endif
2770
2771 #if defined(CMU_LFACLKEN0_LCD)
2772 /** Liquid crystal display, pre FDIV clock */
2773 cmuClock_LCDpre = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)
2774 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2775 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
2776 | (0 << CMU_EN_BIT_POS)
2777 | (CMU_LCDPRE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2778
2779 /** Liquid crystal display clock. Note that FDIV prescaler
2780 * must be set by special API. */
2781 cmuClock_LCD = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2782 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2783 | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)
2784 | (_CMU_LFACLKEN0_LCD_SHIFT << CMU_EN_BIT_POS)
2785 | (CMU_LCD_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2786 #endif
2787
2788 #if defined(CMU_PCNTCTRL_PCNT0CLKEN)
2789 /** Pulse counter 0 clock */
2790 cmuClock_PCNT0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2791 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2792 | (CMU_PCNT_EN_REG << CMU_EN_REG_POS)
2793 | (_CMU_PCNTCTRL_PCNT0CLKEN_SHIFT << CMU_EN_BIT_POS)
2794 | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2795 #endif
2796
2797 #if defined(CMU_PCNTCTRL_PCNT1CLKEN)
2798 /** Pulse counter 1 clock */
2799 cmuClock_PCNT1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2800 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2801 | (CMU_PCNT_EN_REG << CMU_EN_REG_POS)
2802 | (_CMU_PCNTCTRL_PCNT1CLKEN_SHIFT << CMU_EN_BIT_POS)
2803 | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2804 #endif
2805
2806 #if defined(CMU_PCNTCTRL_PCNT2CLKEN)
2807 /** Pulse counter 2 clock */
2808 cmuClock_PCNT2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2809 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2810 | (CMU_PCNT_EN_REG << CMU_EN_REG_POS)
2811 | (_CMU_PCNTCTRL_PCNT2CLKEN_SHIFT << CMU_EN_BIT_POS)
2812 | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2813 #endif
2814 #if defined(CMU_LFACLKEN0_LESENSE)
2815 /** LESENSE clock */
2816 cmuClock_LESENSE = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)
2817 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2818 | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)
2819 | (_CMU_LFACLKEN0_LESENSE_SHIFT << CMU_EN_BIT_POS)
2820 | (CMU_LESENSE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2821 #endif
2822
2823 /***************/
2824 /* LF B branch */
2825 /***************/
2826
2827 /** Low-frequency B clock */
2828 cmuClock_LFB = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2829 | (CMU_LFBCLKSEL_REG << CMU_SEL_REG_POS)
2830 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
2831 | (0 << CMU_EN_BIT_POS)
2832 | (CMU_LFB_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2833
2834 #if defined(CMU_LFBCLKEN0_LEUART0)
2835 /** Low-energy universal asynchronous receiver/transmitter 0 clock */
2836 cmuClock_LEUART0 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS)
2837 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2838 | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS)
2839 | (_CMU_LFBCLKEN0_LEUART0_SHIFT << CMU_EN_BIT_POS)
2840 | (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2841 #endif
2842
2843 #if defined(CMU_LFBCLKEN0_CSEN)
2844 /** Capacitive Sense LF clock */
2845 cmuClock_CSEN_LF = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS)
2846 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2847 | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS)
2848 | (_CMU_LFBCLKEN0_CSEN_SHIFT << CMU_EN_BIT_POS)
2849 | (CMU_CSEN_LF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2850 #endif
2851
2852 #if defined(CMU_LFBCLKEN0_LEUART1)
2853 /** Low-energy universal asynchronous receiver/transmitter 1 clock */
2854 cmuClock_LEUART1 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS)
2855 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2856 | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS)
2857 | (_CMU_LFBCLKEN0_LEUART1_SHIFT << CMU_EN_BIT_POS)
2858 | (CMU_LEUART1_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2859 #endif
2860
2861 #if defined(CMU_LFBCLKEN0_SYSTICK)
2862 /** Cortex SYSTICK LF clock */
2863 cmuClock_SYSTICK = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS)
2864 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2865 | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS)
2866 | (_CMU_LFBCLKEN0_SYSTICK_SHIFT << CMU_EN_BIT_POS)
2867 | (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2868 #endif
2869
2870 #if defined(_CMU_LFCCLKEN0_MASK)
2871 /***************/
2872 /* LF C branch */
2873 /***************/
2874
2875 /** Low-frequency C clock */
2876 cmuClock_LFC = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2877 | (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS)
2878 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
2879 | (0 << CMU_EN_BIT_POS)
2880 | (CMU_LFC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2881
2882 #if defined(CMU_LFCCLKEN0_USBLE)
2883 /** USB LE clock */
2884 cmuClock_USBLE = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2885 | (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS)
2886 | (CMU_LFCCLKEN0_EN_REG << CMU_EN_REG_POS)
2887 | (_CMU_LFCCLKEN0_USBLE_SHIFT << CMU_EN_BIT_POS)
2888 | (CMU_USBLE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2889 #elif defined(CMU_LFCCLKEN0_USB)
2890 /** USB LE clock */
2891 cmuClock_USBLE = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2892 | (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS)
2893 | (CMU_LFCCLKEN0_EN_REG << CMU_EN_REG_POS)
2894 | (_CMU_LFCCLKEN0_USB_SHIFT << CMU_EN_BIT_POS)
2895 | (CMU_USBLE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2896 #endif
2897 #endif
2898
2899 #if defined(_CMU_LFECLKEN0_MASK)
2900 /***************/
2901 /* LF E branch */
2902 /***************/
2903
2904 /** Low-frequency E clock */
2905 cmuClock_LFE = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
2906 | (CMU_LFECLKSEL_REG << CMU_SEL_REG_POS)
2907 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
2908 | (0 << CMU_EN_BIT_POS)
2909 | (CMU_LFE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2910
2911 /** Real-time counter and calendar clock */
2912 #if defined (CMU_LFECLKEN0_RTCC)
2913 cmuClock_RTCC = (CMU_LFEPRESC0_REG << CMU_PRESC_REG_POS)
2914 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2915 | (CMU_LFECLKEN0_EN_REG << CMU_EN_REG_POS)
2916 | (_CMU_LFECLKEN0_RTCC_SHIFT << CMU_EN_BIT_POS)
2917 | (CMU_RTCC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2918 #endif
2919 #endif
2920
2921 /**********************************/
2922 /* Asynchronous peripheral clocks */
2923 /**********************************/
2924
2925 #if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK)
2926 /** ADC0 asynchronous clock */
2927 cmuClock_ADC0ASYNC = (CMU_ADCASYNCDIV_REG << CMU_DIV_REG_POS)
2928 | (CMU_ADC0ASYNCSEL_REG << CMU_SEL_REG_POS)
2929 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
2930 | (0 << CMU_EN_BIT_POS)
2931 | (CMU_ADC0ASYNC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2932 #endif
2933
2934 #if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK)
2935 /** ADC1 asynchronous clock */
2936 cmuClock_ADC1ASYNC = (CMU_ADCASYNCDIV_REG << CMU_DIV_REG_POS)
2937 | (CMU_ADC1ASYNCSEL_REG << CMU_SEL_REG_POS)
2938 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
2939 | (0 << CMU_EN_BIT_POS)
2940 | (CMU_ADC1ASYNC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2941 #endif
2942
2943 #if defined(_CMU_SDIOCTRL_SDIOCLKDIS_MASK)
2944 /** SDIO reference clock */
2945 cmuClock_SDIOREF = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2946 | (CMU_SDIOREFSEL_REG << CMU_SEL_REG_POS)
2947 | (CMU_SDIOREF_EN_REG << CMU_EN_REG_POS)
2948 | (_CMU_SDIOCTRL_SDIOCLKDIS_SHIFT << CMU_EN_BIT_POS)
2949 | (CMU_SDIOREF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2950 #endif
2951
2952 #if defined(_CMU_QSPICTRL_QSPI0CLKDIS_MASK)
2953 /** QSPI0 reference clock */
2954 cmuClock_QSPI0REF = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2955 | (CMU_QSPI0REFSEL_REG << CMU_SEL_REG_POS)
2956 | (CMU_QSPI0REF_EN_REG << CMU_EN_REG_POS)
2957 | (_CMU_QSPICTRL_QSPI0CLKDIS_SHIFT << CMU_EN_BIT_POS)
2958 | (CMU_QSPI0REF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2959 #endif
2960
2961 #if defined(_CMU_PDMCTRL_PDMCLKEN_MASK)
2962 /** PDM reference clock */
2963 cmuClock_PDMREF = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2964 | (CMU_PDMREFSEL_REG << CMU_SEL_REG_POS)
2965 | (CMU_PDMREF_EN_REG << CMU_EN_REG_POS)
2966 | (_CMU_PDMCTRL_PDMCLKEN_SHIFT << CMU_EN_BIT_POS)
2967 | (CMU_PDMREF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2968 #endif
2969 };
2970
2971 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
2972 /* Deprecated CMU_Clock_TypeDef member */
2973 #define cmuClock_CORELE cmuClock_HFLE
2974 /** @endcond */
2975
2976 /** Oscillator types. */
2977 SL_ENUM(CMU_Osc_TypeDef) {
2978 cmuOsc_LFXO, /**< Low-frequency crystal oscillator. */
2979 cmuOsc_LFRCO, /**< Low-frequency RC oscillator. */
2980 cmuOsc_HFXO, /**< High-frequency crystal oscillator. */
2981 cmuOsc_HFRCO, /**< High-frequency RC oscillator. */
2982 cmuOsc_AUXHFRCO, /**< Auxiliary high-frequency RC oscillator. */
2983 #if defined(_CMU_STATUS_USHFRCOENS_MASK)
2984 cmuOsc_USHFRCO, /**< Universal serial high-frequency RC oscillator */
2985 #endif
2986 #if defined(CMU_LFCLKSEL_LFAE_ULFRCO) || defined(CMU_LFACLKSEL_LFA_ULFRCO)
2987 cmuOsc_ULFRCO, /**< Ultra low-frequency RC oscillator. */
2988 #endif
2989 #if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0)
2990 cmuOsc_CLKIN0, /**< External oscillator. */
2991 #endif
2992 #if defined(PLFRCO_PRESENT)
2993 cmuOsc_PLFRCO, /**< Precision Low Frequency Oscillator. */
2994 #endif
2995 };
2996
2997 /** Oscillator modes. */
2998 SL_ENUM(CMU_OscMode_TypeDef) {
2999 cmuOscMode_Crystal, /**< Crystal oscillator. */
3000 cmuOscMode_AcCoupled, /**< AC-coupled buffer. */
3001 cmuOscMode_External, /**< External digital clock. */
3002 };
3003
3004 /** Selectable clock sources. */
3005 SL_ENUM(CMU_Select_TypeDef) {
3006 cmuSelect_Error, /**< Usage error. */
3007 cmuSelect_Disabled, /**< Clock selector disabled. */
3008 cmuSelect_LFXO, /**< Low-frequency crystal oscillator. */
3009 cmuSelect_LFRCO, /**< Low-frequency RC oscillator. */
3010 cmuSelect_HFXO, /**< High-frequency crystal oscillator. */
3011 cmuSelect_HFRCO, /**< High-frequency RC oscillator. */
3012 cmuSelect_HFCLKLE, /**< High-frequency LE clock divided by 2 or 4. */
3013 cmuSelect_AUXHFRCO, /**< Auxiliary clock source can be used for debug clock. */
3014 cmuSelect_HFSRCCLK, /**< High-frequency source clock. */
3015 cmuSelect_HFCLK, /**< Divided HFCLK on Giant for debug clock, undivided on
3016 Tiny Gecko and for USBC (not used on Gecko). */
3017 #if defined(CMU_STATUS_USHFRCOENS)
3018 cmuSelect_USHFRCO, /**< Universal serial high-frequency RC oscillator. */
3019 #endif
3020 #if defined(CMU_CMD_HFCLKSEL_USHFRCODIV2)
3021 cmuSelect_USHFRCODIV2, /**< Universal serial high-frequency RC oscillator / 2. */
3022 #endif
3023 #if defined(CMU_HFXOCTRL_HFXOX2EN)
3024 cmuSelect_HFXOX2, /**< High-frequency crystal oscillator x 2. */
3025 #endif
3026 #if defined(CMU_LFCLKSEL_LFAE_ULFRCO) || defined(CMU_LFACLKSEL_LFA_ULFRCO)
3027 cmuSelect_ULFRCO, /**< Ultra low-frequency RC oscillator. */
3028 #endif
3029 #if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2)
3030 cmuSelect_HFRCODIV2, /**< High-frequency RC oscillator divided by 2. */
3031 #endif
3032 #if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0)
3033 cmuSelect_CLKIN0, /**< External clock input. */
3034 #endif
3035 #if defined(PLFRCO_PRESENT)
3036 cmuSelect_PLFRCO, /**< Precision Low Frequency Oscillator. */
3037 #endif
3038 };
3039
3040 #if defined(CMU_HFCORECLKEN0_LE)
3041 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
3042 /* Deprecated CMU_Select_TypeDef member */
3043 #define cmuSelect_CORELEDIV2 cmuSelect_HFCLKLE
3044 /** @endcond */
3045 #endif
3046
3047 #if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) || defined(_CMU_HFXOCTRL_PEAKDETMODE_MASK)
3048 /** HFXO tuning modes */
3049 SL_ENUM_GENERIC(CMU_HFXOTuningMode_TypeDef, uint32_t) {
3050 cmuHFXOTuningMode_Auto = 0,
3051 cmuHFXOTuningMode_PeakDetectCommand = CMU_CMD_HFXOPEAKDETSTART, /**< Run peak detect optimization only. */
3052 #if defined(CMU_CMD_HFXOSHUNTOPTSTART)
3053 cmuHFXOTuningMode_ShuntCommand = CMU_CMD_HFXOSHUNTOPTSTART, /**< Run shunt current optimization only. */
3054 cmuHFXOTuningMode_PeakShuntCommand = CMU_CMD_HFXOPEAKDETSTART /**< Run peak and shunt current optimization. */
3055 | CMU_CMD_HFXOSHUNTOPTSTART,
3056 #endif
3057 };
3058 #endif
3059
3060 #if defined(_CMU_CTRL_LFXOBOOST_MASK)
3061 /** LFXO Boost values. */
3062 SL_ENUM(CMU_LFXOBoost_TypeDef) {
3063 cmuLfxoBoost70 = 0x0,
3064 cmuLfxoBoost100 = 0x2,
3065 #if defined(_EMU_AUXCTRL_REDLFXOBOOST_MASK)
3066 cmuLfxoBoost70Reduced = 0x1,
3067 cmuLfxoBoost100Reduced = 0x3,
3068 #endif
3069 };
3070 #endif
3071
3072 #if defined(CMU_OSCENCMD_DPLLEN)
3073 /** DPLL reference clock selector. */
3074 SL_ENUM_GENERIC(CMU_DPLLClkSel_TypeDef, uint32_t) {
3075 cmuDPLLClkSel_Hfxo = _CMU_DPLLCTRL_REFSEL_HFXO, /**< HFXO is DPLL reference clock. */
3076 cmuDPLLClkSel_Lfxo = _CMU_DPLLCTRL_REFSEL_LFXO, /**< LFXO is DPLL reference clock. */
3077 cmuDPLLClkSel_Clkin0 = _CMU_DPLLCTRL_REFSEL_CLKIN0 /**< CLKIN0 is DPLL reference clock. */
3078 };
3079
3080 /** DPLL reference clock edge detect selector. */
3081 SL_ENUM_GENERIC(CMU_DPLLEdgeSel_TypeDef, uint32_t) {
3082 cmuDPLLEdgeSel_Fall = _CMU_DPLLCTRL_EDGESEL_FALL, /**< Detect falling edge of reference clock. */
3083 cmuDPLLEdgeSel_Rise = _CMU_DPLLCTRL_EDGESEL_RISE /**< Detect rising edge of reference clock. */
3084 };
3085
3086 /** DPLL lock mode selector. */
3087 SL_ENUM_GENERIC(CMU_DPLLLockMode_TypeDef, uint32_t) {
3088 cmuDPLLLockMode_Freq = _CMU_DPLLCTRL_MODE_FREQLL, /**< Frequency lock mode. */
3089 cmuDPLLLockMode_Phase = _CMU_DPLLCTRL_MODE_PHASELL /**< Phase lock mode. */
3090 };
3091 #endif // CMU_OSCENCMD_DPLLEN
3092
3093 /*******************************************************************************
3094 ******************************* STRUCTS ***********************************
3095 ******************************************************************************/
3096
3097 /** LFXO initialization structure.
3098 * Initialization values should be obtained from a configuration tool,
3099 * application note or crystal data sheet. */
3100 typedef struct {
3101 #if defined(_CMU_LFXOCTRL_MASK)
3102 uint8_t ctune; /**< CTUNE (load capacitance) value */
3103 uint8_t gain; /**< Gain/max startup margin */
3104 #else
3105 CMU_LFXOBoost_TypeDef boost; /**< LFXO boost */
3106 #endif
3107 uint8_t timeout; /**< Startup delay */
3108 CMU_OscMode_TypeDef mode; /**< Oscillator mode */
3109 } CMU_LFXOInit_TypeDef;
3110
3111 #if defined(_CMU_LFXOCTRL_MASK)
3112 /** Default LFXO initialization values. */
3113 #define CMU_LFXOINIT_DEFAULT \
3114 { \
3115 _CMU_LFXOCTRL_TUNING_DEFAULT, /* Default CTUNE value, 0 */ \
3116 _CMU_LFXOCTRL_GAIN_DEFAULT, /* Default gain, 2 */ \
3117 _CMU_LFXOCTRL_TIMEOUT_DEFAULT, /* Default start-up delay, 32 K cycles */ \
3118 cmuOscMode_Crystal, /* Crystal oscillator */ \
3119 }
3120 /** Default LFXO initialization for external clock */
3121 #define CMU_LFXOINIT_EXTERNAL_CLOCK \
3122 { \
3123 0, /* No CTUNE value needed */ \
3124 0, /* No LFXO startup gain */ \
3125 _CMU_LFXOCTRL_TIMEOUT_2CYCLES, /* Minimal lfxo start-up delay, 2 cycles */ \
3126 cmuOscMode_External, /* External digital clock */ \
3127 }
3128 #else
3129 /** Default LFXO initialization values. */
3130 #define CMU_LFXOINIT_DEFAULT \
3131 { \
3132 cmuLfxoBoost70, \
3133 _CMU_CTRL_LFXOTIMEOUT_DEFAULT, \
3134 cmuOscMode_Crystal, \
3135 }
3136 /** Default LFXO initialization for external clock */
3137 #define CMU_LFXOINIT_EXTERNAL_CLOCK \
3138 { \
3139 cmuLfxoBoost70, \
3140 _CMU_CTRL_LFXOTIMEOUT_8CYCLES, \
3141 cmuOscMode_External, \
3142 }
3143 #endif
3144
3145 /** HFXO initialization structure.
3146 * Initialization values should be obtained from a configuration tool,
3147 * application note or crystal data sheet. */
3148 typedef struct {
3149 #if defined(_SILICON_LABS_32B_SERIES_1) && (_SILICON_LABS_GECKO_INTERNAL_SDID >= 100)
3150 uint16_t ctuneStartup; /**< Startup phase CTUNE (load capacitance) value */
3151 uint16_t ctuneSteadyState; /**< Steady-state phase CTUNE (load capacitance) value */
3152 uint16_t xoCoreBiasTrimStartup; /**< Startup XO core bias current trim */
3153 uint16_t xoCoreBiasTrimSteadyState; /**< Steady-state XO core bias current trim */
3154 uint8_t timeoutPeakDetect; /**< Timeout - peak detection */
3155 uint8_t timeoutSteady; /**< Timeout - steady-state */
3156 uint8_t timeoutStartup; /**< Timeout - startup */
3157 #elif defined(_CMU_HFXOCTRL_MASK)
3158 bool lowPowerMode; /**< Enable low-power mode */
3159 bool autoStartEm01; /**< @deprecated Use @ref CMU_HFXOAutostartEnable instead. */
3160 bool autoSelEm01; /**< @deprecated Use @ref CMU_HFXOAutostartEnable instead. */
3161 bool autoStartSelOnRacWakeup; /**< @deprecated Use @ref CMU_HFXOAutostartEnable instead. */
3162 uint16_t ctuneStartup; /**< Startup phase CTUNE (load capacitance) value */
3163 uint16_t ctuneSteadyState; /**< Steady-state phase CTUNE (load capacitance) value */
3164 uint8_t regIshSteadyState; /**< Shunt steady-state current */
3165 uint8_t xoCoreBiasTrimStartup; /**< Startup XO core bias current trim */
3166 uint8_t xoCoreBiasTrimSteadyState; /**< Steady-state XO core bias current trim */
3167 uint8_t thresholdPeakDetect; /**< Peak detection threshold */
3168 uint8_t timeoutShuntOptimization; /**< Timeout - shunt optimization */
3169 uint8_t timeoutPeakDetect; /**< Timeout - peak detection */
3170 uint8_t timeoutSteady; /**< Timeout - steady-state */
3171 uint8_t timeoutStartup; /**< Timeout - startup */
3172 #else
3173 uint8_t boost; /**< HFXO Boost, 0=50% 1=70%, 2=80%, 3=100% */
3174 uint8_t timeout; /**< Startup delay */
3175 bool glitchDetector; /**< Enable/disable glitch detector */
3176 #endif
3177 CMU_OscMode_TypeDef mode; /**< Oscillator mode */
3178 } CMU_HFXOInit_TypeDef;
3179
3180 #if defined(_SILICON_LABS_32B_SERIES_1) && (_SILICON_LABS_GECKO_INTERNAL_SDID >= 100)
3181 /** Default HFXO init. */
3182 #define CMU_HFXOINIT_DEFAULT \
3183 { \
3184 _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \
3185 _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \
3186 _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT, \
3187 _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT, \
3188 _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT, \
3189 _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT, \
3190 _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \
3191 cmuOscMode_Crystal, \
3192 }
3193 /** Init of HFXO with external clock. */
3194 #define CMU_HFXOINIT_EXTERNAL_CLOCK \
3195 { \
3196 _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \
3197 _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \
3198 _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT, \
3199 _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT, \
3200 _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT, \
3201 _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT, \
3202 _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \
3203 cmuOscMode_External, \
3204 }
3205 #elif defined(_CMU_HFXOCTRL_MASK)
3206 /**
3207 * Default HFXO initialization values for Platform 2 devices, which contain a
3208 * separate HFXOCTRL register.
3209 */
3210 #if defined(_EFR_DEVICE)
3211 #define CMU_HFXOINIT_DEFAULT \
3212 { \
3213 false, /* Low-noise mode for EFR32 */ \
3214 false, /* @deprecated no longer in use */ \
3215 false, /* @deprecated no longer in use */ \
3216 false, /* @deprecated no longer in use */ \
3217 _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \
3218 _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \
3219 0xA, /* Default Shunt steady-state current */ \
3220 0x20, /* Matching errata fix in @ref CHIP_Init() */ \
3221 0x7, /* Recommended steady-state XO core bias current */ \
3222 0x6, /* Recommended peak detection threshold */ \
3223 0x2, /* Recommended shunt optimization timeout */ \
3224 0xA, /* Recommended peak detection timeout */ \
3225 0x4, /* Recommended steady timeout */ \
3226 _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \
3227 cmuOscMode_Crystal, \
3228 }
3229 #else /* EFM32 device */
3230 #define CMU_HFXOINIT_DEFAULT \
3231 { \
3232 true, /* Low-power mode for EFM32 */ \
3233 false, /* @deprecated no longer in use */ \
3234 false, /* @deprecated no longer in use */ \
3235 false, /* @deprecated no longer in use */ \
3236 _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \
3237 _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \
3238 0xA, /* Default shunt steady-state current */ \
3239 0x20, /* Matching errata fix in @ref CHIP_Init() */ \
3240 0x7, /* Recommended steady-state osc core bias current */ \
3241 0x6, /* Recommended peak detection threshold */ \
3242 0x2, /* Recommended shunt optimization timeout */ \
3243 0xA, /* Recommended peak detection timeout */ \
3244 0x4, /* Recommended steady timeout */ \
3245 _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \
3246 cmuOscMode_Crystal, \
3247 }
3248 #endif /* _EFR_DEVICE */
3249 /** Init of HFXO with external clock. */
3250 #define CMU_HFXOINIT_EXTERNAL_CLOCK \
3251 { \
3252 true, /* Low-power mode */ \
3253 false, /* @deprecated no longer in use */ \
3254 false, /* @deprecated no longer in use */ \
3255 false, /* @deprecated no longer in use */ \
3256 0, /* Startup CTUNE=0 recommended for external clock */ \
3257 0, /* Steady CTUNE=0 recommended for external clock */ \
3258 0xA, /* Default shunt steady-state current */ \
3259 0, /* Startup IBTRIMXOCORE=0 recommended for external clock */ \
3260 0, /* Steady IBTRIMXOCORE=0 recommended for external clock */ \
3261 0x6, /* Recommended peak detection threshold */ \
3262 0x2, /* Recommended shunt optimization timeout */ \
3263 0x0, /* Peak-detect not recommended for external clock usage */ \
3264 _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES, /* Minimal steady timeout */ \
3265 _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES, /* Minimal startup timeout */ \
3266 cmuOscMode_External, \
3267 }
3268 #else /* _CMU_HFXOCTRL_MASK */
3269 /**
3270 * Default HFXO initialization values for Platform 1 devices.
3271 */
3272 #define CMU_HFXOINIT_DEFAULT \
3273 { \
3274 _CMU_CTRL_HFXOBOOST_DEFAULT, /* 100% HFXO boost */ \
3275 _CMU_CTRL_HFXOTIMEOUT_DEFAULT, /* 16 K startup delay */ \
3276 false, /* Disable glitch detector */ \
3277 cmuOscMode_Crystal, /* Crystal oscillator */ \
3278 }
3279 /** Default HFXO initialization for external clock */
3280 #define CMU_HFXOINIT_EXTERNAL_CLOCK \
3281 { \
3282 0, /* Minimal HFXO boost, 50% */ \
3283 _CMU_CTRL_HFXOTIMEOUT_8CYCLES, /* Minimal startup delay, 8 cycles */ \
3284 false, /* Disable glitch detector */ \
3285 cmuOscMode_External, /* External digital clock */ \
3286 }
3287 #endif /* _CMU_HFXOCTRL_MASK */
3288
3289 #if defined(CMU_OSCENCMD_DPLLEN)
3290 /** DPLL initialization structure.
3291 * Frequency will be Fref*(N+1)/(M+1). */
3292 typedef struct {
3293 uint32_t frequency; /**< PLL frequency value, max 40 MHz. */
3294 uint16_t n; /**< Factor N. 300 <= N <= 4095 */
3295 uint16_t m; /**< Factor M. M <= 4095 */
3296 uint8_t ssInterval; /**< Spread spectrum update interval. */
3297 uint8_t ssAmplitude; /**< Spread spectrum amplitude. */
3298 CMU_DPLLClkSel_TypeDef refClk; /**< Reference clock selector. */
3299 CMU_DPLLEdgeSel_TypeDef edgeSel; /**< Reference clock edge detect selector. */
3300 CMU_DPLLLockMode_TypeDef lockMode; /**< DPLL lock mode selector. */
3301 bool autoRecover; /**< Enable automatic lock recovery. */
3302 } CMU_DPLLInit_TypeDef;
3303
3304 /**
3305 * DPLL initialization values for 39,998,805 Hz using LFXO as reference
3306 * clock, M=2 and N=3661.
3307 */
3308 #define CMU_DPLL_LFXO_TO_40MHZ \
3309 { \
3310 39998805, /* Target frequency. */ \
3311 3661, /* Factor N. */ \
3312 2, /* Factor M. */ \
3313 0, /* No spread spectrum clocking. */ \
3314 0, /* No spread spectrum clocking. */ \
3315 cmuDPLLClkSel_Lfxo, /* Select LFXO as reference clock. */ \
3316 cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \
3317 cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \
3318 true /* Enable automatic lock recovery. */ \
3319 }
3320 #endif // CMU_OSCENCMD_DPLLEN
3321
3322 /*******************************************************************************
3323 ***************************** PROTOTYPES **********************************
3324 ******************************************************************************/
3325
3326 #if defined(_CMU_AUXHFRCOCTRL_BAND_MASK)
3327 CMU_AUXHFRCOBand_TypeDef CMU_AUXHFRCOBandGet(void);
3328 void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOBand_TypeDef band);
3329
3330 #elif defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK)
3331 CMU_AUXHFRCOFreq_TypeDef CMU_AUXHFRCOBandGet(void);
3332 void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOFreq_TypeDef setFreq);
3333 #endif
3334
3335 uint32_t CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef reference);
3336
3337 #if defined(_CMU_CALCTRL_UPSEL_MASK) && defined(_CMU_CALCTRL_DOWNSEL_MASK)
3338 void CMU_CalibrateConfig(uint32_t downCycles, CMU_Osc_TypeDef downSel,
3339 CMU_Osc_TypeDef upSel);
3340 #endif
3341
3342 uint32_t CMU_CalibrateCountGet(void);
3343 void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable);
3344 CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock);
3345 void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div);
3346 uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock);
3347
3348 #if defined(_SILICON_LABS_32B_SERIES_1)
3349 void CMU_ClockPrescSet(CMU_Clock_TypeDef clock, CMU_ClkPresc_TypeDef presc);
3350 uint32_t CMU_ClockPrescGet(CMU_Clock_TypeDef clock);
3351 #endif
3352
3353 void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref);
3354 CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock);
3355 uint16_t CMU_LF_ClockPrecisionGet(CMU_Clock_TypeDef clock);
3356 uint16_t CMU_HF_ClockPrecisionGet(CMU_Clock_TypeDef clock);
3357
3358 #if defined(CMU_OSCENCMD_DPLLEN)
3359 bool CMU_DPLLLock(const CMU_DPLLInit_TypeDef *init);
3360 #endif
3361 void CMU_FreezeEnable(bool enable);
3362
3363 #if defined(_CMU_HFRCOCTRL_BAND_MASK)
3364 CMU_HFRCOBand_TypeDef CMU_HFRCOBandGet(void);
3365 void CMU_HFRCOBandSet(CMU_HFRCOBand_TypeDef band);
3366
3367 #elif defined(_CMU_HFRCOCTRL_FREQRANGE_MASK)
3368 CMU_HFRCOFreq_TypeDef CMU_HFRCOBandGet(void);
3369 void CMU_HFRCOBandSet(CMU_HFRCOFreq_TypeDef setFreq);
3370 #endif
3371
3372 #if defined(_CMU_HFRCOCTRL_SUDELAY_MASK)
3373 uint32_t CMU_HFRCOStartupDelayGet(void);
3374 void CMU_HFRCOStartupDelaySet(uint32_t delay);
3375 #endif
3376
3377 #if defined(_CMU_USHFRCOCTRL_FREQRANGE_MASK)
3378 CMU_USHFRCOFreq_TypeDef CMU_USHFRCOBandGet(void);
3379 void CMU_USHFRCOBandSet(CMU_USHFRCOFreq_TypeDef setFreq);
3380 uint32_t CMU_USHFRCOFreqGet(void);
3381 #endif
3382
3383 #if defined(_CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK)
3384 void CMU_HFXOAutostartEnable(uint32_t userSel,
3385 bool enEM0EM1Start,
3386 bool enEM0EM1StartSel);
3387 #endif
3388
3389 void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit);
3390
3391 uint32_t CMU_LCDClkFDIVGet(void);
3392 void CMU_LCDClkFDIVSet(uint32_t div);
3393 void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit);
3394 void CMU_LFXOPrecisionSet(uint16_t precision);
3395 uint16_t CMU_LFXOPrecisionGet(void);
3396 void CMU_HFXOPrecisionSet(uint16_t precision);
3397 uint16_t CMU_HFXOPrecisionGet(void);
3398
3399 void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait);
3400 uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc);
3401 void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val);
3402
3403 #if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) || defined(_CMU_HFXOCTRL_PEAKDETMODE_MASK)
3404 bool CMU_OscillatorTuningWait(CMU_Osc_TypeDef osc, CMU_HFXOTuningMode_TypeDef mode);
3405 bool CMU_OscillatorTuningOptimize(CMU_Osc_TypeDef osc,
3406 CMU_HFXOTuningMode_TypeDef mode,
3407 bool wait);
3408 #endif
3409
3410 #if (_SILICON_LABS_32B_SERIES < 2)
3411 void CMU_PCNTClockExternalSet(unsigned int instance, bool external);
3412 bool CMU_PCNTClockExternalGet(unsigned int instance);
3413 #endif
3414
3415 #if defined(_CMU_USHFRCOCONF_BAND_MASK)
3416 CMU_USHFRCOBand_TypeDef CMU_USHFRCOBandGet(void);
3417 void CMU_USHFRCOBandSet(CMU_USHFRCOBand_TypeDef band);
3418 uint32_t CMU_USHFRCOFreqGet(void);
3419 #endif
3420 void CMU_UpdateWaitStates(uint32_t freq, int vscale);
3421
3422 #if defined(CMU_CALCTRL_CONT)
3423 /***************************************************************************//**
3424 * @brief
3425 * Configure continuous calibration mode.
3426 * @param[in] enable
3427 * If true, enables continuous calibration, if false disables continuous
3428 * calibration.
3429 ******************************************************************************/
3430 __STATIC_INLINE void CMU_CalibrateCont(bool enable)
3431 {
3432 BUS_RegBitWrite(&CMU->CALCTRL, _CMU_CALCTRL_CONT_SHIFT, (uint32_t)enable);
3433 }
3434 #endif
3435
3436 /***************************************************************************//**
3437 * @brief
3438 * Start calibration.
3439 * @note
3440 * This call is usually invoked after CMU_CalibrateConfig() and possibly
3441 * CMU_CalibrateCont().
3442 ******************************************************************************/
3443 __STATIC_INLINE void CMU_CalibrateStart(void)
3444 {
3445 CMU->CMD = CMU_CMD_CALSTART;
3446 }
3447
3448 #if defined(CMU_CMD_CALSTOP)
3449 /***************************************************************************//**
3450 * @brief
3451 * Stop the calibration counters.
3452 ******************************************************************************/
3453 __STATIC_INLINE void CMU_CalibrateStop(void)
3454 {
3455 CMU->CMD = CMU_CMD_CALSTOP;
3456 }
3457 #endif
3458
3459 /***************************************************************************//**
3460 * @brief
3461 * Convert divider to logarithmic value. It only works for even
3462 * numbers equal to 2^n.
3463 *
3464 * @param[in] div
3465 * An unscaled divider.
3466 *
3467 * @return
3468 * Logarithm base 2 (binary) value, i.e. exponent as used by fixed
3469 * 2^n prescalers.
3470 ******************************************************************************/
3471 __STATIC_INLINE uint32_t CMU_DivToLog2(CMU_ClkDiv_TypeDef div)
3472 {
3473 uint32_t log2;
3474
3475 /* Fixed 2^n prescalers take argument of 32768 or less. */
3476 EFM_ASSERT((div > 0U) && (div <= 32768U));
3477
3478 /* Count leading zeroes and "reverse" result */
3479 log2 = 31UL - __CLZ(div);
3480
3481 return log2;
3482 }
3483
3484 #if defined(CMU_OSCENCMD_DPLLEN)
3485 /***************************************************************************//**
3486 * @brief
3487 * Unlock DPLL.
3488 * @note
3489 * HFRCO is not turned off.
3490 ******************************************************************************/
3491 __STATIC_INLINE void CMU_DPLLUnlock(void)
3492 {
3493 CMU->OSCENCMD = CMU_OSCENCMD_DPLLDIS;
3494 }
3495 #endif
3496
3497 /***************************************************************************//**
3498 * @brief
3499 * Clear one or more pending CMU interrupts.
3500 *
3501 * @param[in] flags
3502 * CMU interrupt sources to clear.
3503 ******************************************************************************/
3504 __STATIC_INLINE void CMU_IntClear(uint32_t flags)
3505 {
3506 CMU->IFC = flags;
3507 }
3508
3509 /***************************************************************************//**
3510 * @brief
3511 * Disable one or more CMU interrupts.
3512 *
3513 * @param[in] flags
3514 * CMU interrupt sources to disable.
3515 ******************************************************************************/
3516 __STATIC_INLINE void CMU_IntDisable(uint32_t flags)
3517 {
3518 CMU->IEN &= ~flags;
3519 }
3520
3521 /***************************************************************************//**
3522 * @brief
3523 * Enable one or more CMU interrupts.
3524 *
3525 * @note
3526 * Depending on use case, a pending interrupt may already be set prior to
3527 * enabling the interrupt. Consider using @ref CMU_IntClear() prior to enabling
3528 * if the pending interrupt should be ignored.
3529 *
3530 * @param[in] flags
3531 * CMU interrupt sources to enable.
3532 ******************************************************************************/
3533 __STATIC_INLINE void CMU_IntEnable(uint32_t flags)
3534 {
3535 CMU->IEN |= flags;
3536 }
3537
3538 /***************************************************************************//**
3539 * @brief
3540 * Get pending CMU interrupts.
3541 *
3542 * @return
3543 * CMU interrupt sources pending.
3544 ******************************************************************************/
3545 __STATIC_INLINE uint32_t CMU_IntGet(void)
3546 {
3547 return CMU->IF;
3548 }
3549
3550 /***************************************************************************//**
3551 * @brief
3552 * Get enabled and pending CMU interrupt flags.
3553 *
3554 * @details
3555 * Useful for handling more interrupt sources in the same interrupt handler.
3556 *
3557 * @note
3558 * This function does not clear event bits.
3559 *
3560 * @return
3561 * Pending and enabled CMU interrupt sources.
3562 * The return value is the bitwise AND of
3563 * - the enabled interrupt sources in CMU_IEN and
3564 * - the pending interrupt flags CMU_IF
3565 ******************************************************************************/
3566 __STATIC_INLINE uint32_t CMU_IntGetEnabled(void)
3567 {
3568 uint32_t ien;
3569
3570 ien = CMU->IEN;
3571 return CMU->IF & ien;
3572 }
3573
3574 /**************************************************************************//**
3575 * @brief
3576 * Set one or more pending CMU interrupts.
3577 *
3578 * @param[in] flags
3579 * CMU interrupt sources to set to pending.
3580 *****************************************************************************/
3581 __STATIC_INLINE void CMU_IntSet(uint32_t flags)
3582 {
3583 CMU->IFS = flags;
3584 }
3585
3586 /***************************************************************************//**
3587 * @brief
3588 * Lock the CMU to protect some of its registers against unintended
3589 * modification.
3590 *
3591 * @details
3592 * See the reference manual for CMU registers that will be
3593 * locked.
3594 *
3595 * @note
3596 * If locking the CMU registers, they must be unlocked prior to using any
3597 * CMU API functions modifying CMU registers protected by the lock.
3598 ******************************************************************************/
3599 __STATIC_INLINE void CMU_Lock(void)
3600 {
3601 CMU->LOCK = CMU_LOCK_LOCKKEY_LOCK;
3602 }
3603
3604 /***************************************************************************//**
3605 * @brief
3606 * Unlock the CMU so that writing to locked registers again is possible.
3607 ******************************************************************************/
3608 __STATIC_INLINE void CMU_Unlock(void)
3609 {
3610 CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK;
3611 }
3612
3613 #endif // defined(_SILICON_LABS_32B_SERIES_2)
3614
3615 #if !defined(_SILICON_LABS_32B_SERIES_0)
3616 /***************************************************************************//**
3617 * @brief
3618 * Convert prescaler divider to a logarithmic value. It only works for even
3619 * numbers equal to 2^n.
3620 *
3621 * @param[in] presc
3622 * Prescaler value used to set the frequency divider. The divider is equal to
3623 * ('presc' + 1). If a divider value is passed for 'presc', 'presc' will be
3624 * equal to (divider - 1).
3625 *
3626 * @return
3627 * Logarithm base 2 (binary) value, i.e. exponent as used by fixed
3628 * 2^n prescalers.
3629 ******************************************************************************/
CMU_PrescToLog2(uint32_t presc)3630 __STATIC_INLINE uint32_t CMU_PrescToLog2(uint32_t presc)
3631 {
3632 uint32_t log2;
3633
3634 /* Integer prescalers take argument less than 32768. */
3635 EFM_ASSERT(presc < 32768U);
3636
3637 /* Count leading zeroes and "reverse" result. Consider divider value to get
3638 * exponent n from 2^n, so ('presc' +1). */
3639 log2 = 31UL - __CLZ(presc + (uint32_t) 1);
3640
3641 /* Check that prescaler is a 2^n number. */
3642 EFM_ASSERT(presc == (SL_Log2ToDiv(log2) - 1U));
3643
3644 return log2;
3645 }
3646 #endif // !defined(_SILICON_LABS_32B_SERIES_0)
3647
3648 /** @} (end addtogroup cmu) */
3649
3650 #ifdef __cplusplus
3651 }
3652 #endif
3653
3654 #endif /* defined(CMU_PRESENT) */
3655 #endif /* EM_CMU_H */
3656
