1 /**************************************************************************//** 2 * @file 3 * @brief CMSIS Cortex-M Peripheral Access Layer Header File 4 * for EFR32ZG23B020F512IM40 5 ****************************************************************************** 6 * # License 7 * <b>Copyright 2024 Silicon Laboratories, Inc. www.silabs.com</b> 8 ****************************************************************************** 9 * 10 * SPDX-License-Identifier: Zlib 11 * 12 * The licensor of this software is Silicon Laboratories Inc. 13 * 14 * This software is provided 'as-is', without any express or implied 15 * warranty. In no event will the authors be held liable for any damages 16 * arising from the use of this software. 17 * 18 * Permission is granted to anyone to use this software for any purpose, 19 * including commercial applications, and to alter it and redistribute it 20 * freely, subject to the following restrictions: 21 * 22 * 1. The origin of this software must not be misrepresented; you must not 23 * claim that you wrote the original software. If you use this software 24 * in a product, an acknowledgment in the product documentation would be 25 * appreciated but is not required. 26 * 2. Altered source versions must be plainly marked as such, and must not be 27 * misrepresented as being the original software. 28 * 3. This notice may not be removed or altered from any source distribution. 29 * 30 *****************************************************************************/ 31 #ifndef EFR32ZG23B020F512IM40_H 32 #define EFR32ZG23B020F512IM40_H 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 /**************************************************************************//** 39 * @addtogroup Parts 40 * @{ 41 *****************************************************************************/ 42 43 /**************************************************************************//** 44 * @defgroup EFR32ZG23B020F512IM40 EFR32ZG23B020F512IM40 45 * @{ 46 *****************************************************************************/ 47 48 /** Interrupt Number Definition */ 49 typedef enum IRQn{ 50 /****** Cortex-M Processor Exceptions Numbers ******************************************/ 51 NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ 52 HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ 53 MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ 54 BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ 55 UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ 56 #if defined(CONFIG_ARM_SECURE_FIRMWARE) 57 SecureFault_IRQn = -9, 58 #endif 59 SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ 60 DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ 61 PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ 62 SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ 63 64 /****** EFR32ZG23 Peripheral Interrupt Numbers ******************************************/ 65 66 SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ 67 SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ 68 SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ 69 EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ 70 TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ 71 TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ 72 TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ 73 TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ 74 TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ 75 USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ 76 USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ 77 EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ 78 EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ 79 EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ 80 EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ 81 EUSART2_RX_IRQn = 15, /*!< 15 EFR32 EUSART2_RX Interrupt */ 82 EUSART2_TX_IRQn = 16, /*!< 16 EFR32 EUSART2_TX Interrupt */ 83 ICACHE0_IRQn = 17, /*!< 17 EFR32 ICACHE0 Interrupt */ 84 BURTC_IRQn = 18, /*!< 18 EFR32 BURTC Interrupt */ 85 LETIMER0_IRQn = 19, /*!< 19 EFR32 LETIMER0 Interrupt */ 86 SYSCFG_IRQn = 20, /*!< 20 EFR32 SYSCFG Interrupt */ 87 MPAHBRAM_IRQn = 21, /*!< 21 EFR32 MPAHBRAM Interrupt */ 88 LDMA_IRQn = 22, /*!< 22 EFR32 LDMA Interrupt */ 89 LFXO_IRQn = 23, /*!< 23 EFR32 LFXO Interrupt */ 90 LFRCO_IRQn = 24, /*!< 24 EFR32 LFRCO Interrupt */ 91 ULFRCO_IRQn = 25, /*!< 25 EFR32 ULFRCO Interrupt */ 92 GPIO_ODD_IRQn = 26, /*!< 26 EFR32 GPIO_ODD Interrupt */ 93 GPIO_EVEN_IRQn = 27, /*!< 27 EFR32 GPIO_EVEN Interrupt */ 94 I2C0_IRQn = 28, /*!< 28 EFR32 I2C0 Interrupt */ 95 I2C1_IRQn = 29, /*!< 29 EFR32 I2C1 Interrupt */ 96 EMUDG_IRQn = 30, /*!< 30 EFR32 EMUDG Interrupt */ 97 AGC_IRQn = 31, /*!< 31 EFR32 AGC Interrupt */ 98 BUFC_IRQn = 32, /*!< 32 EFR32 BUFC Interrupt */ 99 FRC_PRI_IRQn = 33, /*!< 33 EFR32 FRC_PRI Interrupt */ 100 FRC_IRQn = 34, /*!< 34 EFR32 FRC Interrupt */ 101 MODEM_IRQn = 35, /*!< 35 EFR32 MODEM Interrupt */ 102 PROTIMER_IRQn = 36, /*!< 36 EFR32 PROTIMER Interrupt */ 103 RAC_RSM_IRQn = 37, /*!< 37 EFR32 RAC_RSM Interrupt */ 104 RAC_SEQ_IRQn = 38, /*!< 38 EFR32 RAC_SEQ Interrupt */ 105 HOSTMAILBOX_IRQn = 39, /*!< 39 EFR32 HOSTMAILBOX Interrupt */ 106 SYNTH_IRQn = 40, /*!< 40 EFR32 SYNTH Interrupt */ 107 ACMP0_IRQn = 41, /*!< 41 EFR32 ACMP0 Interrupt */ 108 ACMP1_IRQn = 42, /*!< 42 EFR32 ACMP1 Interrupt */ 109 WDOG0_IRQn = 43, /*!< 43 EFR32 WDOG0 Interrupt */ 110 WDOG1_IRQn = 44, /*!< 44 EFR32 WDOG1 Interrupt */ 111 HFXO0_IRQn = 45, /*!< 45 EFR32 HFXO0 Interrupt */ 112 HFRCO0_IRQn = 46, /*!< 46 EFR32 HFRCO0 Interrupt */ 113 HFRCOEM23_IRQn = 47, /*!< 47 EFR32 HFRCOEM23 Interrupt */ 114 CMU_IRQn = 48, /*!< 48 EFR32 CMU Interrupt */ 115 AES_IRQn = 49, /*!< 49 EFR32 AES Interrupt */ 116 IADC_IRQn = 50, /*!< 50 EFR32 IADC Interrupt */ 117 MSC_IRQn = 51, /*!< 51 EFR32 MSC Interrupt */ 118 DPLL0_IRQn = 52, /*!< 52 EFR32 DPLL0 Interrupt */ 119 EMUEFP_IRQn = 53, /*!< 53 EFR32 EMUEFP Interrupt */ 120 DCDC_IRQn = 54, /*!< 54 EFR32 DCDC Interrupt */ 121 VDAC_IRQn = 55, /*!< 55 EFR32 VDAC Interrupt */ 122 PCNT0_IRQn = 56, /*!< 56 EFR32 PCNT0 Interrupt */ 123 SW0_IRQn = 57, /*!< 57 EFR32 SW0 Interrupt */ 124 SW1_IRQn = 58, /*!< 58 EFR32 SW1 Interrupt */ 125 SW2_IRQn = 59, /*!< 59 EFR32 SW2 Interrupt */ 126 SW3_IRQn = 60, /*!< 60 EFR32 SW3 Interrupt */ 127 KERNEL0_IRQn = 61, /*!< 61 EFR32 KERNEL0 Interrupt */ 128 KERNEL1_IRQn = 62, /*!< 62 EFR32 KERNEL1 Interrupt */ 129 M33CTI0_IRQn = 63, /*!< 63 EFR32 M33CTI0 Interrupt */ 130 M33CTI1_IRQn = 64, /*!< 64 EFR32 M33CTI1 Interrupt */ 131 FPUEXH_IRQn = 65, /*!< 65 EFR32 FPUEXH Interrupt */ 132 SETAMPERHOST_IRQn = 66, /*!< 66 EFR32 SETAMPERHOST Interrupt */ 133 SEMBRX_IRQn = 67, /*!< 67 EFR32 SEMBRX Interrupt */ 134 SEMBTX_IRQn = 68, /*!< 68 EFR32 SEMBTX Interrupt */ 135 LESENSE_IRQn = 69, /*!< 69 EFR32 LESENSE Interrupt */ 136 SYSRTC_APP_IRQn = 70, /*!< 70 EFR32 SYSRTC_APP Interrupt */ 137 SYSRTC_SEQ_IRQn = 71, /*!< 71 EFR32 SYSRTC_SEQ Interrupt */ 138 KEYSCAN_IRQn = 73, /*!< 73 EFR32 KEYSCAN Interrupt */ 139 RFECA0_IRQn = 74, /*!< 74 EFR32 RFECA0 Interrupt */ 140 RFECA1_IRQn = 75, /*!< 75 EFR32 RFECA1 Interrupt */ 141 } IRQn_Type; 142 143 /**************************************************************************//** 144 * @defgroup EFR32ZG23B020F512IM40_Core EFR32ZG23B020F512IM40 Core 145 * @{ 146 * @brief Processor and Core Peripheral Section 147 *****************************************************************************/ 148 149 #define __CORTEXM 1U /**< Core architecture */ 150 #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ 151 #define __DSP_PRESENT 1U /**< Presence of DSP */ 152 #define __FPU_PRESENT 1U /**< Presence of FPU */ 153 #define __MPU_PRESENT 1U /**< Presence of MPU */ 154 #define __SAUREGION_PRESENT 1U /**< Presence of FPU */ 155 #define __TZ_PRESENT 1U /**< Presence of TrustZone */ 156 #define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ 157 #define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ 158 #define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ 159 160 /** @} End of group EFR32ZG23B020F512IM40_Core */ 161 162 /**************************************************************************//** 163 * @defgroup EFR32ZG23B020F512IM40_Part EFR32ZG23B020F512IM40 Part 164 * @{ 165 ******************************************************************************/ 166 167 /** Part number */ 168 169 /* If part number is not defined as compiler option, define it */ 170 #if !defined(EFR32ZG23B020F512IM40) 171 #define EFR32ZG23B020F512IM40 1 /**< FULL Part */ 172 #endif 173 174 /** Configure part number */ 175 #define PART_NUMBER "EFR32ZG23B020F512IM40" /**< Part Number */ 176 177 /** Family / Line / Series / Config */ 178 #define _EFR32_ZWAVE_FAMILY 1 /** Device Family Name Identifier */ 179 #define _EFR32_ZG_FAMILY 1 /** Device Family Identifier */ 180 #define _EFR_DEVICE 1 /** Product Line Identifier */ 181 #define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ 182 #define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ 183 #define _SILICON_LABS_32B_SERIES_2_CONFIG_3 /** Product Config Identifier */ 184 #define _SILICON_LABS_32B_SERIES_2_CONFIG 3 /** Product Config Identifier */ 185 #define _SILICON_LABS_GECKO_INTERNAL_SDID 210 /** Silicon Labs internal use only */ 186 #define _SILICON_LABS_GECKO_INTERNAL_SDID_210 /** Silicon Labs internal use only */ 187 #define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ 188 #define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ 189 #define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root of Trust */ 190 #define _SILICON_LABS_SECURITY_FEATURE_BASE 3 /** Base */ 191 #define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */ 192 #define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ 193 #define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ 194 #define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ 195 #define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ 196 #define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ 197 #define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ 198 #define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ 199 #define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ 200 #define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ 201 #define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_SUBGHZ /** Radio type */ 202 #define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio SUBGHZ HP PA output power */ 203 #define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_PRESENT /** Radio SUBGHZ HP PA is present */ 204 205 /** Memory Base addresses and limits */ 206 #define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ 207 #define FLASH_MEM_SIZE (0x00080000UL) /** FLASH_MEM available address space */ 208 #define FLASH_MEM_END (0x0807FFFFUL) /** FLASH_MEM end address */ 209 #define FLASH_MEM_BITS (0x14UL) /** FLASH_MEM used bits */ 210 #define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ 211 #define MSC_FLASH_MEM_SIZE (0x00080000UL) /** MSC_FLASH_MEM available address space */ 212 #define MSC_FLASH_MEM_END (0x0807FFFFUL) /** MSC_FLASH_MEM end address */ 213 #define MSC_FLASH_MEM_BITS (0x14UL) /** MSC_FLASH_MEM used bits */ 214 #define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ 215 #define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ 216 #define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ 217 #define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ 218 #define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ 219 #define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ 220 #define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ 221 #define USERDATA_BITS (0xBUL) /** USERDATA used bits */ 222 #define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ 223 #define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ 224 #define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ 225 #define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ 226 #define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ 227 #define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ 228 #define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ 229 #define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ 230 #define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ 231 #define DMEM_RAM0_RAM_MEM_SIZE (0x00010000UL) /** DMEM_RAM0_RAM_MEM available address space */ 232 #define DMEM_RAM0_RAM_MEM_END (0x2000FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ 233 #define DMEM_RAM0_RAM_MEM_BITS (0x11UL) /** DMEM_RAM0_RAM_MEM used bits */ 234 #define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ 235 #define RAM_MEM_SIZE (0x00010000UL) /** RAM_MEM available address space */ 236 #define RAM_MEM_END (0x2000FFFFUL) /** RAM_MEM end address */ 237 #define RAM_MEM_BITS (0x11UL) /** RAM_MEM used bits */ 238 #define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ 239 #define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ 240 #define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ 241 #define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ 242 #define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ 243 #define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ 244 #define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ 245 #define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ 246 #define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ 247 #define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ 248 #define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ 249 #define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ 250 #define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ 251 #define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ 252 #define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ 253 #define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ 254 #define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ 255 #define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ 256 #define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ 257 #define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ 258 #define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ 259 #define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ 260 #define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ 261 #define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ 262 263 /** Flash and SRAM limits for EFR32ZG23B020F512IM40 */ 264 #define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ 265 #define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */ 266 #define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ 267 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ 268 #define SRAM_SIZE (0x00010000UL) /**< Available SRAM Memory */ 269 #define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ 270 #define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ 271 272 /* GPIO Avalibility Info */ 273 #define GPIO_PA_INDEX 0U /**< Index of port PA */ 274 #define GPIO_PA_COUNT 9U /**< Number of pins on port PA */ 275 #define GPIO_PA_MASK (0x01FFUL) /**< Port PA pin mask */ 276 #define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ 277 #define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ 278 #define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ 279 #define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ 280 #define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ 281 #define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ 282 #define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ 283 #define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ 284 #define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ 285 #define GPIO_PB_INDEX 1U /**< Index of port PB */ 286 #define GPIO_PB_COUNT 2U /**< Number of pins on port PB */ 287 #define GPIO_PB_MASK (0x0003UL) /**< Port PB pin mask */ 288 #define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ 289 #define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ 290 #define GPIO_PC_INDEX 2U /**< Index of port PC */ 291 #define GPIO_PC_COUNT 8U /**< Number of pins on port PC */ 292 #define GPIO_PC_MASK (0x00FFUL) /**< Port PC pin mask */ 293 #define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ 294 #define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ 295 #define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ 296 #define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ 297 #define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ 298 #define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ 299 #define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ 300 #define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ 301 #define GPIO_PD_INDEX 3U /**< Index of port PD */ 302 #define GPIO_PD_COUNT 4U /**< Number of pins on port PD */ 303 #define GPIO_PD_MASK (0x000FUL) /**< Port PD pin mask */ 304 #define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ 305 #define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ 306 #define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ 307 #define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ 308 309 /* Fixed Resource Locations */ 310 #define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ 311 #define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ 312 #define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ 313 #define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ 314 #define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ 315 #define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ 316 #define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ 317 #define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ 318 #define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ 319 #define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ 320 #define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ 321 #define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ 322 #define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ 323 #define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ 324 #define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ 325 #define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ 326 #define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ 327 #define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ 328 #define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ 329 #define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ 330 #define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ 331 #define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ 332 #define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ 333 #define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ 334 #define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ 335 #define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ 336 #define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ 337 #define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ 338 #define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ 339 #define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ 340 #define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ 341 #define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ 342 #define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ 343 #define GPIO_THMSW_EN_PIN 7U /**< Pin of THMSW_EN.*/ 344 #define GPIO_THMSW_EN_PRIMARY_PORT GPIO_PC_INDEX /**< Port of THMSW_EN_PRIMARY.*/ 345 #define GPIO_THMSW_EN_PRIMARY_PIN 9U /**< Pin of THMSW_EN_PRIMARY.*/ 346 #define IADC0_VREFP_PORT GPIO_PA_INDEX /**< Port of VREFP.*/ 347 #define IADC0_VREFP_PIN 0U /**< Pin of VREFP.*/ 348 #define LESENSE_EN_0_PORT GPIO_PA_INDEX /**< Port of EN_0.*/ 349 #define LESENSE_EN_0_PIN 3U /**< Pin of EN_0.*/ 350 #define LESENSE_EN_1_PORT GPIO_PA_INDEX /**< Port of EN_1.*/ 351 #define LESENSE_EN_1_PIN 4U /**< Pin of EN_1.*/ 352 #define LESENSE_EN_2_PORT GPIO_PA_INDEX /**< Port of EN_2.*/ 353 #define LESENSE_EN_2_PIN 5U /**< Pin of EN_2.*/ 354 #define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ 355 #define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ 356 #define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ 357 #define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ 358 #define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ 359 #define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ 360 #define VDAC0_CH0_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH0_MAIN_OUT.*/ 361 #define VDAC0_CH0_MAIN_OUT_PIN 0U /**< Pin of CH0_MAIN_OUT.*/ 362 #define VDAC0_CH1_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH1_MAIN_OUT.*/ 363 #define VDAC0_CH1_MAIN_OUT_PIN 1U /**< Pin of CH1_MAIN_OUT.*/ 364 365 /* Part number capabilities */ 366 #define ACMP_PRESENT /** ACMP is available in this part */ 367 #define ACMP_COUNT 2 /** 2 ACMPs available */ 368 #define BURAM_PRESENT /** BURAM is available in this part */ 369 #define BURAM_COUNT 1 /** 1 BURAMs available */ 370 #define BURTC_PRESENT /** BURTC is available in this part */ 371 #define BURTC_COUNT 1 /** 1 BURTCs available */ 372 #define CMU_PRESENT /** CMU is available in this part */ 373 #define CMU_COUNT 1 /** 1 CMUs available */ 374 #define DCDC_PRESENT /** DCDC is available in this part */ 375 #define DCDC_COUNT 1 /** 1 DCDCs available */ 376 #define DMEM_PRESENT /** DMEM is available in this part */ 377 #define DMEM_COUNT 1 /** 1 DMEMs available */ 378 #define DPLL_PRESENT /** DPLL is available in this part */ 379 #define DPLL_COUNT 1 /** 1 DPLLs available */ 380 #define EMU_PRESENT /** EMU is available in this part */ 381 #define EMU_COUNT 1 /** 1 EMUs available */ 382 #define EUSART_PRESENT /** EUSART is available in this part */ 383 #define EUSART_COUNT 3 /** 3 EUSARTs available */ 384 #define FSRCO_PRESENT /** FSRCO is available in this part */ 385 #define FSRCO_COUNT 1 /** 1 FSRCOs available */ 386 #define GPCRC_PRESENT /** GPCRC is available in this part */ 387 #define GPCRC_COUNT 1 /** 1 GPCRCs available */ 388 #define GPIO_PRESENT /** GPIO is available in this part */ 389 #define GPIO_COUNT 1 /** 1 GPIOs available */ 390 #define HFRCO_PRESENT /** HFRCO is available in this part */ 391 #define HFRCO_COUNT 1 /** 1 HFRCOs available */ 392 #define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ 393 #define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ 394 #define HFXO_PRESENT /** HFXO is available in this part */ 395 #define HFXO_COUNT 1 /** 1 HFXOs available */ 396 #define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ 397 #define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ 398 #define I2C_PRESENT /** I2C is available in this part */ 399 #define I2C_COUNT 2 /** 2 I2Cs available */ 400 #define IADC_PRESENT /** IADC is available in this part */ 401 #define IADC_COUNT 1 /** 1 IADCs available */ 402 #define ICACHE_PRESENT /** ICACHE is available in this part */ 403 #define ICACHE_COUNT 1 /** 1 ICACHEs available */ 404 #define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ 405 #define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ 406 #define LDMA_PRESENT /** LDMA is available in this part */ 407 #define LDMA_COUNT 1 /** 1 LDMAs available */ 408 #define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ 409 #define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ 410 #define LESENSE_PRESENT /** LESENSE is available in this part */ 411 #define LESENSE_COUNT 1 /** 1 LESENSEs available */ 412 #define LETIMER_PRESENT /** LETIMER is available in this part */ 413 #define LETIMER_COUNT 1 /** 1 LETIMERs available */ 414 #define LFRCO_PRESENT /** LFRCO is available in this part */ 415 #define LFRCO_COUNT 1 /** 1 LFRCOs available */ 416 #define LFXO_PRESENT /** LFXO is available in this part */ 417 #define LFXO_COUNT 1 /** 1 LFXOs available */ 418 #define MSC_PRESENT /** MSC is available in this part */ 419 #define MSC_COUNT 1 /** 1 MSCs available */ 420 #define PCNT_PRESENT /** PCNT is available in this part */ 421 #define PCNT_COUNT 1 /** 1 PCNTs available */ 422 #define PFMXPPRF_PRESENT /** PFMXPPRF is available in this part */ 423 #define PFMXPPRF_COUNT 1 /** 1 PFMXPPRFs available */ 424 #define PRS_PRESENT /** PRS is available in this part */ 425 #define PRS_COUNT 1 /** 1 PRSs available */ 426 #define RADIOAES_PRESENT /** RADIOAES is available in this part */ 427 #define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ 428 #define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ 429 #define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ 430 #define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ 431 #define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ 432 #define SMU_PRESENT /** SMU is available in this part */ 433 #define SMU_COUNT 1 /** 1 SMUs available */ 434 #define SYSCFG_PRESENT /** SYSCFG is available in this part */ 435 #define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ 436 #define SYSRTC_PRESENT /** SYSRTC is available in this part */ 437 #define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ 438 #define TIMER_PRESENT /** TIMER is available in this part */ 439 #define TIMER_COUNT 5 /** 5 TIMERs available */ 440 #define ULFRCO_PRESENT /** ULFRCO is available in this part */ 441 #define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ 442 #define USART_PRESENT /** USART is available in this part */ 443 #define USART_COUNT 1 /** 1 USARTs available */ 444 #define VDAC_PRESENT /** VDAC is available in this part */ 445 #define VDAC_COUNT 1 /** 1 VDACs available */ 446 #define WDOG_PRESENT /** WDOG is available in this part */ 447 #define WDOG_COUNT 2 /** 2 WDOGs available */ 448 #define DEVINFO_PRESENT /** DEVINFO is available in this part */ 449 #define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ 450 451 /* Include standard ARM headers for the core */ 452 #include "core_cm33.h" /* Core Header File */ 453 #include "system_efr32zg23.h" /* System Header File */ 454 455 /** @} End of group EFR32ZG23B020F512IM40_Part */ 456 457 /**************************************************************************//** 458 * @defgroup EFR32ZG23B020F512IM40_Peripheral_TypeDefs EFR32ZG23B020F512IM40 Peripheral TypeDefs 459 * @{ 460 * @brief Device Specific Peripheral Register Structures 461 *****************************************************************************/ 462 #include "efr32zg23_scratchpad.h" 463 #include "efr32zg23_emu.h" 464 #include "efr32zg23_cmu.h" 465 #include "efr32zg23_hfrco.h" 466 #include "efr32zg23_fsrco.h" 467 #include "efr32zg23_dpll.h" 468 #include "efr32zg23_lfxo.h" 469 #include "efr32zg23_lfrco.h" 470 #include "efr32zg23_ulfrco.h" 471 #include "efr32zg23_msc.h" 472 #include "efr32zg23_icache.h" 473 #include "efr32zg23_prs.h" 474 #include "efr32zg23_gpio.h" 475 #include "efr32zg23_ldma.h" 476 #include "efr32zg23_ldmaxbar.h" 477 #include "efr32zg23_timer.h" 478 #include "efr32zg23_usart.h" 479 #include "efr32zg23_burtc.h" 480 #include "efr32zg23_i2c.h" 481 #include "efr32zg23_syscfg.h" 482 #include "efr32zg23_buram.h" 483 #include "efr32zg23_gpcrc.h" 484 #include "efr32zg23_dcdc.h" 485 #include "efr32zg23_mailbox.h" 486 #include "efr32zg23_eusart.h" 487 #include "efr32zg23_sysrtc.h" 488 #include "efr32zg23_keyscan.h" 489 #include "efr32zg23_mpahbram.h" 490 #include "efr32zg23_pfmxpprf.h" 491 #include "efr32zg23_aes.h" 492 #include "efr32zg23_smu.h" 493 #include "efr32zg23_letimer.h" 494 #include "efr32zg23_iadc.h" 495 #include "efr32zg23_acmp.h" 496 #include "efr32zg23_vdac.h" 497 #include "efr32zg23_pcnt.h" 498 #include "efr32zg23_lesense.h" 499 #include "efr32zg23_hfxo.h" 500 #include "efr32zg23_wdog.h" 501 #include "efr32zg23_semailbox.h" 502 #include "efr32zg23_devinfo.h" 503 504 /* Custom headers for LDMAXBAR and PRS mappings */ 505 #include "efr32zg23_prs_signals.h" 506 #include "efr32zg23_dma_descriptor.h" 507 #include "efr32zg23_ldmaxbar_defines.h" 508 509 /** @} End of group EFR32ZG23B020F512IM40_Peripheral_TypeDefs */ 510 511 /**************************************************************************//** 512 * @defgroup EFR32ZG23B020F512IM40_Peripheral_Base EFR32ZG23B020F512IM40 Peripheral Memory Map 513 * @{ 514 *****************************************************************************/ 515 516 #define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ 517 #define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ 518 #define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ 519 #define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ 520 #define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ 521 #define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ 522 #define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ 523 #define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ 524 #define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ 525 #define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ 526 #define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ 527 #define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ 528 #define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ 529 #define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ 530 #define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ 531 #define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ 532 #define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ 533 #define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ 534 #define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ 535 #define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ 536 #define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ 537 #define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ 538 #define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ 539 #define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ 540 #define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ 541 #define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ 542 #define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ 543 #define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ 544 #define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ 545 #define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ 546 #define EUSART2_S_BASE (0x400A4000UL) /* EUSART2_S base address */ 547 #define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ 548 #define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ 549 #define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ 550 #define PFMXPPRF_S_BASE (0x400C4000UL) /* PFMXPPRF_S base address */ 551 #define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ 552 #define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ 553 #define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ 554 #define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ 555 #define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ 556 #define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ 557 #define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ 558 #define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ 559 #define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ 560 #define LESENSE_S_BASE (0x49038000UL) /* LESENSE_S base address */ 561 #define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ 562 #define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ 563 #define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ 564 #define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ 565 #define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ 566 #define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ 567 #define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ 568 #define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ 569 #define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ 570 #define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ 571 #define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ 572 #define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ 573 #define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ 574 #define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ 575 #define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ 576 #define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ 577 #define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ 578 #define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ 579 #define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ 580 #define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ 581 #define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ 582 #define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ 583 #define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ 584 #define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ 585 #define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ 586 #define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ 587 #define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ 588 #define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ 589 #define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ 590 #define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ 591 #define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ 592 #define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ 593 #define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ 594 #define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ 595 #define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ 596 #define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ 597 #define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ 598 #define EUSART2_NS_BASE (0x500A4000UL) /* EUSART2_NS base address */ 599 #define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ 600 #define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ 601 #define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ 602 #define PFMXPPRF_NS_BASE (0x500C4000UL) /* PFMXPPRF_NS base address */ 603 #define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ 604 #define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ 605 #define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ 606 #define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ 607 #define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ 608 #define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ 609 #define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ 610 #define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ 611 #define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ 612 #define LESENSE_NS_BASE (0x59038000UL) /* LESENSE_NS base address */ 613 #define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ 614 #define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ 615 #define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ 616 #define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ 617 #define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ 618 #define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ 619 #define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ 620 621 #if defined(SL_COMPONENT_CATALOG_PRESENT) 622 #include "sl_component_catalog.h" 623 624 #endif 625 #if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) 626 #include "sl_trustzone_secure_config.h" 627 628 #endif 629 630 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) 631 #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ 632 #else 633 #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ 634 #endif // SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S 635 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) 636 #define EMU_BASE (EMU_S_BASE) /* EMU base address */ 637 #else 638 #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ 639 #endif // SL_TRUSTZONE_PERIPHERAL_EMU_S 640 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) 641 #define CMU_BASE (CMU_S_BASE) /* CMU base address */ 642 #else 643 #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ 644 #endif // SL_TRUSTZONE_PERIPHERAL_CMU_S 645 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) 646 #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ 647 #else 648 #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ 649 #endif // SL_TRUSTZONE_PERIPHERAL_HFRCO0_S 650 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) 651 #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ 652 #else 653 #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ 654 #endif // SL_TRUSTZONE_PERIPHERAL_FSRCO_S 655 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) 656 #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ 657 #else 658 #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ 659 #endif // SL_TRUSTZONE_PERIPHERAL_DPLL0_S 660 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) 661 #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ 662 #else 663 #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ 664 #endif // SL_TRUSTZONE_PERIPHERAL_LFXO_S 665 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) 666 #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ 667 #else 668 #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ 669 #endif // SL_TRUSTZONE_PERIPHERAL_LFRCO_S 670 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) 671 #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ 672 #else 673 #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ 674 #endif // SL_TRUSTZONE_PERIPHERAL_ULFRCO_S 675 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) 676 #define MSC_BASE (MSC_S_BASE) /* MSC base address */ 677 #else 678 #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ 679 #endif // SL_TRUSTZONE_PERIPHERAL_MSC_S 680 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) 681 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ 682 #else 683 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ 684 #endif // SL_TRUSTZONE_PERIPHERAL_ICACHE0_S 685 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) 686 #define PRS_BASE (PRS_S_BASE) /* PRS base address */ 687 #else 688 #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ 689 #endif // SL_TRUSTZONE_PERIPHERAL_PRS_S 690 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) 691 #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ 692 #else 693 #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ 694 #endif // SL_TRUSTZONE_PERIPHERAL_GPIO_S 695 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) 696 #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ 697 #else 698 #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ 699 #endif // SL_TRUSTZONE_PERIPHERAL_LDMA_S 700 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) 701 #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ 702 #else 703 #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ 704 #endif // SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S 705 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) 706 #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ 707 #else 708 #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ 709 #endif // SL_TRUSTZONE_PERIPHERAL_TIMER0_S 710 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) 711 #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ 712 #else 713 #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ 714 #endif // SL_TRUSTZONE_PERIPHERAL_TIMER1_S 715 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) 716 #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ 717 #else 718 #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ 719 #endif // SL_TRUSTZONE_PERIPHERAL_TIMER2_S 720 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) 721 #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ 722 #else 723 #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ 724 #endif // SL_TRUSTZONE_PERIPHERAL_TIMER3_S 725 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) 726 #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ 727 #else 728 #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ 729 #endif // SL_TRUSTZONE_PERIPHERAL_TIMER4_S 730 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) 731 #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ 732 #else 733 #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ 734 #endif // SL_TRUSTZONE_PERIPHERAL_USART0_S 735 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) 736 #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ 737 #else 738 #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ 739 #endif // SL_TRUSTZONE_PERIPHERAL_BURTC_S 740 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) 741 #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ 742 #else 743 #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ 744 #endif // SL_TRUSTZONE_PERIPHERAL_I2C1_S 745 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) 746 #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ 747 #else 748 #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ 749 #endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S 750 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) 751 #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ 752 #else 753 #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ 754 #endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_S 755 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) 756 #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ 757 #else 758 #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ 759 #endif // SL_TRUSTZONE_PERIPHERAL_BURAM_S 760 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) 761 #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ 762 #else 763 #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ 764 #endif // SL_TRUSTZONE_PERIPHERAL_GPCRC_S 765 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) 766 #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ 767 #else 768 #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ 769 #endif // SL_TRUSTZONE_PERIPHERAL_DCDC_S 770 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) 771 #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ 772 #else 773 #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ 774 #endif // SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S 775 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) 776 #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ 777 #else 778 #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ 779 #endif // SL_TRUSTZONE_PERIPHERAL_EUSART1_S 780 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) 781 #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ 782 #else 783 #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ 784 #endif // SL_TRUSTZONE_PERIPHERAL_EUSART2_S 785 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) 786 #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ 787 #else 788 #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ 789 #endif // SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S 790 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) 791 #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ 792 #else 793 #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ 794 #endif // SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S 795 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) 796 #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ 797 #else 798 #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ 799 #endif // SL_TRUSTZONE_PERIPHERAL_DMEM_S 800 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) 801 #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ 802 #else 803 #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ 804 #endif // SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S 805 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) 806 #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ 807 #else 808 #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ 809 #endif // SL_TRUSTZONE_PERIPHERAL_RADIOAES_S 810 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) 811 #define SMU_BASE (SMU_S_BASE) /* SMU base address */ 812 #else 813 #define SMU_BASE (SMU_S_BASE) /* SMU base address */ 814 #endif // SL_TRUSTZONE_PERIPHERAL_SMU_S 815 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) 816 #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ 817 #else 818 #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ 819 #endif // SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S 820 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) 821 #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ 822 #else 823 #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ 824 #endif // SL_TRUSTZONE_PERIPHERAL_LETIMER0_S 825 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) 826 #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ 827 #else 828 #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ 829 #endif // SL_TRUSTZONE_PERIPHERAL_IADC0_S 830 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) 831 #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ 832 #else 833 #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ 834 #endif // SL_TRUSTZONE_PERIPHERAL_ACMP0_S 835 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) 836 #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ 837 #else 838 #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ 839 #endif // SL_TRUSTZONE_PERIPHERAL_ACMP1_S 840 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) 841 #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ 842 #else 843 #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ 844 #endif // SL_TRUSTZONE_PERIPHERAL_VDAC0_S 845 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) 846 #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ 847 #else 848 #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ 849 #endif // SL_TRUSTZONE_PERIPHERAL_PCNT0_S 850 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) 851 #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ 852 #else 853 #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ 854 #endif // SL_TRUSTZONE_PERIPHERAL_LESENSE_S 855 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) 856 #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ 857 #else 858 #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ 859 #endif // SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S 860 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) 861 #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ 862 #else 863 #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ 864 #endif // SL_TRUSTZONE_PERIPHERAL_HFXO0_S 865 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) 866 #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ 867 #else 868 #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ 869 #endif // SL_TRUSTZONE_PERIPHERAL_I2C0_S 870 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) 871 #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ 872 #else 873 #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ 874 #endif // SL_TRUSTZONE_PERIPHERAL_WDOG0_S 875 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) 876 #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ 877 #else 878 #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ 879 #endif // SL_TRUSTZONE_PERIPHERAL_WDOG1_S 880 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) 881 #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ 882 #else 883 #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ 884 #endif // SL_TRUSTZONE_PERIPHERAL_EUSART0_S 885 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) 886 #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ 887 #else 888 #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ 889 #endif // SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S 890 891 #define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ 892 /** @} End of group EFR32ZG23B020F512IM40_Peripheral_Base */ 893 894 /**************************************************************************//** 895 * @defgroup EFR32ZG23B020F512IM40_Peripheral_Declaration EFR32ZG23B020F512IM40 Peripheral Declarations Map 896 * @{ 897 *****************************************************************************/ 898 899 #define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ 900 #define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ 901 #define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ 902 #define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ 903 #define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ 904 #define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ 905 #define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ 906 #define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ 907 #define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ 908 #define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ 909 #define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ 910 #define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ 911 #define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ 912 #define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ 913 #define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ 914 #define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ 915 #define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ 916 #define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ 917 #define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ 918 #define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ 919 #define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ 920 #define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ 921 #define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ 922 #define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ 923 #define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ 924 #define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ 925 #define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ 926 #define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ 927 #define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ 928 #define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ 929 #define EUSART2_S ((EUSART_TypeDef *) EUSART2_S_BASE) /**< EUSART2_S base pointer */ 930 #define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ 931 #define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ 932 #define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ 933 #define PFMXPPRF_S ((PFMXPPRF_TypeDef *) PFMXPPRF_S_BASE) /**< PFMXPPRF_S base pointer */ 934 #define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ 935 #define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ 936 #define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ 937 #define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ 938 #define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ 939 #define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ 940 #define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ 941 #define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ 942 #define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ 943 #define LESENSE_S ((LESENSE_TypeDef *) LESENSE_S_BASE) /**< LESENSE_S base pointer */ 944 #define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ 945 #define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ 946 #define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ 947 #define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ 948 #define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ 949 #define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ 950 #define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ 951 #define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ 952 #define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ 953 #define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ 954 #define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ 955 #define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ 956 #define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ 957 #define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ 958 #define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ 959 #define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ 960 #define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ 961 #define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ 962 #define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ 963 #define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ 964 #define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ 965 #define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ 966 #define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ 967 #define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ 968 #define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ 969 #define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ 970 #define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ 971 #define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ 972 #define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ 973 #define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ 974 #define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ 975 #define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ 976 #define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ 977 #define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ 978 #define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ 979 #define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ 980 #define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ 981 #define EUSART2_NS ((EUSART_TypeDef *) EUSART2_NS_BASE) /**< EUSART2_NS base pointer */ 982 #define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ 983 #define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ 984 #define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ 985 #define PFMXPPRF_NS ((PFMXPPRF_TypeDef *) PFMXPPRF_NS_BASE) /**< PFMXPPRF_NS base pointer */ 986 #define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ 987 #define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ 988 #define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ 989 #define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ 990 #define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ 991 #define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ 992 #define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ 993 #define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ 994 #define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ 995 #define LESENSE_NS ((LESENSE_TypeDef *) LESENSE_NS_BASE) /**< LESENSE_NS base pointer */ 996 #define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ 997 #define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ 998 #define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ 999 #define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ 1000 #define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ 1001 #define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ 1002 #define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ 1003 #define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ 1004 #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ 1005 #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ 1006 #define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ 1007 #define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ 1008 #define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ 1009 #define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ 1010 #define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ 1011 #define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ 1012 #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ 1013 #define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ 1014 #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ 1015 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ 1016 #define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ 1017 #define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ 1018 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ 1019 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ 1020 #define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ 1021 #define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ 1022 #define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ 1023 #define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ 1024 #define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ 1025 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ 1026 #define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ 1027 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ 1028 #define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ 1029 #define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ 1030 #define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ 1031 #define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ 1032 #define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ 1033 #define EUSART2 ((EUSART_TypeDef *) EUSART2_BASE) /**< EUSART2 base pointer */ 1034 #define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ 1035 #define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ 1036 #define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ 1037 #define PFMXPPRF ((PFMXPPRF_TypeDef *) PFMXPPRF_BASE) /**< PFMXPPRF base pointer */ 1038 #define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ 1039 #define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ 1040 #define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ 1041 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ 1042 #define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ 1043 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ 1044 #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ 1045 #define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ 1046 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ 1047 #define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ 1048 #define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ 1049 #define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ 1050 #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ 1051 #define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ 1052 #define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ 1053 #define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ 1054 #define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ 1055 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ 1056 /** @} End of group EFR32ZG23B020F512IM40_Peripheral_Declaration */ 1057 1058 /**************************************************************************//** 1059 * @defgroup EFR32ZG23B020F512IM40_Peripheral_Parameters EFR32ZG23B020F512IM40 Peripheral Parameters 1060 * @{ 1061 * @brief Device peripheral parameter values 1062 *****************************************************************************/ 1063 1064 /* Common peripheral register block offsets. */ 1065 #define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ 1066 #define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ 1067 #define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ 1068 #define MSC_CDA_PRESENT 0x0UL /**> */ 1069 #define MSC_FDIO_WIDTH 0x40UL /**> None */ 1070 #define MSC_FLASHADDRBITS 0x14UL /**> None */ 1071 #define MSC_FLASHBLOCKADDRBITS 0x14UL /**> None */ 1072 #define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ 1073 #define MSC_FLASH_BLOCK_MAIN_PCOUNT 0x50UL /**> */ 1074 #define MSC_INFOADDRBITS 0xEUL /**> None */ 1075 #define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ 1076 #define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ 1077 #define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ 1078 #define MSC_REDUNDANCY 0x2UL /**> None */ 1079 #define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ 1080 #define MSC_UD_PRESENT 0x1UL /**> */ 1081 #define MSC_YADDRBITS 0x6UL /**> */ 1082 #define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ 1083 #define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ 1084 #define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ 1085 #define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ 1086 #define DMEM_BANK4_SIZE 0x2000UL /**> Bank4 size */ 1087 #define DMEM_BANK5_SIZE 0x2000UL /**> Bank5 size */ 1088 #define DMEM_BANK6_SIZE 0x2000UL /**> Bank6 size */ 1089 #define DMEM_BANK7_SIZE 0x2000UL /**> Bank7 size */ 1090 #define DMEM_NUM_BANKS 0x4UL /**> Number of physical SRAM banks */ 1091 #define DMEM_NUM_PORTS 0x2UL /**> Number of AHB slave ports */ 1092 #define DMEM_NUM_PORTS_IS_2 0x1UL /**> Boolean indicating if NUM_PORTS=2 */ 1093 #define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ 1094 #define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ 1095 #define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ 1096 #define LFXO_CTUNE 0x1UL /**> CTUNE Present */ 1097 #define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ 1098 #define ICACHE0_CACHEABLE_SIZE 0x80000UL /**> Cache Size */ 1099 #define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ 1100 #define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ 1101 #define ICACHE0_FLASH_SIZE 0x80000UL /**> Flash size */ 1102 #define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ 1103 #define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ 1104 #define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ 1105 #define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ 1106 #define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ 1107 #define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ 1108 #define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ 1109 #define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ 1110 #define ICACHE0_SET_BITS 0x5UL /**> Set bits */ 1111 #define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ 1112 #define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ 1113 #define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ 1114 #define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ 1115 #define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ 1116 #define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ 1117 #define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ 1118 #define PRS_ASYNC_CH_NUM 0xCUL /**> None */ 1119 #define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ 1120 #define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ 1121 #define PRS_SYNC_CH_NUM 0x4UL /**> None */ 1122 #define GPIO_COMALLOC_WIDTH 0x4UL /**> New Param */ 1123 #define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ 1124 #define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ 1125 #define GPIO_NUM_EVEN_PA 0x6UL /**> Num of even pins port A */ 1126 #define GPIO_NUM_EVEN_PB 0x4UL /**> Num of even pins port B */ 1127 #define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ 1128 #define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ 1129 #define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ 1130 #define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ 1131 #define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ 1132 #define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ 1133 #define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ 1134 #define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ 1135 #define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ 1136 #define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ 1137 #define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ 1138 #define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ 1139 #define GPIO_PORT_A_WIDTH 0xBUL /**> Port A Width */ 1140 #define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ 1141 #define GPIO_PORT_A_WL 0x8UL /**> New Param */ 1142 #define GPIO_PORT_A_WU 0x3UL /**> New Param */ 1143 #define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ 1144 #define GPIO_PORT_B_WIDTH 0x7UL /**> Port B Width */ 1145 #define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ 1146 #define GPIO_PORT_B_WL 0x7UL /**> New Param */ 1147 #define GPIO_PORT_B_WU 0x0UL /**> New Param */ 1148 #define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ 1149 #define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ 1150 #define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ 1151 #define GPIO_PORT_C_WL 0x8UL /**> New Param */ 1152 #define GPIO_PORT_C_WU 0x2UL /**> New Param */ 1153 #define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ 1154 #define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ 1155 #define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ 1156 #define GPIO_PORT_D_WL 0x6UL /**> New Param */ 1157 #define GPIO_PORT_D_WU 0x0UL /**> New Param */ 1158 #define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ 1159 #define GPIO_SEGALLOC_WIDTH 0x14UL /**> New Param */ 1160 #define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ 1161 #define LDMA_CH_BITS 0x5UL /**> New Param */ 1162 #define LDMA_CH_NUM 0x8UL /**> New Param */ 1163 #define LDMA_FIFO_BITS 0x5UL /**> New Param */ 1164 #define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ 1165 #define LDMAXBAR_CH_BITS 0x5UL /**> None */ 1166 #define LDMAXBAR_CH_NUM 0x8UL /**> None */ 1167 #define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ 1168 #define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ 1169 #define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ 1170 #define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ 1171 #define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ 1172 #define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ 1173 #define TIMER0_NO_DTI 0x0UL /**> */ 1174 #define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ 1175 #define TIMER1_CNTWIDTH 0x10UL /**> Counter Width */ 1176 #define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ 1177 #define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ 1178 #define TIMER1_NO_DTI 0x0UL /**> */ 1179 #define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ 1180 #define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ 1181 #define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ 1182 #define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ 1183 #define TIMER2_NO_DTI 0x0UL /**> */ 1184 #define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ 1185 #define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ 1186 #define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ 1187 #define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ 1188 #define TIMER3_NO_DTI 0x0UL /**> */ 1189 #define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ 1190 #define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ 1191 #define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ 1192 #define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ 1193 #define TIMER4_NO_DTI 0x0UL /**> */ 1194 #define USART0_AUTOTX_REG 0x1UL /**> None */ 1195 #define USART0_AUTOTX_REG_B 0x0UL /**> None */ 1196 #define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ 1197 #define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ 1198 #define USART0_CLK_PRS 0x1UL /**> None */ 1199 #define USART0_CLK_PRS_B 0x0UL /**> New Param */ 1200 #define USART0_FLOW_CONTROL 0x1UL /**> None */ 1201 #define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ 1202 #define USART0_I2S 0x1UL /**> None */ 1203 #define USART0_I2S_B 0x0UL /**> New Param */ 1204 #define USART0_IRDA_AVAILABLE 0x1UL /**> None */ 1205 #define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ 1206 #define USART0_MVDIS_FUNC 0x1UL /**> None */ 1207 #define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ 1208 #define USART0_RX_PRS 0x1UL /**> None */ 1209 #define USART0_RX_PRS_B 0x0UL /**> New Param */ 1210 #define USART0_SC_AVAILABLE 0x1UL /**> None */ 1211 #define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ 1212 #define USART0_SYNC_AVAILABLE 0x1UL /**> None */ 1213 #define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ 1214 #define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ 1215 #define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ 1216 #define USART0_TIMER 0x1UL /**> New Param */ 1217 #define USART0_TIMER_B 0x0UL /**> New Param */ 1218 #define BURTC_CNTWIDTH 0x20UL /**> None */ 1219 #define BURTC_PRECNT_WIDTH 0xFUL /**> */ 1220 #define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ 1221 #define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ 1222 #define SYSCFG_CHIP_FAMILY 0x38UL /**> CHIP Family */ 1223 #define SYSCFG_DEMODRAM_INST_COUNT 0x1UL /**> */ 1224 #define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ 1225 #define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ 1226 #define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ 1227 #define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ 1228 #define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ 1229 #define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ 1230 #define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ 1231 #define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ 1232 #define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ 1233 #define EUSART2_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ 1234 #define EUSART2_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ 1235 #define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ 1236 #define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ 1237 #define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ 1238 #define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ 1239 #define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ 1240 #define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ 1241 #define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ 1242 #define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ 1243 #define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ 1244 #define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ 1245 #define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ 1246 #define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ 1247 #define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ 1248 #define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ 1249 #define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ 1250 #define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ 1251 #define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ 1252 #define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ 1253 #define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ 1254 #define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ 1255 #define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ 1256 #define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ 1257 #define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ 1258 #define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ 1259 #define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ 1260 #define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ 1261 #define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ 1262 #define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ 1263 #define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ 1264 #define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ 1265 #define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ 1266 #define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ 1267 #define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ 1268 #define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ 1269 #define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ 1270 #define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ 1271 #define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ 1272 #define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ 1273 #define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ 1274 #define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ 1275 #define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ 1276 #define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ 1277 #define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ 1278 #define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ 1279 #define PFMXPPRF_COUNT_WIDTH 0x9UL /**> Width of counters for pulse-pairing */ 1280 #define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ 1281 #define SMU_NUM_BMPUS 0x7UL /**> Number of BMPUs */ 1282 #define SMU_NUM_PPU_PERIPHS 0x39UL /**> Number of PPU Peripherals */ 1283 #define SMU_NUM_PPU_PERIPHS_MOD_32 0x19UL /**> Number of PPU Peripherals (mod 32) */ 1284 #define SMU_NUM_PPU_PERIPHS_SUB_32 0x19UL /**> Number of PPU peripherals minus 32 */ 1285 #define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ 1286 #define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ 1287 #define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ 1288 #define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ 1289 #define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ 1290 #define IADC0_ENTRIES 0x10UL /**> ENTRIES */ 1291 #define ACMP0_DAC_INPUT 0x1UL /**> None */ 1292 #define ACMP0_EXT_OVR_IF 0x1UL /**> None */ 1293 #define ACMP1_DAC_INPUT 0x1UL /**> None */ 1294 #define ACMP1_EXT_OVR_IF 0x1UL /**> None */ 1295 #define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ 1296 #define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ 1297 #define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ 1298 #define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ 1299 #define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ 1300 #define PCNT0_PCNT_WIDTH 0x10UL /**> None */ 1301 #define LESENSE_CHANNEL_NUM 0x10UL /**> None */ 1302 #define LESENSE_RIPCNT_WIDTH 0x10UL /**> None */ 1303 #define LESENSE_STATE_NUM 0x20UL /**> None */ 1304 #define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ 1305 #define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ 1306 #define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ 1307 #define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ 1308 #define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ 1309 #define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ 1310 #define WDOG0_PCNUM 0x2UL /**> None */ 1311 #define WDOG1_PCNUM 0x2UL /**> None */ 1312 #define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ 1313 #define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ 1314 #define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ 1315 #define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ 1316 #define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ 1317 #define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ 1318 #define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ 1319 #define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ 1320 #define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ 1321 #define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ 1322 #define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ 1323 #define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ 1324 #define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ 1325 #define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ 1326 #define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ 1327 #define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ 1328 #define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ 1329 #define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ 1330 #define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ 1331 #define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ 1332 #define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ 1333 #define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ 1334 #define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ 1335 #define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ 1336 #define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ 1337 #define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ 1338 #define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ 1339 #define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ 1340 #define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ 1341 #define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ 1342 #define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ 1343 #define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ 1344 #define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ 1345 #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ 1346 1347 /* Instance macros for ACMP */ 1348 #define ACMP(n) (((n) == 0) ? ACMP0 \ 1349 : ((n) == 1) ? ACMP1 \ 1350 : 0x0UL) 1351 #define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ 1352 : ((ref) == ACMP1) ? 1 \ 1353 : -1) 1354 #define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ 1355 : ((n) == 1) ? ACMP1_DAC_INPUT \ 1356 : 0x0UL) 1357 #define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ 1358 : ((n) == 1) ? ACMP1_EXT_OVR_IF \ 1359 : 0x0UL) 1360 1361 /* Instance macros for EUSART */ 1362 #define EUSART(n) (((n) == 0) ? EUSART0 \ 1363 : ((n) == 1) ? EUSART1 \ 1364 : ((n) == 2) ? EUSART2 \ 1365 : 0x0UL) 1366 #define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ 1367 : ((ref) == EUSART1) ? 1 \ 1368 : ((ref) == EUSART2) ? 2 \ 1369 : -1) 1370 #define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ 1371 : ((n) == 1) ? EUSART1_EM2_CAPABLE \ 1372 : ((n) == 2) ? EUSART2_EM2_CAPABLE \ 1373 : 0x0UL) 1374 #define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ 1375 : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ 1376 : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ 1377 : 0x0UL) 1378 1379 /* Instance macros for I2C */ 1380 #define I2C(n) (((n) == 0) ? I2C0 \ 1381 : ((n) == 1) ? I2C1 \ 1382 : 0x0UL) 1383 #define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ 1384 : ((ref) == I2C1) ? 1 \ 1385 : -1) 1386 #define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ 1387 : ((n) == 1) ? I2C1_DELAY \ 1388 : 0x0UL) 1389 #define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ 1390 : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ 1391 : 0x0UL) 1392 1393 /* Instance macros for TIMER */ 1394 #define TIMER(n) (((n) == 0) ? TIMER0 \ 1395 : ((n) == 1) ? TIMER1 \ 1396 : ((n) == 2) ? TIMER2 \ 1397 : ((n) == 3) ? TIMER3 \ 1398 : ((n) == 4) ? TIMER4 \ 1399 : 0x0UL) 1400 #define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ 1401 : ((ref) == TIMER1) ? 1 \ 1402 : ((ref) == TIMER2) ? 2 \ 1403 : ((ref) == TIMER3) ? 3 \ 1404 : ((ref) == TIMER4) ? 4 \ 1405 : -1) 1406 #define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ 1407 : ((n) == 1) ? TIMER1_CC_NUM \ 1408 : ((n) == 2) ? TIMER2_CC_NUM \ 1409 : ((n) == 3) ? TIMER3_CC_NUM \ 1410 : ((n) == 4) ? TIMER4_CC_NUM \ 1411 : 0x0UL) 1412 #define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ 1413 : ((n) == 1) ? TIMER1_CNTWIDTH \ 1414 : ((n) == 2) ? TIMER2_CNTWIDTH \ 1415 : ((n) == 3) ? TIMER3_CNTWIDTH \ 1416 : ((n) == 4) ? TIMER4_CNTWIDTH \ 1417 : 0x0UL) 1418 #define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ 1419 : ((n) == 1) ? TIMER1_DTI \ 1420 : ((n) == 2) ? TIMER2_DTI \ 1421 : ((n) == 3) ? TIMER3_DTI \ 1422 : ((n) == 4) ? TIMER4_DTI \ 1423 : 0x0UL) 1424 #define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ 1425 : ((n) == 1) ? TIMER1_DTI_CC_NUM \ 1426 : ((n) == 2) ? TIMER2_DTI_CC_NUM \ 1427 : ((n) == 3) ? TIMER3_DTI_CC_NUM \ 1428 : ((n) == 4) ? TIMER4_DTI_CC_NUM \ 1429 : 0x0UL) 1430 #define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ 1431 : ((n) == 1) ? TIMER1_NO_DTI \ 1432 : ((n) == 2) ? TIMER2_NO_DTI \ 1433 : ((n) == 3) ? TIMER3_NO_DTI \ 1434 : ((n) == 4) ? TIMER4_NO_DTI \ 1435 : 0x0UL) 1436 1437 /* Instance macros for WDOG */ 1438 #define WDOG(n) (((n) == 0) ? WDOG0 \ 1439 : ((n) == 1) ? WDOG1 \ 1440 : 0x0UL) 1441 #define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ 1442 : ((ref) == WDOG1) ? 1 \ 1443 : -1) 1444 #define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ 1445 : ((n) == 1) ? WDOG1_PCNUM \ 1446 : 0x0UL) 1447 1448 /** @} End of group EFR32ZG23B020F512IM40_Peripheral_Parameters */ 1449 1450 /** @} End of group EFR32ZG23B020F512IM40 */ 1451 /** @}} End of group Parts */ 1452 1453 #ifdef __cplusplus 1454 } 1455 #endif 1456 #endif 1457
