1 /**************************************************************************//**
2 * @file
3 * @brief CMSIS system header file for EFR32MG29
4 ******************************************************************************
5 * # License
6 * <b>Copyright 2024 Silicon Laboratories, Inc. www.silabs.com</b>
7 ******************************************************************************
8 *
9 * SPDX-License-Identifier: Zlib
10 *
11 * The licensor of this software is Silicon Laboratories Inc.
12 *
13 * This software is provided 'as-is', without any express or implied
14 * warranty. In no event will the authors be held liable for any damages
15 * arising from the use of this software.
16 *
17 * Permission is granted to anyone to use this software for any purpose,
18 * including commercial applications, and to alter it and redistribute it
19 * freely, subject to the following restrictions:
20 *
21 * 1. The origin of this software must not be misrepresented; you must not
22 * claim that you wrote the original software. If you use this software
23 * in a product, an acknowledgment in the product documentation would be
24 * appreciated but is not required.
25 * 2. Altered source versions must be plainly marked as such, and must not be
26 * misrepresented as being the original software.
27 * 3. This notice may not be removed or altered from any source distribution.
28 *
29 *****************************************************************************/
30
31 #ifndef SYSTEM_EFR32MG29_H
32 #define SYSTEM_EFR32MG29_H
33
34 #ifdef __cplusplus
35 extern "C" {
36 #endif
37
38 #include <stdint.h>
39 #include "sl_code_classification.h"
40
41 /***************************************************************************//**
42 * @addtogroup Parts
43 * @{
44 ******************************************************************************/
45 /***************************************************************************//**
46 * @addtogroup EFR32MG29 EFR32MG29
47 * @{
48 ******************************************************************************/
49
50 /*******************************************************************************
51 ****************************** TYPEDEFS ***********************************
52 ******************************************************************************/
53
54 /* Interrupt vectortable entry */
55 typedef union {
56 void (*VECTOR_TABLE_Type)(void);
57 void *topOfStack;
58 } tVectorEntry;
59
60 /*******************************************************************************
61 ************************** GLOBAL VARIABLES *******************************
62 ******************************************************************************/
63
64 #if !defined(SYSTEM_NO_STATIC_MEMORY)
65 extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */
66 extern uint32_t SystemHfrcoFreq; /**< System HFRCO frequency */
67 #endif
68
69 /*Re-direction of IRQn.*/
70 #if defined (SL_TRUSTZONE_SECURE)
71 #define SMU_PRIVILEGED_IRQn SMU_S_PRIVILEGED_IRQn
72 #else
73 #define SMU_PRIVILEGED_IRQn SMU_NS_PRIVILEGED_IRQn
74 #endif /* SL_TRUSTZONE_SECURE */
75
76 /*Re-direction of IRQHandler.*/
77 #if defined (SL_TRUSTZONE_SECURE)
78 #define SMU_PRIVILEGED_IRQHandler SMU_S_PRIVILEGED_IRQHandler
79 #else
80 #define SMU_PRIVILEGED_IRQHandler SMU_NS_PRIVILEGED_IRQHandler
81 #endif /* SL_TRUSTZONE_SECURE */
82
83 /*******************************************************************************
84 ***************************** PROTOTYPES **********************************
85 ******************************************************************************/
86
87 void Reset_Handler(void); /**< Reset Handler */
88 void NMI_Handler(void); /**< NMI Handler */
89 void HardFault_Handler(void); /**< Hard Fault Handler */
90 void MemManage_Handler(void); /**< MPU Fault Handler */
91 void BusFault_Handler(void); /**< Bus Fault Handler */
92 void UsageFault_Handler(void); /**< Usage Fault Handler */
93 void SecureFault_Handler(void); /**< Secure Fault Handler */
94 void SVC_Handler(void); /**< SVCall Handler */
95 void DebugMon_Handler(void); /**< Debug Monitor Handler */
96 void PendSV_Handler(void); /**< PendSV Handler */
97 void SysTick_Handler(void); /**< SysTick Handler */
98
99 /* Part Specific Interrupts */
100 void SETAMPERHOST_IRQHandler(void); /**< SETAMPERHOST IRQ Handler */
101 void SEMBRX_IRQHandler(void); /**< SEMBRX IRQ Handler */
102 void SEMBTX_IRQHandler(void); /**< SEMBTX IRQ Handler */
103 void SMU_SECURE_IRQHandler(void); /**< SMU_SECURE IRQ Handler */
104 void SMU_S_PRIVILEGED_IRQHandler(void); /**< SMU_S_PRIVILEGED IRQ Handler */
105 void SMU_NS_PRIVILEGED_IRQHandler(void); /**< SMU_NS_PRIVILEGED IRQ Handler */
106 void EMU_IRQHandler(void); /**< EMU IRQ Handler */
107 void EMUEFP_IRQHandler(void); /**< EMUEFP IRQ Handler */
108 void DCDC_IRQHandler(void); /**< DCDC IRQ Handler */
109 void ETAMPDET_IRQHandler(void); /**< ETAMPDET IRQ Handler */
110 void TIMER0_IRQHandler(void); /**< TIMER0 IRQ Handler */
111 void TIMER1_IRQHandler(void); /**< TIMER1 IRQ Handler */
112 void TIMER2_IRQHandler(void); /**< TIMER2 IRQ Handler */
113 void TIMER3_IRQHandler(void); /**< TIMER3 IRQ Handler */
114 void TIMER4_IRQHandler(void); /**< TIMER4 IRQ Handler */
115 void RTCC_IRQHandler(void); /**< RTCC IRQ Handler */
116 void USART0_RX_IRQHandler(void); /**< USART0_RX IRQ Handler */
117 void USART0_TX_IRQHandler(void); /**< USART0_TX IRQ Handler */
118 void USART1_RX_IRQHandler(void); /**< USART1_RX IRQ Handler */
119 void USART1_TX_IRQHandler(void); /**< USART1_TX IRQ Handler */
120 void EUSART0_RX_IRQHandler(void); /**< EUSART0_RX IRQ Handler */
121 void EUSART0_TX_IRQHandler(void); /**< EUSART0_TX IRQ Handler */
122 void ICACHE0_IRQHandler(void); /**< ICACHE0 IRQ Handler */
123 void BURTC_IRQHandler(void); /**< BURTC IRQ Handler */
124 void LETIMER0_IRQHandler(void); /**< LETIMER0 IRQ Handler */
125 void SYSCFG_IRQHandler(void); /**< SYSCFG IRQ Handler */
126 void LDMA_IRQHandler(void); /**< LDMA IRQ Handler */
127 void LFXO_IRQHandler(void); /**< LFXO IRQ Handler */
128 void LFRCO_IRQHandler(void); /**< LFRCO IRQ Handler */
129 void ULFRCO_IRQHandler(void); /**< ULFRCO IRQ Handler */
130 void GPIO_ODD_IRQHandler(void); /**< GPIO_ODD IRQ Handler */
131 void GPIO_EVEN_IRQHandler(void); /**< GPIO_EVEN IRQ Handler */
132 void I2C0_IRQHandler(void); /**< I2C0 IRQ Handler */
133 void I2C1_IRQHandler(void); /**< I2C1 IRQ Handler */
134 void EMUDG_IRQHandler(void); /**< EMUDG IRQ Handler */
135 void EMUSE_IRQHandler(void); /**< EMUSE IRQ Handler */
136 void AGC_IRQHandler(void); /**< AGC IRQ Handler */
137 void BUFC_IRQHandler(void); /**< BUFC IRQ Handler */
138 void FRC_PRI_IRQHandler(void); /**< FRC_PRI IRQ Handler */
139 void FRC_IRQHandler(void); /**< FRC IRQ Handler */
140 void MODEM_IRQHandler(void); /**< MODEM IRQ Handler */
141 void PROTIMER_IRQHandler(void); /**< PROTIMER IRQ Handler */
142 void RAC_RSM_IRQHandler(void); /**< RAC_RSM IRQ Handler */
143 void RAC_SEQ_IRQHandler(void); /**< RAC_SEQ IRQ Handler */
144 void RDMAILBOX_IRQHandler(void); /**< RDMAILBOX IRQ Handler */
145 void RFSENSE_IRQHandler(void); /**< RFSENSE IRQ Handler */
146 void SYNTH_IRQHandler(void); /**< SYNTH IRQ Handler */
147 void PRORTC_IRQHandler(void); /**< PRORTC IRQ Handler */
148 void ACMP0_IRQHandler(void); /**< ACMP0 IRQ Handler */
149 void WDOG0_IRQHandler(void); /**< WDOG0 IRQ Handler */
150 void HFXO0_IRQHandler(void); /**< HFXO0 IRQ Handler */
151 void HFRCO0_IRQHandler(void); /**< HFRCO0 IRQ Handler */
152 void CMU_IRQHandler(void); /**< CMU IRQ Handler */
153 void AES_IRQHandler(void); /**< AES IRQ Handler */
154 void IADC_IRQHandler(void); /**< IADC IRQ Handler */
155 void MSC_IRQHandler(void); /**< MSC IRQ Handler */
156 void DPLL0_IRQHandler(void); /**< DPLL0 IRQ Handler */
157 void PDM_IRQHandler(void); /**< PDM IRQ Handler */
158 void SW0_IRQHandler(void); /**< SW0 IRQ Handler */
159 void SW1_IRQHandler(void); /**< SW1 IRQ Handler */
160 void SW2_IRQHandler(void); /**< SW2 IRQ Handler */
161 void SW3_IRQHandler(void); /**< SW3 IRQ Handler */
162 void KERNEL0_IRQHandler(void); /**< KERNEL0 IRQ Handler */
163 void KERNEL1_IRQHandler(void); /**< KERNEL1 IRQ Handler */
164 void M33CTI0_IRQHandler(void); /**< M33CTI0 IRQ Handler */
165 void M33CTI1_IRQHandler(void); /**< M33CTI1 IRQ Handler */
166 void FPUEXH_IRQHandler(void); /**< FPUEXH IRQ Handler */
167 void MPAHBRAM_IRQHandler(void); /**< MPAHBRAM IRQ Handler */
168 void EUSART1_RX_IRQHandler(void); /**< EUSART1_RX IRQ Handler */
169 void EUSART1_TX_IRQHandler(void); /**< EUSART1_TX IRQ Handler */
170
171 #if (__FPU_PRESENT == 1)
172 void FPUEH_IRQHandler(void); /**< FPU IRQ Handler */
173 #endif
174
175 SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL)
176 uint32_t SystemHCLKGet(void);
177
178 /**************************************************************************//**
179 * @brief
180 * Update CMSIS SystemCoreClock variable.
181 *
182 * @details
183 * CMSIS defines a global variable SystemCoreClock that shall hold the
184 * core frequency in Hz. If the core frequency is dynamically changed, the
185 * variable must be kept updated in order to be CMSIS compliant.
186 *
187 * Notice that only if changing the core clock frequency through the EMLIB
188 * CMU API, this variable will be kept updated. This function is only
189 * provided for CMSIS compliance and if a user modifies the the core clock
190 * outside the EMLIB CMU API.
191 *****************************************************************************/
SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM,SL_CODE_CLASS_TIME_CRITICAL)192 SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL)
193 static __INLINE uint32_t SystemCoreClockGet(void)
194 {
195 return SystemHCLKGet();
196 }
197
198 /**************************************************************************//**
199 * @brief
200 * Update CMSIS SystemCoreClock variable.
201 *
202 * @details
203 * CMSIS defines a global variable SystemCoreClock that shall hold the
204 * core frequency in Hz. If the core frequency is dynamically changed, the
205 * variable must be kept updated in order to be CMSIS compliant.
206 *
207 * Notice that only if changing the core clock frequency through the EMLIB
208 * CMU API, this variable will be kept updated. This function is only
209 * provided for CMSIS compliance and if a user modifies the the core clock
210 * outside the EMLIB CMU API.
211 *****************************************************************************/
SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM,SL_CODE_CLASS_TIME_CRITICAL)212 SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL)
213 static __INLINE void SystemCoreClockUpdate(void)
214 {
215 SystemHCLKGet();
216 }
217
218 void SystemInit(void);
219 SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL)
220 uint32_t SystemHFRCODPLLClockGet(void);
221 void SystemHFRCODPLLClockSet(uint32_t freq);
222 SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL)
223 uint32_t SystemSYSCLKGet(void);
224 SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL)
225 uint32_t SystemMaxCoreClockGet(void);
226 SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL)
227 uint32_t SystemFSRCOClockGet(void);
228 SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL)
229 uint32_t SystemHFXOClockGet(void);
230 void SystemHFXOClockSet(uint32_t freq);
231 SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL)
232 uint32_t SystemCLKIN0Get(void);
233 SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL)
234 uint32_t SystemLFXOClockGet(void);
235 void SystemLFXOClockSet(uint32_t freq);
236 SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL)
237 uint32_t SystemLFRCOClockGet(void);
238 SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL)
239 uint32_t SystemULFRCOClockGet(void);
240
241 /** @} End of group */
242 /** @} End of group Parts */
243
244 #ifdef __cplusplus
245 }
246 #endif
247 #endif /* SYSTEM_EFR32MG29_H */
248
