1 /**************************************************************************//** 2 * @file 3 * @brief EFR32MG21 SMU register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2024 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32MG21_SMU_H 31 #define EFR32MG21_SMU_H 32 #define SMU_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32MG21_SMU SMU 40 * @{ 41 * @brief EFR32MG21 SMU Register Declaration. 42 *****************************************************************************/ 43 44 /** SMU Register Declaration. */ 45 typedef struct smu_typedef{ 46 __IM uint32_t IPVERSION; /**< IP Version */ 47 __IM uint32_t STATUS; /**< Status Register */ 48 __IOM uint32_t LOCK; /**< Lock Register */ 49 __IOM uint32_t IF; /**< Interrupt Flag Register */ 50 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 51 uint32_t RESERVED0[3U]; /**< Reserved for future use */ 52 __IOM uint32_t M33CTRL; /**< M33 Control Settings */ 53 uint32_t RESERVED1[7U]; /**< Reserved for future use */ 54 __IOM uint32_t PPUPATD0; /**< Privileged Access */ 55 __IOM uint32_t PPUPATD1; /**< Privileged Access */ 56 uint32_t RESERVED2[6U]; /**< Reserved for future use */ 57 __IOM uint32_t PPUSATD0; /**< Secure Access */ 58 __IOM uint32_t PPUSATD1; /**< Secure Access */ 59 uint32_t RESERVED3[54U]; /**< Reserved for future use */ 60 __IM uint32_t PPUFS; /**< Fault Status */ 61 uint32_t RESERVED4[3U]; /**< Reserved for future use */ 62 __IOM uint32_t BMPUPATD0; /**< Privileged Attribute */ 63 uint32_t RESERVED5[7U]; /**< Reserved for future use */ 64 __IOM uint32_t BMPUSATD0; /**< Secure Attribute */ 65 uint32_t RESERVED6[55U]; /**< Reserved for future use */ 66 __IM uint32_t BMPUFS; /**< Fault Status */ 67 __IM uint32_t BMPUFSADDR; /**< Fault Status Address */ 68 uint32_t RESERVED7[2U]; /**< Reserved for future use */ 69 __IOM uint32_t ESAURTYPES0; /**< Region Types 0 */ 70 __IOM uint32_t ESAURTYPES1; /**< Region Types 1 */ 71 uint32_t RESERVED8[2U]; /**< Reserved for future use */ 72 __IOM uint32_t ESAUMRB01; /**< Movable Region Boundary */ 73 __IOM uint32_t ESAUMRB12; /**< Movable Region Boundary */ 74 uint32_t RESERVED9[2U]; /**< Reserved for future use */ 75 __IOM uint32_t ESAUMRB45; /**< Movable Region Boundary */ 76 __IOM uint32_t ESAUMRB56; /**< Movable Region Boundary */ 77 uint32_t RESERVED10[862U]; /**< Reserved for future use */ 78 __IM uint32_t IPVERSION_SET; /**< IP Version */ 79 __IM uint32_t STATUS_SET; /**< Status Register */ 80 __IOM uint32_t LOCK_SET; /**< Lock Register */ 81 __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ 82 __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ 83 uint32_t RESERVED11[3U]; /**< Reserved for future use */ 84 __IOM uint32_t M33CTRL_SET; /**< M33 Control Settings */ 85 uint32_t RESERVED12[7U]; /**< Reserved for future use */ 86 __IOM uint32_t PPUPATD0_SET; /**< Privileged Access */ 87 __IOM uint32_t PPUPATD1_SET; /**< Privileged Access */ 88 uint32_t RESERVED13[6U]; /**< Reserved for future use */ 89 __IOM uint32_t PPUSATD0_SET; /**< Secure Access */ 90 __IOM uint32_t PPUSATD1_SET; /**< Secure Access */ 91 uint32_t RESERVED14[54U]; /**< Reserved for future use */ 92 __IM uint32_t PPUFS_SET; /**< Fault Status */ 93 uint32_t RESERVED15[3U]; /**< Reserved for future use */ 94 __IOM uint32_t BMPUPATD0_SET; /**< Privileged Attribute */ 95 uint32_t RESERVED16[7U]; /**< Reserved for future use */ 96 __IOM uint32_t BMPUSATD0_SET; /**< Secure Attribute */ 97 uint32_t RESERVED17[55U]; /**< Reserved for future use */ 98 __IM uint32_t BMPUFS_SET; /**< Fault Status */ 99 __IM uint32_t BMPUFSADDR_SET; /**< Fault Status Address */ 100 uint32_t RESERVED18[2U]; /**< Reserved for future use */ 101 __IOM uint32_t ESAURTYPES0_SET; /**< Region Types 0 */ 102 __IOM uint32_t ESAURTYPES1_SET; /**< Region Types 1 */ 103 uint32_t RESERVED19[2U]; /**< Reserved for future use */ 104 __IOM uint32_t ESAUMRB01_SET; /**< Movable Region Boundary */ 105 __IOM uint32_t ESAUMRB12_SET; /**< Movable Region Boundary */ 106 uint32_t RESERVED20[2U]; /**< Reserved for future use */ 107 __IOM uint32_t ESAUMRB45_SET; /**< Movable Region Boundary */ 108 __IOM uint32_t ESAUMRB56_SET; /**< Movable Region Boundary */ 109 uint32_t RESERVED21[862U]; /**< Reserved for future use */ 110 __IM uint32_t IPVERSION_CLR; /**< IP Version */ 111 __IM uint32_t STATUS_CLR; /**< Status Register */ 112 __IOM uint32_t LOCK_CLR; /**< Lock Register */ 113 __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ 114 __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ 115 uint32_t RESERVED22[3U]; /**< Reserved for future use */ 116 __IOM uint32_t M33CTRL_CLR; /**< M33 Control Settings */ 117 uint32_t RESERVED23[7U]; /**< Reserved for future use */ 118 __IOM uint32_t PPUPATD0_CLR; /**< Privileged Access */ 119 __IOM uint32_t PPUPATD1_CLR; /**< Privileged Access */ 120 uint32_t RESERVED24[6U]; /**< Reserved for future use */ 121 __IOM uint32_t PPUSATD0_CLR; /**< Secure Access */ 122 __IOM uint32_t PPUSATD1_CLR; /**< Secure Access */ 123 uint32_t RESERVED25[54U]; /**< Reserved for future use */ 124 __IM uint32_t PPUFS_CLR; /**< Fault Status */ 125 uint32_t RESERVED26[3U]; /**< Reserved for future use */ 126 __IOM uint32_t BMPUPATD0_CLR; /**< Privileged Attribute */ 127 uint32_t RESERVED27[7U]; /**< Reserved for future use */ 128 __IOM uint32_t BMPUSATD0_CLR; /**< Secure Attribute */ 129 uint32_t RESERVED28[55U]; /**< Reserved for future use */ 130 __IM uint32_t BMPUFS_CLR; /**< Fault Status */ 131 __IM uint32_t BMPUFSADDR_CLR; /**< Fault Status Address */ 132 uint32_t RESERVED29[2U]; /**< Reserved for future use */ 133 __IOM uint32_t ESAURTYPES0_CLR; /**< Region Types 0 */ 134 __IOM uint32_t ESAURTYPES1_CLR; /**< Region Types 1 */ 135 uint32_t RESERVED30[2U]; /**< Reserved for future use */ 136 __IOM uint32_t ESAUMRB01_CLR; /**< Movable Region Boundary */ 137 __IOM uint32_t ESAUMRB12_CLR; /**< Movable Region Boundary */ 138 uint32_t RESERVED31[2U]; /**< Reserved for future use */ 139 __IOM uint32_t ESAUMRB45_CLR; /**< Movable Region Boundary */ 140 __IOM uint32_t ESAUMRB56_CLR; /**< Movable Region Boundary */ 141 uint32_t RESERVED32[862U]; /**< Reserved for future use */ 142 __IM uint32_t IPVERSION_TGL; /**< IP Version */ 143 __IM uint32_t STATUS_TGL; /**< Status Register */ 144 __IOM uint32_t LOCK_TGL; /**< Lock Register */ 145 __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ 146 __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ 147 uint32_t RESERVED33[3U]; /**< Reserved for future use */ 148 __IOM uint32_t M33CTRL_TGL; /**< M33 Control Settings */ 149 uint32_t RESERVED34[7U]; /**< Reserved for future use */ 150 __IOM uint32_t PPUPATD0_TGL; /**< Privileged Access */ 151 __IOM uint32_t PPUPATD1_TGL; /**< Privileged Access */ 152 uint32_t RESERVED35[6U]; /**< Reserved for future use */ 153 __IOM uint32_t PPUSATD0_TGL; /**< Secure Access */ 154 __IOM uint32_t PPUSATD1_TGL; /**< Secure Access */ 155 uint32_t RESERVED36[54U]; /**< Reserved for future use */ 156 __IM uint32_t PPUFS_TGL; /**< Fault Status */ 157 uint32_t RESERVED37[3U]; /**< Reserved for future use */ 158 __IOM uint32_t BMPUPATD0_TGL; /**< Privileged Attribute */ 159 uint32_t RESERVED38[7U]; /**< Reserved for future use */ 160 __IOM uint32_t BMPUSATD0_TGL; /**< Secure Attribute */ 161 uint32_t RESERVED39[55U]; /**< Reserved for future use */ 162 __IM uint32_t BMPUFS_TGL; /**< Fault Status */ 163 __IM uint32_t BMPUFSADDR_TGL; /**< Fault Status Address */ 164 uint32_t RESERVED40[2U]; /**< Reserved for future use */ 165 __IOM uint32_t ESAURTYPES0_TGL; /**< Region Types 0 */ 166 __IOM uint32_t ESAURTYPES1_TGL; /**< Region Types 1 */ 167 uint32_t RESERVED41[2U]; /**< Reserved for future use */ 168 __IOM uint32_t ESAUMRB01_TGL; /**< Movable Region Boundary */ 169 __IOM uint32_t ESAUMRB12_TGL; /**< Movable Region Boundary */ 170 uint32_t RESERVED42[2U]; /**< Reserved for future use */ 171 __IOM uint32_t ESAUMRB45_TGL; /**< Movable Region Boundary */ 172 __IOM uint32_t ESAUMRB56_TGL; /**< Movable Region Boundary */ 173 } SMU_TypeDef; 174 /** @} End of group EFR32MG21_SMU */ 175 176 /**************************************************************************//** 177 * @addtogroup EFR32MG21_SMU 178 * @{ 179 * @defgroup EFR32MG21_SMU_BitFields SMU Bit Fields 180 * @{ 181 *****************************************************************************/ 182 183 /* Bit fields for SMU IPVERSION */ 184 #define _SMU_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for SMU_IPVERSION */ 185 #define _SMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for SMU_IPVERSION */ 186 #define _SMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for SMU_IPVERSION */ 187 #define _SMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SMU_IPVERSION */ 188 #define _SMU_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IPVERSION */ 189 #define SMU_IPVERSION_IPVERSION_DEFAULT (_SMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IPVERSION */ 190 191 /* Bit fields for SMU STATUS */ 192 #define _SMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for SMU_STATUS */ 193 #define _SMU_STATUS_MASK 0x00000003UL /**< Mask for SMU_STATUS */ 194 #define SMU_STATUS_SMULOCK (0x1UL << 0) /**< SMU Lock */ 195 #define _SMU_STATUS_SMULOCK_SHIFT 0 /**< Shift value for SMU_SMULOCK */ 196 #define _SMU_STATUS_SMULOCK_MASK 0x1UL /**< Bit mask for SMU_SMULOCK */ 197 #define _SMU_STATUS_SMULOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_STATUS */ 198 #define _SMU_STATUS_SMULOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for SMU_STATUS */ 199 #define _SMU_STATUS_SMULOCK_LOCKED 0x00000001UL /**< Mode LOCKED for SMU_STATUS */ 200 #define SMU_STATUS_SMULOCK_DEFAULT (_SMU_STATUS_SMULOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_STATUS */ 201 #define SMU_STATUS_SMULOCK_UNLOCKED (_SMU_STATUS_SMULOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for SMU_STATUS */ 202 #define SMU_STATUS_SMULOCK_LOCKED (_SMU_STATUS_SMULOCK_LOCKED << 0) /**< Shifted mode LOCKED for SMU_STATUS */ 203 #define SMU_STATUS_SMUPRGERR (0x1UL << 1) /**< SMU Programming Error */ 204 #define _SMU_STATUS_SMUPRGERR_SHIFT 1 /**< Shift value for SMU_SMUPRGERR */ 205 #define _SMU_STATUS_SMUPRGERR_MASK 0x2UL /**< Bit mask for SMU_SMUPRGERR */ 206 #define _SMU_STATUS_SMUPRGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_STATUS */ 207 #define SMU_STATUS_SMUPRGERR_DEFAULT (_SMU_STATUS_SMUPRGERR_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_STATUS */ 208 209 /* Bit fields for SMU LOCK */ 210 #define _SMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for SMU_LOCK */ 211 #define _SMU_LOCK_MASK 0x00FFFFFFUL /**< Mask for SMU_LOCK */ 212 #define _SMU_LOCK_SMULOCKKEY_SHIFT 0 /**< Shift value for SMU_SMULOCKKEY */ 213 #define _SMU_LOCK_SMULOCKKEY_MASK 0xFFFFFFUL /**< Bit mask for SMU_SMULOCKKEY */ 214 #define _SMU_LOCK_SMULOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_LOCK */ 215 #define _SMU_LOCK_SMULOCKKEY_UNLOCK 0x00ACCE55UL /**< Mode UNLOCK for SMU_LOCK */ 216 #define SMU_LOCK_SMULOCKKEY_DEFAULT (_SMU_LOCK_SMULOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_LOCK */ 217 #define SMU_LOCK_SMULOCKKEY_UNLOCK (_SMU_LOCK_SMULOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for SMU_LOCK */ 218 219 /* Bit fields for SMU IF */ 220 #define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ 221 #define _SMU_IF_MASK 0x00030005UL /**< Mask for SMU_IF */ 222 #define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ 223 #define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ 224 #define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ 225 #define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ 226 #define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ 227 #define SMU_IF_PPUINST (0x1UL << 2) /**< PPU Instruction Interrupt Flag */ 228 #define _SMU_IF_PPUINST_SHIFT 2 /**< Shift value for SMU_PPUINST */ 229 #define _SMU_IF_PPUINST_MASK 0x4UL /**< Bit mask for SMU_PPUINST */ 230 #define _SMU_IF_PPUINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ 231 #define SMU_IF_PPUINST_DEFAULT (_SMU_IF_PPUINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_IF */ 232 #define SMU_IF_PPUSEC (0x1UL << 16) /**< PPU Security Interrupt Flag */ 233 #define _SMU_IF_PPUSEC_SHIFT 16 /**< Shift value for SMU_PPUSEC */ 234 #define _SMU_IF_PPUSEC_MASK 0x10000UL /**< Bit mask for SMU_PPUSEC */ 235 #define _SMU_IF_PPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ 236 #define SMU_IF_PPUSEC_DEFAULT (_SMU_IF_PPUSEC_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_IF */ 237 #define SMU_IF_BMPUSEC (0x1UL << 17) /**< BMPU Security Interrupt Flag */ 238 #define _SMU_IF_BMPUSEC_SHIFT 17 /**< Shift value for SMU_BMPUSEC */ 239 #define _SMU_IF_BMPUSEC_MASK 0x20000UL /**< Bit mask for SMU_BMPUSEC */ 240 #define _SMU_IF_BMPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ 241 #define SMU_IF_BMPUSEC_DEFAULT (_SMU_IF_BMPUSEC_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_IF */ 242 243 /* Bit fields for SMU IEN */ 244 #define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ 245 #define _SMU_IEN_MASK 0x00030005UL /**< Mask for SMU_IEN */ 246 #define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ 247 #define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ 248 #define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ 249 #define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ 250 #define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ 251 #define SMU_IEN_PPUINST (0x1UL << 2) /**< PPU Instruction Interrupt Flag */ 252 #define _SMU_IEN_PPUINST_SHIFT 2 /**< Shift value for SMU_PPUINST */ 253 #define _SMU_IEN_PPUINST_MASK 0x4UL /**< Bit mask for SMU_PPUINST */ 254 #define _SMU_IEN_PPUINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ 255 #define SMU_IEN_PPUINST_DEFAULT (_SMU_IEN_PPUINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_IEN */ 256 #define SMU_IEN_PPUSEC (0x1UL << 16) /**< PPU Security Interrupt Flag */ 257 #define _SMU_IEN_PPUSEC_SHIFT 16 /**< Shift value for SMU_PPUSEC */ 258 #define _SMU_IEN_PPUSEC_MASK 0x10000UL /**< Bit mask for SMU_PPUSEC */ 259 #define _SMU_IEN_PPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ 260 #define SMU_IEN_PPUSEC_DEFAULT (_SMU_IEN_PPUSEC_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_IEN */ 261 #define SMU_IEN_BMPUSEC (0x1UL << 17) /**< BMPU Security Interrupt Flag */ 262 #define _SMU_IEN_BMPUSEC_SHIFT 17 /**< Shift value for SMU_BMPUSEC */ 263 #define _SMU_IEN_BMPUSEC_MASK 0x20000UL /**< Bit mask for SMU_BMPUSEC */ 264 #define _SMU_IEN_BMPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ 265 #define SMU_IEN_BMPUSEC_DEFAULT (_SMU_IEN_BMPUSEC_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_IEN */ 266 267 /* Bit fields for SMU M33CTRL */ 268 #define _SMU_M33CTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_M33CTRL */ 269 #define _SMU_M33CTRL_MASK 0x0000001FUL /**< Mask for SMU_M33CTRL */ 270 #define SMU_M33CTRL_LOCKSVTAIRCR (0x1UL << 0) /**< SVTAIRCR LOCK bit */ 271 #define _SMU_M33CTRL_LOCKSVTAIRCR_SHIFT 0 /**< Shift value for SMU_LOCKSVTAIRCR */ 272 #define _SMU_M33CTRL_LOCKSVTAIRCR_MASK 0x1UL /**< Bit mask for SMU_LOCKSVTAIRCR */ 273 #define _SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ 274 #define SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT (_SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_M33CTRL */ 275 #define SMU_M33CTRL_LOCKNSVTOR (0x1UL << 1) /**< NSVTOR LOCK bit */ 276 #define _SMU_M33CTRL_LOCKNSVTOR_SHIFT 1 /**< Shift value for SMU_LOCKNSVTOR */ 277 #define _SMU_M33CTRL_LOCKNSVTOR_MASK 0x2UL /**< Bit mask for SMU_LOCKNSVTOR */ 278 #define _SMU_M33CTRL_LOCKNSVTOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ 279 #define SMU_M33CTRL_LOCKNSVTOR_DEFAULT (_SMU_M33CTRL_LOCKNSVTOR_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_M33CTRL */ 280 #define SMU_M33CTRL_LOCKSMPU (0x1UL << 2) /**< SMPU LOCK bit */ 281 #define _SMU_M33CTRL_LOCKSMPU_SHIFT 2 /**< Shift value for SMU_LOCKSMPU */ 282 #define _SMU_M33CTRL_LOCKSMPU_MASK 0x4UL /**< Bit mask for SMU_LOCKSMPU */ 283 #define _SMU_M33CTRL_LOCKSMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ 284 #define SMU_M33CTRL_LOCKSMPU_DEFAULT (_SMU_M33CTRL_LOCKSMPU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_M33CTRL */ 285 #define SMU_M33CTRL_LOCKNSMPU (0x1UL << 3) /**< NSMPU LOCK bit */ 286 #define _SMU_M33CTRL_LOCKNSMPU_SHIFT 3 /**< Shift value for SMU_LOCKNSMPU */ 287 #define _SMU_M33CTRL_LOCKNSMPU_MASK 0x8UL /**< Bit mask for SMU_LOCKNSMPU */ 288 #define _SMU_M33CTRL_LOCKNSMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ 289 #define SMU_M33CTRL_LOCKNSMPU_DEFAULT (_SMU_M33CTRL_LOCKNSMPU_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_M33CTRL */ 290 #define SMU_M33CTRL_LOCKSAU (0x1UL << 4) /**< SAU LOCK bit */ 291 #define _SMU_M33CTRL_LOCKSAU_SHIFT 4 /**< Shift value for SMU_LOCKSAU */ 292 #define _SMU_M33CTRL_LOCKSAU_MASK 0x10UL /**< Bit mask for SMU_LOCKSAU */ 293 #define _SMU_M33CTRL_LOCKSAU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ 294 #define SMU_M33CTRL_LOCKSAU_DEFAULT (_SMU_M33CTRL_LOCKSAU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_M33CTRL */ 295 296 /* Bit fields for SMU PPUPATD0 */ 297 #define _SMU_PPUPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD0 */ 298 #define _SMU_PPUPATD0_MASK 0xFFFFFFFEUL /**< Mask for SMU_PPUPATD0 */ 299 #define SMU_PPUPATD0_EMU (0x1UL << 1) /**< EMU Privileged Access */ 300 #define _SMU_PPUPATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */ 301 #define _SMU_PPUPATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */ 302 #define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 303 #define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 304 #define SMU_PPUPATD0_CMU (0x1UL << 2) /**< CMU Privileged Access */ 305 #define _SMU_PPUPATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */ 306 #define _SMU_PPUPATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */ 307 #define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 308 #define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 309 #define SMU_PPUPATD0_HFXO0 (0x1UL << 3) /**< HFXO0 Privileged Access */ 310 #define _SMU_PPUPATD0_HFXO0_SHIFT 3 /**< Shift value for SMU_HFXO0 */ 311 #define _SMU_PPUPATD0_HFXO0_MASK 0x8UL /**< Bit mask for SMU_HFXO0 */ 312 #define _SMU_PPUPATD0_HFXO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 313 #define SMU_PPUPATD0_HFXO0_DEFAULT (_SMU_PPUPATD0_HFXO0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 314 #define SMU_PPUPATD0_HFRCO0 (0x1UL << 4) /**< HFRCO0 Privileged Access */ 315 #define _SMU_PPUPATD0_HFRCO0_SHIFT 4 /**< Shift value for SMU_HFRCO0 */ 316 #define _SMU_PPUPATD0_HFRCO0_MASK 0x10UL /**< Bit mask for SMU_HFRCO0 */ 317 #define _SMU_PPUPATD0_HFRCO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 318 #define SMU_PPUPATD0_HFRCO0_DEFAULT (_SMU_PPUPATD0_HFRCO0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 319 #define SMU_PPUPATD0_FSRCO (0x1UL << 5) /**< FSRCO Privileged Access */ 320 #define _SMU_PPUPATD0_FSRCO_SHIFT 5 /**< Shift value for SMU_FSRCO */ 321 #define _SMU_PPUPATD0_FSRCO_MASK 0x20UL /**< Bit mask for SMU_FSRCO */ 322 #define _SMU_PPUPATD0_FSRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 323 #define SMU_PPUPATD0_FSRCO_DEFAULT (_SMU_PPUPATD0_FSRCO_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 324 #define SMU_PPUPATD0_DPLL0 (0x1UL << 6) /**< DPLL0 Privileged Access */ 325 #define _SMU_PPUPATD0_DPLL0_SHIFT 6 /**< Shift value for SMU_DPLL0 */ 326 #define _SMU_PPUPATD0_DPLL0_MASK 0x40UL /**< Bit mask for SMU_DPLL0 */ 327 #define _SMU_PPUPATD0_DPLL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 328 #define SMU_PPUPATD0_DPLL0_DEFAULT (_SMU_PPUPATD0_DPLL0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 329 #define SMU_PPUPATD0_LFXO (0x1UL << 7) /**< LFXO Privileged Access */ 330 #define _SMU_PPUPATD0_LFXO_SHIFT 7 /**< Shift value for SMU_LFXO */ 331 #define _SMU_PPUPATD0_LFXO_MASK 0x80UL /**< Bit mask for SMU_LFXO */ 332 #define _SMU_PPUPATD0_LFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 333 #define SMU_PPUPATD0_LFXO_DEFAULT (_SMU_PPUPATD0_LFXO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 334 #define SMU_PPUPATD0_LFRCO (0x1UL << 8) /**< LFRCO Privileged Access */ 335 #define _SMU_PPUPATD0_LFRCO_SHIFT 8 /**< Shift value for SMU_LFRCO */ 336 #define _SMU_PPUPATD0_LFRCO_MASK 0x100UL /**< Bit mask for SMU_LFRCO */ 337 #define _SMU_PPUPATD0_LFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 338 #define SMU_PPUPATD0_LFRCO_DEFAULT (_SMU_PPUPATD0_LFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 339 #define SMU_PPUPATD0_ULFRCO (0x1UL << 9) /**< ULFRCO Privileged Access */ 340 #define _SMU_PPUPATD0_ULFRCO_SHIFT 9 /**< Shift value for SMU_ULFRCO */ 341 #define _SMU_PPUPATD0_ULFRCO_MASK 0x200UL /**< Bit mask for SMU_ULFRCO */ 342 #define _SMU_PPUPATD0_ULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 343 #define SMU_PPUPATD0_ULFRCO_DEFAULT (_SMU_PPUPATD0_ULFRCO_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 344 #define SMU_PPUPATD0_MSC (0x1UL << 10) /**< MSC Privileged Access */ 345 #define _SMU_PPUPATD0_MSC_SHIFT 10 /**< Shift value for SMU_MSC */ 346 #define _SMU_PPUPATD0_MSC_MASK 0x400UL /**< Bit mask for SMU_MSC */ 347 #define _SMU_PPUPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 348 #define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 349 #define SMU_PPUPATD0_ICACHE0 (0x1UL << 11) /**< ICACHE0 Privileged Access */ 350 #define _SMU_PPUPATD0_ICACHE0_SHIFT 11 /**< Shift value for SMU_ICACHE0 */ 351 #define _SMU_PPUPATD0_ICACHE0_MASK 0x800UL /**< Bit mask for SMU_ICACHE0 */ 352 #define _SMU_PPUPATD0_ICACHE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 353 #define SMU_PPUPATD0_ICACHE0_DEFAULT (_SMU_PPUPATD0_ICACHE0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 354 #define SMU_PPUPATD0_PRS (0x1UL << 12) /**< PRS Privileged Access */ 355 #define _SMU_PPUPATD0_PRS_SHIFT 12 /**< Shift value for SMU_PRS */ 356 #define _SMU_PPUPATD0_PRS_MASK 0x1000UL /**< Bit mask for SMU_PRS */ 357 #define _SMU_PPUPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 358 #define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 359 #define SMU_PPUPATD0_GPIO (0x1UL << 13) /**< GPIO Privileged Access */ 360 #define _SMU_PPUPATD0_GPIO_SHIFT 13 /**< Shift value for SMU_GPIO */ 361 #define _SMU_PPUPATD0_GPIO_MASK 0x2000UL /**< Bit mask for SMU_GPIO */ 362 #define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 363 #define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 364 #define SMU_PPUPATD0_LDMA (0x1UL << 14) /**< LDMA Privileged Access */ 365 #define _SMU_PPUPATD0_LDMA_SHIFT 14 /**< Shift value for SMU_LDMA */ 366 #define _SMU_PPUPATD0_LDMA_MASK 0x4000UL /**< Bit mask for SMU_LDMA */ 367 #define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 368 #define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 369 #define SMU_PPUPATD0_LDMAXBAR (0x1UL << 15) /**< LDMAXBAR Privileged Access */ 370 #define _SMU_PPUPATD0_LDMAXBAR_SHIFT 15 /**< Shift value for SMU_LDMAXBAR */ 371 #define _SMU_PPUPATD0_LDMAXBAR_MASK 0x8000UL /**< Bit mask for SMU_LDMAXBAR */ 372 #define _SMU_PPUPATD0_LDMAXBAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 373 #define SMU_PPUPATD0_LDMAXBAR_DEFAULT (_SMU_PPUPATD0_LDMAXBAR_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 374 #define SMU_PPUPATD0_TIMER0 (0x1UL << 16) /**< TIMER0 Privileged Access */ 375 #define _SMU_PPUPATD0_TIMER0_SHIFT 16 /**< Shift value for SMU_TIMER0 */ 376 #define _SMU_PPUPATD0_TIMER0_MASK 0x10000UL /**< Bit mask for SMU_TIMER0 */ 377 #define _SMU_PPUPATD0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 378 #define SMU_PPUPATD0_TIMER0_DEFAULT (_SMU_PPUPATD0_TIMER0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 379 #define SMU_PPUPATD0_TIMER1 (0x1UL << 17) /**< TIMER1 Privileged Access */ 380 #define _SMU_PPUPATD0_TIMER1_SHIFT 17 /**< Shift value for SMU_TIMER1 */ 381 #define _SMU_PPUPATD0_TIMER1_MASK 0x20000UL /**< Bit mask for SMU_TIMER1 */ 382 #define _SMU_PPUPATD0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 383 #define SMU_PPUPATD0_TIMER1_DEFAULT (_SMU_PPUPATD0_TIMER1_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 384 #define SMU_PPUPATD0_TIMER2 (0x1UL << 18) /**< TIMER2 Privileged Access */ 385 #define _SMU_PPUPATD0_TIMER2_SHIFT 18 /**< Shift value for SMU_TIMER2 */ 386 #define _SMU_PPUPATD0_TIMER2_MASK 0x40000UL /**< Bit mask for SMU_TIMER2 */ 387 #define _SMU_PPUPATD0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 388 #define SMU_PPUPATD0_TIMER2_DEFAULT (_SMU_PPUPATD0_TIMER2_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 389 #define SMU_PPUPATD0_TIMER3 (0x1UL << 19) /**< TIMER3 Privileged Access */ 390 #define _SMU_PPUPATD0_TIMER3_SHIFT 19 /**< Shift value for SMU_TIMER3 */ 391 #define _SMU_PPUPATD0_TIMER3_MASK 0x80000UL /**< Bit mask for SMU_TIMER3 */ 392 #define _SMU_PPUPATD0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 393 #define SMU_PPUPATD0_TIMER3_DEFAULT (_SMU_PPUPATD0_TIMER3_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 394 #define SMU_PPUPATD0_USART0 (0x1UL << 20) /**< USART0 Privileged Access */ 395 #define _SMU_PPUPATD0_USART0_SHIFT 20 /**< Shift value for SMU_USART0 */ 396 #define _SMU_PPUPATD0_USART0_MASK 0x100000UL /**< Bit mask for SMU_USART0 */ 397 #define _SMU_PPUPATD0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 398 #define SMU_PPUPATD0_USART0_DEFAULT (_SMU_PPUPATD0_USART0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 399 #define SMU_PPUPATD0_USART1 (0x1UL << 21) /**< USART1 Privileged Access */ 400 #define _SMU_PPUPATD0_USART1_SHIFT 21 /**< Shift value for SMU_USART1 */ 401 #define _SMU_PPUPATD0_USART1_MASK 0x200000UL /**< Bit mask for SMU_USART1 */ 402 #define _SMU_PPUPATD0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 403 #define SMU_PPUPATD0_USART1_DEFAULT (_SMU_PPUPATD0_USART1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 404 #define SMU_PPUPATD0_USART2 (0x1UL << 22) /**< USART2 Privileged Access */ 405 #define _SMU_PPUPATD0_USART2_SHIFT 22 /**< Shift value for SMU_USART2 */ 406 #define _SMU_PPUPATD0_USART2_MASK 0x400000UL /**< Bit mask for SMU_USART2 */ 407 #define _SMU_PPUPATD0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 408 #define SMU_PPUPATD0_USART2_DEFAULT (_SMU_PPUPATD0_USART2_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 409 #define SMU_PPUPATD0_BURTC (0x1UL << 23) /**< BURTC Privileged Access */ 410 #define _SMU_PPUPATD0_BURTC_SHIFT 23 /**< Shift value for SMU_BURTC */ 411 #define _SMU_PPUPATD0_BURTC_MASK 0x800000UL /**< Bit mask for SMU_BURTC */ 412 #define _SMU_PPUPATD0_BURTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 413 #define SMU_PPUPATD0_BURTC_DEFAULT (_SMU_PPUPATD0_BURTC_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 414 #define SMU_PPUPATD0_I2C1 (0x1UL << 24) /**< I2C1 Privileged Access */ 415 #define _SMU_PPUPATD0_I2C1_SHIFT 24 /**< Shift value for SMU_I2C1 */ 416 #define _SMU_PPUPATD0_I2C1_MASK 0x1000000UL /**< Bit mask for SMU_I2C1 */ 417 #define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 418 #define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 419 #define SMU_PPUPATD0_CHIPTESTCTRL (0x1UL << 25) /**< CHIPTESTCTRL Privileged Access */ 420 #define _SMU_PPUPATD0_CHIPTESTCTRL_SHIFT 25 /**< Shift value for SMU_CHIPTESTCTRL */ 421 #define _SMU_PPUPATD0_CHIPTESTCTRL_MASK 0x2000000UL /**< Bit mask for SMU_CHIPTESTCTRL */ 422 #define _SMU_PPUPATD0_CHIPTESTCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 423 #define SMU_PPUPATD0_CHIPTESTCTRL_DEFAULT (_SMU_PPUPATD0_CHIPTESTCTRL_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 424 #define SMU_PPUPATD0_LVGD (0x1UL << 26) /**< LVGD Privileged Access */ 425 #define _SMU_PPUPATD0_LVGD_SHIFT 26 /**< Shift value for SMU_LVGD */ 426 #define _SMU_PPUPATD0_LVGD_MASK 0x4000000UL /**< Bit mask for SMU_LVGD */ 427 #define _SMU_PPUPATD0_LVGD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 428 #define SMU_PPUPATD0_LVGD_DEFAULT (_SMU_PPUPATD0_LVGD_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 429 #define SMU_PPUPATD0_SYSCFG (0x1UL << 27) /**< SYSCFG Privileged Access */ 430 #define _SMU_PPUPATD0_SYSCFG_SHIFT 27 /**< Shift value for SMU_SYSCFG */ 431 #define _SMU_PPUPATD0_SYSCFG_MASK 0x8000000UL /**< Bit mask for SMU_SYSCFG */ 432 #define _SMU_PPUPATD0_SYSCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 433 #define SMU_PPUPATD0_SYSCFG_DEFAULT (_SMU_PPUPATD0_SYSCFG_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 434 #define SMU_PPUPATD0_BURAM (0x1UL << 28) /**< BURAM Privileged Access */ 435 #define _SMU_PPUPATD0_BURAM_SHIFT 28 /**< Shift value for SMU_BURAM */ 436 #define _SMU_PPUPATD0_BURAM_MASK 0x10000000UL /**< Bit mask for SMU_BURAM */ 437 #define _SMU_PPUPATD0_BURAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 438 #define SMU_PPUPATD0_BURAM_DEFAULT (_SMU_PPUPATD0_BURAM_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 439 #define SMU_PPUPATD0_IFADCDEBUG (0x1UL << 29) /**< IFADCDEBUG Privileged Access */ 440 #define _SMU_PPUPATD0_IFADCDEBUG_SHIFT 29 /**< Shift value for SMU_IFADCDEBUG */ 441 #define _SMU_PPUPATD0_IFADCDEBUG_MASK 0x20000000UL /**< Bit mask for SMU_IFADCDEBUG */ 442 #define _SMU_PPUPATD0_IFADCDEBUG_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 443 #define SMU_PPUPATD0_IFADCDEBUG_DEFAULT (_SMU_PPUPATD0_IFADCDEBUG_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 444 #define SMU_PPUPATD0_GPCRC (0x1UL << 30) /**< GPCRC Privileged Access */ 445 #define _SMU_PPUPATD0_GPCRC_SHIFT 30 /**< Shift value for SMU_GPCRC */ 446 #define _SMU_PPUPATD0_GPCRC_MASK 0x40000000UL /**< Bit mask for SMU_GPCRC */ 447 #define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 448 #define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 449 #define SMU_PPUPATD0_RTCC (0x1UL << 31) /**< RTCC Privileged Access */ 450 #define _SMU_PPUPATD0_RTCC_SHIFT 31 /**< Shift value for SMU_RTCC */ 451 #define _SMU_PPUPATD0_RTCC_MASK 0x80000000UL /**< Bit mask for SMU_RTCC */ 452 #define _SMU_PPUPATD0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 453 #define SMU_PPUPATD0_RTCC_DEFAULT (_SMU_PPUPATD0_RTCC_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 454 455 /* Bit fields for SMU PPUPATD1 */ 456 #define _SMU_PPUPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD1 */ 457 #define _SMU_PPUPATD1_MASK 0x00003FFFUL /**< Mask for SMU_PPUPATD1 */ 458 #define SMU_PPUPATD1_LETIMER0 (0x1UL << 0) /**< LETIMER0 Privileged Access */ 459 #define _SMU_PPUPATD1_LETIMER0_SHIFT 0 /**< Shift value for SMU_LETIMER0 */ 460 #define _SMU_PPUPATD1_LETIMER0_MASK 0x1UL /**< Bit mask for SMU_LETIMER0 */ 461 #define _SMU_PPUPATD1_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 462 #define SMU_PPUPATD1_LETIMER0_DEFAULT (_SMU_PPUPATD1_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 463 #define SMU_PPUPATD1_IADC0 (0x1UL << 1) /**< IADC0 Privileged Access */ 464 #define _SMU_PPUPATD1_IADC0_SHIFT 1 /**< Shift value for SMU_IADC0 */ 465 #define _SMU_PPUPATD1_IADC0_MASK 0x2UL /**< Bit mask for SMU_IADC0 */ 466 #define _SMU_PPUPATD1_IADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 467 #define SMU_PPUPATD1_IADC0_DEFAULT (_SMU_PPUPATD1_IADC0_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 468 #define SMU_PPUPATD1_ACMP0 (0x1UL << 2) /**< ACMP0 Privileged Access */ 469 #define _SMU_PPUPATD1_ACMP0_SHIFT 2 /**< Shift value for SMU_ACMP0 */ 470 #define _SMU_PPUPATD1_ACMP0_MASK 0x4UL /**< Bit mask for SMU_ACMP0 */ 471 #define _SMU_PPUPATD1_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 472 #define SMU_PPUPATD1_ACMP0_DEFAULT (_SMU_PPUPATD1_ACMP0_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 473 #define SMU_PPUPATD1_ACMP1 (0x1UL << 3) /**< ACMP1 Privileged Access */ 474 #define _SMU_PPUPATD1_ACMP1_SHIFT 3 /**< Shift value for SMU_ACMP1 */ 475 #define _SMU_PPUPATD1_ACMP1_MASK 0x8UL /**< Bit mask for SMU_ACMP1 */ 476 #define _SMU_PPUPATD1_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 477 #define SMU_PPUPATD1_ACMP1_DEFAULT (_SMU_PPUPATD1_ACMP1_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 478 #define SMU_PPUPATD1_I2C0 (0x1UL << 4) /**< I2C0 Privileged Access */ 479 #define _SMU_PPUPATD1_I2C0_SHIFT 4 /**< Shift value for SMU_I2C0 */ 480 #define _SMU_PPUPATD1_I2C0_MASK 0x10UL /**< Bit mask for SMU_I2C0 */ 481 #define _SMU_PPUPATD1_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 482 #define SMU_PPUPATD1_I2C0_DEFAULT (_SMU_PPUPATD1_I2C0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 483 #define SMU_PPUPATD1_HFRCOEM23 (0x1UL << 5) /**< HFRCOEM23 Privileged Access */ 484 #define _SMU_PPUPATD1_HFRCOEM23_SHIFT 5 /**< Shift value for SMU_HFRCOEM23 */ 485 #define _SMU_PPUPATD1_HFRCOEM23_MASK 0x20UL /**< Bit mask for SMU_HFRCOEM23 */ 486 #define _SMU_PPUPATD1_HFRCOEM23_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 487 #define SMU_PPUPATD1_HFRCOEM23_DEFAULT (_SMU_PPUPATD1_HFRCOEM23_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 488 #define SMU_PPUPATD1_WDOG0 (0x1UL << 6) /**< WDOG0 Privileged Access */ 489 #define _SMU_PPUPATD1_WDOG0_SHIFT 6 /**< Shift value for SMU_WDOG0 */ 490 #define _SMU_PPUPATD1_WDOG0_MASK 0x40UL /**< Bit mask for SMU_WDOG0 */ 491 #define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 492 #define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 493 #define SMU_PPUPATD1_WDOG1 (0x1UL << 7) /**< WDOG1 Privileged Access */ 494 #define _SMU_PPUPATD1_WDOG1_SHIFT 7 /**< Shift value for SMU_WDOG1 */ 495 #define _SMU_PPUPATD1_WDOG1_MASK 0x80UL /**< Bit mask for SMU_WDOG1 */ 496 #define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 497 #define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 498 #define SMU_PPUPATD1_AMUXCP0 (0x1UL << 8) /**< AMUXCP0 Privileged Access */ 499 #define _SMU_PPUPATD1_AMUXCP0_SHIFT 8 /**< Shift value for SMU_AMUXCP0 */ 500 #define _SMU_PPUPATD1_AMUXCP0_MASK 0x100UL /**< Bit mask for SMU_AMUXCP0 */ 501 #define _SMU_PPUPATD1_AMUXCP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 502 #define SMU_PPUPATD1_AMUXCP0_DEFAULT (_SMU_PPUPATD1_AMUXCP0_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 503 #define SMU_PPUPATD1_RADIOAES (0x1UL << 9) /**< RADIOAES Privileged Access */ 504 #define _SMU_PPUPATD1_RADIOAES_SHIFT 9 /**< Shift value for SMU_RADIOAES */ 505 #define _SMU_PPUPATD1_RADIOAES_MASK 0x200UL /**< Bit mask for SMU_RADIOAES */ 506 #define _SMU_PPUPATD1_RADIOAES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 507 #define SMU_PPUPATD1_RADIOAES_DEFAULT (_SMU_PPUPATD1_RADIOAES_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 508 #define SMU_PPUPATD1_BUFC (0x1UL << 10) /**< BUFC Privileged Access */ 509 #define _SMU_PPUPATD1_BUFC_SHIFT 10 /**< Shift value for SMU_BUFC */ 510 #define _SMU_PPUPATD1_BUFC_MASK 0x400UL /**< Bit mask for SMU_BUFC */ 511 #define _SMU_PPUPATD1_BUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 512 #define SMU_PPUPATD1_BUFC_DEFAULT (_SMU_PPUPATD1_BUFC_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 513 #define SMU_PPUPATD1_SMU (0x1UL << 11) /**< SMU Privileged Access */ 514 #define _SMU_PPUPATD1_SMU_SHIFT 11 /**< Shift value for SMU_SMU */ 515 #define _SMU_PPUPATD1_SMU_MASK 0x800UL /**< Bit mask for SMU_SMU */ 516 #define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 517 #define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 518 #define SMU_PPUPATD1_AHBRADIO (0x1UL << 12) /**< AHBRADIO Privileged Access */ 519 #define _SMU_PPUPATD1_AHBRADIO_SHIFT 12 /**< Shift value for SMU_AHBRADIO */ 520 #define _SMU_PPUPATD1_AHBRADIO_MASK 0x1000UL /**< Bit mask for SMU_AHBRADIO */ 521 #define _SMU_PPUPATD1_AHBRADIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 522 #define SMU_PPUPATD1_AHBRADIO_DEFAULT (_SMU_PPUPATD1_AHBRADIO_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 523 #define SMU_PPUPATD1_SEMAILBOX (0x1UL << 13) /**< SE MAILBOX Privileged Access */ 524 #define _SMU_PPUPATD1_SEMAILBOX_SHIFT 13 /**< Shift value for SMU_SEMAILBOX */ 525 #define _SMU_PPUPATD1_SEMAILBOX_MASK 0x2000UL /**< Bit mask for SMU_SEMAILBOX */ 526 #define _SMU_PPUPATD1_SEMAILBOX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 527 #define SMU_PPUPATD1_SEMAILBOX_DEFAULT (_SMU_PPUPATD1_SEMAILBOX_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 528 529 /* Bit fields for SMU PPUSATD0 */ 530 #define _SMU_PPUSATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUSATD0 */ 531 #define _SMU_PPUSATD0_MASK 0xFFFFFFFEUL /**< Mask for SMU_PPUSATD0 */ 532 #define SMU_PPUSATD0_EMU (0x1UL << 1) /**< EMU Secure Access */ 533 #define _SMU_PPUSATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */ 534 #define _SMU_PPUSATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */ 535 #define _SMU_PPUSATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 536 #define SMU_PPUSATD0_EMU_DEFAULT (_SMU_PPUSATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 537 #define SMU_PPUSATD0_CMU (0x1UL << 2) /**< CMU Secure Access */ 538 #define _SMU_PPUSATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */ 539 #define _SMU_PPUSATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */ 540 #define _SMU_PPUSATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 541 #define SMU_PPUSATD0_CMU_DEFAULT (_SMU_PPUSATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 542 #define SMU_PPUSATD0_HFXO0 (0x1UL << 3) /**< HFXO0 Secure Access */ 543 #define _SMU_PPUSATD0_HFXO0_SHIFT 3 /**< Shift value for SMU_HFXO0 */ 544 #define _SMU_PPUSATD0_HFXO0_MASK 0x8UL /**< Bit mask for SMU_HFXO0 */ 545 #define _SMU_PPUSATD0_HFXO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 546 #define SMU_PPUSATD0_HFXO0_DEFAULT (_SMU_PPUSATD0_HFXO0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 547 #define SMU_PPUSATD0_HFRCO0 (0x1UL << 4) /**< HFRCO0 Secure Access */ 548 #define _SMU_PPUSATD0_HFRCO0_SHIFT 4 /**< Shift value for SMU_HFRCO0 */ 549 #define _SMU_PPUSATD0_HFRCO0_MASK 0x10UL /**< Bit mask for SMU_HFRCO0 */ 550 #define _SMU_PPUSATD0_HFRCO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 551 #define SMU_PPUSATD0_HFRCO0_DEFAULT (_SMU_PPUSATD0_HFRCO0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 552 #define SMU_PPUSATD0_FSRCO (0x1UL << 5) /**< FSRCO Secure Access */ 553 #define _SMU_PPUSATD0_FSRCO_SHIFT 5 /**< Shift value for SMU_FSRCO */ 554 #define _SMU_PPUSATD0_FSRCO_MASK 0x20UL /**< Bit mask for SMU_FSRCO */ 555 #define _SMU_PPUSATD0_FSRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 556 #define SMU_PPUSATD0_FSRCO_DEFAULT (_SMU_PPUSATD0_FSRCO_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 557 #define SMU_PPUSATD0_DPLL0 (0x1UL << 6) /**< DPLL0 Secure Access */ 558 #define _SMU_PPUSATD0_DPLL0_SHIFT 6 /**< Shift value for SMU_DPLL0 */ 559 #define _SMU_PPUSATD0_DPLL0_MASK 0x40UL /**< Bit mask for SMU_DPLL0 */ 560 #define _SMU_PPUSATD0_DPLL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 561 #define SMU_PPUSATD0_DPLL0_DEFAULT (_SMU_PPUSATD0_DPLL0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 562 #define SMU_PPUSATD0_LFXO (0x1UL << 7) /**< LFXO Secure Access */ 563 #define _SMU_PPUSATD0_LFXO_SHIFT 7 /**< Shift value for SMU_LFXO */ 564 #define _SMU_PPUSATD0_LFXO_MASK 0x80UL /**< Bit mask for SMU_LFXO */ 565 #define _SMU_PPUSATD0_LFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 566 #define SMU_PPUSATD0_LFXO_DEFAULT (_SMU_PPUSATD0_LFXO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 567 #define SMU_PPUSATD0_LFRCO (0x1UL << 8) /**< LFRCO Secure Access */ 568 #define _SMU_PPUSATD0_LFRCO_SHIFT 8 /**< Shift value for SMU_LFRCO */ 569 #define _SMU_PPUSATD0_LFRCO_MASK 0x100UL /**< Bit mask for SMU_LFRCO */ 570 #define _SMU_PPUSATD0_LFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 571 #define SMU_PPUSATD0_LFRCO_DEFAULT (_SMU_PPUSATD0_LFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 572 #define SMU_PPUSATD0_ULFRCO (0x1UL << 9) /**< ULFRCO Secure Access */ 573 #define _SMU_PPUSATD0_ULFRCO_SHIFT 9 /**< Shift value for SMU_ULFRCO */ 574 #define _SMU_PPUSATD0_ULFRCO_MASK 0x200UL /**< Bit mask for SMU_ULFRCO */ 575 #define _SMU_PPUSATD0_ULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 576 #define SMU_PPUSATD0_ULFRCO_DEFAULT (_SMU_PPUSATD0_ULFRCO_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 577 #define SMU_PPUSATD0_MSC (0x1UL << 10) /**< MSC Secure Access */ 578 #define _SMU_PPUSATD0_MSC_SHIFT 10 /**< Shift value for SMU_MSC */ 579 #define _SMU_PPUSATD0_MSC_MASK 0x400UL /**< Bit mask for SMU_MSC */ 580 #define _SMU_PPUSATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 581 #define SMU_PPUSATD0_MSC_DEFAULT (_SMU_PPUSATD0_MSC_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 582 #define SMU_PPUSATD0_ICACHE0 (0x1UL << 11) /**< ICACHE0 Secure Access */ 583 #define _SMU_PPUSATD0_ICACHE0_SHIFT 11 /**< Shift value for SMU_ICACHE0 */ 584 #define _SMU_PPUSATD0_ICACHE0_MASK 0x800UL /**< Bit mask for SMU_ICACHE0 */ 585 #define _SMU_PPUSATD0_ICACHE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 586 #define SMU_PPUSATD0_ICACHE0_DEFAULT (_SMU_PPUSATD0_ICACHE0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 587 #define SMU_PPUSATD0_PRS (0x1UL << 12) /**< PRS Secure Access */ 588 #define _SMU_PPUSATD0_PRS_SHIFT 12 /**< Shift value for SMU_PRS */ 589 #define _SMU_PPUSATD0_PRS_MASK 0x1000UL /**< Bit mask for SMU_PRS */ 590 #define _SMU_PPUSATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 591 #define SMU_PPUSATD0_PRS_DEFAULT (_SMU_PPUSATD0_PRS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 592 #define SMU_PPUSATD0_GPIO (0x1UL << 13) /**< GPIO Secure Access */ 593 #define _SMU_PPUSATD0_GPIO_SHIFT 13 /**< Shift value for SMU_GPIO */ 594 #define _SMU_PPUSATD0_GPIO_MASK 0x2000UL /**< Bit mask for SMU_GPIO */ 595 #define _SMU_PPUSATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 596 #define SMU_PPUSATD0_GPIO_DEFAULT (_SMU_PPUSATD0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 597 #define SMU_PPUSATD0_LDMA (0x1UL << 14) /**< LDMA Secure Access */ 598 #define _SMU_PPUSATD0_LDMA_SHIFT 14 /**< Shift value for SMU_LDMA */ 599 #define _SMU_PPUSATD0_LDMA_MASK 0x4000UL /**< Bit mask for SMU_LDMA */ 600 #define _SMU_PPUSATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 601 #define SMU_PPUSATD0_LDMA_DEFAULT (_SMU_PPUSATD0_LDMA_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 602 #define SMU_PPUSATD0_LDMAXBAR (0x1UL << 15) /**< LDMAXBAR Secure Access */ 603 #define _SMU_PPUSATD0_LDMAXBAR_SHIFT 15 /**< Shift value for SMU_LDMAXBAR */ 604 #define _SMU_PPUSATD0_LDMAXBAR_MASK 0x8000UL /**< Bit mask for SMU_LDMAXBAR */ 605 #define _SMU_PPUSATD0_LDMAXBAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 606 #define SMU_PPUSATD0_LDMAXBAR_DEFAULT (_SMU_PPUSATD0_LDMAXBAR_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 607 #define SMU_PPUSATD0_TIMER0 (0x1UL << 16) /**< TIMER0 Secure Access */ 608 #define _SMU_PPUSATD0_TIMER0_SHIFT 16 /**< Shift value for SMU_TIMER0 */ 609 #define _SMU_PPUSATD0_TIMER0_MASK 0x10000UL /**< Bit mask for SMU_TIMER0 */ 610 #define _SMU_PPUSATD0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 611 #define SMU_PPUSATD0_TIMER0_DEFAULT (_SMU_PPUSATD0_TIMER0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 612 #define SMU_PPUSATD0_TIMER1 (0x1UL << 17) /**< TIMER1 Secure Access */ 613 #define _SMU_PPUSATD0_TIMER1_SHIFT 17 /**< Shift value for SMU_TIMER1 */ 614 #define _SMU_PPUSATD0_TIMER1_MASK 0x20000UL /**< Bit mask for SMU_TIMER1 */ 615 #define _SMU_PPUSATD0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 616 #define SMU_PPUSATD0_TIMER1_DEFAULT (_SMU_PPUSATD0_TIMER1_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 617 #define SMU_PPUSATD0_TIMER2 (0x1UL << 18) /**< TIMER2 Secure Access */ 618 #define _SMU_PPUSATD0_TIMER2_SHIFT 18 /**< Shift value for SMU_TIMER2 */ 619 #define _SMU_PPUSATD0_TIMER2_MASK 0x40000UL /**< Bit mask for SMU_TIMER2 */ 620 #define _SMU_PPUSATD0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 621 #define SMU_PPUSATD0_TIMER2_DEFAULT (_SMU_PPUSATD0_TIMER2_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 622 #define SMU_PPUSATD0_TIMER3 (0x1UL << 19) /**< TIMER3 Secure Access */ 623 #define _SMU_PPUSATD0_TIMER3_SHIFT 19 /**< Shift value for SMU_TIMER3 */ 624 #define _SMU_PPUSATD0_TIMER3_MASK 0x80000UL /**< Bit mask for SMU_TIMER3 */ 625 #define _SMU_PPUSATD0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 626 #define SMU_PPUSATD0_TIMER3_DEFAULT (_SMU_PPUSATD0_TIMER3_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 627 #define SMU_PPUSATD0_USART0 (0x1UL << 20) /**< USART0 Secure Access */ 628 #define _SMU_PPUSATD0_USART0_SHIFT 20 /**< Shift value for SMU_USART0 */ 629 #define _SMU_PPUSATD0_USART0_MASK 0x100000UL /**< Bit mask for SMU_USART0 */ 630 #define _SMU_PPUSATD0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 631 #define SMU_PPUSATD0_USART0_DEFAULT (_SMU_PPUSATD0_USART0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 632 #define SMU_PPUSATD0_USART1 (0x1UL << 21) /**< USART1 Secure Access */ 633 #define _SMU_PPUSATD0_USART1_SHIFT 21 /**< Shift value for SMU_USART1 */ 634 #define _SMU_PPUSATD0_USART1_MASK 0x200000UL /**< Bit mask for SMU_USART1 */ 635 #define _SMU_PPUSATD0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 636 #define SMU_PPUSATD0_USART1_DEFAULT (_SMU_PPUSATD0_USART1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 637 #define SMU_PPUSATD0_USART2 (0x1UL << 22) /**< USART2 Secure Access */ 638 #define _SMU_PPUSATD0_USART2_SHIFT 22 /**< Shift value for SMU_USART2 */ 639 #define _SMU_PPUSATD0_USART2_MASK 0x400000UL /**< Bit mask for SMU_USART2 */ 640 #define _SMU_PPUSATD0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 641 #define SMU_PPUSATD0_USART2_DEFAULT (_SMU_PPUSATD0_USART2_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 642 #define SMU_PPUSATD0_BURTC (0x1UL << 23) /**< BURTC Secure Access */ 643 #define _SMU_PPUSATD0_BURTC_SHIFT 23 /**< Shift value for SMU_BURTC */ 644 #define _SMU_PPUSATD0_BURTC_MASK 0x800000UL /**< Bit mask for SMU_BURTC */ 645 #define _SMU_PPUSATD0_BURTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 646 #define SMU_PPUSATD0_BURTC_DEFAULT (_SMU_PPUSATD0_BURTC_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 647 #define SMU_PPUSATD0_I2C1 (0x1UL << 24) /**< I2C1 Secure Access */ 648 #define _SMU_PPUSATD0_I2C1_SHIFT 24 /**< Shift value for SMU_I2C1 */ 649 #define _SMU_PPUSATD0_I2C1_MASK 0x1000000UL /**< Bit mask for SMU_I2C1 */ 650 #define _SMU_PPUSATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 651 #define SMU_PPUSATD0_I2C1_DEFAULT (_SMU_PPUSATD0_I2C1_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 652 #define SMU_PPUSATD0_CHIPTESTCTRL (0x1UL << 25) /**< CHIPTESTCTRL Secure Access */ 653 #define _SMU_PPUSATD0_CHIPTESTCTRL_SHIFT 25 /**< Shift value for SMU_CHIPTESTCTRL */ 654 #define _SMU_PPUSATD0_CHIPTESTCTRL_MASK 0x2000000UL /**< Bit mask for SMU_CHIPTESTCTRL */ 655 #define _SMU_PPUSATD0_CHIPTESTCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 656 #define SMU_PPUSATD0_CHIPTESTCTRL_DEFAULT (_SMU_PPUSATD0_CHIPTESTCTRL_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 657 #define SMU_PPUSATD0_LVGD (0x1UL << 26) /**< LVGD Secure Access */ 658 #define _SMU_PPUSATD0_LVGD_SHIFT 26 /**< Shift value for SMU_LVGD */ 659 #define _SMU_PPUSATD0_LVGD_MASK 0x4000000UL /**< Bit mask for SMU_LVGD */ 660 #define _SMU_PPUSATD0_LVGD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 661 #define SMU_PPUSATD0_LVGD_DEFAULT (_SMU_PPUSATD0_LVGD_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 662 #define SMU_PPUSATD0_SYSCFG (0x1UL << 27) /**< SYSCFG Secure Access */ 663 #define _SMU_PPUSATD0_SYSCFG_SHIFT 27 /**< Shift value for SMU_SYSCFG */ 664 #define _SMU_PPUSATD0_SYSCFG_MASK 0x8000000UL /**< Bit mask for SMU_SYSCFG */ 665 #define _SMU_PPUSATD0_SYSCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 666 #define SMU_PPUSATD0_SYSCFG_DEFAULT (_SMU_PPUSATD0_SYSCFG_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 667 #define SMU_PPUSATD0_BURAM (0x1UL << 28) /**< BURAM Secure Access */ 668 #define _SMU_PPUSATD0_BURAM_SHIFT 28 /**< Shift value for SMU_BURAM */ 669 #define _SMU_PPUSATD0_BURAM_MASK 0x10000000UL /**< Bit mask for SMU_BURAM */ 670 #define _SMU_PPUSATD0_BURAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 671 #define SMU_PPUSATD0_BURAM_DEFAULT (_SMU_PPUSATD0_BURAM_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 672 #define SMU_PPUSATD0_IFADCDEBUG (0x1UL << 29) /**< IFADCDEBUG Secure Access */ 673 #define _SMU_PPUSATD0_IFADCDEBUG_SHIFT 29 /**< Shift value for SMU_IFADCDEBUG */ 674 #define _SMU_PPUSATD0_IFADCDEBUG_MASK 0x20000000UL /**< Bit mask for SMU_IFADCDEBUG */ 675 #define _SMU_PPUSATD0_IFADCDEBUG_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 676 #define SMU_PPUSATD0_IFADCDEBUG_DEFAULT (_SMU_PPUSATD0_IFADCDEBUG_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 677 #define SMU_PPUSATD0_GPCRC (0x1UL << 30) /**< GPCRC Secure Access */ 678 #define _SMU_PPUSATD0_GPCRC_SHIFT 30 /**< Shift value for SMU_GPCRC */ 679 #define _SMU_PPUSATD0_GPCRC_MASK 0x40000000UL /**< Bit mask for SMU_GPCRC */ 680 #define _SMU_PPUSATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 681 #define SMU_PPUSATD0_GPCRC_DEFAULT (_SMU_PPUSATD0_GPCRC_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 682 #define SMU_PPUSATD0_RTCC (0x1UL << 31) /**< RTCC Secure Access */ 683 #define _SMU_PPUSATD0_RTCC_SHIFT 31 /**< Shift value for SMU_RTCC */ 684 #define _SMU_PPUSATD0_RTCC_MASK 0x80000000UL /**< Bit mask for SMU_RTCC */ 685 #define _SMU_PPUSATD0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 686 #define SMU_PPUSATD0_RTCC_DEFAULT (_SMU_PPUSATD0_RTCC_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 687 688 /* Bit fields for SMU PPUSATD1 */ 689 #define _SMU_PPUSATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUSATD1 */ 690 #define _SMU_PPUSATD1_MASK 0x00003FFFUL /**< Mask for SMU_PPUSATD1 */ 691 #define SMU_PPUSATD1_LETIMER0 (0x1UL << 0) /**< LETIMER0 Secure Access */ 692 #define _SMU_PPUSATD1_LETIMER0_SHIFT 0 /**< Shift value for SMU_LETIMER0 */ 693 #define _SMU_PPUSATD1_LETIMER0_MASK 0x1UL /**< Bit mask for SMU_LETIMER0 */ 694 #define _SMU_PPUSATD1_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD1 */ 695 #define SMU_PPUSATD1_LETIMER0_DEFAULT (_SMU_PPUSATD1_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ 696 #define SMU_PPUSATD1_IADC0 (0x1UL << 1) /**< IADC0 Secure Access */ 697 #define _SMU_PPUSATD1_IADC0_SHIFT 1 /**< Shift value for SMU_IADC0 */ 698 #define _SMU_PPUSATD1_IADC0_MASK 0x2UL /**< Bit mask for SMU_IADC0 */ 699 #define _SMU_PPUSATD1_IADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD1 */ 700 #define SMU_PPUSATD1_IADC0_DEFAULT (_SMU_PPUSATD1_IADC0_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ 701 #define SMU_PPUSATD1_ACMP0 (0x1UL << 2) /**< ACMP0 Secure Access */ 702 #define _SMU_PPUSATD1_ACMP0_SHIFT 2 /**< Shift value for SMU_ACMP0 */ 703 #define _SMU_PPUSATD1_ACMP0_MASK 0x4UL /**< Bit mask for SMU_ACMP0 */ 704 #define _SMU_PPUSATD1_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD1 */ 705 #define SMU_PPUSATD1_ACMP0_DEFAULT (_SMU_PPUSATD1_ACMP0_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ 706 #define SMU_PPUSATD1_ACMP1 (0x1UL << 3) /**< ACMP1 Secure Access */ 707 #define _SMU_PPUSATD1_ACMP1_SHIFT 3 /**< Shift value for SMU_ACMP1 */ 708 #define _SMU_PPUSATD1_ACMP1_MASK 0x8UL /**< Bit mask for SMU_ACMP1 */ 709 #define _SMU_PPUSATD1_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD1 */ 710 #define SMU_PPUSATD1_ACMP1_DEFAULT (_SMU_PPUSATD1_ACMP1_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ 711 #define SMU_PPUSATD1_I2C0 (0x1UL << 4) /**< I2C0 Secure Access */ 712 #define _SMU_PPUSATD1_I2C0_SHIFT 4 /**< Shift value for SMU_I2C0 */ 713 #define _SMU_PPUSATD1_I2C0_MASK 0x10UL /**< Bit mask for SMU_I2C0 */ 714 #define _SMU_PPUSATD1_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD1 */ 715 #define SMU_PPUSATD1_I2C0_DEFAULT (_SMU_PPUSATD1_I2C0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ 716 #define SMU_PPUSATD1_HFRCOEM23 (0x1UL << 5) /**< HFRCOEM23 Secure Access */ 717 #define _SMU_PPUSATD1_HFRCOEM23_SHIFT 5 /**< Shift value for SMU_HFRCOEM23 */ 718 #define _SMU_PPUSATD1_HFRCOEM23_MASK 0x20UL /**< Bit mask for SMU_HFRCOEM23 */ 719 #define _SMU_PPUSATD1_HFRCOEM23_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD1 */ 720 #define SMU_PPUSATD1_HFRCOEM23_DEFAULT (_SMU_PPUSATD1_HFRCOEM23_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ 721 #define SMU_PPUSATD1_WDOG0 (0x1UL << 6) /**< WDOG0 Secure Access */ 722 #define _SMU_PPUSATD1_WDOG0_SHIFT 6 /**< Shift value for SMU_WDOG0 */ 723 #define _SMU_PPUSATD1_WDOG0_MASK 0x40UL /**< Bit mask for SMU_WDOG0 */ 724 #define _SMU_PPUSATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD1 */ 725 #define SMU_PPUSATD1_WDOG0_DEFAULT (_SMU_PPUSATD1_WDOG0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ 726 #define SMU_PPUSATD1_WDOG1 (0x1UL << 7) /**< WDOG1 Secure Access */ 727 #define _SMU_PPUSATD1_WDOG1_SHIFT 7 /**< Shift value for SMU_WDOG1 */ 728 #define _SMU_PPUSATD1_WDOG1_MASK 0x80UL /**< Bit mask for SMU_WDOG1 */ 729 #define _SMU_PPUSATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD1 */ 730 #define SMU_PPUSATD1_WDOG1_DEFAULT (_SMU_PPUSATD1_WDOG1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ 731 #define SMU_PPUSATD1_AMUXCP0 (0x1UL << 8) /**< AMUXCP0 Secure Access */ 732 #define _SMU_PPUSATD1_AMUXCP0_SHIFT 8 /**< Shift value for SMU_AMUXCP0 */ 733 #define _SMU_PPUSATD1_AMUXCP0_MASK 0x100UL /**< Bit mask for SMU_AMUXCP0 */ 734 #define _SMU_PPUSATD1_AMUXCP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD1 */ 735 #define SMU_PPUSATD1_AMUXCP0_DEFAULT (_SMU_PPUSATD1_AMUXCP0_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ 736 #define SMU_PPUSATD1_RADIOAES (0x1UL << 9) /**< RADIOAES Secure Access */ 737 #define _SMU_PPUSATD1_RADIOAES_SHIFT 9 /**< Shift value for SMU_RADIOAES */ 738 #define _SMU_PPUSATD1_RADIOAES_MASK 0x200UL /**< Bit mask for SMU_RADIOAES */ 739 #define _SMU_PPUSATD1_RADIOAES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD1 */ 740 #define SMU_PPUSATD1_RADIOAES_DEFAULT (_SMU_PPUSATD1_RADIOAES_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ 741 #define SMU_PPUSATD1_BUFC (0x1UL << 10) /**< BUFC Secure Access */ 742 #define _SMU_PPUSATD1_BUFC_SHIFT 10 /**< Shift value for SMU_BUFC */ 743 #define _SMU_PPUSATD1_BUFC_MASK 0x400UL /**< Bit mask for SMU_BUFC */ 744 #define _SMU_PPUSATD1_BUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD1 */ 745 #define SMU_PPUSATD1_BUFC_DEFAULT (_SMU_PPUSATD1_BUFC_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ 746 #define SMU_PPUSATD1_SMU (0x1UL << 11) /**< SMU Secure Access */ 747 #define _SMU_PPUSATD1_SMU_SHIFT 11 /**< Shift value for SMU_SMU */ 748 #define _SMU_PPUSATD1_SMU_MASK 0x800UL /**< Bit mask for SMU_SMU */ 749 #define _SMU_PPUSATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD1 */ 750 #define SMU_PPUSATD1_SMU_DEFAULT (_SMU_PPUSATD1_SMU_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ 751 #define SMU_PPUSATD1_AHBRADIO (0x1UL << 12) /**< AHBRADIO Secure Access */ 752 #define _SMU_PPUSATD1_AHBRADIO_SHIFT 12 /**< Shift value for SMU_AHBRADIO */ 753 #define _SMU_PPUSATD1_AHBRADIO_MASK 0x1000UL /**< Bit mask for SMU_AHBRADIO */ 754 #define _SMU_PPUSATD1_AHBRADIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD1 */ 755 #define SMU_PPUSATD1_AHBRADIO_DEFAULT (_SMU_PPUSATD1_AHBRADIO_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ 756 #define SMU_PPUSATD1_SEMAILBOX (0x1UL << 13) /**< SE MAILBOX Secure Access */ 757 #define _SMU_PPUSATD1_SEMAILBOX_SHIFT 13 /**< Shift value for SMU_SEMAILBOX */ 758 #define _SMU_PPUSATD1_SEMAILBOX_MASK 0x2000UL /**< Bit mask for SMU_SEMAILBOX */ 759 #define _SMU_PPUSATD1_SEMAILBOX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUSATD1 */ 760 #define SMU_PPUSATD1_SEMAILBOX_DEFAULT (_SMU_PPUSATD1_SEMAILBOX_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ 761 762 /* Bit fields for SMU PPUFS */ 763 #define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ 764 #define _SMU_PPUFS_MASK 0x000000FFUL /**< Mask for SMU_PPUFS */ 765 #define _SMU_PPUFS_PPUFSPERIPHID_SHIFT 0 /**< Shift value for SMU_PPUFSPERIPHID */ 766 #define _SMU_PPUFS_PPUFSPERIPHID_MASK 0xFFUL /**< Bit mask for SMU_PPUFSPERIPHID */ 767 #define _SMU_PPUFS_PPUFSPERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ 768 #define SMU_PPUFS_PPUFSPERIPHID_DEFAULT (_SMU_PPUFS_PPUFSPERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ 769 770 /* Bit fields for SMU BMPUPATD0 */ 771 #define _SMU_BMPUPATD0_RESETVALUE 0x0000003FUL /**< Default value for SMU_BMPUPATD0 */ 772 #define _SMU_BMPUPATD0_MASK 0x0000003FUL /**< Mask for SMU_BMPUPATD0 */ 773 #define SMU_BMPUPATD0_RADIOAES (0x1UL << 0) /**< RADIO AES DMA privileged mode */ 774 #define _SMU_BMPUPATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */ 775 #define _SMU_BMPUPATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */ 776 #define _SMU_BMPUPATD0_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ 777 #define SMU_BMPUPATD0_RADIOAES_DEFAULT (_SMU_BMPUPATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ 778 #define SMU_BMPUPATD0_RADIOSUBSYSTEM (0x1UL << 1) /**< RADIO subsystem manager privileged mode */ 779 #define _SMU_BMPUPATD0_RADIOSUBSYSTEM_SHIFT 1 /**< Shift value for SMU_RADIOSUBSYSTEM */ 780 #define _SMU_BMPUPATD0_RADIOSUBSYSTEM_MASK 0x2UL /**< Bit mask for SMU_RADIOSUBSYSTEM */ 781 #define _SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ 782 #define SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ 783 #define SMU_BMPUPATD0_BUFC (0x1UL << 2) /**< RADIO BUFFER controller privileged mode */ 784 #define _SMU_BMPUPATD0_BUFC_SHIFT 2 /**< Shift value for SMU_BUFC */ 785 #define _SMU_BMPUPATD0_BUFC_MASK 0x4UL /**< Bit mask for SMU_BUFC */ 786 #define _SMU_BMPUPATD0_BUFC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ 787 #define SMU_BMPUPATD0_BUFC_DEFAULT (_SMU_BMPUPATD0_BUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ 788 #define SMU_BMPUPATD0_RADIOIFADCDEBUG (0x1UL << 3) /**< RADIO IFADC debug privileged mode */ 789 #define _SMU_BMPUPATD0_RADIOIFADCDEBUG_SHIFT 3 /**< Shift value for SMU_RADIOIFADCDEBUG */ 790 #define _SMU_BMPUPATD0_RADIOIFADCDEBUG_MASK 0x8UL /**< Bit mask for SMU_RADIOIFADCDEBUG */ 791 #define _SMU_BMPUPATD0_RADIOIFADCDEBUG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ 792 #define SMU_BMPUPATD0_RADIOIFADCDEBUG_DEFAULT (_SMU_BMPUPATD0_RADIOIFADCDEBUG_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ 793 #define SMU_BMPUPATD0_LDMA (0x1UL << 4) /**< MCU LDMA privileged mode */ 794 #define _SMU_BMPUPATD0_LDMA_SHIFT 4 /**< Shift value for SMU_LDMA */ 795 #define _SMU_BMPUPATD0_LDMA_MASK 0x10UL /**< Bit mask for SMU_LDMA */ 796 #define _SMU_BMPUPATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ 797 #define SMU_BMPUPATD0_LDMA_DEFAULT (_SMU_BMPUPATD0_LDMA_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ 798 #define SMU_BMPUPATD0_SEDMA (0x1UL << 5) /**< SE mailbox DMA privileged mode */ 799 #define _SMU_BMPUPATD0_SEDMA_SHIFT 5 /**< Shift value for SMU_SEDMA */ 800 #define _SMU_BMPUPATD0_SEDMA_MASK 0x20UL /**< Bit mask for SMU_SEDMA */ 801 #define _SMU_BMPUPATD0_SEDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ 802 #define SMU_BMPUPATD0_SEDMA_DEFAULT (_SMU_BMPUPATD0_SEDMA_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ 803 804 /* Bit fields for SMU BMPUSATD0 */ 805 #define _SMU_BMPUSATD0_RESETVALUE 0x0000003FUL /**< Default value for SMU_BMPUSATD0 */ 806 #define _SMU_BMPUSATD0_MASK 0x0000003FUL /**< Mask for SMU_BMPUSATD0 */ 807 #define SMU_BMPUSATD0_RADIOAES (0x1UL << 0) /**< RADIO AES DMA secure mode */ 808 #define _SMU_BMPUSATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */ 809 #define _SMU_BMPUSATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */ 810 #define _SMU_BMPUSATD0_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ 811 #define SMU_BMPUSATD0_RADIOAES_DEFAULT (_SMU_BMPUSATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ 812 #define SMU_BMPUSATD0_RADIOSUBSYSTEM (0x1UL << 1) /**< RADIO subsystem manager secure mode */ 813 #define _SMU_BMPUSATD0_RADIOSUBSYSTEM_SHIFT 1 /**< Shift value for SMU_RADIOSUBSYSTEM */ 814 #define _SMU_BMPUSATD0_RADIOSUBSYSTEM_MASK 0x2UL /**< Bit mask for SMU_RADIOSUBSYSTEM */ 815 #define _SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ 816 #define SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ 817 #define SMU_BMPUSATD0_BUFC (0x1UL << 2) /**< RADIO BUFFER controller secure mode */ 818 #define _SMU_BMPUSATD0_BUFC_SHIFT 2 /**< Shift value for SMU_BUFC */ 819 #define _SMU_BMPUSATD0_BUFC_MASK 0x4UL /**< Bit mask for SMU_BUFC */ 820 #define _SMU_BMPUSATD0_BUFC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ 821 #define SMU_BMPUSATD0_BUFC_DEFAULT (_SMU_BMPUSATD0_BUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ 822 #define SMU_BMPUSATD0_RADIOIFADCDEBUG (0x1UL << 3) /**< RADIO IFADC debug secure mode */ 823 #define _SMU_BMPUSATD0_RADIOIFADCDEBUG_SHIFT 3 /**< Shift value for SMU_RADIOIFADCDEBUG */ 824 #define _SMU_BMPUSATD0_RADIOIFADCDEBUG_MASK 0x8UL /**< Bit mask for SMU_RADIOIFADCDEBUG */ 825 #define _SMU_BMPUSATD0_RADIOIFADCDEBUG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ 826 #define SMU_BMPUSATD0_RADIOIFADCDEBUG_DEFAULT (_SMU_BMPUSATD0_RADIOIFADCDEBUG_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ 827 #define SMU_BMPUSATD0_LDMA (0x1UL << 4) /**< MCU LDMA secure mode */ 828 #define _SMU_BMPUSATD0_LDMA_SHIFT 4 /**< Shift value for SMU_LDMA */ 829 #define _SMU_BMPUSATD0_LDMA_MASK 0x10UL /**< Bit mask for SMU_LDMA */ 830 #define _SMU_BMPUSATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ 831 #define SMU_BMPUSATD0_LDMA_DEFAULT (_SMU_BMPUSATD0_LDMA_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ 832 #define SMU_BMPUSATD0_SEDMA (0x1UL << 5) /**< MCU to SE mailbox DMA secure mode */ 833 #define _SMU_BMPUSATD0_SEDMA_SHIFT 5 /**< Shift value for SMU_SEDMA */ 834 #define _SMU_BMPUSATD0_SEDMA_MASK 0x20UL /**< Bit mask for SMU_SEDMA */ 835 #define _SMU_BMPUSATD0_SEDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ 836 #define SMU_BMPUSATD0_SEDMA_DEFAULT (_SMU_BMPUSATD0_SEDMA_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ 837 838 /* Bit fields for SMU BMPUFS */ 839 #define _SMU_BMPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_BMPUFS */ 840 #define _SMU_BMPUFS_MASK 0x000000FFUL /**< Mask for SMU_BMPUFS */ 841 #define _SMU_BMPUFS_BMPUFSMASTERID_SHIFT 0 /**< Shift value for SMU_BMPUFSMASTERID */ 842 #define _SMU_BMPUFS_BMPUFSMASTERID_MASK 0xFFUL /**< Bit mask for SMU_BMPUFSMASTERID */ 843 #define _SMU_BMPUFS_BMPUFSMASTERID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUFS */ 844 #define SMU_BMPUFS_BMPUFSMASTERID_DEFAULT (_SMU_BMPUFS_BMPUFSMASTERID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUFS */ 845 846 /* Bit fields for SMU BMPUFSADDR */ 847 #define _SMU_BMPUFSADDR_RESETVALUE 0x00000000UL /**< Default value for SMU_BMPUFSADDR */ 848 #define _SMU_BMPUFSADDR_MASK 0xFFFFFFFFUL /**< Mask for SMU_BMPUFSADDR */ 849 #define _SMU_BMPUFSADDR_BMPUFSADDR_SHIFT 0 /**< Shift value for SMU_BMPUFSADDR */ 850 #define _SMU_BMPUFSADDR_BMPUFSADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SMU_BMPUFSADDR */ 851 #define _SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUFSADDR */ 852 #define SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT (_SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUFSADDR */ 853 854 /* Bit fields for SMU ESAURTYPES0 */ 855 #define _SMU_ESAURTYPES0_RESETVALUE 0x00000000UL /**< Default value for SMU_ESAURTYPES0 */ 856 #define _SMU_ESAURTYPES0_MASK 0x00001000UL /**< Mask for SMU_ESAURTYPES0 */ 857 #define SMU_ESAURTYPES0_ESAUR3NS (0x1UL << 12) /**< Region 3 Non-Secure */ 858 #define _SMU_ESAURTYPES0_ESAUR3NS_SHIFT 12 /**< Shift value for SMU_ESAUR3NS */ 859 #define _SMU_ESAURTYPES0_ESAUR3NS_MASK 0x1000UL /**< Bit mask for SMU_ESAUR3NS */ 860 #define _SMU_ESAURTYPES0_ESAUR3NS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_ESAURTYPES0 */ 861 #define SMU_ESAURTYPES0_ESAUR3NS_DEFAULT (_SMU_ESAURTYPES0_ESAUR3NS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAURTYPES0 */ 862 863 /* Bit fields for SMU ESAURTYPES1 */ 864 #define _SMU_ESAURTYPES1_RESETVALUE 0x00000000UL /**< Default value for SMU_ESAURTYPES1 */ 865 #define _SMU_ESAURTYPES1_MASK 0x00001000UL /**< Mask for SMU_ESAURTYPES1 */ 866 #define SMU_ESAURTYPES1_ESAUR11NS (0x1UL << 12) /**< Region 11 Non-Secure */ 867 #define _SMU_ESAURTYPES1_ESAUR11NS_SHIFT 12 /**< Shift value for SMU_ESAUR11NS */ 868 #define _SMU_ESAURTYPES1_ESAUR11NS_MASK 0x1000UL /**< Bit mask for SMU_ESAUR11NS */ 869 #define _SMU_ESAURTYPES1_ESAUR11NS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_ESAURTYPES1 */ 870 #define SMU_ESAURTYPES1_ESAUR11NS_DEFAULT (_SMU_ESAURTYPES1_ESAUR11NS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAURTYPES1 */ 871 872 /* Bit fields for SMU ESAUMRB01 */ 873 #define _SMU_ESAUMRB01_RESETVALUE 0x02000000UL /**< Default value for SMU_ESAUMRB01 */ 874 #define _SMU_ESAUMRB01_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB01 */ 875 #define _SMU_ESAUMRB01_ESAUMRB01_SHIFT 12 /**< Shift value for SMU_ESAUMRB01 */ 876 #define _SMU_ESAUMRB01_ESAUMRB01_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB01 */ 877 #define _SMU_ESAUMRB01_ESAUMRB01_DEFAULT 0x00002000UL /**< Mode DEFAULT for SMU_ESAUMRB01 */ 878 #define SMU_ESAUMRB01_ESAUMRB01_DEFAULT (_SMU_ESAUMRB01_ESAUMRB01_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB01 */ 879 880 /* Bit fields for SMU ESAUMRB12 */ 881 #define _SMU_ESAUMRB12_RESETVALUE 0x04000000UL /**< Default value for SMU_ESAUMRB12 */ 882 #define _SMU_ESAUMRB12_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB12 */ 883 #define _SMU_ESAUMRB12_ESAUMRB12_SHIFT 12 /**< Shift value for SMU_ESAUMRB12 */ 884 #define _SMU_ESAUMRB12_ESAUMRB12_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB12 */ 885 #define _SMU_ESAUMRB12_ESAUMRB12_DEFAULT 0x00004000UL /**< Mode DEFAULT for SMU_ESAUMRB12 */ 886 #define SMU_ESAUMRB12_ESAUMRB12_DEFAULT (_SMU_ESAUMRB12_ESAUMRB12_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB12 */ 887 888 /* Bit fields for SMU ESAUMRB45 */ 889 #define _SMU_ESAUMRB45_RESETVALUE 0x02000000UL /**< Default value for SMU_ESAUMRB45 */ 890 #define _SMU_ESAUMRB45_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB45 */ 891 #define _SMU_ESAUMRB45_ESAUMRB45_SHIFT 12 /**< Shift value for SMU_ESAUMRB45 */ 892 #define _SMU_ESAUMRB45_ESAUMRB45_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB45 */ 893 #define _SMU_ESAUMRB45_ESAUMRB45_DEFAULT 0x00002000UL /**< Mode DEFAULT for SMU_ESAUMRB45 */ 894 #define SMU_ESAUMRB45_ESAUMRB45_DEFAULT (_SMU_ESAUMRB45_ESAUMRB45_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB45 */ 895 896 /* Bit fields for SMU ESAUMRB56 */ 897 #define _SMU_ESAUMRB56_RESETVALUE 0x04000000UL /**< Default value for SMU_ESAUMRB56 */ 898 #define _SMU_ESAUMRB56_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB56 */ 899 #define _SMU_ESAUMRB56_ESAUMRB56_SHIFT 12 /**< Shift value for SMU_ESAUMRB56 */ 900 #define _SMU_ESAUMRB56_ESAUMRB56_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB56 */ 901 #define _SMU_ESAUMRB56_ESAUMRB56_DEFAULT 0x00004000UL /**< Mode DEFAULT for SMU_ESAUMRB56 */ 902 #define SMU_ESAUMRB56_ESAUMRB56_DEFAULT (_SMU_ESAUMRB56_ESAUMRB56_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB56 */ 903 904 /** @} End of group EFR32MG21_SMU_BitFields */ 905 /** @} End of group EFR32MG21_SMU */ 906 /** @} End of group Parts */ 907 908 #endif // EFR32MG21_SMU_H 909
