1 /**************************************************************************//** 2 * @file 3 * @brief EFR32MG21 SEMAILBOX register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2024 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32MG21_SEMAILBOX_H 31 #define EFR32MG21_SEMAILBOX_H 32 33 /**************************************************************************//** 34 * @addtogroup Parts 35 * @{ 36 ******************************************************************************/ 37 /**************************************************************************//** 38 * @defgroup EFR32MG21_SEMAILBOX_HOST SEMAILBOX_HOST 39 * @{ 40 * @brief EFR32MG21 SEMAILBOX_HOST Register Declaration. 41 *****************************************************************************/ 42 43 /** SEMAILBOX_HOST FIFO Register Group Declaration. */ 44 typedef struct semailbox_fifo_typedef{ 45 __IOM uint32_t DATA; /**< RX/TX FIFO DATA */ 46 } SEMAILBOX_FIFO_TypeDef; 47 48 /** SEMAILBOX_HOST Register Declaration. */ 49 typedef struct semailbox_host_typedef{ 50 SEMAILBOX_FIFO_TypeDef FIFO[16U]; /**< RX/TX FIFO */ 51 __IM uint32_t TX_STATUS; /**< TX Status */ 52 __IM uint32_t RX_STATUS; /**< RX Status */ 53 __IM uint32_t TX_PROT; /**< TX Protection */ 54 __IM uint32_t RX_PROT; /**< RX Protection */ 55 __IOM uint32_t TX_HEADER; /**< TX Header */ 56 __IM uint32_t RX_HEADER; /**< RX Header */ 57 __IOM uint32_t CONFIGURATION; /**< Configuration */ 58 } SEMAILBOX_HOST_TypeDef; 59 /** @} End of group EFR32MG21_SEMAILBOX_HOST */ 60 61 /**************************************************************************//** 62 * @addtogroup EFR32MG21_SEMAILBOX_HOST 63 * @{ 64 * @defgroup EFR32MG21_SEMAILBOX_HOST_BitFields SEMAILBOX_HOST Bit Fields 65 * @{ 66 *****************************************************************************/ 67 68 /* Bit fields for SEMAILBOX DATA */ 69 #define _SEMAILBOX_DATA_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_DATA */ 70 #define _SEMAILBOX_DATA_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_DATA */ 71 #define _SEMAILBOX_DATA_DATA_SHIFT 0 /**< Shift value for SEMAILBOX_DATA */ 72 #define _SEMAILBOX_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_DATA */ 73 #define _SEMAILBOX_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_DATA */ 74 #define SEMAILBOX_DATA_DATA_DEFAULT (_SEMAILBOX_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_DATA */ 75 76 /* Bit fields for SEMAILBOX TX_STATUS */ 77 #define _SEMAILBOX_TX_STATUS_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_TX_STATUS */ 78 #define _SEMAILBOX_TX_STATUS_MASK 0x00B0FFFFUL /**< Mask for SEMAILBOX_TX_STATUS */ 79 #define _SEMAILBOX_TX_STATUS_BYTEREM_SHIFT 0 /**< Shift value for SEMAILBOX_BYTEREM */ 80 #define _SEMAILBOX_TX_STATUS_BYTEREM_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_BYTEREM */ 81 #define _SEMAILBOX_TX_STATUS_BYTEREM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ 82 #define SEMAILBOX_TX_STATUS_BYTEREM_DEFAULT (_SEMAILBOX_TX_STATUS_BYTEREM_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ 83 #define SEMAILBOX_TX_STATUS_TXINT (0x1UL << 20) /**< Interrupt Status */ 84 #define _SEMAILBOX_TX_STATUS_TXINT_SHIFT 20 /**< Shift value for SEMAILBOX_TXINT */ 85 #define _SEMAILBOX_TX_STATUS_TXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_TXINT */ 86 #define _SEMAILBOX_TX_STATUS_TXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ 87 #define SEMAILBOX_TX_STATUS_TXINT_DEFAULT (_SEMAILBOX_TX_STATUS_TXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ 88 #define SEMAILBOX_TX_STATUS_TXFULL (0x1UL << 21) /**< TX FIFO Full */ 89 #define _SEMAILBOX_TX_STATUS_TXFULL_SHIFT 21 /**< Shift value for SEMAILBOX_TXFULL */ 90 #define _SEMAILBOX_TX_STATUS_TXFULL_MASK 0x200000UL /**< Bit mask for SEMAILBOX_TXFULL */ 91 #define _SEMAILBOX_TX_STATUS_TXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ 92 #define SEMAILBOX_TX_STATUS_TXFULL_DEFAULT (_SEMAILBOX_TX_STATUS_TXFULL_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ 93 #define SEMAILBOX_TX_STATUS_TXERROR (0x1UL << 23) /**< TX Error Flag */ 94 #define _SEMAILBOX_TX_STATUS_TXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_TXERROR */ 95 #define _SEMAILBOX_TX_STATUS_TXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_TXERROR */ 96 #define _SEMAILBOX_TX_STATUS_TXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ 97 #define SEMAILBOX_TX_STATUS_TXERROR_DEFAULT (_SEMAILBOX_TX_STATUS_TXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ 98 99 /* Bit fields for SEMAILBOX RX_STATUS */ 100 #define _SEMAILBOX_RX_STATUS_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_RX_STATUS */ 101 #define _SEMAILBOX_RX_STATUS_MASK 0x00FFFFFFUL /**< Mask for SEMAILBOX_RX_STATUS */ 102 #define _SEMAILBOX_RX_STATUS_BYTEREM_SHIFT 0 /**< Shift value for SEMAILBOX_BYTEREM */ 103 #define _SEMAILBOX_RX_STATUS_BYTEREM_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_BYTEREM */ 104 #define _SEMAILBOX_RX_STATUS_BYTEREM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ 105 #define SEMAILBOX_RX_STATUS_BYTEREM_DEFAULT (_SEMAILBOX_RX_STATUS_BYTEREM_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ 106 #define _SEMAILBOX_RX_STATUS_STATUS_SHIFT 16 /**< Shift value for SEMAILBOX_STATUS */ 107 #define _SEMAILBOX_RX_STATUS_STATUS_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_STATUS */ 108 #define _SEMAILBOX_RX_STATUS_STATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ 109 #define SEMAILBOX_RX_STATUS_STATUS_DEFAULT (_SEMAILBOX_RX_STATUS_STATUS_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ 110 #define SEMAILBOX_RX_STATUS_RXINT (0x1UL << 20) /**< Interrupt Status */ 111 #define _SEMAILBOX_RX_STATUS_RXINT_SHIFT 20 /**< Shift value for SEMAILBOX_RXINT */ 112 #define _SEMAILBOX_RX_STATUS_RXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_RXINT */ 113 #define _SEMAILBOX_RX_STATUS_RXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ 114 #define SEMAILBOX_RX_STATUS_RXINT_DEFAULT (_SEMAILBOX_RX_STATUS_RXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ 115 #define SEMAILBOX_RX_STATUS_RXEMPTY (0x1UL << 21) /**< RX FIFO Empty */ 116 #define _SEMAILBOX_RX_STATUS_RXEMPTY_SHIFT 21 /**< Shift value for SEMAILBOX_RXEMPTY */ 117 #define _SEMAILBOX_RX_STATUS_RXEMPTY_MASK 0x200000UL /**< Bit mask for SEMAILBOX_RXEMPTY */ 118 #define _SEMAILBOX_RX_STATUS_RXEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ 119 #define SEMAILBOX_RX_STATUS_RXEMPTY_DEFAULT (_SEMAILBOX_RX_STATUS_RXEMPTY_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ 120 #define SEMAILBOX_RX_STATUS_RXHEADER (0x1UL << 22) /**< RX Header */ 121 #define _SEMAILBOX_RX_STATUS_RXHEADER_SHIFT 22 /**< Shift value for SEMAILBOX_RXHEADER */ 122 #define _SEMAILBOX_RX_STATUS_RXHEADER_MASK 0x400000UL /**< Bit mask for SEMAILBOX_RXHEADER */ 123 #define _SEMAILBOX_RX_STATUS_RXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ 124 #define SEMAILBOX_RX_STATUS_RXHEADER_DEFAULT (_SEMAILBOX_RX_STATUS_RXHEADER_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ 125 #define SEMAILBOX_RX_STATUS_RXERROR (0x1UL << 23) /**< RX Error Flag */ 126 #define _SEMAILBOX_RX_STATUS_RXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_RXERROR */ 127 #define _SEMAILBOX_RX_STATUS_RXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_RXERROR */ 128 #define _SEMAILBOX_RX_STATUS_RXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ 129 #define SEMAILBOX_RX_STATUS_RXERROR_DEFAULT (_SEMAILBOX_RX_STATUS_RXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ 130 131 /* Bit fields for SEMAILBOX TX_PROT */ 132 #define _SEMAILBOX_TX_PROT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_TX_PROT */ 133 #define _SEMAILBOX_TX_PROT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_TX_PROT */ 134 #define SEMAILBOX_TX_PROT_UNPROTECTED (0x1UL << 21) /**< Unprotected */ 135 #define _SEMAILBOX_TX_PROT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ 136 #define _SEMAILBOX_TX_PROT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ 137 #define _SEMAILBOX_TX_PROT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ 138 #define SEMAILBOX_TX_PROT_UNPROTECTED_DEFAULT (_SEMAILBOX_TX_PROT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ 139 #define SEMAILBOX_TX_PROT_PRIV (0x1UL << 22) /**< Privileged Access */ 140 #define _SEMAILBOX_TX_PROT_PRIV_SHIFT 22 /**< Shift value for SEMAILBOX_PRIV */ 141 #define _SEMAILBOX_TX_PROT_PRIV_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIV */ 142 #define _SEMAILBOX_TX_PROT_PRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ 143 #define SEMAILBOX_TX_PROT_PRIV_DEFAULT (_SEMAILBOX_TX_PROT_PRIV_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ 144 #define SEMAILBOX_TX_PROT_NONSEC (0x1UL << 23) /**< Non-Secure Access */ 145 #define _SEMAILBOX_TX_PROT_NONSEC_SHIFT 23 /**< Shift value for SEMAILBOX_NONSEC */ 146 #define _SEMAILBOX_TX_PROT_NONSEC_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSEC */ 147 #define _SEMAILBOX_TX_PROT_NONSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ 148 #define SEMAILBOX_TX_PROT_NONSEC_DEFAULT (_SEMAILBOX_TX_PROT_NONSEC_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ 149 #define _SEMAILBOX_TX_PROT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ 150 #define _SEMAILBOX_TX_PROT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ 151 #define _SEMAILBOX_TX_PROT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ 152 #define SEMAILBOX_TX_PROT_USER_DEFAULT (_SEMAILBOX_TX_PROT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ 153 154 /* Bit fields for SEMAILBOX RX_PROT */ 155 #define _SEMAILBOX_RX_PROT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_RX_PROT */ 156 #define _SEMAILBOX_RX_PROT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_RX_PROT */ 157 #define SEMAILBOX_RX_PROT_UNPROTECTED (0x1UL << 21) /**< Unprotected */ 158 #define _SEMAILBOX_RX_PROT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ 159 #define _SEMAILBOX_RX_PROT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ 160 #define _SEMAILBOX_RX_PROT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ 161 #define SEMAILBOX_RX_PROT_UNPROTECTED_DEFAULT (_SEMAILBOX_RX_PROT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ 162 #define SEMAILBOX_RX_PROT_PRIV (0x1UL << 22) /**< Privileged Access */ 163 #define _SEMAILBOX_RX_PROT_PRIV_SHIFT 22 /**< Shift value for SEMAILBOX_PRIV */ 164 #define _SEMAILBOX_RX_PROT_PRIV_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIV */ 165 #define _SEMAILBOX_RX_PROT_PRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ 166 #define SEMAILBOX_RX_PROT_PRIV_DEFAULT (_SEMAILBOX_RX_PROT_PRIV_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ 167 #define SEMAILBOX_RX_PROT_NONSEC (0x1UL << 23) /**< Non-Secure Access */ 168 #define _SEMAILBOX_RX_PROT_NONSEC_SHIFT 23 /**< Shift value for SEMAILBOX_NONSEC */ 169 #define _SEMAILBOX_RX_PROT_NONSEC_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSEC */ 170 #define _SEMAILBOX_RX_PROT_NONSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ 171 #define SEMAILBOX_RX_PROT_NONSEC_DEFAULT (_SEMAILBOX_RX_PROT_NONSEC_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ 172 #define _SEMAILBOX_RX_PROT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ 173 #define _SEMAILBOX_RX_PROT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ 174 #define _SEMAILBOX_RX_PROT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ 175 #define SEMAILBOX_RX_PROT_USER_DEFAULT (_SEMAILBOX_RX_PROT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ 176 177 /* Bit fields for SEMAILBOX TX_HEADER */ 178 #define _SEMAILBOX_TX_HEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_TX_HEADER */ 179 #define _SEMAILBOX_TX_HEADER_MASK 0x0020FFFFUL /**< Mask for SEMAILBOX_TX_HEADER */ 180 #define _SEMAILBOX_TX_HEADER_SIZE_SHIFT 0 /**< Shift value for SEMAILBOX_SIZE */ 181 #define _SEMAILBOX_TX_HEADER_SIZE_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_SIZE */ 182 #define _SEMAILBOX_TX_HEADER_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_HEADER */ 183 #define SEMAILBOX_TX_HEADER_SIZE_DEFAULT (_SEMAILBOX_TX_HEADER_SIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_TX_HEADER*/ 184 #define SEMAILBOX_TX_HEADER_UNPROTECTED (0x1UL << 21) /**< Unprotected */ 185 #define _SEMAILBOX_TX_HEADER_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ 186 #define _SEMAILBOX_TX_HEADER_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ 187 #define _SEMAILBOX_TX_HEADER_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_HEADER */ 188 #define SEMAILBOX_TX_HEADER_UNPROTECTED_DEFAULT (_SEMAILBOX_TX_HEADER_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_TX_HEADER*/ 189 190 /* Bit fields for SEMAILBOX RX_HEADER */ 191 #define _SEMAILBOX_RX_HEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_RX_HEADER */ 192 #define _SEMAILBOX_RX_HEADER_MASK 0x002FFFFFUL /**< Mask for SEMAILBOX_RX_HEADER */ 193 #define _SEMAILBOX_RX_HEADER_SIZE_SHIFT 0 /**< Shift value for SEMAILBOX_SIZE */ 194 #define _SEMAILBOX_RX_HEADER_SIZE_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_SIZE */ 195 #define _SEMAILBOX_RX_HEADER_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_HEADER */ 196 #define SEMAILBOX_RX_HEADER_SIZE_DEFAULT (_SEMAILBOX_RX_HEADER_SIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_RX_HEADER*/ 197 #define _SEMAILBOX_RX_HEADER_STATUS_SHIFT 16 /**< Shift value for SEMAILBOX_STATUS */ 198 #define _SEMAILBOX_RX_HEADER_STATUS_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_STATUS */ 199 #define _SEMAILBOX_RX_HEADER_STATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_HEADER */ 200 #define SEMAILBOX_RX_HEADER_STATUS_DEFAULT (_SEMAILBOX_RX_HEADER_STATUS_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_RX_HEADER*/ 201 #define SEMAILBOX_RX_HEADER_UNPROTECTED (0x1UL << 21) /**< Unprotected */ 202 #define _SEMAILBOX_RX_HEADER_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ 203 #define _SEMAILBOX_RX_HEADER_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ 204 #define _SEMAILBOX_RX_HEADER_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_HEADER */ 205 #define SEMAILBOX_RX_HEADER_UNPROTECTED_DEFAULT (_SEMAILBOX_RX_HEADER_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_RX_HEADER*/ 206 207 /* Bit fields for SEMAILBOX CONFIGURATION */ 208 #define _SEMAILBOX_CONFIGURATION_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_CONFIGURATION */ 209 #define _SEMAILBOX_CONFIGURATION_MASK 0x00000003UL /**< Mask for SEMAILBOX_CONFIGURATION */ 210 #define SEMAILBOX_CONFIGURATION_TXINTEN (0x1UL << 0) /**< TX Interrupt Enable */ 211 #define _SEMAILBOX_CONFIGURATION_TXINTEN_SHIFT 0 /**< Shift value for SEMAILBOX_TXINTEN */ 212 #define _SEMAILBOX_CONFIGURATION_TXINTEN_MASK 0x1UL /**< Bit mask for SEMAILBOX_TXINTEN */ 213 #define _SEMAILBOX_CONFIGURATION_TXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_CONFIGURATION */ 214 #define SEMAILBOX_CONFIGURATION_TXINTEN_DEFAULT (_SEMAILBOX_CONFIGURATION_TXINTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_CONFIGURATION*/ 215 #define SEMAILBOX_CONFIGURATION_RXINTEN (0x1UL << 1) /**< RX Interrupt Enable */ 216 #define _SEMAILBOX_CONFIGURATION_RXINTEN_SHIFT 1 /**< Shift value for SEMAILBOX_RXINTEN */ 217 #define _SEMAILBOX_CONFIGURATION_RXINTEN_MASK 0x2UL /**< Bit mask for SEMAILBOX_RXINTEN */ 218 #define _SEMAILBOX_CONFIGURATION_RXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_CONFIGURATION */ 219 #define SEMAILBOX_CONFIGURATION_RXINTEN_DEFAULT (_SEMAILBOX_CONFIGURATION_RXINTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SEMAILBOX_CONFIGURATION*/ 220 221 /** @} End of group EFR32MG21_SEMAILBOX_HOST_BitFields */ 222 /** @} End of group EFR32MG21_SEMAILBOX_HOST */ 223 /**************************************************************************//** 224 * @defgroup EFR32MG21_SEMAILBOX_SE SEMAILBOX_SE 225 * @{ 226 * @brief EFR32MG21 SEMAILBOX_SE Register Declaration. 227 *****************************************************************************/ 228 229 /** SEMAILBOX_SE Register Declaration. */ 230 typedef struct semailbox_se_typedef{ 231 __IOM uint32_t NEW_REG; /**< New Register */ 232 } SEMAILBOX_SE_TypeDef; 233 /** @} End of group EFR32MG21_SEMAILBOX_SE */ 234 235 /**************************************************************************//** 236 * @addtogroup EFR32MG21_SEMAILBOX_SE 237 * @{ 238 * @defgroup EFR32MG21_SEMAILBOX_SE_BitFields SEMAILBOX_SE Bit Fields 239 * @{ 240 *****************************************************************************/ 241 242 /* Bit fields for SEMAILBOX NEW_REG */ 243 #define _SEMAILBOX_NEW_REG_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_NEW_REG */ 244 #define _SEMAILBOX_NEW_REG_MASK 0x00000001UL /**< Mask for SEMAILBOX_NEW_REG */ 245 #define SEMAILBOX_NEW_REG_NEWBIT (0x1UL << 0) /**< New BitField */ 246 #define _SEMAILBOX_NEW_REG_NEWBIT_SHIFT 0 /**< Shift value for SEMAILBOX_NEWBIT */ 247 #define _SEMAILBOX_NEW_REG_NEWBIT_MASK 0x1UL /**< Bit mask for SEMAILBOX_NEWBIT */ 248 #define _SEMAILBOX_NEW_REG_NEWBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_NEW_REG */ 249 #define SEMAILBOX_NEW_REG_NEWBIT_DEFAULT (_SEMAILBOX_NEW_REG_NEWBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_NEW_REG */ 250 251 /** @} End of group EFR32MG21_SEMAILBOX_SE_BitFields */ 252 /** @} End of group EFR32MG21_SEMAILBOX_SE */ 253 /** @} End of group Parts */ 254 255 #endif // EFR32MG21_SEMAILBOX_H 256
