1 /**************************************************************************//** 2 * @file 3 * @brief EFR32FG23 LCDRF register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2024 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32FG23_LCDRF_H 31 #define EFR32FG23_LCDRF_H 32 #define LCDRF_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32FG23_LCDRF LCDRF 40 * @{ 41 * @brief EFR32FG23 LCDRF Register Declaration. 42 *****************************************************************************/ 43 44 /** LCDRF Register Declaration. */ 45 typedef struct lcdrf_typedef{ 46 __IOM uint32_t RFIMLCDCTRL; /**< RF Interference Mitigation LCD Control */ 47 uint32_t RESERVED0[1023U]; /**< Reserved for future use */ 48 __IOM uint32_t RFIMLCDCTRL_SET; /**< RF Interference Mitigation LCD Control */ 49 uint32_t RESERVED1[1023U]; /**< Reserved for future use */ 50 __IOM uint32_t RFIMLCDCTRL_CLR; /**< RF Interference Mitigation LCD Control */ 51 uint32_t RESERVED2[1023U]; /**< Reserved for future use */ 52 __IOM uint32_t RFIMLCDCTRL_TGL; /**< RF Interference Mitigation LCD Control */ 53 } LCDRF_TypeDef; 54 /** @} End of group EFR32FG23_LCDRF */ 55 56 /**************************************************************************//** 57 * @addtogroup EFR32FG23_LCDRF 58 * @{ 59 * @defgroup EFR32FG23_LCDRF_BitFields LCDRF Bit Fields 60 * @{ 61 *****************************************************************************/ 62 63 /* Bit fields for LCDRF RFIMLCDCTRL */ 64 #define _LCDRF_RFIMLCDCTRL_RESETVALUE 0x00000000UL /**< Default value for LCDRF_RFIMLCDCTRL */ 65 #define _LCDRF_RFIMLCDCTRL_MASK 0x0000001FUL /**< Mask for LCDRF_RFIMLCDCTRL */ 66 #define LCDRF_RFIMLCDCTRL_LCDCPXOEN (0x1UL << 0) /**< LCD Charge Pump XO Clock Enable */ 67 #define _LCDRF_RFIMLCDCTRL_LCDCPXOEN_SHIFT 0 /**< Shift value for LCDRF_LCDCPXOEN */ 68 #define _LCDRF_RFIMLCDCTRL_LCDCPXOEN_MASK 0x1UL /**< Bit mask for LCDRF_LCDCPXOEN */ 69 #define _LCDRF_RFIMLCDCTRL_LCDCPXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCDRF_RFIMLCDCTRL */ 70 #define LCDRF_RFIMLCDCTRL_LCDCPXOEN_DEFAULT (_LCDRF_RFIMLCDCTRL_LCDCPXOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCDRF_RFIMLCDCTRL */ 71 #define LCDRF_RFIMLCDCTRL_LCDCPXOSEL (0x1UL << 1) /**< LCD Charge Pump XO Select */ 72 #define _LCDRF_RFIMLCDCTRL_LCDCPXOSEL_SHIFT 1 /**< Shift value for LCDRF_LCDCPXOSEL */ 73 #define _LCDRF_RFIMLCDCTRL_LCDCPXOSEL_MASK 0x2UL /**< Bit mask for LCDRF_LCDCPXOSEL */ 74 #define _LCDRF_RFIMLCDCTRL_LCDCPXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCDRF_RFIMLCDCTRL */ 75 #define _LCDRF_RFIMLCDCTRL_LCDCPXOSEL_INTRCO 0x00000000UL /**< Mode INTRCO for LCDRF_RFIMLCDCTRL */ 76 #define _LCDRF_RFIMLCDCTRL_LCDCPXOSEL_HFXODIV 0x00000001UL /**< Mode HFXODIV for LCDRF_RFIMLCDCTRL */ 77 #define LCDRF_RFIMLCDCTRL_LCDCPXOSEL_DEFAULT (_LCDRF_RFIMLCDCTRL_LCDCPXOSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for LCDRF_RFIMLCDCTRL */ 78 #define LCDRF_RFIMLCDCTRL_LCDCPXOSEL_INTRCO (_LCDRF_RFIMLCDCTRL_LCDCPXOSEL_INTRCO << 1) /**< Shifted mode INTRCO for LCDRF_RFIMLCDCTRL */ 79 #define LCDRF_RFIMLCDCTRL_LCDCPXOSEL_HFXODIV (_LCDRF_RFIMLCDCTRL_LCDCPXOSEL_HFXODIV << 1) /**< Shifted mode HFXODIV for LCDRF_RFIMLCDCTRL */ 80 #define LCDRF_RFIMLCDCTRL_LCDCPXORETIMEEN (0x1UL << 2) /**< LCD Charge Pump XO Retime Enable */ 81 #define _LCDRF_RFIMLCDCTRL_LCDCPXORETIMEEN_SHIFT 2 /**< Shift value for LCDRF_LCDCPXORETIMEEN */ 82 #define _LCDRF_RFIMLCDCTRL_LCDCPXORETIMEEN_MASK 0x4UL /**< Bit mask for LCDRF_LCDCPXORETIMEEN */ 83 #define _LCDRF_RFIMLCDCTRL_LCDCPXORETIMEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCDRF_RFIMLCDCTRL */ 84 #define LCDRF_RFIMLCDCTRL_LCDCPXORETIMEEN_DEFAULT (_LCDRF_RFIMLCDCTRL_LCDCPXORETIMEEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LCDRF_RFIMLCDCTRL */ 85 #define LCDRF_RFIMLCDCTRL_LCDLOWNOISE (0x1UL << 3) /**< LCD Low Noise */ 86 #define _LCDRF_RFIMLCDCTRL_LCDLOWNOISE_SHIFT 3 /**< Shift value for LCDRF_LCDLOWNOISE */ 87 #define _LCDRF_RFIMLCDCTRL_LCDLOWNOISE_MASK 0x8UL /**< Bit mask for LCDRF_LCDLOWNOISE */ 88 #define _LCDRF_RFIMLCDCTRL_LCDLOWNOISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCDRF_RFIMLCDCTRL */ 89 #define _LCDRF_RFIMLCDCTRL_LCDLOWNOISE_NORMAL 0x00000000UL /**< Mode NORMAL for LCDRF_RFIMLCDCTRL */ 90 #define _LCDRF_RFIMLCDCTRL_LCDLOWNOISE_SLOW 0x00000001UL /**< Mode SLOW for LCDRF_RFIMLCDCTRL */ 91 #define LCDRF_RFIMLCDCTRL_LCDLOWNOISE_DEFAULT (_LCDRF_RFIMLCDCTRL_LCDLOWNOISE_DEFAULT << 3) /**< Shifted mode DEFAULT for LCDRF_RFIMLCDCTRL */ 92 #define LCDRF_RFIMLCDCTRL_LCDLOWNOISE_NORMAL (_LCDRF_RFIMLCDCTRL_LCDLOWNOISE_NORMAL << 3) /**< Shifted mode NORMAL for LCDRF_RFIMLCDCTRL */ 93 #define LCDRF_RFIMLCDCTRL_LCDLOWNOISE_SLOW (_LCDRF_RFIMLCDCTRL_LCDLOWNOISE_SLOW << 3) /**< Shifted mode SLOW for LCDRF_RFIMLCDCTRL */ 94 #define LCDRF_RFIMLCDCTRL_LCDCMPDOUT (0x1UL << 4) /**< LCD Comparator Dout */ 95 #define _LCDRF_RFIMLCDCTRL_LCDCMPDOUT_SHIFT 4 /**< Shift value for LCDRF_LCDCMPDOUT */ 96 #define _LCDRF_RFIMLCDCTRL_LCDCMPDOUT_MASK 0x10UL /**< Bit mask for LCDRF_LCDCMPDOUT */ 97 #define _LCDRF_RFIMLCDCTRL_LCDCMPDOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCDRF_RFIMLCDCTRL */ 98 #define LCDRF_RFIMLCDCTRL_LCDCMPDOUT_DEFAULT (_LCDRF_RFIMLCDCTRL_LCDCMPDOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for LCDRF_RFIMLCDCTRL */ 99 100 /** @} End of group EFR32FG23_LCDRF_BitFields */ 101 /** @} End of group EFR32FG23_LCDRF */ 102 /** @} End of group Parts */ 103 104 #endif // EFR32FG23_LCDRF_H 105
