1 /**************************************************************************//** 2 * @file 3 * @brief CMSIS Cortex-M Peripheral Access Layer Header File 4 * for EFR32BG29B221F1024CJ45 5 ****************************************************************************** 6 * # License 7 * <b>Copyright 2024 Silicon Laboratories, Inc. www.silabs.com</b> 8 ****************************************************************************** 9 * 10 * SPDX-License-Identifier: Zlib 11 * 12 * The licensor of this software is Silicon Laboratories Inc. 13 * 14 * This software is provided 'as-is', without any express or implied 15 * warranty. In no event will the authors be held liable for any damages 16 * arising from the use of this software. 17 * 18 * Permission is granted to anyone to use this software for any purpose, 19 * including commercial applications, and to alter it and redistribute it 20 * freely, subject to the following restrictions: 21 * 22 * 1. The origin of this software must not be misrepresented; you must not 23 * claim that you wrote the original software. If you use this software 24 * in a product, an acknowledgment in the product documentation would be 25 * appreciated but is not required. 26 * 2. Altered source versions must be plainly marked as such, and must not be 27 * misrepresented as being the original software. 28 * 3. This notice may not be removed or altered from any source distribution. 29 * 30 *****************************************************************************/ 31 #ifndef EFR32BG29B221F1024CJ45_H 32 #define EFR32BG29B221F1024CJ45_H 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 /**************************************************************************//** 39 * @addtogroup Parts 40 * @{ 41 *****************************************************************************/ 42 43 /**************************************************************************//** 44 * @defgroup EFR32BG29B221F1024CJ45 EFR32BG29B221F1024CJ45 45 * @{ 46 *****************************************************************************/ 47 48 /** Interrupt Number Definition */ 49 typedef enum IRQn{ 50 /****** Cortex-M Processor Exceptions Numbers ******************************************/ 51 NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ 52 HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ 53 MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ 54 BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ 55 UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ 56 #if defined(CONFIG_ARM_SECURE_FIRMWARE) 57 SecureFault_IRQn = -9, 58 #endif 59 SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ 60 DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ 61 PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ 62 SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ 63 64 /****** EFR32BG29 Peripheral Interrupt Numbers ******************************************/ 65 66 SETAMPERHOST_IRQn = 0, /*!< 0 EFR32 SETAMPERHOST Interrupt */ 67 SEMBRX_IRQn = 1, /*!< 1 EFR32 SEMBRX Interrupt */ 68 SEMBTX_IRQn = 2, /*!< 2 EFR32 SEMBTX Interrupt */ 69 SMU_SECURE_IRQn = 3, /*!< 3 EFR32 SMU_SECURE Interrupt */ 70 SMU_S_PRIVILEGED_IRQn = 4, /*!< 4 EFR32 SMU_S_PRIVILEGED Interrupt */ 71 SMU_NS_PRIVILEGED_IRQn = 5, /*!< 5 EFR32 SMU_NS_PRIVILEGED Interrupt */ 72 EMU_IRQn = 6, /*!< 6 EFR32 EMU Interrupt */ 73 EMUEFP_IRQn = 7, /*!< 7 EFR32 EMUEFP Interrupt */ 74 DCDC_IRQn = 8, /*!< 8 EFR32 DCDC Interrupt */ 75 ETAMPDET_IRQn = 9, /*!< 9 EFR32 ETAMPDET Interrupt */ 76 TIMER0_IRQn = 10, /*!< 10 EFR32 TIMER0 Interrupt */ 77 TIMER1_IRQn = 11, /*!< 11 EFR32 TIMER1 Interrupt */ 78 TIMER2_IRQn = 12, /*!< 12 EFR32 TIMER2 Interrupt */ 79 TIMER3_IRQn = 13, /*!< 13 EFR32 TIMER3 Interrupt */ 80 TIMER4_IRQn = 14, /*!< 14 EFR32 TIMER4 Interrupt */ 81 RTCC_IRQn = 15, /*!< 15 EFR32 RTCC Interrupt */ 82 USART0_RX_IRQn = 16, /*!< 16 EFR32 USART0_RX Interrupt */ 83 USART0_TX_IRQn = 17, /*!< 17 EFR32 USART0_TX Interrupt */ 84 USART1_RX_IRQn = 18, /*!< 18 EFR32 USART1_RX Interrupt */ 85 USART1_TX_IRQn = 19, /*!< 19 EFR32 USART1_TX Interrupt */ 86 EUSART0_RX_IRQn = 20, /*!< 20 EFR32 EUSART0_RX Interrupt */ 87 EUSART0_TX_IRQn = 21, /*!< 21 EFR32 EUSART0_TX Interrupt */ 88 ICACHE0_IRQn = 22, /*!< 22 EFR32 ICACHE0 Interrupt */ 89 BURTC_IRQn = 23, /*!< 23 EFR32 BURTC Interrupt */ 90 LETIMER0_IRQn = 24, /*!< 24 EFR32 LETIMER0 Interrupt */ 91 SYSCFG_IRQn = 25, /*!< 25 EFR32 SYSCFG Interrupt */ 92 LDMA_IRQn = 26, /*!< 26 EFR32 LDMA Interrupt */ 93 LFXO_IRQn = 27, /*!< 27 EFR32 LFXO Interrupt */ 94 LFRCO_IRQn = 28, /*!< 28 EFR32 LFRCO Interrupt */ 95 ULFRCO_IRQn = 29, /*!< 29 EFR32 ULFRCO Interrupt */ 96 GPIO_ODD_IRQn = 30, /*!< 30 EFR32 GPIO_ODD Interrupt */ 97 GPIO_EVEN_IRQn = 31, /*!< 31 EFR32 GPIO_EVEN Interrupt */ 98 I2C0_IRQn = 32, /*!< 32 EFR32 I2C0 Interrupt */ 99 I2C1_IRQn = 33, /*!< 33 EFR32 I2C1 Interrupt */ 100 EMUDG_IRQn = 34, /*!< 34 EFR32 EMUDG Interrupt */ 101 EMUSE_IRQn = 35, /*!< 35 EFR32 EMUSE Interrupt */ 102 AGC_IRQn = 36, /*!< 36 EFR32 AGC Interrupt */ 103 BUFC_IRQn = 37, /*!< 37 EFR32 BUFC Interrupt */ 104 FRC_PRI_IRQn = 38, /*!< 38 EFR32 FRC_PRI Interrupt */ 105 FRC_IRQn = 39, /*!< 39 EFR32 FRC Interrupt */ 106 MODEM_IRQn = 40, /*!< 40 EFR32 MODEM Interrupt */ 107 PROTIMER_IRQn = 41, /*!< 41 EFR32 PROTIMER Interrupt */ 108 RAC_RSM_IRQn = 42, /*!< 42 EFR32 RAC_RSM Interrupt */ 109 RAC_SEQ_IRQn = 43, /*!< 43 EFR32 RAC_SEQ Interrupt */ 110 RDMAILBOX_IRQn = 44, /*!< 44 EFR32 RDMAILBOX Interrupt */ 111 RFSENSE_IRQn = 45, /*!< 45 EFR32 RFSENSE Interrupt */ 112 SYNTH_IRQn = 46, /*!< 46 EFR32 SYNTH Interrupt */ 113 PRORTC_IRQn = 47, /*!< 47 EFR32 PRORTC Interrupt */ 114 ACMP0_IRQn = 48, /*!< 48 EFR32 ACMP0 Interrupt */ 115 WDOG0_IRQn = 49, /*!< 49 EFR32 WDOG0 Interrupt */ 116 HFXO0_IRQn = 50, /*!< 50 EFR32 HFXO0 Interrupt */ 117 HFRCO0_IRQn = 51, /*!< 51 EFR32 HFRCO0 Interrupt */ 118 CMU_IRQn = 52, /*!< 52 EFR32 CMU Interrupt */ 119 AES_IRQn = 53, /*!< 53 EFR32 AES Interrupt */ 120 IADC_IRQn = 54, /*!< 54 EFR32 IADC Interrupt */ 121 MSC_IRQn = 55, /*!< 55 EFR32 MSC Interrupt */ 122 DPLL0_IRQn = 56, /*!< 56 EFR32 DPLL0 Interrupt */ 123 PDM_IRQn = 57, /*!< 57 EFR32 PDM Interrupt */ 124 SW0_IRQn = 58, /*!< 58 EFR32 SW0 Interrupt */ 125 SW1_IRQn = 59, /*!< 59 EFR32 SW1 Interrupt */ 126 SW2_IRQn = 60, /*!< 60 EFR32 SW2 Interrupt */ 127 SW3_IRQn = 61, /*!< 61 EFR32 SW3 Interrupt */ 128 KERNEL0_IRQn = 62, /*!< 62 EFR32 KERNEL0 Interrupt */ 129 KERNEL1_IRQn = 63, /*!< 63 EFR32 KERNEL1 Interrupt */ 130 M33CTI0_IRQn = 64, /*!< 64 EFR32 M33CTI0 Interrupt */ 131 M33CTI1_IRQn = 65, /*!< 65 EFR32 M33CTI1 Interrupt */ 132 FPUEXH_IRQn = 66, /*!< 66 EFR32 FPUEXH Interrupt */ 133 MPAHBRAM_IRQn = 67, /*!< 67 EFR32 MPAHBRAM Interrupt */ 134 EUSART1_RX_IRQn = 68, /*!< 68 EFR32 EUSART1_RX Interrupt */ 135 EUSART1_TX_IRQn = 69, /*!< 69 EFR32 EUSART1_TX Interrupt */ 136 } IRQn_Type; 137 138 /**************************************************************************//** 139 * @defgroup EFR32BG29B221F1024CJ45_Core EFR32BG29B221F1024CJ45 Core 140 * @{ 141 * @brief Processor and Core Peripheral Section 142 *****************************************************************************/ 143 144 #define __CORTEXM 1U /**< Core architecture */ 145 #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ 146 #define __DSP_PRESENT 1U /**< Presence of DSP */ 147 #define __FPU_PRESENT 1U /**< Presence of FPU */ 148 #define __MPU_PRESENT 1U /**< Presence of MPU */ 149 #define __SAUREGION_PRESENT 1U /**< Presence of FPU */ 150 #define __TZ_PRESENT 1U /**< Presence of TrustZone */ 151 #define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ 152 #define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ 153 #define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ 154 155 /** @} End of group EFR32BG29B221F1024CJ45_Core */ 156 157 /**************************************************************************//** 158 * @defgroup EFR32BG29B221F1024CJ45_Part EFR32BG29B221F1024CJ45 Part 159 * @{ 160 ******************************************************************************/ 161 162 /** Part number */ 163 164 /* If part number is not defined as compiler option, define it */ 165 #if !defined(EFR32BG29B221F1024CJ45) 166 #define EFR32BG29B221F1024CJ45 1 /**< FULL Part */ 167 #endif 168 169 /** Configure part number */ 170 #define PART_NUMBER "EFR32BG29B221F1024CJ45" /**< Part Number */ 171 172 /** Family / Line / Series / Config */ 173 #define _EFR32_BLUE_FAMILY 1 /** Device Family Name Identifier */ 174 #define _EFR32_BG_FAMILY 1 /** Device Family Identifier */ 175 #define _EFR_DEVICE 1 /** Product Line Identifier */ 176 #define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ 177 #define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ 178 #define _SILICON_LABS_32B_SERIES_2_CONFIG_9 /** Product Config Identifier */ 179 #define _SILICON_LABS_32B_SERIES_2_CONFIG 9 /** Product Config Identifier */ 180 #define _SILICON_LABS_GECKO_INTERNAL_SDID 240 /** Silicon Labs internal use only */ 181 #define _SILICON_LABS_GECKO_INTERNAL_SDID_240 /** Silicon Labs internal use only */ 182 #define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ 183 #define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ 184 #define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ 185 #define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */ 186 #define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ 187 #define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ 188 #define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ 189 #define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ 190 #define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST /** DCDC feature set */ 191 #define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ 192 #define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ 193 #define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ 194 #define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ 195 #define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ 196 #define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 4 /** Radio 2G4HZ HP PA output power */ 197 #define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */ 198 #define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */ 199 #define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */ 200 #define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ 201 202 /** Memory Base addresses and limits */ 203 #define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ 204 #define FLASH_MEM_SIZE (0x00100000UL) /** FLASH_MEM available address space */ 205 #define FLASH_MEM_END (0x080FFFFFUL) /** FLASH_MEM end address */ 206 #define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ 207 #define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ 208 #define MSC_FLASH_MEM_SIZE (0x00100000UL) /** MSC_FLASH_MEM available address space */ 209 #define MSC_FLASH_MEM_END (0x080FFFFFUL) /** MSC_FLASH_MEM end address */ 210 #define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ 211 #define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ 212 #define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ 213 #define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ 214 #define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ 215 #define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ 216 #define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ 217 #define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ 218 #define USERDATA_BITS (0xBUL) /** USERDATA used bits */ 219 #define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ 220 #define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ 221 #define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ 222 #define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ 223 #define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ 224 #define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ 225 #define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ 226 #define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ 227 #define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ 228 #define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ 229 #define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ 230 #define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ 231 #define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ 232 #define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ 233 #define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ 234 #define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ 235 #define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ 236 #define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ 237 #define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ 238 #define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ 239 #define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ 240 #define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ 241 #define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ 242 #define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ 243 #define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ 244 #define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ 245 #define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ 246 #define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ 247 #define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ 248 #define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ 249 #define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ 250 #define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ 251 #define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ 252 #define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ 253 #define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ 254 #define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ 255 #define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ 256 #define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ 257 #define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ 258 #define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ 259 260 /** Flash and SRAM limits for EFR32BG29B221F1024CJ45 */ 261 #define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ 262 #define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ 263 #define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ 264 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ 265 #define SRAM_SIZE (0x00030000UL) /**< Available SRAM Memory */ 266 #define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ 267 #define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ 268 269 /* GPIO Avalibility Info */ 270 #define GPIO_PA_INDEX 0U /**< Index of port PA */ 271 #define GPIO_PA_COUNT 7U /**< Number of pins on port PA */ 272 #define GPIO_PA_MASK (0x007FUL) /**< Port PA pin mask */ 273 #define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ 274 #define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ 275 #define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ 276 #define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ 277 #define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ 278 #define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ 279 #define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ 280 #define GPIO_PB_INDEX 1U /**< Index of port PB */ 281 #define GPIO_PB_COUNT 3U /**< Number of pins on port PB */ 282 #define GPIO_PB_MASK (0x0007UL) /**< Port PB pin mask */ 283 #define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ 284 #define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ 285 #define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ 286 #define GPIO_PC_INDEX 2U /**< Index of port PC */ 287 #define GPIO_PC_COUNT 7U /**< Number of pins on port PC */ 288 #define GPIO_PC_MASK (0x007FUL) /**< Port PC pin mask */ 289 #define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ 290 #define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ 291 #define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ 292 #define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ 293 #define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ 294 #define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ 295 #define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ 296 #define GPIO_PD_INDEX 3U /**< Index of port PD */ 297 #define GPIO_PD_COUNT 2U /**< Number of pins on port PD */ 298 #define GPIO_PD_MASK (0x0003UL) /**< Port PD pin mask */ 299 #define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ 300 #define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ 301 302 /* Fixed Resource Locations */ 303 #define ETAMPDET_ETAMPIN0_PORT GPIO_PB_INDEX /**< Port of ETAMPIN0.*/ 304 #define ETAMPDET_ETAMPIN0_PIN 1U /**< Pin of ETAMPIN0.*/ 305 #define ETAMPDET_ETAMPIN1_PORT GPIO_PC_INDEX /**< Port of ETAMPIN1.*/ 306 #define ETAMPDET_ETAMPIN1_PIN 0U /**< Pin of ETAMPIN1.*/ 307 #define ETAMPDET_ETAMPOUT0_PORT GPIO_PC_INDEX /**< Port of ETAMPOUT0.*/ 308 #define ETAMPDET_ETAMPOUT0_PIN 1U /**< Pin of ETAMPOUT0.*/ 309 #define ETAMPDET_ETAMPOUT1_PORT GPIO_PC_INDEX /**< Port of ETAMPOUT1.*/ 310 #define ETAMPDET_ETAMPOUT1_PIN 2U /**< Pin of ETAMPOUT1.*/ 311 #define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ 312 #define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ 313 #define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ 314 #define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ 315 #define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ 316 #define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ 317 #define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ 318 #define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ 319 #define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ 320 #define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ 321 #define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ 322 #define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ 323 #define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ 324 #define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ 325 #define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ 326 #define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ 327 #define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ 328 #define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ 329 #define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ 330 #define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ 331 #define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ 332 #define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ 333 #define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ 334 #define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ 335 #define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ 336 #define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ 337 #define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ 338 #define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ 339 #define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ 340 #define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ 341 #define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ 342 #define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ 343 #define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ 344 #define GPIO_THMSW_EN_PIN 0U /**< Pin of THMSW_EN.*/ 345 #define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ 346 #define GPIO_THMSW_HALFSWITCH_PIN 0U /**< Pin of THMSW_HALFSWITCH.*/ 347 #define IADC0_VREFP_PORT GPIO_PA_INDEX /**< Port of VREFP.*/ 348 #define IADC0_VREFP_PIN 0U /**< Pin of VREFP.*/ 349 #define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ 350 #define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ 351 #define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ 352 #define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ 353 #define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ 354 #define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ 355 356 /* Part number capabilities */ 357 #define ACMP_PRESENT /** ACMP is available in this part */ 358 #define ACMP_COUNT 1 /** 1 ACMPs available */ 359 #define BURAM_PRESENT /** BURAM is available in this part */ 360 #define BURAM_COUNT 1 /** 1 BURAMs available */ 361 #define BURTC_PRESENT /** BURTC is available in this part */ 362 #define BURTC_COUNT 1 /** 1 BURTCs available */ 363 #define CMU_PRESENT /** CMU is available in this part */ 364 #define CMU_COUNT 1 /** 1 CMUs available */ 365 #define DCDC_PRESENT /** DCDC is available in this part */ 366 #define DCDC_COUNT 1 /** 1 DCDCs available */ 367 #define DMEM_PRESENT /** DMEM is available in this part */ 368 #define DMEM_COUNT 1 /** 1 DMEMs available */ 369 #define DPLL_PRESENT /** DPLL is available in this part */ 370 #define DPLL_COUNT 1 /** 1 DPLLs available */ 371 #define EMU_PRESENT /** EMU is available in this part */ 372 #define EMU_COUNT 1 /** 1 EMUs available */ 373 #define ETAMPDET_PRESENT /** ETAMPDET is available in this part */ 374 #define ETAMPDET_COUNT 1 /** 1 ETAMPDETs available */ 375 #define EUSART_PRESENT /** EUSART is available in this part */ 376 #define EUSART_COUNT 2 /** 2 EUSARTs available */ 377 #define FSRCO_PRESENT /** FSRCO is available in this part */ 378 #define FSRCO_COUNT 1 /** 1 FSRCOs available */ 379 #define GPCRC_PRESENT /** GPCRC is available in this part */ 380 #define GPCRC_COUNT 1 /** 1 GPCRCs available */ 381 #define GPIO_PRESENT /** GPIO is available in this part */ 382 #define GPIO_COUNT 1 /** 1 GPIOs available */ 383 #define HFRCO_PRESENT /** HFRCO is available in this part */ 384 #define HFRCO_COUNT 1 /** 1 HFRCOs available */ 385 #define HFXO_PRESENT /** HFXO is available in this part */ 386 #define HFXO_COUNT 1 /** 1 HFXOs available */ 387 #define I2C_PRESENT /** I2C is available in this part */ 388 #define I2C_COUNT 2 /** 2 I2Cs available */ 389 #define IADC_PRESENT /** IADC is available in this part */ 390 #define IADC_COUNT 1 /** 1 IADCs available */ 391 #define ICACHE_PRESENT /** ICACHE is available in this part */ 392 #define ICACHE_COUNT 1 /** 1 ICACHEs available */ 393 #define LDMA_PRESENT /** LDMA is available in this part */ 394 #define LDMA_COUNT 1 /** 1 LDMAs available */ 395 #define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ 396 #define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ 397 #define LETIMER_PRESENT /** LETIMER is available in this part */ 398 #define LETIMER_COUNT 1 /** 1 LETIMERs available */ 399 #define LFRCO_PRESENT /** LFRCO is available in this part */ 400 #define LFRCO_COUNT 1 /** 1 LFRCOs available */ 401 #define LFXO_PRESENT /** LFXO is available in this part */ 402 #define LFXO_COUNT 1 /** 1 LFXOs available */ 403 #define MSC_PRESENT /** MSC is available in this part */ 404 #define MSC_COUNT 1 /** 1 MSCs available */ 405 #define PDM_PRESENT /** PDM is available in this part */ 406 #define PDM_COUNT 1 /** 1 PDMs available */ 407 #define PRORTC_PRESENT /** PRORTC is available in this part */ 408 #define PRORTC_COUNT 1 /** 1 PRORTCs available */ 409 #define PRS_PRESENT /** PRS is available in this part */ 410 #define PRS_COUNT 1 /** 1 PRSs available */ 411 #define RADIOAES_PRESENT /** RADIOAES is available in this part */ 412 #define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ 413 #define RTCC_PRESENT /** RTCC is available in this part */ 414 #define RTCC_COUNT 1 /** 1 RTCCs available */ 415 #define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ 416 #define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ 417 #define SMU_PRESENT /** SMU is available in this part */ 418 #define SMU_COUNT 1 /** 1 SMUs available */ 419 #define SYSCFG_PRESENT /** SYSCFG is available in this part */ 420 #define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ 421 #define TIMER_PRESENT /** TIMER is available in this part */ 422 #define TIMER_COUNT 5 /** 5 TIMERs available */ 423 #define ULFRCO_PRESENT /** ULFRCO is available in this part */ 424 #define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ 425 #define USART_PRESENT /** USART is available in this part */ 426 #define USART_COUNT 2 /** 2 USARTs available */ 427 #define WDOG_PRESENT /** WDOG is available in this part */ 428 #define WDOG_COUNT 1 /** 1 WDOGs available */ 429 #define DEVINFO_PRESENT /** DEVINFO is available in this part */ 430 #define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ 431 432 /* Include standard ARM headers for the core */ 433 #include "core_cm33.h" /* Core Header File */ 434 #include "system_efr32bg29.h" /* System Header File */ 435 436 /** @} End of group EFR32BG29B221F1024CJ45_Part */ 437 438 /**************************************************************************//** 439 * @defgroup EFR32BG29B221F1024CJ45_Peripheral_TypeDefs EFR32BG29B221F1024CJ45 Peripheral TypeDefs 440 * @{ 441 * @brief Device Specific Peripheral Register Structures 442 *****************************************************************************/ 443 #include "efr32bg29_emu.h" 444 #include "efr32bg29_cmu.h" 445 #include "efr32bg29_hfxo.h" 446 #include "efr32bg29_hfrco.h" 447 #include "efr32bg29_fsrco.h" 448 #include "efr32bg29_dpll.h" 449 #include "efr32bg29_lfxo.h" 450 #include "efr32bg29_lfrco.h" 451 #include "efr32bg29_ulfrco.h" 452 #include "efr32bg29_msc.h" 453 #include "efr32bg29_icache.h" 454 #include "efr32bg29_prs.h" 455 #include "efr32bg29_gpio.h" 456 #include "efr32bg29_ldma.h" 457 #include "efr32bg29_ldmaxbar.h" 458 #include "efr32bg29_timer.h" 459 #include "efr32bg29_usart.h" 460 #include "efr32bg29_burtc.h" 461 #include "efr32bg29_i2c.h" 462 #include "efr32bg29_syscfg.h" 463 #include "efr32bg29_buram.h" 464 #include "efr32bg29_gpcrc.h" 465 #include "efr32bg29_dcdc.h" 466 #include "efr32bg29_pdm.h" 467 #include "efr32bg29_etampdet.h" 468 #include "efr32bg29_mpahbram.h" 469 #include "efr32bg29_eusart.h" 470 #include "efr32bg29_aes.h" 471 #include "efr32bg29_smu.h" 472 #include "efr32bg29_rtcc.h" 473 #include "efr32bg29_wdog.h" 474 #include "efr32bg29_letimer.h" 475 #include "efr32bg29_iadc.h" 476 #include "efr32bg29_acmp.h" 477 #include "efr32bg29_semailbox.h" 478 #include "efr32bg29_devinfo.h" 479 480 /* Custom headers for LDMAXBAR and PRS mappings */ 481 #include "efr32bg29_prs_signals.h" 482 #include "efr32bg29_dma_descriptor.h" 483 #include "efr32bg29_ldmaxbar_defines.h" 484 485 /** @} End of group EFR32BG29B221F1024CJ45_Peripheral_TypeDefs */ 486 487 /**************************************************************************//** 488 * @defgroup EFR32BG29B221F1024CJ45_Peripheral_Base EFR32BG29B221F1024CJ45 Peripheral Memory Map 489 * @{ 490 *****************************************************************************/ 491 492 #define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ 493 #define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ 494 #define HFXO0_S_BASE (0x4000C000UL) /* HFXO0_S base address */ 495 #define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ 496 #define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ 497 #define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ 498 #define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ 499 #define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ 500 #define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ 501 #define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ 502 #define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ 503 #define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ 504 #define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ 505 #define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ 506 #define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ 507 #define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ 508 #define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ 509 #define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ 510 #define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ 511 #define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ 512 #define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ 513 #define USART1_S_BASE (0x40060000UL) /* USART1_S base address */ 514 #define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ 515 #define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ 516 #define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ 517 #define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ 518 #define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ 519 #define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ 520 #define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ 521 #define PDM_S_BASE (0x40098000UL) /* PDM_S base address */ 522 #define ETAMPDET_S_BASE (0x400A4000UL) /* ETAMPDET_S base address */ 523 #define DMEM_S_BASE (0x400B0000UL) /* DMEM_S base address */ 524 #define EUSART1_S_BASE (0x400B4000UL) /* EUSART1_S base address */ 525 #define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ 526 #define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ 527 #define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ 528 #define RTCC_S_BASE (0x48000000UL) /* RTCC_S base address */ 529 #define WDOG0_S_BASE (0x48018000UL) /* WDOG0_S base address */ 530 #define LETIMER0_S_BASE (0x4A000000UL) /* LETIMER0_S base address */ 531 #define IADC0_S_BASE (0x4A004000UL) /* IADC0_S base address */ 532 #define ACMP0_S_BASE (0x4A008000UL) /* ACMP0_S base address */ 533 #define I2C0_S_BASE (0x4A010000UL) /* I2C0_S base address */ 534 #define EUSART0_S_BASE (0x4A040000UL) /* EUSART0_S base address */ 535 #define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ 536 #define PRORTC_S_BASE (0xA8000000UL) /* PRORTC_S base address */ 537 #define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ 538 #define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ 539 #define HFXO0_NS_BASE (0x5000C000UL) /* HFXO0_NS base address */ 540 #define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ 541 #define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ 542 #define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ 543 #define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ 544 #define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ 545 #define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ 546 #define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ 547 #define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ 548 #define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ 549 #define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ 550 #define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ 551 #define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ 552 #define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ 553 #define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ 554 #define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ 555 #define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ 556 #define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ 557 #define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ 558 #define USART1_NS_BASE (0x50060000UL) /* USART1_NS base address */ 559 #define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ 560 #define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ 561 #define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ 562 #define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ 563 #define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ 564 #define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ 565 #define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ 566 #define PDM_NS_BASE (0x50098000UL) /* PDM_NS base address */ 567 #define ETAMPDET_NS_BASE (0x500A4000UL) /* ETAMPDET_NS base address */ 568 #define DMEM_NS_BASE (0x500B0000UL) /* DMEM_NS base address */ 569 #define EUSART1_NS_BASE (0x500B4000UL) /* EUSART1_NS base address */ 570 #define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ 571 #define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ 572 #define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ 573 #define RTCC_NS_BASE (0x58000000UL) /* RTCC_NS base address */ 574 #define WDOG0_NS_BASE (0x58018000UL) /* WDOG0_NS base address */ 575 #define LETIMER0_NS_BASE (0x5A000000UL) /* LETIMER0_NS base address */ 576 #define IADC0_NS_BASE (0x5A004000UL) /* IADC0_NS base address */ 577 #define ACMP0_NS_BASE (0x5A008000UL) /* ACMP0_NS base address */ 578 #define I2C0_NS_BASE (0x5A010000UL) /* I2C0_NS base address */ 579 #define EUSART0_NS_BASE (0x5A040000UL) /* EUSART0_NS base address */ 580 #define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ 581 #define PRORTC_NS_BASE (0xB8000000UL) /* PRORTC_NS base address */ 582 583 #if defined(SL_COMPONENT_CATALOG_PRESENT) 584 #include "sl_component_catalog.h" 585 586 #endif 587 #if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) 588 #include "sl_trustzone_secure_config.h" 589 590 #endif 591 592 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) 593 #define EMU_BASE (EMU_S_BASE) /* EMU base address */ 594 #else 595 #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ 596 #endif // SL_TRUSTZONE_PERIPHERAL_EMU_S 597 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) 598 #define CMU_BASE (CMU_S_BASE) /* CMU base address */ 599 #else 600 #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ 601 #endif // SL_TRUSTZONE_PERIPHERAL_CMU_S 602 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) 603 #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ 604 #else 605 #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ 606 #endif // SL_TRUSTZONE_PERIPHERAL_HFXO0_S 607 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) 608 #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ 609 #else 610 #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ 611 #endif // SL_TRUSTZONE_PERIPHERAL_HFRCO0_S 612 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) 613 #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ 614 #else 615 #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ 616 #endif // SL_TRUSTZONE_PERIPHERAL_FSRCO_S 617 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) 618 #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ 619 #else 620 #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ 621 #endif // SL_TRUSTZONE_PERIPHERAL_DPLL0_S 622 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) 623 #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ 624 #else 625 #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ 626 #endif // SL_TRUSTZONE_PERIPHERAL_LFXO_S 627 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) 628 #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ 629 #else 630 #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ 631 #endif // SL_TRUSTZONE_PERIPHERAL_LFRCO_S 632 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) 633 #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ 634 #else 635 #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ 636 #endif // SL_TRUSTZONE_PERIPHERAL_ULFRCO_S 637 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) 638 #define MSC_BASE (MSC_S_BASE) /* MSC base address */ 639 #else 640 #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ 641 #endif // SL_TRUSTZONE_PERIPHERAL_MSC_S 642 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) 643 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ 644 #else 645 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ 646 #endif // SL_TRUSTZONE_PERIPHERAL_ICACHE0_S 647 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) 648 #define PRS_BASE (PRS_S_BASE) /* PRS base address */ 649 #else 650 #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ 651 #endif // SL_TRUSTZONE_PERIPHERAL_PRS_S 652 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) 653 #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ 654 #else 655 #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ 656 #endif // SL_TRUSTZONE_PERIPHERAL_GPIO_S 657 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) 658 #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ 659 #else 660 #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ 661 #endif // SL_TRUSTZONE_PERIPHERAL_LDMA_S 662 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) 663 #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ 664 #else 665 #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ 666 #endif // SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S 667 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) 668 #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ 669 #else 670 #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ 671 #endif // SL_TRUSTZONE_PERIPHERAL_TIMER0_S 672 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) 673 #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ 674 #else 675 #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ 676 #endif // SL_TRUSTZONE_PERIPHERAL_TIMER1_S 677 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) 678 #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ 679 #else 680 #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ 681 #endif // SL_TRUSTZONE_PERIPHERAL_TIMER2_S 682 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) 683 #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ 684 #else 685 #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ 686 #endif // SL_TRUSTZONE_PERIPHERAL_TIMER3_S 687 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) 688 #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ 689 #else 690 #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ 691 #endif // SL_TRUSTZONE_PERIPHERAL_TIMER4_S 692 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) 693 #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ 694 #else 695 #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ 696 #endif // SL_TRUSTZONE_PERIPHERAL_USART0_S 697 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) 698 #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ 699 #else 700 #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ 701 #endif // SL_TRUSTZONE_PERIPHERAL_USART1_S 702 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) 703 #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ 704 #else 705 #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ 706 #endif // SL_TRUSTZONE_PERIPHERAL_BURTC_S 707 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) 708 #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ 709 #else 710 #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ 711 #endif // SL_TRUSTZONE_PERIPHERAL_I2C1_S 712 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) 713 #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ 714 #else 715 #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ 716 #endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S 717 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) 718 #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ 719 #else 720 #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ 721 #endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_S 722 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) 723 #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ 724 #else 725 #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ 726 #endif // SL_TRUSTZONE_PERIPHERAL_BURAM_S 727 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) 728 #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ 729 #else 730 #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ 731 #endif // SL_TRUSTZONE_PERIPHERAL_GPCRC_S 732 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) 733 #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ 734 #else 735 #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ 736 #endif // SL_TRUSTZONE_PERIPHERAL_DCDC_S 737 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) 738 #define PDM_BASE (PDM_S_BASE) /* PDM base address */ 739 #else 740 #define PDM_BASE (PDM_NS_BASE) /* PDM base address */ 741 #endif // SL_TRUSTZONE_PERIPHERAL_PDM_S 742 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S) && (SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S != 0))) 743 #define ETAMPDET_BASE (ETAMPDET_S_BASE) /* ETAMPDET base address */ 744 #else 745 #define ETAMPDET_BASE (ETAMPDET_NS_BASE) /* ETAMPDET base address */ 746 #endif // SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S 747 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) 748 #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ 749 #else 750 #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ 751 #endif // SL_TRUSTZONE_PERIPHERAL_DMEM_S 752 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) 753 #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ 754 #else 755 #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ 756 #endif // SL_TRUSTZONE_PERIPHERAL_EUSART1_S 757 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) 758 #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ 759 #else 760 #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ 761 #endif // SL_TRUSTZONE_PERIPHERAL_RADIOAES_S 762 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) 763 #define SMU_BASE (SMU_S_BASE) /* SMU base address */ 764 #else 765 #define SMU_BASE (SMU_S_BASE) /* SMU base address */ 766 #endif // SL_TRUSTZONE_PERIPHERAL_SMU_S 767 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) 768 #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ 769 #else 770 #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ 771 #endif // SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S 772 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) 773 #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ 774 #else 775 #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ 776 #endif // SL_TRUSTZONE_PERIPHERAL_RTCC_S 777 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) 778 #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ 779 #else 780 #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ 781 #endif // SL_TRUSTZONE_PERIPHERAL_WDOG0_S 782 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) 783 #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ 784 #else 785 #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ 786 #endif // SL_TRUSTZONE_PERIPHERAL_LETIMER0_S 787 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) 788 #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ 789 #else 790 #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ 791 #endif // SL_TRUSTZONE_PERIPHERAL_IADC0_S 792 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) 793 #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ 794 #else 795 #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ 796 #endif // SL_TRUSTZONE_PERIPHERAL_ACMP0_S 797 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) 798 #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ 799 #else 800 #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ 801 #endif // SL_TRUSTZONE_PERIPHERAL_I2C0_S 802 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) 803 #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ 804 #else 805 #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ 806 #endif // SL_TRUSTZONE_PERIPHERAL_EUSART0_S 807 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) 808 #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ 809 #else 810 #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ 811 #endif // SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S 812 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) 813 #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ 814 #else 815 #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ 816 #endif // SL_TRUSTZONE_PERIPHERAL_PRORTC_S 817 818 #define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ 819 /** @} End of group EFR32BG29B221F1024CJ45_Peripheral_Base */ 820 821 /**************************************************************************//** 822 * @defgroup EFR32BG29B221F1024CJ45_Peripheral_Declaration EFR32BG29B221F1024CJ45 Peripheral Declarations Map 823 * @{ 824 *****************************************************************************/ 825 826 #define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ 827 #define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ 828 #define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ 829 #define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ 830 #define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ 831 #define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ 832 #define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ 833 #define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ 834 #define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ 835 #define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ 836 #define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ 837 #define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ 838 #define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ 839 #define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ 840 #define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ 841 #define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ 842 #define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ 843 #define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ 844 #define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ 845 #define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ 846 #define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ 847 #define USART1_S ((USART_TypeDef *) USART1_S_BASE) /**< USART1_S base pointer */ 848 #define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ 849 #define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ 850 #define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ 851 #define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ 852 #define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ 853 #define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ 854 #define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ 855 #define PDM_S ((PDM_TypeDef *) PDM_S_BASE) /**< PDM_S base pointer */ 856 #define ETAMPDET_S ((ETAMPDET_TypeDef *) ETAMPDET_S_BASE) /**< ETAMPDET_S base pointer */ 857 #define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ 858 #define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ 859 #define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ 860 #define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ 861 #define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ 862 #define RTCC_S ((RTCC_TypeDef *) RTCC_S_BASE) /**< RTCC_S base pointer */ 863 #define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ 864 #define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ 865 #define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ 866 #define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ 867 #define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ 868 #define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ 869 #define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ 870 #define PRORTC_S ((RTCC_TypeDef *) PRORTC_S_BASE) /**< PRORTC_S base pointer */ 871 #define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ 872 #define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ 873 #define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ 874 #define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ 875 #define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ 876 #define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ 877 #define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ 878 #define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ 879 #define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ 880 #define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ 881 #define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ 882 #define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ 883 #define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ 884 #define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ 885 #define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ 886 #define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ 887 #define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ 888 #define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ 889 #define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ 890 #define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ 891 #define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ 892 #define USART1_NS ((USART_TypeDef *) USART1_NS_BASE) /**< USART1_NS base pointer */ 893 #define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ 894 #define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ 895 #define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ 896 #define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ 897 #define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ 898 #define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ 899 #define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ 900 #define PDM_NS ((PDM_TypeDef *) PDM_NS_BASE) /**< PDM_NS base pointer */ 901 #define ETAMPDET_NS ((ETAMPDET_TypeDef *) ETAMPDET_NS_BASE) /**< ETAMPDET_NS base pointer */ 902 #define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ 903 #define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ 904 #define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ 905 #define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ 906 #define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ 907 #define RTCC_NS ((RTCC_TypeDef *) RTCC_NS_BASE) /**< RTCC_NS base pointer */ 908 #define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ 909 #define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ 910 #define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ 911 #define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ 912 #define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ 913 #define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ 914 #define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ 915 #define PRORTC_NS ((RTCC_TypeDef *) PRORTC_NS_BASE) /**< PRORTC_NS base pointer */ 916 #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ 917 #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ 918 #define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ 919 #define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ 920 #define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ 921 #define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ 922 #define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ 923 #define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ 924 #define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ 925 #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ 926 #define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ 927 #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ 928 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ 929 #define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ 930 #define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ 931 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ 932 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ 933 #define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ 934 #define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ 935 #define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ 936 #define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ 937 #define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ 938 #define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ 939 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ 940 #define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ 941 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ 942 #define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ 943 #define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ 944 #define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ 945 #define PDM ((PDM_TypeDef *) PDM_BASE) /**< PDM base pointer */ 946 #define ETAMPDET ((ETAMPDET_TypeDef *) ETAMPDET_BASE) /**< ETAMPDET base pointer */ 947 #define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ 948 #define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ 949 #define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ 950 #define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ 951 #define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ 952 #define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ 953 #define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ 954 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ 955 #define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ 956 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ 957 #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ 958 #define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ 959 #define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ 960 #define PRORTC ((RTCC_TypeDef *) PRORTC_BASE) /**< PRORTC base pointer */ 961 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ 962 /** @} End of group EFR32BG29B221F1024CJ45_Peripheral_Declaration */ 963 964 /**************************************************************************//** 965 * @defgroup EFR32BG29B221F1024CJ45_Peripheral_Parameters EFR32BG29B221F1024CJ45 Peripheral Parameters 966 * @{ 967 * @brief Device peripheral parameter values 968 *****************************************************************************/ 969 970 /* Common peripheral register block offsets. */ 971 #define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ 972 #define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ 973 #define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ 974 #define MSC_CDA_PRESENT 0x0UL /**> */ 975 #define MSC_FDIO_WIDTH 0x40UL /**> None */ 976 #define MSC_FLASHADDRBITS 0x15UL /**> None */ 977 #define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ 978 #define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ 979 #define MSC_FLASH_BLOCK_MAIN_PCOUNT 0x90UL /**> */ 980 #define MSC_INFOADDRBITS 0xEUL /**> None */ 981 #define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ 982 #define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ 983 #define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ 984 #define MSC_REDUNDANCY 0x2UL /**> None */ 985 #define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ 986 #define MSC_UD_PRESENT 0x1UL /**> */ 987 #define MSC_YADDRBITS 0x6UL /**> */ 988 #define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ 989 #define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ 990 #define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ 991 #define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ 992 #define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ 993 #define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ 994 #define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ 995 #define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ 996 #define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ 997 #define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ 998 #define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ 999 #define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ 1000 #define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ 1001 #define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ 1002 #define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ 1003 #define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ 1004 #define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ 1005 #define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ 1006 #define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ 1007 #define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ 1008 #define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ 1009 #define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ 1010 #define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ 1011 #define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ 1012 #define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ 1013 #define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ 1014 #define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ 1015 #define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ 1016 #define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ 1017 #define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ 1018 #define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ 1019 #define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ 1020 #define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ 1021 #define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ 1022 #define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ 1023 #define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ 1024 #define DMEM_NUM_PORTS 0x2UL /**> Number of AHB slave ports */ 1025 #define DMEM_NUM_PORTS_IS_2 0x1UL /**> Boolean indicating if NUM_PORTS=2 */ 1026 #define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ 1027 #define HFRCO0_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ 1028 #define HFRCO0_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ 1029 #define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ 1030 #define LFXO_CTUNE 0x1UL /**> CTUNE Present */ 1031 #define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ 1032 #define ICACHE0_CACHEABLE_SIZE 0x100000UL /**> Cache Size */ 1033 #define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ 1034 #define ICACHE0_DEFAULT_OFF 0x1UL /**> Default off */ 1035 #define ICACHE0_FLASH_SIZE 0x100000UL /**> Flash size */ 1036 #define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ 1037 #define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ 1038 #define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ 1039 #define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ 1040 #define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ 1041 #define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ 1042 #define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ 1043 #define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ 1044 #define ICACHE0_SET_BITS 0x5UL /**> Set bits */ 1045 #define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ 1046 #define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ 1047 #define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ 1048 #define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ 1049 #define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ 1050 #define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ 1051 #define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ 1052 #define PRS_ASYNC_CH_NUM 0xCUL /**> None */ 1053 #define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ 1054 #define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ 1055 #define PRS_SYNC_CH_NUM 0x4UL /**> None */ 1056 #define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ 1057 #define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ 1058 #define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ 1059 #define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ 1060 #define GPIO_NUM_EVEN_PC 0x4UL /**> Num of even pins port C */ 1061 #define GPIO_NUM_EVEN_PD 0x2UL /**> Num of even pins port D */ 1062 #define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ 1063 #define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ 1064 #define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ 1065 #define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ 1066 #define GPIO_NUM_ODD_PA 0x4UL /**> Num of odd pins port A */ 1067 #define GPIO_NUM_ODD_PB 0x2UL /**> Num of odd pins port B */ 1068 #define GPIO_NUM_ODD_PC 0x4UL /**> Num of odd pins port C */ 1069 #define GPIO_NUM_ODD_PD 0x2UL /**> Num of odd pins port D */ 1070 #define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ 1071 #define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ 1072 #define GPIO_PORT_A_WIDTH 0x9UL /**> Port A Width */ 1073 #define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ 1074 #define GPIO_PORT_A_WL 0x8UL /**> New Param */ 1075 #define GPIO_PORT_A_WU 0x1UL /**> New Param */ 1076 #define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ 1077 #define GPIO_PORT_B_WIDTH 0x5UL /**> Port B Width */ 1078 #define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ 1079 #define GPIO_PORT_B_WL 0x5UL /**> New Param */ 1080 #define GPIO_PORT_B_WU 0x0UL /**> New Param */ 1081 #define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ 1082 #define GPIO_PORT_C_WIDTH 0x8UL /**> Port C Width */ 1083 #define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ 1084 #define GPIO_PORT_C_WL 0x8UL /**> New Param */ 1085 #define GPIO_PORT_C_WU 0x0UL /**> New Param */ 1086 #define GPIO_PORT_C_WU_ZERO 0x1UL /**> New Param */ 1087 #define GPIO_PORT_D_WIDTH 0x4UL /**> Port D Width */ 1088 #define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ 1089 #define GPIO_PORT_D_WL 0x4UL /**> New Param */ 1090 #define GPIO_PORT_D_WU 0x0UL /**> New Param */ 1091 #define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ 1092 #define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ 1093 #define LDMA_CH_BITS 0x5UL /**> New Param */ 1094 #define LDMA_CH_NUM 0x8UL /**> New Param */ 1095 #define LDMA_FIFO_BITS 0x5UL /**> New Param */ 1096 #define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ 1097 #define LDMAXBAR_CH_BITS 0x5UL /**> None */ 1098 #define LDMAXBAR_CH_NUM 0x8UL /**> None */ 1099 #define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ 1100 #define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ 1101 #define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ 1102 #define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ 1103 #define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ 1104 #define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ 1105 #define TIMER0_NO_DTI 0x0UL /**> */ 1106 #define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ 1107 #define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ 1108 #define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ 1109 #define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ 1110 #define TIMER1_NO_DTI 0x0UL /**> */ 1111 #define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ 1112 #define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ 1113 #define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ 1114 #define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ 1115 #define TIMER2_NO_DTI 0x0UL /**> */ 1116 #define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ 1117 #define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ 1118 #define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ 1119 #define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ 1120 #define TIMER3_NO_DTI 0x0UL /**> */ 1121 #define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ 1122 #define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ 1123 #define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ 1124 #define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ 1125 #define TIMER4_NO_DTI 0x0UL /**> */ 1126 #define USART0_AUTOTX_REG 0x1UL /**> None */ 1127 #define USART0_AUTOTX_REG_B 0x0UL /**> None */ 1128 #define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ 1129 #define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ 1130 #define USART0_CLK_PRS 0x1UL /**> None */ 1131 #define USART0_CLK_PRS_B 0x0UL /**> New Param */ 1132 #define USART0_FLOW_CONTROL 0x1UL /**> None */ 1133 #define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ 1134 #define USART0_I2S 0x1UL /**> None */ 1135 #define USART0_I2S_B 0x0UL /**> New Param */ 1136 #define USART0_IRDA_AVAILABLE 0x1UL /**> None */ 1137 #define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ 1138 #define USART0_MVDIS_FUNC 0x1UL /**> None */ 1139 #define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ 1140 #define USART0_RX_PRS 0x1UL /**> None */ 1141 #define USART0_RX_PRS_B 0x0UL /**> New Param */ 1142 #define USART0_SC_AVAILABLE 0x1UL /**> None */ 1143 #define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ 1144 #define USART0_SYNC_AVAILABLE 0x1UL /**> None */ 1145 #define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ 1146 #define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ 1147 #define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ 1148 #define USART0_TIMER 0x1UL /**> New Param */ 1149 #define USART0_TIMER_B 0x0UL /**> New Param */ 1150 #define USART1_AUTOTX_REG 0x1UL /**> None */ 1151 #define USART1_AUTOTX_REG_B 0x0UL /**> None */ 1152 #define USART1_AUTOTX_TRIGGER 0x1UL /**> None */ 1153 #define USART1_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ 1154 #define USART1_CLK_PRS 0x1UL /**> None */ 1155 #define USART1_CLK_PRS_B 0x0UL /**> New Param */ 1156 #define USART1_FLOW_CONTROL 0x1UL /**> None */ 1157 #define USART1_FLOW_CONTROL_B 0x0UL /**> New Param */ 1158 #define USART1_I2S 0x1UL /**> None */ 1159 #define USART1_I2S_B 0x0UL /**> New Param */ 1160 #define USART1_IRDA_AVAILABLE 0x1UL /**> None */ 1161 #define USART1_IRDA_AVAILABLE_B 0x0UL /**> New Param */ 1162 #define USART1_MVDIS_FUNC 0x1UL /**> None */ 1163 #define USART1_MVDIS_FUNC_B 0x0UL /**> New Param */ 1164 #define USART1_RX_PRS 0x1UL /**> None */ 1165 #define USART1_RX_PRS_B 0x0UL /**> New Param */ 1166 #define USART1_SC_AVAILABLE 0x1UL /**> None */ 1167 #define USART1_SC_AVAILABLE_B 0x0UL /**> New Param */ 1168 #define USART1_SYNC_AVAILABLE 0x1UL /**> None */ 1169 #define USART1_SYNC_AVAILABLE_B 0x0UL /**> New Param */ 1170 #define USART1_SYNC_LATE_SAMPLE 0x1UL /**> None */ 1171 #define USART1_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ 1172 #define USART1_TIMER 0x1UL /**> New Param */ 1173 #define USART1_TIMER_B 0x0UL /**> New Param */ 1174 #define BURTC_CNTWIDTH 0x20UL /**> None */ 1175 #define BURTC_PRECNT_WIDTH 0xFUL /**> */ 1176 #define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ 1177 #define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ 1178 #define SYSCFG_CHIP_PARTNUMBER 0x4UL /**> Chip Part Number */ 1179 #define SYSCFG_DEMODRAM_INST_COUNT 0x1UL /**> */ 1180 #define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ 1181 #define SYSCFG_RAM0_INST_COUNT 0x10UL /**> None */ 1182 #define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ 1183 #define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ 1184 #define DCDC_DCDCMODE_WIDTH 0x1UL /**> Mode register width */ 1185 #define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ 1186 #define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ 1187 #define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ 1188 #define PDM_FIFO_LEN 0x4UL /**> New Param */ 1189 #define PDM_NUM_CH 0x2UL /**> None */ 1190 #define PDM_CH2_PRESENT_B 0x1UL /**> New Param */ 1191 #define PDM_CH3_PRESENT_B 0x1UL /**> New Param */ 1192 #define PDM_NUM_CH_WIDTH 0x1UL /**> New Param */ 1193 #define PDM_PIPELINE 0x0UL /**> None */ 1194 #define PDM_STEREO23_PRESENT_B 0x1UL /**> New Param */ 1195 #define ETAMPDET_NUM_CHNLS 0x2UL /**> */ 1196 #define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ 1197 #define EUSART1_EXCLUDE_DALI 0x0UL /**> Exclude DALI */ 1198 #define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ 1199 #define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ 1200 #define SMU_NUM_BMPUS 0x5UL /**> Number of BMPUs */ 1201 #define SMU_NUM_PPU_PERIPHS 0x32UL /**> Number of PPU Peripherals */ 1202 #define SMU_NUM_PPU_PERIPHS_MOD_32 0x12UL /**> Number of PPU Peripherals (mod 32) */ 1203 #define SMU_NUM_PPU_PERIPHS_SUB_32 0x12UL /**> Number of PPU peripherals minus 32 */ 1204 #define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ 1205 #define RTCC_CC_NUM 0x3UL /**> None */ 1206 #define WDOG0_PCNUM 0x2UL /**> None */ 1207 #define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ 1208 #define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ 1209 #define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ 1210 #define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ 1211 #define IADC0_ENTRIES 0x10UL /**> ENTRIES */ 1212 #define ACMP0_DAC_INPUT 0x0UL /**> None */ 1213 #define ACMP0_EXT_OVR_IF 0x0UL /**> None */ 1214 #define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ 1215 #define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ 1216 #define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ 1217 #define EUSART0_EXCLUDE_DALI 0x1UL /**> Exclude DALI */ 1218 #define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ 1219 #define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ 1220 #define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ 1221 #define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ 1222 #define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ 1223 #define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ 1224 #define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ 1225 #define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ 1226 #define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ 1227 #define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ 1228 #define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ 1229 #define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ 1230 #define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ 1231 #define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ 1232 #define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ 1233 #define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ 1234 #define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ 1235 #define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ 1236 #define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ 1237 #define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ 1238 #define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ 1239 #define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ 1240 #define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ 1241 #define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ 1242 #define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ 1243 #define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ 1244 #define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ 1245 #define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ 1246 #define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ 1247 #define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ 1248 #define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ 1249 #define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ 1250 #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ 1251 #define PRORTC_CC_NUM 0x2UL /**> None */ 1252 1253 /* Instance macros for ACMP */ 1254 #define ACMP(n) (((n) == 0) ? ACMP0 \ 1255 : 0x0UL) 1256 #define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ 1257 : -1) 1258 #define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ 1259 : 0x0UL) 1260 #define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ 1261 : 0x0UL) 1262 1263 /* Instance macros for EUSART */ 1264 #define EUSART(n) (((n) == 0) ? EUSART0 \ 1265 : ((n) == 1) ? EUSART1 \ 1266 : 0x0UL) 1267 #define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ 1268 : ((ref) == EUSART1) ? 1 \ 1269 : -1) 1270 #define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ 1271 : ((n) == 1) ? EUSART1_EM2_CAPABLE \ 1272 : 0x0UL) 1273 #define EUSART_EXCLUDE_DALI(n) (((n) == 0) ? EUSART0_EXCLUDE_DALI \ 1274 : ((n) == 1) ? EUSART1_EXCLUDE_DALI \ 1275 : 0x0UL) 1276 #define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ 1277 : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ 1278 : 0x0UL) 1279 1280 /* Instance macros for I2C */ 1281 #define I2C(n) (((n) == 0) ? I2C0 \ 1282 : ((n) == 1) ? I2C1 \ 1283 : 0x0UL) 1284 #define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ 1285 : ((ref) == I2C1) ? 1 \ 1286 : -1) 1287 #define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ 1288 : ((n) == 1) ? I2C1_DELAY \ 1289 : 0x0UL) 1290 #define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ 1291 : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ 1292 : 0x0UL) 1293 1294 /* Instance macros for IADC */ 1295 #define IADC(n) (((n) == 0) ? IADC0 \ 1296 : 0x0UL) 1297 #define IADC_NUM(ref) (((ref) == IADC0) ? 0 \ 1298 : -1) 1299 #define IADC_CONFIGNUM(n) (((n) == 0) ? IADC0_CONFIGNUM \ 1300 : 0x0UL) 1301 #define IADC_FULLRANGEUNIPOLAR(n) (((n) == 0) ? IADC0_FULLRANGEUNIPOLAR \ 1302 : 0x0UL) 1303 #define IADC_SCANBYTES(n) (((n) == 0) ? IADC0_SCANBYTES \ 1304 : 0x0UL) 1305 #define IADC_ENTRIES(n) (((n) == 0) ? IADC0_ENTRIES \ 1306 : 0x0UL) 1307 1308 /* Instance macros for LETIMER */ 1309 #define LETIMER(n) (((n) == 0) ? LETIMER0 \ 1310 : 0x0UL) 1311 #define LETIMER_NUM(ref) (((ref) == LETIMER0) ? 0 \ 1312 : -1) 1313 #define LETIMER_CNT_WIDTH(n) (((n) == 0) ? LETIMER0_CNT_WIDTH \ 1314 : 0x0UL) 1315 1316 /* Instance macros for TIMER */ 1317 #define TIMER(n) (((n) == 0) ? TIMER0 \ 1318 : ((n) == 1) ? TIMER1 \ 1319 : ((n) == 2) ? TIMER2 \ 1320 : ((n) == 3) ? TIMER3 \ 1321 : ((n) == 4) ? TIMER4 \ 1322 : 0x0UL) 1323 #define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ 1324 : ((ref) == TIMER1) ? 1 \ 1325 : ((ref) == TIMER2) ? 2 \ 1326 : ((ref) == TIMER3) ? 3 \ 1327 : ((ref) == TIMER4) ? 4 \ 1328 : -1) 1329 #define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ 1330 : ((n) == 1) ? TIMER1_CC_NUM \ 1331 : ((n) == 2) ? TIMER2_CC_NUM \ 1332 : ((n) == 3) ? TIMER3_CC_NUM \ 1333 : ((n) == 4) ? TIMER4_CC_NUM \ 1334 : 0x0UL) 1335 #define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ 1336 : ((n) == 1) ? TIMER1_CNTWIDTH \ 1337 : ((n) == 2) ? TIMER2_CNTWIDTH \ 1338 : ((n) == 3) ? TIMER3_CNTWIDTH \ 1339 : ((n) == 4) ? TIMER4_CNTWIDTH \ 1340 : 0x0UL) 1341 #define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ 1342 : ((n) == 1) ? TIMER1_DTI \ 1343 : ((n) == 2) ? TIMER2_DTI \ 1344 : ((n) == 3) ? TIMER3_DTI \ 1345 : ((n) == 4) ? TIMER4_DTI \ 1346 : 0x0UL) 1347 #define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ 1348 : ((n) == 1) ? TIMER1_DTI_CC_NUM \ 1349 : ((n) == 2) ? TIMER2_DTI_CC_NUM \ 1350 : ((n) == 3) ? TIMER3_DTI_CC_NUM \ 1351 : ((n) == 4) ? TIMER4_DTI_CC_NUM \ 1352 : 0x0UL) 1353 #define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ 1354 : ((n) == 1) ? TIMER1_NO_DTI \ 1355 : ((n) == 2) ? TIMER2_NO_DTI \ 1356 : ((n) == 3) ? TIMER3_NO_DTI \ 1357 : ((n) == 4) ? TIMER4_NO_DTI \ 1358 : 0x0UL) 1359 1360 /* Instance macros for USART */ 1361 #define USART(n) (((n) == 0) ? USART0 \ 1362 : ((n) == 1) ? USART1 \ 1363 : 0x0UL) 1364 #define USART_NUM(ref) (((ref) == USART0) ? 0 \ 1365 : ((ref) == USART1) ? 1 \ 1366 : -1) 1367 #define USART_AUTOTX_REG(n) (((n) == 0) ? USART0_AUTOTX_REG \ 1368 : ((n) == 1) ? USART1_AUTOTX_REG \ 1369 : 0x0UL) 1370 #define USART_AUTOTX_REG_B(n) (((n) == 0) ? USART0_AUTOTX_REG_B \ 1371 : ((n) == 1) ? USART1_AUTOTX_REG_B \ 1372 : 0x0UL) 1373 #define USART_AUTOTX_TRIGGER(n) (((n) == 0) ? USART0_AUTOTX_TRIGGER \ 1374 : ((n) == 1) ? USART1_AUTOTX_TRIGGER \ 1375 : 0x0UL) 1376 #define USART_AUTOTX_TRIGGER_B(n) (((n) == 0) ? USART0_AUTOTX_TRIGGER_B \ 1377 : ((n) == 1) ? USART1_AUTOTX_TRIGGER_B \ 1378 : 0x0UL) 1379 #define USART_CLK_PRS(n) (((n) == 0) ? USART0_CLK_PRS \ 1380 : ((n) == 1) ? USART1_CLK_PRS \ 1381 : 0x0UL) 1382 #define USART_CLK_PRS_B(n) (((n) == 0) ? USART0_CLK_PRS_B \ 1383 : ((n) == 1) ? USART1_CLK_PRS_B \ 1384 : 0x0UL) 1385 #define USART_FLOW_CONTROL(n) (((n) == 0) ? USART0_FLOW_CONTROL \ 1386 : ((n) == 1) ? USART1_FLOW_CONTROL \ 1387 : 0x0UL) 1388 #define USART_FLOW_CONTROL_B(n) (((n) == 0) ? USART0_FLOW_CONTROL_B \ 1389 : ((n) == 1) ? USART1_FLOW_CONTROL_B \ 1390 : 0x0UL) 1391 #define USART_I2S(n) (((n) == 0) ? USART0_I2S \ 1392 : ((n) == 1) ? USART1_I2S \ 1393 : 0x0UL) 1394 #define USART_I2S_B(n) (((n) == 0) ? USART0_I2S_B \ 1395 : ((n) == 1) ? USART1_I2S_B \ 1396 : 0x0UL) 1397 #define USART_IRDA_AVAILABLE(n) (((n) == 0) ? USART0_IRDA_AVAILABLE \ 1398 : ((n) == 1) ? USART1_IRDA_AVAILABLE \ 1399 : 0x0UL) 1400 #define USART_IRDA_AVAILABLE_B(n) (((n) == 0) ? USART0_IRDA_AVAILABLE_B \ 1401 : ((n) == 1) ? USART1_IRDA_AVAILABLE_B \ 1402 : 0x0UL) 1403 #define USART_MVDIS_FUNC(n) (((n) == 0) ? USART0_MVDIS_FUNC \ 1404 : ((n) == 1) ? USART1_MVDIS_FUNC \ 1405 : 0x0UL) 1406 #define USART_MVDIS_FUNC_B(n) (((n) == 0) ? USART0_MVDIS_FUNC_B \ 1407 : ((n) == 1) ? USART1_MVDIS_FUNC_B \ 1408 : 0x0UL) 1409 #define USART_RX_PRS(n) (((n) == 0) ? USART0_RX_PRS \ 1410 : ((n) == 1) ? USART1_RX_PRS \ 1411 : 0x0UL) 1412 #define USART_RX_PRS_B(n) (((n) == 0) ? USART0_RX_PRS_B \ 1413 : ((n) == 1) ? USART1_RX_PRS_B \ 1414 : 0x0UL) 1415 #define USART_SC_AVAILABLE(n) (((n) == 0) ? USART0_SC_AVAILABLE \ 1416 : ((n) == 1) ? USART1_SC_AVAILABLE \ 1417 : 0x0UL) 1418 #define USART_SC_AVAILABLE_B(n) (((n) == 0) ? USART0_SC_AVAILABLE_B \ 1419 : ((n) == 1) ? USART1_SC_AVAILABLE_B \ 1420 : 0x0UL) 1421 #define USART_SYNC_AVAILABLE(n) (((n) == 0) ? USART0_SYNC_AVAILABLE \ 1422 : ((n) == 1) ? USART1_SYNC_AVAILABLE \ 1423 : 0x0UL) 1424 #define USART_SYNC_AVAILABLE_B(n) (((n) == 0) ? USART0_SYNC_AVAILABLE_B \ 1425 : ((n) == 1) ? USART1_SYNC_AVAILABLE_B \ 1426 : 0x0UL) 1427 #define USART_SYNC_LATE_SAMPLE(n) (((n) == 0) ? USART0_SYNC_LATE_SAMPLE \ 1428 : ((n) == 1) ? USART1_SYNC_LATE_SAMPLE \ 1429 : 0x0UL) 1430 #define USART_SYNC_LATE_SAMPLE_B(n) (((n) == 0) ? USART0_SYNC_LATE_SAMPLE_B \ 1431 : ((n) == 1) ? USART1_SYNC_LATE_SAMPLE_B \ 1432 : 0x0UL) 1433 #define USART_TIMER(n) (((n) == 0) ? USART0_TIMER \ 1434 : ((n) == 1) ? USART1_TIMER \ 1435 : 0x0UL) 1436 #define USART_TIMER_B(n) (((n) == 0) ? USART0_TIMER_B \ 1437 : ((n) == 1) ? USART1_TIMER_B \ 1438 : 0x0UL) 1439 1440 /* Instance macros for WDOG */ 1441 #define WDOG(n) (((n) == 0) ? WDOG0 \ 1442 : 0x0UL) 1443 #define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ 1444 : -1) 1445 #define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ 1446 : 0x0UL) 1447 1448 /** @} End of group EFR32BG29B221F1024CJ45_Peripheral_Parameters */ 1449 1450 /** @} End of group EFR32BG29B221F1024CJ45 */ 1451 /** @}} End of group Parts */ 1452 1453 #ifdef __cplusplus 1454 } 1455 #endif 1456 #endif 1457
