1 /**************************************************************************//** 2 * @file 3 * @brief EFR32BG27 SYSCFG register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2024 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32BG27_SYSCFG_H 31 #define EFR32BG27_SYSCFG_H 32 #define SYSCFG_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32BG27_SYSCFG SYSCFG 40 * @{ 41 * @brief EFR32BG27 SYSCFG Register Declaration. 42 *****************************************************************************/ 43 44 /** SYSCFG Register Declaration. */ 45 typedef struct syscfg_typedef{ 46 __IM uint32_t IPVERSION; /**< IP version ID */ 47 __IOM uint32_t IF; /**< Interrupt Flag */ 48 __IOM uint32_t IEN; /**< Interrupt Enable */ 49 uint32_t RESERVED0[1U]; /**< Reserved for future use */ 50 __IOM uint32_t CHIPREVHW; /**< Chip Revision, Hard-wired */ 51 __IOM uint32_t CHIPREV; /**< Chip Revision */ 52 uint32_t RESERVED1[2U]; /**< Reserved for future use */ 53 __IOM uint32_t CFGSYSTIC; /**< SysTick clock source */ 54 uint32_t RESERVED2[55U]; /**< Reserved for future use */ 55 uint32_t RESERVED3[1U]; /**< Reserved for future use */ 56 uint32_t RESERVED4[63U]; /**< Reserved for future use */ 57 __IOM uint32_t CTRL; /**< Control */ 58 uint32_t RESERVED5[1U]; /**< Reserved for future use */ 59 __IOM uint32_t DMEM0RETNCTRL; /**< DMEM0 Retention Control */ 60 uint32_t RESERVED6[1U]; /**< Reserved for future use */ 61 __IM uint32_t DMEM0ECCADDR; /**< DMEM0 ECC Address */ 62 __IOM uint32_t DMEM0ECCCTRL; /**< DMEM0 ECC Control */ 63 uint32_t RESERVED7[61U]; /**< Reserved for future use */ 64 __IOM uint32_t RAMBIASCONF; /**< RAM Bias Configuration */ 65 uint32_t RESERVED8[60U]; /**< Reserved for future use */ 66 __IOM uint32_t RADIORAMRETNCTRL; /**< RADIO SEQRAM Retention Control */ 67 uint32_t RESERVED9[1U]; /**< Reserved for future use */ 68 __IOM uint32_t RADIOECCCTRL; /**< RADIO SEQRAM ECC Control */ 69 uint32_t RESERVED10[1U]; /**< Reserved for future use */ 70 __IM uint32_t SEQRAMECCADDR; /**< SEQRAM ECC Address */ 71 __IM uint32_t FRCRAMECCADDR; /**< FRCRAM ECC Address */ 72 __IOM uint32_t ICACHERAMRETNCTRL; /**< HOST ICACHERAM Retention Control */ 73 uint32_t RESERVED11[121U]; /**< Reserved for future use */ 74 __IOM uint32_t ROOTDATA0; /**< Data Register 0 */ 75 __IOM uint32_t ROOTDATA1; /**< Data Register 1 */ 76 __IM uint32_t ROOTLOCKSTATUS; /**< Lock Status */ 77 __IOM uint32_t ROOTSESWVERSION; /**< SE SW Version */ 78 uint32_t RESERVED12[636U]; /**< Reserved for future use */ 79 __IM uint32_t IPVERSION_SET; /**< IP version ID */ 80 __IOM uint32_t IF_SET; /**< Interrupt Flag */ 81 __IOM uint32_t IEN_SET; /**< Interrupt Enable */ 82 uint32_t RESERVED13[1U]; /**< Reserved for future use */ 83 __IOM uint32_t CHIPREVHW_SET; /**< Chip Revision, Hard-wired */ 84 __IOM uint32_t CHIPREV_SET; /**< Chip Revision */ 85 uint32_t RESERVED14[2U]; /**< Reserved for future use */ 86 __IOM uint32_t CFGSYSTIC_SET; /**< SysTick clock source */ 87 uint32_t RESERVED15[55U]; /**< Reserved for future use */ 88 uint32_t RESERVED16[1U]; /**< Reserved for future use */ 89 uint32_t RESERVED17[63U]; /**< Reserved for future use */ 90 __IOM uint32_t CTRL_SET; /**< Control */ 91 uint32_t RESERVED18[1U]; /**< Reserved for future use */ 92 __IOM uint32_t DMEM0RETNCTRL_SET; /**< DMEM0 Retention Control */ 93 uint32_t RESERVED19[1U]; /**< Reserved for future use */ 94 __IM uint32_t DMEM0ECCADDR_SET; /**< DMEM0 ECC Address */ 95 __IOM uint32_t DMEM0ECCCTRL_SET; /**< DMEM0 ECC Control */ 96 uint32_t RESERVED20[61U]; /**< Reserved for future use */ 97 __IOM uint32_t RAMBIASCONF_SET; /**< RAM Bias Configuration */ 98 uint32_t RESERVED21[60U]; /**< Reserved for future use */ 99 __IOM uint32_t RADIORAMRETNCTRL_SET; /**< RADIO SEQRAM Retention Control */ 100 uint32_t RESERVED22[1U]; /**< Reserved for future use */ 101 __IOM uint32_t RADIOECCCTRL_SET; /**< RADIO SEQRAM ECC Control */ 102 uint32_t RESERVED23[1U]; /**< Reserved for future use */ 103 __IM uint32_t SEQRAMECCADDR_SET; /**< SEQRAM ECC Address */ 104 __IM uint32_t FRCRAMECCADDR_SET; /**< FRCRAM ECC Address */ 105 __IOM uint32_t ICACHERAMRETNCTRL_SET; /**< HOST ICACHERAM Retention Control */ 106 uint32_t RESERVED24[121U]; /**< Reserved for future use */ 107 __IOM uint32_t ROOTDATA0_SET; /**< Data Register 0 */ 108 __IOM uint32_t ROOTDATA1_SET; /**< Data Register 1 */ 109 __IM uint32_t ROOTLOCKSTATUS_SET; /**< Lock Status */ 110 __IOM uint32_t ROOTSESWVERSION_SET; /**< SE SW Version */ 111 uint32_t RESERVED25[636U]; /**< Reserved for future use */ 112 __IM uint32_t IPVERSION_CLR; /**< IP version ID */ 113 __IOM uint32_t IF_CLR; /**< Interrupt Flag */ 114 __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ 115 uint32_t RESERVED26[1U]; /**< Reserved for future use */ 116 __IOM uint32_t CHIPREVHW_CLR; /**< Chip Revision, Hard-wired */ 117 __IOM uint32_t CHIPREV_CLR; /**< Chip Revision */ 118 uint32_t RESERVED27[2U]; /**< Reserved for future use */ 119 __IOM uint32_t CFGSYSTIC_CLR; /**< SysTick clock source */ 120 uint32_t RESERVED28[55U]; /**< Reserved for future use */ 121 uint32_t RESERVED29[1U]; /**< Reserved for future use */ 122 uint32_t RESERVED30[63U]; /**< Reserved for future use */ 123 __IOM uint32_t CTRL_CLR; /**< Control */ 124 uint32_t RESERVED31[1U]; /**< Reserved for future use */ 125 __IOM uint32_t DMEM0RETNCTRL_CLR; /**< DMEM0 Retention Control */ 126 uint32_t RESERVED32[1U]; /**< Reserved for future use */ 127 __IM uint32_t DMEM0ECCADDR_CLR; /**< DMEM0 ECC Address */ 128 __IOM uint32_t DMEM0ECCCTRL_CLR; /**< DMEM0 ECC Control */ 129 uint32_t RESERVED33[61U]; /**< Reserved for future use */ 130 __IOM uint32_t RAMBIASCONF_CLR; /**< RAM Bias Configuration */ 131 uint32_t RESERVED34[60U]; /**< Reserved for future use */ 132 __IOM uint32_t RADIORAMRETNCTRL_CLR; /**< RADIO SEQRAM Retention Control */ 133 uint32_t RESERVED35[1U]; /**< Reserved for future use */ 134 __IOM uint32_t RADIOECCCTRL_CLR; /**< RADIO SEQRAM ECC Control */ 135 uint32_t RESERVED36[1U]; /**< Reserved for future use */ 136 __IM uint32_t SEQRAMECCADDR_CLR; /**< SEQRAM ECC Address */ 137 __IM uint32_t FRCRAMECCADDR_CLR; /**< FRCRAM ECC Address */ 138 __IOM uint32_t ICACHERAMRETNCTRL_CLR; /**< HOST ICACHERAM Retention Control */ 139 uint32_t RESERVED37[121U]; /**< Reserved for future use */ 140 __IOM uint32_t ROOTDATA0_CLR; /**< Data Register 0 */ 141 __IOM uint32_t ROOTDATA1_CLR; /**< Data Register 1 */ 142 __IM uint32_t ROOTLOCKSTATUS_CLR; /**< Lock Status */ 143 __IOM uint32_t ROOTSESWVERSION_CLR; /**< SE SW Version */ 144 uint32_t RESERVED38[636U]; /**< Reserved for future use */ 145 __IM uint32_t IPVERSION_TGL; /**< IP version ID */ 146 __IOM uint32_t IF_TGL; /**< Interrupt Flag */ 147 __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ 148 uint32_t RESERVED39[1U]; /**< Reserved for future use */ 149 __IOM uint32_t CHIPREVHW_TGL; /**< Chip Revision, Hard-wired */ 150 __IOM uint32_t CHIPREV_TGL; /**< Chip Revision */ 151 uint32_t RESERVED40[2U]; /**< Reserved for future use */ 152 __IOM uint32_t CFGSYSTIC_TGL; /**< SysTick clock source */ 153 uint32_t RESERVED41[55U]; /**< Reserved for future use */ 154 uint32_t RESERVED42[1U]; /**< Reserved for future use */ 155 uint32_t RESERVED43[63U]; /**< Reserved for future use */ 156 __IOM uint32_t CTRL_TGL; /**< Control */ 157 uint32_t RESERVED44[1U]; /**< Reserved for future use */ 158 __IOM uint32_t DMEM0RETNCTRL_TGL; /**< DMEM0 Retention Control */ 159 uint32_t RESERVED45[1U]; /**< Reserved for future use */ 160 __IM uint32_t DMEM0ECCADDR_TGL; /**< DMEM0 ECC Address */ 161 __IOM uint32_t DMEM0ECCCTRL_TGL; /**< DMEM0 ECC Control */ 162 uint32_t RESERVED46[61U]; /**< Reserved for future use */ 163 __IOM uint32_t RAMBIASCONF_TGL; /**< RAM Bias Configuration */ 164 uint32_t RESERVED47[60U]; /**< Reserved for future use */ 165 __IOM uint32_t RADIORAMRETNCTRL_TGL; /**< RADIO SEQRAM Retention Control */ 166 uint32_t RESERVED48[1U]; /**< Reserved for future use */ 167 __IOM uint32_t RADIOECCCTRL_TGL; /**< RADIO SEQRAM ECC Control */ 168 uint32_t RESERVED49[1U]; /**< Reserved for future use */ 169 __IM uint32_t SEQRAMECCADDR_TGL; /**< SEQRAM ECC Address */ 170 __IM uint32_t FRCRAMECCADDR_TGL; /**< FRCRAM ECC Address */ 171 __IOM uint32_t ICACHERAMRETNCTRL_TGL; /**< HOST ICACHERAM Retention Control */ 172 uint32_t RESERVED50[121U]; /**< Reserved for future use */ 173 __IOM uint32_t ROOTDATA0_TGL; /**< Data Register 0 */ 174 __IOM uint32_t ROOTDATA1_TGL; /**< Data Register 1 */ 175 __IM uint32_t ROOTLOCKSTATUS_TGL; /**< Lock Status */ 176 __IOM uint32_t ROOTSESWVERSION_TGL; /**< SE SW Version */ 177 } SYSCFG_TypeDef; 178 /** @} End of group EFR32BG27_SYSCFG */ 179 180 /**************************************************************************//** 181 * @addtogroup EFR32BG27_SYSCFG 182 * @{ 183 * @defgroup EFR32BG27_SYSCFG_BitFields SYSCFG Bit Fields 184 * @{ 185 *****************************************************************************/ 186 187 /* Bit fields for SYSCFG IPVERSION */ 188 #define _SYSCFG_IPVERSION_RESETVALUE 0x00000005UL /**< Default value for SYSCFG_IPVERSION */ 189 #define _SYSCFG_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_IPVERSION */ 190 #define _SYSCFG_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for SYSCFG_IPVERSION */ 191 #define _SYSCFG_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_IPVERSION */ 192 #define _SYSCFG_IPVERSION_IPVERSION_DEFAULT 0x00000005UL /**< Mode DEFAULT for SYSCFG_IPVERSION */ 193 #define SYSCFG_IPVERSION_IPVERSION_DEFAULT (_SYSCFG_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_IPVERSION */ 194 195 /* Bit fields for SYSCFG IF */ 196 #define _SYSCFG_IF_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_IF */ 197 #define _SYSCFG_IF_MASK 0x33033F0FUL /**< Mask for SYSCFG_IF */ 198 #define SYSCFG_IF_SW0 (0x1UL << 0) /**< Software Interrupt Flag */ 199 #define _SYSCFG_IF_SW0_SHIFT 0 /**< Shift value for SYSCFG_SW0 */ 200 #define _SYSCFG_IF_SW0_MASK 0x1UL /**< Bit mask for SYSCFG_SW0 */ 201 #define _SYSCFG_IF_SW0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ 202 #define SYSCFG_IF_SW0_DEFAULT (_SYSCFG_IF_SW0_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_IF */ 203 #define SYSCFG_IF_SW1 (0x1UL << 1) /**< Software Interrupt Flag */ 204 #define _SYSCFG_IF_SW1_SHIFT 1 /**< Shift value for SYSCFG_SW1 */ 205 #define _SYSCFG_IF_SW1_MASK 0x2UL /**< Bit mask for SYSCFG_SW1 */ 206 #define _SYSCFG_IF_SW1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ 207 #define SYSCFG_IF_SW1_DEFAULT (_SYSCFG_IF_SW1_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_IF */ 208 #define SYSCFG_IF_SW2 (0x1UL << 2) /**< Software Interrupt Flag */ 209 #define _SYSCFG_IF_SW2_SHIFT 2 /**< Shift value for SYSCFG_SW2 */ 210 #define _SYSCFG_IF_SW2_MASK 0x4UL /**< Bit mask for SYSCFG_SW2 */ 211 #define _SYSCFG_IF_SW2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ 212 #define SYSCFG_IF_SW2_DEFAULT (_SYSCFG_IF_SW2_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_IF */ 213 #define SYSCFG_IF_SW3 (0x1UL << 3) /**< Software Interrupt Flag */ 214 #define _SYSCFG_IF_SW3_SHIFT 3 /**< Shift value for SYSCFG_SW3 */ 215 #define _SYSCFG_IF_SW3_MASK 0x8UL /**< Bit mask for SYSCFG_SW3 */ 216 #define _SYSCFG_IF_SW3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ 217 #define SYSCFG_IF_SW3_DEFAULT (_SYSCFG_IF_SW3_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSCFG_IF */ 218 #define SYSCFG_IF_FPIOC (0x1UL << 8) /**< FPU Invalid Operation interrupt flag */ 219 #define _SYSCFG_IF_FPIOC_SHIFT 8 /**< Shift value for SYSCFG_FPIOC */ 220 #define _SYSCFG_IF_FPIOC_MASK 0x100UL /**< Bit mask for SYSCFG_FPIOC */ 221 #define _SYSCFG_IF_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ 222 #define SYSCFG_IF_FPIOC_DEFAULT (_SYSCFG_IF_FPIOC_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_IF */ 223 #define SYSCFG_IF_FPDZC (0x1UL << 9) /**< FPU Divide by zero interrupt flag */ 224 #define _SYSCFG_IF_FPDZC_SHIFT 9 /**< Shift value for SYSCFG_FPDZC */ 225 #define _SYSCFG_IF_FPDZC_MASK 0x200UL /**< Bit mask for SYSCFG_FPDZC */ 226 #define _SYSCFG_IF_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ 227 #define SYSCFG_IF_FPDZC_DEFAULT (_SYSCFG_IF_FPDZC_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSCFG_IF */ 228 #define SYSCFG_IF_FPUFC (0x1UL << 10) /**< FPU Underflow interrupt flag */ 229 #define _SYSCFG_IF_FPUFC_SHIFT 10 /**< Shift value for SYSCFG_FPUFC */ 230 #define _SYSCFG_IF_FPUFC_MASK 0x400UL /**< Bit mask for SYSCFG_FPUFC */ 231 #define _SYSCFG_IF_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ 232 #define SYSCFG_IF_FPUFC_DEFAULT (_SYSCFG_IF_FPUFC_DEFAULT << 10) /**< Shifted mode DEFAULT for SYSCFG_IF */ 233 #define SYSCFG_IF_FPOFC (0x1UL << 11) /**< FPU Overflow interrupt flag */ 234 #define _SYSCFG_IF_FPOFC_SHIFT 11 /**< Shift value for SYSCFG_FPOFC */ 235 #define _SYSCFG_IF_FPOFC_MASK 0x800UL /**< Bit mask for SYSCFG_FPOFC */ 236 #define _SYSCFG_IF_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ 237 #define SYSCFG_IF_FPOFC_DEFAULT (_SYSCFG_IF_FPOFC_DEFAULT << 11) /**< Shifted mode DEFAULT for SYSCFG_IF */ 238 #define SYSCFG_IF_FPIDC (0x1UL << 12) /**< FPU Input denormal interrupt flag */ 239 #define _SYSCFG_IF_FPIDC_SHIFT 12 /**< Shift value for SYSCFG_FPIDC */ 240 #define _SYSCFG_IF_FPIDC_MASK 0x1000UL /**< Bit mask for SYSCFG_FPIDC */ 241 #define _SYSCFG_IF_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ 242 #define SYSCFG_IF_FPIDC_DEFAULT (_SYSCFG_IF_FPIDC_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_IF */ 243 #define SYSCFG_IF_FPIXC (0x1UL << 13) /**< FPU Inexact interrupt flag */ 244 #define _SYSCFG_IF_FPIXC_SHIFT 13 /**< Shift value for SYSCFG_FPIXC */ 245 #define _SYSCFG_IF_FPIXC_MASK 0x2000UL /**< Bit mask for SYSCFG_FPIXC */ 246 #define _SYSCFG_IF_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ 247 #define SYSCFG_IF_FPIXC_DEFAULT (_SYSCFG_IF_FPIXC_DEFAULT << 13) /**< Shifted mode DEFAULT for SYSCFG_IF */ 248 #define SYSCFG_IF_RAMERR1B (0x1UL << 16) /**< RAM Error 1-Bit Interrupt Flag */ 249 #define _SYSCFG_IF_RAMERR1B_SHIFT 16 /**< Shift value for SYSCFG_RAMERR1B */ 250 #define _SYSCFG_IF_RAMERR1B_MASK 0x10000UL /**< Bit mask for SYSCFG_RAMERR1B */ 251 #define _SYSCFG_IF_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ 252 #define SYSCFG_IF_RAMERR1B_DEFAULT (_SYSCFG_IF_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_IF */ 253 #define SYSCFG_IF_RAMERR2B (0x1UL << 17) /**< RAM Error 2-Bit Interrupt Flag */ 254 #define _SYSCFG_IF_RAMERR2B_SHIFT 17 /**< Shift value for SYSCFG_RAMERR2B */ 255 #define _SYSCFG_IF_RAMERR2B_MASK 0x20000UL /**< Bit mask for SYSCFG_RAMERR2B */ 256 #define _SYSCFG_IF_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ 257 #define SYSCFG_IF_RAMERR2B_DEFAULT (_SYSCFG_IF_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for SYSCFG_IF */ 258 #define SYSCFG_IF_SEQRAMERR1B (0x1UL << 24) /**< SEQRAM Error 1-Bit Interrupt Flag */ 259 #define _SYSCFG_IF_SEQRAMERR1B_SHIFT 24 /**< Shift value for SYSCFG_SEQRAMERR1B */ 260 #define _SYSCFG_IF_SEQRAMERR1B_MASK 0x1000000UL /**< Bit mask for SYSCFG_SEQRAMERR1B */ 261 #define _SYSCFG_IF_SEQRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ 262 #define SYSCFG_IF_SEQRAMERR1B_DEFAULT (_SYSCFG_IF_SEQRAMERR1B_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_IF */ 263 #define SYSCFG_IF_SEQRAMERR2B (0x1UL << 25) /**< SEQRAM Error 2-Bit Interrupt Flag */ 264 #define _SYSCFG_IF_SEQRAMERR2B_SHIFT 25 /**< Shift value for SYSCFG_SEQRAMERR2B */ 265 #define _SYSCFG_IF_SEQRAMERR2B_MASK 0x2000000UL /**< Bit mask for SYSCFG_SEQRAMERR2B */ 266 #define _SYSCFG_IF_SEQRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ 267 #define SYSCFG_IF_SEQRAMERR2B_DEFAULT (_SYSCFG_IF_SEQRAMERR2B_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_IF */ 268 #define SYSCFG_IF_FRCRAMERR1B (0x1UL << 28) /**< FRCRAM Error 1-Bit Interrupt Flag */ 269 #define _SYSCFG_IF_FRCRAMERR1B_SHIFT 28 /**< Shift value for SYSCFG_FRCRAMERR1B */ 270 #define _SYSCFG_IF_FRCRAMERR1B_MASK 0x10000000UL /**< Bit mask for SYSCFG_FRCRAMERR1B */ 271 #define _SYSCFG_IF_FRCRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ 272 #define SYSCFG_IF_FRCRAMERR1B_DEFAULT (_SYSCFG_IF_FRCRAMERR1B_DEFAULT << 28) /**< Shifted mode DEFAULT for SYSCFG_IF */ 273 #define SYSCFG_IF_FRCRAMERR2B (0x1UL << 29) /**< FRCRAM Error 2-Bit Interrupt Flag */ 274 #define _SYSCFG_IF_FRCRAMERR2B_SHIFT 29 /**< Shift value for SYSCFG_FRCRAMERR2B */ 275 #define _SYSCFG_IF_FRCRAMERR2B_MASK 0x20000000UL /**< Bit mask for SYSCFG_FRCRAMERR2B */ 276 #define _SYSCFG_IF_FRCRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ 277 #define SYSCFG_IF_FRCRAMERR2B_DEFAULT (_SYSCFG_IF_FRCRAMERR2B_DEFAULT << 29) /**< Shifted mode DEFAULT for SYSCFG_IF */ 278 279 /* Bit fields for SYSCFG IEN */ 280 #define _SYSCFG_IEN_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_IEN */ 281 #define _SYSCFG_IEN_MASK 0x33033F0FUL /**< Mask for SYSCFG_IEN */ 282 #define SYSCFG_IEN_SW0 (0x1UL << 0) /**< Software Interrupt Enable */ 283 #define _SYSCFG_IEN_SW0_SHIFT 0 /**< Shift value for SYSCFG_SW0 */ 284 #define _SYSCFG_IEN_SW0_MASK 0x1UL /**< Bit mask for SYSCFG_SW0 */ 285 #define _SYSCFG_IEN_SW0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ 286 #define SYSCFG_IEN_SW0_DEFAULT (_SYSCFG_IEN_SW0_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_IEN */ 287 #define SYSCFG_IEN_SW1 (0x1UL << 1) /**< Software Interrupt Enable */ 288 #define _SYSCFG_IEN_SW1_SHIFT 1 /**< Shift value for SYSCFG_SW1 */ 289 #define _SYSCFG_IEN_SW1_MASK 0x2UL /**< Bit mask for SYSCFG_SW1 */ 290 #define _SYSCFG_IEN_SW1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ 291 #define SYSCFG_IEN_SW1_DEFAULT (_SYSCFG_IEN_SW1_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_IEN */ 292 #define SYSCFG_IEN_SW2 (0x1UL << 2) /**< Software Interrupt Enable */ 293 #define _SYSCFG_IEN_SW2_SHIFT 2 /**< Shift value for SYSCFG_SW2 */ 294 #define _SYSCFG_IEN_SW2_MASK 0x4UL /**< Bit mask for SYSCFG_SW2 */ 295 #define _SYSCFG_IEN_SW2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ 296 #define SYSCFG_IEN_SW2_DEFAULT (_SYSCFG_IEN_SW2_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_IEN */ 297 #define SYSCFG_IEN_SW3 (0x1UL << 3) /**< Software Interrupt Enable */ 298 #define _SYSCFG_IEN_SW3_SHIFT 3 /**< Shift value for SYSCFG_SW3 */ 299 #define _SYSCFG_IEN_SW3_MASK 0x8UL /**< Bit mask for SYSCFG_SW3 */ 300 #define _SYSCFG_IEN_SW3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ 301 #define SYSCFG_IEN_SW3_DEFAULT (_SYSCFG_IEN_SW3_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSCFG_IEN */ 302 #define SYSCFG_IEN_FPIOC (0x1UL << 8) /**< FPU Invalid Operation Interrupt Enable */ 303 #define _SYSCFG_IEN_FPIOC_SHIFT 8 /**< Shift value for SYSCFG_FPIOC */ 304 #define _SYSCFG_IEN_FPIOC_MASK 0x100UL /**< Bit mask for SYSCFG_FPIOC */ 305 #define _SYSCFG_IEN_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ 306 #define SYSCFG_IEN_FPIOC_DEFAULT (_SYSCFG_IEN_FPIOC_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_IEN */ 307 #define SYSCFG_IEN_FPDZC (0x1UL << 9) /**< FPU Divide by zero Interrupt Enable */ 308 #define _SYSCFG_IEN_FPDZC_SHIFT 9 /**< Shift value for SYSCFG_FPDZC */ 309 #define _SYSCFG_IEN_FPDZC_MASK 0x200UL /**< Bit mask for SYSCFG_FPDZC */ 310 #define _SYSCFG_IEN_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ 311 #define SYSCFG_IEN_FPDZC_DEFAULT (_SYSCFG_IEN_FPDZC_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSCFG_IEN */ 312 #define SYSCFG_IEN_FPUFC (0x1UL << 10) /**< FPU Underflow Interrupt Enable */ 313 #define _SYSCFG_IEN_FPUFC_SHIFT 10 /**< Shift value for SYSCFG_FPUFC */ 314 #define _SYSCFG_IEN_FPUFC_MASK 0x400UL /**< Bit mask for SYSCFG_FPUFC */ 315 #define _SYSCFG_IEN_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ 316 #define SYSCFG_IEN_FPUFC_DEFAULT (_SYSCFG_IEN_FPUFC_DEFAULT << 10) /**< Shifted mode DEFAULT for SYSCFG_IEN */ 317 #define SYSCFG_IEN_FPOFC (0x1UL << 11) /**< FPU Overflow Interrupt Enable */ 318 #define _SYSCFG_IEN_FPOFC_SHIFT 11 /**< Shift value for SYSCFG_FPOFC */ 319 #define _SYSCFG_IEN_FPOFC_MASK 0x800UL /**< Bit mask for SYSCFG_FPOFC */ 320 #define _SYSCFG_IEN_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ 321 #define SYSCFG_IEN_FPOFC_DEFAULT (_SYSCFG_IEN_FPOFC_DEFAULT << 11) /**< Shifted mode DEFAULT for SYSCFG_IEN */ 322 #define SYSCFG_IEN_FPIDC (0x1UL << 12) /**< FPU Input denormal Interrupt Enable */ 323 #define _SYSCFG_IEN_FPIDC_SHIFT 12 /**< Shift value for SYSCFG_FPIDC */ 324 #define _SYSCFG_IEN_FPIDC_MASK 0x1000UL /**< Bit mask for SYSCFG_FPIDC */ 325 #define _SYSCFG_IEN_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ 326 #define SYSCFG_IEN_FPIDC_DEFAULT (_SYSCFG_IEN_FPIDC_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_IEN */ 327 #define SYSCFG_IEN_FPIXC (0x1UL << 13) /**< FPU Inexact Interrupt Enable */ 328 #define _SYSCFG_IEN_FPIXC_SHIFT 13 /**< Shift value for SYSCFG_FPIXC */ 329 #define _SYSCFG_IEN_FPIXC_MASK 0x2000UL /**< Bit mask for SYSCFG_FPIXC */ 330 #define _SYSCFG_IEN_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ 331 #define SYSCFG_IEN_FPIXC_DEFAULT (_SYSCFG_IEN_FPIXC_DEFAULT << 13) /**< Shifted mode DEFAULT for SYSCFG_IEN */ 332 #define SYSCFG_IEN_RAMERR1B (0x1UL << 16) /**< RAM Error 1-bit Interrupt Enable */ 333 #define _SYSCFG_IEN_RAMERR1B_SHIFT 16 /**< Shift value for SYSCFG_RAMERR1B */ 334 #define _SYSCFG_IEN_RAMERR1B_MASK 0x10000UL /**< Bit mask for SYSCFG_RAMERR1B */ 335 #define _SYSCFG_IEN_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ 336 #define SYSCFG_IEN_RAMERR1B_DEFAULT (_SYSCFG_IEN_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_IEN */ 337 #define SYSCFG_IEN_RAMERR2B (0x1UL << 17) /**< RAM Error 2-bit Interrupt Enable */ 338 #define _SYSCFG_IEN_RAMERR2B_SHIFT 17 /**< Shift value for SYSCFG_RAMERR2B */ 339 #define _SYSCFG_IEN_RAMERR2B_MASK 0x20000UL /**< Bit mask for SYSCFG_RAMERR2B */ 340 #define _SYSCFG_IEN_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ 341 #define SYSCFG_IEN_RAMERR2B_DEFAULT (_SYSCFG_IEN_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for SYSCFG_IEN */ 342 #define SYSCFG_IEN_SEQRAMERR1B (0x1UL << 24) /**< SEQRAM Error 1-bit Interrupt Enable */ 343 #define _SYSCFG_IEN_SEQRAMERR1B_SHIFT 24 /**< Shift value for SYSCFG_SEQRAMERR1B */ 344 #define _SYSCFG_IEN_SEQRAMERR1B_MASK 0x1000000UL /**< Bit mask for SYSCFG_SEQRAMERR1B */ 345 #define _SYSCFG_IEN_SEQRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ 346 #define SYSCFG_IEN_SEQRAMERR1B_DEFAULT (_SYSCFG_IEN_SEQRAMERR1B_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_IEN */ 347 #define SYSCFG_IEN_SEQRAMERR2B (0x1UL << 25) /**< SEQRAM Error 2-bit Interrupt Enable */ 348 #define _SYSCFG_IEN_SEQRAMERR2B_SHIFT 25 /**< Shift value for SYSCFG_SEQRAMERR2B */ 349 #define _SYSCFG_IEN_SEQRAMERR2B_MASK 0x2000000UL /**< Bit mask for SYSCFG_SEQRAMERR2B */ 350 #define _SYSCFG_IEN_SEQRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ 351 #define SYSCFG_IEN_SEQRAMERR2B_DEFAULT (_SYSCFG_IEN_SEQRAMERR2B_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_IEN */ 352 #define SYSCFG_IEN_FRCRAMERR1B (0x1UL << 28) /**< FRCRAM Error 1-bit Interrupt Enable */ 353 #define _SYSCFG_IEN_FRCRAMERR1B_SHIFT 28 /**< Shift value for SYSCFG_FRCRAMERR1B */ 354 #define _SYSCFG_IEN_FRCRAMERR1B_MASK 0x10000000UL /**< Bit mask for SYSCFG_FRCRAMERR1B */ 355 #define _SYSCFG_IEN_FRCRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ 356 #define SYSCFG_IEN_FRCRAMERR1B_DEFAULT (_SYSCFG_IEN_FRCRAMERR1B_DEFAULT << 28) /**< Shifted mode DEFAULT for SYSCFG_IEN */ 357 #define SYSCFG_IEN_FRCRAMERR2B (0x1UL << 29) /**< FRCRAM Error 2-bit Interrupt Enable */ 358 #define _SYSCFG_IEN_FRCRAMERR2B_SHIFT 29 /**< Shift value for SYSCFG_FRCRAMERR2B */ 359 #define _SYSCFG_IEN_FRCRAMERR2B_MASK 0x20000000UL /**< Bit mask for SYSCFG_FRCRAMERR2B */ 360 #define _SYSCFG_IEN_FRCRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ 361 #define SYSCFG_IEN_FRCRAMERR2B_DEFAULT (_SYSCFG_IEN_FRCRAMERR2B_DEFAULT << 29) /**< Shifted mode DEFAULT for SYSCFG_IEN */ 362 363 /* Bit fields for SYSCFG CHIPREVHW */ 364 #define _SYSCFG_CHIPREVHW_RESETVALUE 0x00011011UL /**< Default value for SYSCFG_CHIPREVHW */ 365 #define _SYSCFG_CHIPREVHW_MASK 0xFF0FFFFFUL /**< Mask for SYSCFG_CHIPREVHW */ 366 #define _SYSCFG_CHIPREVHW_PARTNUMBER_SHIFT 0 /**< Shift value for SYSCFG_PARTNUMBER */ 367 #define _SYSCFG_CHIPREVHW_PARTNUMBER_MASK 0xFFFUL /**< Bit mask for SYSCFG_PARTNUMBER */ 368 #define _SYSCFG_CHIPREVHW_PARTNUMBER_DEFAULT 0x00000011UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */ 369 #define SYSCFG_CHIPREVHW_PARTNUMBER_DEFAULT (_SYSCFG_CHIPREVHW_PARTNUMBER_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */ 370 #define _SYSCFG_CHIPREVHW_MINOR_SHIFT 12 /**< Shift value for SYSCFG_MINOR */ 371 #define _SYSCFG_CHIPREVHW_MINOR_MASK 0xF000UL /**< Bit mask for SYSCFG_MINOR */ 372 #define _SYSCFG_CHIPREVHW_MINOR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */ 373 #define SYSCFG_CHIPREVHW_MINOR_DEFAULT (_SYSCFG_CHIPREVHW_MINOR_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */ 374 #define _SYSCFG_CHIPREVHW_MAJOR_SHIFT 16 /**< Shift value for SYSCFG_MAJOR */ 375 #define _SYSCFG_CHIPREVHW_MAJOR_MASK 0xF0000UL /**< Bit mask for SYSCFG_MAJOR */ 376 #define _SYSCFG_CHIPREVHW_MAJOR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */ 377 #define SYSCFG_CHIPREVHW_MAJOR_DEFAULT (_SYSCFG_CHIPREVHW_MAJOR_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */ 378 379 /* Bit fields for SYSCFG CHIPREV */ 380 #define _SYSCFG_CHIPREV_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_CHIPREV */ 381 #define _SYSCFG_CHIPREV_MASK 0x000FFFFFUL /**< Mask for SYSCFG_CHIPREV */ 382 #define _SYSCFG_CHIPREV_PARTNUMBER_SHIFT 0 /**< Shift value for SYSCFG_PARTNUMBER */ 383 #define _SYSCFG_CHIPREV_PARTNUMBER_MASK 0xFFFUL /**< Bit mask for SYSCFG_PARTNUMBER */ 384 #define _SYSCFG_CHIPREV_PARTNUMBER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */ 385 #define SYSCFG_CHIPREV_PARTNUMBER_DEFAULT (_SYSCFG_CHIPREV_PARTNUMBER_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */ 386 #define _SYSCFG_CHIPREV_MINOR_SHIFT 12 /**< Shift value for SYSCFG_MINOR */ 387 #define _SYSCFG_CHIPREV_MINOR_MASK 0xF000UL /**< Bit mask for SYSCFG_MINOR */ 388 #define _SYSCFG_CHIPREV_MINOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */ 389 #define SYSCFG_CHIPREV_MINOR_DEFAULT (_SYSCFG_CHIPREV_MINOR_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */ 390 #define _SYSCFG_CHIPREV_MAJOR_SHIFT 16 /**< Shift value for SYSCFG_MAJOR */ 391 #define _SYSCFG_CHIPREV_MAJOR_MASK 0xF0000UL /**< Bit mask for SYSCFG_MAJOR */ 392 #define _SYSCFG_CHIPREV_MAJOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */ 393 #define SYSCFG_CHIPREV_MAJOR_DEFAULT (_SYSCFG_CHIPREV_MAJOR_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */ 394 395 /* Bit fields for SYSCFG CFGSYSTIC */ 396 #define _SYSCFG_CFGSYSTIC_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_CFGSYSTIC */ 397 #define _SYSCFG_CFGSYSTIC_MASK 0x00000001UL /**< Mask for SYSCFG_CFGSYSTIC */ 398 #define SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN (0x1UL << 0) /**< SysTick External Clock Enable */ 399 #define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_SHIFT 0 /**< Shift value for SYSCFG_SYSTICEXTCLKEN */ 400 #define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_MASK 0x1UL /**< Bit mask for SYSCFG_SYSTICEXTCLKEN */ 401 #define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CFGSYSTIC */ 402 #define SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT (_SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CFGSYSTIC */ 403 404 /* Bit fields for SYSCFG CTRL */ 405 #define _SYSCFG_CTRL_RESETVALUE 0x00000023UL /**< Default value for SYSCFG_CTRL */ 406 #define _SYSCFG_CTRL_MASK 0x00000023UL /**< Mask for SYSCFG_CTRL */ 407 #define SYSCFG_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enabl */ 408 #define _SYSCFG_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for SYSCFG_ADDRFAULTEN */ 409 #define _SYSCFG_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for SYSCFG_ADDRFAULTEN */ 410 #define _SYSCFG_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CTRL */ 411 #define SYSCFG_CTRL_ADDRFAULTEN_DEFAULT (_SYSCFG_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CTRL */ 412 #define SYSCFG_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Disabled Clkbus Bus Fault Enable */ 413 #define _SYSCFG_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for SYSCFG_CLKDISFAULTEN */ 414 #define _SYSCFG_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for SYSCFG_CLKDISFAULTEN */ 415 #define _SYSCFG_CTRL_CLKDISFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CTRL */ 416 #define SYSCFG_CTRL_CLKDISFAULTEN_DEFAULT (_SYSCFG_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_CTRL */ 417 #define SYSCFG_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two bit ECC error bus fault response ena */ 418 #define _SYSCFG_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for SYSCFG_RAMECCERRFAULTEN */ 419 #define _SYSCFG_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for SYSCFG_RAMECCERRFAULTEN */ 420 #define _SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CTRL */ 421 #define SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT (_SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for SYSCFG_CTRL */ 422 423 /* Bit fields for SYSCFG DMEM0RETNCTRL */ 424 #define _SYSCFG_DMEM0RETNCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_DMEM0RETNCTRL */ 425 #define _SYSCFG_DMEM0RETNCTRL_MASK 0x00000007UL /**< Mask for SYSCFG_DMEM0RETNCTRL */ 426 #define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_SHIFT 0 /**< Shift value for SYSCFG_RAMRETNCTRL */ 427 #define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_MASK 0x7UL /**< Bit mask for SYSCFG_RAMRETNCTRL */ 428 #define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0RETNCTRL */ 429 #define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_DMEM0RETNCTRL */ 430 #define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK0 0x00000001UL /**< Mode BLK0 for SYSCFG_DMEM0RETNCTRL */ 431 #define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1 0x00000002UL /**< Mode BLK1 for SYSCFG_DMEM0RETNCTRL */ 432 #define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK0TO1 0x00000003UL /**< Mode BLK0TO1 for SYSCFG_DMEM0RETNCTRL */ 433 #define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK2 0x00000004UL /**< Mode BLK2 for SYSCFG_DMEM0RETNCTRL */ 434 #define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK0AND2 0x00000005UL /**< Mode BLK0AND2 for SYSCFG_DMEM0RETNCTRL */ 435 #define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1TO2 0x00000006UL /**< Mode BLK1TO2 for SYSCFG_DMEM0RETNCTRL */ 436 #define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK0TO2 0x00000007UL /**< Mode BLK0TO2 for SYSCFG_DMEM0RETNCTRL */ 437 #define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_DMEM0RETNCTRL*/ 438 #define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON << 0) /**< Shifted mode ALLON for SYSCFG_DMEM0RETNCTRL */ 439 #define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK0 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK0 << 0) /**< Shifted mode BLK0 for SYSCFG_DMEM0RETNCTRL */ 440 #define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1 << 0) /**< Shifted mode BLK1 for SYSCFG_DMEM0RETNCTRL */ 441 #define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK0TO1 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK0TO1 << 0) /**< Shifted mode BLK0TO1 for SYSCFG_DMEM0RETNCTRL*/ 442 #define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK2 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK2 << 0) /**< Shifted mode BLK2 for SYSCFG_DMEM0RETNCTRL */ 443 #define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK0AND2 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK0AND2 << 0) /**< Shifted mode BLK0AND2 for SYSCFG_DMEM0RETNCTRL*/ 444 #define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1TO2 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1TO2 << 0) /**< Shifted mode BLK1TO2 for SYSCFG_DMEM0RETNCTRL*/ 445 #define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK0TO2 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK0TO2 << 0) /**< Shifted mode BLK0TO2 for SYSCFG_DMEM0RETNCTRL*/ 446 447 /* Bit fields for SYSCFG DMEM0ECCADDR */ 448 #define _SYSCFG_DMEM0ECCADDR_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_DMEM0ECCADDR */ 449 #define _SYSCFG_DMEM0ECCADDR_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_DMEM0ECCADDR */ 450 #define _SYSCFG_DMEM0ECCADDR_DMEM0ECCADDR_SHIFT 0 /**< Shift value for SYSCFG_DMEM0ECCADDR */ 451 #define _SYSCFG_DMEM0ECCADDR_DMEM0ECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DMEM0ECCADDR */ 452 #define _SYSCFG_DMEM0ECCADDR_DMEM0ECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0ECCADDR */ 453 #define SYSCFG_DMEM0ECCADDR_DMEM0ECCADDR_DEFAULT (_SYSCFG_DMEM0ECCADDR_DMEM0ECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_DMEM0ECCADDR*/ 454 455 /* Bit fields for SYSCFG DMEM0ECCCTRL */ 456 #define _SYSCFG_DMEM0ECCCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_DMEM0ECCCTRL */ 457 #define _SYSCFG_DMEM0ECCCTRL_MASK 0x00000003UL /**< Mask for SYSCFG_DMEM0ECCCTRL */ 458 #define SYSCFG_DMEM0ECCCTRL_RAMECCEN (0x1UL << 0) /**< RAM ECC Enable */ 459 #define _SYSCFG_DMEM0ECCCTRL_RAMECCEN_SHIFT 0 /**< Shift value for SYSCFG_RAMECCEN */ 460 #define _SYSCFG_DMEM0ECCCTRL_RAMECCEN_MASK 0x1UL /**< Bit mask for SYSCFG_RAMECCEN */ 461 #define _SYSCFG_DMEM0ECCCTRL_RAMECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0ECCCTRL */ 462 #define SYSCFG_DMEM0ECCCTRL_RAMECCEN_DEFAULT (_SYSCFG_DMEM0ECCCTRL_RAMECCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_DMEM0ECCCTRL*/ 463 #define SYSCFG_DMEM0ECCCTRL_RAMECCEWEN (0x1UL << 1) /**< RAM ECC Error Writeback Enable */ 464 #define _SYSCFG_DMEM0ECCCTRL_RAMECCEWEN_SHIFT 1 /**< Shift value for SYSCFG_RAMECCEWEN */ 465 #define _SYSCFG_DMEM0ECCCTRL_RAMECCEWEN_MASK 0x2UL /**< Bit mask for SYSCFG_RAMECCEWEN */ 466 #define _SYSCFG_DMEM0ECCCTRL_RAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0ECCCTRL */ 467 #define SYSCFG_DMEM0ECCCTRL_RAMECCEWEN_DEFAULT (_SYSCFG_DMEM0ECCCTRL_RAMECCEWEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_DMEM0ECCCTRL*/ 468 469 /* Bit fields for SYSCFG RAMBIASCONF */ 470 #define _SYSCFG_RAMBIASCONF_RESETVALUE 0x00000002UL /**< Default value for SYSCFG_RAMBIASCONF */ 471 #define _SYSCFG_RAMBIASCONF_MASK 0x0000000FUL /**< Mask for SYSCFG_RAMBIASCONF */ 472 #define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_SHIFT 0 /**< Shift value for SYSCFG_RAMBIASCTRL */ 473 #define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_MASK 0xFUL /**< Bit mask for SYSCFG_RAMBIASCTRL */ 474 #define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_DEFAULT 0x00000002UL /**< Mode DEFAULT for SYSCFG_RAMBIASCONF */ 475 #define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_No 0x00000000UL /**< Mode No for SYSCFG_RAMBIASCONF */ 476 #define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB100 0x00000001UL /**< Mode VSB100 for SYSCFG_RAMBIASCONF */ 477 #define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB200 0x00000002UL /**< Mode VSB200 for SYSCFG_RAMBIASCONF */ 478 #define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB300 0x00000004UL /**< Mode VSB300 for SYSCFG_RAMBIASCONF */ 479 #define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB400 0x00000008UL /**< Mode VSB400 for SYSCFG_RAMBIASCONF */ 480 #define SYSCFG_RAMBIASCONF_RAMBIASCTRL_DEFAULT (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RAMBIASCONF */ 481 #define SYSCFG_RAMBIASCONF_RAMBIASCTRL_No (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_No << 0) /**< Shifted mode No for SYSCFG_RAMBIASCONF */ 482 #define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB100 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB100 << 0) /**< Shifted mode VSB100 for SYSCFG_RAMBIASCONF */ 483 #define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB200 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB200 << 0) /**< Shifted mode VSB200 for SYSCFG_RAMBIASCONF */ 484 #define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB300 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB300 << 0) /**< Shifted mode VSB300 for SYSCFG_RAMBIASCONF */ 485 #define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB400 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB400 << 0) /**< Shifted mode VSB400 for SYSCFG_RAMBIASCONF */ 486 487 /* Bit fields for SYSCFG RADIORAMRETNCTRL */ 488 #define _SYSCFG_RADIORAMRETNCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_RADIORAMRETNCTRL */ 489 #define _SYSCFG_RADIORAMRETNCTRL_MASK 0x00000103UL /**< Mask for SYSCFG_RADIORAMRETNCTRL */ 490 #define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMRETNCTRL */ 491 #define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_MASK 0x3UL /**< Bit mask for SYSCFG_SEQRAMRETNCTRL */ 492 #define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIORAMRETNCTRL */ 493 #define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_RADIORAMRETNCTRL */ 494 #define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 0x00000001UL /**< Mode BLK0 for SYSCFG_RADIORAMRETNCTRL */ 495 #define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 0x00000002UL /**< Mode BLK1 for SYSCFG_RADIORAMRETNCTRL */ 496 #define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF 0x00000003UL /**< Mode ALLOFF for SYSCFG_RADIORAMRETNCTRL */ 497 #define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RADIORAMRETNCTRL*/ 498 #define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON << 0) /**< Shifted mode ALLON for SYSCFG_RADIORAMRETNCTRL*/ 499 #define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 << 0) /**< Shifted mode BLK0 for SYSCFG_RADIORAMRETNCTRL*/ 500 #define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 << 0) /**< Shifted mode BLK1 for SYSCFG_RADIORAMRETNCTRL*/ 501 #define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF << 0) /**< Shifted mode ALLOFF for SYSCFG_RADIORAMRETNCTRL*/ 502 #define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL (0x1UL << 8) /**< FRCRAM Retention Control */ 503 #define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_SHIFT 8 /**< Shift value for SYSCFG_FRCRAMRETNCTRL */ 504 #define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_MASK 0x100UL /**< Bit mask for SYSCFG_FRCRAMRETNCTRL */ 505 #define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIORAMRETNCTRL */ 506 #define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_RADIORAMRETNCTRL */ 507 #define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF 0x00000001UL /**< Mode ALLOFF for SYSCFG_RADIORAMRETNCTRL */ 508 #define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_RADIORAMRETNCTRL*/ 509 #define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON << 8) /**< Shifted mode ALLON for SYSCFG_RADIORAMRETNCTRL*/ 510 #define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF << 8) /**< Shifted mode ALLOFF for SYSCFG_RADIORAMRETNCTRL*/ 511 512 /* Bit fields for SYSCFG RADIOECCCTRL */ 513 #define _SYSCFG_RADIOECCCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_RADIOECCCTRL */ 514 #define _SYSCFG_RADIOECCCTRL_MASK 0x00000303UL /**< Mask for SYSCFG_RADIOECCCTRL */ 515 #define SYSCFG_RADIOECCCTRL_SEQRAMECCEN (0x1UL << 0) /**< SEQRAM ECC Enable */ 516 #define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMECCEN */ 517 #define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_MASK 0x1UL /**< Bit mask for SYSCFG_SEQRAMECCEN */ 518 #define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ 519 #define SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT (_SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ 520 #define SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN (0x1UL << 1) /**< SEQRAM ECC Error Writeback Enable */ 521 #define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_SHIFT 1 /**< Shift value for SYSCFG_SEQRAMECCEWEN */ 522 #define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_MASK 0x2UL /**< Bit mask for SYSCFG_SEQRAMECCEWEN */ 523 #define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ 524 #define SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT (_SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ 525 #define SYSCFG_RADIOECCCTRL_FRCRAMECCEN (0x1UL << 8) /**< FRCRAM ECC Enable */ 526 #define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_SHIFT 8 /**< Shift value for SYSCFG_FRCRAMECCEN */ 527 #define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_MASK 0x100UL /**< Bit mask for SYSCFG_FRCRAMECCEN */ 528 #define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ 529 #define SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT (_SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ 530 #define SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN (0x1UL << 9) /**< FRCRAM ECC Error Writeback Enable */ 531 #define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_SHIFT 9 /**< Shift value for SYSCFG_FRCRAMECCEWEN */ 532 #define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_MASK 0x200UL /**< Bit mask for SYSCFG_FRCRAMECCEWEN */ 533 #define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ 534 #define SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT (_SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ 535 536 /* Bit fields for SYSCFG SEQRAMECCADDR */ 537 #define _SYSCFG_SEQRAMECCADDR_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_SEQRAMECCADDR */ 538 #define _SYSCFG_SEQRAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_SEQRAMECCADDR */ 539 #define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMECCADDR */ 540 #define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_SEQRAMECCADDR */ 541 #define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_SEQRAMECCADDR */ 542 #define SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT (_SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_SEQRAMECCADDR*/ 543 544 /* Bit fields for SYSCFG FRCRAMECCADDR */ 545 #define _SYSCFG_FRCRAMECCADDR_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_FRCRAMECCADDR */ 546 #define _SYSCFG_FRCRAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_FRCRAMECCADDR */ 547 #define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_SHIFT 0 /**< Shift value for SYSCFG_FRCRAMECCADDR */ 548 #define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_FRCRAMECCADDR */ 549 #define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_FRCRAMECCADDR */ 550 #define SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT (_SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_FRCRAMECCADDR*/ 551 552 /* Bit fields for SYSCFG ICACHERAMRETNCTRL */ 553 #define _SYSCFG_ICACHERAMRETNCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ICACHERAMRETNCTRL */ 554 #define _SYSCFG_ICACHERAMRETNCTRL_MASK 0x00000001UL /**< Mask for SYSCFG_ICACHERAMRETNCTRL */ 555 #define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL (0x1UL << 0) /**< ICACHERAM Retention control */ 556 #define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_SHIFT 0 /**< Shift value for SYSCFG_RAMRETNCTRL */ 557 #define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_MASK 0x1UL /**< Bit mask for SYSCFG_RAMRETNCTRL */ 558 #define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ICACHERAMRETNCTRL */ 559 #define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_ICACHERAMRETNCTRL */ 560 #define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLOFF 0x00000001UL /**< Mode ALLOFF for SYSCFG_ICACHERAMRETNCTRL */ 561 #define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_DEFAULT (_SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ICACHERAMRETNCTRL*/ 562 #define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLON (_SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLON << 0) /**< Shifted mode ALLON for SYSCFG_ICACHERAMRETNCTRL*/ 563 #define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLOFF (_SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLOFF << 0) /**< Shifted mode ALLOFF for SYSCFG_ICACHERAMRETNCTRL*/ 564 565 /* Bit fields for SYSCFG ROOTDATA0 */ 566 #define _SYSCFG_ROOTDATA0_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTDATA0 */ 567 #define _SYSCFG_ROOTDATA0_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTDATA0 */ 568 #define _SYSCFG_ROOTDATA0_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ 569 #define _SYSCFG_ROOTDATA0_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ 570 #define _SYSCFG_ROOTDATA0_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTDATA0 */ 571 #define SYSCFG_ROOTDATA0_DATA_DEFAULT (_SYSCFG_ROOTDATA0_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTDATA0 */ 572 573 /* Bit fields for SYSCFG ROOTDATA1 */ 574 #define _SYSCFG_ROOTDATA1_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTDATA1 */ 575 #define _SYSCFG_ROOTDATA1_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTDATA1 */ 576 #define _SYSCFG_ROOTDATA1_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ 577 #define _SYSCFG_ROOTDATA1_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ 578 #define _SYSCFG_ROOTDATA1_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTDATA1 */ 579 #define SYSCFG_ROOTDATA1_DATA_DEFAULT (_SYSCFG_ROOTDATA1_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTDATA1 */ 580 581 /* Bit fields for SYSCFG ROOTLOCKSTATUS */ 582 #define _SYSCFG_ROOTLOCKSTATUS_RESETVALUE 0x011F0107UL /**< Default value for SYSCFG_ROOTLOCKSTATUS */ 583 #define _SYSCFG_ROOTLOCKSTATUS_MASK 0x811F0117UL /**< Mask for SYSCFG_ROOTLOCKSTATUS */ 584 #define SYSCFG_ROOTLOCKSTATUS_BUSLOCK (0x1UL << 0) /**< Bus Lock */ 585 #define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_SHIFT 0 /**< Shift value for SYSCFG_BUSLOCK */ 586 #define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_MASK 0x1UL /**< Bit mask for SYSCFG_BUSLOCK */ 587 #define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ 588 #define SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ 589 #define SYSCFG_ROOTLOCKSTATUS_REGLOCK (0x1UL << 1) /**< Register Lock */ 590 #define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_SHIFT 1 /**< Shift value for SYSCFG_REGLOCK */ 591 #define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_MASK 0x2UL /**< Bit mask for SYSCFG_REGLOCK */ 592 #define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ 593 #define SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ 594 #define SYSCFG_ROOTLOCKSTATUS_MFRLOCK (0x1UL << 2) /**< Manufacture Lock */ 595 #define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_SHIFT 2 /**< Shift value for SYSCFG_MFRLOCK */ 596 #define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_MASK 0x4UL /**< Bit mask for SYSCFG_MFRLOCK */ 597 #define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ 598 #define SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ 599 #define SYSCFG_ROOTLOCKSTATUS_ROOTMODELOCK (0x1UL << 4) /**< Root Mode Lock */ 600 #define _SYSCFG_ROOTLOCKSTATUS_ROOTMODELOCK_SHIFT 4 /**< Shift value for SYSCFG_ROOTMODELOCK */ 601 #define _SYSCFG_ROOTLOCKSTATUS_ROOTMODELOCK_MASK 0x10UL /**< Bit mask for SYSCFG_ROOTMODELOCK */ 602 #define _SYSCFG_ROOTLOCKSTATUS_ROOTMODELOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ 603 #define SYSCFG_ROOTLOCKSTATUS_ROOTMODELOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_ROOTMODELOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ 604 #define SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK (0x1UL << 8) /**< Root Debug Lock */ 605 #define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_SHIFT 8 /**< Shift value for SYSCFG_ROOTDBGLOCK */ 606 #define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_MASK 0x100UL /**< Bit mask for SYSCFG_ROOTDBGLOCK */ 607 #define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ 608 #define SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ 609 #define SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK (0x1UL << 16) /**< User Invasive Debug Lock */ 610 #define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_SHIFT 16 /**< Shift value for SYSCFG_USERDBGLOCK */ 611 #define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_MASK 0x10000UL /**< Bit mask for SYSCFG_USERDBGLOCK */ 612 #define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ 613 #define SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ 614 #define SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK (0x1UL << 17) /**< User Non-invasive Debug Lock */ 615 #define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_SHIFT 17 /**< Shift value for SYSCFG_USERNIDLOCK */ 616 #define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_MASK 0x20000UL /**< Bit mask for SYSCFG_USERNIDLOCK */ 617 #define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ 618 #define SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ 619 #define SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK (0x1UL << 18) /**< User Secure Invasive Debug Lock */ 620 #define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_SHIFT 18 /**< Shift value for SYSCFG_USERSPIDLOCK */ 621 #define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_MASK 0x40000UL /**< Bit mask for SYSCFG_USERSPIDLOCK */ 622 #define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ 623 #define SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ 624 #define SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK (0x1UL << 19) /**< User Secure Non-invasive Debug Lock */ 625 #define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_SHIFT 19 /**< Shift value for SYSCFG_USERSPNIDLOCK */ 626 #define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_MASK 0x80000UL /**< Bit mask for SYSCFG_USERSPNIDLOCK */ 627 #define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ 628 #define SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ 629 #define SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK (0x1UL << 20) /**< User Debug Access Port Lock */ 630 #define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_SHIFT 20 /**< Shift value for SYSCFG_USERDBGAPLOCK */ 631 #define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_MASK 0x100000UL /**< Bit mask for SYSCFG_USERDBGAPLOCK */ 632 #define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ 633 #define SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ 634 #define SYSCFG_ROOTLOCKSTATUS_RADIODBGLOCK (0x1UL << 24) /**< Radio Debug Lock */ 635 #define _SYSCFG_ROOTLOCKSTATUS_RADIODBGLOCK_SHIFT 24 /**< Shift value for SYSCFG_RADIODBGLOCK */ 636 #define _SYSCFG_ROOTLOCKSTATUS_RADIODBGLOCK_MASK 0x1000000UL /**< Bit mask for SYSCFG_RADIODBGLOCK */ 637 #define _SYSCFG_ROOTLOCKSTATUS_RADIODBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ 638 #define SYSCFG_ROOTLOCKSTATUS_RADIODBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_RADIODBGLOCK_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ 639 #define SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED (0x1UL << 31) /**< E-Fuse Unlocked */ 640 #define _SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_SHIFT 31 /**< Shift value for SYSCFG_EFUSEUNLOCKED */ 641 #define _SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_MASK 0x80000000UL /**< Bit mask for SYSCFG_EFUSEUNLOCKED */ 642 #define _SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ 643 #define SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_DEFAULT << 31) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ 644 645 /* Bit fields for SYSCFG ROOTSESWVERSION */ 646 #define _SYSCFG_ROOTSESWVERSION_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTSESWVERSION */ 647 #define _SYSCFG_ROOTSESWVERSION_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTSESWVERSION */ 648 #define _SYSCFG_ROOTSESWVERSION_SWVERSION_SHIFT 0 /**< Shift value for SYSCFG_SWVERSION */ 649 #define _SYSCFG_ROOTSESWVERSION_SWVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_SWVERSION */ 650 #define _SYSCFG_ROOTSESWVERSION_SWVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTSESWVERSION */ 651 #define SYSCFG_ROOTSESWVERSION_SWVERSION_DEFAULT (_SYSCFG_ROOTSESWVERSION_SWVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTSESWVERSION*/ 652 653 /** @} End of group EFR32BG27_SYSCFG_BitFields */ 654 /** @} End of group EFR32BG27_SYSCFG */ 655 /**************************************************************************//** 656 * @defgroup EFR32BG27_SYSCFG_CFGNS SYSCFG_CFGNS 657 * @{ 658 * @brief EFR32BG27 SYSCFG_CFGNS Register Declaration. 659 *****************************************************************************/ 660 661 /** SYSCFG_CFGNS Register Declaration. */ 662 typedef struct syscfg_cfgns_typedef{ 663 uint32_t RESERVED0[7U]; /**< Reserved for future use */ 664 __IOM uint32_t CFGNSTCALIB; /**< Configure Non-secure Sys-Tick Cal. */ 665 uint32_t RESERVED1[376U]; /**< Reserved for future use */ 666 __IOM uint32_t ROOTNSDATA0; /**< Data Register 0 */ 667 __IOM uint32_t ROOTNSDATA1; /**< Data Register 1 */ 668 uint32_t RESERVED2[638U]; /**< Reserved for future use */ 669 uint32_t RESERVED3[7U]; /**< Reserved for future use */ 670 __IOM uint32_t CFGNSTCALIB_SET; /**< Configure Non-secure Sys-Tick Cal. */ 671 uint32_t RESERVED4[376U]; /**< Reserved for future use */ 672 __IOM uint32_t ROOTNSDATA0_SET; /**< Data Register 0 */ 673 __IOM uint32_t ROOTNSDATA1_SET; /**< Data Register 1 */ 674 uint32_t RESERVED5[638U]; /**< Reserved for future use */ 675 uint32_t RESERVED6[7U]; /**< Reserved for future use */ 676 __IOM uint32_t CFGNSTCALIB_CLR; /**< Configure Non-secure Sys-Tick Cal. */ 677 uint32_t RESERVED7[376U]; /**< Reserved for future use */ 678 __IOM uint32_t ROOTNSDATA0_CLR; /**< Data Register 0 */ 679 __IOM uint32_t ROOTNSDATA1_CLR; /**< Data Register 1 */ 680 uint32_t RESERVED8[638U]; /**< Reserved for future use */ 681 uint32_t RESERVED9[7U]; /**< Reserved for future use */ 682 __IOM uint32_t CFGNSTCALIB_TGL; /**< Configure Non-secure Sys-Tick Cal. */ 683 uint32_t RESERVED10[376U]; /**< Reserved for future use */ 684 __IOM uint32_t ROOTNSDATA0_TGL; /**< Data Register 0 */ 685 __IOM uint32_t ROOTNSDATA1_TGL; /**< Data Register 1 */ 686 } SYSCFG_CFGNS_TypeDef; 687 /** @} End of group EFR32BG27_SYSCFG_CFGNS */ 688 689 /**************************************************************************//** 690 * @addtogroup EFR32BG27_SYSCFG_CFGNS 691 * @{ 692 * @defgroup EFR32BG27_SYSCFG_CFGNS_BitFields SYSCFG_CFGNS Bit Fields 693 * @{ 694 *****************************************************************************/ 695 696 /* Bit fields for SYSCFG CFGNSTCALIB */ 697 #define _SYSCFG_CFGNSTCALIB_RESETVALUE 0x01004A37UL /**< Default value for SYSCFG_CFGNSTCALIB */ 698 #define _SYSCFG_CFGNSTCALIB_MASK 0x03FFFFFFUL /**< Mask for SYSCFG_CFGNSTCALIB */ 699 #define _SYSCFG_CFGNSTCALIB_TENMS_SHIFT 0 /**< Shift value for SYSCFG_TENMS */ 700 #define _SYSCFG_CFGNSTCALIB_TENMS_MASK 0xFFFFFFUL /**< Bit mask for SYSCFG_TENMS */ 701 #define _SYSCFG_CFGNSTCALIB_TENMS_DEFAULT 0x00004A37UL /**< Mode DEFAULT for SYSCFG_CFGNSTCALIB */ 702 #define SYSCFG_CFGNSTCALIB_TENMS_DEFAULT (_SYSCFG_CFGNSTCALIB_TENMS_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CFGNSTCALIB */ 703 #define SYSCFG_CFGNSTCALIB_SKEW (0x1UL << 24) /**< Skew */ 704 #define _SYSCFG_CFGNSTCALIB_SKEW_SHIFT 24 /**< Shift value for SYSCFG_SKEW */ 705 #define _SYSCFG_CFGNSTCALIB_SKEW_MASK 0x1000000UL /**< Bit mask for SYSCFG_SKEW */ 706 #define _SYSCFG_CFGNSTCALIB_SKEW_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CFGNSTCALIB */ 707 #define SYSCFG_CFGNSTCALIB_SKEW_DEFAULT (_SYSCFG_CFGNSTCALIB_SKEW_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_CFGNSTCALIB */ 708 #define SYSCFG_CFGNSTCALIB_NOREF (0x1UL << 25) /**< No Reference */ 709 #define _SYSCFG_CFGNSTCALIB_NOREF_SHIFT 25 /**< Shift value for SYSCFG_NOREF */ 710 #define _SYSCFG_CFGNSTCALIB_NOREF_MASK 0x2000000UL /**< Bit mask for SYSCFG_NOREF */ 711 #define _SYSCFG_CFGNSTCALIB_NOREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CFGNSTCALIB */ 712 #define _SYSCFG_CFGNSTCALIB_NOREF_REF 0x00000000UL /**< Mode REF for SYSCFG_CFGNSTCALIB */ 713 #define _SYSCFG_CFGNSTCALIB_NOREF_NOREF 0x00000001UL /**< Mode NOREF for SYSCFG_CFGNSTCALIB */ 714 #define SYSCFG_CFGNSTCALIB_NOREF_DEFAULT (_SYSCFG_CFGNSTCALIB_NOREF_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_CFGNSTCALIB */ 715 #define SYSCFG_CFGNSTCALIB_NOREF_REF (_SYSCFG_CFGNSTCALIB_NOREF_REF << 25) /**< Shifted mode REF for SYSCFG_CFGNSTCALIB */ 716 #define SYSCFG_CFGNSTCALIB_NOREF_NOREF (_SYSCFG_CFGNSTCALIB_NOREF_NOREF << 25) /**< Shifted mode NOREF for SYSCFG_CFGNSTCALIB */ 717 718 /* Bit fields for SYSCFG ROOTNSDATA0 */ 719 #define _SYSCFG_ROOTNSDATA0_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTNSDATA0 */ 720 #define _SYSCFG_ROOTNSDATA0_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTNSDATA0 */ 721 #define _SYSCFG_ROOTNSDATA0_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ 722 #define _SYSCFG_ROOTNSDATA0_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ 723 #define _SYSCFG_ROOTNSDATA0_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTNSDATA0 */ 724 #define SYSCFG_ROOTNSDATA0_DATA_DEFAULT (_SYSCFG_ROOTNSDATA0_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTNSDATA0 */ 725 726 /* Bit fields for SYSCFG ROOTNSDATA1 */ 727 #define _SYSCFG_ROOTNSDATA1_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTNSDATA1 */ 728 #define _SYSCFG_ROOTNSDATA1_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTNSDATA1 */ 729 #define _SYSCFG_ROOTNSDATA1_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ 730 #define _SYSCFG_ROOTNSDATA1_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ 731 #define _SYSCFG_ROOTNSDATA1_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTNSDATA1 */ 732 #define SYSCFG_ROOTNSDATA1_DATA_DEFAULT (_SYSCFG_ROOTNSDATA1_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTNSDATA1 */ 733 734 /** @} End of group EFR32BG27_SYSCFG_CFGNS_BitFields */ 735 /** @} End of group EFR32BG27_SYSCFG_CFGNS */ 736 /** @} End of group Parts */ 737 738 #endif // EFR32BG27_SYSCFG_H 739
