1 /**************************************************************************//** 2 * @file 3 * @brief EFR32BG27 SEPUF register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2024 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32BG27_SEPUF_H 31 #define EFR32BG27_SEPUF_H 32 33 /**************************************************************************//** 34 * @addtogroup Parts 35 * @{ 36 ******************************************************************************/ 37 /**************************************************************************//** 38 * @defgroup EFR32BG27_SEPUF_APBCFG SEPUF_APBCFG 39 * @{ 40 * @brief EFR32BG27 SEPUF_APBCFG Register Declaration. 41 *****************************************************************************/ 42 43 /** SEPUF_APBCFG Register Declaration. */ 44 typedef struct sepuf_apbcfg_typedef{ 45 __IOM uint32_t QK_CR; /**< QK_CR */ 46 uint32_t RESERVED0[7U]; /**< Reserved for future use */ 47 __IM uint32_t QK_SR; /**< QK_SR */ 48 uint32_t RESERVED1[1U]; /**< Reserved for future use */ 49 __IM uint32_t QK_AR; /**< QK_AR */ 50 uint32_t RESERVED2[6U]; /**< Reserved for future use */ 51 __IOM uint32_t QK_CI; /**< QK_CI */ 52 __IM uint32_t QK_CO; /**< QK_CO */ 53 uint32_t RESERVED3[36U]; /**< Reserved for future use */ 54 __IOM uint32_t QK_IF_SR; /**< QK_IF_SR */ 55 uint32_t RESERVED4[7U]; /**< Reserved for future use */ 56 __IM uint32_t QK_VER; /**< QK_VER */ 57 } SEPUF_APBCFG_TypeDef; 58 /** @} End of group EFR32BG27_SEPUF_APBCFG */ 59 60 /**************************************************************************//** 61 * @addtogroup EFR32BG27_SEPUF_APBCFG 62 * @{ 63 * @defgroup EFR32BG27_SEPUF_APBCFG_BitFields SEPUF_APBCFG Bit Fields 64 * @{ 65 *****************************************************************************/ 66 67 /* Bit fields for SEPUF QK_CR */ 68 #define _SEPUF_QK_CR_RESETVALUE 0x00000000UL /**< Default value for SEPUF_QK_CR */ 69 #define _SEPUF_QK_CR_MASK 0x00000007UL /**< Mask for SEPUF_QK_CR */ 70 #define SEPUF_QK_CR_QK_ZEROIZE (0x1UL << 0) /**< QK_ZEROIZE */ 71 #define _SEPUF_QK_CR_QK_ZEROIZE_SHIFT 0 /**< Shift value for SEPUF_QK_ZEROIZE */ 72 #define _SEPUF_QK_CR_QK_ZEROIZE_MASK 0x1UL /**< Bit mask for SEPUF_QK_ZEROIZE */ 73 #define _SEPUF_QK_CR_QK_ZEROIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEPUF_QK_CR */ 74 #define SEPUF_QK_CR_QK_ZEROIZE_DEFAULT (_SEPUF_QK_CR_QK_ZEROIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for SEPUF_QK_CR */ 75 #define SEPUF_QK_CR_QK_ENROLL (0x1UL << 1) /**< QK_ENROLL */ 76 #define _SEPUF_QK_CR_QK_ENROLL_SHIFT 1 /**< Shift value for SEPUF_QK_ENROLL */ 77 #define _SEPUF_QK_CR_QK_ENROLL_MASK 0x2UL /**< Bit mask for SEPUF_QK_ENROLL */ 78 #define _SEPUF_QK_CR_QK_ENROLL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEPUF_QK_CR */ 79 #define SEPUF_QK_CR_QK_ENROLL_DEFAULT (_SEPUF_QK_CR_QK_ENROLL_DEFAULT << 1) /**< Shifted mode DEFAULT for SEPUF_QK_CR */ 80 #define SEPUF_QK_CR_QK_START (0x1UL << 2) /**< QK_START */ 81 #define _SEPUF_QK_CR_QK_START_SHIFT 2 /**< Shift value for SEPUF_QK_START */ 82 #define _SEPUF_QK_CR_QK_START_MASK 0x4UL /**< Bit mask for SEPUF_QK_START */ 83 #define _SEPUF_QK_CR_QK_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEPUF_QK_CR */ 84 #define SEPUF_QK_CR_QK_START_DEFAULT (_SEPUF_QK_CR_QK_START_DEFAULT << 2) /**< Shifted mode DEFAULT for SEPUF_QK_CR */ 85 86 /* Bit fields for SEPUF QK_SR */ 87 #define _SEPUF_QK_SR_RESETVALUE 0x00000001UL /**< Default value for SEPUF_QK_SR */ 88 #define _SEPUF_QK_SR_MASK 0x000000E7UL /**< Mask for SEPUF_QK_SR */ 89 #define SEPUF_QK_SR_QK_BUSY (0x1UL << 0) /**< QK_BUSY */ 90 #define _SEPUF_QK_SR_QK_BUSY_SHIFT 0 /**< Shift value for SEPUF_QK_BUSY */ 91 #define _SEPUF_QK_SR_QK_BUSY_MASK 0x1UL /**< Bit mask for SEPUF_QK_BUSY */ 92 #define _SEPUF_QK_SR_QK_BUSY_DEFAULT 0x00000001UL /**< Mode DEFAULT for SEPUF_QK_SR */ 93 #define SEPUF_QK_SR_QK_BUSY_DEFAULT (_SEPUF_QK_SR_QK_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for SEPUF_QK_SR */ 94 #define SEPUF_QK_SR_QK_OK (0x1UL << 1) /**< QK_OK */ 95 #define _SEPUF_QK_SR_QK_OK_SHIFT 1 /**< Shift value for SEPUF_QK_OK */ 96 #define _SEPUF_QK_SR_QK_OK_MASK 0x2UL /**< Bit mask for SEPUF_QK_OK */ 97 #define _SEPUF_QK_SR_QK_OK_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEPUF_QK_SR */ 98 #define SEPUF_QK_SR_QK_OK_DEFAULT (_SEPUF_QK_SR_QK_OK_DEFAULT << 1) /**< Shifted mode DEFAULT for SEPUF_QK_SR */ 99 #define SEPUF_QK_SR_QK_ERROR (0x1UL << 2) /**< QK_ERROR */ 100 #define _SEPUF_QK_SR_QK_ERROR_SHIFT 2 /**< Shift value for SEPUF_QK_ERROR */ 101 #define _SEPUF_QK_SR_QK_ERROR_MASK 0x4UL /**< Bit mask for SEPUF_QK_ERROR */ 102 #define _SEPUF_QK_SR_QK_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEPUF_QK_SR */ 103 #define SEPUF_QK_SR_QK_ERROR_DEFAULT (_SEPUF_QK_SR_QK_ERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for SEPUF_QK_SR */ 104 #define SEPUF_QK_SR_QK_KO_OR (0x1UL << 5) /**< QK_KO_OR */ 105 #define _SEPUF_QK_SR_QK_KO_OR_SHIFT 5 /**< Shift value for SEPUF_QK_KO_OR */ 106 #define _SEPUF_QK_SR_QK_KO_OR_MASK 0x20UL /**< Bit mask for SEPUF_QK_KO_OR */ 107 #define _SEPUF_QK_SR_QK_KO_OR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEPUF_QK_SR */ 108 #define SEPUF_QK_SR_QK_KO_OR_DEFAULT (_SEPUF_QK_SR_QK_KO_OR_DEFAULT << 5) /**< Shifted mode DEFAULT for SEPUF_QK_SR */ 109 #define SEPUF_QK_SR_QK_CI_IR (0x1UL << 6) /**< QK_CI_IR */ 110 #define _SEPUF_QK_SR_QK_CI_IR_SHIFT 6 /**< Shift value for SEPUF_QK_CI_IR */ 111 #define _SEPUF_QK_SR_QK_CI_IR_MASK 0x40UL /**< Bit mask for SEPUF_QK_CI_IR */ 112 #define _SEPUF_QK_SR_QK_CI_IR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEPUF_QK_SR */ 113 #define SEPUF_QK_SR_QK_CI_IR_DEFAULT (_SEPUF_QK_SR_QK_CI_IR_DEFAULT << 6) /**< Shifted mode DEFAULT for SEPUF_QK_SR */ 114 #define SEPUF_QK_SR_QK_CO_OR (0x1UL << 7) /**< QK_CO_OR */ 115 #define _SEPUF_QK_SR_QK_CO_OR_SHIFT 7 /**< Shift value for SEPUF_QK_CO_OR */ 116 #define _SEPUF_QK_SR_QK_CO_OR_MASK 0x80UL /**< Bit mask for SEPUF_QK_CO_OR */ 117 #define _SEPUF_QK_SR_QK_CO_OR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEPUF_QK_SR */ 118 #define SEPUF_QK_SR_QK_CO_OR_DEFAULT (_SEPUF_QK_SR_QK_CO_OR_DEFAULT << 7) /**< Shifted mode DEFAULT for SEPUF_QK_SR */ 119 120 /* Bit fields for SEPUF QK_AR */ 121 #define _SEPUF_QK_AR_RESETVALUE 0x00000000UL /**< Default value for SEPUF_QK_AR */ 122 #define _SEPUF_QK_AR_MASK 0x00000003UL /**< Mask for SEPUF_QK_AR */ 123 #define SEPUF_QK_AR_QK_ALLOW_ENROLL (0x1UL << 0) /**< QK_ALLOW_ENROLL */ 124 #define _SEPUF_QK_AR_QK_ALLOW_ENROLL_SHIFT 0 /**< Shift value for SEPUF_QK_ALLOW_ENROLL */ 125 #define _SEPUF_QK_AR_QK_ALLOW_ENROLL_MASK 0x1UL /**< Bit mask for SEPUF_QK_ALLOW_ENROLL */ 126 #define _SEPUF_QK_AR_QK_ALLOW_ENROLL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEPUF_QK_AR */ 127 #define SEPUF_QK_AR_QK_ALLOW_ENROLL_DEFAULT (_SEPUF_QK_AR_QK_ALLOW_ENROLL_DEFAULT << 0) /**< Shifted mode DEFAULT for SEPUF_QK_AR */ 128 #define SEPUF_QK_AR_QK_ALLOW_START (0x1UL << 1) /**< QK_ALLOW_START */ 129 #define _SEPUF_QK_AR_QK_ALLOW_START_SHIFT 1 /**< Shift value for SEPUF_QK_ALLOW_START */ 130 #define _SEPUF_QK_AR_QK_ALLOW_START_MASK 0x2UL /**< Bit mask for SEPUF_QK_ALLOW_START */ 131 #define _SEPUF_QK_AR_QK_ALLOW_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEPUF_QK_AR */ 132 #define SEPUF_QK_AR_QK_ALLOW_START_DEFAULT (_SEPUF_QK_AR_QK_ALLOW_START_DEFAULT << 1) /**< Shifted mode DEFAULT for SEPUF_QK_AR */ 133 134 /* Bit fields for SEPUF QK_CI */ 135 #define _SEPUF_QK_CI_RESETVALUE 0x00000000UL /**< Default value for SEPUF_QK_CI */ 136 #define _SEPUF_QK_CI_MASK 0x00000001UL /**< Mask for SEPUF_QK_CI */ 137 #define SEPUF_QK_CI_QK_CI (0x1UL << 0) /**< QK_CI */ 138 #define _SEPUF_QK_CI_QK_CI_SHIFT 0 /**< Shift value for SEPUF_QK_CI */ 139 #define _SEPUF_QK_CI_QK_CI_MASK 0x1UL /**< Bit mask for SEPUF_QK_CI */ 140 #define _SEPUF_QK_CI_QK_CI_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEPUF_QK_CI */ 141 #define SEPUF_QK_CI_QK_CI_DEFAULT (_SEPUF_QK_CI_QK_CI_DEFAULT << 0) /**< Shifted mode DEFAULT for SEPUF_QK_CI */ 142 143 /* Bit fields for SEPUF QK_CO */ 144 #define _SEPUF_QK_CO_RESETVALUE 0x00000000UL /**< Default value for SEPUF_QK_CO */ 145 #define _SEPUF_QK_CO_MASK 0x00000001UL /**< Mask for SEPUF_QK_CO */ 146 #define SEPUF_QK_CO_QK_CO (0x1UL << 0) /**< QK_CO */ 147 #define _SEPUF_QK_CO_QK_CO_SHIFT 0 /**< Shift value for SEPUF_QK_CO */ 148 #define _SEPUF_QK_CO_QK_CO_MASK 0x1UL /**< Bit mask for SEPUF_QK_CO */ 149 #define _SEPUF_QK_CO_QK_CO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEPUF_QK_CO */ 150 #define SEPUF_QK_CO_QK_CO_DEFAULT (_SEPUF_QK_CO_QK_CO_DEFAULT << 0) /**< Shifted mode DEFAULT for SEPUF_QK_CO */ 151 152 /* Bit fields for SEPUF QK_IF_SR */ 153 #define _SEPUF_QK_IF_SR_RESETVALUE 0x00000000UL /**< Default value for SEPUF_QK_IF_SR */ 154 #define _SEPUF_QK_IF_SR_MASK 0x00000081UL /**< Mask for SEPUF_QK_IF_SR */ 155 #define SEPUF_QK_IF_SR_IF_ERROR (0x1UL << 0) /**< IF_ERROR */ 156 #define _SEPUF_QK_IF_SR_IF_ERROR_SHIFT 0 /**< Shift value for SEPUF_IF_ERROR */ 157 #define _SEPUF_QK_IF_SR_IF_ERROR_MASK 0x1UL /**< Bit mask for SEPUF_IF_ERROR */ 158 #define _SEPUF_QK_IF_SR_IF_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEPUF_QK_IF_SR */ 159 #define SEPUF_QK_IF_SR_IF_ERROR_DEFAULT (_SEPUF_QK_IF_SR_IF_ERROR_DEFAULT << 0) /**< Shifted mode DEFAULT for SEPUF_QK_IF_SR */ 160 #define SEPUF_QK_IF_SR_MEM_IF_ERROR (0x1UL << 7) /**< MEM_IF_ERROR */ 161 #define _SEPUF_QK_IF_SR_MEM_IF_ERROR_SHIFT 7 /**< Shift value for SEPUF_MEM_IF_ERROR */ 162 #define _SEPUF_QK_IF_SR_MEM_IF_ERROR_MASK 0x80UL /**< Bit mask for SEPUF_MEM_IF_ERROR */ 163 #define _SEPUF_QK_IF_SR_MEM_IF_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEPUF_QK_IF_SR */ 164 #define SEPUF_QK_IF_SR_MEM_IF_ERROR_DEFAULT (_SEPUF_QK_IF_SR_MEM_IF_ERROR_DEFAULT << 7) /**< Shifted mode DEFAULT for SEPUF_QK_IF_SR */ 165 166 /* Bit fields for SEPUF QK_VER */ 167 #define _SEPUF_QK_VER_RESETVALUE 0x18910201UL /**< Default value for SEPUF_QK_VER */ 168 #define _SEPUF_QK_VER_MASK 0xFFFFFFFFUL /**< Mask for SEPUF_QK_VER */ 169 #define _SEPUF_QK_VER_QK_VERSION_SHIFT 0 /**< Shift value for SEPUF_QK_VERSION */ 170 #define _SEPUF_QK_VER_QK_VERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SEPUF_QK_VERSION */ 171 #define _SEPUF_QK_VER_QK_VERSION_DEFAULT 0x18910201UL /**< Mode DEFAULT for SEPUF_QK_VER */ 172 #define SEPUF_QK_VER_QK_VERSION_DEFAULT (_SEPUF_QK_VER_QK_VERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SEPUF_QK_VER */ 173 174 /** @} End of group EFR32BG27_SEPUF_APBCFG_BitFields */ 175 /** @} End of group EFR32BG27_SEPUF_APBCFG */ 176 /** @} End of group Parts */ 177 178 #endif // EFR32BG27_SEPUF_H 179
