1 /**************************************************************************//** 2 * @file 3 * @brief EFR32BG27 PDM register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2024 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32BG27_PDM_H 31 #define EFR32BG27_PDM_H 32 #define PDM_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32BG27_PDM PDM 40 * @{ 41 * @brief EFR32BG27 PDM Register Declaration. 42 *****************************************************************************/ 43 44 /** PDM Register Declaration. */ 45 typedef struct pdm_typedef{ 46 __IM uint32_t IPVERSION; /**< IP Version ID */ 47 __IOM uint32_t EN; /**< PDM Module enable Register */ 48 __IOM uint32_t CTRL; /**< PDM Core Control Register */ 49 __IOM uint32_t CMD; /**< PDM Core Command Register */ 50 __IM uint32_t STATUS; /**< PDM Status register */ 51 __IOM uint32_t CFG0; /**< PDM Core Configuration Register0 */ 52 __IOM uint32_t CFG1; /**< PDM Core Configuration Register1 */ 53 uint32_t RESERVED0[1U]; /**< Reserved for future use */ 54 __IM uint32_t RXDATA; /**< PDM Received Data Register */ 55 uint32_t RESERVED1[7U]; /**< Reserved for future use */ 56 __IOM uint32_t IF; /**< Interrupt Flag Register */ 57 __IOM uint32_t IEN; /**< Interrupt Flag Register */ 58 uint32_t RESERVED2[6U]; /**< Reserved for future use */ 59 __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ 60 uint32_t RESERVED3[999U]; /**< Reserved for future use */ 61 __IM uint32_t IPVERSION_SET; /**< IP Version ID */ 62 __IOM uint32_t EN_SET; /**< PDM Module enable Register */ 63 __IOM uint32_t CTRL_SET; /**< PDM Core Control Register */ 64 __IOM uint32_t CMD_SET; /**< PDM Core Command Register */ 65 __IM uint32_t STATUS_SET; /**< PDM Status register */ 66 __IOM uint32_t CFG0_SET; /**< PDM Core Configuration Register0 */ 67 __IOM uint32_t CFG1_SET; /**< PDM Core Configuration Register1 */ 68 uint32_t RESERVED4[1U]; /**< Reserved for future use */ 69 __IM uint32_t RXDATA_SET; /**< PDM Received Data Register */ 70 uint32_t RESERVED5[7U]; /**< Reserved for future use */ 71 __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ 72 __IOM uint32_t IEN_SET; /**< Interrupt Flag Register */ 73 uint32_t RESERVED6[6U]; /**< Reserved for future use */ 74 __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ 75 uint32_t RESERVED7[999U]; /**< Reserved for future use */ 76 __IM uint32_t IPVERSION_CLR; /**< IP Version ID */ 77 __IOM uint32_t EN_CLR; /**< PDM Module enable Register */ 78 __IOM uint32_t CTRL_CLR; /**< PDM Core Control Register */ 79 __IOM uint32_t CMD_CLR; /**< PDM Core Command Register */ 80 __IM uint32_t STATUS_CLR; /**< PDM Status register */ 81 __IOM uint32_t CFG0_CLR; /**< PDM Core Configuration Register0 */ 82 __IOM uint32_t CFG1_CLR; /**< PDM Core Configuration Register1 */ 83 uint32_t RESERVED8[1U]; /**< Reserved for future use */ 84 __IM uint32_t RXDATA_CLR; /**< PDM Received Data Register */ 85 uint32_t RESERVED9[7U]; /**< Reserved for future use */ 86 __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ 87 __IOM uint32_t IEN_CLR; /**< Interrupt Flag Register */ 88 uint32_t RESERVED10[6U]; /**< Reserved for future use */ 89 __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ 90 uint32_t RESERVED11[999U]; /**< Reserved for future use */ 91 __IM uint32_t IPVERSION_TGL; /**< IP Version ID */ 92 __IOM uint32_t EN_TGL; /**< PDM Module enable Register */ 93 __IOM uint32_t CTRL_TGL; /**< PDM Core Control Register */ 94 __IOM uint32_t CMD_TGL; /**< PDM Core Command Register */ 95 __IM uint32_t STATUS_TGL; /**< PDM Status register */ 96 __IOM uint32_t CFG0_TGL; /**< PDM Core Configuration Register0 */ 97 __IOM uint32_t CFG1_TGL; /**< PDM Core Configuration Register1 */ 98 uint32_t RESERVED12[1U]; /**< Reserved for future use */ 99 __IM uint32_t RXDATA_TGL; /**< PDM Received Data Register */ 100 uint32_t RESERVED13[7U]; /**< Reserved for future use */ 101 __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ 102 __IOM uint32_t IEN_TGL; /**< Interrupt Flag Register */ 103 uint32_t RESERVED14[6U]; /**< Reserved for future use */ 104 __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ 105 } PDM_TypeDef; 106 /** @} End of group EFR32BG27_PDM */ 107 108 /**************************************************************************//** 109 * @addtogroup EFR32BG27_PDM 110 * @{ 111 * @defgroup EFR32BG27_PDM_BitFields PDM Bit Fields 112 * @{ 113 *****************************************************************************/ 114 115 /* Bit fields for PDM IPVERSION */ 116 #define _PDM_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for PDM_IPVERSION */ 117 #define _PDM_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for PDM_IPVERSION */ 118 #define _PDM_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for PDM_IPVERSION */ 119 #define _PDM_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for PDM_IPVERSION */ 120 #define _PDM_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IPVERSION */ 121 #define PDM_IPVERSION_IPVERSION_DEFAULT (_PDM_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_IPVERSION */ 122 123 /* Bit fields for PDM EN */ 124 #define _PDM_EN_RESETVALUE 0x00000000UL /**< Default value for PDM_EN */ 125 #define _PDM_EN_MASK 0x00000001UL /**< Mask for PDM_EN */ 126 #define PDM_EN_EN (0x1UL << 0) /**< PDM enable */ 127 #define _PDM_EN_EN_SHIFT 0 /**< Shift value for PDM_EN */ 128 #define _PDM_EN_EN_MASK 0x1UL /**< Bit mask for PDM_EN */ 129 #define _PDM_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_EN */ 130 #define _PDM_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for PDM_EN */ 131 #define _PDM_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for PDM_EN */ 132 #define PDM_EN_EN_DEFAULT (_PDM_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_EN */ 133 #define PDM_EN_EN_DISABLE (_PDM_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for PDM_EN */ 134 #define PDM_EN_EN_ENABLE (_PDM_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for PDM_EN */ 135 136 /* Bit fields for PDM CTRL */ 137 #define _PDM_CTRL_RESETVALUE 0x00000000UL /**< Default value for PDM_CTRL */ 138 #define _PDM_CTRL_MASK 0x000FFF1FUL /**< Mask for PDM_CTRL */ 139 #define _PDM_CTRL_GAIN_SHIFT 0 /**< Shift value for PDM_GAIN */ 140 #define _PDM_CTRL_GAIN_MASK 0x1FUL /**< Bit mask for PDM_GAIN */ 141 #define _PDM_CTRL_GAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CTRL */ 142 #define PDM_CTRL_GAIN_DEFAULT (_PDM_CTRL_GAIN_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_CTRL */ 143 #define _PDM_CTRL_DSR_SHIFT 8 /**< Shift value for PDM_DSR */ 144 #define _PDM_CTRL_DSR_MASK 0xFFF00UL /**< Bit mask for PDM_DSR */ 145 #define _PDM_CTRL_DSR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CTRL */ 146 #define PDM_CTRL_DSR_DEFAULT (_PDM_CTRL_DSR_DEFAULT << 8) /**< Shifted mode DEFAULT for PDM_CTRL */ 147 148 /* Bit fields for PDM CMD */ 149 #define _PDM_CMD_RESETVALUE 0x00000000UL /**< Default value for PDM_CMD */ 150 #define _PDM_CMD_MASK 0x00010111UL /**< Mask for PDM_CMD */ 151 #define PDM_CMD_START (0x1UL << 0) /**< Start DCF */ 152 #define _PDM_CMD_START_SHIFT 0 /**< Shift value for PDM_START */ 153 #define _PDM_CMD_START_MASK 0x1UL /**< Bit mask for PDM_START */ 154 #define _PDM_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CMD */ 155 #define PDM_CMD_START_DEFAULT (_PDM_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_CMD */ 156 #define PDM_CMD_STOP (0x1UL << 4) /**< Stop DCF */ 157 #define _PDM_CMD_STOP_SHIFT 4 /**< Shift value for PDM_STOP */ 158 #define _PDM_CMD_STOP_MASK 0x10UL /**< Bit mask for PDM_STOP */ 159 #define _PDM_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CMD */ 160 #define PDM_CMD_STOP_DEFAULT (_PDM_CMD_STOP_DEFAULT << 4) /**< Shifted mode DEFAULT for PDM_CMD */ 161 #define PDM_CMD_CLEAR (0x1UL << 8) /**< Clear DCF */ 162 #define _PDM_CMD_CLEAR_SHIFT 8 /**< Shift value for PDM_CLEAR */ 163 #define _PDM_CMD_CLEAR_MASK 0x100UL /**< Bit mask for PDM_CLEAR */ 164 #define _PDM_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CMD */ 165 #define PDM_CMD_CLEAR_DEFAULT (_PDM_CMD_CLEAR_DEFAULT << 8) /**< Shifted mode DEFAULT for PDM_CMD */ 166 #define PDM_CMD_FIFOFL (0x1UL << 16) /**< FIFO Flush */ 167 #define _PDM_CMD_FIFOFL_SHIFT 16 /**< Shift value for PDM_FIFOFL */ 168 #define _PDM_CMD_FIFOFL_MASK 0x10000UL /**< Bit mask for PDM_FIFOFL */ 169 #define _PDM_CMD_FIFOFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CMD */ 170 #define PDM_CMD_FIFOFL_DEFAULT (_PDM_CMD_FIFOFL_DEFAULT << 16) /**< Shifted mode DEFAULT for PDM_CMD */ 171 172 /* Bit fields for PDM STATUS */ 173 #define _PDM_STATUS_RESETVALUE 0x00000020UL /**< Default value for PDM_STATUS */ 174 #define _PDM_STATUS_MASK 0x00000731UL /**< Mask for PDM_STATUS */ 175 #define PDM_STATUS_ACT (0x1UL << 0) /**< PDM is active */ 176 #define _PDM_STATUS_ACT_SHIFT 0 /**< Shift value for PDM_ACT */ 177 #define _PDM_STATUS_ACT_MASK 0x1UL /**< Bit mask for PDM_ACT */ 178 #define _PDM_STATUS_ACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_STATUS */ 179 #define PDM_STATUS_ACT_DEFAULT (_PDM_STATUS_ACT_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_STATUS */ 180 #define PDM_STATUS_FULL (0x1UL << 4) /**< FIFO FULL Status */ 181 #define _PDM_STATUS_FULL_SHIFT 4 /**< Shift value for PDM_FULL */ 182 #define _PDM_STATUS_FULL_MASK 0x10UL /**< Bit mask for PDM_FULL */ 183 #define _PDM_STATUS_FULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_STATUS */ 184 #define PDM_STATUS_FULL_DEFAULT (_PDM_STATUS_FULL_DEFAULT << 4) /**< Shifted mode DEFAULT for PDM_STATUS */ 185 #define PDM_STATUS_EMPTY (0x1UL << 5) /**< FIFO EMPTY Status */ 186 #define _PDM_STATUS_EMPTY_SHIFT 5 /**< Shift value for PDM_EMPTY */ 187 #define _PDM_STATUS_EMPTY_MASK 0x20UL /**< Bit mask for PDM_EMPTY */ 188 #define _PDM_STATUS_EMPTY_DEFAULT 0x00000001UL /**< Mode DEFAULT for PDM_STATUS */ 189 #define PDM_STATUS_EMPTY_DEFAULT (_PDM_STATUS_EMPTY_DEFAULT << 5) /**< Shifted mode DEFAULT for PDM_STATUS */ 190 #define _PDM_STATUS_FIFOCNT_SHIFT 8 /**< Shift value for PDM_FIFOCNT */ 191 #define _PDM_STATUS_FIFOCNT_MASK 0x700UL /**< Bit mask for PDM_FIFOCNT */ 192 #define _PDM_STATUS_FIFOCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_STATUS */ 193 #define PDM_STATUS_FIFOCNT_DEFAULT (_PDM_STATUS_FIFOCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for PDM_STATUS */ 194 195 /* Bit fields for PDM CFG0 */ 196 #define _PDM_CFG0_RESETVALUE 0x00000000UL /**< Default value for PDM_CFG0 */ 197 #define _PDM_CFG0_MASK 0x03013713UL /**< Mask for PDM_CFG0 */ 198 #define _PDM_CFG0_FORDER_SHIFT 0 /**< Shift value for PDM_FORDER */ 199 #define _PDM_CFG0_FORDER_MASK 0x3UL /**< Bit mask for PDM_FORDER */ 200 #define _PDM_CFG0_FORDER_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ 201 #define _PDM_CFG0_FORDER_SECOND 0x00000000UL /**< Mode SECOND for PDM_CFG0 */ 202 #define _PDM_CFG0_FORDER_THIRD 0x00000001UL /**< Mode THIRD for PDM_CFG0 */ 203 #define _PDM_CFG0_FORDER_FOURTH 0x00000002UL /**< Mode FOURTH for PDM_CFG0 */ 204 #define _PDM_CFG0_FORDER_FIFTH 0x00000003UL /**< Mode FIFTH for PDM_CFG0 */ 205 #define PDM_CFG0_FORDER_DEFAULT (_PDM_CFG0_FORDER_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_CFG0 */ 206 #define PDM_CFG0_FORDER_SECOND (_PDM_CFG0_FORDER_SECOND << 0) /**< Shifted mode SECOND for PDM_CFG0 */ 207 #define PDM_CFG0_FORDER_THIRD (_PDM_CFG0_FORDER_THIRD << 0) /**< Shifted mode THIRD for PDM_CFG0 */ 208 #define PDM_CFG0_FORDER_FOURTH (_PDM_CFG0_FORDER_FOURTH << 0) /**< Shifted mode FOURTH for PDM_CFG0 */ 209 #define PDM_CFG0_FORDER_FIFTH (_PDM_CFG0_FORDER_FIFTH << 0) /**< Shifted mode FIFTH for PDM_CFG0 */ 210 #define PDM_CFG0_NUMCH (0x1UL << 4) /**< Number of Channels */ 211 #define _PDM_CFG0_NUMCH_SHIFT 4 /**< Shift value for PDM_NUMCH */ 212 #define _PDM_CFG0_NUMCH_MASK 0x10UL /**< Bit mask for PDM_NUMCH */ 213 #define _PDM_CFG0_NUMCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ 214 #define _PDM_CFG0_NUMCH_ONE 0x00000000UL /**< Mode ONE for PDM_CFG0 */ 215 #define _PDM_CFG0_NUMCH_TWO 0x00000001UL /**< Mode TWO for PDM_CFG0 */ 216 #define PDM_CFG0_NUMCH_DEFAULT (_PDM_CFG0_NUMCH_DEFAULT << 4) /**< Shifted mode DEFAULT for PDM_CFG0 */ 217 #define PDM_CFG0_NUMCH_ONE (_PDM_CFG0_NUMCH_ONE << 4) /**< Shifted mode ONE for PDM_CFG0 */ 218 #define PDM_CFG0_NUMCH_TWO (_PDM_CFG0_NUMCH_TWO << 4) /**< Shifted mode TWO for PDM_CFG0 */ 219 #define _PDM_CFG0_DATAFORMAT_SHIFT 8 /**< Shift value for PDM_DATAFORMAT */ 220 #define _PDM_CFG0_DATAFORMAT_MASK 0x700UL /**< Bit mask for PDM_DATAFORMAT */ 221 #define _PDM_CFG0_DATAFORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ 222 #define _PDM_CFG0_DATAFORMAT_RIGHT16 0x00000000UL /**< Mode RIGHT16 for PDM_CFG0 */ 223 #define _PDM_CFG0_DATAFORMAT_DOUBLE16 0x00000001UL /**< Mode DOUBLE16 for PDM_CFG0 */ 224 #define _PDM_CFG0_DATAFORMAT_RIGHT24 0x00000002UL /**< Mode RIGHT24 for PDM_CFG0 */ 225 #define _PDM_CFG0_DATAFORMAT_FULL32BIT 0x00000003UL /**< Mode FULL32BIT for PDM_CFG0 */ 226 #define _PDM_CFG0_DATAFORMAT_LEFT16 0x00000004UL /**< Mode LEFT16 for PDM_CFG0 */ 227 #define _PDM_CFG0_DATAFORMAT_LEFT24 0x00000005UL /**< Mode LEFT24 for PDM_CFG0 */ 228 #define _PDM_CFG0_DATAFORMAT_RAW32BIT 0x00000006UL /**< Mode RAW32BIT for PDM_CFG0 */ 229 #define PDM_CFG0_DATAFORMAT_DEFAULT (_PDM_CFG0_DATAFORMAT_DEFAULT << 8) /**< Shifted mode DEFAULT for PDM_CFG0 */ 230 #define PDM_CFG0_DATAFORMAT_RIGHT16 (_PDM_CFG0_DATAFORMAT_RIGHT16 << 8) /**< Shifted mode RIGHT16 for PDM_CFG0 */ 231 #define PDM_CFG0_DATAFORMAT_DOUBLE16 (_PDM_CFG0_DATAFORMAT_DOUBLE16 << 8) /**< Shifted mode DOUBLE16 for PDM_CFG0 */ 232 #define PDM_CFG0_DATAFORMAT_RIGHT24 (_PDM_CFG0_DATAFORMAT_RIGHT24 << 8) /**< Shifted mode RIGHT24 for PDM_CFG0 */ 233 #define PDM_CFG0_DATAFORMAT_FULL32BIT (_PDM_CFG0_DATAFORMAT_FULL32BIT << 8) /**< Shifted mode FULL32BIT for PDM_CFG0 */ 234 #define PDM_CFG0_DATAFORMAT_LEFT16 (_PDM_CFG0_DATAFORMAT_LEFT16 << 8) /**< Shifted mode LEFT16 for PDM_CFG0 */ 235 #define PDM_CFG0_DATAFORMAT_LEFT24 (_PDM_CFG0_DATAFORMAT_LEFT24 << 8) /**< Shifted mode LEFT24 for PDM_CFG0 */ 236 #define PDM_CFG0_DATAFORMAT_RAW32BIT (_PDM_CFG0_DATAFORMAT_RAW32BIT << 8) /**< Shifted mode RAW32BIT for PDM_CFG0 */ 237 #define _PDM_CFG0_FIFODVL_SHIFT 12 /**< Shift value for PDM_FIFODVL */ 238 #define _PDM_CFG0_FIFODVL_MASK 0x3000UL /**< Bit mask for PDM_FIFODVL */ 239 #define _PDM_CFG0_FIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ 240 #define _PDM_CFG0_FIFODVL_ONE 0x00000000UL /**< Mode ONE for PDM_CFG0 */ 241 #define _PDM_CFG0_FIFODVL_TWO 0x00000001UL /**< Mode TWO for PDM_CFG0 */ 242 #define _PDM_CFG0_FIFODVL_THREE 0x00000002UL /**< Mode THREE for PDM_CFG0 */ 243 #define _PDM_CFG0_FIFODVL_FOUR 0x00000003UL /**< Mode FOUR for PDM_CFG0 */ 244 #define PDM_CFG0_FIFODVL_DEFAULT (_PDM_CFG0_FIFODVL_DEFAULT << 12) /**< Shifted mode DEFAULT for PDM_CFG0 */ 245 #define PDM_CFG0_FIFODVL_ONE (_PDM_CFG0_FIFODVL_ONE << 12) /**< Shifted mode ONE for PDM_CFG0 */ 246 #define PDM_CFG0_FIFODVL_TWO (_PDM_CFG0_FIFODVL_TWO << 12) /**< Shifted mode TWO for PDM_CFG0 */ 247 #define PDM_CFG0_FIFODVL_THREE (_PDM_CFG0_FIFODVL_THREE << 12) /**< Shifted mode THREE for PDM_CFG0 */ 248 #define PDM_CFG0_FIFODVL_FOUR (_PDM_CFG0_FIFODVL_FOUR << 12) /**< Shifted mode FOUR for PDM_CFG0 */ 249 #define PDM_CFG0_STEREOMODECH01 (0x1UL << 16) /**< Stereo mode CH01 */ 250 #define _PDM_CFG0_STEREOMODECH01_SHIFT 16 /**< Shift value for PDM_STEREOMODECH01 */ 251 #define _PDM_CFG0_STEREOMODECH01_MASK 0x10000UL /**< Bit mask for PDM_STEREOMODECH01 */ 252 #define _PDM_CFG0_STEREOMODECH01_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ 253 #define _PDM_CFG0_STEREOMODECH01_DISABLE 0x00000000UL /**< Mode DISABLE for PDM_CFG0 */ 254 #define _PDM_CFG0_STEREOMODECH01_CH01ENABLE 0x00000001UL /**< Mode CH01ENABLE for PDM_CFG0 */ 255 #define PDM_CFG0_STEREOMODECH01_DEFAULT (_PDM_CFG0_STEREOMODECH01_DEFAULT << 16) /**< Shifted mode DEFAULT for PDM_CFG0 */ 256 #define PDM_CFG0_STEREOMODECH01_DISABLE (_PDM_CFG0_STEREOMODECH01_DISABLE << 16) /**< Shifted mode DISABLE for PDM_CFG0 */ 257 #define PDM_CFG0_STEREOMODECH01_CH01ENABLE (_PDM_CFG0_STEREOMODECH01_CH01ENABLE << 16) /**< Shifted mode CH01ENABLE for PDM_CFG0 */ 258 #define PDM_CFG0_CH0CLKPOL (0x1UL << 24) /**< CH0 CLK Polarity */ 259 #define _PDM_CFG0_CH0CLKPOL_SHIFT 24 /**< Shift value for PDM_CH0CLKPOL */ 260 #define _PDM_CFG0_CH0CLKPOL_MASK 0x1000000UL /**< Bit mask for PDM_CH0CLKPOL */ 261 #define _PDM_CFG0_CH0CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ 262 #define _PDM_CFG0_CH0CLKPOL_NORMAL 0x00000000UL /**< Mode NORMAL for PDM_CFG0 */ 263 #define _PDM_CFG0_CH0CLKPOL_INVERT 0x00000001UL /**< Mode INVERT for PDM_CFG0 */ 264 #define PDM_CFG0_CH0CLKPOL_DEFAULT (_PDM_CFG0_CH0CLKPOL_DEFAULT << 24) /**< Shifted mode DEFAULT for PDM_CFG0 */ 265 #define PDM_CFG0_CH0CLKPOL_NORMAL (_PDM_CFG0_CH0CLKPOL_NORMAL << 24) /**< Shifted mode NORMAL for PDM_CFG0 */ 266 #define PDM_CFG0_CH0CLKPOL_INVERT (_PDM_CFG0_CH0CLKPOL_INVERT << 24) /**< Shifted mode INVERT for PDM_CFG0 */ 267 #define PDM_CFG0_CH1CLKPOL (0x1UL << 25) /**< CH1 CLK Polarity */ 268 #define _PDM_CFG0_CH1CLKPOL_SHIFT 25 /**< Shift value for PDM_CH1CLKPOL */ 269 #define _PDM_CFG0_CH1CLKPOL_MASK 0x2000000UL /**< Bit mask for PDM_CH1CLKPOL */ 270 #define _PDM_CFG0_CH1CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ 271 #define _PDM_CFG0_CH1CLKPOL_NORMAL 0x00000000UL /**< Mode NORMAL for PDM_CFG0 */ 272 #define _PDM_CFG0_CH1CLKPOL_INVERT 0x00000001UL /**< Mode INVERT for PDM_CFG0 */ 273 #define PDM_CFG0_CH1CLKPOL_DEFAULT (_PDM_CFG0_CH1CLKPOL_DEFAULT << 25) /**< Shifted mode DEFAULT for PDM_CFG0 */ 274 #define PDM_CFG0_CH1CLKPOL_NORMAL (_PDM_CFG0_CH1CLKPOL_NORMAL << 25) /**< Shifted mode NORMAL for PDM_CFG0 */ 275 #define PDM_CFG0_CH1CLKPOL_INVERT (_PDM_CFG0_CH1CLKPOL_INVERT << 25) /**< Shifted mode INVERT for PDM_CFG0 */ 276 277 /* Bit fields for PDM CFG1 */ 278 #define _PDM_CFG1_RESETVALUE 0x00000000UL /**< Default value for PDM_CFG1 */ 279 #define _PDM_CFG1_MASK 0x030003FFUL /**< Mask for PDM_CFG1 */ 280 #define _PDM_CFG1_PRESC_SHIFT 0 /**< Shift value for PDM_PRESC */ 281 #define _PDM_CFG1_PRESC_MASK 0x3FFUL /**< Bit mask for PDM_PRESC */ 282 #define _PDM_CFG1_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG1 */ 283 #define PDM_CFG1_PRESC_DEFAULT (_PDM_CFG1_PRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_CFG1 */ 284 #define _PDM_CFG1_DLYMUXSEL_SHIFT 24 /**< Shift value for PDM_DLYMUXSEL */ 285 #define _PDM_CFG1_DLYMUXSEL_MASK 0x3000000UL /**< Bit mask for PDM_DLYMUXSEL */ 286 #define _PDM_CFG1_DLYMUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG1 */ 287 #define PDM_CFG1_DLYMUXSEL_DEFAULT (_PDM_CFG1_DLYMUXSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PDM_CFG1 */ 288 289 /* Bit fields for PDM RXDATA */ 290 #define _PDM_RXDATA_RESETVALUE 0x00000000UL /**< Default value for PDM_RXDATA */ 291 #define _PDM_RXDATA_MASK 0xFFFFFFFFUL /**< Mask for PDM_RXDATA */ 292 #define _PDM_RXDATA_RXDATA_SHIFT 0 /**< Shift value for PDM_RXDATA */ 293 #define _PDM_RXDATA_RXDATA_MASK 0xFFFFFFFFUL /**< Bit mask for PDM_RXDATA */ 294 #define _PDM_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_RXDATA */ 295 #define PDM_RXDATA_RXDATA_DEFAULT (_PDM_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_RXDATA */ 296 297 /* Bit fields for PDM IF */ 298 #define _PDM_IF_RESETVALUE 0x00000000UL /**< Default value for PDM_IF */ 299 #define _PDM_IF_MASK 0x0000000FUL /**< Mask for PDM_IF */ 300 #define PDM_IF_DV (0x1UL << 0) /**< Data Valid Interrupt Flag */ 301 #define _PDM_IF_DV_SHIFT 0 /**< Shift value for PDM_DV */ 302 #define _PDM_IF_DV_MASK 0x1UL /**< Bit mask for PDM_DV */ 303 #define _PDM_IF_DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IF */ 304 #define PDM_IF_DV_DEFAULT (_PDM_IF_DV_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_IF */ 305 #define PDM_IF_DVL (0x1UL << 1) /**< Data Valid Level Interrupt Flag */ 306 #define _PDM_IF_DVL_SHIFT 1 /**< Shift value for PDM_DVL */ 307 #define _PDM_IF_DVL_MASK 0x2UL /**< Bit mask for PDM_DVL */ 308 #define _PDM_IF_DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IF */ 309 #define PDM_IF_DVL_DEFAULT (_PDM_IF_DVL_DEFAULT << 1) /**< Shifted mode DEFAULT for PDM_IF */ 310 #define PDM_IF_OF (0x1UL << 2) /**< FIFO Overflow Interrupt Flag */ 311 #define _PDM_IF_OF_SHIFT 2 /**< Shift value for PDM_OF */ 312 #define _PDM_IF_OF_MASK 0x4UL /**< Bit mask for PDM_OF */ 313 #define _PDM_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IF */ 314 #define PDM_IF_OF_DEFAULT (_PDM_IF_OF_DEFAULT << 2) /**< Shifted mode DEFAULT for PDM_IF */ 315 #define PDM_IF_UF (0x1UL << 3) /**< FIFO Undeflow Interrupt Flag */ 316 #define _PDM_IF_UF_SHIFT 3 /**< Shift value for PDM_UF */ 317 #define _PDM_IF_UF_MASK 0x8UL /**< Bit mask for PDM_UF */ 318 #define _PDM_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IF */ 319 #define PDM_IF_UF_DEFAULT (_PDM_IF_UF_DEFAULT << 3) /**< Shifted mode DEFAULT for PDM_IF */ 320 321 /* Bit fields for PDM IEN */ 322 #define _PDM_IEN_RESETVALUE 0x00000000UL /**< Default value for PDM_IEN */ 323 #define _PDM_IEN_MASK 0x0000000FUL /**< Mask for PDM_IEN */ 324 #define PDM_IEN_DV (0x1UL << 0) /**< Data Valid Interrupt Enable */ 325 #define _PDM_IEN_DV_SHIFT 0 /**< Shift value for PDM_DV */ 326 #define _PDM_IEN_DV_MASK 0x1UL /**< Bit mask for PDM_DV */ 327 #define _PDM_IEN_DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IEN */ 328 #define PDM_IEN_DV_DEFAULT (_PDM_IEN_DV_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_IEN */ 329 #define PDM_IEN_DVL (0x1UL << 1) /**< Data Valid Level Interrupt Enable */ 330 #define _PDM_IEN_DVL_SHIFT 1 /**< Shift value for PDM_DVL */ 331 #define _PDM_IEN_DVL_MASK 0x2UL /**< Bit mask for PDM_DVL */ 332 #define _PDM_IEN_DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IEN */ 333 #define PDM_IEN_DVL_DEFAULT (_PDM_IEN_DVL_DEFAULT << 1) /**< Shifted mode DEFAULT for PDM_IEN */ 334 #define PDM_IEN_OF (0x1UL << 2) /**< FIFO Overflow Interrupt Enable */ 335 #define _PDM_IEN_OF_SHIFT 2 /**< Shift value for PDM_OF */ 336 #define _PDM_IEN_OF_MASK 0x4UL /**< Bit mask for PDM_OF */ 337 #define _PDM_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IEN */ 338 #define PDM_IEN_OF_DEFAULT (_PDM_IEN_OF_DEFAULT << 2) /**< Shifted mode DEFAULT for PDM_IEN */ 339 #define PDM_IEN_UF (0x1UL << 3) /**< FIFO Undeflow Interrupt Enable */ 340 #define _PDM_IEN_UF_SHIFT 3 /**< Shift value for PDM_UF */ 341 #define _PDM_IEN_UF_MASK 0x8UL /**< Bit mask for PDM_UF */ 342 #define _PDM_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IEN */ 343 #define PDM_IEN_UF_DEFAULT (_PDM_IEN_UF_DEFAULT << 3) /**< Shifted mode DEFAULT for PDM_IEN */ 344 345 /* Bit fields for PDM SYNCBUSY */ 346 #define _PDM_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for PDM_SYNCBUSY */ 347 #define _PDM_SYNCBUSY_MASK 0x00000009UL /**< Mask for PDM_SYNCBUSY */ 348 #define PDM_SYNCBUSY_SYNCBUSY (0x1UL << 0) /**< sync busy */ 349 #define _PDM_SYNCBUSY_SYNCBUSY_SHIFT 0 /**< Shift value for PDM_SYNCBUSY */ 350 #define _PDM_SYNCBUSY_SYNCBUSY_MASK 0x1UL /**< Bit mask for PDM_SYNCBUSY */ 351 #define _PDM_SYNCBUSY_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_SYNCBUSY */ 352 #define PDM_SYNCBUSY_SYNCBUSY_DEFAULT (_PDM_SYNCBUSY_SYNCBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_SYNCBUSY */ 353 #define PDM_SYNCBUSY_FIFOFLBUSY (0x1UL << 3) /**< FIFO Flush Sync busy */ 354 #define _PDM_SYNCBUSY_FIFOFLBUSY_SHIFT 3 /**< Shift value for PDM_FIFOFLBUSY */ 355 #define _PDM_SYNCBUSY_FIFOFLBUSY_MASK 0x8UL /**< Bit mask for PDM_FIFOFLBUSY */ 356 #define _PDM_SYNCBUSY_FIFOFLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_SYNCBUSY */ 357 #define PDM_SYNCBUSY_FIFOFLBUSY_DEFAULT (_PDM_SYNCBUSY_FIFOFLBUSY_DEFAULT << 3) /**< Shifted mode DEFAULT for PDM_SYNCBUSY */ 358 359 /** @} End of group EFR32BG27_PDM_BitFields */ 360 /** @} End of group EFR32BG27_PDM */ 361 /** @} End of group Parts */ 362 363 #endif // EFR32BG27_PDM_H 364
