1 /**************************************************************************//** 2 * @file 3 * @brief CMSIS Cortex-M Peripheral Access Layer Header File 4 * for EFR32BG22C112F352GM40 5 ****************************************************************************** 6 * # License 7 * <b>Copyright 2024 Silicon Laboratories, Inc. www.silabs.com</b> 8 ****************************************************************************** 9 * 10 * SPDX-License-Identifier: Zlib 11 * 12 * The licensor of this software is Silicon Laboratories Inc. 13 * 14 * This software is provided 'as-is', without any express or implied 15 * warranty. In no event will the authors be held liable for any damages 16 * arising from the use of this software. 17 * 18 * Permission is granted to anyone to use this software for any purpose, 19 * including commercial applications, and to alter it and redistribute it 20 * freely, subject to the following restrictions: 21 * 22 * 1. The origin of this software must not be misrepresented; you must not 23 * claim that you wrote the original software. If you use this software 24 * in a product, an acknowledgment in the product documentation would be 25 * appreciated but is not required. 26 * 2. Altered source versions must be plainly marked as such, and must not be 27 * misrepresented as being the original software. 28 * 3. This notice may not be removed or altered from any source distribution. 29 * 30 *****************************************************************************/ 31 #ifndef EFR32BG22C112F352GM40_H 32 #define EFR32BG22C112F352GM40_H 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 /**************************************************************************//** 39 * @addtogroup Parts 40 * @{ 41 *****************************************************************************/ 42 43 /**************************************************************************//** 44 * @defgroup EFR32BG22C112F352GM40 EFR32BG22C112F352GM40 45 * @{ 46 *****************************************************************************/ 47 48 /** Interrupt Number Definition */ 49 typedef enum IRQn{ 50 /****** Cortex-M Processor Exceptions Numbers ******************************************/ 51 NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ 52 HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ 53 MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ 54 BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ 55 UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ 56 #if defined(CONFIG_ARM_SECURE_FIRMWARE) 57 SecureFault_IRQn = -9, 58 #endif 59 SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ 60 DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ 61 PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ 62 SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ 63 64 /****** EFR32BG22 Peripheral Interrupt Numbers ******************************************/ 65 66 CRYPTOACC_IRQn = 0, /*!< 0 EFR32 CRYPTOACC Interrupt */ 67 TRNG_IRQn = 1, /*!< 1 EFR32 TRNG Interrupt */ 68 PKE_IRQn = 2, /*!< 2 EFR32 PKE Interrupt */ 69 SMU_SECURE_IRQn = 3, /*!< 3 EFR32 SMU_SECURE Interrupt */ 70 SMU_S_PRIVILEGED_IRQn = 4, /*!< 4 EFR32 SMU_S_PRIVILEGED Interrupt */ 71 SMU_NS_PRIVILEGED_IRQn = 5, /*!< 5 EFR32 SMU_NS_PRIVILEGED Interrupt */ 72 EMU_IRQn = 6, /*!< 6 EFR32 EMU Interrupt */ 73 TIMER0_IRQn = 7, /*!< 7 EFR32 TIMER0 Interrupt */ 74 TIMER1_IRQn = 8, /*!< 8 EFR32 TIMER1 Interrupt */ 75 TIMER2_IRQn = 9, /*!< 9 EFR32 TIMER2 Interrupt */ 76 TIMER3_IRQn = 10, /*!< 10 EFR32 TIMER3 Interrupt */ 77 TIMER4_IRQn = 11, /*!< 11 EFR32 TIMER4 Interrupt */ 78 RTCC_IRQn = 12, /*!< 12 EFR32 RTCC Interrupt */ 79 USART0_RX_IRQn = 13, /*!< 13 EFR32 USART0_RX Interrupt */ 80 USART0_TX_IRQn = 14, /*!< 14 EFR32 USART0_TX Interrupt */ 81 USART1_RX_IRQn = 15, /*!< 15 EFR32 USART1_RX Interrupt */ 82 USART1_TX_IRQn = 16, /*!< 16 EFR32 USART1_TX Interrupt */ 83 ICACHE0_IRQn = 17, /*!< 17 EFR32 ICACHE0 Interrupt */ 84 BURTC_IRQn = 18, /*!< 18 EFR32 BURTC Interrupt */ 85 LETIMER0_IRQn = 19, /*!< 19 EFR32 LETIMER0 Interrupt */ 86 SYSCFG_IRQn = 20, /*!< 20 EFR32 SYSCFG Interrupt */ 87 LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ 88 LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ 89 LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ 90 ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ 91 GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ 92 GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ 93 I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ 94 I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ 95 EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ 96 EMUSE_IRQn = 30, /*!< 30 EFR32 EMUSE Interrupt */ 97 AGC_IRQn = 31, /*!< 31 EFR32 AGC Interrupt */ 98 BUFC_IRQn = 32, /*!< 32 EFR32 BUFC Interrupt */ 99 FRC_PRI_IRQn = 33, /*!< 33 EFR32 FRC_PRI Interrupt */ 100 FRC_IRQn = 34, /*!< 34 EFR32 FRC Interrupt */ 101 MODEM_IRQn = 35, /*!< 35 EFR32 MODEM Interrupt */ 102 PROTIMER_IRQn = 36, /*!< 36 EFR32 PROTIMER Interrupt */ 103 RAC_RSM_IRQn = 37, /*!< 37 EFR32 RAC_RSM Interrupt */ 104 RAC_SEQ_IRQn = 38, /*!< 38 EFR32 RAC_SEQ Interrupt */ 105 RDMAILBOX_IRQn = 39, /*!< 39 EFR32 RDMAILBOX Interrupt */ 106 RFSENSE_IRQn = 40, /*!< 40 EFR32 RFSENSE Interrupt */ 107 PRORTC_IRQn = 41, /*!< 41 EFR32 PRORTC Interrupt */ 108 SYNTH_IRQn = 42, /*!< 42 EFR32 SYNTH Interrupt */ 109 WDOG0_IRQn = 43, /*!< 43 EFR32 WDOG0 Interrupt */ 110 HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ 111 HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ 112 CMU_IRQn = 46, /*!< 46 EFR32 CMU Interrupt */ 113 AES_IRQn = 47, /*!< 47 EFR32 AES Interrupt */ 114 IADC_IRQn = 48, /*!< 48 EFR32 IADC Interrupt */ 115 MSC_IRQn = 49, /*!< 49 EFR32 MSC Interrupt */ 116 DPLL0_IRQn = 50, /*!< 50 EFR32 DPLL0 Interrupt */ 117 PDM_IRQn = 51, /*!< 51 EFR32 PDM Interrupt */ 118 SW0_IRQn = 52, /*!< 52 EFR32 SW0 Interrupt */ 119 SW1_IRQn = 53, /*!< 53 EFR32 SW1 Interrupt */ 120 SW2_IRQn = 54, /*!< 54 EFR32 SW2 Interrupt */ 121 SW3_IRQn = 55, /*!< 55 EFR32 SW3 Interrupt */ 122 KERNEL0_IRQn = 56, /*!< 56 EFR32 KERNEL0 Interrupt */ 123 KERNEL1_IRQn = 57, /*!< 57 EFR32 KERNEL1 Interrupt */ 124 M33CTI0_IRQn = 58, /*!< 58 EFR32 M33CTI0 Interrupt */ 125 M33CTI1_IRQn = 59, /*!< 59 EFR32 M33CTI1 Interrupt */ 126 EMUEFP_IRQn = 60, /*!< 60 EFR32 EMUEFP Interrupt */ 127 DCDC_IRQn = 61, /*!< 61 EFR32 DCDC Interrupt */ 128 EUART0_RX_IRQn = 62, /*!< 62 EFR32 EUART0_RX Interrupt */ 129 EUART0_TX_IRQn = 63, /*!< 63 EFR32 EUART0_TX Interrupt */ 130 } IRQn_Type; 131 132 /**************************************************************************//** 133 * @defgroup EFR32BG22C112F352GM40_Core EFR32BG22C112F352GM40 Core 134 * @{ 135 * @brief Processor and Core Peripheral Section 136 *****************************************************************************/ 137 138 #define __CORTEXM 1U /**< Core architecture */ 139 #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ 140 #define __DSP_PRESENT 1U /**< Presence of DSP */ 141 #define __FPU_PRESENT 1U /**< Presence of FPU */ 142 #define __MPU_PRESENT 1U /**< Presence of MPU */ 143 #define __SAUREGION_PRESENT 1U /**< Presence of FPU */ 144 #define __TZ_PRESENT 1U /**< Presence of TrustZone */ 145 #define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ 146 #define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ 147 #define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ 148 149 /** @} End of group EFR32BG22C112F352GM40_Core */ 150 151 /**************************************************************************//** 152 * @defgroup EFR32BG22C112F352GM40_Part EFR32BG22C112F352GM40 Part 153 * @{ 154 ******************************************************************************/ 155 156 /** Part number */ 157 158 /* If part number is not defined as compiler option, define it */ 159 #if !defined(EFR32BG22C112F352GM40) 160 #define EFR32BG22C112F352GM40 1 /**< FULL Part */ 161 #endif 162 163 /** Configure part number */ 164 #define PART_NUMBER "EFR32BG22C112F352GM40" /**< Part Number */ 165 166 /** Family / Line / Series / Config */ 167 #define _EFR32_BLUE_FAMILY 1 /** Device Family Name Identifier */ 168 #define _EFR32_BG_FAMILY 1 /** Device Family Identifier */ 169 #define _EFR_DEVICE 1 /** Product Line Identifier */ 170 #define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ 171 #define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ 172 #define _SILICON_LABS_32B_SERIES_2_CONFIG_2 /** Product Config Identifier */ 173 #define _SILICON_LABS_32B_SERIES_2_CONFIG 2 /** Product Config Identifier */ 174 #define _SILICON_LABS_GECKO_INTERNAL_SDID 205 /** Silicon Labs internal use only */ 175 #define _SILICON_LABS_GECKO_INTERNAL_SDID_205 /** Silicon Labs internal use only */ 176 #define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ 177 #define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ 178 #define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ 179 #define _SILICON_LABS_SECURITY_FEATURE_BASE 3 /** Base Security as Series 1 */ 180 #define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_ROT /** Security feature set */ 181 #define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ 182 #define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ 183 #define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ 184 #define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ 185 #define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ 186 #define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ 187 #define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ 188 #define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ 189 #define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ 190 #define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ 191 #define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */ 192 #define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */ 193 #define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ 194 195 /** Memory Base addresses and limits */ 196 #define FLASH_MEM_BASE (0x00000000UL) /** FLASH_MEM base address */ 197 #define FLASH_MEM_SIZE (0x00080000UL) /** FLASH_MEM available address space */ 198 #define FLASH_MEM_END (0x0007FFFFUL) /** FLASH_MEM end address */ 199 #define FLASH_MEM_BITS (0x14UL) /** FLASH_MEM used bits */ 200 #define MSC_FLASH_MEM_BASE (0x00000000UL) /** MSC_FLASH_MEM base address */ 201 #define MSC_FLASH_MEM_SIZE (0x00080000UL) /** MSC_FLASH_MEM available address space */ 202 #define MSC_FLASH_MEM_END (0x0007FFFFUL) /** MSC_FLASH_MEM end address */ 203 #define MSC_FLASH_MEM_BITS (0x14UL) /** MSC_FLASH_MEM used bits */ 204 #define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ 205 #define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ 206 #define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ 207 #define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ 208 #define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ 209 #define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ 210 #define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ 211 #define USERDATA_BITS (0xBUL) /** USERDATA used bits */ 212 #define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ 213 #define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ 214 #define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ 215 #define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ 216 #define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE0E000UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ 217 #define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ 218 #define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE0E5FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ 219 #define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ 220 #define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ 221 #define DMEM_RAM0_RAM_MEM_SIZE (0x00008000UL) /** DMEM_RAM0_RAM_MEM available address space */ 222 #define DMEM_RAM0_RAM_MEM_END (0x20007FFFUL) /** DMEM_RAM0_RAM_MEM end address */ 223 #define DMEM_RAM0_RAM_MEM_BITS (0x10UL) /** DMEM_RAM0_RAM_MEM used bits */ 224 #define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ 225 #define RAM_MEM_SIZE (0x00008000UL) /** RAM_MEM available address space */ 226 #define RAM_MEM_END (0x20007FFFUL) /** RAM_MEM end address */ 227 #define RAM_MEM_BITS (0x10UL) /** RAM_MEM used bits */ 228 #define CRYPTOACC_RNGOUT_FIFO_S_MEM_BASE (0x4C024000UL) /** CRYPTOACC_RNGOUT_FIFO_S_MEM base address */ 229 #define CRYPTOACC_RNGOUT_FIFO_S_MEM_SIZE (0x00004000UL) /** CRYPTOACC_RNGOUT_FIFO_S_MEM available address space */ 230 #define CRYPTOACC_RNGOUT_FIFO_S_MEM_END (0x4C027FFFUL) /** CRYPTOACC_RNGOUT_FIFO_S_MEM end address */ 231 #define CRYPTOACC_RNGOUT_FIFO_S_MEM_BITS (0xFUL) /** CRYPTOACC_RNGOUT_FIFO_S_MEM used bits */ 232 #define CRYPTOACC_PKRAM_MAIN_S_MEM_BASE (0x4C028000UL) /** CRYPTOACC_PKRAM_MAIN_S_MEM base address */ 233 #define CRYPTOACC_PKRAM_MAIN_S_MEM_SIZE (0x00001000UL) /** CRYPTOACC_PKRAM_MAIN_S_MEM available address space */ 234 #define CRYPTOACC_PKRAM_MAIN_S_MEM_END (0x4C028FFFUL) /** CRYPTOACC_PKRAM_MAIN_S_MEM end address */ 235 #define CRYPTOACC_PKRAM_MAIN_S_MEM_BITS (0xDUL) /** CRYPTOACC_PKRAM_MAIN_S_MEM used bits */ 236 #define CRYPTOACC_RNGOUT_FIFO_MEM_BASE (0x5C024000UL) /** CRYPTOACC_RNGOUT_FIFO_MEM base address */ 237 #define CRYPTOACC_RNGOUT_FIFO_MEM_SIZE (0x00004000UL) /** CRYPTOACC_RNGOUT_FIFO_MEM available address space */ 238 #define CRYPTOACC_RNGOUT_FIFO_MEM_END (0x5C027FFFUL) /** CRYPTOACC_RNGOUT_FIFO_MEM end address */ 239 #define CRYPTOACC_RNGOUT_FIFO_MEM_BITS (0xFUL) /** CRYPTOACC_RNGOUT_FIFO_MEM used bits */ 240 #define CRYPTOACC_RNGOUT_FIFO_NS_MEM_BASE (0x5C024000UL) /** CRYPTOACC_RNGOUT_FIFO_NS_MEM base address */ 241 #define CRYPTOACC_RNGOUT_FIFO_NS_MEM_SIZE (0x00004000UL) /** CRYPTOACC_RNGOUT_FIFO_NS_MEM available address space */ 242 #define CRYPTOACC_RNGOUT_FIFO_NS_MEM_END (0x5C027FFFUL) /** CRYPTOACC_RNGOUT_FIFO_NS_MEM end address */ 243 #define CRYPTOACC_RNGOUT_FIFO_NS_MEM_BITS (0xFUL) /** CRYPTOACC_RNGOUT_FIFO_NS_MEM used bits */ 244 #define CRYPTOACC_PKRAM_MAIN_MEM_BASE (0x5C028000UL) /** CRYPTOACC_PKRAM_MAIN_MEM base address */ 245 #define CRYPTOACC_PKRAM_MAIN_MEM_SIZE (0x00001000UL) /** CRYPTOACC_PKRAM_MAIN_MEM available address space */ 246 #define CRYPTOACC_PKRAM_MAIN_MEM_END (0x5C028FFFUL) /** CRYPTOACC_PKRAM_MAIN_MEM end address */ 247 #define CRYPTOACC_PKRAM_MAIN_MEM_BITS (0xDUL) /** CRYPTOACC_PKRAM_MAIN_MEM used bits */ 248 #define CRYPTOACC_PKRAM_MAIN_NS_MEM_BASE (0x5C028000UL) /** CRYPTOACC_PKRAM_MAIN_NS_MEM base address */ 249 #define CRYPTOACC_PKRAM_MAIN_NS_MEM_SIZE (0x00001000UL) /** CRYPTOACC_PKRAM_MAIN_NS_MEM available address space */ 250 #define CRYPTOACC_PKRAM_MAIN_NS_MEM_END (0x5C028FFFUL) /** CRYPTOACC_PKRAM_MAIN_NS_MEM end address */ 251 #define CRYPTOACC_PKRAM_MAIN_NS_MEM_BITS (0xDUL) /** CRYPTOACC_PKRAM_MAIN_NS_MEM used bits */ 252 #define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ 253 #define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ 254 #define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ 255 #define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ 256 #define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ 257 #define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ 258 #define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ 259 #define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ 260 #define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ 261 #define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ 262 #define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ 263 #define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ 264 #define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ 265 #define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ 266 #define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ 267 #define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ 268 #define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ 269 #define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ 270 #define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ 271 #define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ 272 #define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ 273 #define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ 274 #define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ 275 #define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ 276 277 /** Flash and SRAM limits for EFR32BG22C112F352GM40 */ 278 #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ 279 #define FLASH_SIZE (0x00058000UL) /**< Available Flash Memory */ 280 #define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ 281 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ 282 #define SRAM_SIZE (0x00008000UL) /**< Available SRAM Memory */ 283 #define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ 284 #define EXT_IRQ_COUNT 64 /**< Number of External (NVIC) interrupts */ 285 286 /* GPIO Avalibility Info */ 287 #define GPIO_PA_INDEX 0U /**< Index of port PA */ 288 #define GPIO_PA_COUNT 9U /**< Number of pins on port PA */ 289 #define GPIO_PA_MASK (0x01FFUL) /**< Port PA pin mask */ 290 #define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ 291 #define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ 292 #define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ 293 #define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ 294 #define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ 295 #define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ 296 #define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ 297 #define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ 298 #define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ 299 #define GPIO_PB_INDEX 1U /**< Index of port PB */ 300 #define GPIO_PB_COUNT 5U /**< Number of pins on port PB */ 301 #define GPIO_PB_MASK (0x001FUL) /**< Port PB pin mask */ 302 #define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ 303 #define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ 304 #define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ 305 #define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ 306 #define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ 307 #define GPIO_PC_INDEX 2U /**< Index of port PC */ 308 #define GPIO_PC_COUNT 8U /**< Number of pins on port PC */ 309 #define GPIO_PC_MASK (0x00FFUL) /**< Port PC pin mask */ 310 #define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ 311 #define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ 312 #define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ 313 #define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ 314 #define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ 315 #define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ 316 #define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ 317 #define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ 318 #define GPIO_PD_INDEX 3U /**< Index of port PD */ 319 #define GPIO_PD_COUNT 4U /**< Number of pins on port PD */ 320 #define GPIO_PD_MASK (0x000FUL) /**< Port PD pin mask */ 321 #define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ 322 #define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ 323 #define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ 324 #define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ 325 326 /* Fixed Resource Locations */ 327 #define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ 328 #define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ 329 #define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ 330 #define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ 331 #define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ 332 #define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ 333 #define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ 334 #define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ 335 #define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ 336 #define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ 337 #define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ 338 #define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ 339 #define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ 340 #define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ 341 #define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ 342 #define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ 343 #define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ 344 #define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ 345 #define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ 346 #define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ 347 #define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ 348 #define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ 349 #define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ 350 #define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ 351 #define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ 352 #define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ 353 #define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ 354 #define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ 355 #define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ 356 #define GPIO_THMSW_EN_PIN 0U /**< Pin of THMSW_EN.*/ 357 #define IADC0_VREFP_PORT GPIO_PA_INDEX /**< Port of VREFP.*/ 358 #define IADC0_VREFP_PIN 0U /**< Pin of VREFP.*/ 359 #define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ 360 #define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ 361 #define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ 362 #define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ 363 #define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ 364 #define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ 365 366 /* Part number capabilities */ 367 #define BURAM_PRESENT /** BURAM is available in this part */ 368 #define BURAM_COUNT 1 /** 1 BURAMs available */ 369 #define BURTC_PRESENT /** BURTC is available in this part */ 370 #define BURTC_COUNT 1 /** 1 BURTCs available */ 371 #define CMU_PRESENT /** CMU is available in this part */ 372 #define CMU_COUNT 1 /** 1 CMUs available */ 373 #define CRYPTOACC_PRESENT /** CRYPTOACC is available in this part */ 374 #define CRYPTOACC_COUNT 1 /** 1 CRYPTOACCs available */ 375 #define DCDC_PRESENT /** DCDC is available in this part */ 376 #define DCDC_COUNT 1 /** 1 DCDCs available */ 377 #define DPLL_PRESENT /** DPLL is available in this part */ 378 #define DPLL_COUNT 1 /** 1 DPLLs available */ 379 #define EMU_PRESENT /** EMU is available in this part */ 380 #define EMU_COUNT 1 /** 1 EMUs available */ 381 #define EUART_PRESENT /** EUART is available in this part */ 382 #define EUART_COUNT 1 /** 1 EUARTs available */ 383 #define FSRCO_PRESENT /** FSRCO is available in this part */ 384 #define FSRCO_COUNT 1 /** 1 FSRCOs available */ 385 #define GPCRC_PRESENT /** GPCRC is available in this part */ 386 #define GPCRC_COUNT 1 /** 1 GPCRCs available */ 387 #define GPIO_PRESENT /** GPIO is available in this part */ 388 #define GPIO_COUNT 1 /** 1 GPIOs available */ 389 #define HFRCO_PRESENT /** HFRCO is available in this part */ 390 #define HFRCO_COUNT 1 /** 1 HFRCOs available */ 391 #define HFXO_PRESENT /** HFXO is available in this part */ 392 #define HFXO_COUNT 1 /** 1 HFXOs available */ 393 #define I2C_PRESENT /** I2C is available in this part */ 394 #define I2C_COUNT 2 /** 2 I2Cs available */ 395 #define IADC_PRESENT /** IADC is available in this part */ 396 #define IADC_COUNT 1 /** 1 IADCs available */ 397 #define ICACHE_PRESENT /** ICACHE is available in this part */ 398 #define ICACHE_COUNT 1 /** 1 ICACHEs available */ 399 #define LDMA_PRESENT /** LDMA is available in this part */ 400 #define LDMA_COUNT 1 /** 1 LDMAs available */ 401 #define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ 402 #define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ 403 #define LETIMER_PRESENT /** LETIMER is available in this part */ 404 #define LETIMER_COUNT 1 /** 1 LETIMERs available */ 405 #define LFRCO_PRESENT /** LFRCO is available in this part */ 406 #define LFRCO_COUNT 1 /** 1 LFRCOs available */ 407 #define LFXO_PRESENT /** LFXO is available in this part */ 408 #define LFXO_COUNT 1 /** 1 LFXOs available */ 409 #define MSC_PRESENT /** MSC is available in this part */ 410 #define MSC_COUNT 1 /** 1 MSCs available */ 411 #define PDM_PRESENT /** PDM is available in this part */ 412 #define PDM_COUNT 1 /** 1 PDMs available */ 413 #define PRORTC_PRESENT /** PRORTC is available in this part */ 414 #define PRORTC_COUNT 1 /** 1 PRORTCs available */ 415 #define PRS_PRESENT /** PRS is available in this part */ 416 #define PRS_COUNT 1 /** 1 PRSs available */ 417 #define RADIOAES_PRESENT /** RADIOAES is available in this part */ 418 #define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ 419 #define RTCC_PRESENT /** RTCC is available in this part */ 420 #define RTCC_COUNT 1 /** 1 RTCCs available */ 421 #define SMU_PRESENT /** SMU is available in this part */ 422 #define SMU_COUNT 1 /** 1 SMUs available */ 423 #define SYSCFG_PRESENT /** SYSCFG is available in this part */ 424 #define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ 425 #define TIMER_PRESENT /** TIMER is available in this part */ 426 #define TIMER_COUNT 5 /** 5 TIMERs available */ 427 #define ULFRCO_PRESENT /** ULFRCO is available in this part */ 428 #define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ 429 #define USART_PRESENT /** USART is available in this part */ 430 #define USART_COUNT 2 /** 2 USARTs available */ 431 #define WDOG_PRESENT /** WDOG is available in this part */ 432 #define WDOG_COUNT 1 /** 1 WDOGs available */ 433 #define DEVINFO_PRESENT /** DEVINFO is available in this part */ 434 #define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ 435 436 /* Include standard ARM headers for the core */ 437 #include "core_cm33.h" /* Core Header File */ 438 #include "system_efr32bg22.h" /* System Header File */ 439 440 /** @} End of group EFR32BG22C112F352GM40_Part */ 441 442 /**************************************************************************//** 443 * @defgroup EFR32BG22C112F352GM40_Peripheral_TypeDefs EFR32BG22C112F352GM40 Peripheral TypeDefs 444 * @{ 445 * @brief Device Specific Peripheral Register Structures 446 *****************************************************************************/ 447 #include "efr32bg22_emu.h" 448 #include "efr32bg22_cmu.h" 449 #include "efr32bg22_hfxo.h" 450 #include "efr32bg22_hfrco.h" 451 #include "efr32bg22_fsrco.h" 452 #include "efr32bg22_dpll.h" 453 #include "efr32bg22_lfxo.h" 454 #include "efr32bg22_lfrco.h" 455 #include "efr32bg22_ulfrco.h" 456 #include "efr32bg22_msc.h" 457 #include "efr32bg22_icache.h" 458 #include "efr32bg22_prs.h" 459 #include "efr32bg22_gpio.h" 460 #include "efr32bg22_ldma.h" 461 #include "efr32bg22_ldmaxbar.h" 462 #include "efr32bg22_timer.h" 463 #include "efr32bg22_usart.h" 464 #include "efr32bg22_burtc.h" 465 #include "efr32bg22_i2c.h" 466 #include "efr32bg22_syscfg.h" 467 #include "efr32bg22_buram.h" 468 #include "efr32bg22_gpcrc.h" 469 #include "efr32bg22_dcdc.h" 470 #include "efr32bg22_pdm.h" 471 #include "efr32bg22_aes.h" 472 #include "efr32bg22_smu.h" 473 #include "efr32bg22_rtcc.h" 474 #include "efr32bg22_letimer.h" 475 #include "efr32bg22_iadc.h" 476 #include "efr32bg22_wdog.h" 477 #include "efr32bg22_eusart.h" 478 #include "efr32bg22_cryptoacc.h" 479 #include "efr32bg22_devinfo.h" 480 481 /* Custom headers for LDMAXBAR and PRS mappings */ 482 #include "efr32bg22_prs_signals.h" 483 #include "efr32bg22_dma_descriptor.h" 484 #include "efr32bg22_ldmaxbar_defines.h" 485 486 /** @} End of group EFR32BG22C112F352GM40_Peripheral_TypeDefs */ 487 488 /**************************************************************************//** 489 * @defgroup EFR32BG22C112F352GM40_Peripheral_Base EFR32BG22C112F352GM40 Peripheral Memory Map 490 * @{ 491 *****************************************************************************/ 492 493 #define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ 494 #define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ 495 #define HFXO0_S_BASE (0x4000C000UL) /* HFXO0_S base address */ 496 #define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ 497 #define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ 498 #define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ 499 #define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ 500 #define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ 501 #define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ 502 #define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ 503 #define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ 504 #define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ 505 #define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ 506 #define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ 507 #define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ 508 #define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ 509 #define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ 510 #define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ 511 #define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ 512 #define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ 513 #define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ 514 #define USART1_S_BASE (0x40060000UL) /* USART1_S base address */ 515 #define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ 516 #define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ 517 #define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ 518 #define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ 519 #define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ 520 #define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ 521 #define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ 522 #define PDM_S_BASE (0x40098000UL) /* PDM_S base address */ 523 #define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ 524 #define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ 525 #define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ 526 #define RTCC_S_BASE (0x48000000UL) /* RTCC_S base address */ 527 #define LETIMER0_S_BASE (0x4A000000UL) /* LETIMER0_S base address */ 528 #define IADC0_S_BASE (0x4A004000UL) /* IADC0_S base address */ 529 #define I2C0_S_BASE (0x4A010000UL) /* I2C0_S base address */ 530 #define WDOG0_S_BASE (0x4A018000UL) /* WDOG0_S base address */ 531 #define EUART0_S_BASE (0x4A030000UL) /* EUART0_S base address */ 532 #define CRYPTOACC_S_BASE (0x4C020000UL) /* CRYPTOACC_S base address */ 533 #define CRYPTOACC_S_RNGCTRL_BASE (0x4C021000UL) /* CRYPTOACC_S_RNGCTRL base address */ 534 #define CRYPTOACC_S_PKCTRL_BASE (0x4C022000UL) /* CRYPTOACC_S_PKCTRL base address */ 535 #define PRORTC_S_BASE (0xA8000000UL) /* PRORTC_S base address */ 536 #define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ 537 #define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ 538 #define HFXO0_NS_BASE (0x5000C000UL) /* HFXO0_NS base address */ 539 #define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ 540 #define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ 541 #define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ 542 #define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ 543 #define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ 544 #define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ 545 #define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ 546 #define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ 547 #define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ 548 #define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ 549 #define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ 550 #define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ 551 #define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ 552 #define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ 553 #define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ 554 #define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ 555 #define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ 556 #define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ 557 #define USART1_NS_BASE (0x50060000UL) /* USART1_NS base address */ 558 #define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ 559 #define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ 560 #define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ 561 #define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ 562 #define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ 563 #define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ 564 #define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ 565 #define PDM_NS_BASE (0x50098000UL) /* PDM_NS base address */ 566 #define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ 567 #define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ 568 #define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ 569 #define RTCC_NS_BASE (0x58000000UL) /* RTCC_NS base address */ 570 #define LETIMER0_NS_BASE (0x5A000000UL) /* LETIMER0_NS base address */ 571 #define IADC0_NS_BASE (0x5A004000UL) /* IADC0_NS base address */ 572 #define I2C0_NS_BASE (0x5A010000UL) /* I2C0_NS base address */ 573 #define WDOG0_NS_BASE (0x5A018000UL) /* WDOG0_NS base address */ 574 #define EUART0_NS_BASE (0x5A030000UL) /* EUART0_NS base address */ 575 #define CRYPTOACC_NS_BASE (0x5C020000UL) /* CRYPTOACC_NS base address */ 576 #define CRYPTOACC_NS_RNGCTRL_BASE (0x5C021000UL) /* CRYPTOACC_NS_RNGCTRL base address */ 577 #define CRYPTOACC_NS_PKCTRL_BASE (0x5C022000UL) /* CRYPTOACC_NS_PKCTRL base address */ 578 #define PRORTC_NS_BASE (0xB8000000UL) /* PRORTC_NS base address */ 579 580 #if defined(SL_COMPONENT_CATALOG_PRESENT) 581 #include "sl_component_catalog.h" 582 583 #endif 584 #if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) 585 #include "sl_trustzone_secure_config.h" 586 587 #endif 588 589 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) 590 #define EMU_BASE (EMU_S_BASE) /* EMU base address */ 591 #else 592 #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ 593 #endif // SL_TRUSTZONE_PERIPHERAL_EMU_S 594 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) 595 #define CMU_BASE (CMU_S_BASE) /* CMU base address */ 596 #else 597 #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ 598 #endif // SL_TRUSTZONE_PERIPHERAL_CMU_S 599 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) 600 #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ 601 #else 602 #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ 603 #endif // SL_TRUSTZONE_PERIPHERAL_HFXO0_S 604 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) 605 #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ 606 #else 607 #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ 608 #endif // SL_TRUSTZONE_PERIPHERAL_HFRCO0_S 609 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) 610 #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ 611 #else 612 #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ 613 #endif // SL_TRUSTZONE_PERIPHERAL_FSRCO_S 614 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) 615 #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ 616 #else 617 #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ 618 #endif // SL_TRUSTZONE_PERIPHERAL_DPLL0_S 619 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) 620 #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ 621 #else 622 #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ 623 #endif // SL_TRUSTZONE_PERIPHERAL_LFXO_S 624 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) 625 #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ 626 #else 627 #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ 628 #endif // SL_TRUSTZONE_PERIPHERAL_LFRCO_S 629 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) 630 #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ 631 #else 632 #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ 633 #endif // SL_TRUSTZONE_PERIPHERAL_ULFRCO_S 634 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) 635 #define MSC_BASE (MSC_S_BASE) /* MSC base address */ 636 #else 637 #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ 638 #endif // SL_TRUSTZONE_PERIPHERAL_MSC_S 639 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) 640 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ 641 #else 642 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ 643 #endif // SL_TRUSTZONE_PERIPHERAL_ICACHE0_S 644 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) 645 #define PRS_BASE (PRS_S_BASE) /* PRS base address */ 646 #else 647 #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ 648 #endif // SL_TRUSTZONE_PERIPHERAL_PRS_S 649 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) 650 #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ 651 #else 652 #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ 653 #endif // SL_TRUSTZONE_PERIPHERAL_GPIO_S 654 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) 655 #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ 656 #else 657 #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ 658 #endif // SL_TRUSTZONE_PERIPHERAL_LDMA_S 659 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) 660 #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ 661 #else 662 #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ 663 #endif // SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S 664 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) 665 #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ 666 #else 667 #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ 668 #endif // SL_TRUSTZONE_PERIPHERAL_TIMER0_S 669 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) 670 #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ 671 #else 672 #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ 673 #endif // SL_TRUSTZONE_PERIPHERAL_TIMER1_S 674 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) 675 #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ 676 #else 677 #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ 678 #endif // SL_TRUSTZONE_PERIPHERAL_TIMER2_S 679 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) 680 #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ 681 #else 682 #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ 683 #endif // SL_TRUSTZONE_PERIPHERAL_TIMER3_S 684 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) 685 #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ 686 #else 687 #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ 688 #endif // SL_TRUSTZONE_PERIPHERAL_TIMER4_S 689 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) 690 #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ 691 #else 692 #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ 693 #endif // SL_TRUSTZONE_PERIPHERAL_USART0_S 694 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) 695 #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ 696 #else 697 #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ 698 #endif // SL_TRUSTZONE_PERIPHERAL_USART1_S 699 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) 700 #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ 701 #else 702 #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ 703 #endif // SL_TRUSTZONE_PERIPHERAL_BURTC_S 704 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) 705 #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ 706 #else 707 #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ 708 #endif // SL_TRUSTZONE_PERIPHERAL_I2C1_S 709 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) 710 #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ 711 #else 712 #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ 713 #endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S 714 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) 715 #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ 716 #else 717 #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ 718 #endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_S 719 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) 720 #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ 721 #else 722 #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ 723 #endif // SL_TRUSTZONE_PERIPHERAL_BURAM_S 724 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) 725 #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ 726 #else 727 #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ 728 #endif // SL_TRUSTZONE_PERIPHERAL_GPCRC_S 729 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) 730 #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ 731 #else 732 #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ 733 #endif // SL_TRUSTZONE_PERIPHERAL_DCDC_S 734 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) 735 #define PDM_BASE (PDM_S_BASE) /* PDM base address */ 736 #else 737 #define PDM_BASE (PDM_NS_BASE) /* PDM base address */ 738 #endif // SL_TRUSTZONE_PERIPHERAL_PDM_S 739 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) 740 #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ 741 #else 742 #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ 743 #endif // SL_TRUSTZONE_PERIPHERAL_RADIOAES_S 744 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) 745 #define SMU_BASE (SMU_S_BASE) /* SMU base address */ 746 #else 747 #define SMU_BASE (SMU_S_BASE) /* SMU base address */ 748 #endif // SL_TRUSTZONE_PERIPHERAL_SMU_S 749 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) 750 #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ 751 #else 752 #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ 753 #endif // SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S 754 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) 755 #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ 756 #else 757 #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ 758 #endif // SL_TRUSTZONE_PERIPHERAL_RTCC_S 759 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) 760 #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ 761 #else 762 #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ 763 #endif // SL_TRUSTZONE_PERIPHERAL_LETIMER0_S 764 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) 765 #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ 766 #else 767 #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ 768 #endif // SL_TRUSTZONE_PERIPHERAL_IADC0_S 769 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) 770 #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ 771 #else 772 #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ 773 #endif // SL_TRUSTZONE_PERIPHERAL_I2C0_S 774 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) 775 #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ 776 #else 777 #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ 778 #endif // SL_TRUSTZONE_PERIPHERAL_WDOG0_S 779 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUART0_S != 0))) 780 #define EUART0_BASE (EUART0_S_BASE) /* EUART0 base address */ 781 #else 782 #define EUART0_BASE (EUART0_NS_BASE) /* EUART0 base address */ 783 #endif // SL_TRUSTZONE_PERIPHERAL_EUART0_S 784 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S != 0))) 785 #define CRYPTOACC_BASE (CRYPTOACC_S_BASE) /* CRYPTOACC base address */ 786 #else 787 #define CRYPTOACC_BASE (CRYPTOACC_NS_BASE) /* CRYPTOACC base address */ 788 #endif // SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S 789 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S != 0))) 790 #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_S_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ 791 #else 792 #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_NS_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ 793 #endif // SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S 794 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S != 0))) 795 #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_S_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ 796 #else 797 #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_NS_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ 798 #endif // SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S 799 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) 800 #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ 801 #else 802 #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ 803 #endif // SL_TRUSTZONE_PERIPHERAL_PRORTC_S 804 805 #define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ 806 /** @} End of group EFR32BG22C112F352GM40_Peripheral_Base */ 807 808 /**************************************************************************//** 809 * @defgroup EFR32BG22C112F352GM40_Peripheral_Declaration EFR32BG22C112F352GM40 Peripheral Declarations Map 810 * @{ 811 *****************************************************************************/ 812 813 #define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ 814 #define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ 815 #define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ 816 #define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ 817 #define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ 818 #define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ 819 #define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ 820 #define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ 821 #define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ 822 #define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ 823 #define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ 824 #define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ 825 #define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ 826 #define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ 827 #define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ 828 #define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ 829 #define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ 830 #define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ 831 #define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ 832 #define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ 833 #define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ 834 #define USART1_S ((USART_TypeDef *) USART1_S_BASE) /**< USART1_S base pointer */ 835 #define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ 836 #define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ 837 #define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ 838 #define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ 839 #define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ 840 #define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ 841 #define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ 842 #define PDM_S ((PDM_TypeDef *) PDM_S_BASE) /**< PDM_S base pointer */ 843 #define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ 844 #define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ 845 #define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ 846 #define RTCC_S ((RTCC_TypeDef *) RTCC_S_BASE) /**< RTCC_S base pointer */ 847 #define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ 848 #define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ 849 #define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ 850 #define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ 851 #define EUART0_S ((EUSART_TypeDef *) EUART0_S_BASE) /**< EUART0_S base pointer */ 852 #define CRYPTOACC_S ((CRYPTOACC_TypeDef *) CRYPTOACC_S_BASE) /**< CRYPTOACC_S base pointer */ 853 #define CRYPTOACC_S_RNGCTRL ((CRYPTOACC_RNGCTRL_TypeDef *) CRYPTOACC_S_RNGCTRL_BASE) /**< CRYPTOACC_S_RNGCTRL base pointer */ 854 #define CRYPTOACC_S_PKCTRL ((CRYPTOACC_PKCTRL_TypeDef *) CRYPTOACC_S_PKCTRL_BASE) /**< CRYPTOACC_S_PKCTRL base pointer */ 855 #define PRORTC_S ((RTCC_TypeDef *) PRORTC_S_BASE) /**< PRORTC_S base pointer */ 856 #define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ 857 #define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ 858 #define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ 859 #define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ 860 #define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ 861 #define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ 862 #define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ 863 #define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ 864 #define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ 865 #define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ 866 #define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ 867 #define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ 868 #define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ 869 #define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ 870 #define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ 871 #define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ 872 #define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ 873 #define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ 874 #define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ 875 #define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ 876 #define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ 877 #define USART1_NS ((USART_TypeDef *) USART1_NS_BASE) /**< USART1_NS base pointer */ 878 #define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ 879 #define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ 880 #define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ 881 #define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ 882 #define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ 883 #define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ 884 #define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ 885 #define PDM_NS ((PDM_TypeDef *) PDM_NS_BASE) /**< PDM_NS base pointer */ 886 #define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ 887 #define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ 888 #define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ 889 #define RTCC_NS ((RTCC_TypeDef *) RTCC_NS_BASE) /**< RTCC_NS base pointer */ 890 #define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ 891 #define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ 892 #define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ 893 #define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ 894 #define EUART0_NS ((EUSART_TypeDef *) EUART0_NS_BASE) /**< EUART0_NS base pointer */ 895 #define CRYPTOACC_NS ((CRYPTOACC_TypeDef *) CRYPTOACC_NS_BASE) /**< CRYPTOACC_NS base pointer */ 896 #define CRYPTOACC_NS_RNGCTRL ((CRYPTOACC_RNGCTRL_TypeDef *) CRYPTOACC_NS_RNGCTRL_BASE) /**< CRYPTOACC_NS_RNGCTRL base pointer */ 897 #define CRYPTOACC_NS_PKCTRL ((CRYPTOACC_PKCTRL_TypeDef *) CRYPTOACC_NS_PKCTRL_BASE) /**< CRYPTOACC_NS_PKCTRL base pointer */ 898 #define PRORTC_NS ((RTCC_TypeDef *) PRORTC_NS_BASE) /**< PRORTC_NS base pointer */ 899 #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ 900 #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ 901 #define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ 902 #define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ 903 #define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ 904 #define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ 905 #define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ 906 #define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ 907 #define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ 908 #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ 909 #define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ 910 #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ 911 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ 912 #define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ 913 #define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ 914 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ 915 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ 916 #define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ 917 #define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ 918 #define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ 919 #define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ 920 #define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ 921 #define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ 922 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ 923 #define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ 924 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ 925 #define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ 926 #define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ 927 #define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ 928 #define PDM ((PDM_TypeDef *) PDM_BASE) /**< PDM base pointer */ 929 #define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ 930 #define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ 931 #define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ 932 #define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ 933 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ 934 #define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ 935 #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ 936 #define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ 937 #define EUART0 ((EUSART_TypeDef *) EUART0_BASE) /**< EUART0 base pointer */ 938 #define CRYPTOACC ((CRYPTOACC_TypeDef *) CRYPTOACC_BASE) /**< CRYPTOACC base pointer */ 939 #define CRYPTOACC_RNGCTRL ((CRYPTOACC_RNGCTRL_TypeDef *) CRYPTOACC_RNGCTRL_BASE) /**< CRYPTOACC_RNGCTRL base pointer */ 940 #define CRYPTOACC_PKCTRL ((CRYPTOACC_PKCTRL_TypeDef *) CRYPTOACC_PKCTRL_BASE) /**< CRYPTOACC_PKCTRL base pointer */ 941 #define PRORTC ((RTCC_TypeDef *) PRORTC_BASE) /**< PRORTC base pointer */ 942 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ 943 /** @} End of group EFR32BG22C112F352GM40_Peripheral_Declaration */ 944 945 /**************************************************************************//** 946 * @defgroup EFR32BG22C112F352GM40_Peripheral_Parameters EFR32BG22C112F352GM40 Peripheral Parameters 947 * @{ 948 * @brief Device peripheral parameter values 949 *****************************************************************************/ 950 951 /* Common peripheral register block offsets. */ 952 #define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ 953 #define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ 954 #define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ 955 #define MSC_CDA_PRESENT 0x1UL /**> */ 956 #define MSC_FDIO_WIDTH 0x40UL /**> None */ 957 #define MSC_FLASHADDRBITS 0x13UL /**> None */ 958 #define MSC_FLASHBLOCKADDRBITS 0x13UL /**> None */ 959 #define MSC_FLASH_BLOCK_INFO_PCOUNT 0xCUL /**> None */ 960 #define MSC_INFOADDRBITS 0x10UL /**> None */ 961 #define MSC_INFOBLOCKADDRBITS 0x10UL /**> None */ 962 #define MSC_INFO_PSIZE_BITS 0xCUL /**> None */ 963 #define MSC_MAIN_PSIZE_BITS 0xCUL /**> None */ 964 #define MSC_MTP_PRESENT 0x1UL /**> */ 965 #define MSC_REDUNDANCY 0x2UL /**> None */ 966 #define MSC_UD_IN_MTP_PAGE 0x0UL /**> */ 967 #define MSC_YADDRBITS 0x6UL /**> */ 968 #define SYSROM_WORDS 0x700UL /**> Number of words in ROM */ 969 #define SYSROM_ROM_SIZE_BYTES 0x1C00UL /**> Number of bytes in ROM */ 970 #define DMEM_BANK0_SIZE 0x6000UL /**> Bank0 Size */ 971 #define DMEM_BANK1_SIZE 0x2000UL /**> Bank1 Size */ 972 #define DMEM_BANK2_SIZE 0x0UL /**> Bank2 Size */ 973 #define DMEM_BANK3_SIZE 0x0UL /**> Bank3 Size */ 974 #define DMEM_BANK4_SIZE 0x0UL /**> Bank4 Size */ 975 #define DMEM_BANK5_SIZE 0x0UL /**> Bank5 Size */ 976 #define DMEM_BANK6_SIZE 0x0UL /**> Bank6 Size */ 977 #define DMEM_BANK7_SIZE 0x0UL /**> Bank7 Size */ 978 #define DMEM_NUM_BANKS 0x2UL /**> Number of Banks */ 979 #define DMEM_SIZE 0x8000UL /**> Total size */ 980 #define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ 981 #define LFXO_CTUNE 0x1UL /**> CTUNE Present */ 982 #define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ 983 #define ICACHE0_CACHEABLE_SIZE 0x200UL /**> Cache Size */ 984 #define ICACHE0_CACHEABLE_START 0x12UL /**> Cache Start */ 985 #define ICACHE0_DEFAULT_OFF 0x1UL /**> Default off */ 986 #define ICACHE0_FLASH_SIZE 0x80000UL /**> Flash size */ 987 #define ICACHE0_FLASH_START 0x0UL /**> Flash start */ 988 #define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ 989 #define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ 990 #define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ 991 #define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ 992 #define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ 993 #define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ 994 #define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ 995 #define ICACHE0_SET_BITS 0x5UL /**> Set bits */ 996 #define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ 997 #define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ 998 #define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ 999 #define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ 1000 #define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ 1001 #define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ 1002 #define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ 1003 #define PRS_ASYNC_CH_NUM 0xCUL /**> None */ 1004 #define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ 1005 #define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ 1006 #define PRS_SYNC_CH_NUM 0x4UL /**> None */ 1007 #define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ 1008 #define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ 1009 #define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ 1010 #define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ 1011 #define GPIO_NUM_EVEN_PC 0x4UL /**> Num of even pins port C */ 1012 #define GPIO_NUM_EVEN_PD 0x2UL /**> Num of even pins port D */ 1013 #define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ 1014 #define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ 1015 #define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ 1016 #define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ 1017 #define GPIO_NUM_ODD_PA 0x4UL /**> Num of odd pins port A */ 1018 #define GPIO_NUM_ODD_PB 0x2UL /**> Num of odd pins port B */ 1019 #define GPIO_NUM_ODD_PC 0x4UL /**> Num of odd pins port C */ 1020 #define GPIO_NUM_ODD_PD 0x2UL /**> Num of odd pins port D */ 1021 #define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ 1022 #define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ 1023 #define GPIO_PORT_A_WIDTH 0x9UL /**> Port A Width */ 1024 #define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ 1025 #define GPIO_PORT_A_WL 0x8UL /**> New Param */ 1026 #define GPIO_PORT_A_WU 0x1UL /**> New Param */ 1027 #define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ 1028 #define GPIO_PORT_B_WIDTH 0x5UL /**> Port B Width */ 1029 #define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ 1030 #define GPIO_PORT_B_WL 0x5UL /**> New Param */ 1031 #define GPIO_PORT_B_WU 0x0UL /**> New Param */ 1032 #define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ 1033 #define GPIO_PORT_C_WIDTH 0x8UL /**> Port C Width */ 1034 #define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ 1035 #define GPIO_PORT_C_WL 0x8UL /**> New Param */ 1036 #define GPIO_PORT_C_WU 0x0UL /**> New Param */ 1037 #define GPIO_PORT_C_WU_ZERO 0x1UL /**> New Param */ 1038 #define GPIO_PORT_D_WIDTH 0x4UL /**> Port D Width */ 1039 #define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ 1040 #define GPIO_PORT_D_WL 0x4UL /**> New Param */ 1041 #define GPIO_PORT_D_WU 0x0UL /**> New Param */ 1042 #define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ 1043 #define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ 1044 #define LDMA_CH_BITS 0x5UL /**> New Param */ 1045 #define LDMA_CH_NUM 0x8UL /**> New Param */ 1046 #define LDMA_FIFO_BITS 0x5UL /**> New Param */ 1047 #define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ 1048 #define LDMAXBAR_CH_BITS 0x5UL /**> None */ 1049 #define LDMAXBAR_CH_NUM 0x8UL /**> None */ 1050 #define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ 1051 #define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ 1052 #define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ 1053 #define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ 1054 #define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ 1055 #define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ 1056 #define TIMER0_NO_DTI 0x0UL /**> */ 1057 #define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ 1058 #define TIMER1_CNTWIDTH 0x10UL /**> Counter Width */ 1059 #define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ 1060 #define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ 1061 #define TIMER1_NO_DTI 0x0UL /**> */ 1062 #define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ 1063 #define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ 1064 #define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ 1065 #define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ 1066 #define TIMER2_NO_DTI 0x0UL /**> */ 1067 #define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ 1068 #define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ 1069 #define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ 1070 #define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ 1071 #define TIMER3_NO_DTI 0x0UL /**> */ 1072 #define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ 1073 #define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ 1074 #define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ 1075 #define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ 1076 #define TIMER4_NO_DTI 0x0UL /**> */ 1077 #define USART0_AUTOTX_REG 0x1UL /**> None */ 1078 #define USART0_AUTOTX_REG_B 0x0UL /**> None */ 1079 #define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ 1080 #define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ 1081 #define USART0_CLK_PRS 0x1UL /**> None */ 1082 #define USART0_CLK_PRS_B 0x0UL /**> New Param */ 1083 #define USART0_FLOW_CONTROL 0x1UL /**> None */ 1084 #define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ 1085 #define USART0_I2S 0x1UL /**> None */ 1086 #define USART0_I2S_B 0x0UL /**> New Param */ 1087 #define USART0_IRDA_AVAILABLE 0x1UL /**> None */ 1088 #define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ 1089 #define USART0_MVDIS_FUNC 0x1UL /**> None */ 1090 #define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ 1091 #define USART0_RX_PRS 0x1UL /**> None */ 1092 #define USART0_RX_PRS_B 0x0UL /**> New Param */ 1093 #define USART0_SC_AVAILABLE 0x1UL /**> None */ 1094 #define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ 1095 #define USART0_SYNC_AVAILABLE 0x1UL /**> None */ 1096 #define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ 1097 #define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ 1098 #define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ 1099 #define USART0_TIMER 0x1UL /**> New Param */ 1100 #define USART0_TIMER_B 0x0UL /**> New Param */ 1101 #define USART1_AUTOTX_REG 0x1UL /**> None */ 1102 #define USART1_AUTOTX_REG_B 0x0UL /**> None */ 1103 #define USART1_AUTOTX_TRIGGER 0x1UL /**> None */ 1104 #define USART1_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ 1105 #define USART1_CLK_PRS 0x1UL /**> None */ 1106 #define USART1_CLK_PRS_B 0x0UL /**> New Param */ 1107 #define USART1_FLOW_CONTROL 0x1UL /**> None */ 1108 #define USART1_FLOW_CONTROL_B 0x0UL /**> New Param */ 1109 #define USART1_I2S 0x1UL /**> None */ 1110 #define USART1_I2S_B 0x0UL /**> New Param */ 1111 #define USART1_IRDA_AVAILABLE 0x1UL /**> None */ 1112 #define USART1_IRDA_AVAILABLE_B 0x0UL /**> New Param */ 1113 #define USART1_MVDIS_FUNC 0x1UL /**> None */ 1114 #define USART1_MVDIS_FUNC_B 0x0UL /**> New Param */ 1115 #define USART1_RX_PRS 0x1UL /**> None */ 1116 #define USART1_RX_PRS_B 0x0UL /**> New Param */ 1117 #define USART1_SC_AVAILABLE 0x1UL /**> None */ 1118 #define USART1_SC_AVAILABLE_B 0x0UL /**> New Param */ 1119 #define USART1_SYNC_AVAILABLE 0x1UL /**> None */ 1120 #define USART1_SYNC_AVAILABLE_B 0x0UL /**> New Param */ 1121 #define USART1_SYNC_LATE_SAMPLE 0x1UL /**> None */ 1122 #define USART1_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ 1123 #define USART1_TIMER 0x1UL /**> New Param */ 1124 #define USART1_TIMER_B 0x0UL /**> New Param */ 1125 #define BURTC_CNTWIDTH 0x20UL /**> None */ 1126 #define BURTC_PRECNT_WIDTH 0xFUL /**> */ 1127 #define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ 1128 #define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ 1129 #define SYSCFG_CHIP_FAMILY 0x34UL /**> CHIP Family */ 1130 #define SYSCFG_DEMODRAM_INST_COUNT 0x1UL /**> */ 1131 #define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ 1132 #define SYSCFG_RAM0_INST_COUNT 0x2UL /**> None */ 1133 #define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ 1134 #define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ 1135 #define DCDC_DCDCMODE_WIDTH 0x1UL /**> Mode register width */ 1136 #define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ 1137 #define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ 1138 #define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ 1139 #define PDM_FIFO_LEN 0x4UL /**> New Param */ 1140 #define PDM_NUM_CH 0x2UL /**> None */ 1141 #define PDM_CH2_PRESENT_B 0x1UL /**> New Param */ 1142 #define PDM_CH3_PRESENT_B 0x1UL /**> New Param */ 1143 #define PDM_NUM_CH_WIDTH 0x1UL /**> New Param */ 1144 #define PDM_PIPELINE 0x0UL /**> None */ 1145 #define PDM_STEREO23_PRESENT_B 0x1UL /**> New Param */ 1146 #define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x0UL /**> Enable sidechannel counter measures */ 1147 #define SMU_NUM_BMPUS 0x5UL /**> Number of BMPUs */ 1148 #define SMU_NUM_PPU_PERIPHS 0x30UL /**> Number of PPU Peripherals */ 1149 #define SMU_NUM_PPU_PERIPHS_MOD_32 0x10UL /**> Number of PPU Peripherals (mod 32) */ 1150 #define SMU_NUM_PPU_PERIPHS_SUB_32 0x10UL /**> Number of PPU peripherals minus 32 */ 1151 #define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ 1152 #define RTCC_CC_NUM 0x3UL /**> None */ 1153 #define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ 1154 #define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ 1155 #define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ 1156 #define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ 1157 #define IADC0_ENTRIES 0x10UL /**> ENTRIES */ 1158 #define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ 1159 #define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ 1160 #define WDOG0_PCNUM 0x2UL /**> None */ 1161 #define EUART0_USE_AS_LEUART 0x1UL /**> LEUART instace */ 1162 #define EUART0_USE_AS_UART 0x0UL /**> UART instance */ 1163 #define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ 1164 #define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ 1165 #define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ 1166 #define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ 1167 #define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ 1168 #define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ 1169 #define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ 1170 #define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ 1171 #define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ 1172 #define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ 1173 #define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ 1174 #define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ 1175 #define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ 1176 #define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ 1177 #define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ 1178 #define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ 1179 #define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ 1180 #define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ 1181 #define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ 1182 #define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ 1183 #define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ 1184 #define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ 1185 #define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ 1186 #define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ 1187 #define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ 1188 #define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ 1189 #define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ 1190 #define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ 1191 #define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ 1192 #define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ 1193 #define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ 1194 #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ 1195 #define PRORTC_CC_NUM 0x2UL /**> None */ 1196 1197 /* Instance macros for I2C */ 1198 #define I2C(n) (((n) == 0) ? I2C0 \ 1199 : ((n) == 1) ? I2C1 \ 1200 : 0x0UL) 1201 #define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ 1202 : ((ref) == I2C1) ? 1 \ 1203 : -1) 1204 #define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ 1205 : ((n) == 1) ? I2C1_DELAY \ 1206 : 0x0UL) 1207 #define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ 1208 : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ 1209 : 0x0UL) 1210 1211 /* Instance macros for TIMER */ 1212 #define TIMER(n) (((n) == 0) ? TIMER0 \ 1213 : ((n) == 1) ? TIMER1 \ 1214 : ((n) == 2) ? TIMER2 \ 1215 : ((n) == 3) ? TIMER3 \ 1216 : ((n) == 4) ? TIMER4 \ 1217 : 0x0UL) 1218 #define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ 1219 : ((ref) == TIMER1) ? 1 \ 1220 : ((ref) == TIMER2) ? 2 \ 1221 : ((ref) == TIMER3) ? 3 \ 1222 : ((ref) == TIMER4) ? 4 \ 1223 : -1) 1224 #define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ 1225 : ((n) == 1) ? TIMER1_CC_NUM \ 1226 : ((n) == 2) ? TIMER2_CC_NUM \ 1227 : ((n) == 3) ? TIMER3_CC_NUM \ 1228 : ((n) == 4) ? TIMER4_CC_NUM \ 1229 : 0x0UL) 1230 #define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ 1231 : ((n) == 1) ? TIMER1_CNTWIDTH \ 1232 : ((n) == 2) ? TIMER2_CNTWIDTH \ 1233 : ((n) == 3) ? TIMER3_CNTWIDTH \ 1234 : ((n) == 4) ? TIMER4_CNTWIDTH \ 1235 : 0x0UL) 1236 #define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ 1237 : ((n) == 1) ? TIMER1_DTI \ 1238 : ((n) == 2) ? TIMER2_DTI \ 1239 : ((n) == 3) ? TIMER3_DTI \ 1240 : ((n) == 4) ? TIMER4_DTI \ 1241 : 0x0UL) 1242 #define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ 1243 : ((n) == 1) ? TIMER1_DTI_CC_NUM \ 1244 : ((n) == 2) ? TIMER2_DTI_CC_NUM \ 1245 : ((n) == 3) ? TIMER3_DTI_CC_NUM \ 1246 : ((n) == 4) ? TIMER4_DTI_CC_NUM \ 1247 : 0x0UL) 1248 #define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ 1249 : ((n) == 1) ? TIMER1_NO_DTI \ 1250 : ((n) == 2) ? TIMER2_NO_DTI \ 1251 : ((n) == 3) ? TIMER3_NO_DTI \ 1252 : ((n) == 4) ? TIMER4_NO_DTI \ 1253 : 0x0UL) 1254 1255 /* Instance macros for USART */ 1256 #define USART(n) (((n) == 0) ? USART0 \ 1257 : ((n) == 1) ? USART1 \ 1258 : 0x0UL) 1259 #define USART_NUM(ref) (((ref) == USART0) ? 0 \ 1260 : ((ref) == USART1) ? 1 \ 1261 : -1) 1262 #define USART_AUTOTX_REG(n) (((n) == 0) ? USART0_AUTOTX_REG \ 1263 : ((n) == 1) ? USART1_AUTOTX_REG \ 1264 : 0x0UL) 1265 #define USART_AUTOTX_REG_B(n) (((n) == 0) ? USART0_AUTOTX_REG_B \ 1266 : ((n) == 1) ? USART1_AUTOTX_REG_B \ 1267 : 0x0UL) 1268 #define USART_AUTOTX_TRIGGER(n) (((n) == 0) ? USART0_AUTOTX_TRIGGER \ 1269 : ((n) == 1) ? USART1_AUTOTX_TRIGGER \ 1270 : 0x0UL) 1271 #define USART_AUTOTX_TRIGGER_B(n) (((n) == 0) ? USART0_AUTOTX_TRIGGER_B \ 1272 : ((n) == 1) ? USART1_AUTOTX_TRIGGER_B \ 1273 : 0x0UL) 1274 #define USART_CLK_PRS(n) (((n) == 0) ? USART0_CLK_PRS \ 1275 : ((n) == 1) ? USART1_CLK_PRS \ 1276 : 0x0UL) 1277 #define USART_CLK_PRS_B(n) (((n) == 0) ? USART0_CLK_PRS_B \ 1278 : ((n) == 1) ? USART1_CLK_PRS_B \ 1279 : 0x0UL) 1280 #define USART_FLOW_CONTROL(n) (((n) == 0) ? USART0_FLOW_CONTROL \ 1281 : ((n) == 1) ? USART1_FLOW_CONTROL \ 1282 : 0x0UL) 1283 #define USART_FLOW_CONTROL_B(n) (((n) == 0) ? USART0_FLOW_CONTROL_B \ 1284 : ((n) == 1) ? USART1_FLOW_CONTROL_B \ 1285 : 0x0UL) 1286 #define USART_I2S(n) (((n) == 0) ? USART0_I2S \ 1287 : ((n) == 1) ? USART1_I2S \ 1288 : 0x0UL) 1289 #define USART_I2S_B(n) (((n) == 0) ? USART0_I2S_B \ 1290 : ((n) == 1) ? USART1_I2S_B \ 1291 : 0x0UL) 1292 #define USART_IRDA_AVAILABLE(n) (((n) == 0) ? USART0_IRDA_AVAILABLE \ 1293 : ((n) == 1) ? USART1_IRDA_AVAILABLE \ 1294 : 0x0UL) 1295 #define USART_IRDA_AVAILABLE_B(n) (((n) == 0) ? USART0_IRDA_AVAILABLE_B \ 1296 : ((n) == 1) ? USART1_IRDA_AVAILABLE_B \ 1297 : 0x0UL) 1298 #define USART_MVDIS_FUNC(n) (((n) == 0) ? USART0_MVDIS_FUNC \ 1299 : ((n) == 1) ? USART1_MVDIS_FUNC \ 1300 : 0x0UL) 1301 #define USART_MVDIS_FUNC_B(n) (((n) == 0) ? USART0_MVDIS_FUNC_B \ 1302 : ((n) == 1) ? USART1_MVDIS_FUNC_B \ 1303 : 0x0UL) 1304 #define USART_RX_PRS(n) (((n) == 0) ? USART0_RX_PRS \ 1305 : ((n) == 1) ? USART1_RX_PRS \ 1306 : 0x0UL) 1307 #define USART_RX_PRS_B(n) (((n) == 0) ? USART0_RX_PRS_B \ 1308 : ((n) == 1) ? USART1_RX_PRS_B \ 1309 : 0x0UL) 1310 #define USART_SC_AVAILABLE(n) (((n) == 0) ? USART0_SC_AVAILABLE \ 1311 : ((n) == 1) ? USART1_SC_AVAILABLE \ 1312 : 0x0UL) 1313 #define USART_SC_AVAILABLE_B(n) (((n) == 0) ? USART0_SC_AVAILABLE_B \ 1314 : ((n) == 1) ? USART1_SC_AVAILABLE_B \ 1315 : 0x0UL) 1316 #define USART_SYNC_AVAILABLE(n) (((n) == 0) ? USART0_SYNC_AVAILABLE \ 1317 : ((n) == 1) ? USART1_SYNC_AVAILABLE \ 1318 : 0x0UL) 1319 #define USART_SYNC_AVAILABLE_B(n) (((n) == 0) ? USART0_SYNC_AVAILABLE_B \ 1320 : ((n) == 1) ? USART1_SYNC_AVAILABLE_B \ 1321 : 0x0UL) 1322 #define USART_SYNC_LATE_SAMPLE(n) (((n) == 0) ? USART0_SYNC_LATE_SAMPLE \ 1323 : ((n) == 1) ? USART1_SYNC_LATE_SAMPLE \ 1324 : 0x0UL) 1325 #define USART_SYNC_LATE_SAMPLE_B(n) (((n) == 0) ? USART0_SYNC_LATE_SAMPLE_B \ 1326 : ((n) == 1) ? USART1_SYNC_LATE_SAMPLE_B \ 1327 : 0x0UL) 1328 #define USART_TIMER(n) (((n) == 0) ? USART0_TIMER \ 1329 : ((n) == 1) ? USART1_TIMER \ 1330 : 0x0UL) 1331 #define USART_TIMER_B(n) (((n) == 0) ? USART0_TIMER_B \ 1332 : ((n) == 1) ? USART1_TIMER_B \ 1333 : 0x0UL) 1334 1335 /** @} End of group EFR32BG22C112F352GM40_Peripheral_Parameters */ 1336 1337 /** @} End of group EFR32BG22C112F352GM40 */ 1338 /** @}} End of group Parts */ 1339 1340 #ifdef __cplusplus 1341 } 1342 #endif 1343 #endif 1344
