1 /**************************************************************************//** 2 * @file 3 * @brief EFR32BG22 LFRCO register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2024 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32BG22_LFRCO_H 31 #define EFR32BG22_LFRCO_H 32 #define LFRCO_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32BG22_LFRCO LFRCO 40 * @{ 41 * @brief EFR32BG22 LFRCO Register Declaration. 42 *****************************************************************************/ 43 44 /** LFRCO Register Declaration. */ 45 typedef struct lfrco_typedef{ 46 __IM uint32_t IPVERSION; /**< IP version */ 47 __IOM uint32_t CTRL; /**< Control Register */ 48 __IM uint32_t STATUS; /**< Status Register */ 49 uint32_t RESERVED0[2U]; /**< Reserved for future use */ 50 __IOM uint32_t IF; /**< Interrupt Flag Register */ 51 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 52 uint32_t RESERVED1[1U]; /**< Reserved for future use */ 53 __IOM uint32_t LOCK; /**< Configuration Lock Register */ 54 __IOM uint32_t CFG; /**< Configuration Register */ 55 uint32_t RESERVED2[1U]; /**< Reserved for future use */ 56 __IOM uint32_t NOMCAL; /**< Nominal Calibration Register */ 57 __IOM uint32_t NOMCALINV; /**< Nominal Calibration Inverted Register */ 58 __IOM uint32_t CMD; /**< Command Register */ 59 uint32_t RESERVED3[1010U]; /**< Reserved for future use */ 60 __IM uint32_t IPVERSION_SET; /**< IP version */ 61 __IOM uint32_t CTRL_SET; /**< Control Register */ 62 __IM uint32_t STATUS_SET; /**< Status Register */ 63 uint32_t RESERVED4[2U]; /**< Reserved for future use */ 64 __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ 65 __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ 66 uint32_t RESERVED5[1U]; /**< Reserved for future use */ 67 __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ 68 __IOM uint32_t CFG_SET; /**< Configuration Register */ 69 uint32_t RESERVED6[1U]; /**< Reserved for future use */ 70 __IOM uint32_t NOMCAL_SET; /**< Nominal Calibration Register */ 71 __IOM uint32_t NOMCALINV_SET; /**< Nominal Calibration Inverted Register */ 72 __IOM uint32_t CMD_SET; /**< Command Register */ 73 uint32_t RESERVED7[1010U]; /**< Reserved for future use */ 74 __IM uint32_t IPVERSION_CLR; /**< IP version */ 75 __IOM uint32_t CTRL_CLR; /**< Control Register */ 76 __IM uint32_t STATUS_CLR; /**< Status Register */ 77 uint32_t RESERVED8[2U]; /**< Reserved for future use */ 78 __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ 79 __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ 80 uint32_t RESERVED9[1U]; /**< Reserved for future use */ 81 __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ 82 __IOM uint32_t CFG_CLR; /**< Configuration Register */ 83 uint32_t RESERVED10[1U]; /**< Reserved for future use */ 84 __IOM uint32_t NOMCAL_CLR; /**< Nominal Calibration Register */ 85 __IOM uint32_t NOMCALINV_CLR; /**< Nominal Calibration Inverted Register */ 86 __IOM uint32_t CMD_CLR; /**< Command Register */ 87 uint32_t RESERVED11[1010U]; /**< Reserved for future use */ 88 __IM uint32_t IPVERSION_TGL; /**< IP version */ 89 __IOM uint32_t CTRL_TGL; /**< Control Register */ 90 __IM uint32_t STATUS_TGL; /**< Status Register */ 91 uint32_t RESERVED12[2U]; /**< Reserved for future use */ 92 __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ 93 __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ 94 uint32_t RESERVED13[1U]; /**< Reserved for future use */ 95 __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ 96 __IOM uint32_t CFG_TGL; /**< Configuration Register */ 97 uint32_t RESERVED14[1U]; /**< Reserved for future use */ 98 __IOM uint32_t NOMCAL_TGL; /**< Nominal Calibration Register */ 99 __IOM uint32_t NOMCALINV_TGL; /**< Nominal Calibration Inverted Register */ 100 __IOM uint32_t CMD_TGL; /**< Command Register */ 101 } LFRCO_TypeDef; 102 /** @} End of group EFR32BG22_LFRCO */ 103 104 /**************************************************************************//** 105 * @addtogroup EFR32BG22_LFRCO 106 * @{ 107 * @defgroup EFR32BG22_LFRCO_BitFields LFRCO Bit Fields 108 * @{ 109 *****************************************************************************/ 110 111 /* Bit fields for LFRCO IPVERSION */ 112 #define _LFRCO_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for LFRCO_IPVERSION */ 113 #define _LFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LFRCO_IPVERSION */ 114 #define _LFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LFRCO_IPVERSION */ 115 #define _LFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LFRCO_IPVERSION */ 116 #define _LFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for LFRCO_IPVERSION */ 117 #define LFRCO_IPVERSION_IPVERSION_DEFAULT (_LFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IPVERSION */ 118 119 /* Bit fields for LFRCO CTRL */ 120 #define _LFRCO_CTRL_RESETVALUE 0x00000000UL /**< Default value for LFRCO_CTRL */ 121 #define _LFRCO_CTRL_MASK 0x00000003UL /**< Mask for LFRCO_CTRL */ 122 #define LFRCO_CTRL_FORCEEN (0x1UL << 0) /**< Force Enable */ 123 #define _LFRCO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for LFRCO_FORCEEN */ 124 #define _LFRCO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for LFRCO_FORCEEN */ 125 #define _LFRCO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_CTRL */ 126 #define LFRCO_CTRL_FORCEEN_DEFAULT (_LFRCO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_CTRL */ 127 #define LFRCO_CTRL_DISONDEMAND (0x1UL << 1) /**< Disable On-Demand */ 128 #define _LFRCO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for LFRCO_DISONDEMAND */ 129 #define _LFRCO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for LFRCO_DISONDEMAND */ 130 #define _LFRCO_CTRL_DISONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_CTRL */ 131 #define LFRCO_CTRL_DISONDEMAND_DEFAULT (_LFRCO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_CTRL */ 132 133 /* Bit fields for LFRCO STATUS */ 134 #define _LFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for LFRCO_STATUS */ 135 #define _LFRCO_STATUS_MASK 0x80010001UL /**< Mask for LFRCO_STATUS */ 136 #define LFRCO_STATUS_RDY (0x1UL << 0) /**< Ready Status */ 137 #define _LFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ 138 #define _LFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ 139 #define _LFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ 140 #define LFRCO_STATUS_RDY_DEFAULT (_LFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_STATUS */ 141 #define LFRCO_STATUS_ENS (0x1UL << 16) /**< Enabled Status */ 142 #define _LFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for LFRCO_ENS */ 143 #define _LFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for LFRCO_ENS */ 144 #define _LFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ 145 #define LFRCO_STATUS_ENS_DEFAULT (_LFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for LFRCO_STATUS */ 146 #define LFRCO_STATUS_LOCK (0x1UL << 31) /**< Lock Status */ 147 #define _LFRCO_STATUS_LOCK_SHIFT 31 /**< Shift value for LFRCO_LOCK */ 148 #define _LFRCO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for LFRCO_LOCK */ 149 #define _LFRCO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ 150 #define _LFRCO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LFRCO_STATUS */ 151 #define _LFRCO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for LFRCO_STATUS */ 152 #define LFRCO_STATUS_LOCK_DEFAULT (_LFRCO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for LFRCO_STATUS */ 153 #define LFRCO_STATUS_LOCK_UNLOCKED (_LFRCO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for LFRCO_STATUS */ 154 #define LFRCO_STATUS_LOCK_LOCKED (_LFRCO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for LFRCO_STATUS */ 155 156 /* Bit fields for LFRCO IF */ 157 #define _LFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for LFRCO_IF */ 158 #define _LFRCO_IF_MASK 0x00070707UL /**< Mask for LFRCO_IF */ 159 #define LFRCO_IF_RDY (0x1UL << 0) /**< Ready Flag */ 160 #define _LFRCO_IF_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ 161 #define _LFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ 162 #define _LFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ 163 #define LFRCO_IF_RDY_DEFAULT (_LFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IF */ 164 #define LFRCO_IF_POSEDGE (0x1UL << 1) /**< Rising Edge Flag */ 165 #define _LFRCO_IF_POSEDGE_SHIFT 1 /**< Shift value for LFRCO_POSEDGE */ 166 #define _LFRCO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for LFRCO_POSEDGE */ 167 #define _LFRCO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ 168 #define LFRCO_IF_POSEDGE_DEFAULT (_LFRCO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_IF */ 169 #define LFRCO_IF_NEGEDGE (0x1UL << 2) /**< Falling Edge Flag */ 170 #define _LFRCO_IF_NEGEDGE_SHIFT 2 /**< Shift value for LFRCO_NEGEDGE */ 171 #define _LFRCO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for LFRCO_NEGEDGE */ 172 #define _LFRCO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ 173 #define LFRCO_IF_NEGEDGE_DEFAULT (_LFRCO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFRCO_IF */ 174 #define LFRCO_IF_TCDONE (0x1UL << 8) /**< Temperature Check Done Flag */ 175 #define _LFRCO_IF_TCDONE_SHIFT 8 /**< Shift value for LFRCO_TCDONE */ 176 #define _LFRCO_IF_TCDONE_MASK 0x100UL /**< Bit mask for LFRCO_TCDONE */ 177 #define _LFRCO_IF_TCDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ 178 #define LFRCO_IF_TCDONE_DEFAULT (_LFRCO_IF_TCDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for LFRCO_IF */ 179 #define LFRCO_IF_CALDONE (0x1UL << 9) /**< Calibration Done Flag */ 180 #define _LFRCO_IF_CALDONE_SHIFT 9 /**< Shift value for LFRCO_CALDONE */ 181 #define _LFRCO_IF_CALDONE_MASK 0x200UL /**< Bit mask for LFRCO_CALDONE */ 182 #define _LFRCO_IF_CALDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ 183 #define LFRCO_IF_CALDONE_DEFAULT (_LFRCO_IF_CALDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for LFRCO_IF */ 184 #define LFRCO_IF_TEMPCHANGE (0x1UL << 10) /**< Temperature Change Flag */ 185 #define _LFRCO_IF_TEMPCHANGE_SHIFT 10 /**< Shift value for LFRCO_TEMPCHANGE */ 186 #define _LFRCO_IF_TEMPCHANGE_MASK 0x400UL /**< Bit mask for LFRCO_TEMPCHANGE */ 187 #define _LFRCO_IF_TEMPCHANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ 188 #define LFRCO_IF_TEMPCHANGE_DEFAULT (_LFRCO_IF_TEMPCHANGE_DEFAULT << 10) /**< Shifted mode DEFAULT for LFRCO_IF */ 189 #define LFRCO_IF_SCHEDERR (0x1UL << 16) /**< Scheduling Error Flag */ 190 #define _LFRCO_IF_SCHEDERR_SHIFT 16 /**< Shift value for LFRCO_SCHEDERR */ 191 #define _LFRCO_IF_SCHEDERR_MASK 0x10000UL /**< Bit mask for LFRCO_SCHEDERR */ 192 #define _LFRCO_IF_SCHEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ 193 #define LFRCO_IF_SCHEDERR_DEFAULT (_LFRCO_IF_SCHEDERR_DEFAULT << 16) /**< Shifted mode DEFAULT for LFRCO_IF */ 194 #define LFRCO_IF_TCOOR (0x1UL << 17) /**< Temperature Check Out Of Range Flag */ 195 #define _LFRCO_IF_TCOOR_SHIFT 17 /**< Shift value for LFRCO_TCOOR */ 196 #define _LFRCO_IF_TCOOR_MASK 0x20000UL /**< Bit mask for LFRCO_TCOOR */ 197 #define _LFRCO_IF_TCOOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ 198 #define LFRCO_IF_TCOOR_DEFAULT (_LFRCO_IF_TCOOR_DEFAULT << 17) /**< Shifted mode DEFAULT for LFRCO_IF */ 199 #define LFRCO_IF_CALOOR (0x1UL << 18) /**< Calibration Out Of Range Flag */ 200 #define _LFRCO_IF_CALOOR_SHIFT 18 /**< Shift value for LFRCO_CALOOR */ 201 #define _LFRCO_IF_CALOOR_MASK 0x40000UL /**< Bit mask for LFRCO_CALOOR */ 202 #define _LFRCO_IF_CALOOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ 203 #define LFRCO_IF_CALOOR_DEFAULT (_LFRCO_IF_CALOOR_DEFAULT << 18) /**< Shifted mode DEFAULT for LFRCO_IF */ 204 205 /* Bit fields for LFRCO IEN */ 206 #define _LFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for LFRCO_IEN */ 207 #define _LFRCO_IEN_MASK 0x00070707UL /**< Mask for LFRCO_IEN */ 208 #define LFRCO_IEN_RDY (0x1UL << 0) /**< Ready Enable */ 209 #define _LFRCO_IEN_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ 210 #define _LFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ 211 #define _LFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ 212 #define LFRCO_IEN_RDY_DEFAULT (_LFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IEN */ 213 #define LFRCO_IEN_POSEDGE (0x1UL << 1) /**< Rising Edge Enable */ 214 #define _LFRCO_IEN_POSEDGE_SHIFT 1 /**< Shift value for LFRCO_POSEDGE */ 215 #define _LFRCO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for LFRCO_POSEDGE */ 216 #define _LFRCO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ 217 #define LFRCO_IEN_POSEDGE_DEFAULT (_LFRCO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_IEN */ 218 #define LFRCO_IEN_NEGEDGE (0x1UL << 2) /**< Falling Edge Enable */ 219 #define _LFRCO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for LFRCO_NEGEDGE */ 220 #define _LFRCO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for LFRCO_NEGEDGE */ 221 #define _LFRCO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ 222 #define LFRCO_IEN_NEGEDGE_DEFAULT (_LFRCO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFRCO_IEN */ 223 #define LFRCO_IEN_TCDONE (0x1UL << 8) /**< Temperature Check Done Enable */ 224 #define _LFRCO_IEN_TCDONE_SHIFT 8 /**< Shift value for LFRCO_TCDONE */ 225 #define _LFRCO_IEN_TCDONE_MASK 0x100UL /**< Bit mask for LFRCO_TCDONE */ 226 #define _LFRCO_IEN_TCDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ 227 #define LFRCO_IEN_TCDONE_DEFAULT (_LFRCO_IEN_TCDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for LFRCO_IEN */ 228 #define LFRCO_IEN_CALDONE (0x1UL << 9) /**< Calibration Done Enable */ 229 #define _LFRCO_IEN_CALDONE_SHIFT 9 /**< Shift value for LFRCO_CALDONE */ 230 #define _LFRCO_IEN_CALDONE_MASK 0x200UL /**< Bit mask for LFRCO_CALDONE */ 231 #define _LFRCO_IEN_CALDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ 232 #define LFRCO_IEN_CALDONE_DEFAULT (_LFRCO_IEN_CALDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for LFRCO_IEN */ 233 #define LFRCO_IEN_TEMPCHANGE (0x1UL << 10) /**< Temperature Change Enable */ 234 #define _LFRCO_IEN_TEMPCHANGE_SHIFT 10 /**< Shift value for LFRCO_TEMPCHANGE */ 235 #define _LFRCO_IEN_TEMPCHANGE_MASK 0x400UL /**< Bit mask for LFRCO_TEMPCHANGE */ 236 #define _LFRCO_IEN_TEMPCHANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ 237 #define LFRCO_IEN_TEMPCHANGE_DEFAULT (_LFRCO_IEN_TEMPCHANGE_DEFAULT << 10) /**< Shifted mode DEFAULT for LFRCO_IEN */ 238 #define LFRCO_IEN_SCHEDERR (0x1UL << 16) /**< Scheduling Error Enable */ 239 #define _LFRCO_IEN_SCHEDERR_SHIFT 16 /**< Shift value for LFRCO_SCHEDERR */ 240 #define _LFRCO_IEN_SCHEDERR_MASK 0x10000UL /**< Bit mask for LFRCO_SCHEDERR */ 241 #define _LFRCO_IEN_SCHEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ 242 #define LFRCO_IEN_SCHEDERR_DEFAULT (_LFRCO_IEN_SCHEDERR_DEFAULT << 16) /**< Shifted mode DEFAULT for LFRCO_IEN */ 243 #define LFRCO_IEN_TCOOR (0x1UL << 17) /**< Temperature Check Out Of Range Enable */ 244 #define _LFRCO_IEN_TCOOR_SHIFT 17 /**< Shift value for LFRCO_TCOOR */ 245 #define _LFRCO_IEN_TCOOR_MASK 0x20000UL /**< Bit mask for LFRCO_TCOOR */ 246 #define _LFRCO_IEN_TCOOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ 247 #define LFRCO_IEN_TCOOR_DEFAULT (_LFRCO_IEN_TCOOR_DEFAULT << 17) /**< Shifted mode DEFAULT for LFRCO_IEN */ 248 #define LFRCO_IEN_CALOOR (0x1UL << 18) /**< Calibration Out Of Range Enable */ 249 #define _LFRCO_IEN_CALOOR_SHIFT 18 /**< Shift value for LFRCO_CALOOR */ 250 #define _LFRCO_IEN_CALOOR_MASK 0x40000UL /**< Bit mask for LFRCO_CALOOR */ 251 #define _LFRCO_IEN_CALOOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ 252 #define LFRCO_IEN_CALOOR_DEFAULT (_LFRCO_IEN_CALOOR_DEFAULT << 18) /**< Shifted mode DEFAULT for LFRCO_IEN */ 253 254 /* Bit fields for LFRCO LOCK */ 255 #define _LFRCO_LOCK_RESETVALUE 0x00000000UL /**< Default value for LFRCO_LOCK */ 256 #define _LFRCO_LOCK_MASK 0x0000FFFFUL /**< Mask for LFRCO_LOCK */ 257 #define _LFRCO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for LFRCO_LOCKKEY */ 258 #define _LFRCO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for LFRCO_LOCKKEY */ 259 #define _LFRCO_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_LOCK */ 260 #define _LFRCO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for LFRCO_LOCK */ 261 #define _LFRCO_LOCK_LOCKKEY_UNLOCK 0x00000F93UL /**< Mode UNLOCK for LFRCO_LOCK */ 262 #define LFRCO_LOCK_LOCKKEY_DEFAULT (_LFRCO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_LOCK */ 263 #define LFRCO_LOCK_LOCKKEY_LOCK (_LFRCO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for LFRCO_LOCK */ 264 #define LFRCO_LOCK_LOCKKEY_UNLOCK (_LFRCO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LFRCO_LOCK */ 265 266 /* Bit fields for LFRCO CFG */ 267 #define _LFRCO_CFG_RESETVALUE 0x00000000UL /**< Default value for LFRCO_CFG */ 268 #define _LFRCO_CFG_MASK 0x00000001UL /**< Mask for LFRCO_CFG */ 269 #define LFRCO_CFG_HIGHPRECEN (0x1UL << 0) /**< High Precision Enable */ 270 #define _LFRCO_CFG_HIGHPRECEN_SHIFT 0 /**< Shift value for LFRCO_HIGHPRECEN */ 271 #define _LFRCO_CFG_HIGHPRECEN_MASK 0x1UL /**< Bit mask for LFRCO_HIGHPRECEN */ 272 #define _LFRCO_CFG_HIGHPRECEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_CFG */ 273 #define LFRCO_CFG_HIGHPRECEN_DEFAULT (_LFRCO_CFG_HIGHPRECEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_CFG */ 274 275 /* Bit fields for LFRCO NOMCAL */ 276 #define _LFRCO_NOMCAL_RESETVALUE 0x0005B8D8UL /**< Default value for LFRCO_NOMCAL */ 277 #define _LFRCO_NOMCAL_MASK 0x001FFFFFUL /**< Mask for LFRCO_NOMCAL */ 278 #define _LFRCO_NOMCAL_NOMCALCNT_SHIFT 0 /**< Shift value for LFRCO_NOMCALCNT */ 279 #define _LFRCO_NOMCAL_NOMCALCNT_MASK 0x1FFFFFUL /**< Bit mask for LFRCO_NOMCALCNT */ 280 #define _LFRCO_NOMCAL_NOMCALCNT_DEFAULT 0x0005B8D8UL /**< Mode DEFAULT for LFRCO_NOMCAL */ 281 #define LFRCO_NOMCAL_NOMCALCNT_DEFAULT (_LFRCO_NOMCAL_NOMCALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_NOMCAL */ 282 283 /* Bit fields for LFRCO NOMCALINV */ 284 #define _LFRCO_NOMCALINV_RESETVALUE 0x0000597AUL /**< Default value for LFRCO_NOMCALINV */ 285 #define _LFRCO_NOMCALINV_MASK 0x0001FFFFUL /**< Mask for LFRCO_NOMCALINV */ 286 #define _LFRCO_NOMCALINV_NOMCALCNTINV_SHIFT 0 /**< Shift value for LFRCO_NOMCALCNTINV */ 287 #define _LFRCO_NOMCALINV_NOMCALCNTINV_MASK 0x1FFFFUL /**< Bit mask for LFRCO_NOMCALCNTINV */ 288 #define _LFRCO_NOMCALINV_NOMCALCNTINV_DEFAULT 0x0000597AUL /**< Mode DEFAULT for LFRCO_NOMCALINV */ 289 #define LFRCO_NOMCALINV_NOMCALCNTINV_DEFAULT (_LFRCO_NOMCALINV_NOMCALCNTINV_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_NOMCALINV */ 290 291 /* Bit fields for LFRCO CMD */ 292 #define _LFRCO_CMD_RESETVALUE 0x00000000UL /**< Default value for LFRCO_CMD */ 293 #define _LFRCO_CMD_MASK 0x00000001UL /**< Mask for LFRCO_CMD */ 294 #define LFRCO_CMD_REDUCETCINT (0x1UL << 0) /**< Reduce Temperature Check Interval */ 295 #define _LFRCO_CMD_REDUCETCINT_SHIFT 0 /**< Shift value for LFRCO_REDUCETCINT */ 296 #define _LFRCO_CMD_REDUCETCINT_MASK 0x1UL /**< Bit mask for LFRCO_REDUCETCINT */ 297 #define _LFRCO_CMD_REDUCETCINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_CMD */ 298 #define LFRCO_CMD_REDUCETCINT_DEFAULT (_LFRCO_CMD_REDUCETCINT_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_CMD */ 299 300 /** @} End of group EFR32BG22_LFRCO_BitFields */ 301 /** @} End of group EFR32BG22_LFRCO */ 302 /** @} End of group Parts */ 303 304 #endif // EFR32BG22_LFRCO_H 305
