si32Hal/sim3u1xx/SI32_SIM3U1XX_PBCFG_A_Registers.h

//------------------------------------------------------------------------------
// Copyright 2012 (c) Silicon Laboratories Inc.
//
// SPDX-License-Identifier: Zlib
//
// This siHAL software is provided 'as-is', without any express or implied
// warranty. In no event will the authors be held liable for any damages
// arising from the use of this software.
//
// Permission is granted to anyone to use this software for any purpose,
// including commercial applications, and to alter it and redistribute it
// freely, subject to the following restrictions:
//
// 1. The origin of this software must not be misrepresented; you must not
//    claim that you wrote the original software. If you use this software
//    in a product, an acknowledgment in the product documentation would be
//    appreciated but is not required.
// 2. Altered source versions must be plainly marked as such, and must not be
//    misrepresented as being the original software.
// 3. This notice may not be removed or altered from any source distribution.
//------------------------------------------------------------------------------
//
// This file applies to the SIM3U1XX_PBCFG_A module
//
// Script: 0.57
// Version: 1

#ifndef __SI32_PBCFG_A_REGISTERS_H__
#define __SI32_PBCFG_A_REGISTERS_H__

#include <stdint.h>

#ifdef __cplusplus
extern "C" {
#endif

struct SI32_PBCFG_A_CONTROL0_Struct
{
   union
   {
      struct
      {
         // External Interrupt 0 Pin Selection
         volatile uint32_t INT0SEL: 4;
         // External Interrupt 0 Polarity
         volatile uint32_t INT0POL: 1;
         // External Interrupt 0 Mode
         volatile uint32_t INT0MD: 1;
                  uint32_t reserved0: 1;
         // External Interrupt 0 Enable
         volatile uint32_t INT0EN: 1;
         // External Interrupt 1 Pin Selection
         volatile uint32_t INT1SEL: 4;
         // External Interrupt 1 Polarity
         volatile uint32_t INT1POL: 1;
         // External Interrupt 1 Mode
         volatile uint32_t INT1MD: 1;
                  uint32_t reserved1: 1;
         // External Interrupt 1 Enable
         volatile uint32_t INT1EN: 1;
                  uint32_t reserved2: 8;
         // Pulse Generator Timer
         volatile uint32_t PGTIMER: 5;
                  uint32_t reserved3: 2;
         // Pulse Generator Timer Done Flag
         volatile uint32_t PGDONEF: 1;
      };
      volatile uint32_t U32;
   };
};

#define SI32_PBCFG_A_CONTROL0_INT0SEL_MASK  0x0000000F
#define SI32_PBCFG_A_CONTROL0_INT0SEL_SHIFT  0
// Select INT0.0
#define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_0_VALUE  0
#define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_0_U32 \
   (SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_0_VALUE << SI32_PBCFG_A_CONTROL0_INT0SEL_SHIFT)
// Select INT0.1
#define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_1_VALUE  1
#define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_1_U32 \
   (SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_1_VALUE << SI32_PBCFG_A_CONTROL0_INT0SEL_SHIFT)
// Select INT0.2
#define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_2_VALUE  2
#define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_2_U32 \
   (SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_2_VALUE << SI32_PBCFG_A_CONTROL0_INT0SEL_SHIFT)
// Select INT0.3
#define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_3_VALUE  3
#define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_3_U32 \
   (SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_3_VALUE << SI32_PBCFG_A_CONTROL0_INT0SEL_SHIFT)
// Select INT0.4
#define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_4_VALUE  4
#define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_4_U32 \
   (SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_4_VALUE << SI32_PBCFG_A_CONTROL0_INT0SEL_SHIFT)
// Select INT0.5
#define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_5_VALUE  5
#define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_5_U32 \
   (SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_5_VALUE << SI32_PBCFG_A_CONTROL0_INT0SEL_SHIFT)
// Select INT0.6
#define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_6_VALUE  6
#define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_6_U32 \
   (SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_6_VALUE << SI32_PBCFG_A_CONTROL0_INT0SEL_SHIFT)
// Select INT0.7
#define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_7_VALUE  7
#define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_7_U32 \
   (SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_7_VALUE << SI32_PBCFG_A_CONTROL0_INT0SEL_SHIFT)
// Select INT0.8
#define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_8_VALUE  8
#define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_8_U32 \
   (SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_8_VALUE << SI32_PBCFG_A_CONTROL0_INT0SEL_SHIFT)
// Select INT0.9
#define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_9_VALUE  9
#define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_9_U32 \
   (SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_9_VALUE << SI32_PBCFG_A_CONTROL0_INT0SEL_SHIFT)
// Select INT0.10
#define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_10_VALUE  10
#define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_10_U32 \
   (SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_10_VALUE << SI32_PBCFG_A_CONTROL0_INT0SEL_SHIFT)
// Select INT0.11
#define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_11_VALUE  11
#define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_11_U32 \
   (SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_11_VALUE << SI32_PBCFG_A_CONTROL0_INT0SEL_SHIFT)
// Select INT0.12
#define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_12_VALUE  12
#define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_12_U32 \
   (SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_12_VALUE << SI32_PBCFG_A_CONTROL0_INT0SEL_SHIFT)
// Select INT0.13
#define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_13_VALUE  13
#define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_13_U32 \
   (SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_13_VALUE << SI32_PBCFG_A_CONTROL0_INT0SEL_SHIFT)
// Select INT0.14
#define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_14_VALUE  14
#define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_14_U32 \
   (SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_14_VALUE << SI32_PBCFG_A_CONTROL0_INT0SEL_SHIFT)
// Select INT0.15
#define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_15_VALUE  15
#define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_15_U32 \
   (SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_15_VALUE << SI32_PBCFG_A_CONTROL0_INT0SEL_SHIFT)

#define SI32_PBCFG_A_CONTROL0_INT0POL_MASK  0x00000010
#define SI32_PBCFG_A_CONTROL0_INT0POL_SHIFT  4
// A low value or falling edge on the selected pin will cause interrupt.
#define SI32_PBCFG_A_CONTROL0_INT0POL_LOW_VALUE  0
#define SI32_PBCFG_A_CONTROL0_INT0POL_LOW_U32 \
   (SI32_PBCFG_A_CONTROL0_INT0POL_LOW_VALUE << SI32_PBCFG_A_CONTROL0_INT0POL_SHIFT)
// A high value or rising edge on the selected pin will cause interrupt.
#define SI32_PBCFG_A_CONTROL0_INT0POL_HIGH_VALUE  1
#define SI32_PBCFG_A_CONTROL0_INT0POL_HIGH_U32 \
   (SI32_PBCFG_A_CONTROL0_INT0POL_HIGH_VALUE << SI32_PBCFG_A_CONTROL0_INT0POL_SHIFT)

#define SI32_PBCFG_A_CONTROL0_INT0MD_MASK  0x00000020
#define SI32_PBCFG_A_CONTROL0_INT0MD_SHIFT  5
// Interrupt based on level sensitivity.
#define SI32_PBCFG_A_CONTROL0_INT0MD_LEVEL_VALUE  0
#define SI32_PBCFG_A_CONTROL0_INT0MD_LEVEL_U32 \
   (SI32_PBCFG_A_CONTROL0_INT0MD_LEVEL_VALUE << SI32_PBCFG_A_CONTROL0_INT0MD_SHIFT)
// Interrupt based on edge sensitivity.
#define SI32_PBCFG_A_CONTROL0_INT0MD_EDGE_VALUE  1
#define SI32_PBCFG_A_CONTROL0_INT0MD_EDGE_U32 \
   (SI32_PBCFG_A_CONTROL0_INT0MD_EDGE_VALUE << SI32_PBCFG_A_CONTROL0_INT0MD_SHIFT)

#define SI32_PBCFG_A_CONTROL0_INT0EN_MASK  0x00000080
#define SI32_PBCFG_A_CONTROL0_INT0EN_SHIFT  7
// Disable external interrupt 0.
#define SI32_PBCFG_A_CONTROL0_INT0EN_DISABLED_VALUE  0
#define SI32_PBCFG_A_CONTROL0_INT0EN_DISABLED_U32 \
   (SI32_PBCFG_A_CONTROL0_INT0EN_DISABLED_VALUE << SI32_PBCFG_A_CONTROL0_INT0EN_SHIFT)
// Enable external interrupt 0.
#define SI32_PBCFG_A_CONTROL0_INT0EN_ENABLED_VALUE  1
#define SI32_PBCFG_A_CONTROL0_INT0EN_ENABLED_U32 \
   (SI32_PBCFG_A_CONTROL0_INT0EN_ENABLED_VALUE << SI32_PBCFG_A_CONTROL0_INT0EN_SHIFT)

#define SI32_PBCFG_A_CONTROL0_INT1SEL_MASK  0x00000F00
#define SI32_PBCFG_A_CONTROL0_INT1SEL_SHIFT  8
// Select INT1.0
#define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_0_VALUE  0
#define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_0_U32 \
   (SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_0_VALUE << SI32_PBCFG_A_CONTROL0_INT1SEL_SHIFT)
// Select INT1.1
#define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_1_VALUE  1
#define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_1_U32 \
   (SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_1_VALUE << SI32_PBCFG_A_CONTROL0_INT1SEL_SHIFT)
// Select INT1.2
#define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_2_VALUE  2
#define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_2_U32 \
   (SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_2_VALUE << SI32_PBCFG_A_CONTROL0_INT1SEL_SHIFT)
// Select INT1.3
#define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_3_VALUE  3
#define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_3_U32 \
   (SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_3_VALUE << SI32_PBCFG_A_CONTROL0_INT1SEL_SHIFT)
// Select INT1.4
#define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_4_VALUE  4
#define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_4_U32 \
   (SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_4_VALUE << SI32_PBCFG_A_CONTROL0_INT1SEL_SHIFT)
// Select INT1.5
#define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_5_VALUE  5
#define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_5_U32 \
   (SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_5_VALUE << SI32_PBCFG_A_CONTROL0_INT1SEL_SHIFT)
// Select INT1.6
#define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_6_VALUE  6
#define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_6_U32 \
   (SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_6_VALUE << SI32_PBCFG_A_CONTROL0_INT1SEL_SHIFT)
// Select INT1.7
#define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_7_VALUE  7
#define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_7_U32 \
   (SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_7_VALUE << SI32_PBCFG_A_CONTROL0_INT1SEL_SHIFT)
// Select INT1.8
#define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_8_VALUE  8
#define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_8_U32 \
   (SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_8_VALUE << SI32_PBCFG_A_CONTROL0_INT1SEL_SHIFT)
// Select INT1.9
#define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_9_VALUE  9
#define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_9_U32 \
   (SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_9_VALUE << SI32_PBCFG_A_CONTROL0_INT1SEL_SHIFT)
// Select INT1.10
#define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_10_VALUE  10
#define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_10_U32 \
   (SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_10_VALUE << SI32_PBCFG_A_CONTROL0_INT1SEL_SHIFT)
// Select INT1.11
#define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_11_VALUE  11
#define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_11_U32 \
   (SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_11_VALUE << SI32_PBCFG_A_CONTROL0_INT1SEL_SHIFT)
// Select INT1.12
#define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_12_VALUE  12
#define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_12_U32 \
   (SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_12_VALUE << SI32_PBCFG_A_CONTROL0_INT1SEL_SHIFT)
// Select INT1.13
#define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_13_VALUE  13
#define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_13_U32 \
   (SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_13_VALUE << SI32_PBCFG_A_CONTROL0_INT1SEL_SHIFT)
// Select INT1.14
#define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_14_VALUE  14
#define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_14_U32 \
   (SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_14_VALUE << SI32_PBCFG_A_CONTROL0_INT1SEL_SHIFT)
// Select INT1.15
#define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_15_VALUE  15
#define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_15_U32 \
   (SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_15_VALUE << SI32_PBCFG_A_CONTROL0_INT1SEL_SHIFT)

#define SI32_PBCFG_A_CONTROL0_INT1POL_MASK  0x00001000
#define SI32_PBCFG_A_CONTROL0_INT1POL_SHIFT  12
// A low value or falling edge on the selected pin will cause interrupt.
#define SI32_PBCFG_A_CONTROL0_INT1POL_LOW_VALUE  0
#define SI32_PBCFG_A_CONTROL0_INT1POL_LOW_U32 \
   (SI32_PBCFG_A_CONTROL0_INT1POL_LOW_VALUE << SI32_PBCFG_A_CONTROL0_INT1POL_SHIFT)
// A high value or rising edge on the selected pin will cause interrupt.
#define SI32_PBCFG_A_CONTROL0_INT1POL_HIGH_VALUE  1
#define SI32_PBCFG_A_CONTROL0_INT1POL_HIGH_U32 \
   (SI32_PBCFG_A_CONTROL0_INT1POL_HIGH_VALUE << SI32_PBCFG_A_CONTROL0_INT1POL_SHIFT)

#define SI32_PBCFG_A_CONTROL0_INT1MD_MASK  0x00002000
#define SI32_PBCFG_A_CONTROL0_INT1MD_SHIFT  13
// Interrupt based on level sensitivity.
#define SI32_PBCFG_A_CONTROL0_INT1MD_LEVEL_VALUE  0
#define SI32_PBCFG_A_CONTROL0_INT1MD_LEVEL_U32 \
   (SI32_PBCFG_A_CONTROL0_INT1MD_LEVEL_VALUE << SI32_PBCFG_A_CONTROL0_INT1MD_SHIFT)
// Interrupt based on edge sensitivity.
#define SI32_PBCFG_A_CONTROL0_INT1MD_EDGE_VALUE  1
#define SI32_PBCFG_A_CONTROL0_INT1MD_EDGE_U32 \
   (SI32_PBCFG_A_CONTROL0_INT1MD_EDGE_VALUE << SI32_PBCFG_A_CONTROL0_INT1MD_SHIFT)

#define SI32_PBCFG_A_CONTROL0_INT1EN_MASK  0x00008000
#define SI32_PBCFG_A_CONTROL0_INT1EN_SHIFT  15
// Disable external interrupt 1.
#define SI32_PBCFG_A_CONTROL0_INT1EN_DISABLED_VALUE  0
#define SI32_PBCFG_A_CONTROL0_INT1EN_DISABLED_U32 \
   (SI32_PBCFG_A_CONTROL0_INT1EN_DISABLED_VALUE << SI32_PBCFG_A_CONTROL0_INT1EN_SHIFT)
// Enable external interrupt 1.
#define SI32_PBCFG_A_CONTROL0_INT1EN_ENABLED_VALUE  1
#define SI32_PBCFG_A_CONTROL0_INT1EN_ENABLED_U32 \
   (SI32_PBCFG_A_CONTROL0_INT1EN_ENABLED_VALUE << SI32_PBCFG_A_CONTROL0_INT1EN_SHIFT)

#define SI32_PBCFG_A_CONTROL0_PGTIMER_MASK  0x1F000000
#define SI32_PBCFG_A_CONTROL0_PGTIMER_SHIFT  24

#define SI32_PBCFG_A_CONTROL0_PGDONEF_MASK  0x80000000
#define SI32_PBCFG_A_CONTROL0_PGDONEF_SHIFT  31
// Firmware has written to the PBPGPHASE register, but the Pulse Generator timer
// has not expired.
#define SI32_PBCFG_A_CONTROL0_PGDONEF_NOT_SET_VALUE  0U
#define SI32_PBCFG_A_CONTROL0_PGDONEF_NOT_SET_U32 \
   (SI32_PBCFG_A_CONTROL0_PGDONEF_NOT_SET_VALUE << SI32_PBCFG_A_CONTROL0_PGDONEF_SHIFT)
// The Pulse Generator cycle finished since the last time PBPGPHASE was written.
#define SI32_PBCFG_A_CONTROL0_PGDONEF_SET_VALUE  1U
#define SI32_PBCFG_A_CONTROL0_PGDONEF_SET_U32 \
   (SI32_PBCFG_A_CONTROL0_PGDONEF_SET_VALUE << SI32_PBCFG_A_CONTROL0_PGDONEF_SHIFT)


struct SI32_PBCFG_A_CONTROL1_Struct
{
   union
   {
      struct
      {
         // JTAG Enable
         volatile uint32_t JTAGEN: 1;
         // ETM Enable
         volatile uint32_t ETMEN: 1;
                  uint32_t reserved0: 5;
         // EMIF <overline>BE0</overline> Pin Enable
         volatile uint32_t EMIFBE0BEN: 1;
         // EMIF CS1 Pin Enable
         volatile uint32_t EMIFCS1EN: 1;
         // EMIF Enable
         volatile uint32_t EMIFEN: 1;
         // EMIF Width
         volatile uint32_t EMIFWIDTH: 6;
         // Match Mode
         volatile uint32_t MATMD: 2;
                  uint32_t reserved1: 5;
         // External Regulator Reset Mode
         volatile uint32_t EVREGRMD: 1;
                  uint32_t reserved2: 7;
         // Port Bank Configuration Lock
         volatile uint32_t LOCK: 1;
      };
      volatile uint32_t U32;
   };
};

#define SI32_PBCFG_A_CONTROL1_JTAGEN_MASK  0x00000001
#define SI32_PBCFG_A_CONTROL1_JTAGEN_SHIFT  0
// JTAG functionality is not pinned out.
#define SI32_PBCFG_A_CONTROL1_JTAGEN_DISABLED_VALUE  0
#define SI32_PBCFG_A_CONTROL1_JTAGEN_DISABLED_U32 \
   (SI32_PBCFG_A_CONTROL1_JTAGEN_DISABLED_VALUE << SI32_PBCFG_A_CONTROL1_JTAGEN_SHIFT)
// JTAG functionality is pinned out.
#define SI32_PBCFG_A_CONTROL1_JTAGEN_ENABLED_VALUE  1
#define SI32_PBCFG_A_CONTROL1_JTAGEN_ENABLED_U32 \
   (SI32_PBCFG_A_CONTROL1_JTAGEN_ENABLED_VALUE << SI32_PBCFG_A_CONTROL1_JTAGEN_SHIFT)

#define SI32_PBCFG_A_CONTROL1_ETMEN_MASK  0x00000002
#define SI32_PBCFG_A_CONTROL1_ETMEN_SHIFT  1
// ETM not pinned out.
#define SI32_PBCFG_A_CONTROL1_ETMEN_DISABLED_VALUE  0
#define SI32_PBCFG_A_CONTROL1_ETMEN_DISABLED_U32 \
   (SI32_PBCFG_A_CONTROL1_ETMEN_DISABLED_VALUE << SI32_PBCFG_A_CONTROL1_ETMEN_SHIFT)
// ETM is enabled and pinned out.
#define SI32_PBCFG_A_CONTROL1_ETMEN_ENABLED_VALUE  1
#define SI32_PBCFG_A_CONTROL1_ETMEN_ENABLED_U32 \
   (SI32_PBCFG_A_CONTROL1_ETMEN_ENABLED_VALUE << SI32_PBCFG_A_CONTROL1_ETMEN_SHIFT)

#define SI32_PBCFG_A_CONTROL1_EMIFBE0BEN_MASK  0x00000080
#define SI32_PBCFG_A_CONTROL1_EMIFBE0BEN_SHIFT  7
// Disable the EMIF /BE0 pin.
#define SI32_PBCFG_A_CONTROL1_EMIFBE0BEN_DISABLED_VALUE  0
#define SI32_PBCFG_A_CONTROL1_EMIFBE0BEN_DISABLED_U32 \
   (SI32_PBCFG_A_CONTROL1_EMIFBE0BEN_DISABLED_VALUE << SI32_PBCFG_A_CONTROL1_EMIFBE0BEN_SHIFT)
// Enable the /BE0 pin if EMIFEN is also set to 1.
#define SI32_PBCFG_A_CONTROL1_EMIFBE0BEN_ENABLED_VALUE  1
#define SI32_PBCFG_A_CONTROL1_EMIFBE0BEN_ENABLED_U32 \
   (SI32_PBCFG_A_CONTROL1_EMIFBE0BEN_ENABLED_VALUE << SI32_PBCFG_A_CONTROL1_EMIFBE0BEN_SHIFT)

#define SI32_PBCFG_A_CONTROL1_EMIFCS1EN_MASK  0x00000100
#define SI32_PBCFG_A_CONTROL1_EMIFCS1EN_SHIFT  8
// Disable the EMIF CS1 pin.
#define SI32_PBCFG_A_CONTROL1_EMIFCS1EN_DISABLED_VALUE  0
#define SI32_PBCFG_A_CONTROL1_EMIFCS1EN_DISABLED_U32 \
   (SI32_PBCFG_A_CONTROL1_EMIFCS1EN_DISABLED_VALUE << SI32_PBCFG_A_CONTROL1_EMIFCS1EN_SHIFT)
// Enable the CS1 pin if EMIFEN is also set to 1.
#define SI32_PBCFG_A_CONTROL1_EMIFCS1EN_ENABLED_VALUE  1
#define SI32_PBCFG_A_CONTROL1_EMIFCS1EN_ENABLED_U32 \
   (SI32_PBCFG_A_CONTROL1_EMIFCS1EN_ENABLED_VALUE << SI32_PBCFG_A_CONTROL1_EMIFCS1EN_SHIFT)

#define SI32_PBCFG_A_CONTROL1_EMIFEN_MASK  0x00000200
#define SI32_PBCFG_A_CONTROL1_EMIFEN_SHIFT  9
// Disable the EMIF pins.
#define SI32_PBCFG_A_CONTROL1_EMIFEN_DISABLED_VALUE  0
#define SI32_PBCFG_A_CONTROL1_EMIFEN_DISABLED_U32 \
   (SI32_PBCFG_A_CONTROL1_EMIFEN_DISABLED_VALUE << SI32_PBCFG_A_CONTROL1_EMIFEN_SHIFT)
// EMIF is enabled and pinned out.
#define SI32_PBCFG_A_CONTROL1_EMIFEN_ENABLED_VALUE  1
#define SI32_PBCFG_A_CONTROL1_EMIFEN_ENABLED_U32 \
   (SI32_PBCFG_A_CONTROL1_EMIFEN_ENABLED_VALUE << SI32_PBCFG_A_CONTROL1_EMIFEN_SHIFT)

#define SI32_PBCFG_A_CONTROL1_EMIFWIDTH_MASK  0x0000FC00
#define SI32_PBCFG_A_CONTROL1_EMIFWIDTH_SHIFT  10
// EMIF Address[7:0]
#define SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_8_VALUE  0
#define SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_8_U32 \
   (SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_8_VALUE << SI32_PBCFG_A_CONTROL1_EMIFWIDTH_SHIFT)
// EMIF Address[8:0], PB2.8 = A[8]
#define SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_9_VALUE  1
#define SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_9_U32 \
   (SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_9_VALUE << SI32_PBCFG_A_CONTROL1_EMIFWIDTH_SHIFT)
// EMIF Address[9:0], PB2.7 = A[9]
#define SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_10_VALUE  2
#define SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_10_U32 \
   (SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_10_VALUE << SI32_PBCFG_A_CONTROL1_EMIFWIDTH_SHIFT)
// EMIF Address[10:0], PB2.6 = A[10]
#define SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_11_VALUE  3
#define SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_11_U32 \
   (SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_11_VALUE << SI32_PBCFG_A_CONTROL1_EMIFWIDTH_SHIFT)
// EMIF Address[11:0], PB2.5 = A[11]
#define SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_12_VALUE  4
#define SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_12_U32 \
   (SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_12_VALUE << SI32_PBCFG_A_CONTROL1_EMIFWIDTH_SHIFT)
// EMIF Address[12:0], PB2.4 = A[12]
#define SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_13_VALUE  5
#define SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_13_U32 \
   (SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_13_VALUE << SI32_PBCFG_A_CONTROL1_EMIFWIDTH_SHIFT)
// EMIF Address[13:0], PB2.3 = A[13]
#define SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_14_VALUE  6
#define SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_14_U32 \
   (SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_14_VALUE << SI32_PBCFG_A_CONTROL1_EMIFWIDTH_SHIFT)
// EMIF Address[14:0], PB2.2 = A[14]
#define SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_15_VALUE  7
#define SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_15_U32 \
   (SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_15_VALUE << SI32_PBCFG_A_CONTROL1_EMIFWIDTH_SHIFT)
// EMIF Address[15:0], PB2.1 = A[15]
#define SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_16_VALUE  8
#define SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_16_U32 \
   (SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_16_VALUE << SI32_PBCFG_A_CONTROL1_EMIFWIDTH_SHIFT)
// EMIF Address[16:0], PB2.0 = A[16]
#define SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_17_VALUE  9
#define SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_17_U32 \
   (SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_17_VALUE << SI32_PBCFG_A_CONTROL1_EMIFWIDTH_SHIFT)
// EMIF Address[17:0], PB1.15 = A[17]
#define SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_18_VALUE  10
#define SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_18_U32 \
   (SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_18_VALUE << SI32_PBCFG_A_CONTROL1_EMIFWIDTH_SHIFT)
// EMIF Address[18:0], PB1.14 = A[18]
#define SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_19_VALUE  11
#define SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_19_U32 \
   (SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_19_VALUE << SI32_PBCFG_A_CONTROL1_EMIFWIDTH_SHIFT)
// EMIF Address[19:0], PB1.13 = A[19]
#define SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_20_VALUE  12
#define SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_20_U32 \
   (SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_20_VALUE << SI32_PBCFG_A_CONTROL1_EMIFWIDTH_SHIFT)
// EMIF Address[20:0], PB1.12 = A[20]
#define SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_21_VALUE  13
#define SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_21_U32 \
   (SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_21_VALUE << SI32_PBCFG_A_CONTROL1_EMIFWIDTH_SHIFT)
// EMIF Address[21:0], PB1.11 = A[21]
#define SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_22_VALUE  14
#define SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_22_U32 \
   (SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_22_VALUE << SI32_PBCFG_A_CONTROL1_EMIFWIDTH_SHIFT)
// EMIF Address[22:0], PB1.10 = A[22]
#define SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_23_VALUE  15
#define SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_23_U32 \
   (SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_23_VALUE << SI32_PBCFG_A_CONTROL1_EMIFWIDTH_SHIFT)
// EMIF Address[23:0], PB1.10 = A[23]
#define SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_24_VALUE  16
#define SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_24_U32 \
   (SI32_PBCFG_A_CONTROL1_EMIFWIDTH_AWIDTH_24_VALUE << SI32_PBCFG_A_CONTROL1_EMIFWIDTH_SHIFT)

#define SI32_PBCFG_A_CONTROL1_MATMD_MASK  0x00030000
#define SI32_PBCFG_A_CONTROL1_MATMD_SHIFT  16
// Port Match registers used to provide interrupt / wake sources.
#define SI32_PBCFG_A_CONTROL1_MATMD_PINMATCH_VALUE  0
#define SI32_PBCFG_A_CONTROL1_MATMD_PINMATCH_U32 \
   (SI32_PBCFG_A_CONTROL1_MATMD_PINMATCH_VALUE << SI32_PBCFG_A_CONTROL1_MATMD_SHIFT)
// Port Match registers used to monitor output pin activity for Capacitive Sensing
// measurements.
#define SI32_PBCFG_A_CONTROL1_MATMD_CAPSENSE_TX_VALUE  1
#define SI32_PBCFG_A_CONTROL1_MATMD_CAPSENSE_TX_U32 \
   (SI32_PBCFG_A_CONTROL1_MATMD_CAPSENSE_TX_VALUE << SI32_PBCFG_A_CONTROL1_MATMD_SHIFT)
// Port Match registers used to monitor input pin activity for Capacitive Sensing
// measurements.
#define SI32_PBCFG_A_CONTROL1_MATMD_CAPSENSE_RX_VALUE  2
#define SI32_PBCFG_A_CONTROL1_MATMD_CAPSENSE_RX_U32 \
   (SI32_PBCFG_A_CONTROL1_MATMD_CAPSENSE_RX_VALUE << SI32_PBCFG_A_CONTROL1_MATMD_SHIFT)

#define SI32_PBCFG_A_CONTROL1_EVREGRMD_MASK  0x00800000
#define SI32_PBCFG_A_CONTROL1_EVREGRMD_SHIFT  23
// The pins used by the external regulator will default to digital inputs with weak
// pull-up enabled on any reset.
#define SI32_PBCFG_A_CONTROL1_EVREGRMD_RESET_ON_ANY_VALUE  0
#define SI32_PBCFG_A_CONTROL1_EVREGRMD_RESET_ON_ANY_U32 \
   (SI32_PBCFG_A_CONTROL1_EVREGRMD_RESET_ON_ANY_VALUE << SI32_PBCFG_A_CONTROL1_EVREGRMD_SHIFT)
// The pins used by the external regulator will default to digital inputs with weak
// pull-up enabled only on Power-On Reset. Their configured mode will be preserved
// through all other resets.
#define SI32_PBCFG_A_CONTROL1_EVREGRMD_RESET_ON_POR_VALUE  1
#define SI32_PBCFG_A_CONTROL1_EVREGRMD_RESET_ON_POR_U32 \
   (SI32_PBCFG_A_CONTROL1_EVREGRMD_RESET_ON_POR_VALUE << SI32_PBCFG_A_CONTROL1_EVREGRMD_SHIFT)

#define SI32_PBCFG_A_CONTROL1_LOCK_MASK  0x80000000
#define SI32_PBCFG_A_CONTROL1_LOCK_SHIFT  31
// Port Bank Configuration and Control registers are unlocked.
#define SI32_PBCFG_A_CONTROL1_LOCK_UNLOCKED_VALUE  0U
#define SI32_PBCFG_A_CONTROL1_LOCK_UNLOCKED_U32 \
   (SI32_PBCFG_A_CONTROL1_LOCK_UNLOCKED_VALUE << SI32_PBCFG_A_CONTROL1_LOCK_SHIFT)
// The following registers are locked from write access: CONTROL1, XBAR0L, XBAR0H,
// XBAR1, and all PBSKIP registers.
#define SI32_PBCFG_A_CONTROL1_LOCK_LOCKED_VALUE  1U
#define SI32_PBCFG_A_CONTROL1_LOCK_LOCKED_U32 \
   (SI32_PBCFG_A_CONTROL1_LOCK_LOCKED_VALUE << SI32_PBCFG_A_CONTROL1_LOCK_SHIFT)


struct SI32_PBCFG_A_XBAR0L_Struct
{
   union
   {
      struct
      {
         // USART0 Enable
         volatile uint32_t USART0EN: 1;
         // USART0 Flow Control Enable
         volatile uint32_t USART0FCEN: 1;
         // USART0 Clock Signal Enable
         volatile uint32_t USART0CEN: 1;
         // SPI0 Enable
         volatile uint32_t SPI0EN: 1;
         // SPI0 NSS Pin Enable
         volatile uint32_t SPI0NSSEN: 1;
         // USART1 Enable
         volatile uint32_t USART1EN: 1;
         // USART1 Flow Control Enable
         volatile uint32_t USART1FCEN: 1;
         // USART1 Clock Signal Enable
         volatile uint32_t USART1CEN: 1;
         // EPCA0 Channel Enable
         volatile uint32_t EPCA0EN: 3;
                  uint32_t reserved0: 3;
         // PCA0 Channel Enable
         volatile uint32_t PCA0EN: 2;
         // PCA1 Channel Enable
         volatile uint32_t PCA1EN: 2;
         // EPCA0 ECI Enable
         volatile uint32_t EECI0EN: 1;
         // PCA0 ECI Enable
         volatile uint32_t ECI0EN: 1;
         // PCA1 ECI Enable
         volatile uint32_t ECI1EN: 1;
         // I2S0 TX Enable
         volatile uint32_t I2S0TXEN: 1;
         // I2C0 Enable
         volatile uint32_t I2C0EN: 1;
         // Comparator 0 Synchronous Output (CMP0S) Enable
         volatile uint32_t CMP0SEN: 1;
         // Comparator 0 Asynchronous Output (CMP0A) Enable
         volatile uint32_t CMP0AEN: 1;
         // Comparator 1 Synchronous Output (CMP1S) Enable
         volatile uint32_t CMP1SEN: 1;
         // Comparator 1 Asynchronous Output (CMP1A) Enable
         volatile uint32_t CMP1AEN: 1;
         // TIMER0 T0CT Enable
         volatile uint32_t TMR0CTEN: 1;
         // TIMER0 T0EX Enable
         volatile uint32_t TMR0EXEN: 1;
         // TIMER1 T1CT Enable
         volatile uint32_t TMR1CTEN: 1;
         // TIMER1 T1EX Enable
         volatile uint32_t TMR1EXEN: 1;
                  uint32_t reserved1: 1;
      };
      volatile uint32_t U32;
   };
};

#define SI32_PBCFG_A_XBAR0L_USART0EN_MASK  0x00000001
#define SI32_PBCFG_A_XBAR0L_USART0EN_SHIFT  0
// Disable USART0 RX and TX on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_USART0EN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR0L_USART0EN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR0L_USART0EN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0L_USART0EN_SHIFT)
// Enable USART0 RX and TX on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_USART0EN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR0L_USART0EN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR0L_USART0EN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0L_USART0EN_SHIFT)

#define SI32_PBCFG_A_XBAR0L_USART0FCEN_MASK  0x00000002
#define SI32_PBCFG_A_XBAR0L_USART0FCEN_SHIFT  1
// Disable USART0 flow control on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_USART0FCEN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR0L_USART0FCEN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR0L_USART0FCEN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0L_USART0FCEN_SHIFT)
// Enable USART0 flow control on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_USART0FCEN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR0L_USART0FCEN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR0L_USART0FCEN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0L_USART0FCEN_SHIFT)

#define SI32_PBCFG_A_XBAR0L_USART0CEN_MASK  0x00000004
#define SI32_PBCFG_A_XBAR0L_USART0CEN_SHIFT  2
// Disable USART0 clock on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_USART0CEN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR0L_USART0CEN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR0L_USART0CEN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0L_USART0CEN_SHIFT)
// Enable USART0 clock on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_USART0CEN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR0L_USART0CEN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR0L_USART0CEN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0L_USART0CEN_SHIFT)

#define SI32_PBCFG_A_XBAR0L_SPI0EN_MASK  0x00000008
#define SI32_PBCFG_A_XBAR0L_SPI0EN_SHIFT  3
// Disable SPI0 SCK, MISO, and MOSI on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_SPI0EN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR0L_SPI0EN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR0L_SPI0EN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0L_SPI0EN_SHIFT)
// Enable SPI0 SCK, MISO, and MOSI on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_SPI0EN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR0L_SPI0EN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR0L_SPI0EN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0L_SPI0EN_SHIFT)

#define SI32_PBCFG_A_XBAR0L_SPI0NSSEN_MASK  0x00000010
#define SI32_PBCFG_A_XBAR0L_SPI0NSSEN_SHIFT  4
// Disable SPI0 NSS on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_SPI0NSSEN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR0L_SPI0NSSEN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR0L_SPI0NSSEN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0L_SPI0NSSEN_SHIFT)
// Enable SPI0 NSS on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_SPI0NSSEN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR0L_SPI0NSSEN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR0L_SPI0NSSEN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0L_SPI0NSSEN_SHIFT)

#define SI32_PBCFG_A_XBAR0L_USART1EN_MASK  0x00000020
#define SI32_PBCFG_A_XBAR0L_USART1EN_SHIFT  5
// Disable USART1 RX and TX on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_USART1EN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR0L_USART1EN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR0L_USART1EN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0L_USART1EN_SHIFT)
// Enable USART1 RX and TX on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_USART1EN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR0L_USART1EN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR0L_USART1EN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0L_USART1EN_SHIFT)

#define SI32_PBCFG_A_XBAR0L_USART1FCEN_MASK  0x00000040
#define SI32_PBCFG_A_XBAR0L_USART1FCEN_SHIFT  6
// Disable USART1 flow control on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_USART1FCEN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR0L_USART1FCEN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR0L_USART1FCEN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0L_USART1FCEN_SHIFT)
// Enable USART1 flow control on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_USART1FCEN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR0L_USART1FCEN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR0L_USART1FCEN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0L_USART1FCEN_SHIFT)

#define SI32_PBCFG_A_XBAR0L_USART1CEN_MASK  0x00000080
#define SI32_PBCFG_A_XBAR0L_USART1CEN_SHIFT  7
// Disable USART1 clock on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_USART1CEN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR0L_USART1CEN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR0L_USART1CEN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0L_USART1CEN_SHIFT)
// Enable USART1 clock on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_USART1CEN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR0L_USART1CEN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR0L_USART1CEN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0L_USART1CEN_SHIFT)

#define SI32_PBCFG_A_XBAR0L_EPCA0EN_MASK  0x00000700
#define SI32_PBCFG_A_XBAR0L_EPCA0EN_SHIFT  8
// Disable all EPCA0 channels on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_EPCA0EN_NONE_VALUE  0
#define SI32_PBCFG_A_XBAR0L_EPCA0EN_NONE_U32 \
   (SI32_PBCFG_A_XBAR0L_EPCA0EN_NONE_VALUE << SI32_PBCFG_A_XBAR0L_EPCA0EN_SHIFT)
// Enable EPCA0 STD_CEX0 on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_EPCA0EN_STD_CEX0_VALUE  1
#define SI32_PBCFG_A_XBAR0L_EPCA0EN_STD_CEX0_U32 \
   (SI32_PBCFG_A_XBAR0L_EPCA0EN_STD_CEX0_VALUE << SI32_PBCFG_A_XBAR0L_EPCA0EN_SHIFT)
// Enable EPCA0 STD_CEX0 and STD_CEX1 on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_EPCA0EN_STD_CEX0_1_VALUE  2
#define SI32_PBCFG_A_XBAR0L_EPCA0EN_STD_CEX0_1_U32 \
   (SI32_PBCFG_A_XBAR0L_EPCA0EN_STD_CEX0_1_VALUE << SI32_PBCFG_A_XBAR0L_EPCA0EN_SHIFT)
// Enable EPCA0 STD_CEX0, STD_CEX1, and STD_CEX2 on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_EPCA0EN_STD_CEX0_2_VALUE  3
#define SI32_PBCFG_A_XBAR0L_EPCA0EN_STD_CEX0_2_U32 \
   (SI32_PBCFG_A_XBAR0L_EPCA0EN_STD_CEX0_2_VALUE << SI32_PBCFG_A_XBAR0L_EPCA0EN_SHIFT)
// Enable EPCA0 STD_CEX0, STD_CEX1, STD_CEX2, and STD_CEX3 on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_EPCA0EN_STD_CEX0_3_VALUE  4
#define SI32_PBCFG_A_XBAR0L_EPCA0EN_STD_CEX0_3_U32 \
   (SI32_PBCFG_A_XBAR0L_EPCA0EN_STD_CEX0_3_VALUE << SI32_PBCFG_A_XBAR0L_EPCA0EN_SHIFT)
// Enable EPCA0 STD_CEX0, STD_CEX1, STD_CEX2, STD_CEX3, and STD_CEX4 on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_EPCA0EN_STD_CEX0_4_VALUE  5
#define SI32_PBCFG_A_XBAR0L_EPCA0EN_STD_CEX0_4_U32 \
   (SI32_PBCFG_A_XBAR0L_EPCA0EN_STD_CEX0_4_VALUE << SI32_PBCFG_A_XBAR0L_EPCA0EN_SHIFT)
// Enable EPCA0 STD_CEX0, STD_CEX1, STD_CEX2, STD_CEX3, STD_CEX4, and STD_CEX5 on
// Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_EPCA0EN_STD_CEX0_5_VALUE  6
#define SI32_PBCFG_A_XBAR0L_EPCA0EN_STD_CEX0_5_U32 \
   (SI32_PBCFG_A_XBAR0L_EPCA0EN_STD_CEX0_5_VALUE << SI32_PBCFG_A_XBAR0L_EPCA0EN_SHIFT)

#define SI32_PBCFG_A_XBAR0L_PCA0EN_MASK  0x0000C000
#define SI32_PBCFG_A_XBAR0L_PCA0EN_SHIFT  14
// Disable all PCA0 channels on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_PCA0EN_NONE_VALUE  0
#define SI32_PBCFG_A_XBAR0L_PCA0EN_NONE_U32 \
   (SI32_PBCFG_A_XBAR0L_PCA0EN_NONE_VALUE << SI32_PBCFG_A_XBAR0L_PCA0EN_SHIFT)
// Enable PCA0 CEX0 on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_PCA0EN_CEX0_VALUE  1
#define SI32_PBCFG_A_XBAR0L_PCA0EN_CEX0_U32 \
   (SI32_PBCFG_A_XBAR0L_PCA0EN_CEX0_VALUE << SI32_PBCFG_A_XBAR0L_PCA0EN_SHIFT)
// Enable PCA0 CEX0 and CEX1 on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_PCA0EN_CEX0_1_VALUE  3
#define SI32_PBCFG_A_XBAR0L_PCA0EN_CEX0_1_U32 \
   (SI32_PBCFG_A_XBAR0L_PCA0EN_CEX0_1_VALUE << SI32_PBCFG_A_XBAR0L_PCA0EN_SHIFT)

#define SI32_PBCFG_A_XBAR0L_PCA1EN_MASK  0x00030000
#define SI32_PBCFG_A_XBAR0L_PCA1EN_SHIFT  16
// Disable all PCA1 channels on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_PCA1EN_NONE_VALUE  0
#define SI32_PBCFG_A_XBAR0L_PCA1EN_NONE_U32 \
   (SI32_PBCFG_A_XBAR0L_PCA1EN_NONE_VALUE << SI32_PBCFG_A_XBAR0L_PCA1EN_SHIFT)
// Enable PCA1 CEX0 on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_PCA1EN_CEX0_VALUE  1
#define SI32_PBCFG_A_XBAR0L_PCA1EN_CEX0_U32 \
   (SI32_PBCFG_A_XBAR0L_PCA1EN_CEX0_VALUE << SI32_PBCFG_A_XBAR0L_PCA1EN_SHIFT)
// Enable PCA1 CEX0 and CEX1 on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_PCA1EN_CEX0_1_VALUE  3
#define SI32_PBCFG_A_XBAR0L_PCA1EN_CEX0_1_U32 \
   (SI32_PBCFG_A_XBAR0L_PCA1EN_CEX0_1_VALUE << SI32_PBCFG_A_XBAR0L_PCA1EN_SHIFT)

#define SI32_PBCFG_A_XBAR0L_EECI0EN_MASK  0x00040000
#define SI32_PBCFG_A_XBAR0L_EECI0EN_SHIFT  18
// Disable EPCA0 ECI on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_EECI0EN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR0L_EECI0EN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR0L_EECI0EN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0L_EECI0EN_SHIFT)
// Enable EPCA0 ECI on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_EECI0EN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR0L_EECI0EN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR0L_EECI0EN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0L_EECI0EN_SHIFT)

#define SI32_PBCFG_A_XBAR0L_ECI0EN_MASK  0x00080000
#define SI32_PBCFG_A_XBAR0L_ECI0EN_SHIFT  19
// Disable PCA0 ECI on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_ECI0EN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR0L_ECI0EN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR0L_ECI0EN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0L_ECI0EN_SHIFT)
// Enable PCA0 ECI on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_ECI0EN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR0L_ECI0EN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR0L_ECI0EN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0L_ECI0EN_SHIFT)

#define SI32_PBCFG_A_XBAR0L_ECI1EN_MASK  0x00100000
#define SI32_PBCFG_A_XBAR0L_ECI1EN_SHIFT  20
// Disable PCA1 ECI on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_ECI1EN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR0L_ECI1EN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR0L_ECI1EN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0L_ECI1EN_SHIFT)
// Enable PCA1 ECI on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_ECI1EN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR0L_ECI1EN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR0L_ECI1EN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0L_ECI1EN_SHIFT)

#define SI32_PBCFG_A_XBAR0L_I2S0TXEN_MASK  0x00200000
#define SI32_PBCFG_A_XBAR0L_I2S0TXEN_SHIFT  21
// Disable I2S0 TX on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_I2S0TXEN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR0L_I2S0TXEN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR0L_I2S0TXEN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0L_I2S0TXEN_SHIFT)
// Enable I2S0 TX on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_I2S0TXEN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR0L_I2S0TXEN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR0L_I2S0TXEN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0L_I2S0TXEN_SHIFT)

#define SI32_PBCFG_A_XBAR0L_I2C0EN_MASK  0x00400000
#define SI32_PBCFG_A_XBAR0L_I2C0EN_SHIFT  22
// Disable I2C0 SDA and SCL on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_I2C0EN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR0L_I2C0EN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR0L_I2C0EN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0L_I2C0EN_SHIFT)
// Enable I2C0 SDA and SCL on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_I2C0EN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR0L_I2C0EN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR0L_I2C0EN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0L_I2C0EN_SHIFT)

#define SI32_PBCFG_A_XBAR0L_CMP0SEN_MASK  0x00800000
#define SI32_PBCFG_A_XBAR0L_CMP0SEN_SHIFT  23
// Disable Comparator 0 Synchronous Output (CMP0S) on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_CMP0SEN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR0L_CMP0SEN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR0L_CMP0SEN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0L_CMP0SEN_SHIFT)
// Enable Comparator 0 Synchronous Output (CMP0S) on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_CMP0SEN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR0L_CMP0SEN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR0L_CMP0SEN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0L_CMP0SEN_SHIFT)

#define SI32_PBCFG_A_XBAR0L_CMP0AEN_MASK  0x01000000
#define SI32_PBCFG_A_XBAR0L_CMP0AEN_SHIFT  24
// Disable Comparator 0 Asynchronous Output (CMP0A) on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_CMP0AEN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR0L_CMP0AEN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR0L_CMP0AEN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0L_CMP0AEN_SHIFT)
// Enable Comparator 0 Asynchronous Output (CMP0A) on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_CMP0AEN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR0L_CMP0AEN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR0L_CMP0AEN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0L_CMP0AEN_SHIFT)

#define SI32_PBCFG_A_XBAR0L_CMP1SEN_MASK  0x02000000
#define SI32_PBCFG_A_XBAR0L_CMP1SEN_SHIFT  25
// Disable Comparator 1 Synchronous Output (CMP1S) on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_CMP1SEN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR0L_CMP1SEN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR0L_CMP1SEN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0L_CMP1SEN_SHIFT)
// Enable Comparator 1 Synchronous Output (CMP1S) on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_CMP1SEN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR0L_CMP1SEN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR0L_CMP1SEN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0L_CMP1SEN_SHIFT)

#define SI32_PBCFG_A_XBAR0L_CMP1AEN_MASK  0x04000000
#define SI32_PBCFG_A_XBAR0L_CMP1AEN_SHIFT  26
// Disable Comparator 1 Asynchronous Output (CMP1A) on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_CMP1AEN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR0L_CMP1AEN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR0L_CMP1AEN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0L_CMP1AEN_SHIFT)
// Enable Comparator 1 Asynchronous Output (CMP1A) on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_CMP1AEN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR0L_CMP1AEN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR0L_CMP1AEN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0L_CMP1AEN_SHIFT)

#define SI32_PBCFG_A_XBAR0L_TMR0CTEN_MASK  0x08000000
#define SI32_PBCFG_A_XBAR0L_TMR0CTEN_SHIFT  27
// Disable TIMER0 CT on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_TMR0CTEN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR0L_TMR0CTEN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR0L_TMR0CTEN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0L_TMR0CTEN_SHIFT)
// Enable TIMER0 CT on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_TMR0CTEN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR0L_TMR0CTEN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR0L_TMR0CTEN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0L_TMR0CTEN_SHIFT)

#define SI32_PBCFG_A_XBAR0L_TMR0EXEN_MASK  0x10000000
#define SI32_PBCFG_A_XBAR0L_TMR0EXEN_SHIFT  28
// Disable TIMER0 EX on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_TMR0EXEN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR0L_TMR0EXEN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR0L_TMR0EXEN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0L_TMR0EXEN_SHIFT)
// Enable TIMER0 EX on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_TMR0EXEN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR0L_TMR0EXEN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR0L_TMR0EXEN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0L_TMR0EXEN_SHIFT)

#define SI32_PBCFG_A_XBAR0L_TMR1CTEN_MASK  0x20000000
#define SI32_PBCFG_A_XBAR0L_TMR1CTEN_SHIFT  29
// Disable TIMER1 CT on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_TMR1CTEN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR0L_TMR1CTEN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR0L_TMR1CTEN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0L_TMR1CTEN_SHIFT)
// Enable TIMER1 CT on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_TMR1CTEN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR0L_TMR1CTEN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR0L_TMR1CTEN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0L_TMR1CTEN_SHIFT)

#define SI32_PBCFG_A_XBAR0L_TMR1EXEN_MASK  0x40000000
#define SI32_PBCFG_A_XBAR0L_TMR1EXEN_SHIFT  30
// Disable TIMER1 EX on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_TMR1EXEN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR0L_TMR1EXEN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR0L_TMR1EXEN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0L_TMR1EXEN_SHIFT)
// Enable TIMER1 EX on Crossbar 0.
#define SI32_PBCFG_A_XBAR0L_TMR1EXEN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR0L_TMR1EXEN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR0L_TMR1EXEN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0L_TMR1EXEN_SHIFT)


struct SI32_PBCFG_A_XBAR0H_Struct
{
   union
   {
      struct
      {
         // UART0 Enable
         volatile uint32_t UART0EN: 1;
         // UART0 Flow Control Enable
         volatile uint32_t UART0FCEN: 1;
         // UART1 Enable
         volatile uint32_t UART1EN: 1;
         // SPI1 Enable
         volatile uint32_t SPI1EN: 1;
         // SPI1 NSS Pin Enable
         volatile uint32_t SPI1NSSEN: 1;
         // SPI2 Enable
         volatile uint32_t SPI2EN: 1;
         // SPI2 NSS Pin Enable
         volatile uint32_t SPI2NSSEN: 1;
         // AHB Clock Output Enable
         volatile uint32_t AHBEN: 1;
                  uint32_t reserved0: 23;
         // Crossbar 0 Enable
         volatile uint32_t XBAR0EN: 1;
      };
      volatile uint32_t U32;
   };
};

#define SI32_PBCFG_A_XBAR0H_UART0EN_MASK  0x00000001
#define SI32_PBCFG_A_XBAR0H_UART0EN_SHIFT  0
// Disable UART0 RX and TX on Crossbar 0.
#define SI32_PBCFG_A_XBAR0H_UART0EN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR0H_UART0EN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR0H_UART0EN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0H_UART0EN_SHIFT)
// Enable UART0 RX and TX on Crossbar 0.
#define SI32_PBCFG_A_XBAR0H_UART0EN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR0H_UART0EN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR0H_UART0EN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0H_UART0EN_SHIFT)

#define SI32_PBCFG_A_XBAR0H_UART0FCEN_MASK  0x00000002
#define SI32_PBCFG_A_XBAR0H_UART0FCEN_SHIFT  1
// Disable UART0 flow control on Crossbar 0.
#define SI32_PBCFG_A_XBAR0H_UART0FCEN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR0H_UART0FCEN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR0H_UART0FCEN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0H_UART0FCEN_SHIFT)
// Enable UART0 flow control on Crossbar 0.
#define SI32_PBCFG_A_XBAR0H_UART0FCEN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR0H_UART0FCEN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR0H_UART0FCEN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0H_UART0FCEN_SHIFT)

#define SI32_PBCFG_A_XBAR0H_UART1EN_MASK  0x00000004
#define SI32_PBCFG_A_XBAR0H_UART1EN_SHIFT  2
// Disable UART1 RX and TX on Crossbar 0.
#define SI32_PBCFG_A_XBAR0H_UART1EN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR0H_UART1EN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR0H_UART1EN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0H_UART1EN_SHIFT)
// Enable UART1 RX and TX on Crossbar 0.
#define SI32_PBCFG_A_XBAR0H_UART1EN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR0H_UART1EN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR0H_UART1EN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0H_UART1EN_SHIFT)

#define SI32_PBCFG_A_XBAR0H_SPI1EN_MASK  0x00000008
#define SI32_PBCFG_A_XBAR0H_SPI1EN_SHIFT  3
// Disable SPI1 SCK, MISO, and MOSI on Crossbar 0.
#define SI32_PBCFG_A_XBAR0H_SPI1EN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR0H_SPI1EN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR0H_SPI1EN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0H_SPI1EN_SHIFT)
// Enable SPI1 SCK, MISO, and MOSI on Crossbar 0.
#define SI32_PBCFG_A_XBAR0H_SPI1EN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR0H_SPI1EN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR0H_SPI1EN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0H_SPI1EN_SHIFT)

#define SI32_PBCFG_A_XBAR0H_SPI1NSSEN_MASK  0x00000010
#define SI32_PBCFG_A_XBAR0H_SPI1NSSEN_SHIFT  4
// Disable SPI1 NSS on Crossbar 0.
#define SI32_PBCFG_A_XBAR0H_SPI1NSSEN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR0H_SPI1NSSEN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR0H_SPI1NSSEN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0H_SPI1NSSEN_SHIFT)
// Enable SPI1 NSS on Crossbar 0.
#define SI32_PBCFG_A_XBAR0H_SPI1NSSEN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR0H_SPI1NSSEN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR0H_SPI1NSSEN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0H_SPI1NSSEN_SHIFT)

#define SI32_PBCFG_A_XBAR0H_SPI2EN_MASK  0x00000020
#define SI32_PBCFG_A_XBAR0H_SPI2EN_SHIFT  5
// Disable SPI2 SCK, MISO, and MOSI on Crossbar 0.
#define SI32_PBCFG_A_XBAR0H_SPI2EN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR0H_SPI2EN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR0H_SPI2EN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0H_SPI2EN_SHIFT)
// Enable SPI2 SCK, MISO, and MOSI on Crossbar 0.
#define SI32_PBCFG_A_XBAR0H_SPI2EN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR0H_SPI2EN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR0H_SPI2EN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0H_SPI2EN_SHIFT)

#define SI32_PBCFG_A_XBAR0H_SPI2NSSEN_MASK  0x00000040
#define SI32_PBCFG_A_XBAR0H_SPI2NSSEN_SHIFT  6
// Disable SPI2 NSS on Crossbar 0.
#define SI32_PBCFG_A_XBAR0H_SPI2NSSEN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR0H_SPI2NSSEN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR0H_SPI2NSSEN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0H_SPI2NSSEN_SHIFT)
// Enable SPI2 NSS on Crossbar 0.
#define SI32_PBCFG_A_XBAR0H_SPI2NSSEN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR0H_SPI2NSSEN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR0H_SPI2NSSEN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0H_SPI2NSSEN_SHIFT)

#define SI32_PBCFG_A_XBAR0H_AHBEN_MASK  0x00000080
#define SI32_PBCFG_A_XBAR0H_AHBEN_SHIFT  7
// Disable the AHB Clock / 16 output on Crossbar 0.
#define SI32_PBCFG_A_XBAR0H_AHBEN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR0H_AHBEN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR0H_AHBEN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0H_AHBEN_SHIFT)
// Enable the AHB Clock / 16 output on Crossbar 0.
#define SI32_PBCFG_A_XBAR0H_AHBEN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR0H_AHBEN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR0H_AHBEN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0H_AHBEN_SHIFT)

#define SI32_PBCFG_A_XBAR0H_XBAR0EN_MASK  0x80000000
#define SI32_PBCFG_A_XBAR0H_XBAR0EN_SHIFT  31
// Disable Crossbar 0.
#define SI32_PBCFG_A_XBAR0H_XBAR0EN_DISABLED_VALUE  0U
#define SI32_PBCFG_A_XBAR0H_XBAR0EN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR0H_XBAR0EN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0H_XBAR0EN_SHIFT)
// Enable Crossbar 0.
#define SI32_PBCFG_A_XBAR0H_XBAR0EN_ENABLED_VALUE  1U
#define SI32_PBCFG_A_XBAR0H_XBAR0EN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR0H_XBAR0EN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0H_XBAR0EN_SHIFT)


struct SI32_PBCFG_A_XBAR1_Struct
{
   union
   {
      struct
      {
         // SSG0 Enable
         volatile uint32_t SSG0EN: 2;
         // Comparator 0 Synchronous Output (CMP0S) Enable
         volatile uint32_t CMP0SEN: 1;
         // Comparator 1 Synchronous Output (CMP1S) Enable
         volatile uint32_t CMP1SEN: 1;
         // SPI1 Enable
         volatile uint32_t SPI1EN: 1;
         // SPI1 NSS Pin Enable
         volatile uint32_t SPI1NSSEN: 1;
         // RTC0 Output Enable
         volatile uint32_t RTC0EN: 1;
         // SPI2 Enable
         volatile uint32_t SPI2EN: 1;
         // SPI2 NSS Pin Enable
         volatile uint32_t SPI2NSSEN: 1;
         // USART1 Enable
         volatile uint32_t USART1EN: 1;
         // USART1 Flow Control Enable
         volatile uint32_t USART1FCEN: 1;
         // USART1 Clock Signal Enable
         volatile uint32_t USART1CEN: 1;
         // UART0 Enable
         volatile uint32_t UART0EN: 1;
         // UART0 Flow Control Enable
         volatile uint32_t UART0FCEN: 1;
         // I2S0 TX Enable
         volatile uint32_t I2S0TXEN: 1;
         // I2C0 Enable
         volatile uint32_t I2C0EN: 1;
         // UART1 Enable
         volatile uint32_t UART1EN: 1;
         // I2S0 RX Enable
         volatile uint32_t I2S0RXEN: 1;
                  uint32_t reserved0: 1;
         // LPTIMER0 Output Enable
         volatile uint32_t LPT0OEN: 1;
         // I2C1 Enable
         volatile uint32_t I2C1EN: 1;
         // High Drive Kill Pin Enable
         volatile uint32_t KILLHDEN: 1;
                  uint32_t reserved1: 9;
         // Crossbar 1 Enable
         volatile uint32_t XBAR1EN: 1;
      };
      volatile uint32_t U32;
   };
};

#define SI32_PBCFG_A_XBAR1_SSG0EN_MASK  0x00000003
#define SI32_PBCFG_A_XBAR1_SSG0EN_SHIFT  0
// Disable all SSG0 channels on Crossbar 1.
#define SI32_PBCFG_A_XBAR1_SSG0EN_NONE_VALUE  0
#define SI32_PBCFG_A_XBAR1_SSG0EN_NONE_U32 \
   (SI32_PBCFG_A_XBAR1_SSG0EN_NONE_VALUE << SI32_PBCFG_A_XBAR1_SSG0EN_SHIFT)
// Enable SSG0 EX0 on Crossbar 1.
#define SI32_PBCFG_A_XBAR1_SSG0EN_EX0_VALUE  1
#define SI32_PBCFG_A_XBAR1_SSG0EN_EX0_U32 \
   (SI32_PBCFG_A_XBAR1_SSG0EN_EX0_VALUE << SI32_PBCFG_A_XBAR1_SSG0EN_SHIFT)
// Enable SSG0 EX0 and EX1 on Crossbar 1.
#define SI32_PBCFG_A_XBAR1_SSG0EN_EX0_1_VALUE  2
#define SI32_PBCFG_A_XBAR1_SSG0EN_EX0_1_U32 \
   (SI32_PBCFG_A_XBAR1_SSG0EN_EX0_1_VALUE << SI32_PBCFG_A_XBAR1_SSG0EN_SHIFT)
// Enable SSG0 EX0, EX1, EX2, and EX3 on Crossbar 1.
#define SI32_PBCFG_A_XBAR1_SSG0EN_EX0_3_VALUE  3
#define SI32_PBCFG_A_XBAR1_SSG0EN_EX0_3_U32 \
   (SI32_PBCFG_A_XBAR1_SSG0EN_EX0_3_VALUE << SI32_PBCFG_A_XBAR1_SSG0EN_SHIFT)

#define SI32_PBCFG_A_XBAR1_CMP0SEN_MASK  0x00000004
#define SI32_PBCFG_A_XBAR1_CMP0SEN_SHIFT  2
// Disable Comparator 0 Synchronous Output (CMP0S) on Crossbar 1.
#define SI32_PBCFG_A_XBAR1_CMP0SEN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR1_CMP0SEN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR1_CMP0SEN_DISABLED_VALUE << SI32_PBCFG_A_XBAR1_CMP0SEN_SHIFT)
// Enable Comparator 0 Synchronous Output (CMP0S) on Crossbar 1.
#define SI32_PBCFG_A_XBAR1_CMP0SEN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR1_CMP0SEN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR1_CMP0SEN_ENABLED_VALUE << SI32_PBCFG_A_XBAR1_CMP0SEN_SHIFT)

#define SI32_PBCFG_A_XBAR1_CMP1SEN_MASK  0x00000008
#define SI32_PBCFG_A_XBAR1_CMP1SEN_SHIFT  3
// Disable Comparator 1 Synchronous Output (CMP1S) on Crossbar 1.
#define SI32_PBCFG_A_XBAR1_CMP1SEN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR1_CMP1SEN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR1_CMP1SEN_DISABLED_VALUE << SI32_PBCFG_A_XBAR1_CMP1SEN_SHIFT)
// Enable Comparator 1 Synchronous Output (CMP1S) on Crossbar 1.
#define SI32_PBCFG_A_XBAR1_CMP1SEN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR1_CMP1SEN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR1_CMP1SEN_ENABLED_VALUE << SI32_PBCFG_A_XBAR1_CMP1SEN_SHIFT)

#define SI32_PBCFG_A_XBAR1_SPI1EN_MASK  0x00000010
#define SI32_PBCFG_A_XBAR1_SPI1EN_SHIFT  4
// Disable SPI1 SCK, MISO, and MOSI on Crossbar 1.
#define SI32_PBCFG_A_XBAR1_SPI1EN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR1_SPI1EN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR1_SPI1EN_DISABLED_VALUE << SI32_PBCFG_A_XBAR1_SPI1EN_SHIFT)
// Enable SPI1 SCK, MISO, and MOSI on Crossbar 1.
#define SI32_PBCFG_A_XBAR1_SPI1EN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR1_SPI1EN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR1_SPI1EN_ENABLED_VALUE << SI32_PBCFG_A_XBAR1_SPI1EN_SHIFT)

#define SI32_PBCFG_A_XBAR1_SPI1NSSEN_MASK  0x00000020
#define SI32_PBCFG_A_XBAR1_SPI1NSSEN_SHIFT  5
// Disable SPI1 NSS on Crossbar 1.
#define SI32_PBCFG_A_XBAR1_SPI1NSSEN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR1_SPI1NSSEN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR1_SPI1NSSEN_DISABLED_VALUE << SI32_PBCFG_A_XBAR1_SPI1NSSEN_SHIFT)
// Enable SPI1 NSS on Crossbar 1.
#define SI32_PBCFG_A_XBAR1_SPI1NSSEN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR1_SPI1NSSEN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR1_SPI1NSSEN_ENABLED_VALUE << SI32_PBCFG_A_XBAR1_SPI1NSSEN_SHIFT)

#define SI32_PBCFG_A_XBAR1_RTC0EN_MASK  0x00000040
#define SI32_PBCFG_A_XBAR1_RTC0EN_SHIFT  6
// Disable RTC0 Output on Crossbar 1.
#define SI32_PBCFG_A_XBAR1_RTC0EN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR1_RTC0EN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR1_RTC0EN_DISABLED_VALUE << SI32_PBCFG_A_XBAR1_RTC0EN_SHIFT)
// Enable RTC0 Output on Crossbar 1.
#define SI32_PBCFG_A_XBAR1_RTC0EN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR1_RTC0EN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR1_RTC0EN_ENABLED_VALUE << SI32_PBCFG_A_XBAR1_RTC0EN_SHIFT)

#define SI32_PBCFG_A_XBAR1_SPI2EN_MASK  0x00000080
#define SI32_PBCFG_A_XBAR1_SPI2EN_SHIFT  7
// Disable SPI2 SCK, MISO, and MOSI on Crossbar 1.
#define SI32_PBCFG_A_XBAR1_SPI2EN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR1_SPI2EN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR1_SPI2EN_DISABLED_VALUE << SI32_PBCFG_A_XBAR1_SPI2EN_SHIFT)
// Enable SPI2 SCK, MISO, and MOSI on Crossbar 1.
#define SI32_PBCFG_A_XBAR1_SPI2EN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR1_SPI2EN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR1_SPI2EN_ENABLED_VALUE << SI32_PBCFG_A_XBAR1_SPI2EN_SHIFT)

#define SI32_PBCFG_A_XBAR1_SPI2NSSEN_MASK  0x00000100
#define SI32_PBCFG_A_XBAR1_SPI2NSSEN_SHIFT  8
// Disable SPI2 NSS on Crossbar 1.
#define SI32_PBCFG_A_XBAR1_SPI2NSSEN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR1_SPI2NSSEN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR1_SPI2NSSEN_DISABLED_VALUE << SI32_PBCFG_A_XBAR1_SPI2NSSEN_SHIFT)
// Enable SPI2 NSS on Crossbar 1.
#define SI32_PBCFG_A_XBAR1_SPI2NSSEN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR1_SPI2NSSEN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR1_SPI2NSSEN_ENABLED_VALUE << SI32_PBCFG_A_XBAR1_SPI2NSSEN_SHIFT)

#define SI32_PBCFG_A_XBAR1_USART1EN_MASK  0x00000200
#define SI32_PBCFG_A_XBAR1_USART1EN_SHIFT  9
// Disable USART1 RX and TX on Crossbar 1.
#define SI32_PBCFG_A_XBAR1_USART1EN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR1_USART1EN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR1_USART1EN_DISABLED_VALUE << SI32_PBCFG_A_XBAR1_USART1EN_SHIFT)
// Enable USART1 RX and TX on Crossbar 1.
#define SI32_PBCFG_A_XBAR1_USART1EN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR1_USART1EN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR1_USART1EN_ENABLED_VALUE << SI32_PBCFG_A_XBAR1_USART1EN_SHIFT)

#define SI32_PBCFG_A_XBAR1_USART1FCEN_MASK  0x00000400
#define SI32_PBCFG_A_XBAR1_USART1FCEN_SHIFT  10
// Disable USART1 flow control on Crossbar 1.
#define SI32_PBCFG_A_XBAR1_USART1FCEN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR1_USART1FCEN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR1_USART1FCEN_DISABLED_VALUE << SI32_PBCFG_A_XBAR1_USART1FCEN_SHIFT)
// Enable USART1 flow control on Crossbar 1.
#define SI32_PBCFG_A_XBAR1_USART1FCEN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR1_USART1FCEN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR1_USART1FCEN_ENABLED_VALUE << SI32_PBCFG_A_XBAR1_USART1FCEN_SHIFT)

#define SI32_PBCFG_A_XBAR1_USART1CEN_MASK  0x00000800
#define SI32_PBCFG_A_XBAR1_USART1CEN_SHIFT  11
// Disable USART1 clock on Crossbar 1.
#define SI32_PBCFG_A_XBAR1_USART1CEN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR1_USART1CEN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR1_USART1CEN_DISABLED_VALUE << SI32_PBCFG_A_XBAR1_USART1CEN_SHIFT)
// Enable USART1 clock on Crossbar 1.
#define SI32_PBCFG_A_XBAR1_USART1CEN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR1_USART1CEN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR1_USART1CEN_ENABLED_VALUE << SI32_PBCFG_A_XBAR1_USART1CEN_SHIFT)

#define SI32_PBCFG_A_XBAR1_UART0EN_MASK  0x00001000
#define SI32_PBCFG_A_XBAR1_UART0EN_SHIFT  12
// Disable UART0 RX and TX on Crossbar 1.
#define SI32_PBCFG_A_XBAR1_UART0EN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR1_UART0EN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR1_UART0EN_DISABLED_VALUE << SI32_PBCFG_A_XBAR1_UART0EN_SHIFT)
// Enable UART0 RX and TX on Crossbar 1.
#define SI32_PBCFG_A_XBAR1_UART0EN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR1_UART0EN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR1_UART0EN_ENABLED_VALUE << SI32_PBCFG_A_XBAR1_UART0EN_SHIFT)

#define SI32_PBCFG_A_XBAR1_UART0FCEN_MASK  0x00002000
#define SI32_PBCFG_A_XBAR1_UART0FCEN_SHIFT  13
// Disable UART0 flow control on Crossbar 1.
#define SI32_PBCFG_A_XBAR1_UART0FCEN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR1_UART0FCEN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR1_UART0FCEN_DISABLED_VALUE << SI32_PBCFG_A_XBAR1_UART0FCEN_SHIFT)
// Enable UART0 flow control on Crossbar1.
#define SI32_PBCFG_A_XBAR1_UART0FCEN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR1_UART0FCEN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR1_UART0FCEN_ENABLED_VALUE << SI32_PBCFG_A_XBAR1_UART0FCEN_SHIFT)

#define SI32_PBCFG_A_XBAR1_I2S0TXEN_MASK  0x00004000
#define SI32_PBCFG_A_XBAR1_I2S0TXEN_SHIFT  14
// Disable I2S0 TX on Crossbar 1.
#define SI32_PBCFG_A_XBAR1_I2S0TXEN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR1_I2S0TXEN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR1_I2S0TXEN_DISABLED_VALUE << SI32_PBCFG_A_XBAR1_I2S0TXEN_SHIFT)
// Enable I2S0 TX on Crossbar 1.
#define SI32_PBCFG_A_XBAR1_I2S0TXEN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR1_I2S0TXEN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR1_I2S0TXEN_ENABLED_VALUE << SI32_PBCFG_A_XBAR1_I2S0TXEN_SHIFT)

#define SI32_PBCFG_A_XBAR1_I2C0EN_MASK  0x00008000
#define SI32_PBCFG_A_XBAR1_I2C0EN_SHIFT  15
// Disable I2C0 SDA and SCL on Crossbar 1.
#define SI32_PBCFG_A_XBAR1_I2C0EN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR1_I2C0EN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR1_I2C0EN_DISABLED_VALUE << SI32_PBCFG_A_XBAR1_I2C0EN_SHIFT)
// Enable I2C0 SDA and SCL on Crossbar 1.
#define SI32_PBCFG_A_XBAR1_I2C0EN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR1_I2C0EN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR1_I2C0EN_ENABLED_VALUE << SI32_PBCFG_A_XBAR1_I2C0EN_SHIFT)

#define SI32_PBCFG_A_XBAR1_UART1EN_MASK  0x00010000
#define SI32_PBCFG_A_XBAR1_UART1EN_SHIFT  16
// Disable UART1 RX and TX on Crossbar 1.
#define SI32_PBCFG_A_XBAR1_UART1EN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR1_UART1EN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR1_UART1EN_DISABLED_VALUE << SI32_PBCFG_A_XBAR1_UART1EN_SHIFT)
// Enable UART1 RX and TX on Crossbar 1.
#define SI32_PBCFG_A_XBAR1_UART1EN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR1_UART1EN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR1_UART1EN_ENABLED_VALUE << SI32_PBCFG_A_XBAR1_UART1EN_SHIFT)

#define SI32_PBCFG_A_XBAR1_I2S0RXEN_MASK  0x00020000
#define SI32_PBCFG_A_XBAR1_I2S0RXEN_SHIFT  17
// Disable I2S0 RX on Crossbar 1.
#define SI32_PBCFG_A_XBAR1_I2S0RXEN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR1_I2S0RXEN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR1_I2S0RXEN_DISABLED_VALUE << SI32_PBCFG_A_XBAR1_I2S0RXEN_SHIFT)
// Enable I2S0 RX on Crossbar 1.
#define SI32_PBCFG_A_XBAR1_I2S0RXEN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR1_I2S0RXEN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR1_I2S0RXEN_ENABLED_VALUE << SI32_PBCFG_A_XBAR1_I2S0RXEN_SHIFT)

#define SI32_PBCFG_A_XBAR1_LPT0OEN_MASK  0x00080000
#define SI32_PBCFG_A_XBAR1_LPT0OEN_SHIFT  19
// Disable LPTIMER0 Output on Crossbar 1.
#define SI32_PBCFG_A_XBAR1_LPT0OEN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR1_LPT0OEN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR1_LPT0OEN_DISABLED_VALUE << SI32_PBCFG_A_XBAR1_LPT0OEN_SHIFT)
// Enable LPTIMER0 Output on Crossbar 1.
#define SI32_PBCFG_A_XBAR1_LPT0OEN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR1_LPT0OEN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR1_LPT0OEN_ENABLED_VALUE << SI32_PBCFG_A_XBAR1_LPT0OEN_SHIFT)

#define SI32_PBCFG_A_XBAR1_I2C1EN_MASK  0x00100000
#define SI32_PBCFG_A_XBAR1_I2C1EN_SHIFT  20
// Disable I2C1 SDA and SCL on Crossbar 1.
#define SI32_PBCFG_A_XBAR1_I2C1EN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR1_I2C1EN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR1_I2C1EN_DISABLED_VALUE << SI32_PBCFG_A_XBAR1_I2C1EN_SHIFT)
// Enable I2C1 SDA and SCL on Crossbar 1.
#define SI32_PBCFG_A_XBAR1_I2C1EN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR1_I2C1EN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR1_I2C1EN_ENABLED_VALUE << SI32_PBCFG_A_XBAR1_I2C1EN_SHIFT)

#define SI32_PBCFG_A_XBAR1_KILLHDEN_MASK  0x00200000
#define SI32_PBCFG_A_XBAR1_KILLHDEN_SHIFT  21
// Disable the PB High Drive Kill Pin on Crossbar 1.
#define SI32_PBCFG_A_XBAR1_KILLHDEN_DISABLED_VALUE  0
#define SI32_PBCFG_A_XBAR1_KILLHDEN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR1_KILLHDEN_DISABLED_VALUE << SI32_PBCFG_A_XBAR1_KILLHDEN_SHIFT)
// Enable the PB High Drive Kill Pin on Crossbar 1.
#define SI32_PBCFG_A_XBAR1_KILLHDEN_ENABLED_VALUE  1
#define SI32_PBCFG_A_XBAR1_KILLHDEN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR1_KILLHDEN_ENABLED_VALUE << SI32_PBCFG_A_XBAR1_KILLHDEN_SHIFT)

#define SI32_PBCFG_A_XBAR1_XBAR1EN_MASK  0x80000000
#define SI32_PBCFG_A_XBAR1_XBAR1EN_SHIFT  31
// Disable Crossbar 1.
#define SI32_PBCFG_A_XBAR1_XBAR1EN_DISABLED_VALUE  0U
#define SI32_PBCFG_A_XBAR1_XBAR1EN_DISABLED_U32 \
   (SI32_PBCFG_A_XBAR1_XBAR1EN_DISABLED_VALUE << SI32_PBCFG_A_XBAR1_XBAR1EN_SHIFT)
// Enable Crossbar 1.
#define SI32_PBCFG_A_XBAR1_XBAR1EN_ENABLED_VALUE  1U
#define SI32_PBCFG_A_XBAR1_XBAR1EN_ENABLED_U32 \
   (SI32_PBCFG_A_XBAR1_XBAR1EN_ENABLED_VALUE << SI32_PBCFG_A_XBAR1_XBAR1EN_SHIFT)


struct SI32_PBCFG_A_PBKEY_Struct
{
   union
   {
      struct
      {
         // Port Bank 2, 3, and 4 Key
         volatile uint8_t KEY;
                  uint32_t reserved0: 24;
      };
      volatile uint32_t U32;
   };
};

#define SI32_PBCFG_A_PBKEY_KEY_MASK  0x000000FF
#define SI32_PBCFG_A_PBKEY_KEY_SHIFT  0
// Port Bank 2, 3, and 4 registers are locked and no valid values have been written
// to PBKEY.
#define SI32_PBCFG_A_PBKEY_KEY_LOCKED_VALUE  0
#define SI32_PBCFG_A_PBKEY_KEY_LOCKED_U32 \
   (SI32_PBCFG_A_PBKEY_KEY_LOCKED_VALUE << SI32_PBCFG_A_PBKEY_KEY_SHIFT)
// Port Bank 2, 3, and 4 registers are locked and the first valid value (0xA5) has
// been written to PBKEY.
#define SI32_PBCFG_A_PBKEY_KEY_INTERMEDIATE_VALUE  1
#define SI32_PBCFG_A_PBKEY_KEY_INTERMEDIATE_U32 \
   (SI32_PBCFG_A_PBKEY_KEY_INTERMEDIATE_VALUE << SI32_PBCFG_A_PBKEY_KEY_SHIFT)
// Port Bank 2, 3, and 4 registers are unlocked. Any subsequent writes to the Port
// Bank 2, 3, or 4 registers or PBKEY will lock the interface.
#define SI32_PBCFG_A_PBKEY_KEY_UNLOCKED_VALUE  2
#define SI32_PBCFG_A_PBKEY_KEY_UNLOCKED_U32 \
   (SI32_PBCFG_A_PBKEY_KEY_UNLOCKED_VALUE << SI32_PBCFG_A_PBKEY_KEY_SHIFT)


typedef struct SI32_PBCFG_A_Struct
{
   struct SI32_PBCFG_A_CONTROL0_Struct             CONTROL0       ; // Base Address + 0x0
   volatile uint32_t                               CONTROL0_SET;
   volatile uint32_t                               CONTROL0_CLR;
   uint32_t                                        reserved0;
   struct SI32_PBCFG_A_CONTROL1_Struct             CONTROL1       ; // Base Address + 0x10
   volatile uint32_t                               CONTROL1_SET;
   volatile uint32_t                               CONTROL1_CLR;
   uint32_t                                        reserved1;
   struct SI32_PBCFG_A_XBAR0L_Struct               XBAR0L         ; // Base Address + 0x20
   volatile uint32_t                               XBAR0L_SET;
   volatile uint32_t                               XBAR0L_CLR;
   uint32_t                                        reserved2;
   struct SI32_PBCFG_A_XBAR0H_Struct               XBAR0H         ; // Base Address + 0x30
   volatile uint32_t                               XBAR0H_SET;
   volatile uint32_t                               XBAR0H_CLR;
   uint32_t                                        reserved3;
   struct SI32_PBCFG_A_XBAR1_Struct                XBAR1          ; // Base Address + 0x40
   volatile uint32_t                               XBAR1_SET;
   volatile uint32_t                               XBAR1_CLR;
   uint32_t                                        reserved4;
   struct SI32_PBCFG_A_PBKEY_Struct                PBKEY          ; // Base Address + 0x50
   uint32_t                                        reserved5;
   uint32_t                                        reserved6;
   uint32_t                                        reserved7;
} SI32_PBCFG_A_Type;

#ifdef __cplusplus
}
#endif

#endif // __SI32_PBCFG_A_REGISTERS_H__

//-eof--------------------------------------------------------------------------