1 //------------------------------------------------------------------------------ 2 // Copyright 2012 (c) Silicon Laboratories Inc. 3 // 4 // SPDX-License-Identifier: Zlib 5 // 6 // This siHAL software is provided 'as-is', without any express or implied 7 // warranty. In no event will the authors be held liable for any damages 8 // arising from the use of this software. 9 // 10 // Permission is granted to anyone to use this software for any purpose, 11 // including commercial applications, and to alter it and redistribute it 12 // freely, subject to the following restrictions: 13 // 14 // 1. The origin of this software must not be misrepresented; you must not 15 // claim that you wrote the original software. If you use this software 16 // in a product, an acknowledgment in the product documentation would be 17 // appreciated but is not required. 18 // 2. Altered source versions must be plainly marked as such, and must not be 19 // misrepresented as being the original software. 20 // 3. This notice may not be removed or altered from any source distribution. 21 //------------------------------------------------------------------------------ 22 // 23 // This file applies to the SIM3U1XX_LOCK_A module 24 // 25 // Script: 0.57 26 // Version: 1 27 28 #ifndef __SI32_LOCK_A_REGISTERS_H__ 29 #define __SI32_LOCK_A_REGISTERS_H__ 30 31 #include <stdint.h> 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 struct SI32_LOCK_A_KEY_Struct 38 { 39 union 40 { 41 struct 42 { 43 // Peripheral Lock Mask Key 44 volatile uint8_t KEY_BITS; 45 uint32_t reserved0: 24; 46 }; 47 volatile uint32_t U32; 48 }; 49 }; 50 51 #define SI32_LOCK_A_KEY_KEY_MASK 0x000000FF 52 #define SI32_LOCK_A_KEY_KEY_SHIFT 0 53 // PERIPHLOCK registers are locked and no valid values have been written to KEY. 54 #define SI32_LOCK_A_KEY_KEY_LOCKED_VALUE 0 55 #define SI32_LOCK_A_KEY_KEY_LOCKED_U32 \ 56 (SI32_LOCK_A_KEY_KEY_LOCKED_VALUE << SI32_LOCK_A_KEY_KEY_SHIFT) 57 // PERIPHLOCK registers are locked and the first valid value (0xA5) has been 58 // written to KEY. 59 #define SI32_LOCK_A_KEY_KEY_INTERMEDIATE_VALUE 1 60 #define SI32_LOCK_A_KEY_KEY_INTERMEDIATE_U32 \ 61 (SI32_LOCK_A_KEY_KEY_INTERMEDIATE_VALUE << SI32_LOCK_A_KEY_KEY_SHIFT) 62 // PERIPHLOCK registers are unlocked. Any subsequent writes to KEY will lock the 63 // interface. 64 #define SI32_LOCK_A_KEY_KEY_UNLOCKED_VALUE 2 65 #define SI32_LOCK_A_KEY_KEY_UNLOCKED_U32 \ 66 (SI32_LOCK_A_KEY_KEY_UNLOCKED_VALUE << SI32_LOCK_A_KEY_KEY_SHIFT) 67 68 69 70 struct SI32_LOCK_A_PERIPHLOCK0_Struct 71 { 72 union 73 { 74 struct 75 { 76 // USART/UART Module Lock Enable 77 volatile uint32_t USARTL: 1; 78 // SPI Module Lock Enable 79 volatile uint32_t SPIL: 1; 80 // I2C Module Lock Enable 81 volatile uint32_t I2CL: 1; 82 // PCA Module Lock Enable 83 volatile uint32_t PCAL: 1; 84 // Timer Module Lock Enable 85 volatile uint32_t TIMERL: 1; 86 // USB Module Lock Enable 87 volatile uint32_t USBL: 1; 88 // SARADC Module Lock Enable 89 volatile uint32_t SARADCL: 1; 90 // SSG Module Lock Enable 91 volatile uint32_t SSGL: 1; 92 // Comparator Module Lock Enable 93 volatile uint32_t CMPL: 1; 94 // Capacitive Sensing Module Lock Enable 95 volatile uint32_t CSL: 1; 96 // EMIF Module Lock Enable 97 volatile uint32_t EMIFL: 1; 98 // AES Module Lock Enable 99 volatile uint32_t AESL: 1; 100 // CRC Module Lock Enable 101 volatile uint32_t CRCL: 1; 102 // RTC Module Lock Enable 103 volatile uint32_t RTCL: 1; 104 // Clock Control and Reset Sources Lock Enable 105 volatile uint32_t CLKRSTL: 1; 106 // Voltage Supply Monitor Module Lock Enable 107 volatile uint32_t VMONL: 1; 108 // IDAC Module Lock Enable 109 volatile uint32_t IDACL: 1; 110 // DMA Controller Module Lock Enable 111 volatile uint32_t DMACTRLL: 1; 112 // DMA Crossbar Module Lock Enable 113 volatile uint32_t DMAXBARL: 1; 114 // Low Power Timer Module Lock Enable 115 volatile uint32_t LPTL: 1; 116 // Voltage Reference Module Lock Enable 117 volatile uint32_t VREFL: 1; 118 // I2S Module Lock Enable 119 volatile uint32_t I2SL: 1; 120 // PLL Module Lock Enable 121 volatile uint32_t PLLL: 1; 122 // External Oscillator Module Lock Enable 123 volatile uint32_t EXTOSCL: 1; 124 // Voltage Regulator Module Lock Enable 125 volatile uint32_t VREGL: 1; 126 // Low Power Oscillator Lock Enable 127 volatile uint32_t LPOSCL: 1; 128 // External Regulator Module Lock Enable 129 volatile uint32_t EVREGL: 1; 130 uint32_t reserved0: 1; 131 // IVC Module Lock Enable 132 volatile uint32_t IVCL: 1; 133 uint32_t reserved1: 3; 134 }; 135 volatile uint32_t U32; 136 }; 137 }; 138 139 #define SI32_LOCK_A_PERIPHLOCK0_USARTL_MASK 0x00000001 140 #define SI32_LOCK_A_PERIPHLOCK0_USARTL_SHIFT 0 141 // Unlock the USART0, USART1, UART0, and UART1 Module registers. 142 #define SI32_LOCK_A_PERIPHLOCK0_USARTL_UNLOCKED_VALUE 0 143 #define SI32_LOCK_A_PERIPHLOCK0_USARTL_UNLOCKED_U32 \ 144 (SI32_LOCK_A_PERIPHLOCK0_USARTL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_USARTL_SHIFT) 145 // Lock the USART0, USART1, UART0, and UART1 Module registers (bits can still be 146 // read). 147 #define SI32_LOCK_A_PERIPHLOCK0_USARTL_LOCKED_VALUE 1 148 #define SI32_LOCK_A_PERIPHLOCK0_USARTL_LOCKED_U32 \ 149 (SI32_LOCK_A_PERIPHLOCK0_USARTL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_USARTL_SHIFT) 150 151 #define SI32_LOCK_A_PERIPHLOCK0_SPIL_MASK 0x00000002 152 #define SI32_LOCK_A_PERIPHLOCK0_SPIL_SHIFT 1 153 // Unlock the SPI0, SPI1, and SPI2 Module registers. 154 #define SI32_LOCK_A_PERIPHLOCK0_SPIL_UNLOCKED_VALUE 0 155 #define SI32_LOCK_A_PERIPHLOCK0_SPIL_UNLOCKED_U32 \ 156 (SI32_LOCK_A_PERIPHLOCK0_SPIL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_SPIL_SHIFT) 157 // Lock the SPI0, SPI1, and SPI2 Module registers (bits can still be read). 158 #define SI32_LOCK_A_PERIPHLOCK0_SPIL_LOCKED_VALUE 1 159 #define SI32_LOCK_A_PERIPHLOCK0_SPIL_LOCKED_U32 \ 160 (SI32_LOCK_A_PERIPHLOCK0_SPIL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_SPIL_SHIFT) 161 162 #define SI32_LOCK_A_PERIPHLOCK0_I2CL_MASK 0x00000004 163 #define SI32_LOCK_A_PERIPHLOCK0_I2CL_SHIFT 2 164 // Unlock the I2C0 and I2C1 Module registers. 165 #define SI32_LOCK_A_PERIPHLOCK0_I2CL_UNLOCKED_VALUE 0 166 #define SI32_LOCK_A_PERIPHLOCK0_I2CL_UNLOCKED_U32 \ 167 (SI32_LOCK_A_PERIPHLOCK0_I2CL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_I2CL_SHIFT) 168 // Lock the I2C0 and I2C1 Module registers (bits can still be read). 169 #define SI32_LOCK_A_PERIPHLOCK0_I2CL_LOCKED_VALUE 1 170 #define SI32_LOCK_A_PERIPHLOCK0_I2CL_LOCKED_U32 \ 171 (SI32_LOCK_A_PERIPHLOCK0_I2CL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_I2CL_SHIFT) 172 173 #define SI32_LOCK_A_PERIPHLOCK0_PCAL_MASK 0x00000008 174 #define SI32_LOCK_A_PERIPHLOCK0_PCAL_SHIFT 3 175 // Unlock the EPCA0, PCA0, and PCA1 Module registers. 176 #define SI32_LOCK_A_PERIPHLOCK0_PCAL_UNLOCKED_VALUE 0 177 #define SI32_LOCK_A_PERIPHLOCK0_PCAL_UNLOCKED_U32 \ 178 (SI32_LOCK_A_PERIPHLOCK0_PCAL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_PCAL_SHIFT) 179 // Lock the EPCA0, PCA0, and PCA1 Module registers (bits can still be read). 180 #define SI32_LOCK_A_PERIPHLOCK0_PCAL_LOCKED_VALUE 1 181 #define SI32_LOCK_A_PERIPHLOCK0_PCAL_LOCKED_U32 \ 182 (SI32_LOCK_A_PERIPHLOCK0_PCAL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_PCAL_SHIFT) 183 184 #define SI32_LOCK_A_PERIPHLOCK0_TIMERL_MASK 0x00000010 185 #define SI32_LOCK_A_PERIPHLOCK0_TIMERL_SHIFT 4 186 // Unlock the TIMER0 and TIMER1 Module registers. 187 #define SI32_LOCK_A_PERIPHLOCK0_TIMERL_UNLOCKED_VALUE 0 188 #define SI32_LOCK_A_PERIPHLOCK0_TIMERL_UNLOCKED_U32 \ 189 (SI32_LOCK_A_PERIPHLOCK0_TIMERL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_TIMERL_SHIFT) 190 // Lock the TIMER0 and TIMER1 Module registers (bits can still be read). 191 #define SI32_LOCK_A_PERIPHLOCK0_TIMERL_LOCKED_VALUE 1 192 #define SI32_LOCK_A_PERIPHLOCK0_TIMERL_LOCKED_U32 \ 193 (SI32_LOCK_A_PERIPHLOCK0_TIMERL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_TIMERL_SHIFT) 194 195 #define SI32_LOCK_A_PERIPHLOCK0_USBL_MASK 0x00000020 196 #define SI32_LOCK_A_PERIPHLOCK0_USBL_SHIFT 5 197 // Unlock the USB0 Module registers. 198 #define SI32_LOCK_A_PERIPHLOCK0_USBL_UNLOCKED_VALUE 0 199 #define SI32_LOCK_A_PERIPHLOCK0_USBL_UNLOCKED_U32 \ 200 (SI32_LOCK_A_PERIPHLOCK0_USBL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_USBL_SHIFT) 201 // Lock the USB0 Module registers (bits can still be read). 202 #define SI32_LOCK_A_PERIPHLOCK0_USBL_LOCKED_VALUE 1 203 #define SI32_LOCK_A_PERIPHLOCK0_USBL_LOCKED_U32 \ 204 (SI32_LOCK_A_PERIPHLOCK0_USBL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_USBL_SHIFT) 205 206 #define SI32_LOCK_A_PERIPHLOCK0_SARADCL_MASK 0x00000040 207 #define SI32_LOCK_A_PERIPHLOCK0_SARADCL_SHIFT 6 208 // Unlock the SARADC0 and SARADC1 Module registers. 209 #define SI32_LOCK_A_PERIPHLOCK0_SARADCL_UNLOCKED_VALUE 0 210 #define SI32_LOCK_A_PERIPHLOCK0_SARADCL_UNLOCKED_U32 \ 211 (SI32_LOCK_A_PERIPHLOCK0_SARADCL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_SARADCL_SHIFT) 212 // Lock the SARADC0 and SARADC1 Module registers (bits can still be read). 213 #define SI32_LOCK_A_PERIPHLOCK0_SARADCL_LOCKED_VALUE 1 214 #define SI32_LOCK_A_PERIPHLOCK0_SARADCL_LOCKED_U32 \ 215 (SI32_LOCK_A_PERIPHLOCK0_SARADCL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_SARADCL_SHIFT) 216 217 #define SI32_LOCK_A_PERIPHLOCK0_SSGL_MASK 0x00000080 218 #define SI32_LOCK_A_PERIPHLOCK0_SSGL_SHIFT 7 219 // Unlock the SSG0 Module registers. 220 #define SI32_LOCK_A_PERIPHLOCK0_SSGL_UNLOCKED_VALUE 0 221 #define SI32_LOCK_A_PERIPHLOCK0_SSGL_UNLOCKED_U32 \ 222 (SI32_LOCK_A_PERIPHLOCK0_SSGL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_SSGL_SHIFT) 223 // Lock the SSG0 Module registers (bits can still be read). 224 #define SI32_LOCK_A_PERIPHLOCK0_SSGL_LOCKED_VALUE 1 225 #define SI32_LOCK_A_PERIPHLOCK0_SSGL_LOCKED_U32 \ 226 (SI32_LOCK_A_PERIPHLOCK0_SSGL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_SSGL_SHIFT) 227 228 #define SI32_LOCK_A_PERIPHLOCK0_CMPL_MASK 0x00000100 229 #define SI32_LOCK_A_PERIPHLOCK0_CMPL_SHIFT 8 230 // Unlock the Comparator 0 and Comparator 1 Module registers. 231 #define SI32_LOCK_A_PERIPHLOCK0_CMPL_UNLOCKED_VALUE 0 232 #define SI32_LOCK_A_PERIPHLOCK0_CMPL_UNLOCKED_U32 \ 233 (SI32_LOCK_A_PERIPHLOCK0_CMPL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_CMPL_SHIFT) 234 // Lock the Comparator 0 and Comparator 1 Module registers (bits can still be 235 // read). 236 #define SI32_LOCK_A_PERIPHLOCK0_CMPL_LOCKED_VALUE 1 237 #define SI32_LOCK_A_PERIPHLOCK0_CMPL_LOCKED_U32 \ 238 (SI32_LOCK_A_PERIPHLOCK0_CMPL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_CMPL_SHIFT) 239 240 #define SI32_LOCK_A_PERIPHLOCK0_CSL_MASK 0x00000200 241 #define SI32_LOCK_A_PERIPHLOCK0_CSL_SHIFT 9 242 // Unlock the Capacitive Sensing (CAPSENSE0) Module registers. 243 #define SI32_LOCK_A_PERIPHLOCK0_CSL_UNLOCKED_VALUE 0 244 #define SI32_LOCK_A_PERIPHLOCK0_CSL_UNLOCKED_U32 \ 245 (SI32_LOCK_A_PERIPHLOCK0_CSL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_CSL_SHIFT) 246 // Lock the Capacitive Sensing (CAPSENSE0) Module registers (bits can still be 247 // read). 248 #define SI32_LOCK_A_PERIPHLOCK0_CSL_LOCKED_VALUE 1 249 #define SI32_LOCK_A_PERIPHLOCK0_CSL_LOCKED_U32 \ 250 (SI32_LOCK_A_PERIPHLOCK0_CSL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_CSL_SHIFT) 251 252 #define SI32_LOCK_A_PERIPHLOCK0_EMIFL_MASK 0x00000400 253 #define SI32_LOCK_A_PERIPHLOCK0_EMIFL_SHIFT 10 254 // Unlock the External Memory Interface (EMIF0) Module registers. 255 #define SI32_LOCK_A_PERIPHLOCK0_EMIFL_UNLOCKED_VALUE 0 256 #define SI32_LOCK_A_PERIPHLOCK0_EMIFL_UNLOCKED_U32 \ 257 (SI32_LOCK_A_PERIPHLOCK0_EMIFL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_EMIFL_SHIFT) 258 // Lock the External Memory Interface (EMIF0) Module registers (bits can still be 259 // read). 260 #define SI32_LOCK_A_PERIPHLOCK0_EMIFL_LOCKED_VALUE 1 261 #define SI32_LOCK_A_PERIPHLOCK0_EMIFL_LOCKED_U32 \ 262 (SI32_LOCK_A_PERIPHLOCK0_EMIFL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_EMIFL_SHIFT) 263 264 #define SI32_LOCK_A_PERIPHLOCK0_AESL_MASK 0x00000800 265 #define SI32_LOCK_A_PERIPHLOCK0_AESL_SHIFT 11 266 // Unlock the AES0 Module registers. 267 #define SI32_LOCK_A_PERIPHLOCK0_AESL_UNLOCKED_VALUE 0 268 #define SI32_LOCK_A_PERIPHLOCK0_AESL_UNLOCKED_U32 \ 269 (SI32_LOCK_A_PERIPHLOCK0_AESL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_AESL_SHIFT) 270 // Lock the AES0 Module registers (bits can still be read). 271 #define SI32_LOCK_A_PERIPHLOCK0_AESL_LOCKED_VALUE 1 272 #define SI32_LOCK_A_PERIPHLOCK0_AESL_LOCKED_U32 \ 273 (SI32_LOCK_A_PERIPHLOCK0_AESL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_AESL_SHIFT) 274 275 #define SI32_LOCK_A_PERIPHLOCK0_CRCL_MASK 0x00001000 276 #define SI32_LOCK_A_PERIPHLOCK0_CRCL_SHIFT 12 277 // Unlock the CRC0 Module registers. 278 #define SI32_LOCK_A_PERIPHLOCK0_CRCL_UNLOCKED_VALUE 0 279 #define SI32_LOCK_A_PERIPHLOCK0_CRCL_UNLOCKED_U32 \ 280 (SI32_LOCK_A_PERIPHLOCK0_CRCL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_CRCL_SHIFT) 281 // Lock the CRC0 Module registers (bits can still be read). 282 #define SI32_LOCK_A_PERIPHLOCK0_CRCL_LOCKED_VALUE 1 283 #define SI32_LOCK_A_PERIPHLOCK0_CRCL_LOCKED_U32 \ 284 (SI32_LOCK_A_PERIPHLOCK0_CRCL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_CRCL_SHIFT) 285 286 #define SI32_LOCK_A_PERIPHLOCK0_RTCL_MASK 0x00002000 287 #define SI32_LOCK_A_PERIPHLOCK0_RTCL_SHIFT 13 288 // Unlock the RTC0 Module registers. 289 #define SI32_LOCK_A_PERIPHLOCK0_RTCL_UNLOCKED_VALUE 0 290 #define SI32_LOCK_A_PERIPHLOCK0_RTCL_UNLOCKED_U32 \ 291 (SI32_LOCK_A_PERIPHLOCK0_RTCL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_RTCL_SHIFT) 292 // Lock the RTC0 Module registers (bits can still be read). 293 #define SI32_LOCK_A_PERIPHLOCK0_RTCL_LOCKED_VALUE 1 294 #define SI32_LOCK_A_PERIPHLOCK0_RTCL_LOCKED_U32 \ 295 (SI32_LOCK_A_PERIPHLOCK0_RTCL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_RTCL_SHIFT) 296 297 #define SI32_LOCK_A_PERIPHLOCK0_CLKRSTL_MASK 0x00004000 298 #define SI32_LOCK_A_PERIPHLOCK0_CLKRSTL_SHIFT 14 299 // Unlock the Clock Control (CLKCTRL) and Reset Sources (RSTSRC) Module registers. 300 #define SI32_LOCK_A_PERIPHLOCK0_CLKRSTL_UNLOCKED_VALUE 0 301 #define SI32_LOCK_A_PERIPHLOCK0_CLKRSTL_UNLOCKED_U32 \ 302 (SI32_LOCK_A_PERIPHLOCK0_CLKRSTL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_CLKRSTL_SHIFT) 303 // Lock the Clock Control (CLKCTRL) and Reset Sources (RSTSRC) Module registers 304 // (bits can still be read). 305 #define SI32_LOCK_A_PERIPHLOCK0_CLKRSTL_LOCKED_VALUE 1 306 #define SI32_LOCK_A_PERIPHLOCK0_CLKRSTL_LOCKED_U32 \ 307 (SI32_LOCK_A_PERIPHLOCK0_CLKRSTL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_CLKRSTL_SHIFT) 308 309 #define SI32_LOCK_A_PERIPHLOCK0_VMONL_MASK 0x00008000 310 #define SI32_LOCK_A_PERIPHLOCK0_VMONL_SHIFT 15 311 // Unlock the Voltage Supply Monitor (VMON0) Module registers. 312 #define SI32_LOCK_A_PERIPHLOCK0_VMONL_UNLOCKED_VALUE 0 313 #define SI32_LOCK_A_PERIPHLOCK0_VMONL_UNLOCKED_U32 \ 314 (SI32_LOCK_A_PERIPHLOCK0_VMONL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_VMONL_SHIFT) 315 // Lock the Voltage Supply Monitor (VMON0) Module registers (bits can still be 316 // read). 317 #define SI32_LOCK_A_PERIPHLOCK0_VMONL_LOCKED_VALUE 1 318 #define SI32_LOCK_A_PERIPHLOCK0_VMONL_LOCKED_U32 \ 319 (SI32_LOCK_A_PERIPHLOCK0_VMONL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_VMONL_SHIFT) 320 321 #define SI32_LOCK_A_PERIPHLOCK0_IDACL_MASK 0x00010000 322 #define SI32_LOCK_A_PERIPHLOCK0_IDACL_SHIFT 16 323 // Unlock the IDAC0 and IDAC1 Module registers. 324 #define SI32_LOCK_A_PERIPHLOCK0_IDACL_UNLOCKED_VALUE 0 325 #define SI32_LOCK_A_PERIPHLOCK0_IDACL_UNLOCKED_U32 \ 326 (SI32_LOCK_A_PERIPHLOCK0_IDACL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_IDACL_SHIFT) 327 // Lock the IDAC0 and IDAC1 Module registers (bits can still be read). 328 #define SI32_LOCK_A_PERIPHLOCK0_IDACL_LOCKED_VALUE 1 329 #define SI32_LOCK_A_PERIPHLOCK0_IDACL_LOCKED_U32 \ 330 (SI32_LOCK_A_PERIPHLOCK0_IDACL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_IDACL_SHIFT) 331 332 #define SI32_LOCK_A_PERIPHLOCK0_DMACTRLL_MASK 0x00020000 333 #define SI32_LOCK_A_PERIPHLOCK0_DMACTRLL_SHIFT 17 334 // Unlock the DMA Controller (DMACTRL0) Module registers. 335 #define SI32_LOCK_A_PERIPHLOCK0_DMACTRLL_UNLOCKED_VALUE 0 336 #define SI32_LOCK_A_PERIPHLOCK0_DMACTRLL_UNLOCKED_U32 \ 337 (SI32_LOCK_A_PERIPHLOCK0_DMACTRLL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_DMACTRLL_SHIFT) 338 // Lock the DMA Controller (DMACTRL0) Module registers (bits can still be read). 339 #define SI32_LOCK_A_PERIPHLOCK0_DMACTRLL_LOCKED_VALUE 1 340 #define SI32_LOCK_A_PERIPHLOCK0_DMACTRLL_LOCKED_U32 \ 341 (SI32_LOCK_A_PERIPHLOCK0_DMACTRLL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_DMACTRLL_SHIFT) 342 343 #define SI32_LOCK_A_PERIPHLOCK0_DMAXBARL_MASK 0x00040000 344 #define SI32_LOCK_A_PERIPHLOCK0_DMAXBARL_SHIFT 18 345 // Unlock the DMA Crossbar (DMAXBAR0) Module registers. 346 #define SI32_LOCK_A_PERIPHLOCK0_DMAXBARL_UNLOCKED_VALUE 0 347 #define SI32_LOCK_A_PERIPHLOCK0_DMAXBARL_UNLOCKED_U32 \ 348 (SI32_LOCK_A_PERIPHLOCK0_DMAXBARL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_DMAXBARL_SHIFT) 349 // Lock the DMA Crossbar (DMAXBAR0) Module registers (bits can still be read). 350 #define SI32_LOCK_A_PERIPHLOCK0_DMAXBARL_LOCKED_VALUE 1 351 #define SI32_LOCK_A_PERIPHLOCK0_DMAXBARL_LOCKED_U32 \ 352 (SI32_LOCK_A_PERIPHLOCK0_DMAXBARL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_DMAXBARL_SHIFT) 353 354 #define SI32_LOCK_A_PERIPHLOCK0_LPTL_MASK 0x00080000 355 #define SI32_LOCK_A_PERIPHLOCK0_LPTL_SHIFT 19 356 // Unlock the Low Power Timer (LPTIMER0) Module registers. 357 #define SI32_LOCK_A_PERIPHLOCK0_LPTL_UNLOCKED_VALUE 0 358 #define SI32_LOCK_A_PERIPHLOCK0_LPTL_UNLOCKED_U32 \ 359 (SI32_LOCK_A_PERIPHLOCK0_LPTL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_LPTL_SHIFT) 360 // Lock the Low Power Timer (LPTIMER0) Module registers (bits can still be read). 361 #define SI32_LOCK_A_PERIPHLOCK0_LPTL_LOCKED_VALUE 1 362 #define SI32_LOCK_A_PERIPHLOCK0_LPTL_LOCKED_U32 \ 363 (SI32_LOCK_A_PERIPHLOCK0_LPTL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_LPTL_SHIFT) 364 365 #define SI32_LOCK_A_PERIPHLOCK0_VREFL_MASK 0x00100000 366 #define SI32_LOCK_A_PERIPHLOCK0_VREFL_SHIFT 20 367 // Unlock the Voltage Reference (VREF0) Module registers. 368 #define SI32_LOCK_A_PERIPHLOCK0_VREFL_UNLOCKED_VALUE 0 369 #define SI32_LOCK_A_PERIPHLOCK0_VREFL_UNLOCKED_U32 \ 370 (SI32_LOCK_A_PERIPHLOCK0_VREFL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_VREFL_SHIFT) 371 // Lock the Voltage Reference (VREF0) Module registers (bits can still be read). 372 #define SI32_LOCK_A_PERIPHLOCK0_VREFL_LOCKED_VALUE 1 373 #define SI32_LOCK_A_PERIPHLOCK0_VREFL_LOCKED_U32 \ 374 (SI32_LOCK_A_PERIPHLOCK0_VREFL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_VREFL_SHIFT) 375 376 #define SI32_LOCK_A_PERIPHLOCK0_I2SL_MASK 0x00200000 377 #define SI32_LOCK_A_PERIPHLOCK0_I2SL_SHIFT 21 378 // Unlock the I2S0 Module registers. 379 #define SI32_LOCK_A_PERIPHLOCK0_I2SL_UNLOCKED_VALUE 0 380 #define SI32_LOCK_A_PERIPHLOCK0_I2SL_UNLOCKED_U32 \ 381 (SI32_LOCK_A_PERIPHLOCK0_I2SL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_I2SL_SHIFT) 382 // Lock the I2S0 Module registers (bits can still be read). 383 #define SI32_LOCK_A_PERIPHLOCK0_I2SL_LOCKED_VALUE 1 384 #define SI32_LOCK_A_PERIPHLOCK0_I2SL_LOCKED_U32 \ 385 (SI32_LOCK_A_PERIPHLOCK0_I2SL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_I2SL_SHIFT) 386 387 #define SI32_LOCK_A_PERIPHLOCK0_PLLL_MASK 0x00400000 388 #define SI32_LOCK_A_PERIPHLOCK0_PLLL_SHIFT 22 389 // Unlock the PLL0 Module registers. 390 #define SI32_LOCK_A_PERIPHLOCK0_PLLL_UNLOCKED_VALUE 0 391 #define SI32_LOCK_A_PERIPHLOCK0_PLLL_UNLOCKED_U32 \ 392 (SI32_LOCK_A_PERIPHLOCK0_PLLL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_PLLL_SHIFT) 393 // Lock the PLL0 Module registers (bits can still be read). 394 #define SI32_LOCK_A_PERIPHLOCK0_PLLL_LOCKED_VALUE 1 395 #define SI32_LOCK_A_PERIPHLOCK0_PLLL_LOCKED_U32 \ 396 (SI32_LOCK_A_PERIPHLOCK0_PLLL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_PLLL_SHIFT) 397 398 #define SI32_LOCK_A_PERIPHLOCK0_EXTOSCL_MASK 0x00800000 399 #define SI32_LOCK_A_PERIPHLOCK0_EXTOSCL_SHIFT 23 400 // Unlock the External Oscillator (EXTOSC0) Module registers. 401 #define SI32_LOCK_A_PERIPHLOCK0_EXTOSCL_UNLOCKED_VALUE 0 402 #define SI32_LOCK_A_PERIPHLOCK0_EXTOSCL_UNLOCKED_U32 \ 403 (SI32_LOCK_A_PERIPHLOCK0_EXTOSCL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_EXTOSCL_SHIFT) 404 // Lock the External Oscillator (EXTOSC0) Module registers (bits can still be 405 // read). 406 #define SI32_LOCK_A_PERIPHLOCK0_EXTOSCL_LOCKED_VALUE 1 407 #define SI32_LOCK_A_PERIPHLOCK0_EXTOSCL_LOCKED_U32 \ 408 (SI32_LOCK_A_PERIPHLOCK0_EXTOSCL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_EXTOSCL_SHIFT) 409 410 #define SI32_LOCK_A_PERIPHLOCK0_VREGL_MASK 0x01000000 411 #define SI32_LOCK_A_PERIPHLOCK0_VREGL_SHIFT 24 412 // Unlock the Voltage Regulator (VREG0) Module registers. 413 #define SI32_LOCK_A_PERIPHLOCK0_VREGL_UNLOCKED_VALUE 0 414 #define SI32_LOCK_A_PERIPHLOCK0_VREGL_UNLOCKED_U32 \ 415 (SI32_LOCK_A_PERIPHLOCK0_VREGL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_VREGL_SHIFT) 416 // Lock the Voltage Regulator (VREG0) Module registers (bits can still be read). 417 #define SI32_LOCK_A_PERIPHLOCK0_VREGL_LOCKED_VALUE 1 418 #define SI32_LOCK_A_PERIPHLOCK0_VREGL_LOCKED_U32 \ 419 (SI32_LOCK_A_PERIPHLOCK0_VREGL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_VREGL_SHIFT) 420 421 #define SI32_LOCK_A_PERIPHLOCK0_LPOSCL_MASK 0x02000000 422 #define SI32_LOCK_A_PERIPHLOCK0_LPOSCL_SHIFT 25 423 // Unlock the Low Power Oscillator (LPOSC0) Module registers. 424 #define SI32_LOCK_A_PERIPHLOCK0_LPOSCL_UNLOCKED_VALUE 0 425 #define SI32_LOCK_A_PERIPHLOCK0_LPOSCL_UNLOCKED_U32 \ 426 (SI32_LOCK_A_PERIPHLOCK0_LPOSCL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_LPOSCL_SHIFT) 427 // Lock the Low Power Oscillator (LPOSC0) Module registers (bits can still be 428 // read). 429 #define SI32_LOCK_A_PERIPHLOCK0_LPOSCL_LOCKED_VALUE 1 430 #define SI32_LOCK_A_PERIPHLOCK0_LPOSCL_LOCKED_U32 \ 431 (SI32_LOCK_A_PERIPHLOCK0_LPOSCL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_LPOSCL_SHIFT) 432 433 #define SI32_LOCK_A_PERIPHLOCK0_EVREGL_MASK 0x04000000 434 #define SI32_LOCK_A_PERIPHLOCK0_EVREGL_SHIFT 26 435 // Unlock the External Regulator (EXTVREG0) Module registers. 436 #define SI32_LOCK_A_PERIPHLOCK0_EVREGL_UNLOCKED_VALUE 0 437 #define SI32_LOCK_A_PERIPHLOCK0_EVREGL_UNLOCKED_U32 \ 438 (SI32_LOCK_A_PERIPHLOCK0_EVREGL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_EVREGL_SHIFT) 439 // Lock the External Regulator (EXTVREG0) Module registers (bits can still be 440 // read). 441 #define SI32_LOCK_A_PERIPHLOCK0_EVREGL_LOCKED_VALUE 1 442 #define SI32_LOCK_A_PERIPHLOCK0_EVREGL_LOCKED_U32 \ 443 (SI32_LOCK_A_PERIPHLOCK0_EVREGL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_EVREGL_SHIFT) 444 445 #define SI32_LOCK_A_PERIPHLOCK0_IVCL_MASK 0x10000000 446 #define SI32_LOCK_A_PERIPHLOCK0_IVCL_SHIFT 28 447 // Unlock the IVC0 Module registers. 448 #define SI32_LOCK_A_PERIPHLOCK0_IVCL_UNLOCKED_VALUE 0 449 #define SI32_LOCK_A_PERIPHLOCK0_IVCL_UNLOCKED_U32 \ 450 (SI32_LOCK_A_PERIPHLOCK0_IVCL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_IVCL_SHIFT) 451 // Lock the IVC0 Module registers (bits can still be read). 452 #define SI32_LOCK_A_PERIPHLOCK0_IVCL_LOCKED_VALUE 1 453 #define SI32_LOCK_A_PERIPHLOCK0_IVCL_LOCKED_U32 \ 454 (SI32_LOCK_A_PERIPHLOCK0_IVCL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_IVCL_SHIFT) 455 456 457 458 struct SI32_LOCK_A_PERIPHLOCK1_Struct 459 { 460 union 461 { 462 struct 463 { 464 // PMU Module Lock Enable 465 volatile uint32_t PMUL: 1; 466 uint32_t reserved0: 31; 467 }; 468 volatile uint32_t U32; 469 }; 470 }; 471 472 #define SI32_LOCK_A_PERIPHLOCK1_PMUL_MASK 0x00000001 473 #define SI32_LOCK_A_PERIPHLOCK1_PMUL_SHIFT 0 474 // Unlock the PMU Module registers. 475 #define SI32_LOCK_A_PERIPHLOCK1_PMUL_UNLOCKED_VALUE 0 476 #define SI32_LOCK_A_PERIPHLOCK1_PMUL_UNLOCKED_U32 \ 477 (SI32_LOCK_A_PERIPHLOCK1_PMUL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK1_PMUL_SHIFT) 478 // Lock the PMU Module registers (bits can still be read). 479 #define SI32_LOCK_A_PERIPHLOCK1_PMUL_LOCKED_VALUE 1 480 #define SI32_LOCK_A_PERIPHLOCK1_PMUL_LOCKED_U32 \ 481 (SI32_LOCK_A_PERIPHLOCK1_PMUL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK1_PMUL_SHIFT) 482 483 484 485 typedef struct SI32_LOCK_A_Struct 486 { 487 struct SI32_LOCK_A_KEY_Struct KEY ; // Base Address + 0x0 488 uint32_t reserved0; 489 uint32_t reserved1; 490 uint32_t reserved2; 491 uint32_t reserved3[4]; 492 struct SI32_LOCK_A_PERIPHLOCK0_Struct PERIPHLOCK0 ; // Base Address + 0x20 493 volatile uint32_t PERIPHLOCK0_SET; 494 volatile uint32_t PERIPHLOCK0_CLR; 495 uint32_t reserved4; 496 uint32_t reserved5[4]; 497 struct SI32_LOCK_A_PERIPHLOCK1_Struct PERIPHLOCK1 ; // Base Address + 0x40 498 volatile uint32_t PERIPHLOCK1_SET; 499 volatile uint32_t PERIPHLOCK1_CLR; 500 uint32_t reserved6; 501 } SI32_LOCK_A_Type; 502 503 #ifdef __cplusplus 504 } 505 #endif 506 507 #endif // __SI32_LOCK_A_REGISTERS_H__ 508 509 //-eof-------------------------------------------------------------------------- 510 511
