1 //----------------------------------------------------------------------------- 2 // Copyright 2012 (c) Silicon Laboratories Inc. 3 // 4 // SPDX-License-Identifier: Zlib 5 // 6 // This siHAL software is provided 'as-is', without any express or implied 7 // warranty. In no event will the authors be held liable for any damages 8 // arising from the use of this software. 9 // 10 // Permission is granted to anyone to use this software for any purpose, 11 // including commercial applications, and to alter it and redistribute it 12 // freely, subject to the following restrictions: 13 // 14 // 1. The origin of this software must not be misrepresented; you must not 15 // claim that you wrote the original software. If you use this software 16 // in a product, an acknowledgment in the product documentation would be 17 // appreciated but is not required. 18 // 2. Altered source versions must be plainly marked as such, and must not be 19 // misrepresented as being the original software. 20 // 3. This notice may not be removed or altered from any source distribution. 21 //----------------------------------------------------------------------------- 22 // 23 // This file applies to the SIM3L1XX_PBSTD_A module 24 // 25 // Script: 0.61 26 // Version: 1 27 28 #ifndef __SI32_PBSTD_A_REGISTERS_H__ 29 #define __SI32_PBSTD_A_REGISTERS_H__ 30 31 #include <stdint.h> 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 struct SI32_PBSTD_A_PB_Struct 38 { 39 union 40 { 41 struct 42 { 43 // Output Latch 44 volatile uint16_t PB_BITS; 45 uint32_t reserved0: 16; 46 }; 47 volatile uint32_t U32; 48 }; 49 }; 50 51 #define SI32_PBSTD_A_PB_PB_MASK 0x0000FFFF 52 #define SI32_PBSTD_A_PB_PB_SHIFT 0 53 54 55 56 struct SI32_PBSTD_A_PBPIN_Struct 57 { 58 union 59 { 60 struct 61 { 62 // Pin Value 63 volatile uint16_t PBPIN_BITS; 64 uint32_t reserved0: 16; 65 }; 66 volatile uint32_t U32; 67 }; 68 }; 69 70 #define SI32_PBSTD_A_PBPIN_PBPIN_MASK 0x0000FFFF 71 #define SI32_PBSTD_A_PBPIN_PBPIN_SHIFT 0 72 73 74 75 struct SI32_PBSTD_A_PBMDSEL_Struct 76 { 77 union 78 { 79 struct 80 { 81 // Mode Select 82 volatile uint16_t PBMDSEL_BITS; 83 uint32_t reserved0: 16; 84 }; 85 volatile uint32_t U32; 86 }; 87 }; 88 89 #define SI32_PBSTD_A_PBMDSEL_PBMDSEL_MASK 0x0000FFFF 90 #define SI32_PBSTD_A_PBMDSEL_PBMDSEL_SHIFT 0 91 92 93 94 struct SI32_PBSTD_A_PBSKIPEN_Struct 95 { 96 union 97 { 98 struct 99 { 100 // Crossbar Pin Skip Enable 101 volatile uint16_t PBSKIPEN_BITS; 102 uint32_t reserved0: 16; 103 }; 104 volatile uint32_t U32; 105 }; 106 }; 107 108 #define SI32_PBSTD_A_PBSKIPEN_PBSKIPEN_MASK 0x0000FFFF 109 #define SI32_PBSTD_A_PBSKIPEN_PBSKIPEN_SHIFT 0 110 111 112 113 struct SI32_PBSTD_A_PBOUTMD_Struct 114 { 115 union 116 { 117 struct 118 { 119 // Output Mode 120 volatile uint16_t PBOUTMD_BITS; 121 uint32_t reserved0: 16; 122 }; 123 volatile uint32_t U32; 124 }; 125 }; 126 127 #define SI32_PBSTD_A_PBOUTMD_PBOUTMD_MASK 0x0000FFFF 128 #define SI32_PBSTD_A_PBOUTMD_PBOUTMD_SHIFT 0 129 130 131 132 struct SI32_PBSTD_A_PBDRV_Struct 133 { 134 union 135 { 136 struct 137 { 138 // Drive Strength 139 volatile uint16_t PBDRV_BITS; 140 // Port Bank Weak Pull-up Enable 141 volatile uint32_t PBPUEN: 1; 142 uint32_t reserved0: 15; 143 }; 144 volatile uint32_t U32; 145 }; 146 }; 147 148 #define SI32_PBSTD_A_PBDRV_PBDRV_MASK 0x0000FFFF 149 #define SI32_PBSTD_A_PBDRV_PBDRV_SHIFT 0 150 151 #define SI32_PBSTD_A_PBDRV_PBPUEN_MASK 0x00010000 152 #define SI32_PBSTD_A_PBDRV_PBPUEN_SHIFT 16 153 // Disable weak pull-ups for this port. 154 #define SI32_PBSTD_A_PBDRV_PBPUEN_DISABLED_VALUE 0 155 #define SI32_PBSTD_A_PBDRV_PBPUEN_DISABLED_U32 \ 156 (SI32_PBSTD_A_PBDRV_PBPUEN_DISABLED_VALUE << SI32_PBSTD_A_PBDRV_PBPUEN_SHIFT) 157 // Enable weak pull-ups for this port. 158 #define SI32_PBSTD_A_PBDRV_PBPUEN_ENABLED_VALUE 1 159 #define SI32_PBSTD_A_PBDRV_PBPUEN_ENABLED_U32 \ 160 (SI32_PBSTD_A_PBDRV_PBPUEN_ENABLED_VALUE << SI32_PBSTD_A_PBDRV_PBPUEN_SHIFT) 161 162 163 164 struct SI32_PBSTD_A_PM_Struct 165 { 166 union 167 { 168 struct 169 { 170 // Port Match Value 171 volatile uint16_t PM_BITS; 172 uint32_t reserved0: 16; 173 }; 174 volatile uint32_t U32; 175 }; 176 }; 177 178 #define SI32_PBSTD_A_PM_PM_MASK 0x0000FFFF 179 #define SI32_PBSTD_A_PM_PM_SHIFT 0 180 181 182 183 struct SI32_PBSTD_A_PMEN_Struct 184 { 185 union 186 { 187 struct 188 { 189 // Port Match Enable 190 volatile uint16_t PMEN_BITS; 191 uint32_t reserved0: 16; 192 }; 193 volatile uint32_t U32; 194 }; 195 }; 196 197 #define SI32_PBSTD_A_PMEN_PMEN_MASK 0x0000FFFF 198 #define SI32_PBSTD_A_PMEN_PMEN_SHIFT 0 199 200 201 202 struct SI32_PBSTD_A_PBPGEN_Struct 203 { 204 union 205 { 206 struct 207 { 208 // Pulse Generator Pin Enable 209 volatile uint32_t PBPGEN_BITS: 12; 210 uint32_t reserved0: 20; 211 }; 212 volatile uint32_t U32; 213 }; 214 }; 215 216 #define SI32_PBSTD_A_PBPGEN_PBPGEN_MASK 0x00000FFF 217 #define SI32_PBSTD_A_PBPGEN_PBPGEN_SHIFT 0 218 219 220 221 struct SI32_PBSTD_A_PBPGPHASE_Struct 222 { 223 union 224 { 225 struct 226 { 227 // Pulse Generator Phase 0 228 volatile uint32_t PBPGPH0: 12; 229 uint32_t reserved0: 4; 230 // Pulse Generator Phase 1 231 volatile uint32_t PBPGPH1: 12; 232 uint32_t reserved1: 4; 233 }; 234 volatile uint32_t U32; 235 }; 236 }; 237 238 #define SI32_PBSTD_A_PBPGPHASE_PBPGPH0_MASK 0x00000FFF 239 #define SI32_PBSTD_A_PBPGPHASE_PBPGPH0_SHIFT 0 240 241 #define SI32_PBSTD_A_PBPGPHASE_PBPGPH1_MASK 0x0FFF0000 242 #define SI32_PBSTD_A_PBPGPHASE_PBPGPH1_SHIFT 16 243 244 245 246 typedef struct SI32_PBSTD_A_Struct 247 { 248 struct SI32_PBSTD_A_PB_Struct PB ; // Base Address + 0x0 249 volatile uint32_t PB_SET; 250 volatile uint32_t PB_CLR; 251 volatile uint32_t PB_MSK; 252 struct SI32_PBSTD_A_PBPIN_Struct PBPIN ; // Base Address + 0x10 253 uint32_t reserved0; 254 uint32_t reserved1; 255 uint32_t reserved2; 256 struct SI32_PBSTD_A_PBMDSEL_Struct PBMDSEL ; // Base Address + 0x20 257 volatile uint32_t PBMDSEL_SET; 258 volatile uint32_t PBMDSEL_CLR; 259 uint32_t reserved3; 260 struct SI32_PBSTD_A_PBSKIPEN_Struct PBSKIPEN ; // Base Address + 0x30 261 volatile uint32_t PBSKIPEN_SET; 262 volatile uint32_t PBSKIPEN_CLR; 263 uint32_t reserved4; 264 struct SI32_PBSTD_A_PBOUTMD_Struct PBOUTMD ; // Base Address + 0x40 265 volatile uint32_t PBOUTMD_SET; 266 volatile uint32_t PBOUTMD_CLR; 267 uint32_t reserved5; 268 struct SI32_PBSTD_A_PBDRV_Struct PBDRV ; // Base Address + 0x50 269 volatile uint32_t PBDRV_SET; 270 volatile uint32_t PBDRV_CLR; 271 uint32_t reserved6; 272 struct SI32_PBSTD_A_PM_Struct PM ; // Base Address + 0x60 273 volatile uint32_t PM_SET; 274 volatile uint32_t PM_CLR; 275 uint32_t reserved7; 276 struct SI32_PBSTD_A_PMEN_Struct PMEN ; // Base Address + 0x70 277 volatile uint32_t PMEN_SET; 278 volatile uint32_t PMEN_CLR; 279 uint32_t reserved8; 280 struct SI32_PBSTD_A_PBPGEN_Struct PBPGEN ; // Base Address + 0x80 281 uint32_t reserved9; 282 uint32_t reserved10; 283 uint32_t reserved11; 284 struct SI32_PBSTD_A_PBPGPHASE_Struct PBPGPHASE ; // Base Address + 0x90 285 uint32_t reserved12; 286 uint32_t reserved13; 287 uint32_t reserved14; 288 } SI32_PBSTD_A_Type; 289 290 #ifdef __cplusplus 291 } 292 #endif 293 294 #endif // __SI32_PBSTD_A_REGISTERS_H__ 295 296 //-eof-------------------------------------------------------------------------- 297 298
