1 //-----------------------------------------------------------------------------
2 // Copyright 2012 (c) Silicon Laboratories Inc.
3 //
4 // SPDX-License-Identifier: Zlib
5 //
6 // This siHAL software is provided 'as-is', without any express or implied
7 // warranty. In no event will the authors be held liable for any damages
8 // arising from the use of this software.
9 //
10 // Permission is granted to anyone to use this software for any purpose,
11 // including commercial applications, and to alter it and redistribute it
12 // freely, subject to the following restrictions:
13 //
14 // 1. The origin of this software must not be misrepresented; you must not
15 //    claim that you wrote the original software. If you use this software
16 //    in a product, an acknowledgment in the product documentation would be
17 //    appreciated but is not required.
18 // 2. Altered source versions must be plainly marked as such, and must not be
19 //    misrepresented as being the original software.
20 // 3. This notice may not be removed or altered from any source distribution.
21 //-----------------------------------------------------------------------------
22 //
23 // This file applies to the SIM3L1XX_PBGP_A module
24 //
25 // Script: 0.61
26 // Version: 1
27 
28 #ifndef __SI32_PBGP_A_REGISTERS_H__
29 #define __SI32_PBGP_A_REGISTERS_H__
30 
31 #include <stdint.h>
32 
33 #ifdef __cplusplus
34 extern "C" {
35 #endif
36 
37 struct SI32_PBGP_A_PB_Struct
38 {
39    union
40    {
41       struct
42       {
43          // Output Latch
44          volatile uint16_t PB_BITS;
45                   uint32_t reserved0: 16;
46       };
47       volatile uint32_t U32;
48    };
49 };
50 
51 #define SI32_PBGP_A_PB_PB_MASK  0x0000FFFF
52 #define SI32_PBGP_A_PB_PB_SHIFT  0
53 
54 
55 
56 struct SI32_PBGP_A_PBPIN_Struct
57 {
58    union
59    {
60       struct
61       {
62          // Pin Value
63          volatile uint16_t PBPIN_BITS;
64                   uint32_t reserved0: 16;
65       };
66       volatile uint32_t U32;
67    };
68 };
69 
70 #define SI32_PBGP_A_PBPIN_PBPIN_MASK  0x0000FFFF
71 #define SI32_PBGP_A_PBPIN_PBPIN_SHIFT  0
72 
73 
74 
75 struct SI32_PBGP_A_PBMDSEL_Struct
76 {
77    union
78    {
79       struct
80       {
81          // Mode Select
82          volatile uint16_t PBMDSEL_BITS;
83                   uint32_t reserved0: 16;
84       };
85       volatile uint32_t U32;
86    };
87 };
88 
89 #define SI32_PBGP_A_PBMDSEL_PBMDSEL_MASK  0x0000FFFF
90 #define SI32_PBGP_A_PBMDSEL_PBMDSEL_SHIFT  0
91 
92 
93 
94 struct SI32_PBGP_A_PBOUTMD_Struct
95 {
96    union
97    {
98       struct
99       {
100          // Output Mode
101          volatile uint16_t PBOUTMD_BITS;
102                   uint32_t reserved0: 16;
103       };
104       volatile uint32_t U32;
105    };
106 };
107 
108 #define SI32_PBGP_A_PBOUTMD_PBOUTMD_MASK  0x0000FFFF
109 #define SI32_PBGP_A_PBOUTMD_PBOUTMD_SHIFT  0
110 
111 
112 
113 struct SI32_PBGP_A_PBDRV_Struct
114 {
115    union
116    {
117       struct
118       {
119          // Drive Strength
120          volatile uint16_t PBDRV_BITS;
121          // Port Bank Weak Pull-up Enable
122          volatile uint32_t PBPUEN: 1;
123                   uint32_t reserved0: 15;
124       };
125       volatile uint32_t U32;
126    };
127 };
128 
129 #define SI32_PBGP_A_PBDRV_PBDRV_MASK  0x0000FFFF
130 #define SI32_PBGP_A_PBDRV_PBDRV_SHIFT  0
131 
132 #define SI32_PBGP_A_PBDRV_PBPUEN_MASK  0x00010000
133 #define SI32_PBGP_A_PBDRV_PBPUEN_SHIFT  16
134 // Disable weak pull-ups for this port.
135 #define SI32_PBGP_A_PBDRV_PBPUEN_DISABLED_VALUE  0
136 #define SI32_PBGP_A_PBDRV_PBPUEN_DISABLED_U32 \
137    (SI32_PBGP_A_PBDRV_PBPUEN_DISABLED_VALUE << SI32_PBGP_A_PBDRV_PBPUEN_SHIFT)
138 // Enable weak pull-ups for this port.
139 #define SI32_PBGP_A_PBDRV_PBPUEN_ENABLED_VALUE  1
140 #define SI32_PBGP_A_PBDRV_PBPUEN_ENABLED_U32 \
141    (SI32_PBGP_A_PBDRV_PBPUEN_ENABLED_VALUE << SI32_PBGP_A_PBDRV_PBPUEN_SHIFT)
142 
143 
144 
145 struct SI32_PBGP_A_PM_Struct
146 {
147    union
148    {
149       struct
150       {
151          // Port Match Value
152          volatile uint16_t PM_BITS;
153                   uint32_t reserved0: 16;
154       };
155       volatile uint32_t U32;
156    };
157 };
158 
159 #define SI32_PBGP_A_PM_PM_MASK  0x0000FFFF
160 #define SI32_PBGP_A_PM_PM_SHIFT  0
161 
162 
163 
164 struct SI32_PBGP_A_PMEN_Struct
165 {
166    union
167    {
168       struct
169       {
170          // Port Match Enable
171          volatile uint16_t PMEN_BITS;
172                   uint32_t reserved0: 16;
173       };
174       volatile uint32_t U32;
175    };
176 };
177 
178 #define SI32_PBGP_A_PMEN_PMEN_MASK  0x0000FFFF
179 #define SI32_PBGP_A_PMEN_PMEN_SHIFT  0
180 
181 
182 
183 typedef struct SI32_PBGP_A_Struct
184 {
185    struct SI32_PBGP_A_PB_Struct                    PB             ; // Base Address + 0x0
186    volatile uint32_t                               PB_SET;
187    volatile uint32_t                               PB_CLR;
188    volatile uint32_t                               PB_MSK;
189    struct SI32_PBGP_A_PBPIN_Struct                 PBPIN          ; // Base Address + 0x10
190    uint32_t                                        reserved0;
191    uint32_t                                        reserved1;
192    uint32_t                                        reserved2;
193    struct SI32_PBGP_A_PBMDSEL_Struct               PBMDSEL        ; // Base Address + 0x20
194    volatile uint32_t                               PBMDSEL_SET;
195    volatile uint32_t                               PBMDSEL_CLR;
196    uint32_t                                        reserved3;
197    struct SI32_PBGP_A_PBOUTMD_Struct               PBOUTMD        ; // Base Address + 0x30
198    volatile uint32_t                               PBOUTMD_SET;
199    volatile uint32_t                               PBOUTMD_CLR;
200    uint32_t                                        reserved4;
201    struct SI32_PBGP_A_PBDRV_Struct                 PBDRV          ; // Base Address + 0x40
202    volatile uint32_t                               PBDRV_SET;
203    volatile uint32_t                               PBDRV_CLR;
204    uint32_t                                        reserved5;
205    struct SI32_PBGP_A_PM_Struct                    PM             ; // Base Address + 0x50
206    volatile uint32_t                               PM_SET;
207    volatile uint32_t                               PM_CLR;
208    uint32_t                                        reserved6;
209    struct SI32_PBGP_A_PMEN_Struct                  PMEN           ; // Base Address + 0x60
210    volatile uint32_t                               PMEN_SET;
211    volatile uint32_t                               PMEN_CLR;
212    uint32_t                                        reserved7;
213 } SI32_PBGP_A_Type;
214 
215 #ifdef __cplusplus
216 }
217 #endif
218 
219 #endif // __SI32_PBGP_A_REGISTERS_H__
220 
221 //-eof--------------------------------------------------------------------------
222 
223