1 //----------------------------------------------------------------------------- 2 // Copyright 2012 (c) Silicon Laboratories Inc. 3 // 4 // SPDX-License-Identifier: Zlib 5 // 6 // This siHAL software is provided 'as-is', without any express or implied 7 // warranty. In no event will the authors be held liable for any damages 8 // arising from the use of this software. 9 // 10 // Permission is granted to anyone to use this software for any purpose, 11 // including commercial applications, and to alter it and redistribute it 12 // freely, subject to the following restrictions: 13 // 14 // 1. The origin of this software must not be misrepresented; you must not 15 // claim that you wrote the original software. If you use this software 16 // in a product, an acknowledgment in the product documentation would be 17 // appreciated but is not required. 18 // 2. Altered source versions must be plainly marked as such, and must not be 19 // misrepresented as being the original software. 20 // 3. This notice may not be removed or altered from any source distribution. 21 //----------------------------------------------------------------------------- 22 // 23 // This file applies to the SIM3L1XX_LOCK_A module 24 // 25 // Script: 0.61 26 // Version: 1 27 28 #ifndef __SI32_LOCK_A_REGISTERS_H__ 29 #define __SI32_LOCK_A_REGISTERS_H__ 30 31 #include <stdint.h> 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 struct SI32_LOCK_A_KEY_Struct 38 { 39 union 40 { 41 struct 42 { 43 // Peripheral Lock Mask Key 44 volatile uint8_t KEY_BITS; 45 uint32_t reserved0: 24; 46 }; 47 volatile uint32_t U32; 48 }; 49 }; 50 51 #define SI32_LOCK_A_KEY_KEY_MASK 0x000000FF 52 #define SI32_LOCK_A_KEY_KEY_SHIFT 0 53 // PERIPHLOCK registers are locked and no valid values have been written to KEY. 54 #define SI32_LOCK_A_KEY_KEY_LOCKED_VALUE 0 55 #define SI32_LOCK_A_KEY_KEY_LOCKED_U32 \ 56 (SI32_LOCK_A_KEY_KEY_LOCKED_VALUE << SI32_LOCK_A_KEY_KEY_SHIFT) 57 // PERIPHLOCK registers are locked and the first valid value (0xA5) has been 58 // written to KEY. 59 #define SI32_LOCK_A_KEY_KEY_INTERMEDIATE_VALUE 1 60 #define SI32_LOCK_A_KEY_KEY_INTERMEDIATE_U32 \ 61 (SI32_LOCK_A_KEY_KEY_INTERMEDIATE_VALUE << SI32_LOCK_A_KEY_KEY_SHIFT) 62 // PERIPHLOCK registers are unlocked. Any subsequent writes to KEY will lock the 63 // interface. 64 #define SI32_LOCK_A_KEY_KEY_UNLOCKED_VALUE 2 65 #define SI32_LOCK_A_KEY_KEY_UNLOCKED_U32 \ 66 (SI32_LOCK_A_KEY_KEY_UNLOCKED_VALUE << SI32_LOCK_A_KEY_KEY_SHIFT) 67 68 69 70 struct SI32_LOCK_A_PERIPHLOCK0_Struct 71 { 72 union 73 { 74 struct 75 { 76 // USART/UART Module Lock Enable 77 volatile uint32_t USARTL: 1; 78 // SPI Module Lock Enable 79 volatile uint32_t SPIL: 1; 80 // I2C Module Lock Enable 81 volatile uint32_t I2CL: 1; 82 // PCA Module Lock Enable 83 volatile uint32_t PCAL: 1; 84 // Timer Module Lock Enable 85 volatile uint32_t TIMERL: 1; 86 // SARADC Module Lock Enable 87 volatile uint32_t SARADCL: 1; 88 // Comparator Module Lock Enable 89 volatile uint32_t CMPL: 1; 90 // AES Module Lock Enable 91 volatile uint32_t AESL: 1; 92 // CRC Module Lock Enable 93 volatile uint32_t CRCL: 1; 94 // RTC Module Lock Enable 95 volatile uint32_t RTCL: 1; 96 // Reset Sources Module Lock Enable 97 volatile uint32_t RSTSRCL: 1; 98 // Clock Control Lock Enable 99 volatile uint32_t CLKCTRL: 1; 100 // Voltage Supply Monitor Module Lock Enable 101 volatile uint32_t VMONL: 1; 102 // IDAC Module Lock Enable 103 volatile uint32_t IDACL: 1; 104 // DMA Controller Module Lock Enable 105 volatile uint32_t DMACTRLL: 1; 106 // DMA Crossbar Module Lock Enable 107 volatile uint32_t DMAXBARL: 1; 108 // Low Power Timer Module Lock Enable 109 volatile uint32_t LPTL: 1; 110 // Voltage Reference Module Lock Enable 111 volatile uint32_t LDOL: 1; 112 // PLL Module Lock Enable 113 volatile uint32_t PLLL: 1; 114 // External Oscillator Module Lock Enable 115 volatile uint32_t EXTOSCL: 1; 116 // PVT Oscillator Module Lock Enable 117 volatile uint32_t PVTL: 1; 118 // Low Power Oscillator Lock Enable 119 volatile uint32_t LPOSCL: 1; 120 // Advanced Capture Counter Module Lock 121 volatile uint32_t ACCTRL: 1; 122 uint32_t reserved0: 4; 123 // PMU Module Lock Enable 124 volatile uint32_t PMUL: 1; 125 // DTM Module Lock 126 volatile uint32_t DTML: 1; 127 // LCD Module Lock 128 volatile uint32_t LCDL: 1; 129 // DC-DC Converter Module Lock 130 volatile uint32_t DCDCL: 1; 131 uint32_t reserved1: 1; 132 }; 133 volatile uint32_t U32; 134 }; 135 }; 136 137 #define SI32_LOCK_A_PERIPHLOCK0_USARTL_MASK 0x00000001 138 #define SI32_LOCK_A_PERIPHLOCK0_USARTL_SHIFT 0 139 // Unlock the USART0 and UART0 Module registers. 140 #define SI32_LOCK_A_PERIPHLOCK0_USARTL_UNLOCKED_VALUE 0 141 #define SI32_LOCK_A_PERIPHLOCK0_USARTL_UNLOCKED_U32 \ 142 (SI32_LOCK_A_PERIPHLOCK0_USARTL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_USARTL_SHIFT) 143 // Lock the USART0 and UART0 Module registers (bits can still be read). 144 #define SI32_LOCK_A_PERIPHLOCK0_USARTL_LOCKED_VALUE 1 145 #define SI32_LOCK_A_PERIPHLOCK0_USARTL_LOCKED_U32 \ 146 (SI32_LOCK_A_PERIPHLOCK0_USARTL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_USARTL_SHIFT) 147 148 #define SI32_LOCK_A_PERIPHLOCK0_SPIL_MASK 0x00000002 149 #define SI32_LOCK_A_PERIPHLOCK0_SPIL_SHIFT 1 150 // Unlock the SPI0 and SPI1 Module registers. 151 #define SI32_LOCK_A_PERIPHLOCK0_SPIL_UNLOCKED_VALUE 0 152 #define SI32_LOCK_A_PERIPHLOCK0_SPIL_UNLOCKED_U32 \ 153 (SI32_LOCK_A_PERIPHLOCK0_SPIL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_SPIL_SHIFT) 154 // Lock the SPI0 and SPI1 Module registers (bits can still be read). 155 #define SI32_LOCK_A_PERIPHLOCK0_SPIL_LOCKED_VALUE 1 156 #define SI32_LOCK_A_PERIPHLOCK0_SPIL_LOCKED_U32 \ 157 (SI32_LOCK_A_PERIPHLOCK0_SPIL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_SPIL_SHIFT) 158 159 #define SI32_LOCK_A_PERIPHLOCK0_I2CL_MASK 0x00000004 160 #define SI32_LOCK_A_PERIPHLOCK0_I2CL_SHIFT 2 161 // Unlock the I2C0 Module registers. 162 #define SI32_LOCK_A_PERIPHLOCK0_I2CL_UNLOCKED_VALUE 0 163 #define SI32_LOCK_A_PERIPHLOCK0_I2CL_UNLOCKED_U32 \ 164 (SI32_LOCK_A_PERIPHLOCK0_I2CL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_I2CL_SHIFT) 165 // Lock the I2C0 Module registers (bits can still be read). 166 #define SI32_LOCK_A_PERIPHLOCK0_I2CL_LOCKED_VALUE 1 167 #define SI32_LOCK_A_PERIPHLOCK0_I2CL_LOCKED_U32 \ 168 (SI32_LOCK_A_PERIPHLOCK0_I2CL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_I2CL_SHIFT) 169 170 #define SI32_LOCK_A_PERIPHLOCK0_PCAL_MASK 0x00000008 171 #define SI32_LOCK_A_PERIPHLOCK0_PCAL_SHIFT 3 172 // Unlock the EPCA0 Module registers. 173 #define SI32_LOCK_A_PERIPHLOCK0_PCAL_UNLOCKED_VALUE 0 174 #define SI32_LOCK_A_PERIPHLOCK0_PCAL_UNLOCKED_U32 \ 175 (SI32_LOCK_A_PERIPHLOCK0_PCAL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_PCAL_SHIFT) 176 // Lock the EPCA0 Module registers (bits can still be read). 177 #define SI32_LOCK_A_PERIPHLOCK0_PCAL_LOCKED_VALUE 1 178 #define SI32_LOCK_A_PERIPHLOCK0_PCAL_LOCKED_U32 \ 179 (SI32_LOCK_A_PERIPHLOCK0_PCAL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_PCAL_SHIFT) 180 181 #define SI32_LOCK_A_PERIPHLOCK0_TIMERL_MASK 0x00000010 182 #define SI32_LOCK_A_PERIPHLOCK0_TIMERL_SHIFT 4 183 // Unlock the TIMER0, TIMER1, and TIMER2 Module registers. 184 #define SI32_LOCK_A_PERIPHLOCK0_TIMERL_UNLOCKED_VALUE 0 185 #define SI32_LOCK_A_PERIPHLOCK0_TIMERL_UNLOCKED_U32 \ 186 (SI32_LOCK_A_PERIPHLOCK0_TIMERL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_TIMERL_SHIFT) 187 // Lock the TIMER0, TIMER1, and TIMER2 Module registers (bits can still be read). 188 #define SI32_LOCK_A_PERIPHLOCK0_TIMERL_LOCKED_VALUE 1 189 #define SI32_LOCK_A_PERIPHLOCK0_TIMERL_LOCKED_U32 \ 190 (SI32_LOCK_A_PERIPHLOCK0_TIMERL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_TIMERL_SHIFT) 191 192 #define SI32_LOCK_A_PERIPHLOCK0_SARADCL_MASK 0x00000020 193 #define SI32_LOCK_A_PERIPHLOCK0_SARADCL_SHIFT 5 194 // Unlock the SARADC0 Module registers. 195 #define SI32_LOCK_A_PERIPHLOCK0_SARADCL_UNLOCKED_VALUE 0 196 #define SI32_LOCK_A_PERIPHLOCK0_SARADCL_UNLOCKED_U32 \ 197 (SI32_LOCK_A_PERIPHLOCK0_SARADCL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_SARADCL_SHIFT) 198 // Lock the SARADC0 Module registers (bits can still be read). 199 #define SI32_LOCK_A_PERIPHLOCK0_SARADCL_LOCKED_VALUE 1 200 #define SI32_LOCK_A_PERIPHLOCK0_SARADCL_LOCKED_U32 \ 201 (SI32_LOCK_A_PERIPHLOCK0_SARADCL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_SARADCL_SHIFT) 202 203 #define SI32_LOCK_A_PERIPHLOCK0_CMPL_MASK 0x00000040 204 #define SI32_LOCK_A_PERIPHLOCK0_CMPL_SHIFT 6 205 // Unlock the Comparator 0 and Comparator 1 Module registers. 206 #define SI32_LOCK_A_PERIPHLOCK0_CMPL_UNLOCKED_VALUE 0 207 #define SI32_LOCK_A_PERIPHLOCK0_CMPL_UNLOCKED_U32 \ 208 (SI32_LOCK_A_PERIPHLOCK0_CMPL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_CMPL_SHIFT) 209 // Lock the Comparator 0 and Comparator 1 Module registers (bits can still be 210 // read). 211 #define SI32_LOCK_A_PERIPHLOCK0_CMPL_LOCKED_VALUE 1 212 #define SI32_LOCK_A_PERIPHLOCK0_CMPL_LOCKED_U32 \ 213 (SI32_LOCK_A_PERIPHLOCK0_CMPL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_CMPL_SHIFT) 214 215 #define SI32_LOCK_A_PERIPHLOCK0_AESL_MASK 0x00000080 216 #define SI32_LOCK_A_PERIPHLOCK0_AESL_SHIFT 7 217 // Unlock the AES0 Module registers. 218 #define SI32_LOCK_A_PERIPHLOCK0_AESL_UNLOCKED_VALUE 0 219 #define SI32_LOCK_A_PERIPHLOCK0_AESL_UNLOCKED_U32 \ 220 (SI32_LOCK_A_PERIPHLOCK0_AESL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_AESL_SHIFT) 221 // Lock the AES0 Module registers (bits can still be read). 222 #define SI32_LOCK_A_PERIPHLOCK0_AESL_LOCKED_VALUE 1 223 #define SI32_LOCK_A_PERIPHLOCK0_AESL_LOCKED_U32 \ 224 (SI32_LOCK_A_PERIPHLOCK0_AESL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_AESL_SHIFT) 225 226 #define SI32_LOCK_A_PERIPHLOCK0_CRCL_MASK 0x00000100 227 #define SI32_LOCK_A_PERIPHLOCK0_CRCL_SHIFT 8 228 // Unlock the CRC0 Module registers. 229 #define SI32_LOCK_A_PERIPHLOCK0_CRCL_UNLOCKED_VALUE 0 230 #define SI32_LOCK_A_PERIPHLOCK0_CRCL_UNLOCKED_U32 \ 231 (SI32_LOCK_A_PERIPHLOCK0_CRCL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_CRCL_SHIFT) 232 // Lock the CRC0 Module registers (bits can still be read). 233 #define SI32_LOCK_A_PERIPHLOCK0_CRCL_LOCKED_VALUE 1 234 #define SI32_LOCK_A_PERIPHLOCK0_CRCL_LOCKED_U32 \ 235 (SI32_LOCK_A_PERIPHLOCK0_CRCL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_CRCL_SHIFT) 236 237 #define SI32_LOCK_A_PERIPHLOCK0_RTCL_MASK 0x00000200 238 #define SI32_LOCK_A_PERIPHLOCK0_RTCL_SHIFT 9 239 // Unlock the RTC0 Module registers. 240 #define SI32_LOCK_A_PERIPHLOCK0_RTCL_UNLOCKED_VALUE 0 241 #define SI32_LOCK_A_PERIPHLOCK0_RTCL_UNLOCKED_U32 \ 242 (SI32_LOCK_A_PERIPHLOCK0_RTCL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_RTCL_SHIFT) 243 // Lock the RTC0 Module registers (bits can still be read). 244 #define SI32_LOCK_A_PERIPHLOCK0_RTCL_LOCKED_VALUE 1 245 #define SI32_LOCK_A_PERIPHLOCK0_RTCL_LOCKED_U32 \ 246 (SI32_LOCK_A_PERIPHLOCK0_RTCL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_RTCL_SHIFT) 247 248 #define SI32_LOCK_A_PERIPHLOCK0_RSTSRCL_MASK 0x00000400 249 #define SI32_LOCK_A_PERIPHLOCK0_RSTSRCL_SHIFT 10 250 // Unlock the Reset Sources (RSTSRC) Module registers. 251 #define SI32_LOCK_A_PERIPHLOCK0_RSTSRCL_UNLOCKED_VALUE 0 252 #define SI32_LOCK_A_PERIPHLOCK0_RSTSRCL_UNLOCKED_U32 \ 253 (SI32_LOCK_A_PERIPHLOCK0_RSTSRCL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_RSTSRCL_SHIFT) 254 // Lock the Reset Sources (RSTSRC) Module registers (bits can still be read). 255 #define SI32_LOCK_A_PERIPHLOCK0_RSTSRCL_LOCKED_VALUE 1 256 #define SI32_LOCK_A_PERIPHLOCK0_RSTSRCL_LOCKED_U32 \ 257 (SI32_LOCK_A_PERIPHLOCK0_RSTSRCL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_RSTSRCL_SHIFT) 258 259 #define SI32_LOCK_A_PERIPHLOCK0_CLKCTRL_MASK 0x00000800 260 #define SI32_LOCK_A_PERIPHLOCK0_CLKCTRL_SHIFT 11 261 // Unlock the Clock Control (CLKCTRL)Module registers. 262 #define SI32_LOCK_A_PERIPHLOCK0_CLKCTRL_UNLOCKED_VALUE 0 263 #define SI32_LOCK_A_PERIPHLOCK0_CLKCTRL_UNLOCKED_U32 \ 264 (SI32_LOCK_A_PERIPHLOCK0_CLKCTRL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_CLKCTRL_SHIFT) 265 // Lock the Clock Control (CLKCTRL) Module registers (bits can still be read). 266 #define SI32_LOCK_A_PERIPHLOCK0_CLKCTRL_LOCKED_VALUE 1 267 #define SI32_LOCK_A_PERIPHLOCK0_CLKCTRL_LOCKED_U32 \ 268 (SI32_LOCK_A_PERIPHLOCK0_CLKCTRL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_CLKCTRL_SHIFT) 269 270 #define SI32_LOCK_A_PERIPHLOCK0_VMONL_MASK 0x00001000 271 #define SI32_LOCK_A_PERIPHLOCK0_VMONL_SHIFT 12 272 // Unlock the Voltage Supply Monitor (VMON0) Module registers. 273 #define SI32_LOCK_A_PERIPHLOCK0_VMONL_UNLOCKED_VALUE 0 274 #define SI32_LOCK_A_PERIPHLOCK0_VMONL_UNLOCKED_U32 \ 275 (SI32_LOCK_A_PERIPHLOCK0_VMONL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_VMONL_SHIFT) 276 // Lock the Voltage Supply Monitor (VMON0) Module registers (bits can still be 277 // read). 278 #define SI32_LOCK_A_PERIPHLOCK0_VMONL_LOCKED_VALUE 1 279 #define SI32_LOCK_A_PERIPHLOCK0_VMONL_LOCKED_U32 \ 280 (SI32_LOCK_A_PERIPHLOCK0_VMONL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_VMONL_SHIFT) 281 282 #define SI32_LOCK_A_PERIPHLOCK0_IDACL_MASK 0x00002000 283 #define SI32_LOCK_A_PERIPHLOCK0_IDACL_SHIFT 13 284 // Unlock the IDAC0 Module registers. 285 #define SI32_LOCK_A_PERIPHLOCK0_IDACL_UNLOCKED_VALUE 0 286 #define SI32_LOCK_A_PERIPHLOCK0_IDACL_UNLOCKED_U32 \ 287 (SI32_LOCK_A_PERIPHLOCK0_IDACL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_IDACL_SHIFT) 288 // Lock the IDAC0 Module registers (bits can still be read). 289 #define SI32_LOCK_A_PERIPHLOCK0_IDACL_LOCKED_VALUE 1 290 #define SI32_LOCK_A_PERIPHLOCK0_IDACL_LOCKED_U32 \ 291 (SI32_LOCK_A_PERIPHLOCK0_IDACL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_IDACL_SHIFT) 292 293 #define SI32_LOCK_A_PERIPHLOCK0_DMACTRLL_MASK 0x00004000 294 #define SI32_LOCK_A_PERIPHLOCK0_DMACTRLL_SHIFT 14 295 // Unlock the DMA Controller (DMACTRL0) Module registers. 296 #define SI32_LOCK_A_PERIPHLOCK0_DMACTRLL_UNLOCKED_VALUE 0 297 #define SI32_LOCK_A_PERIPHLOCK0_DMACTRLL_UNLOCKED_U32 \ 298 (SI32_LOCK_A_PERIPHLOCK0_DMACTRLL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_DMACTRLL_SHIFT) 299 // Lock the DMA Controller (DMACTRL0) Module registers (bits can still be read). 300 #define SI32_LOCK_A_PERIPHLOCK0_DMACTRLL_LOCKED_VALUE 1 301 #define SI32_LOCK_A_PERIPHLOCK0_DMACTRLL_LOCKED_U32 \ 302 (SI32_LOCK_A_PERIPHLOCK0_DMACTRLL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_DMACTRLL_SHIFT) 303 304 #define SI32_LOCK_A_PERIPHLOCK0_DMAXBARL_MASK 0x00008000 305 #define SI32_LOCK_A_PERIPHLOCK0_DMAXBARL_SHIFT 15 306 // Unlock the DMA Crossbar (DMAXBAR0) Module registers. 307 #define SI32_LOCK_A_PERIPHLOCK0_DMAXBARL_UNLOCKED_VALUE 0 308 #define SI32_LOCK_A_PERIPHLOCK0_DMAXBARL_UNLOCKED_U32 \ 309 (SI32_LOCK_A_PERIPHLOCK0_DMAXBARL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_DMAXBARL_SHIFT) 310 // Lock the DMA Crossbar (DMAXBAR0) Module registers (bits can still be read). 311 #define SI32_LOCK_A_PERIPHLOCK0_DMAXBARL_LOCKED_VALUE 1 312 #define SI32_LOCK_A_PERIPHLOCK0_DMAXBARL_LOCKED_U32 \ 313 (SI32_LOCK_A_PERIPHLOCK0_DMAXBARL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_DMAXBARL_SHIFT) 314 315 #define SI32_LOCK_A_PERIPHLOCK0_LPTL_MASK 0x00010000 316 #define SI32_LOCK_A_PERIPHLOCK0_LPTL_SHIFT 16 317 // Unlock the Low Power Timer (LPTIMER0) Module registers. 318 #define SI32_LOCK_A_PERIPHLOCK0_LPTL_UNLOCKED_VALUE 0 319 #define SI32_LOCK_A_PERIPHLOCK0_LPTL_UNLOCKED_U32 \ 320 (SI32_LOCK_A_PERIPHLOCK0_LPTL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_LPTL_SHIFT) 321 // Lock the Low Power Timer (LPTIMER0) Module registers (bits can still be read). 322 #define SI32_LOCK_A_PERIPHLOCK0_LPTL_LOCKED_VALUE 1 323 #define SI32_LOCK_A_PERIPHLOCK0_LPTL_LOCKED_U32 \ 324 (SI32_LOCK_A_PERIPHLOCK0_LPTL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_LPTL_SHIFT) 325 326 #define SI32_LOCK_A_PERIPHLOCK0_LDOL_MASK 0x00020000 327 #define SI32_LOCK_A_PERIPHLOCK0_LDOL_SHIFT 17 328 // Unlock the LDO0 Module registers. 329 #define SI32_LOCK_A_PERIPHLOCK0_LDOL_UNLOCKED_VALUE 0 330 #define SI32_LOCK_A_PERIPHLOCK0_LDOL_UNLOCKED_U32 \ 331 (SI32_LOCK_A_PERIPHLOCK0_LDOL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_LDOL_SHIFT) 332 // Lock the LDO0 Module registers (bits can still be read). 333 #define SI32_LOCK_A_PERIPHLOCK0_LDOL_LOCKED_VALUE 1 334 #define SI32_LOCK_A_PERIPHLOCK0_LDOL_LOCKED_U32 \ 335 (SI32_LOCK_A_PERIPHLOCK0_LDOL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_LDOL_SHIFT) 336 337 #define SI32_LOCK_A_PERIPHLOCK0_PLLL_MASK 0x00040000 338 #define SI32_LOCK_A_PERIPHLOCK0_PLLL_SHIFT 18 339 // Unlock the PLL0 Module registers. 340 #define SI32_LOCK_A_PERIPHLOCK0_PLLL_UNLOCKED_VALUE 0 341 #define SI32_LOCK_A_PERIPHLOCK0_PLLL_UNLOCKED_U32 \ 342 (SI32_LOCK_A_PERIPHLOCK0_PLLL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_PLLL_SHIFT) 343 // Lock the PLL0 Module registers (bits can still be read). 344 #define SI32_LOCK_A_PERIPHLOCK0_PLLL_LOCKED_VALUE 1 345 #define SI32_LOCK_A_PERIPHLOCK0_PLLL_LOCKED_U32 \ 346 (SI32_LOCK_A_PERIPHLOCK0_PLLL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_PLLL_SHIFT) 347 348 #define SI32_LOCK_A_PERIPHLOCK0_EXTOSCL_MASK 0x00080000 349 #define SI32_LOCK_A_PERIPHLOCK0_EXTOSCL_SHIFT 19 350 // Unlock the External Oscillator (EXTOSC0) Module registers. 351 #define SI32_LOCK_A_PERIPHLOCK0_EXTOSCL_UNLOCKED_VALUE 0 352 #define SI32_LOCK_A_PERIPHLOCK0_EXTOSCL_UNLOCKED_U32 \ 353 (SI32_LOCK_A_PERIPHLOCK0_EXTOSCL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_EXTOSCL_SHIFT) 354 // Lock the External Oscillator (EXTOSC0) Module registers (bits can still be 355 // read). 356 #define SI32_LOCK_A_PERIPHLOCK0_EXTOSCL_LOCKED_VALUE 1 357 #define SI32_LOCK_A_PERIPHLOCK0_EXTOSCL_LOCKED_U32 \ 358 (SI32_LOCK_A_PERIPHLOCK0_EXTOSCL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_EXTOSCL_SHIFT) 359 360 #define SI32_LOCK_A_PERIPHLOCK0_PVTL_MASK 0x00100000 361 #define SI32_LOCK_A_PERIPHLOCK0_PVTL_SHIFT 20 362 // Unlock the PVTOSC0 Module registers. 363 #define SI32_LOCK_A_PERIPHLOCK0_PVTL_UNLOCKED_VALUE 0 364 #define SI32_LOCK_A_PERIPHLOCK0_PVTL_UNLOCKED_U32 \ 365 (SI32_LOCK_A_PERIPHLOCK0_PVTL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_PVTL_SHIFT) 366 // Lock the PVTOSC0 Module registers (bits can still be read). 367 #define SI32_LOCK_A_PERIPHLOCK0_PVTL_LOCKED_VALUE 1 368 #define SI32_LOCK_A_PERIPHLOCK0_PVTL_LOCKED_U32 \ 369 (SI32_LOCK_A_PERIPHLOCK0_PVTL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_PVTL_SHIFT) 370 371 #define SI32_LOCK_A_PERIPHLOCK0_LPOSCL_MASK 0x00200000 372 #define SI32_LOCK_A_PERIPHLOCK0_LPOSCL_SHIFT 21 373 // Unlock the Low Power Oscillator (LPOSC0) Module registers. 374 #define SI32_LOCK_A_PERIPHLOCK0_LPOSCL_UNLOCKED_VALUE 0 375 #define SI32_LOCK_A_PERIPHLOCK0_LPOSCL_UNLOCKED_U32 \ 376 (SI32_LOCK_A_PERIPHLOCK0_LPOSCL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_LPOSCL_SHIFT) 377 // Lock the Low Power Oscillator (LPOSC0) Module registers (bits can still be 378 // read). 379 #define SI32_LOCK_A_PERIPHLOCK0_LPOSCL_LOCKED_VALUE 1 380 #define SI32_LOCK_A_PERIPHLOCK0_LPOSCL_LOCKED_U32 \ 381 (SI32_LOCK_A_PERIPHLOCK0_LPOSCL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_LPOSCL_SHIFT) 382 383 #define SI32_LOCK_A_PERIPHLOCK0_ACCTRL_MASK 0x00400000 384 #define SI32_LOCK_A_PERIPHLOCK0_ACCTRL_SHIFT 22 385 // Unlock the Advanced Capture Counter (ACCTR0) Module registers. 386 #define SI32_LOCK_A_PERIPHLOCK0_ACCTRL_UNLOCKED_VALUE 0 387 #define SI32_LOCK_A_PERIPHLOCK0_ACCTRL_UNLOCKED_U32 \ 388 (SI32_LOCK_A_PERIPHLOCK0_ACCTRL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_ACCTRL_SHIFT) 389 // Lock the Advanced Capture Counter (ACCTR0) Module registers (bits can still be 390 // read). 391 #define SI32_LOCK_A_PERIPHLOCK0_ACCTRL_LOCKED_VALUE 1 392 #define SI32_LOCK_A_PERIPHLOCK0_ACCTRL_LOCKED_U32 \ 393 (SI32_LOCK_A_PERIPHLOCK0_ACCTRL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_ACCTRL_SHIFT) 394 395 #define SI32_LOCK_A_PERIPHLOCK0_PMUL_MASK 0x08000000 396 #define SI32_LOCK_A_PERIPHLOCK0_PMUL_SHIFT 27 397 // Unlock the PMU Module registers. 398 #define SI32_LOCK_A_PERIPHLOCK0_PMUL_UNLOCKED_VALUE 0 399 #define SI32_LOCK_A_PERIPHLOCK0_PMUL_UNLOCKED_U32 \ 400 (SI32_LOCK_A_PERIPHLOCK0_PMUL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_PMUL_SHIFT) 401 // Lock the PMU Module registers (bits can still be read). 402 #define SI32_LOCK_A_PERIPHLOCK0_PMUL_LOCKED_VALUE 1 403 #define SI32_LOCK_A_PERIPHLOCK0_PMUL_LOCKED_U32 \ 404 (SI32_LOCK_A_PERIPHLOCK0_PMUL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_PMUL_SHIFT) 405 406 #define SI32_LOCK_A_PERIPHLOCK0_DTML_MASK 0x10000000 407 #define SI32_LOCK_A_PERIPHLOCK0_DTML_SHIFT 28 408 // Unlock the DTM0, DTM1, and DTM2 Module registers. 409 #define SI32_LOCK_A_PERIPHLOCK0_DTML_UNLOCKED_VALUE 0 410 #define SI32_LOCK_A_PERIPHLOCK0_DTML_UNLOCKED_U32 \ 411 (SI32_LOCK_A_PERIPHLOCK0_DTML_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_DTML_SHIFT) 412 // Lock the DTM0, DTM1, and DTM2 Module registers (bits can still be read). 413 #define SI32_LOCK_A_PERIPHLOCK0_DTML_LOCKED_VALUE 1 414 #define SI32_LOCK_A_PERIPHLOCK0_DTML_LOCKED_U32 \ 415 (SI32_LOCK_A_PERIPHLOCK0_DTML_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_DTML_SHIFT) 416 417 #define SI32_LOCK_A_PERIPHLOCK0_LCDL_MASK 0x20000000 418 #define SI32_LOCK_A_PERIPHLOCK0_LCDL_SHIFT 29 419 // Unlock the LCD0 Module registers. 420 #define SI32_LOCK_A_PERIPHLOCK0_LCDL_UNLOCKED_VALUE 0 421 #define SI32_LOCK_A_PERIPHLOCK0_LCDL_UNLOCKED_U32 \ 422 (SI32_LOCK_A_PERIPHLOCK0_LCDL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_LCDL_SHIFT) 423 // Lock the LCD0 Module registers (bits can still be read). 424 #define SI32_LOCK_A_PERIPHLOCK0_LCDL_LOCKED_VALUE 1 425 #define SI32_LOCK_A_PERIPHLOCK0_LCDL_LOCKED_U32 \ 426 (SI32_LOCK_A_PERIPHLOCK0_LCDL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_LCDL_SHIFT) 427 428 #define SI32_LOCK_A_PERIPHLOCK0_DCDCL_MASK 0x40000000 429 #define SI32_LOCK_A_PERIPHLOCK0_DCDCL_SHIFT 30 430 // Unlock the DCDC0 Module registers. 431 #define SI32_LOCK_A_PERIPHLOCK0_DCDCL_UNLOCKED_VALUE 0 432 #define SI32_LOCK_A_PERIPHLOCK0_DCDCL_UNLOCKED_U32 \ 433 (SI32_LOCK_A_PERIPHLOCK0_DCDCL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_DCDCL_SHIFT) 434 // Lock the DCDC0 Module registers (bits can still be read). 435 #define SI32_LOCK_A_PERIPHLOCK0_DCDCL_LOCKED_VALUE 1 436 #define SI32_LOCK_A_PERIPHLOCK0_DCDCL_LOCKED_U32 \ 437 (SI32_LOCK_A_PERIPHLOCK0_DCDCL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK0_DCDCL_SHIFT) 438 439 440 441 struct SI32_LOCK_A_PERIPHLOCK1_Struct 442 { 443 union 444 { 445 struct 446 { 447 // Encoder Decoder Module Lock 448 volatile uint32_t ENCDECL: 1; 449 uint32_t reserved0: 31; 450 }; 451 volatile uint32_t U32; 452 }; 453 }; 454 455 #define SI32_LOCK_A_PERIPHLOCK1_ENCDECL_MASK 0x00000001 456 #define SI32_LOCK_A_PERIPHLOCK1_ENCDECL_SHIFT 0 457 // Unlock the ENCDEC0 Module registers. 458 #define SI32_LOCK_A_PERIPHLOCK1_ENCDECL_UNLOCKED_VALUE 0 459 #define SI32_LOCK_A_PERIPHLOCK1_ENCDECL_UNLOCKED_U32 \ 460 (SI32_LOCK_A_PERIPHLOCK1_ENCDECL_UNLOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK1_ENCDECL_SHIFT) 461 // Lock the ENCDEC0 Module registers (bits can still be read). 462 #define SI32_LOCK_A_PERIPHLOCK1_ENCDECL_LOCKED_VALUE 1 463 #define SI32_LOCK_A_PERIPHLOCK1_ENCDECL_LOCKED_U32 \ 464 (SI32_LOCK_A_PERIPHLOCK1_ENCDECL_LOCKED_VALUE << SI32_LOCK_A_PERIPHLOCK1_ENCDECL_SHIFT) 465 466 467 468 typedef struct SI32_LOCK_A_Struct 469 { 470 struct SI32_LOCK_A_KEY_Struct KEY ; // Base Address + 0x0 471 uint32_t reserved0; 472 uint32_t reserved1; 473 uint32_t reserved2; 474 uint32_t reserved3[4]; 475 struct SI32_LOCK_A_PERIPHLOCK0_Struct PERIPHLOCK0 ; // Base Address + 0x20 476 volatile uint32_t PERIPHLOCK0_SET; 477 volatile uint32_t PERIPHLOCK0_CLR; 478 uint32_t reserved4; 479 uint32_t reserved5[4]; 480 struct SI32_LOCK_A_PERIPHLOCK1_Struct PERIPHLOCK1 ; // Base Address + 0x40 481 volatile uint32_t PERIPHLOCK1_SET; 482 volatile uint32_t PERIPHLOCK1_CLR; 483 uint32_t reserved6; 484 } SI32_LOCK_A_Type; 485 486 #ifdef __cplusplus 487 } 488 #endif 489 490 #endif // __SI32_LOCK_A_REGISTERS_H__ 491 492 //-eof-------------------------------------------------------------------------- 493 494
