1 2 //------------------------------------------------------------------------------ 3 // Copyright 2012 (c) Silicon Laboratories Inc. 4 // 5 // SPDX-License-Identifier: Zlib 6 // 7 // This siHAL software is provided 'as-is', without any express or implied 8 // warranty. In no event will the authors be held liable for any damages 9 // arising from the use of this software. 10 // 11 // Permission is granted to anyone to use this software for any purpose, 12 // including commercial applications, and to alter it and redistribute it 13 // freely, subject to the following restrictions: 14 // 15 // 1. The origin of this software must not be misrepresented; you must not 16 // claim that you wrote the original software. If you use this software 17 // in a product, an acknowledgment in the product documentation would be 18 // appreciated but is not required. 19 // 2. Altered source versions must be plainly marked as such, and must not be 20 // misrepresented as being the original software. 21 // 3. This notice may not be removed or altered from any source distribution. 22 //------------------------------------------------------------------------------ 23 24 #ifndef __SIM3C1XX_H__ 25 #define __SIM3C1XX_H__ 26 27 #ifdef __cplusplus 28 extern "C" { 29 #endif 30 31 #define __MPU_PRESENT 0 32 #define __NVIC_PRIO_BITS 4 33 #define __Vendor_SysTickConfig 0 34 35 typedef enum IRQn 36 { 37 // CPU 38 NonMaskableInt_IRQn = -14, // 2 39 MemoryManagement_IRQn = -12, // 4 40 BusFault_IRQn = -11, // 5 41 UsageFault_IRQn = -10, // 6 42 SVCall_IRQn = -5, // 11 43 DebugMonitor_IRQn = -4, // 12 44 PendSV_IRQn = -2, // 14 45 SysTick_IRQn = -1, // 15 46 // MCU 47 WDTIMER0_IRQn = 0, 48 PBEXT0_IRQn = 1, 49 PBEXT1_IRQn = 2, 50 RTC0ALRM_IRQn = 3, 51 DMACH0_IRQn = 4, 52 DMACH1_IRQn = 5, 53 DMACH2_IRQn = 6, 54 DMACH3_IRQn = 7, 55 DMACH4_IRQn = 8, 56 DMACH5_IRQn = 9, 57 DMACH6_IRQn = 10, 58 DMACH7_IRQn = 11, 59 DMACH8_IRQn = 12, 60 DMACH9_IRQn = 13, 61 DMACH10_IRQn = 14, 62 DMACH11_IRQn = 15, 63 DMACH12_IRQn = 16, 64 DMACH13_IRQn = 17, 65 DMACH14_IRQn = 18, 66 DMACH15_IRQn = 19, 67 TIMER0L_IRQn = 20, 68 TIMER0H_IRQn = 21, 69 TIMER1L_IRQn = 22, 70 TIMER1H_IRQn = 23, 71 EPCA0_IRQn = 24, 72 PCA0_IRQn = 25, 73 PCA1_IRQn = 26, 74 USART0_IRQn = 27, 75 USART1_IRQn = 28, 76 SPI0_IRQn = 29, 77 SPI1_IRQn = 30, 78 SPI2_IRQn = 31, 79 I2C0_IRQn = 32, 80 I2C1_IRQn = 33, 81 SARADC0_IRQn = 35, 82 SARADC1_IRQn = 36, 83 CMP0_IRQn = 37, 84 CMP1_IRQn = 38, 85 CAPSENSE0_IRQn = 39, 86 I2S0RX_IRQn = 40, 87 I2S0TX_IRQn = 41, 88 AES0_IRQn = 42, 89 VDDLOW_IRQn = 43, 90 RTC0FAIL_IRQn = 44, 91 PMATCH_IRQn = 45, 92 UART0_IRQn = 46, 93 UART1_IRQn = 47, 94 IDAC0_IRQn = 48, 95 IDAC1_IRQn = 49, 96 LPTIMER0_IRQn = 50, 97 PLL0_IRQn = 51, 98 VBUSINVALID_IRQn = 52, 99 VREG0LOW_IRQn = 53, 100 } IRQn_Type; 101 102 #include <core_cm3.h> 103 #include <system_sim3c1xx.h> 104 105 //----------------------------------------------------------------------------- 106 107 #include <SI32_AES_A_Registers.h> 108 #include <SI32_CAPSENSE_A_Registers.h> 109 #include <SI32_CMP_A_Registers.h> 110 #include <SI32_CRC_A_Registers.h> 111 #include <SI32_DMACTRL_A_Registers.h> 112 #include <SI32_DMADESC_A_Registers.h> 113 #include <SI32_EMIF_A_Registers.h> 114 #include <SI32_EMIFIF_A_Registers.h> 115 #include <SI32_EPCA_A_Registers.h> 116 #include <SI32_EPCACH_A_Registers.h> 117 #include <SI32_EXTOSC_A_Registers.h> 118 #include <SI32_EXTVREG_A_Registers.h> 119 #include <SI32_FLASHCTRL_A_Registers.h> 120 #include <SI32_I2C_A_Registers.h> 121 #include <SI32_I2S_A_Registers.h> 122 #include <SI32_IDAC_A_Registers.h> 123 #include <SI32_IVC_A_Registers.h> 124 #include <SI32_LPTIMER_A_Registers.h> 125 #include <SI32_PCA_A_Registers.h> 126 #include <SI32_PCACH_A_Registers.h> 127 #include <SI32_PLL_A_Registers.h> 128 #include <SI32_RTC_A_Registers.h> 129 #include <SI32_SARADC_A_Registers.h> 130 #include <SI32_SPI_A_Registers.h> 131 #include <SI32_SSG_A_Registers.h> 132 #include <SI32_TIMER_A_Registers.h> 133 #include <SI32_USART_A_Registers.h> 134 #include <SI32_UART_A_Registers.h> 135 #include <SI32_VMON_A_Registers.h> 136 #include <SI32_VREF_A_Registers.h> 137 #include <SI32_VREG_A_Registers.h> 138 #include <SI32_WDTIMER_A_Registers.h> 139 140 #include <SI32_SIM3C1XX_CLKCTRL_A_Registers.h> 141 #include <SI32_SIM3C1XX_DEVICEID_A_Registers.h> 142 #include <SI32_SIM3C1XX_DMAXBAR_A_Registers.h> 143 #include <SI32_SIM3C1XX_LDO_A_Registers.h> 144 #include <SI32_SIM3C1XX_LOCK_A_Registers.h> 145 #include <SI32_SIM3C1XX_PBCFG_A_Registers.h> 146 #include <SI32_SIM3C1XX_PBSTD_A_Registers.h> 147 #include <SI32_SIM3C1XX_PBHD_A_Registers.h> 148 #include <SI32_SIM3C1XX_PMU_A_Registers.h> 149 #include <SI32_SIM3C1XX_RSTSRC_A_Registers.h> 150 #include <SI32_SIM3C1XX_SCONFIG_A_Registers.h> 151 152 //----------------------------------------------------------------------------- 153 // Define constants for the chip's memory regions. 154 #define SI32_MCU_FLASH_BASE 0x00000000 155 #define SI32_MCU_RAM_BASE 0x20000000 156 157 #if defined(SI32_MCU_SIM3C16X) 158 # define SI32_MCU_FLASH_SIZE 0x0003FFFC 159 # define SI32_MCU_RAM_SIZE 0x00008000 160 #elif defined(SI32_MCU_SIM3C15X) 161 # define SI32_MCU_FLASH_SIZE 0x00020000 162 # define SI32_MCU_RAM_SIZE 0x00008000 163 #elif defined(SI32_MCU_SIM3C14X) 164 # define SI32_MCU_FLASH_SIZE 0x00010000 165 # define SI32_MCU_RAM_SIZE 0x00004000 166 #else //defined(SI32_MCU_SIM3C13X) 167 # define SI32_MCU_FLASH_SIZE 0x00008000 168 # define SI32_MCU_RAM_SIZE 0x00002000 169 #endif 170 171 #define SI32_MCU_RETENTION_RAM_BASE SI32_MCU_RAM_BASE 172 #define SI32_MCU_RETENTION_RAM_SIZE 0x00001000 173 174 #define SI32_MCU_EMIF_CS0_BASE 0x60000000 175 #define SI32_MCU_EMIF_CS1_BASE 0x68000000 176 #define SI32_MCU_EMIF_SIZE 0x08000000 177 178 //------------------------------------------------------------------------------ 179 // ARM RealView 180 #if defined (__CC_ARM) 181 182 #define __SI32_RETENTION_REGION __attribute__ ((section(".SI32.RETENTION"), zero_init)) 183 #define __SI32_EMIF_CS0_REGION __attribute__ ((section(".SI32.EMIF_CS0"))) 184 #define __SI32_EMIF_CS1_REGION __attribute__ ((section(".SI32.EMIF_CS1"))) 185 186 //------------------------------------------------------------------------------ 187 // IAR 188 #elif defined (__ICCARM__) 189 190 #define __SI32_RETENTION_REGION _Pragma("location=\".SI32.RETENTION\"") 191 #define __SI32_EMIF_CS0_REGION _Pragma("location=\".SI32.EMIF_CS0\"") 192 #define __SI32_EMIF_CS1_REGION _Pragma("location=\".SI32.EMIF_CS1\"") 193 194 //------------------------------------------------------------------------------ 195 // GCC 196 #elif defined (__GNUC__) 197 198 #define __SI32_RETENTION_REGION __attribute__ ((section(".bss.$RESERVED"))) 199 #define __SI32_EMIF_CS0_REGION 200 #define __SI32_EMIF_CS1_REGION 201 202 #endif 203 204 //----------------------------------------------------------------------------- 205 // Define the instances of the peripherals 206 207 // USART 208 #define SI32_USART_0 ((SI32_USART_A_Type*)0x40000000) 209 #define SI32_USART_1 ((SI32_USART_A_Type*)0x40001000) 210 211 // UART 212 #define SI32_UART_0 ((SI32_UART_A_Type*)0x40002000) 213 #define SI32_UART_1 ((SI32_UART_A_Type*)0x40003000) 214 215 // SPI 216 #define SI32_SPI_0 ((SI32_SPI_A_Type*)0x40004000) 217 #define SI32_SPI_1 ((SI32_SPI_A_Type*)0x40005000) 218 #define SI32_SPI_2 ((SI32_SPI_A_Type*)0x40006000) 219 220 // I2C 221 #define SI32_I2C_0 ((SI32_I2C_A_Type*)0x40009000) 222 #define SI32_I2C_1 ((SI32_I2C_A_Type*)0x4000A000) 223 224 // PCAE 225 #define SI32_EPCA_0 ((SI32_EPCA_A_Type*) 0x4000E180) 226 #define SI32_EPCA_0_CH0 ((SI32_EPCACH_A_Type*)0x4000E000) 227 #define SI32_EPCA_0_CH1 ((SI32_EPCACH_A_Type*)0x4000E040) 228 #define SI32_EPCA_0_CH2 ((SI32_EPCACH_A_Type*)0x4000E080) 229 #define SI32_EPCA_0_CH3 ((SI32_EPCACH_A_Type*)0x4000E0C0) 230 #define SI32_EPCA_0_CH4 ((SI32_EPCACH_A_Type*)0x4000E100) 231 #define SI32_EPCA_0_CH5 ((SI32_EPCACH_A_Type*)0x4000E140) 232 233 // PCA 234 #define SI32_PCA_0 ((SI32_PCA_A_Type*) 0x4000F180) 235 #define SI32_PCA_0_CH0 ((SI32_PCACH_A_Type*)0x4000F000) 236 #define SI32_PCA_0_CH1 ((SI32_PCACH_A_Type*)0x4000F040) 237 #define SI32_PCA_1 ((SI32_PCA_A_Type*) 0x40010180) 238 #define SI32_PCA_1_CH0 ((SI32_PCACH_A_Type*)0x40010000) 239 #define SI32_PCA_1_CH1 ((SI32_PCACH_A_Type*)0x40010040) 240 241 // Timers 242 #define SI32_TIMER_0 ((SI32_TIMER_A_Type*)0x40014000) 243 #define SI32_TIMER_1 ((SI32_TIMER_A_Type*)0x40015000) 244 245 // ADCs 246 #define SI32_SARADC_0 ((SI32_SARADC_A_Type*)0x4001A000) 247 #define SI32_SARADC_1 ((SI32_SARADC_A_Type*)0x4001B000) 248 249 // SSG0 250 #define SI32_SSG_0 ((SI32_SSG_A_Type*)0x4001E000) 251 252 // Comparator 253 #define SI32_CMP_0 ((SI32_CMP_A_Type*)0x4001F000) 254 #define SI32_CMP_1 ((SI32_CMP_A_Type*)0x40020000) 255 256 // LDO 257 #define SI32_LDO_0 ((SI32_LDO_A_Type*)0x40039000) 258 259 // VREF 260 #define SI32_VREF_0 ((SI32_VREF_A_Type*)0x40039010) 261 262 // CapSense 263 #define SI32_CAPSENSE_0 ((SI32_CAPSENSE_A_Type*)0x40023000) 264 265 // EMIF 266 #define SI32_EMIF_0 ((SI32_EMIF_A_Type*) 0x40026000) 267 #define SI32_EMIF_0_IF0 ((SI32_EMIFIF_A_Type*)0x40026080) 268 #define SI32_EMIF_0_IF1 ((SI32_EMIFIF_A_Type*)0x40026100) 269 270 // AES 271 #define SI32_AES_0 ((SI32_AES_A_Type*)0x40027000) 272 273 // CRC 274 #define SI32_CRC_0 ((SI32_CRC_A_Type*)0x40028000) 275 276 // RTC and LFO 277 #define SI32_RTC_0 ((SI32_RTC_A_Type*)0x40029000) 278 279 // Port I/O 280 #define SI32_PBCFG_0 ((SI32_PBCFG_A_Type*)0x4002A000) 281 #define SI32_PBSTD_0 ((SI32_PBSTD_A_Type*)0x4002A0A0) 282 #define SI32_PBSTD_1 ((SI32_PBSTD_A_Type*)0x4002A140) 283 #define SI32_PBSTD_2 ((SI32_PBSTD_A_Type*)0x4002A1E0) 284 #define SI32_PBSTD_3 ((SI32_PBSTD_A_Type*)0x4002A320) 285 #define SI32_PBHD_4 ((SI32_PBHD_A_Type*) 0x4002A3C0) 286 287 // Clock Control 288 #define SI32_CLKCTRL_0 ((SI32_CLKCTRL_A_Type*)0x4002D000) 289 290 // Reset Sources 291 #define SI32_RSTSRC_0 ((SI32_RSTSRC_A_Type*)0x4002D060) 292 293 // Flash Interface 294 #define SI32_FLASHCTRL_0 ((SI32_FLASHCTRL_A_Type*)0x4002E000) 295 296 // VDD Monitor 297 #define SI32_VMON_0 ((SI32_VMON_A_Type*)0x4002F000) 298 299 // Watchdog Timer 300 #define SI32_WDTIMER_0 ((SI32_WDTIMER_A_Type*)0x40030000) 301 302 // DACs 303 #define SI32_IDAC_0 ((SI32_IDAC_A_Type*)0x40031000) 304 #define SI32_IDAC_1 ((SI32_IDAC_A_Type*)0x40032000) 305 306 // DMA Controller 307 #define SI32_DMACTRL_0 ((SI32_DMACTRL_A_Type*)0x40036000) 308 309 // DMA Crossbar 310 #define SI32_DMAXBAR_0 ((SI32_DMAXBAR_A_Type*)0x40037000) 311 312 // Low Power Timer 313 #define SI32_LPTIMER_0 ((SI32_LPTIMER_A_Type*)0x40038000) 314 315 // Voltage Regulators 316 #define SI32_VREG_0 ((SI32_VREG_A_Type*) 0x40040000) 317 #define SI32_EXTVREG_0 ((SI32_EXTVREG_A_Type*)0x40042000) 318 319 // I2S 320 #define SI32_I2S_0 ((SI32_I2S_A_Type*)0x4003A000) 321 322 // PLL 323 #define SI32_PLL_0 ((SI32_PLL_A_Type*)0x4003B000) 324 325 // IVC 326 #define SI32_IVC_0 ((SI32_IVC_A_Type*)0x40044000) 327 328 // Oscillators 329 #define SI32_LPOSC_0 ((SI32_LPOSC_A_Type*) 0x40041000) 330 #define SI32_EXTOSC_0 ((SI32_EXTOSC_A_Type*)0x4003C000) 331 332 // PMU 333 #define SI32_PMU_0 ((SI32_PMU_A_Type*)0x40048000) 334 335 // Lock 336 #define SI32_LOCK_0 ((SI32_LOCK_A_Type*)0x40049000) 337 338 // System Configuration 339 #define SI32_SCONFIG_0 ((SI32_SCONFIG_A_Type*)0x400490B0) 340 341 // Device ID 342 #define SI32_DEVICEID_0 ((SI32_DEVICEID_A_Type*)0x400490C0) 343 344 //----------------------------------------------------------------------------- 345 346 #ifdef __cplusplus 347 } 348 #endif 349 350 #endif // __SIM3C1XX_H__ 351 352 //-eof------------------------------------------------------------------------- 353 354
