1 //------------------------------------------------------------------------------ 2 // Copyright 2012 (c) Silicon Laboratories Inc. 3 // 4 // SPDX-License-Identifier: Zlib 5 // 6 // This siHAL software is provided 'as-is', without any express or implied 7 // warranty. In no event will the authors be held liable for any damages 8 // arising from the use of this software. 9 // 10 // Permission is granted to anyone to use this software for any purpose, 11 // including commercial applications, and to alter it and redistribute it 12 // freely, subject to the following restrictions: 13 // 14 // 1. The origin of this software must not be misrepresented; you must not 15 // claim that you wrote the original software. If you use this software 16 // in a product, an acknowledgment in the product documentation would be 17 // appreciated but is not required. 18 // 2. Altered source versions must be plainly marked as such, and must not be 19 // misrepresented as being the original software. 20 // 3. This notice may not be removed or altered from any source distribution. 21 //------------------------------------------------------------------------------ 22 // 23 // This file applies to the SIM3C1XX_CLKCTRL_A module 24 // 25 // Script: 0.57 26 // Version: 1 27 28 #ifndef __SI32_CLKCTRL_A_REGISTERS_H__ 29 #define __SI32_CLKCTRL_A_REGISTERS_H__ 30 31 #include <stdint.h> 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 struct SI32_CLKCTRL_A_CONTROL_Struct 38 { 39 union 40 { 41 struct 42 { 43 // AHB Clock Source Select 44 volatile uint32_t AHBSEL: 3; 45 uint32_t reserved0: 5; 46 // AHB Clock Divider 47 volatile uint32_t AHBDIV: 3; 48 uint32_t reserved1: 5; 49 // APB Clock Divider 50 volatile uint32_t APBDIV: 1; 51 uint32_t reserved2: 11; 52 // External Clock Edge Select 53 volatile uint32_t EXTESEL: 1; 54 // Oscillators Busy Flag 55 volatile uint32_t OBUSYF: 1; 56 uint32_t reserved3: 2; 57 }; 58 volatile uint32_t U32; 59 }; 60 }; 61 62 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_MASK 0x00000007 63 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_SHIFT 0 64 // AHB clock source is the Low-Power Oscillator. 65 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_LPOSC0_VALUE 0 66 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_LPOSC0_U32 \ 67 (SI32_CLKCTRL_A_CONTROL_AHBSEL_LPOSC0_VALUE << SI32_CLKCTRL_A_CONTROL_AHBSEL_SHIFT) 68 // AHB clock source is the Low-Frequency Oscillator. 69 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_LFOSC0_VALUE 1 70 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_LFOSC0_U32 \ 71 (SI32_CLKCTRL_A_CONTROL_AHBSEL_LFOSC0_VALUE << SI32_CLKCTRL_A_CONTROL_AHBSEL_SHIFT) 72 // AHB clock source is the RTC Oscillator. 73 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_RTC0OSC_VALUE 2 74 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_RTC0OSC_U32 \ 75 (SI32_CLKCTRL_A_CONTROL_AHBSEL_RTC0OSC_VALUE << SI32_CLKCTRL_A_CONTROL_AHBSEL_SHIFT) 76 // AHB clock source is the External Oscillator. 77 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_EXTOSC0_VALUE 3 78 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_EXTOSC0_U32 \ 79 (SI32_CLKCTRL_A_CONTROL_AHBSEL_EXTOSC0_VALUE << SI32_CLKCTRL_A_CONTROL_AHBSEL_SHIFT) 80 // AHB clock source is the PLL. 81 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_PLL0OSC_VALUE 5 82 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_PLL0OSC_U32 \ 83 (SI32_CLKCTRL_A_CONTROL_AHBSEL_PLL0OSC_VALUE << SI32_CLKCTRL_A_CONTROL_AHBSEL_SHIFT) 84 // AHB clock source is a divided version of the Low-Power Oscillator. 85 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_LPOSC0_DIV_VALUE 6 86 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_LPOSC0_DIV_U32 \ 87 (SI32_CLKCTRL_A_CONTROL_AHBSEL_LPOSC0_DIV_VALUE << SI32_CLKCTRL_A_CONTROL_AHBSEL_SHIFT) 88 89 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_MASK 0x00000700 90 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_SHIFT 8 91 // AHB clock divided by 1. 92 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV1_VALUE 0 93 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV1_U32 \ 94 (SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV1_VALUE << SI32_CLKCTRL_A_CONTROL_AHBDIV_SHIFT) 95 // AHB clock divided by 2. 96 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV2_VALUE 1 97 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV2_U32 \ 98 (SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV2_VALUE << SI32_CLKCTRL_A_CONTROL_AHBDIV_SHIFT) 99 // AHB clock divided by 4. 100 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV4_VALUE 2 101 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV4_U32 \ 102 (SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV4_VALUE << SI32_CLKCTRL_A_CONTROL_AHBDIV_SHIFT) 103 // AHB clock divided by 8. 104 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV8_VALUE 3 105 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV8_U32 \ 106 (SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV8_VALUE << SI32_CLKCTRL_A_CONTROL_AHBDIV_SHIFT) 107 // AHB clock divided by 16. 108 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV16_VALUE 4 109 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV16_U32 \ 110 (SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV16_VALUE << SI32_CLKCTRL_A_CONTROL_AHBDIV_SHIFT) 111 // AHB clock divided by 32. 112 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV32_VALUE 5 113 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV32_U32 \ 114 (SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV32_VALUE << SI32_CLKCTRL_A_CONTROL_AHBDIV_SHIFT) 115 // AHB clock divided by 64. 116 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV64_VALUE 6 117 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV64_U32 \ 118 (SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV64_VALUE << SI32_CLKCTRL_A_CONTROL_AHBDIV_SHIFT) 119 // AHB clock divided by 128. 120 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV128_VALUE 7 121 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV128_U32 \ 122 (SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV128_VALUE << SI32_CLKCTRL_A_CONTROL_AHBDIV_SHIFT) 123 124 #define SI32_CLKCTRL_A_CONTROL_APBDIV_MASK 0x00010000 125 #define SI32_CLKCTRL_A_CONTROL_APBDIV_SHIFT 16 126 // APB clock is the same as the AHB clock (divided by 1). 127 #define SI32_CLKCTRL_A_CONTROL_APBDIV_DIV1_VALUE 0 128 #define SI32_CLKCTRL_A_CONTROL_APBDIV_DIV1_U32 \ 129 (SI32_CLKCTRL_A_CONTROL_APBDIV_DIV1_VALUE << SI32_CLKCTRL_A_CONTROL_APBDIV_SHIFT) 130 // APB clock is the AHB clock divided by 2. 131 #define SI32_CLKCTRL_A_CONTROL_APBDIV_DIV2_VALUE 1 132 #define SI32_CLKCTRL_A_CONTROL_APBDIV_DIV2_U32 \ 133 (SI32_CLKCTRL_A_CONTROL_APBDIV_DIV2_VALUE << SI32_CLKCTRL_A_CONTROL_APBDIV_SHIFT) 134 135 #define SI32_CLKCTRL_A_CONTROL_EXTESEL_MASK 0x10000000 136 #define SI32_CLKCTRL_A_CONTROL_EXTESEL_SHIFT 28 137 // External clock generated by both rising and falling edges of the external 138 // oscillator. 139 #define SI32_CLKCTRL_A_CONTROL_EXTESEL_BOTH_EDGES_VALUE 0 140 #define SI32_CLKCTRL_A_CONTROL_EXTESEL_BOTH_EDGES_U32 \ 141 (SI32_CLKCTRL_A_CONTROL_EXTESEL_BOTH_EDGES_VALUE << SI32_CLKCTRL_A_CONTROL_EXTESEL_SHIFT) 142 // External clock generated by only rising edges of the external oscillator. 143 #define SI32_CLKCTRL_A_CONTROL_EXTESEL_RISING_ONLY_VALUE 1 144 #define SI32_CLKCTRL_A_CONTROL_EXTESEL_RISING_ONLY_U32 \ 145 (SI32_CLKCTRL_A_CONTROL_EXTESEL_RISING_ONLY_VALUE << SI32_CLKCTRL_A_CONTROL_EXTESEL_SHIFT) 146 147 #define SI32_CLKCTRL_A_CONTROL_OBUSYF_MASK 0x20000000 148 #define SI32_CLKCTRL_A_CONTROL_OBUSYF_SHIFT 29 149 // AHB and APB oscillators are not busy. 150 #define SI32_CLKCTRL_A_CONTROL_OBUSYF_NOT_SET_VALUE 0 151 #define SI32_CLKCTRL_A_CONTROL_OBUSYF_NOT_SET_U32 \ 152 (SI32_CLKCTRL_A_CONTROL_OBUSYF_NOT_SET_VALUE << SI32_CLKCTRL_A_CONTROL_OBUSYF_SHIFT) 153 // AHB and APB oscillators are busy and the AHBSEL, AHBDIV, and APBDIV fields 154 // should not be modified. 155 #define SI32_CLKCTRL_A_CONTROL_OBUSYF_SET_VALUE 1 156 #define SI32_CLKCTRL_A_CONTROL_OBUSYF_SET_U32 \ 157 (SI32_CLKCTRL_A_CONTROL_OBUSYF_SET_VALUE << SI32_CLKCTRL_A_CONTROL_OBUSYF_SHIFT) 158 159 160 161 struct SI32_CLKCTRL_A_AHBCLKG_Struct 162 { 163 union 164 { 165 struct 166 { 167 // RAM Clock Enable 168 volatile uint32_t RAMCEN: 1; 169 // DMA Controller Clock Enable 170 volatile uint32_t DMACEN: 1; 171 // Flash Clock Enable 172 volatile uint32_t FLASHCEN: 1; 173 // EMIF Clock Enable 174 volatile uint32_t EMIF0CEN: 1; 175 uint32_t reserved0: 28; 176 }; 177 volatile uint32_t U32; 178 }; 179 }; 180 181 #define SI32_CLKCTRL_A_AHBCLKG_RAMCEN_MASK 0x00000001 182 #define SI32_CLKCTRL_A_AHBCLKG_RAMCEN_SHIFT 0 183 // Disable the AHB clock to the RAM. 184 #define SI32_CLKCTRL_A_AHBCLKG_RAMCEN_DISABLED_VALUE 0 185 #define SI32_CLKCTRL_A_AHBCLKG_RAMCEN_DISABLED_U32 \ 186 (SI32_CLKCTRL_A_AHBCLKG_RAMCEN_DISABLED_VALUE << SI32_CLKCTRL_A_AHBCLKG_RAMCEN_SHIFT) 187 // Enable the AHB clock to the RAM (default). 188 #define SI32_CLKCTRL_A_AHBCLKG_RAMCEN_ENABLED_VALUE 1 189 #define SI32_CLKCTRL_A_AHBCLKG_RAMCEN_ENABLED_U32 \ 190 (SI32_CLKCTRL_A_AHBCLKG_RAMCEN_ENABLED_VALUE << SI32_CLKCTRL_A_AHBCLKG_RAMCEN_SHIFT) 191 192 #define SI32_CLKCTRL_A_AHBCLKG_DMACEN_MASK 0x00000002 193 #define SI32_CLKCTRL_A_AHBCLKG_DMACEN_SHIFT 1 194 // Disable the AHB clock to the DMA Controller (default). 195 #define SI32_CLKCTRL_A_AHBCLKG_DMACEN_DISABLED_VALUE 0 196 #define SI32_CLKCTRL_A_AHBCLKG_DMACEN_DISABLED_U32 \ 197 (SI32_CLKCTRL_A_AHBCLKG_DMACEN_DISABLED_VALUE << SI32_CLKCTRL_A_AHBCLKG_DMACEN_SHIFT) 198 // Enable the AHB clock to the DMA Controller. 199 #define SI32_CLKCTRL_A_AHBCLKG_DMACEN_ENABLED_VALUE 1 200 #define SI32_CLKCTRL_A_AHBCLKG_DMACEN_ENABLED_U32 \ 201 (SI32_CLKCTRL_A_AHBCLKG_DMACEN_ENABLED_VALUE << SI32_CLKCTRL_A_AHBCLKG_DMACEN_SHIFT) 202 203 #define SI32_CLKCTRL_A_AHBCLKG_FLASHCEN_MASK 0x00000004 204 #define SI32_CLKCTRL_A_AHBCLKG_FLASHCEN_SHIFT 2 205 // Disable the AHB clock to the Flash. 206 #define SI32_CLKCTRL_A_AHBCLKG_FLASHCEN_DISABLED_VALUE 0 207 #define SI32_CLKCTRL_A_AHBCLKG_FLASHCEN_DISABLED_U32 \ 208 (SI32_CLKCTRL_A_AHBCLKG_FLASHCEN_DISABLED_VALUE << SI32_CLKCTRL_A_AHBCLKG_FLASHCEN_SHIFT) 209 // Enable the AHB clock to the Flash (default). 210 #define SI32_CLKCTRL_A_AHBCLKG_FLASHCEN_ENABLED_VALUE 1 211 #define SI32_CLKCTRL_A_AHBCLKG_FLASHCEN_ENABLED_U32 \ 212 (SI32_CLKCTRL_A_AHBCLKG_FLASHCEN_ENABLED_VALUE << SI32_CLKCTRL_A_AHBCLKG_FLASHCEN_SHIFT) 213 214 #define SI32_CLKCTRL_A_AHBCLKG_EMIF0CEN_MASK 0x00000008 215 #define SI32_CLKCTRL_A_AHBCLKG_EMIF0CEN_SHIFT 3 216 // Disable the AHB clock to the External Memory Interface (EMIF) (default). 217 #define SI32_CLKCTRL_A_AHBCLKG_EMIF0CEN_DISABLED_VALUE 0 218 #define SI32_CLKCTRL_A_AHBCLKG_EMIF0CEN_DISABLED_U32 \ 219 (SI32_CLKCTRL_A_AHBCLKG_EMIF0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_AHBCLKG_EMIF0CEN_SHIFT) 220 // Enable the AHB clock to the External Memory Interface (EMIF). 221 #define SI32_CLKCTRL_A_AHBCLKG_EMIF0CEN_ENABLED_VALUE 1 222 #define SI32_CLKCTRL_A_AHBCLKG_EMIF0CEN_ENABLED_U32 \ 223 (SI32_CLKCTRL_A_AHBCLKG_EMIF0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_AHBCLKG_EMIF0CEN_SHIFT) 224 225 226 227 struct SI32_CLKCTRL_A_APBCLKG0_Struct 228 { 229 union 230 { 231 struct 232 { 233 // PLL Module Clock Enable 234 volatile uint32_t PLL0CEN: 1; 235 // Port Bank Module Clock Enable 236 volatile uint32_t PB0CEN: 1; 237 // USART0 Module Clock Enable 238 volatile uint32_t USART0CEN: 1; 239 // USART1 Module Clock Enable 240 volatile uint32_t USART1CEN: 1; 241 // UART0 Module Clock Enable 242 volatile uint32_t UART0CEN: 1; 243 // UART1 Module Clock Enable 244 volatile uint32_t UART1CEN: 1; 245 // SPI0 Module Clock Enable 246 volatile uint32_t SPI0CEN: 1; 247 // SPI1 Module Clock Enable 248 volatile uint32_t SPI1CEN: 1; 249 // SPI2 Module Clock Enable 250 volatile uint32_t SPI2CEN: 1; 251 // I2C0 Module Clock Enable 252 volatile uint32_t I2C0CEN: 1; 253 // I2C1 Module Clock Enable 254 volatile uint32_t I2C1CEN: 1; 255 // EPCA0 Module Clock Enable 256 volatile uint32_t EPCA0CEN: 1; 257 // PCA0 Module Clock Enable 258 volatile uint32_t PCA0CEN: 1; 259 // PCA1 Module Clock Enable 260 volatile uint32_t PCA1CEN: 1; 261 // SSG0 Module Clock Enable 262 volatile uint32_t SSG0CEN: 1; 263 // TIMER0 Module Clock Enable 264 volatile uint32_t TIMER0CEN: 1; 265 // TIMER1 Module Clock Enable 266 volatile uint32_t TIMER1CEN: 1; 267 // SARADC0 Module Clock Enable 268 volatile uint32_t ADC0CEN: 1; 269 // SARADC1 Module Clock Enable 270 volatile uint32_t ADC1CEN: 1; 271 // Comparator 0 Module Clock Enable 272 volatile uint32_t CMP0CEN: 1; 273 // Comparator 1 Module Clock Enable 274 volatile uint32_t CMP1CEN: 1; 275 // Capacitive Sensing (CAPSENSE0) Module Clock Enable 276 volatile uint32_t CS0CEN: 1; 277 // AES0 Module Clock Enable 278 volatile uint32_t AES0CEN: 1; 279 // CRC0 Module Clock Enable 280 volatile uint32_t CRC0CEN: 1; 281 // IDAC0 Module Clock Enable 282 volatile uint32_t IDAC0CEN: 1; 283 // IDAC1 Module Clock Enable 284 volatile uint32_t IDAC1CEN: 1; 285 // Low Power Timer (LPTIMER0) Module Clock Enable 286 volatile uint32_t LPT0CEN: 1; 287 // I2S0 Module Clock Enable 288 volatile uint32_t I2S0CEN: 1; 289 uint32_t reserved0: 1; 290 // External Regulator Clock Enable 291 volatile uint32_t EVREGCEN: 1; 292 // Flash Controller Clock Enable 293 volatile uint32_t FLCTRLCEN: 1; 294 uint32_t reserved1: 1; 295 }; 296 volatile uint32_t U32; 297 }; 298 }; 299 300 #define SI32_CLKCTRL_A_APBCLKG0_PLL0CEN_MASK 0x00000001 301 #define SI32_CLKCTRL_A_APBCLKG0_PLL0CEN_SHIFT 0 302 // Disable the APB clock to the PLL0 registers (default). 303 #define SI32_CLKCTRL_A_APBCLKG0_PLL0CEN_DISABLED_VALUE 0 304 #define SI32_CLKCTRL_A_APBCLKG0_PLL0CEN_DISABLED_U32 \ 305 (SI32_CLKCTRL_A_APBCLKG0_PLL0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_PLL0CEN_SHIFT) 306 // Enable the APB clock to the PLL0 registers. 307 #define SI32_CLKCTRL_A_APBCLKG0_PLL0CEN_ENABLED_VALUE 1 308 #define SI32_CLKCTRL_A_APBCLKG0_PLL0CEN_ENABLED_U32 \ 309 (SI32_CLKCTRL_A_APBCLKG0_PLL0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_PLL0CEN_SHIFT) 310 311 #define SI32_CLKCTRL_A_APBCLKG0_PB0CEN_MASK 0x00000002 312 #define SI32_CLKCTRL_A_APBCLKG0_PB0CEN_SHIFT 1 313 // Disable the APB clock to the Port Bank Modules (default). 314 #define SI32_CLKCTRL_A_APBCLKG0_PB0CEN_DISABLED_VALUE 0 315 #define SI32_CLKCTRL_A_APBCLKG0_PB0CEN_DISABLED_U32 \ 316 (SI32_CLKCTRL_A_APBCLKG0_PB0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_PB0CEN_SHIFT) 317 // Enable the APB clock to the Port Bank Modules. 318 #define SI32_CLKCTRL_A_APBCLKG0_PB0CEN_ENABLED_VALUE 1 319 #define SI32_CLKCTRL_A_APBCLKG0_PB0CEN_ENABLED_U32 \ 320 (SI32_CLKCTRL_A_APBCLKG0_PB0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_PB0CEN_SHIFT) 321 322 #define SI32_CLKCTRL_A_APBCLKG0_USART0CEN_MASK 0x00000004 323 #define SI32_CLKCTRL_A_APBCLKG0_USART0CEN_SHIFT 2 324 // Disable the APB clock to the USART0 Module (default). 325 #define SI32_CLKCTRL_A_APBCLKG0_USART0CEN_DISABLED_VALUE 0 326 #define SI32_CLKCTRL_A_APBCLKG0_USART0CEN_DISABLED_U32 \ 327 (SI32_CLKCTRL_A_APBCLKG0_USART0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_USART0CEN_SHIFT) 328 // Enable the APB clock to the USART0 Module. 329 #define SI32_CLKCTRL_A_APBCLKG0_USART0CEN_ENABLED_VALUE 1 330 #define SI32_CLKCTRL_A_APBCLKG0_USART0CEN_ENABLED_U32 \ 331 (SI32_CLKCTRL_A_APBCLKG0_USART0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_USART0CEN_SHIFT) 332 333 #define SI32_CLKCTRL_A_APBCLKG0_USART1CEN_MASK 0x00000008 334 #define SI32_CLKCTRL_A_APBCLKG0_USART1CEN_SHIFT 3 335 // Disable the APB clock to the USART1 Module (default). 336 #define SI32_CLKCTRL_A_APBCLKG0_USART1CEN_DISABLED_VALUE 0 337 #define SI32_CLKCTRL_A_APBCLKG0_USART1CEN_DISABLED_U32 \ 338 (SI32_CLKCTRL_A_APBCLKG0_USART1CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_USART1CEN_SHIFT) 339 // Enable the APB clock to the USART1 Module. 340 #define SI32_CLKCTRL_A_APBCLKG0_USART1CEN_ENABLED_VALUE 1 341 #define SI32_CLKCTRL_A_APBCLKG0_USART1CEN_ENABLED_U32 \ 342 (SI32_CLKCTRL_A_APBCLKG0_USART1CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_USART1CEN_SHIFT) 343 344 #define SI32_CLKCTRL_A_APBCLKG0_UART0CEN_MASK 0x00000010 345 #define SI32_CLKCTRL_A_APBCLKG0_UART0CEN_SHIFT 4 346 // Disable the APB clock to the UART0 Module (default). 347 #define SI32_CLKCTRL_A_APBCLKG0_UART0CEN_DISABLED_VALUE 0 348 #define SI32_CLKCTRL_A_APBCLKG0_UART0CEN_DISABLED_U32 \ 349 (SI32_CLKCTRL_A_APBCLKG0_UART0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_UART0CEN_SHIFT) 350 // Enable the APB clock to the UART0 Module. 351 #define SI32_CLKCTRL_A_APBCLKG0_UART0CEN_ENABLED_VALUE 1 352 #define SI32_CLKCTRL_A_APBCLKG0_UART0CEN_ENABLED_U32 \ 353 (SI32_CLKCTRL_A_APBCLKG0_UART0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_UART0CEN_SHIFT) 354 355 #define SI32_CLKCTRL_A_APBCLKG0_UART1CEN_MASK 0x00000020 356 #define SI32_CLKCTRL_A_APBCLKG0_UART1CEN_SHIFT 5 357 // Disable the APB clock to the UART1 Module (default). 358 #define SI32_CLKCTRL_A_APBCLKG0_UART1CEN_DISABLED_VALUE 0 359 #define SI32_CLKCTRL_A_APBCLKG0_UART1CEN_DISABLED_U32 \ 360 (SI32_CLKCTRL_A_APBCLKG0_UART1CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_UART1CEN_SHIFT) 361 // Enable the APB clock to the UART1 Module. 362 #define SI32_CLKCTRL_A_APBCLKG0_UART1CEN_ENABLED_VALUE 1 363 #define SI32_CLKCTRL_A_APBCLKG0_UART1CEN_ENABLED_U32 \ 364 (SI32_CLKCTRL_A_APBCLKG0_UART1CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_UART1CEN_SHIFT) 365 366 #define SI32_CLKCTRL_A_APBCLKG0_SPI0CEN_MASK 0x00000040 367 #define SI32_CLKCTRL_A_APBCLKG0_SPI0CEN_SHIFT 6 368 // Disable the APB clock to the SPI0 Module (default). 369 #define SI32_CLKCTRL_A_APBCLKG0_SPI0CEN_DISABLED_VALUE 0 370 #define SI32_CLKCTRL_A_APBCLKG0_SPI0CEN_DISABLED_U32 \ 371 (SI32_CLKCTRL_A_APBCLKG0_SPI0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_SPI0CEN_SHIFT) 372 // Enable the APB clock to the SPI0 Module. 373 #define SI32_CLKCTRL_A_APBCLKG0_SPI0CEN_ENABLED_VALUE 1 374 #define SI32_CLKCTRL_A_APBCLKG0_SPI0CEN_ENABLED_U32 \ 375 (SI32_CLKCTRL_A_APBCLKG0_SPI0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_SPI0CEN_SHIFT) 376 377 #define SI32_CLKCTRL_A_APBCLKG0_SPI1CEN_MASK 0x00000080 378 #define SI32_CLKCTRL_A_APBCLKG0_SPI1CEN_SHIFT 7 379 // Disable the APB clock to the SPI1 Module (default). 380 #define SI32_CLKCTRL_A_APBCLKG0_SPI1CEN_DISABLED_VALUE 0 381 #define SI32_CLKCTRL_A_APBCLKG0_SPI1CEN_DISABLED_U32 \ 382 (SI32_CLKCTRL_A_APBCLKG0_SPI1CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_SPI1CEN_SHIFT) 383 // Enable the APB clock to the SPI1 Module. 384 #define SI32_CLKCTRL_A_APBCLKG0_SPI1CEN_ENABLED_VALUE 1 385 #define SI32_CLKCTRL_A_APBCLKG0_SPI1CEN_ENABLED_U32 \ 386 (SI32_CLKCTRL_A_APBCLKG0_SPI1CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_SPI1CEN_SHIFT) 387 388 #define SI32_CLKCTRL_A_APBCLKG0_SPI2CEN_MASK 0x00000100 389 #define SI32_CLKCTRL_A_APBCLKG0_SPI2CEN_SHIFT 8 390 // Disable the APB clock to the SPI2 Module (default). 391 #define SI32_CLKCTRL_A_APBCLKG0_SPI2CEN_DISABLED_VALUE 0 392 #define SI32_CLKCTRL_A_APBCLKG0_SPI2CEN_DISABLED_U32 \ 393 (SI32_CLKCTRL_A_APBCLKG0_SPI2CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_SPI2CEN_SHIFT) 394 // Enable the APB clock to the SPI2 Module. 395 #define SI32_CLKCTRL_A_APBCLKG0_SPI2CEN_ENABLED_VALUE 1 396 #define SI32_CLKCTRL_A_APBCLKG0_SPI2CEN_ENABLED_U32 \ 397 (SI32_CLKCTRL_A_APBCLKG0_SPI2CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_SPI2CEN_SHIFT) 398 399 #define SI32_CLKCTRL_A_APBCLKG0_I2C0CEN_MASK 0x00000200 400 #define SI32_CLKCTRL_A_APBCLKG0_I2C0CEN_SHIFT 9 401 // Disable the APB clock to the I2C0 Module (default). 402 #define SI32_CLKCTRL_A_APBCLKG0_I2C0CEN_DISABLED_VALUE 0 403 #define SI32_CLKCTRL_A_APBCLKG0_I2C0CEN_DISABLED_U32 \ 404 (SI32_CLKCTRL_A_APBCLKG0_I2C0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_I2C0CEN_SHIFT) 405 // Enable the APB clock to the I2C0 Module. 406 #define SI32_CLKCTRL_A_APBCLKG0_I2C0CEN_ENABLED_VALUE 1 407 #define SI32_CLKCTRL_A_APBCLKG0_I2C0CEN_ENABLED_U32 \ 408 (SI32_CLKCTRL_A_APBCLKG0_I2C0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_I2C0CEN_SHIFT) 409 410 #define SI32_CLKCTRL_A_APBCLKG0_I2C1CEN_MASK 0x00000400 411 #define SI32_CLKCTRL_A_APBCLKG0_I2C1CEN_SHIFT 10 412 // Disable the APB clock to the I2C1 Module (default). 413 #define SI32_CLKCTRL_A_APBCLKG0_I2C1CEN_DISABLED_VALUE 0 414 #define SI32_CLKCTRL_A_APBCLKG0_I2C1CEN_DISABLED_U32 \ 415 (SI32_CLKCTRL_A_APBCLKG0_I2C1CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_I2C1CEN_SHIFT) 416 // Enable the APB clock to the I2C1 Module. 417 #define SI32_CLKCTRL_A_APBCLKG0_I2C1CEN_ENABLED_VALUE 1 418 #define SI32_CLKCTRL_A_APBCLKG0_I2C1CEN_ENABLED_U32 \ 419 (SI32_CLKCTRL_A_APBCLKG0_I2C1CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_I2C1CEN_SHIFT) 420 421 #define SI32_CLKCTRL_A_APBCLKG0_EPCA0CEN_MASK 0x00000800 422 #define SI32_CLKCTRL_A_APBCLKG0_EPCA0CEN_SHIFT 11 423 // Disable the APB clock to the EPCA0 Module (default). 424 #define SI32_CLKCTRL_A_APBCLKG0_EPCA0CEN_DISABLED_VALUE 0 425 #define SI32_CLKCTRL_A_APBCLKG0_EPCA0CEN_DISABLED_U32 \ 426 (SI32_CLKCTRL_A_APBCLKG0_EPCA0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_EPCA0CEN_SHIFT) 427 // Enable the APB clock to the EPCA0 Module. 428 #define SI32_CLKCTRL_A_APBCLKG0_EPCA0CEN_ENABLED_VALUE 1 429 #define SI32_CLKCTRL_A_APBCLKG0_EPCA0CEN_ENABLED_U32 \ 430 (SI32_CLKCTRL_A_APBCLKG0_EPCA0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_EPCA0CEN_SHIFT) 431 432 #define SI32_CLKCTRL_A_APBCLKG0_PCA0CEN_MASK 0x00001000 433 #define SI32_CLKCTRL_A_APBCLKG0_PCA0CEN_SHIFT 12 434 // Disable the APB clock to the PCA0 Module (default). 435 #define SI32_CLKCTRL_A_APBCLKG0_PCA0CEN_DISABLED_VALUE 0 436 #define SI32_CLKCTRL_A_APBCLKG0_PCA0CEN_DISABLED_U32 \ 437 (SI32_CLKCTRL_A_APBCLKG0_PCA0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_PCA0CEN_SHIFT) 438 // Enable the APB clock to the PCA0 Module. 439 #define SI32_CLKCTRL_A_APBCLKG0_PCA0CEN_ENABLED_VALUE 1 440 #define SI32_CLKCTRL_A_APBCLKG0_PCA0CEN_ENABLED_U32 \ 441 (SI32_CLKCTRL_A_APBCLKG0_PCA0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_PCA0CEN_SHIFT) 442 443 #define SI32_CLKCTRL_A_APBCLKG0_PCA1CEN_MASK 0x00002000 444 #define SI32_CLKCTRL_A_APBCLKG0_PCA1CEN_SHIFT 13 445 // Disable the APB clock to the PCA1 Module (default). 446 #define SI32_CLKCTRL_A_APBCLKG0_PCA1CEN_DISABLED_VALUE 0 447 #define SI32_CLKCTRL_A_APBCLKG0_PCA1CEN_DISABLED_U32 \ 448 (SI32_CLKCTRL_A_APBCLKG0_PCA1CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_PCA1CEN_SHIFT) 449 // Enable the APB clock to the PCA1 Module. 450 #define SI32_CLKCTRL_A_APBCLKG0_PCA1CEN_ENABLED_VALUE 1 451 #define SI32_CLKCTRL_A_APBCLKG0_PCA1CEN_ENABLED_U32 \ 452 (SI32_CLKCTRL_A_APBCLKG0_PCA1CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_PCA1CEN_SHIFT) 453 454 #define SI32_CLKCTRL_A_APBCLKG0_SSG0CEN_MASK 0x00004000 455 #define SI32_CLKCTRL_A_APBCLKG0_SSG0CEN_SHIFT 14 456 // Disable the APB clock to the SSG0 Module (default). 457 #define SI32_CLKCTRL_A_APBCLKG0_SSG0CEN_DISABLED_VALUE 0 458 #define SI32_CLKCTRL_A_APBCLKG0_SSG0CEN_DISABLED_U32 \ 459 (SI32_CLKCTRL_A_APBCLKG0_SSG0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_SSG0CEN_SHIFT) 460 // Enable the APB clock to the SSG0 Module. 461 #define SI32_CLKCTRL_A_APBCLKG0_SSG0CEN_ENABLED_VALUE 1 462 #define SI32_CLKCTRL_A_APBCLKG0_SSG0CEN_ENABLED_U32 \ 463 (SI32_CLKCTRL_A_APBCLKG0_SSG0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_SSG0CEN_SHIFT) 464 465 #define SI32_CLKCTRL_A_APBCLKG0_TIMER0CEN_MASK 0x00008000 466 #define SI32_CLKCTRL_A_APBCLKG0_TIMER0CEN_SHIFT 15 467 // Disable the APB clock to the TIMER0 Module (default). 468 #define SI32_CLKCTRL_A_APBCLKG0_TIMER0CEN_DISABLED_VALUE 0 469 #define SI32_CLKCTRL_A_APBCLKG0_TIMER0CEN_DISABLED_U32 \ 470 (SI32_CLKCTRL_A_APBCLKG0_TIMER0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_TIMER0CEN_SHIFT) 471 // Enable the APB clock to the TIMER0 Module. 472 #define SI32_CLKCTRL_A_APBCLKG0_TIMER0CEN_ENABLED_VALUE 1 473 #define SI32_CLKCTRL_A_APBCLKG0_TIMER0CEN_ENABLED_U32 \ 474 (SI32_CLKCTRL_A_APBCLKG0_TIMER0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_TIMER0CEN_SHIFT) 475 476 #define SI32_CLKCTRL_A_APBCLKG0_TIMER1CEN_MASK 0x00010000 477 #define SI32_CLKCTRL_A_APBCLKG0_TIMER1CEN_SHIFT 16 478 // Disable the APB clock to the TIMER1 Module (default). 479 #define SI32_CLKCTRL_A_APBCLKG0_TIMER1CEN_DISABLED_VALUE 0 480 #define SI32_CLKCTRL_A_APBCLKG0_TIMER1CEN_DISABLED_U32 \ 481 (SI32_CLKCTRL_A_APBCLKG0_TIMER1CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_TIMER1CEN_SHIFT) 482 // Enable the APB clock to the TIMER1 Module. 483 #define SI32_CLKCTRL_A_APBCLKG0_TIMER1CEN_ENABLED_VALUE 1 484 #define SI32_CLKCTRL_A_APBCLKG0_TIMER1CEN_ENABLED_U32 \ 485 (SI32_CLKCTRL_A_APBCLKG0_TIMER1CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_TIMER1CEN_SHIFT) 486 487 #define SI32_CLKCTRL_A_APBCLKG0_ADC0CEN_MASK 0x00020000 488 #define SI32_CLKCTRL_A_APBCLKG0_ADC0CEN_SHIFT 17 489 // Disable the APB clock to the SARADC0 Module (default). 490 #define SI32_CLKCTRL_A_APBCLKG0_ADC0CEN_DISABLED_VALUE 0 491 #define SI32_CLKCTRL_A_APBCLKG0_ADC0CEN_DISABLED_U32 \ 492 (SI32_CLKCTRL_A_APBCLKG0_ADC0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_ADC0CEN_SHIFT) 493 // Enable the APB clock to the SARADC0 Module. 494 #define SI32_CLKCTRL_A_APBCLKG0_ADC0CEN_ENABLED_VALUE 1 495 #define SI32_CLKCTRL_A_APBCLKG0_ADC0CEN_ENABLED_U32 \ 496 (SI32_CLKCTRL_A_APBCLKG0_ADC0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_ADC0CEN_SHIFT) 497 498 #define SI32_CLKCTRL_A_APBCLKG0_ADC1CEN_MASK 0x00040000 499 #define SI32_CLKCTRL_A_APBCLKG0_ADC1CEN_SHIFT 18 500 // Disable the APB clock to the SARADC1 Module (default). 501 #define SI32_CLKCTRL_A_APBCLKG0_ADC1CEN_DISABLED_VALUE 0 502 #define SI32_CLKCTRL_A_APBCLKG0_ADC1CEN_DISABLED_U32 \ 503 (SI32_CLKCTRL_A_APBCLKG0_ADC1CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_ADC1CEN_SHIFT) 504 // Enable the APB clock to the SARADC1 Module. 505 #define SI32_CLKCTRL_A_APBCLKG0_ADC1CEN_ENABLED_VALUE 1 506 #define SI32_CLKCTRL_A_APBCLKG0_ADC1CEN_ENABLED_U32 \ 507 (SI32_CLKCTRL_A_APBCLKG0_ADC1CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_ADC1CEN_SHIFT) 508 509 #define SI32_CLKCTRL_A_APBCLKG0_CMP0CEN_MASK 0x00080000 510 #define SI32_CLKCTRL_A_APBCLKG0_CMP0CEN_SHIFT 19 511 // Disable the APB clock to the Comparator 0 Module (default). 512 #define SI32_CLKCTRL_A_APBCLKG0_CMP0CEN_DISABLED_VALUE 0 513 #define SI32_CLKCTRL_A_APBCLKG0_CMP0CEN_DISABLED_U32 \ 514 (SI32_CLKCTRL_A_APBCLKG0_CMP0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_CMP0CEN_SHIFT) 515 // Enable the APB clock to the Comparator 0 Module. 516 #define SI32_CLKCTRL_A_APBCLKG0_CMP0CEN_ENABLED_VALUE 1 517 #define SI32_CLKCTRL_A_APBCLKG0_CMP0CEN_ENABLED_U32 \ 518 (SI32_CLKCTRL_A_APBCLKG0_CMP0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_CMP0CEN_SHIFT) 519 520 #define SI32_CLKCTRL_A_APBCLKG0_CMP1CEN_MASK 0x00100000 521 #define SI32_CLKCTRL_A_APBCLKG0_CMP1CEN_SHIFT 20 522 // Disable the APB clock to the Comparator 1 Module (default). 523 #define SI32_CLKCTRL_A_APBCLKG0_CMP1CEN_DISABLED_VALUE 0 524 #define SI32_CLKCTRL_A_APBCLKG0_CMP1CEN_DISABLED_U32 \ 525 (SI32_CLKCTRL_A_APBCLKG0_CMP1CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_CMP1CEN_SHIFT) 526 // Enable the APB clock to the Comparator 1 Module. 527 #define SI32_CLKCTRL_A_APBCLKG0_CMP1CEN_ENABLED_VALUE 1 528 #define SI32_CLKCTRL_A_APBCLKG0_CMP1CEN_ENABLED_U32 \ 529 (SI32_CLKCTRL_A_APBCLKG0_CMP1CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_CMP1CEN_SHIFT) 530 531 #define SI32_CLKCTRL_A_APBCLKG0_CS0CEN_MASK 0x00200000 532 #define SI32_CLKCTRL_A_APBCLKG0_CS0CEN_SHIFT 21 533 // Disable the APB clock to the CAPSENSE0 Module (default). 534 #define SI32_CLKCTRL_A_APBCLKG0_CS0CEN_DISABLED_VALUE 0 535 #define SI32_CLKCTRL_A_APBCLKG0_CS0CEN_DISABLED_U32 \ 536 (SI32_CLKCTRL_A_APBCLKG0_CS0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_CS0CEN_SHIFT) 537 // Enable the APB clock to the CAPSENSE0 Module. 538 #define SI32_CLKCTRL_A_APBCLKG0_CS0CEN_ENABLED_VALUE 1 539 #define SI32_CLKCTRL_A_APBCLKG0_CS0CEN_ENABLED_U32 \ 540 (SI32_CLKCTRL_A_APBCLKG0_CS0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_CS0CEN_SHIFT) 541 542 #define SI32_CLKCTRL_A_APBCLKG0_AES0CEN_MASK 0x00400000 543 #define SI32_CLKCTRL_A_APBCLKG0_AES0CEN_SHIFT 22 544 // Disable the APB clock to the AES0 Module (default). 545 #define SI32_CLKCTRL_A_APBCLKG0_AES0CEN_DISABLED_VALUE 0 546 #define SI32_CLKCTRL_A_APBCLKG0_AES0CEN_DISABLED_U32 \ 547 (SI32_CLKCTRL_A_APBCLKG0_AES0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_AES0CEN_SHIFT) 548 // Enable the APB clock to the AES0 Module. 549 #define SI32_CLKCTRL_A_APBCLKG0_AES0CEN_ENABLED_VALUE 1 550 #define SI32_CLKCTRL_A_APBCLKG0_AES0CEN_ENABLED_U32 \ 551 (SI32_CLKCTRL_A_APBCLKG0_AES0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_AES0CEN_SHIFT) 552 553 #define SI32_CLKCTRL_A_APBCLKG0_CRC0CEN_MASK 0x00800000 554 #define SI32_CLKCTRL_A_APBCLKG0_CRC0CEN_SHIFT 23 555 // Disable the APB clock to the CRC0 Module (default). 556 #define SI32_CLKCTRL_A_APBCLKG0_CRC0CEN_DISABLED_VALUE 0 557 #define SI32_CLKCTRL_A_APBCLKG0_CRC0CEN_DISABLED_U32 \ 558 (SI32_CLKCTRL_A_APBCLKG0_CRC0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_CRC0CEN_SHIFT) 559 // Enable the APB clock to the CRC0 Module. 560 #define SI32_CLKCTRL_A_APBCLKG0_CRC0CEN_ENABLED_VALUE 1 561 #define SI32_CLKCTRL_A_APBCLKG0_CRC0CEN_ENABLED_U32 \ 562 (SI32_CLKCTRL_A_APBCLKG0_CRC0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_CRC0CEN_SHIFT) 563 564 #define SI32_CLKCTRL_A_APBCLKG0_IDAC0CEN_MASK 0x01000000 565 #define SI32_CLKCTRL_A_APBCLKG0_IDAC0CEN_SHIFT 24 566 // Disable the APB clock to the IDAC0 Module (default). 567 #define SI32_CLKCTRL_A_APBCLKG0_IDAC0CEN_DISABLED_VALUE 0 568 #define SI32_CLKCTRL_A_APBCLKG0_IDAC0CEN_DISABLED_U32 \ 569 (SI32_CLKCTRL_A_APBCLKG0_IDAC0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_IDAC0CEN_SHIFT) 570 // Enable the APB clock to the IDAC0 Module. 571 #define SI32_CLKCTRL_A_APBCLKG0_IDAC0CEN_ENABLED_VALUE 1 572 #define SI32_CLKCTRL_A_APBCLKG0_IDAC0CEN_ENABLED_U32 \ 573 (SI32_CLKCTRL_A_APBCLKG0_IDAC0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_IDAC0CEN_SHIFT) 574 575 #define SI32_CLKCTRL_A_APBCLKG0_IDAC1CEN_MASK 0x02000000 576 #define SI32_CLKCTRL_A_APBCLKG0_IDAC1CEN_SHIFT 25 577 // Disable the APB clock to the IDAC1 Module (default). 578 #define SI32_CLKCTRL_A_APBCLKG0_IDAC1CEN_DISABLED_VALUE 0 579 #define SI32_CLKCTRL_A_APBCLKG0_IDAC1CEN_DISABLED_U32 \ 580 (SI32_CLKCTRL_A_APBCLKG0_IDAC1CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_IDAC1CEN_SHIFT) 581 // Enable the APB clock to the IDAC1 Module. 582 #define SI32_CLKCTRL_A_APBCLKG0_IDAC1CEN_ENABLED_VALUE 1 583 #define SI32_CLKCTRL_A_APBCLKG0_IDAC1CEN_ENABLED_U32 \ 584 (SI32_CLKCTRL_A_APBCLKG0_IDAC1CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_IDAC1CEN_SHIFT) 585 586 #define SI32_CLKCTRL_A_APBCLKG0_LPT0CEN_MASK 0x04000000 587 #define SI32_CLKCTRL_A_APBCLKG0_LPT0CEN_SHIFT 26 588 // Disable the APB clock to the LPTIMER0 Module (default). 589 #define SI32_CLKCTRL_A_APBCLKG0_LPT0CEN_DISABLED_VALUE 0 590 #define SI32_CLKCTRL_A_APBCLKG0_LPT0CEN_DISABLED_U32 \ 591 (SI32_CLKCTRL_A_APBCLKG0_LPT0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_LPT0CEN_SHIFT) 592 // Enable the APB clock to the LPTIMER0 Module. 593 #define SI32_CLKCTRL_A_APBCLKG0_LPT0CEN_ENABLED_VALUE 1 594 #define SI32_CLKCTRL_A_APBCLKG0_LPT0CEN_ENABLED_U32 \ 595 (SI32_CLKCTRL_A_APBCLKG0_LPT0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_LPT0CEN_SHIFT) 596 597 #define SI32_CLKCTRL_A_APBCLKG0_I2S0CEN_MASK 0x08000000 598 #define SI32_CLKCTRL_A_APBCLKG0_I2S0CEN_SHIFT 27 599 // Disable the APB clock to the I2S0 Module (default). 600 #define SI32_CLKCTRL_A_APBCLKG0_I2S0CEN_DISABLED_VALUE 0 601 #define SI32_CLKCTRL_A_APBCLKG0_I2S0CEN_DISABLED_U32 \ 602 (SI32_CLKCTRL_A_APBCLKG0_I2S0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_I2S0CEN_SHIFT) 603 // Enable the APB clock to the I2S0 Module. 604 #define SI32_CLKCTRL_A_APBCLKG0_I2S0CEN_ENABLED_VALUE 1 605 #define SI32_CLKCTRL_A_APBCLKG0_I2S0CEN_ENABLED_U32 \ 606 (SI32_CLKCTRL_A_APBCLKG0_I2S0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_I2S0CEN_SHIFT) 607 608 #define SI32_CLKCTRL_A_APBCLKG0_EVREGCEN_MASK 0x20000000 609 #define SI32_CLKCTRL_A_APBCLKG0_EVREGCEN_SHIFT 29 610 // Disable the APB clock to the External Regulator Module (EXTVREG0) (default). 611 #define SI32_CLKCTRL_A_APBCLKG0_EVREGCEN_DISABLED_VALUE 0 612 #define SI32_CLKCTRL_A_APBCLKG0_EVREGCEN_DISABLED_U32 \ 613 (SI32_CLKCTRL_A_APBCLKG0_EVREGCEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_EVREGCEN_SHIFT) 614 // Enable the APB clock to the External Regulator Module (EXTVREG0). 615 #define SI32_CLKCTRL_A_APBCLKG0_EVREGCEN_ENABLED_VALUE 1 616 #define SI32_CLKCTRL_A_APBCLKG0_EVREGCEN_ENABLED_U32 \ 617 (SI32_CLKCTRL_A_APBCLKG0_EVREGCEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_EVREGCEN_SHIFT) 618 619 #define SI32_CLKCTRL_A_APBCLKG0_FLCTRLCEN_MASK 0x40000000 620 #define SI32_CLKCTRL_A_APBCLKG0_FLCTRLCEN_SHIFT 30 621 // Disable the APB clock to the Flash Controller Module (FLASHCTRL0) (default). 622 #define SI32_CLKCTRL_A_APBCLKG0_FLCTRLCEN_DISABLED_VALUE 0 623 #define SI32_CLKCTRL_A_APBCLKG0_FLCTRLCEN_DISABLED_U32 \ 624 (SI32_CLKCTRL_A_APBCLKG0_FLCTRLCEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_FLCTRLCEN_SHIFT) 625 // Enable the APB clock to the Flash Controller Module (FLASHCTRL0). 626 #define SI32_CLKCTRL_A_APBCLKG0_FLCTRLCEN_ENABLED_VALUE 1 627 #define SI32_CLKCTRL_A_APBCLKG0_FLCTRLCEN_ENABLED_U32 \ 628 (SI32_CLKCTRL_A_APBCLKG0_FLCTRLCEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_FLCTRLCEN_SHIFT) 629 630 631 632 struct SI32_CLKCTRL_A_APBCLKG1_Struct 633 { 634 union 635 { 636 struct 637 { 638 // Miscellaneous 0 Clock Enable 639 volatile uint32_t MISC0CEN: 1; 640 // Miscellaneous 1 Clock Enable 641 volatile uint32_t MISC1CEN: 1; 642 // Miscellaneous 2 Clock Enable 643 volatile uint32_t MISC2CEN: 1; 644 uint32_t reserved0: 29; 645 }; 646 volatile uint32_t U32; 647 }; 648 }; 649 650 #define SI32_CLKCTRL_A_APBCLKG1_MISC0CEN_MASK 0x00000001 651 #define SI32_CLKCTRL_A_APBCLKG1_MISC0CEN_SHIFT 0 652 // Disable the APB clock to the RSTSRC0, LOCK0, VMON0, VREG0, LDO0, VREF0, EXTOSC0, 653 // LPOSC0, EXTVREG0, IVC0 and RTC0 modules (default). 654 #define SI32_CLKCTRL_A_APBCLKG1_MISC0CEN_DISABLED_VALUE 0 655 #define SI32_CLKCTRL_A_APBCLKG1_MISC0CEN_DISABLED_U32 \ 656 (SI32_CLKCTRL_A_APBCLKG1_MISC0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG1_MISC0CEN_SHIFT) 657 // Enable the APB clock to the RSTSRC0, LOCK0, VMON0, VREG0, LDO0, VREF0, EXTOSC0, 658 // LPOSC0, EXTVREG0, IVC0 and RTC0 modules. 659 #define SI32_CLKCTRL_A_APBCLKG1_MISC0CEN_ENABLED_VALUE 1 660 #define SI32_CLKCTRL_A_APBCLKG1_MISC0CEN_ENABLED_U32 \ 661 (SI32_CLKCTRL_A_APBCLKG1_MISC0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG1_MISC0CEN_SHIFT) 662 663 #define SI32_CLKCTRL_A_APBCLKG1_MISC1CEN_MASK 0x00000002 664 #define SI32_CLKCTRL_A_APBCLKG1_MISC1CEN_SHIFT 1 665 // Disable the APB clock to the Watchdog Timer (WDTIMER0), EMIF0, and DMA Crossbar 666 // (DMAXBAR0) modules. 667 #define SI32_CLKCTRL_A_APBCLKG1_MISC1CEN_DISABLED_VALUE 0 668 #define SI32_CLKCTRL_A_APBCLKG1_MISC1CEN_DISABLED_U32 \ 669 (SI32_CLKCTRL_A_APBCLKG1_MISC1CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG1_MISC1CEN_SHIFT) 670 // Enable the APB clock to the Watchdog Timer (WDTIMER0), EMIF0, and DMA Crossbar 671 // (DMAXBAR0) modules (default). 672 #define SI32_CLKCTRL_A_APBCLKG1_MISC1CEN_ENABLED_VALUE 1 673 #define SI32_CLKCTRL_A_APBCLKG1_MISC1CEN_ENABLED_U32 \ 674 (SI32_CLKCTRL_A_APBCLKG1_MISC1CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG1_MISC1CEN_SHIFT) 675 676 #define SI32_CLKCTRL_A_APBCLKG1_MISC2CEN_MASK 0x00000004 677 #define SI32_CLKCTRL_A_APBCLKG1_MISC2CEN_SHIFT 2 678 // Disable the APB clock to the OSCVLDF flag in the EXTOSC module (default). 679 #define SI32_CLKCTRL_A_APBCLKG1_MISC2CEN_DISABLED_VALUE 0 680 #define SI32_CLKCTRL_A_APBCLKG1_MISC2CEN_DISABLED_U32 \ 681 (SI32_CLKCTRL_A_APBCLKG1_MISC2CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG1_MISC2CEN_SHIFT) 682 // Enable the APB clock to the OSCVLDF flag in the EXTOSC module. 683 #define SI32_CLKCTRL_A_APBCLKG1_MISC2CEN_ENABLED_VALUE 1 684 #define SI32_CLKCTRL_A_APBCLKG1_MISC2CEN_ENABLED_U32 \ 685 (SI32_CLKCTRL_A_APBCLKG1_MISC2CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG1_MISC2CEN_SHIFT) 686 687 688 689 struct SI32_CLKCTRL_A_PM3CN_Struct 690 { 691 union 692 { 693 struct 694 { 695 // Power Mode 3 Fast-Wake Clock Source 696 volatile uint32_t PM3CSEL: 3; 697 uint32_t reserved0: 13; 698 // Power Mode 3 Fast-Wake Clock Enable 699 volatile uint32_t PM3CEN: 1; 700 uint32_t reserved1: 15; 701 }; 702 volatile uint32_t U32; 703 }; 704 }; 705 706 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_MASK 0x00000007 707 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_SHIFT 0 708 // Power Mode 3 clock source is the Low-Power Oscillator. 709 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_LPOSC0_VALUE 0 710 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_LPOSC0_U32 \ 711 (SI32_CLKCTRL_A_PM3CN_PM3CSEL_LPOSC0_VALUE << SI32_CLKCTRL_A_PM3CN_PM3CSEL_SHIFT) 712 // Power Mode 3 clock source is the Low-Frequency Oscillator. 713 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_LFOSC0_VALUE 1 714 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_LFOSC0_U32 \ 715 (SI32_CLKCTRL_A_PM3CN_PM3CSEL_LFOSC0_VALUE << SI32_CLKCTRL_A_PM3CN_PM3CSEL_SHIFT) 716 // Power Mode 3 clock source is the RTC Oscillator. 717 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_RTC0OSC_VALUE 2 718 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_RTC0OSC_U32 \ 719 (SI32_CLKCTRL_A_PM3CN_PM3CSEL_RTC0OSC_VALUE << SI32_CLKCTRL_A_PM3CN_PM3CSEL_SHIFT) 720 // Power Mode 3 clock source is the External Oscillator. 721 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_EXTOSC0_VALUE 3 722 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_EXTOSC0_U32 \ 723 (SI32_CLKCTRL_A_PM3CN_PM3CSEL_EXTOSC0_VALUE << SI32_CLKCTRL_A_PM3CN_PM3CSEL_SHIFT) 724 // Power Mode 3 clock source is the PLL. 725 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_PLL0OSC_VALUE 5 726 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_PLL0OSC_U32 \ 727 (SI32_CLKCTRL_A_PM3CN_PM3CSEL_PLL0OSC_VALUE << SI32_CLKCTRL_A_PM3CN_PM3CSEL_SHIFT) 728 // Power Mode 3 clock source is a divided version of the Low-Power Oscillator. 729 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_LPOSC0_DIV_VALUE 6 730 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_LPOSC0_DIV_U32 \ 731 (SI32_CLKCTRL_A_PM3CN_PM3CSEL_LPOSC0_DIV_VALUE << SI32_CLKCTRL_A_PM3CN_PM3CSEL_SHIFT) 732 733 #define SI32_CLKCTRL_A_PM3CN_PM3CEN_MASK 0x00010000 734 #define SI32_CLKCTRL_A_PM3CN_PM3CEN_SHIFT 16 735 // Disable the core clock when in Power Mode 3. 736 #define SI32_CLKCTRL_A_PM3CN_PM3CEN_DISABLED_VALUE 0 737 #define SI32_CLKCTRL_A_PM3CN_PM3CEN_DISABLED_U32 \ 738 (SI32_CLKCTRL_A_PM3CN_PM3CEN_DISABLED_VALUE << SI32_CLKCTRL_A_PM3CN_PM3CEN_SHIFT) 739 // The core clock is enabled and runs off the clock selected by PM3CSEL in Power 740 // Mode 3. 741 #define SI32_CLKCTRL_A_PM3CN_PM3CEN_ENABLED_VALUE 1 742 #define SI32_CLKCTRL_A_PM3CN_PM3CEN_ENABLED_U32 \ 743 (SI32_CLKCTRL_A_PM3CN_PM3CEN_ENABLED_VALUE << SI32_CLKCTRL_A_PM3CN_PM3CEN_SHIFT) 744 745 746 747 typedef struct SI32_CLKCTRL_A_Struct 748 { 749 struct SI32_CLKCTRL_A_CONTROL_Struct CONTROL ; // Base Address + 0x0 750 uint32_t reserved0; 751 uint32_t reserved1; 752 uint32_t reserved2; 753 struct SI32_CLKCTRL_A_AHBCLKG_Struct AHBCLKG ; // Base Address + 0x10 754 volatile uint32_t AHBCLKG_SET; 755 volatile uint32_t AHBCLKG_CLR; 756 uint32_t reserved3; 757 struct SI32_CLKCTRL_A_APBCLKG0_Struct APBCLKG0 ; // Base Address + 0x20 758 volatile uint32_t APBCLKG0_SET; 759 volatile uint32_t APBCLKG0_CLR; 760 uint32_t reserved4; 761 struct SI32_CLKCTRL_A_APBCLKG1_Struct APBCLKG1 ; // Base Address + 0x30 762 volatile uint32_t APBCLKG1_SET; 763 volatile uint32_t APBCLKG1_CLR; 764 uint32_t reserved5; 765 struct SI32_CLKCTRL_A_PM3CN_Struct PM3CN ; // Base Address + 0x40 766 uint32_t reserved6; 767 uint32_t reserved7; 768 uint32_t reserved8; 769 } SI32_CLKCTRL_A_Type; 770 771 #ifdef __cplusplus 772 } 773 #endif 774 775 #endif // __SI32_CLKCTRL_A_REGISTERS_H__ 776 777 //-eof-------------------------------------------------------------------------- 778 779
