1 //------------------------------------------------------------------------------ 2 // Copyright 2012 (c) Silicon Laboratories Inc. 3 // 4 // SPDX-License-Identifier: Zlib 5 // 6 // This siHAL software is provided 'as-is', without any express or implied 7 // warranty. In no event will the authors be held liable for any damages 8 // arising from the use of this software. 9 // 10 // Permission is granted to anyone to use this software for any purpose, 11 // including commercial applications, and to alter it and redistribute it 12 // freely, subject to the following restrictions: 13 // 14 // 1. The origin of this software must not be misrepresented; you must not 15 // claim that you wrote the original software. If you use this software 16 // in a product, an acknowledgment in the product documentation would be 17 // appreciated but is not required. 18 // 2. Altered source versions must be plainly marked as such, and must not be 19 // misrepresented as being the original software. 20 // 3. This notice may not be removed or altered from any source distribution. 21 //------------------------------------------------------------------------------ 22 // 23 // This file applies to the SIM3C1XX_DMAXBAR_A module 24 // 25 // Version: 1 26 27 #ifndef __SI32_DMAXBAR_A_Support_Guard__ 28 #define __SI32_DMAXBAR_A_Support_Guard__ 29 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 //----------------------------------------------------------------------------- 37 // Define the number of DMA channels. 38 39 #define SI32_DMACTRL_NUM_CHANNELS 16 40 41 //----------------------------------------------------------------------------- 42 // Define the DMA Crossbar Channel Select Enum Type 43 44 typedef enum SI32_DMAXBAR_CHNSEL_Enum 45 { 46 SI32_DMAXBAR_CHAN0_SPI1_RX = 0x01, 47 SI32_DMAXBAR_CHAN0_USART0_RX = 0x02, 48 SI32_DMAXBAR_CHAN0_I2C0_TX = 0x03, 49 SI32_DMAXBAR_CHAN0_DMA0T0_RISE = 0x04, 50 SI32_DMAXBAR_CHAN0_DMA0T0_FALL = 0x05, 51 SI32_DMAXBAR_CHAN0_DMA0T1_RISE = 0x06, 52 SI32_DMAXBAR_CHAN0_DMA0T1_FALL = 0x07, 53 SI32_DMAXBAR_CHAN0_TIMER0L = 0x08, 54 SI32_DMAXBAR_CHAN0_TIMER0H = 0x09, 55 SI32_DMAXBAR_CHAN0_TIMER1L = 0x0A, 56 SI32_DMAXBAR_CHAN0_TIMER1H = 0x0B, 57 SI32_DMAXBAR_CHAN0_NONE = 0x0F, 58 59 SI32_DMAXBAR_CHAN1_SPI0_RX = 0x11, 60 SI32_DMAXBAR_CHAN1_USART1_RX = 0x12, 61 SI32_DMAXBAR_CHAN1_I2C0_RX = 0x13, 62 SI32_DMAXBAR_CHAN1_IDAC1 = 0x14, 63 SI32_DMAXBAR_CHAN1_EPCA0_CONTROL = 0x15, 64 SI32_DMAXBAR_CHAN1_DMA0T0_RISE = 0x16, 65 SI32_DMAXBAR_CHAN1_DMA0T0_FALL = 0x17, 66 SI32_DMAXBAR_CHAN1_DMA0T1_RISE = 0x18, 67 SI32_DMAXBAR_CHAN1_DMA0T1_FALL = 0x19, 68 SI32_DMAXBAR_CHAN1_TIMER0L = 0x1A, 69 SI32_DMAXBAR_CHAN1_TIMER1L = 0x1B, 70 SI32_DMAXBAR_CHAN1_TIMER1H = 0x1C, 71 SI32_DMAXBAR_CHAN1_NONE = 0x1F, 72 73 SI32_DMAXBAR_CHAN2_SPI0_TX = 0x21, 74 SI32_DMAXBAR_CHAN2_USART0_TX = 0x22, 75 SI32_DMAXBAR_CHAN2_SARADC0 = 0x23, 76 SI32_DMAXBAR_CHAN2_IDAC1 = 0x24, 77 SI32_DMAXBAR_CHAN2_I2S0_TX = 0x25, 78 SI32_DMAXBAR_CHAN2_EPCA0_CONTROL = 0x26, 79 SI32_DMAXBAR_CHAN2_DMA0T0_RISE = 0x27, 80 SI32_DMAXBAR_CHAN2_DMA0T0_FALL = 0x28, 81 SI32_DMAXBAR_CHAN2_DMA0T1_RISE = 0x29, 82 SI32_DMAXBAR_CHAN2_DMA0T1_FALL = 0x2A, 83 SI32_DMAXBAR_CHAN2_NONE = 0x2F, 84 85 SI32_DMAXBAR_CHAN3_SARADC1 = 0x31, 86 SI32_DMAXBAR_CHAN3_IDAC0 = 0x32, 87 SI32_DMAXBAR_CHAN3_I2S0_TX = 0x33, 88 SI32_DMAXBAR_CHAN3_EPCA0_CAPTURE = 0x34, 89 SI32_DMAXBAR_CHAN3_DMA0T0_RISE = 0x35, 90 SI32_DMAXBAR_CHAN3_DMA0T0_FALL = 0x36, 91 SI32_DMAXBAR_CHAN3_DMA0T1_RISE = 0x37, 92 SI32_DMAXBAR_CHAN3_DMA0T1_FALL = 0x38, 93 SI32_DMAXBAR_CHAN3_TIMER1H = 0x39, 94 SI32_DMAXBAR_CHAN3_NONE = 0x3F, 95 96 SI32_DMAXBAR_CHAN4_SPI1_TX = 0x41, 97 SI32_DMAXBAR_CHAN4_USART0_TX = 0x42, 98 SI32_DMAXBAR_CHAN4_SARADC0 = 0x43, 99 SI32_DMAXBAR_CHAN4_I2S0_RX = 0x44, 100 SI32_DMAXBAR_CHAN4_EPCA0_CAPTURE = 0x45, 101 SI32_DMAXBAR_CHAN4_DMA0T0_RISE = 0x46, 102 SI32_DMAXBAR_CHAN4_DMA0T0_FALL = 0x47, 103 SI32_DMAXBAR_CHAN4_DMA0T1_RISE = 0x48, 104 SI32_DMAXBAR_CHAN4_DMA0T1_FALL = 0x49, 105 SI32_DMAXBAR_CHAN4_TIMER0H = 0x4A, 106 SI32_DMAXBAR_CHAN4_NONE = 0x4F, 107 108 SI32_DMAXBAR_CHAN5_AES0_TX = 0x51, 109 SI32_DMAXBAR_CHAN5_USART1_TX = 0x52, 110 SI32_DMAXBAR_CHAN5_SARADC0 = 0x53, 111 SI32_DMAXBAR_CHAN5_I2S0_RX = 0x54, 112 SI32_DMAXBAR_CHAN5_DMA0T0_RISE = 0x55, 113 SI32_DMAXBAR_CHAN5_DMA0T0_FALL = 0x56, 114 SI32_DMAXBAR_CHAN5_DMA0T1_RISE = 0x57, 115 SI32_DMAXBAR_CHAN5_DMA0T1_FALL = 0x58, 116 SI32_DMAXBAR_CHAN5_NONE = 0x5F, 117 118 SI32_DMAXBAR_CHAN6_AES0_RX = 0x61, 119 SI32_DMAXBAR_CHAN6_USART0_RX = 0x62, 120 SI32_DMAXBAR_CHAN6_I2C0_RX = 0x63, 121 SI32_DMAXBAR_CHAN6_IDAC0 = 0x64, 122 SI32_DMAXBAR_CHAN6_DMA0T0_RISE = 0x65, 123 SI32_DMAXBAR_CHAN6_DMA0T0_FALL = 0x66, 124 SI32_DMAXBAR_CHAN6_DMA0T1_RISE = 0x67, 125 SI32_DMAXBAR_CHAN6_DMA0T1_FALL = 0x68, 126 SI32_DMAXBAR_CHAN6_TIMER0H = 0x69, 127 SI32_DMAXBAR_CHAN6_NONE = 0x6F, 128 129 SI32_DMAXBAR_CHAN7_AES0_XOR = 0x71, 130 SI32_DMAXBAR_CHAN7_SPI1_TX = 0x72, 131 SI32_DMAXBAR_CHAN7_USART0_TX = 0x73, 132 SI32_DMAXBAR_CHAN7_DMA0T0_RISE = 0x74, 133 SI32_DMAXBAR_CHAN7_DMA0T0_FALL = 0x75, 134 SI32_DMAXBAR_CHAN7_DMA0T1_RISE = 0x76, 135 SI32_DMAXBAR_CHAN7_DMA0T1_FALL = 0x77, 136 SI32_DMAXBAR_CHAN7_TIMER0L = 0x78, 137 SI32_DMAXBAR_CHAN7_TIMER1L = 0x79, 138 SI32_DMAXBAR_CHAN7_TIMER1H = 0x7A, 139 SI32_DMAXBAR_CHAN7_NONE = 0x7F, 140 141 SI32_DMAXBAR_CHAN8_USART1_RX = 0x81, 142 SI32_DMAXBAR_CHAN8_SPI1_RX = 0x82, 143 SI32_DMAXBAR_CHAN8_USART0_RX = 0x83, 144 SI32_DMAXBAR_CHAN8_EPCA0_CAPTURE = 0x84, 145 SI32_DMAXBAR_CHAN8_DMA0T0_RISE = 0x85, 146 SI32_DMAXBAR_CHAN8_DMA0T0_FALL = 0x86, 147 SI32_DMAXBAR_CHAN8_DMA0T1_RISE = 0x87, 148 SI32_DMAXBAR_CHAN8_DMA0T1_FALL = 0x88, 149 SI32_DMAXBAR_CHAN8_NONE = 0x8F, 150 151 SI32_DMAXBAR_CHAN9_USART1_TX = 0x91, 152 SI32_DMAXBAR_CHAN9_I2C0_TX = 0x92, 153 SI32_DMAXBAR_CHAN9_EPCA0_CAPTURE = 0x93, 154 SI32_DMAXBAR_CHAN9_DMA0T0_RISE = 0x94, 155 SI32_DMAXBAR_CHAN9_DMA0T0_FALL = 0x95, 156 SI32_DMAXBAR_CHAN9_DMA0T1_RISE = 0x96, 157 SI32_DMAXBAR_CHAN9_DMA0T1_FALL = 0x97, 158 SI32_DMAXBAR_CHAN9_TIMER0H = 0x98, 159 SI32_DMAXBAR_CHAN9_NONE = 0x9F, 160 161 SI32_DMAXBAR_CHAN10_AES0_TX = 0xA1, 162 SI32_DMAXBAR_CHAN10_SARADC1 = 0xA2, 163 SI32_DMAXBAR_CHAN10_I2S0_RX = 0xA3, 164 SI32_DMAXBAR_CHAN10_DMA0T0_RISE = 0xA4, 165 SI32_DMAXBAR_CHAN10_DMA0T0_FALL = 0xA5, 166 SI32_DMAXBAR_CHAN10_DMA0T1_RISE = 0xA6, 167 SI32_DMAXBAR_CHAN10_DMA0T1_FALL = 0xA7, 168 SI32_DMAXBAR_CHAN10_TIMER1H = 0xA8, 169 SI32_DMAXBAR_CHAN10_NONE = 0xAF, 170 171 SI32_DMAXBAR_CHAN11_AES0_RX = 0xB1, 172 SI32_DMAXBAR_CHAN11_USART1_RX = 0xB2, 173 SI32_DMAXBAR_CHAN11_USART0_RX = 0xB3, 174 SI32_DMAXBAR_CHAN11_I2C0_RX = 0xB4, 175 SI32_DMAXBAR_CHAN11_I2S0_RX = 0xB5, 176 SI32_DMAXBAR_CHAN11_DMA0T0_RISE = 0xB6, 177 SI32_DMAXBAR_CHAN11_DMA0T0_FALL = 0xB7, 178 SI32_DMAXBAR_CHAN11_DMA0T1_RISE = 0xB8, 179 SI32_DMAXBAR_CHAN11_DMA0T1_FALL = 0xB9, 180 SI32_DMAXBAR_CHAN11_TIMER0H = 0xBA, 181 SI32_DMAXBAR_CHAN11_NONE = 0xBF, 182 183 SI32_DMAXBAR_CHAN12_AES0_XOR = 0xC1, 184 SI32_DMAXBAR_CHAN12_USART1_TX = 0xC2, 185 SI32_DMAXBAR_CHAN12_SPI1_TX = 0xC3, 186 SI32_DMAXBAR_CHAN12_IDAC1 = 0xC4, 187 SI32_DMAXBAR_CHAN12_I2S0_TX = 0xC5, 188 SI32_DMAXBAR_CHAN12_DMA0T0_RISE = 0xC6, 189 SI32_DMAXBAR_CHAN12_DMA0T0_FALL = 0xC7, 190 SI32_DMAXBAR_CHAN12_DMA0T1_RISE = 0xC8, 191 SI32_DMAXBAR_CHAN12_DMA0T1_FALL = 0xC9, 192 SI32_DMAXBAR_CHAN12_TIMER0L = 0xCA, 193 SI32_DMAXBAR_CHAN12_TIMER1L = 0xCB, 194 SI32_DMAXBAR_CHAN12_TIMER1H = 0xCC, 195 SI32_DMAXBAR_CHAN12_NONE = 0xCF, 196 197 SI32_DMAXBAR_CHAN13_SPI0_RX = 0xD1, 198 SI32_DMAXBAR_CHAN13_USART0_RX = 0xD2, 199 SI32_DMAXBAR_CHAN13_IDAC1 = 0xD3, 200 SI32_DMAXBAR_CHAN13_I2S0_TX = 0xD4, 201 SI32_DMAXBAR_CHAN13_DMA0T0_RISE = 0xD5, 202 SI32_DMAXBAR_CHAN13_DMA0T0_FALL = 0xD6, 203 SI32_DMAXBAR_CHAN13_DMA0T1_RISE = 0xD7, 204 SI32_DMAXBAR_CHAN13_DMA0T1_FALL = 0xD8, 205 SI32_DMAXBAR_CHAN13_TIMER0H = 0xD9, 206 SI32_DMAXBAR_CHAN13_NONE = 0xDF, 207 208 SI32_DMAXBAR_CHAN14_SPI0_TX = 0xE1, 209 SI32_DMAXBAR_CHAN14_USART0_TX = 0xE2, 210 SI32_DMAXBAR_CHAN14_IDAC0 = 0xE3, 211 SI32_DMAXBAR_CHAN14_EPCA0_CONTROL = 0xE4, 212 SI32_DMAXBAR_CHAN14_DMA0T0_RISE = 0xE5, 213 SI32_DMAXBAR_CHAN14_DMA0T0_FALL = 0xE6, 214 SI32_DMAXBAR_CHAN14_DMA0T1_RISE = 0xE7, 215 SI32_DMAXBAR_CHAN14_DMA0T1_FALL = 0xE8, 216 SI32_DMAXBAR_CHAN14_TIMER0L = 0xE9, 217 SI32_DMAXBAR_CHAN14_TIMER1L = 0xEA, 218 SI32_DMAXBAR_CHAN14_NONE = 0xEF, 219 220 SI32_DMAXBAR_CHAN15_SARADC1 = 0xF1, 221 SI32_DMAXBAR_CHAN15_IDAC0 = 0xF2, 222 SI32_DMAXBAR_CHAN15_EPCA0_CONTROL = 0xF3, 223 SI32_DMAXBAR_CHAN15_DMA0T0_RISE = 0xF4, 224 SI32_DMAXBAR_CHAN15_DMA0T0_FALL = 0xF5, 225 SI32_DMAXBAR_CHAN15_DMA0T1_RISE = 0xF6, 226 SI32_DMAXBAR_CHAN15_DMA0T1_FALL = 0xF7, 227 SI32_DMAXBAR_CHAN15_TIMER0H = 0xF8, 228 SI32_DMAXBAR_CHAN15_TIMER1H = 0xF9, 229 SI32_DMAXBAR_CHAN15_NONE = 0xFF 230 } 231 SI32_DMAXBAR_CHNSEL_Enum_Type; 232 233 // Extracts DMA channel number from SI32_DMAXBAR_CHNSEL_Enum_Type 234 #define SI32_DMAXBAR_CHANNEL_OF(chsel) (((chsel) & 0xF0) >> 4) 235 236 //----------------------------------------------------------------------------- 237 // Define the DMA Endpoints 238 239 #define SI32_ADC_0_RX_ENDPOINT &SI32_ADC_0->DATA.U32 240 #define SI32_ADC_1_RX_ENDPOINT &SI32_ADC_1->DATA.U32 241 #define SI32_AES_0_TX_ENDPOINT &SI32_AES_0->DATAFIFO.U32 242 #define SI32_AES_0_RX_ENDPOINT &SI32_AES_0->DATAFIFO.U32 243 #define SI32_AES_0_XOR_ENDPOINT &SI32_AES_0->XORFIFO.U32 244 #define SI32_EPCA_0_CH0_RX_ENDPOINT &SI32_EPCA_0_CH0->CCAPV.U32 245 #define SI32_EPCA_0_CH1_RX_ENDPOINT &SI32_EPCA_0_CH1->CCAPV.U32 246 #define SI32_EPCA_0_CH2_RX_ENDPOINT &SI32_EPCA_0_CH2->CCAPV.U32 247 #define SI32_EPCA_0_CH3_RX_ENDPOINT &SI32_EPCA_0_CH3->CCAPV.U32 248 #define SI32_EPCA_0_CH4_RX_ENDPOINT &SI32_EPCA_0_CH4->CCAPV.U32 249 #define SI32_EPCA_0_CH5_RX_ENDPOINT &SI32_EPCA_0_CH5->CCAPV.U32 250 #define SI32_EPCA_0_TX_ENDPOINT &SI32_EPCA_0->DTARGET.U32 251 #define SI32_EPCA_0_CH0_TX_ENDPOINT &SI32_EPCA_0_CH0->CCAPVUPD.U32 252 #define SI32_EPCA_0_CH1_TX_ENDPOINT &SI32_EPCA_0_CH1->CCAPVUPD.U32 253 #define SI32_EPCA_0_CH2_TX_ENDPOINT &SI32_EPCA_0_CH2->CCAPVUPD.U32 254 #define SI32_EPCA_0_CH3_TX_ENDPOINT &SI32_EPCA_0_CH3->CCAPVUPD.U32 255 #define SI32_EPCA_0_CH4_TX_ENDPOINT &SI32_EPCA_0_CH4->CCAPVUPD.U32 256 #define SI32_EPCA_0_CH5_TX_ENDPOINT &SI32_EPCA_0_CH5->CCAPVUPD.U32 257 #define SI32_I2C_0_RX_ENDPOINT &SI32_I2C_0->DATA.U32 258 #define SI32_I2C_0_TX_ENDPOINT &SI32_I2C_0->DATA.U32 259 #define SI32_I2S_0_RX_ENDPOINT &SI32_I2S_0->RXFIFO.U32 260 #define SI32_I2S_0_TX_ENDPOINT &SI32_I2S_0->TXFIFO.U32 261 #define SI32_IDAC_0_TX_ENDPOINT &SI32_IDAC_0->DATA.U32 262 #define SI32_IDAC_1_TX_ENDPOINT &SI32_IDAC_1->DATA.U32 263 #define SI32_SPI_0_RX_ENDPOINT &SI32_SPI_0->DATA.U32 264 #define SI32_SPI_0_TX_ENDPOINT &SI32_SPI_0->DATA.U32 265 #define SI32_SPI_1_RX_ENDPOINT &SI32_SPI_1->DATA.U32 266 #define SI32_SPI_1_TX_ENDPOINT &SI32_SPI_1->DATA.U32 267 #define SI32_USART_0_RX_ENDPOINT &SI32_USART_0->DATA.U32 268 #define SI32_USART_0_TX_ENDPOINT &SI32_USART_0->DATA.U32 269 #define SI32_USART_1_RX_ENDPOINT &SI32_USART_1->DATA.U32 270 #define SI32_USART_1_TX_ENDPOINT &SI32_USART_1->DATA.U32 271 272 #ifdef __cplusplus 273 } 274 #endif 275 276 #endif // __SI32_DMAXBAR_A_Support_Guard__ 277 278 //-eof-------------------------------------------------------------------------- 279
