1 //----------------------------------------------------------------------------- 2 // Copyright 2012 (c) Silicon Laboratories Inc. 3 // 4 // SPDX-License-Identifier: Zlib 5 // 6 // This siHAL software is provided 'as-is', without any express or implied 7 // warranty. In no event will the authors be held liable for any damages 8 // arising from the use of this software. 9 // 10 // Permission is granted to anyone to use this software for any purpose, 11 // including commercial applications, and to alter it and redistribute it 12 // freely, subject to the following restrictions: 13 // 14 // 1. The origin of this software must not be misrepresented; you must not 15 // claim that you wrote the original software. If you use this software 16 // in a product, an acknowledgment in the product documentation would be 17 // appreciated but is not required. 18 // 2. Altered source versions must be plainly marked as such, and must not be 19 // misrepresented as being the original software. 20 // 3. This notice may not be removed or altered from any source distribution. 21 //----------------------------------------------------------------------------- 22 // 23 // Script: 0.61 24 // Version: 1 25 26 #ifndef __SI32_WDTIMER_A_REGISTERS_H__ 27 #define __SI32_WDTIMER_A_REGISTERS_H__ 28 29 #include <stdint.h> 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 struct SI32_WDTIMER_A_CONTROL_Struct 36 { 37 union 38 { 39 struct 40 { 41 // Early Warning Interrupt Enable 42 volatile uint32_t EWIEN: 1; 43 // Watchdog Timer Debug Mode 44 volatile uint32_t DBGMD: 1; 45 uint32_t reserved0: 30; 46 }; 47 volatile uint32_t U32; 48 }; 49 }; 50 51 #define SI32_WDTIMER_A_CONTROL_EWIEN_MASK 0x00000001 52 #define SI32_WDTIMER_A_CONTROL_EWIEN_SHIFT 0 53 // Disable the early warning interrupt (EWI). 54 #define SI32_WDTIMER_A_CONTROL_EWIEN_DISABLED_VALUE 0 55 #define SI32_WDTIMER_A_CONTROL_EWIEN_DISABLED_U32 \ 56 (SI32_WDTIMER_A_CONTROL_EWIEN_DISABLED_VALUE << SI32_WDTIMER_A_CONTROL_EWIEN_SHIFT) 57 // Enable the early warning interrupt (EWI). 58 #define SI32_WDTIMER_A_CONTROL_EWIEN_ENABLED_VALUE 1 59 #define SI32_WDTIMER_A_CONTROL_EWIEN_ENABLED_U32 \ 60 (SI32_WDTIMER_A_CONTROL_EWIEN_ENABLED_VALUE << SI32_WDTIMER_A_CONTROL_EWIEN_SHIFT) 61 62 #define SI32_WDTIMER_A_CONTROL_DBGMD_MASK 0x00000002 63 #define SI32_WDTIMER_A_CONTROL_DBGMD_SHIFT 1 64 // The WDTIMER module will continue to operate while the core is halted in debug 65 // mode. 66 #define SI32_WDTIMER_A_CONTROL_DBGMD_RUN_VALUE 0 67 #define SI32_WDTIMER_A_CONTROL_DBGMD_RUN_U32 \ 68 (SI32_WDTIMER_A_CONTROL_DBGMD_RUN_VALUE << SI32_WDTIMER_A_CONTROL_DBGMD_SHIFT) 69 // A debug breakpoint will cause the WDTIMER module to halt. 70 #define SI32_WDTIMER_A_CONTROL_DBGMD_HALT_VALUE 1 71 #define SI32_WDTIMER_A_CONTROL_DBGMD_HALT_U32 \ 72 (SI32_WDTIMER_A_CONTROL_DBGMD_HALT_VALUE << SI32_WDTIMER_A_CONTROL_DBGMD_SHIFT) 73 74 75 76 struct SI32_WDTIMER_A_STATUS_Struct 77 { 78 union 79 { 80 struct 81 { 82 // Key Status 83 volatile uint32_t KEYSTS: 1; 84 // Register Access Status 85 volatile uint32_t PRIVSTS: 1; 86 // Early Warning Interrupt Flag 87 volatile uint32_t EWI: 1; 88 // Reset Threshold Flag 89 volatile uint32_t RTHF: 1; 90 // Watchdog Timer Threshold Update Status 91 volatile uint32_t UPDSTS: 1; 92 uint32_t reserved0: 27; 93 }; 94 volatile uint32_t U32; 95 }; 96 }; 97 98 #define SI32_WDTIMER_A_STATUS_KEYSTS_MASK 0x00000001 99 #define SI32_WDTIMER_A_STATUS_KEYSTS_SHIFT 0 100 // No keys have been processed by the interface. 101 #define SI32_WDTIMER_A_STATUS_KEYSTS_IDLE_VALUE 0 102 #define SI32_WDTIMER_A_STATUS_KEYSTS_IDLE_U32 \ 103 (SI32_WDTIMER_A_STATUS_KEYSTS_IDLE_VALUE << SI32_WDTIMER_A_STATUS_KEYSTS_SHIFT) 104 // The attention key has been received and the module is awaiting a command. 105 #define SI32_WDTIMER_A_STATUS_KEYSTS_READY_VALUE 1 106 #define SI32_WDTIMER_A_STATUS_KEYSTS_READY_U32 \ 107 (SI32_WDTIMER_A_STATUS_KEYSTS_READY_VALUE << SI32_WDTIMER_A_STATUS_KEYSTS_SHIFT) 108 109 #define SI32_WDTIMER_A_STATUS_PRIVSTS_MASK 0x00000002 110 #define SI32_WDTIMER_A_STATUS_PRIVSTS_SHIFT 1 111 // The watchdog timer registers are currently read-only. 112 #define SI32_WDTIMER_A_STATUS_PRIVSTS_READ_ONLY_VALUE 0 113 #define SI32_WDTIMER_A_STATUS_PRIVSTS_READ_ONLY_U32 \ 114 (SI32_WDTIMER_A_STATUS_PRIVSTS_READ_ONLY_VALUE << SI32_WDTIMER_A_STATUS_PRIVSTS_SHIFT) 115 // A write transaction can be performed on the module registers. 116 #define SI32_WDTIMER_A_STATUS_PRIVSTS_READ_WRITE_VALUE 1 117 #define SI32_WDTIMER_A_STATUS_PRIVSTS_READ_WRITE_U32 \ 118 (SI32_WDTIMER_A_STATUS_PRIVSTS_READ_WRITE_VALUE << SI32_WDTIMER_A_STATUS_PRIVSTS_SHIFT) 119 120 #define SI32_WDTIMER_A_STATUS_EWI_MASK 0x00000004 121 #define SI32_WDTIMER_A_STATUS_EWI_SHIFT 2 122 // Read: An early warning match did not occur. Write: Clear the early warning 123 // interrupt. 124 #define SI32_WDTIMER_A_STATUS_EWI_NOT_SET_VALUE 0 125 #define SI32_WDTIMER_A_STATUS_EWI_NOT_SET_U32 \ 126 (SI32_WDTIMER_A_STATUS_EWI_NOT_SET_VALUE << SI32_WDTIMER_A_STATUS_EWI_SHIFT) 127 // Read: An early warning match occurred and the interrupt is pending. Write: Force 128 // a watchdog timer early warning interrupt to occur. 129 #define SI32_WDTIMER_A_STATUS_EWI_SET_VALUE 1 130 #define SI32_WDTIMER_A_STATUS_EWI_SET_U32 \ 131 (SI32_WDTIMER_A_STATUS_EWI_SET_VALUE << SI32_WDTIMER_A_STATUS_EWI_SHIFT) 132 133 #define SI32_WDTIMER_A_STATUS_RTHF_MASK 0x00000008 134 #define SI32_WDTIMER_A_STATUS_RTHF_SHIFT 3 135 // The counter is currently less than the reset threshold (RTH) value. 136 #define SI32_WDTIMER_A_STATUS_RTHF_LT_VALUE 0 137 #define SI32_WDTIMER_A_STATUS_RTHF_LT_U32 \ 138 (SI32_WDTIMER_A_STATUS_RTHF_LT_VALUE << SI32_WDTIMER_A_STATUS_RTHF_SHIFT) 139 // The counter is currently greater than or equal to the reset threshold (RTH) 140 // value. 141 #define SI32_WDTIMER_A_STATUS_RTHF_GTE_VALUE 1 142 #define SI32_WDTIMER_A_STATUS_RTHF_GTE_U32 \ 143 (SI32_WDTIMER_A_STATUS_RTHF_GTE_VALUE << SI32_WDTIMER_A_STATUS_RTHF_SHIFT) 144 145 #define SI32_WDTIMER_A_STATUS_UPDSTS_MASK 0x00000010 146 #define SI32_WDTIMER_A_STATUS_UPDSTS_SHIFT 4 147 // An update completed or is not pending. The EWTH and RTH fields can be written. 148 #define SI32_WDTIMER_A_STATUS_UPDSTS_IDLE_VALUE 0 149 #define SI32_WDTIMER_A_STATUS_UPDSTS_IDLE_U32 \ 150 (SI32_WDTIMER_A_STATUS_UPDSTS_IDLE_VALUE << SI32_WDTIMER_A_STATUS_UPDSTS_SHIFT) 151 // An update of the threshold register is occurring. The EWTH and RTH fields should 152 // not be modified until hardware clears UPDSTS to 0. 153 #define SI32_WDTIMER_A_STATUS_UPDSTS_UPDATING_VALUE 1 154 #define SI32_WDTIMER_A_STATUS_UPDSTS_UPDATING_U32 \ 155 (SI32_WDTIMER_A_STATUS_UPDSTS_UPDATING_VALUE << SI32_WDTIMER_A_STATUS_UPDSTS_SHIFT) 156 157 158 159 struct SI32_WDTIMER_A_THRESHOLD_Struct 160 { 161 union 162 { 163 struct 164 { 165 // Early Warning Threshold 166 volatile uint16_t EWTH; 167 // Reset Threshold 168 volatile uint16_t RTH; 169 }; 170 volatile uint32_t U32; 171 }; 172 }; 173 174 #define SI32_WDTIMER_A_THRESHOLD_EWTH_MASK 0x0000FFFF 175 #define SI32_WDTIMER_A_THRESHOLD_EWTH_SHIFT 0 176 177 #define SI32_WDTIMER_A_THRESHOLD_RTH_MASK 0xFFFF0000 178 #define SI32_WDTIMER_A_THRESHOLD_RTH_SHIFT 16 179 180 181 182 struct SI32_WDTIMER_A_WDTKEY_Struct 183 { 184 union 185 { 186 struct 187 { 188 // Watchdog Timer Key 189 volatile uint8_t KEY; 190 uint32_t reserved0: 24; 191 }; 192 volatile uint32_t U32; 193 }; 194 }; 195 196 #define SI32_WDTIMER_A_WDTKEY_KEY_MASK 0x000000FF 197 #define SI32_WDTIMER_A_WDTKEY_KEY_SHIFT 0 198 // Attention key to start the command sequence. 199 #define SI32_WDTIMER_A_WDTKEY_KEY_ATTN_VALUE 165 200 #define SI32_WDTIMER_A_WDTKEY_KEY_ATTN_U32 \ 201 (SI32_WDTIMER_A_WDTKEY_KEY_ATTN_VALUE << SI32_WDTIMER_A_WDTKEY_KEY_SHIFT) 202 // Reset the watchdog timer. 203 #define SI32_WDTIMER_A_WDTKEY_KEY_RESET_VALUE 204 204 #define SI32_WDTIMER_A_WDTKEY_KEY_RESET_U32 \ 205 (SI32_WDTIMER_A_WDTKEY_KEY_RESET_VALUE << SI32_WDTIMER_A_WDTKEY_KEY_SHIFT) 206 // Disable the watchdog timer. 207 #define SI32_WDTIMER_A_WDTKEY_KEY_DISABLE_VALUE 221 208 #define SI32_WDTIMER_A_WDTKEY_KEY_DISABLE_U32 \ 209 (SI32_WDTIMER_A_WDTKEY_KEY_DISABLE_VALUE << SI32_WDTIMER_A_WDTKEY_KEY_SHIFT) 210 // Start the watchdog timer. 211 #define SI32_WDTIMER_A_WDTKEY_KEY_START_VALUE 238 212 #define SI32_WDTIMER_A_WDTKEY_KEY_START_U32 \ 213 (SI32_WDTIMER_A_WDTKEY_KEY_START_VALUE << SI32_WDTIMER_A_WDTKEY_KEY_SHIFT) 214 // Allow one write access to the module registers. 215 #define SI32_WDTIMER_A_WDTKEY_KEY_WRITE_VALUE 241 216 #define SI32_WDTIMER_A_WDTKEY_KEY_WRITE_U32 \ 217 (SI32_WDTIMER_A_WDTKEY_KEY_WRITE_VALUE << SI32_WDTIMER_A_WDTKEY_KEY_SHIFT) 218 // Lock the module from any other writes until the next system reset. 219 #define SI32_WDTIMER_A_WDTKEY_KEY_LOCK_VALUE 255 220 #define SI32_WDTIMER_A_WDTKEY_KEY_LOCK_U32 \ 221 (SI32_WDTIMER_A_WDTKEY_KEY_LOCK_VALUE << SI32_WDTIMER_A_WDTKEY_KEY_SHIFT) 222 223 224 225 typedef struct SI32_WDTIMER_A_Struct 226 { 227 struct SI32_WDTIMER_A_CONTROL_Struct CONTROL ; // Base Address + 0x0 228 volatile uint32_t CONTROL_SET; 229 volatile uint32_t CONTROL_CLR; 230 uint32_t reserved0; 231 struct SI32_WDTIMER_A_STATUS_Struct STATUS ; // Base Address + 0x10 232 volatile uint32_t STATUS_SET; 233 volatile uint32_t STATUS_CLR; 234 uint32_t reserved1; 235 struct SI32_WDTIMER_A_THRESHOLD_Struct THRESHOLD ; // Base Address + 0x20 236 uint32_t reserved2; 237 uint32_t reserved3; 238 uint32_t reserved4; 239 struct SI32_WDTIMER_A_WDTKEY_Struct WDTKEY ; // Base Address + 0x30 240 uint32_t reserved5; 241 uint32_t reserved6; 242 uint32_t reserved7; 243 uint32_t reserved8[4]; 244 uint32_t reserved9[4]; 245 } SI32_WDTIMER_A_Type; 246 247 #ifdef __cplusplus 248 } 249 #endif 250 251 #endif // __SI32_WDTIMER_A_REGISTERS_H__ 252 253 //-eof-------------------------------------------------------------------------- 254 255
