1 //------------------------------------------------------------------------------ 2 // Copyright 2012 (c) Silicon Laboratories Inc. 3 // 4 // SPDX-License-Identifier: Zlib 5 // 6 // This siHAL software is provided 'as-is', without any express or implied 7 // warranty. In no event will the authors be held liable for any damages 8 // arising from the use of this software. 9 // 10 // Permission is granted to anyone to use this software for any purpose, 11 // including commercial applications, and to alter it and redistribute it 12 // freely, subject to the following restrictions: 13 // 14 // 1. The origin of this software must not be misrepresented; you must not 15 // claim that you wrote the original software. If you use this software 16 // in a product, an acknowledgment in the product documentation would be 17 // appreciated but is not required. 18 // 2. Altered source versions must be plainly marked as such, and must not be 19 // misrepresented as being the original software. 20 // 3. This notice may not be removed or altered from any source distribution. 21 //------------------------------------------------------------------------------ 22 // 23 // Script: 0.57 24 // Version: 1 25 26 #ifndef __SI32_VMON_A_REGISTERS_H__ 27 #define __SI32_VMON_A_REGISTERS_H__ 28 29 #include <stdint.h> 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 struct SI32_VMON_A_CONTROL_Struct 36 { 37 union 38 { 39 struct 40 { 41 // VREGIN Supply Monitor Enable 42 volatile uint32_t VREGINSEN: 1; 43 // VREGIN Low Interrupt Flag 44 volatile uint32_t VREGINLI: 1; 45 // VDD Reset Threshold Status Flag 46 volatile uint32_t VDDRSTF: 1; 47 // VDD Low Interrupt Flag 48 volatile uint32_t VDDLI: 1; 49 // VDD High Threshold Enable 50 volatile uint32_t VDDHITHEN: 1; 51 uint32_t reserved0: 1; 52 // VDD Low Interrupt Enable 53 volatile uint32_t VDDLIEN: 1; 54 // VREGIN Low Interrupt Enable 55 volatile uint32_t VREGINLIEN: 1; 56 uint32_t reserved1: 23; 57 // VDD Supply Monitor Enable 58 volatile uint32_t VMONEN: 1; 59 }; 60 volatile uint32_t U32; 61 }; 62 }; 63 64 #define SI32_VMON_A_CONTROL_VREGINSEN_MASK 0x00000001 65 #define SI32_VMON_A_CONTROL_VREGINSEN_SHIFT 0 66 // Disable the VREGIN supply monitor. 67 #define SI32_VMON_A_CONTROL_VREGINSEN_DISABLED_VALUE 0 68 #define SI32_VMON_A_CONTROL_VREGINSEN_DISABLED_U32 \ 69 (SI32_VMON_A_CONTROL_VREGINSEN_DISABLED_VALUE << SI32_VMON_A_CONTROL_VREGINSEN_SHIFT) 70 // Enable the VREGIN supply monitor. 71 #define SI32_VMON_A_CONTROL_VREGINSEN_ENABLED_VALUE 1 72 #define SI32_VMON_A_CONTROL_VREGINSEN_ENABLED_U32 \ 73 (SI32_VMON_A_CONTROL_VREGINSEN_ENABLED_VALUE << SI32_VMON_A_CONTROL_VREGINSEN_SHIFT) 74 75 #define SI32_VMON_A_CONTROL_VREGINLI_MASK 0x00000002 76 #define SI32_VMON_A_CONTROL_VREGINLI_SHIFT 1 77 // VREGIN is not above the interrupt threshold. 78 #define SI32_VMON_A_CONTROL_VREGINLI_VREGIN_IS_LOW_VALUE 0 79 #define SI32_VMON_A_CONTROL_VREGINLI_VREGIN_IS_LOW_U32 \ 80 (SI32_VMON_A_CONTROL_VREGINLI_VREGIN_IS_LOW_VALUE << SI32_VMON_A_CONTROL_VREGINLI_SHIFT) 81 // VREGIN is above the interrupt threshold. 82 #define SI32_VMON_A_CONTROL_VREGINLI_VREGIN_IS_OK_VALUE 1 83 #define SI32_VMON_A_CONTROL_VREGINLI_VREGIN_IS_OK_U32 \ 84 (SI32_VMON_A_CONTROL_VREGINLI_VREGIN_IS_OK_VALUE << SI32_VMON_A_CONTROL_VREGINLI_SHIFT) 85 86 #define SI32_VMON_A_CONTROL_VDDRSTF_MASK 0x00000004 87 #define SI32_VMON_A_CONTROL_VDDRSTF_SHIFT 2 88 // The VDD voltage is below the VDD reset threshold. 89 #define SI32_VMON_A_CONTROL_VDDRSTF_VDD_IS_BELOW_RESET_VALUE 0 90 #define SI32_VMON_A_CONTROL_VDDRSTF_VDD_IS_BELOW_RESET_U32 \ 91 (SI32_VMON_A_CONTROL_VDDRSTF_VDD_IS_BELOW_RESET_VALUE << SI32_VMON_A_CONTROL_VDDRSTF_SHIFT) 92 // The VDD voltage is above the VDD reset threshold. 93 #define SI32_VMON_A_CONTROL_VDDRSTF_VDD_IS_ABOVE_RESET_VALUE 1 94 #define SI32_VMON_A_CONTROL_VDDRSTF_VDD_IS_ABOVE_RESET_U32 \ 95 (SI32_VMON_A_CONTROL_VDDRSTF_VDD_IS_ABOVE_RESET_VALUE << SI32_VMON_A_CONTROL_VDDRSTF_SHIFT) 96 97 #define SI32_VMON_A_CONTROL_VDDLI_MASK 0x00000008 98 #define SI32_VMON_A_CONTROL_VDDLI_SHIFT 3 99 // The VDD voltage is below the early warning threshold. 100 #define SI32_VMON_A_CONTROL_VDDLI_VDD_IS_LOW_VALUE 0 101 #define SI32_VMON_A_CONTROL_VDDLI_VDD_IS_LOW_U32 \ 102 (SI32_VMON_A_CONTROL_VDDLI_VDD_IS_LOW_VALUE << SI32_VMON_A_CONTROL_VDDLI_SHIFT) 103 // The VDD voltage is above the early warning threshold. 104 #define SI32_VMON_A_CONTROL_VDDLI_VDD_IS_OK_VALUE 1 105 #define SI32_VMON_A_CONTROL_VDDLI_VDD_IS_OK_U32 \ 106 (SI32_VMON_A_CONTROL_VDDLI_VDD_IS_OK_VALUE << SI32_VMON_A_CONTROL_VDDLI_SHIFT) 107 108 #define SI32_VMON_A_CONTROL_VDDHITHEN_MASK 0x00000010 109 #define SI32_VMON_A_CONTROL_VDDHITHEN_SHIFT 4 110 // Use the standard VDD thresholds. 111 #define SI32_VMON_A_CONTROL_VDDHITHEN_DISABLED_VALUE 0 112 #define SI32_VMON_A_CONTROL_VDDHITHEN_DISABLED_U32 \ 113 (SI32_VMON_A_CONTROL_VDDHITHEN_DISABLED_VALUE << SI32_VMON_A_CONTROL_VDDHITHEN_SHIFT) 114 // Use the high VDD thresholds. 115 #define SI32_VMON_A_CONTROL_VDDHITHEN_ENABLED_VALUE 1 116 #define SI32_VMON_A_CONTROL_VDDHITHEN_ENABLED_U32 \ 117 (SI32_VMON_A_CONTROL_VDDHITHEN_ENABLED_VALUE << SI32_VMON_A_CONTROL_VDDHITHEN_SHIFT) 118 119 #define SI32_VMON_A_CONTROL_VDDLIEN_MASK 0x00000040 120 #define SI32_VMON_A_CONTROL_VDDLIEN_SHIFT 6 121 // Disable the VDD low interrupt. 122 #define SI32_VMON_A_CONTROL_VDDLIEN_DISABLED_VALUE 0 123 #define SI32_VMON_A_CONTROL_VDDLIEN_DISABLED_U32 \ 124 (SI32_VMON_A_CONTROL_VDDLIEN_DISABLED_VALUE << SI32_VMON_A_CONTROL_VDDLIEN_SHIFT) 125 // Enable the VDD low interrupt. 126 #define SI32_VMON_A_CONTROL_VDDLIEN_ENABLED_VALUE 1 127 #define SI32_VMON_A_CONTROL_VDDLIEN_ENABLED_U32 \ 128 (SI32_VMON_A_CONTROL_VDDLIEN_ENABLED_VALUE << SI32_VMON_A_CONTROL_VDDLIEN_SHIFT) 129 130 #define SI32_VMON_A_CONTROL_VREGINLIEN_MASK 0x00000080 131 #define SI32_VMON_A_CONTROL_VREGINLIEN_SHIFT 7 132 // Disable the VREGIN low interrupt. 133 #define SI32_VMON_A_CONTROL_VREGINLIEN_DISABLED_VALUE 0 134 #define SI32_VMON_A_CONTROL_VREGINLIEN_DISABLED_U32 \ 135 (SI32_VMON_A_CONTROL_VREGINLIEN_DISABLED_VALUE << SI32_VMON_A_CONTROL_VREGINLIEN_SHIFT) 136 // Enable the VREGIN low interrupt. 137 #define SI32_VMON_A_CONTROL_VREGINLIEN_ENABLED_VALUE 1 138 #define SI32_VMON_A_CONTROL_VREGINLIEN_ENABLED_U32 \ 139 (SI32_VMON_A_CONTROL_VREGINLIEN_ENABLED_VALUE << SI32_VMON_A_CONTROL_VREGINLIEN_SHIFT) 140 141 #define SI32_VMON_A_CONTROL_VMONEN_MASK 0x80000000 142 #define SI32_VMON_A_CONTROL_VMONEN_SHIFT 31 143 // Disable the VDD supply monitor. 144 #define SI32_VMON_A_CONTROL_VMONEN_DISABLED_VALUE 0U 145 #define SI32_VMON_A_CONTROL_VMONEN_DISABLED_U32 \ 146 (SI32_VMON_A_CONTROL_VMONEN_DISABLED_VALUE << SI32_VMON_A_CONTROL_VMONEN_SHIFT) 147 // Enable the VDD supply monitor. 148 #define SI32_VMON_A_CONTROL_VMONEN_ENABLED_VALUE 1U 149 #define SI32_VMON_A_CONTROL_VMONEN_ENABLED_U32 \ 150 (SI32_VMON_A_CONTROL_VMONEN_ENABLED_VALUE << SI32_VMON_A_CONTROL_VMONEN_SHIFT) 151 152 153 154 typedef struct SI32_VMON_A_Struct 155 { 156 struct SI32_VMON_A_CONTROL_Struct CONTROL ; // Base Address + 0x0 157 volatile uint32_t CONTROL_SET; 158 volatile uint32_t CONTROL_CLR; 159 uint32_t reserved0; 160 uint32_t reserved1[4]; 161 } SI32_VMON_A_Type; 162 163 #ifdef __cplusplus 164 } 165 #endif 166 167 #endif // __SI32_VMON_A_REGISTERS_H__ 168 169 //-eof-------------------------------------------------------------------------- 170 171
