1 //----------------------------------------------------------------------------- 2 // Copyright 2012 (c) Silicon Laboratories Inc. 3 // 4 // SPDX-License-Identifier: Zlib 5 // 6 // This siHAL software is provided 'as-is', without any express or implied 7 // warranty. In no event will the authors be held liable for any damages 8 // arising from the use of this software. 9 // 10 // Permission is granted to anyone to use this software for any purpose, 11 // including commercial applications, and to alter it and redistribute it 12 // freely, subject to the following restrictions: 13 // 14 // 1. The origin of this software must not be misrepresented; you must not 15 // claim that you wrote the original software. If you use this software 16 // in a product, an acknowledgment in the product documentation would be 17 // appreciated but is not required. 18 // 2. Altered source versions must be plainly marked as such, and must not be 19 // misrepresented as being the original software. 20 // 3. This notice may not be removed or altered from any source distribution. 21 //----------------------------------------------------------------------------- 22 // 23 // Script: 0.61 24 // Version: 1 25 26 #ifndef __SI32_SPI_A_REGISTERS_H__ 27 #define __SI32_SPI_A_REGISTERS_H__ 28 29 #include <stdint.h> 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 struct SI32_SPI_A_DATA_Struct 36 { 37 union 38 { 39 // This is a FIFO register 40 volatile uint8_t U8; 41 volatile uint16_t U16; 42 volatile uint32_t U32; 43 }; 44 }; 45 46 #define SI32_SPI_A_DATA_DATA_MASK 0xFFFFFFFF 47 #define SI32_SPI_A_DATA_DATA_SHIFT 0 48 49 50 51 struct SI32_SPI_A_CONTROL_Struct 52 { 53 union 54 { 55 struct 56 { 57 // Receive FIFO Read Request Interrupt Flag 58 volatile uint32_t RFRQI: 1; 59 // Receive FIFO Overrun Interrupt Flag 60 volatile uint32_t RFORI: 1; 61 // Transmit FIFO Write Request Interrupt Flag 62 volatile uint32_t TFRQI: 1; 63 // Transmit FIFO Overrun Interrupt Flag 64 volatile uint32_t TFORI: 1; 65 // Slave Selected Interrupt Flag 66 volatile uint32_t SLVSELI: 1; 67 // Mode Fault Interrupt Flag 68 volatile uint32_t MDFI: 1; 69 // Underrun Interrupt Flag 70 volatile uint32_t URI: 1; 71 // Shift Register Empty Interrupt Flag 72 volatile uint32_t SREI: 1; 73 // Illegal Receive FIFO Access Interrupt Flag 74 volatile uint32_t RFILI: 1; 75 // Illegal Transmit FIFO Access Interrupt Flag 76 volatile uint32_t TFILI: 1; 77 uint32_t reserved0: 4; 78 // NSS Instantaneous Pin Status 79 volatile uint32_t NSSSTS: 1; 80 // SPI Busy 81 volatile uint32_t BUSYF: 1; 82 // Receive FIFO Counter 83 volatile uint32_t RFCNT: 4; 84 // Transmit FIFO Counter 85 volatile uint32_t TFCNT: 4; 86 // SPI Debug Mode 87 volatile uint32_t DBGMD: 1; 88 uint32_t reserved1: 7; 89 }; 90 volatile uint32_t U32; 91 }; 92 }; 93 94 #define SI32_SPI_A_CONTROL_RFRQI_MASK 0x00000001 95 #define SI32_SPI_A_CONTROL_RFRQI_SHIFT 0 96 // The RX FIFO has fewer bytes than the level defined by RFTH. 97 #define SI32_SPI_A_CONTROL_RFRQI_NOT_SET_VALUE 0 98 #define SI32_SPI_A_CONTROL_RFRQI_NOT_SET_U32 \ 99 (SI32_SPI_A_CONTROL_RFRQI_NOT_SET_VALUE << SI32_SPI_A_CONTROL_RFRQI_SHIFT) 100 // The RX FIFO has equal or more bytes than the level defined by RFTH. 101 #define SI32_SPI_A_CONTROL_RFRQI_SET_VALUE 1 102 #define SI32_SPI_A_CONTROL_RFRQI_SET_U32 \ 103 (SI32_SPI_A_CONTROL_RFRQI_SET_VALUE << SI32_SPI_A_CONTROL_RFRQI_SHIFT) 104 105 #define SI32_SPI_A_CONTROL_RFORI_MASK 0x00000002 106 #define SI32_SPI_A_CONTROL_RFORI_SHIFT 1 107 // Read: A receive FIFO overrun has not occurred. Write: Clear the flag. 108 #define SI32_SPI_A_CONTROL_RFORI_NOT_SET_VALUE 0 109 #define SI32_SPI_A_CONTROL_RFORI_NOT_SET_U32 \ 110 (SI32_SPI_A_CONTROL_RFORI_NOT_SET_VALUE << SI32_SPI_A_CONTROL_RFORI_SHIFT) 111 // Read: A receive FIFO overrun occurred. Write: Force a receive overrun 112 // interrupt. 113 #define SI32_SPI_A_CONTROL_RFORI_SET_VALUE 1 114 #define SI32_SPI_A_CONTROL_RFORI_SET_U32 \ 115 (SI32_SPI_A_CONTROL_RFORI_SET_VALUE << SI32_SPI_A_CONTROL_RFORI_SHIFT) 116 117 #define SI32_SPI_A_CONTROL_TFRQI_MASK 0x00000004 118 #define SI32_SPI_A_CONTROL_TFRQI_SHIFT 2 119 // The TX FIFO has fewer bytes than the level defined by TFTH. 120 #define SI32_SPI_A_CONTROL_TFRQI_NOT_SET_VALUE 0 121 #define SI32_SPI_A_CONTROL_TFRQI_NOT_SET_U32 \ 122 (SI32_SPI_A_CONTROL_TFRQI_NOT_SET_VALUE << SI32_SPI_A_CONTROL_TFRQI_SHIFT) 123 // The TX FIFO has equal or more bytes than the level defined by TFTH. 124 #define SI32_SPI_A_CONTROL_TFRQI_SET_VALUE 1 125 #define SI32_SPI_A_CONTROL_TFRQI_SET_U32 \ 126 (SI32_SPI_A_CONTROL_TFRQI_SET_VALUE << SI32_SPI_A_CONTROL_TFRQI_SHIFT) 127 128 #define SI32_SPI_A_CONTROL_TFORI_MASK 0x00000008 129 #define SI32_SPI_A_CONTROL_TFORI_SHIFT 3 130 // Read: A transmit FIFO overrun has not occurred. Write: Clear the flag. 131 #define SI32_SPI_A_CONTROL_TFORI_NOT_SET_VALUE 0 132 #define SI32_SPI_A_CONTROL_TFORI_NOT_SET_U32 \ 133 (SI32_SPI_A_CONTROL_TFORI_NOT_SET_VALUE << SI32_SPI_A_CONTROL_TFORI_SHIFT) 134 // Read: A transmit FIFO overrun occurred. Write: Force a transmit overrun 135 // interrupt. 136 #define SI32_SPI_A_CONTROL_TFORI_SET_VALUE 1 137 #define SI32_SPI_A_CONTROL_TFORI_SET_U32 \ 138 (SI32_SPI_A_CONTROL_TFORI_SET_VALUE << SI32_SPI_A_CONTROL_TFORI_SHIFT) 139 140 #define SI32_SPI_A_CONTROL_SLVSELI_MASK 0x00000010 141 #define SI32_SPI_A_CONTROL_SLVSELI_SHIFT 4 142 // The slave select signal (NSS) is not active. 143 #define SI32_SPI_A_CONTROL_SLVSELI_NOT_SET_VALUE 0 144 #define SI32_SPI_A_CONTROL_SLVSELI_NOT_SET_U32 \ 145 (SI32_SPI_A_CONTROL_SLVSELI_NOT_SET_VALUE << SI32_SPI_A_CONTROL_SLVSELI_SHIFT) 146 // The slave select signal (NSS) is active. 147 #define SI32_SPI_A_CONTROL_SLVSELI_SET_VALUE 1 148 #define SI32_SPI_A_CONTROL_SLVSELI_SET_U32 \ 149 (SI32_SPI_A_CONTROL_SLVSELI_SET_VALUE << SI32_SPI_A_CONTROL_SLVSELI_SHIFT) 150 151 #define SI32_SPI_A_CONTROL_MDFI_MASK 0x00000020 152 #define SI32_SPI_A_CONTROL_MDFI_SHIFT 5 153 // Read: A master mode collision is not detected. Write: Clear the flag. 154 #define SI32_SPI_A_CONTROL_MDFI_NOT_SET_VALUE 0 155 #define SI32_SPI_A_CONTROL_MDFI_NOT_SET_U32 \ 156 (SI32_SPI_A_CONTROL_MDFI_NOT_SET_VALUE << SI32_SPI_A_CONTROL_MDFI_SHIFT) 157 // Read: A master mode collision occurred. Write: Force a mode fault interrupt. 158 #define SI32_SPI_A_CONTROL_MDFI_SET_VALUE 1 159 #define SI32_SPI_A_CONTROL_MDFI_SET_U32 \ 160 (SI32_SPI_A_CONTROL_MDFI_SET_VALUE << SI32_SPI_A_CONTROL_MDFI_SHIFT) 161 162 #define SI32_SPI_A_CONTROL_URI_MASK 0x00000040 163 #define SI32_SPI_A_CONTROL_URI_SHIFT 6 164 // Read: A data transfer is still in progress. Write: Clear the flag. 165 #define SI32_SPI_A_CONTROL_URI_NOT_SET_VALUE 0 166 #define SI32_SPI_A_CONTROL_URI_NOT_SET_U32 \ 167 (SI32_SPI_A_CONTROL_URI_NOT_SET_VALUE << SI32_SPI_A_CONTROL_URI_SHIFT) 168 // Read: The transmit FIFO and shift register are empty and the data transfer has 169 // ended. Write: Force an underrun interrupt. 170 #define SI32_SPI_A_CONTROL_URI_SET_VALUE 1 171 #define SI32_SPI_A_CONTROL_URI_SET_U32 \ 172 (SI32_SPI_A_CONTROL_URI_SET_VALUE << SI32_SPI_A_CONTROL_URI_SHIFT) 173 174 #define SI32_SPI_A_CONTROL_SREI_MASK 0x00000080 175 #define SI32_SPI_A_CONTROL_SREI_SHIFT 7 176 // There is data still present in the transmit FIFO. 177 #define SI32_SPI_A_CONTROL_SREI_NOT_SET_VALUE 0 178 #define SI32_SPI_A_CONTROL_SREI_NOT_SET_U32 \ 179 (SI32_SPI_A_CONTROL_SREI_NOT_SET_VALUE << SI32_SPI_A_CONTROL_SREI_SHIFT) 180 // All data has been transferred out of the shift register and there is no data 181 // waiting in the transmit FIFO. 182 #define SI32_SPI_A_CONTROL_SREI_SET_VALUE 1 183 #define SI32_SPI_A_CONTROL_SREI_SET_U32 \ 184 (SI32_SPI_A_CONTROL_SREI_SET_VALUE << SI32_SPI_A_CONTROL_SREI_SHIFT) 185 186 #define SI32_SPI_A_CONTROL_RFILI_MASK 0x00000100 187 #define SI32_SPI_A_CONTROL_RFILI_SHIFT 8 188 // Read: An illegal write or read of the receive FIFO has not occurred. Write: 189 // Clear the flag. 190 #define SI32_SPI_A_CONTROL_RFILI_NOT_SET_VALUE 0 191 #define SI32_SPI_A_CONTROL_RFILI_NOT_SET_U32 \ 192 (SI32_SPI_A_CONTROL_RFILI_NOT_SET_VALUE << SI32_SPI_A_CONTROL_RFILI_SHIFT) 193 // Read: An illegal write or read of the receive FIFO occurred. Write: Force an 194 // illegal receive access interrupt. 195 #define SI32_SPI_A_CONTROL_RFILI_SET_VALUE 1 196 #define SI32_SPI_A_CONTROL_RFILI_SET_U32 \ 197 (SI32_SPI_A_CONTROL_RFILI_SET_VALUE << SI32_SPI_A_CONTROL_RFILI_SHIFT) 198 199 #define SI32_SPI_A_CONTROL_TFILI_MASK 0x00000200 200 #define SI32_SPI_A_CONTROL_TFILI_SHIFT 9 201 // Read: An illegal write or read of the transmit FIFO has not occurred. Write: 202 // Clear the flag. 203 #define SI32_SPI_A_CONTROL_TFILI_NOT_SET_VALUE 0 204 #define SI32_SPI_A_CONTROL_TFILI_NOT_SET_U32 \ 205 (SI32_SPI_A_CONTROL_TFILI_NOT_SET_VALUE << SI32_SPI_A_CONTROL_TFILI_SHIFT) 206 // Read: An illegal write or read of the transmit FIFO occurred. Write: Force an 207 // illegal transmit access interrupt. 208 #define SI32_SPI_A_CONTROL_TFILI_SET_VALUE 1 209 #define SI32_SPI_A_CONTROL_TFILI_SET_U32 \ 210 (SI32_SPI_A_CONTROL_TFILI_SET_VALUE << SI32_SPI_A_CONTROL_TFILI_SHIFT) 211 212 #define SI32_SPI_A_CONTROL_NSSSTS_MASK 0x00004000 213 #define SI32_SPI_A_CONTROL_NSSSTS_SHIFT 14 214 // NSS is currently a logic low. 215 #define SI32_SPI_A_CONTROL_NSSSTS_LOW_VALUE 0 216 #define SI32_SPI_A_CONTROL_NSSSTS_LOW_U32 \ 217 (SI32_SPI_A_CONTROL_NSSSTS_LOW_VALUE << SI32_SPI_A_CONTROL_NSSSTS_SHIFT) 218 // NSS is currently a logic high. 219 #define SI32_SPI_A_CONTROL_NSSSTS_HIGH_VALUE 1 220 #define SI32_SPI_A_CONTROL_NSSSTS_HIGH_U32 \ 221 (SI32_SPI_A_CONTROL_NSSSTS_HIGH_VALUE << SI32_SPI_A_CONTROL_NSSSTS_SHIFT) 222 223 #define SI32_SPI_A_CONTROL_BUSYF_MASK 0x00008000 224 #define SI32_SPI_A_CONTROL_BUSYF_SHIFT 15 225 // The SPI is not busy and a transfer is not in progress. 226 #define SI32_SPI_A_CONTROL_BUSYF_NOT_SET_VALUE 0 227 #define SI32_SPI_A_CONTROL_BUSYF_NOT_SET_U32 \ 228 (SI32_SPI_A_CONTROL_BUSYF_NOT_SET_VALUE << SI32_SPI_A_CONTROL_BUSYF_SHIFT) 229 // The SPI is currently busy and a transfer is in progress. 230 #define SI32_SPI_A_CONTROL_BUSYF_SET_VALUE 1 231 #define SI32_SPI_A_CONTROL_BUSYF_SET_U32 \ 232 (SI32_SPI_A_CONTROL_BUSYF_SET_VALUE << SI32_SPI_A_CONTROL_BUSYF_SHIFT) 233 234 #define SI32_SPI_A_CONTROL_RFCNT_MASK 0x000F0000 235 #define SI32_SPI_A_CONTROL_RFCNT_SHIFT 16 236 237 #define SI32_SPI_A_CONTROL_TFCNT_MASK 0x00F00000 238 #define SI32_SPI_A_CONTROL_TFCNT_SHIFT 20 239 240 #define SI32_SPI_A_CONTROL_DBGMD_MASK 0x01000000 241 #define SI32_SPI_A_CONTROL_DBGMD_SHIFT 24 242 // The SPI module will continue to operate while the core is halted in debug mode. 243 #define SI32_SPI_A_CONTROL_DBGMD_RUN_VALUE 0 244 #define SI32_SPI_A_CONTROL_DBGMD_RUN_U32 \ 245 (SI32_SPI_A_CONTROL_DBGMD_RUN_VALUE << SI32_SPI_A_CONTROL_DBGMD_SHIFT) 246 // A debug breakpoint will cause the SPI module to halt. 247 #define SI32_SPI_A_CONTROL_DBGMD_HALT_VALUE 1 248 #define SI32_SPI_A_CONTROL_DBGMD_HALT_U32 \ 249 (SI32_SPI_A_CONTROL_DBGMD_HALT_VALUE << SI32_SPI_A_CONTROL_DBGMD_SHIFT) 250 251 252 253 struct SI32_SPI_A_CONFIG_Struct 254 { 255 union 256 { 257 struct 258 { 259 // Receive FIFO Read Request Interrupt Enable 260 volatile uint32_t RFRQIEN: 1; 261 // Receive FIFO Overrun Interrupt Enable 262 volatile uint32_t RFORIEN: 1; 263 // Transmit FIFO Write Request Interrupt Enable 264 volatile uint32_t TFRQIEN: 1; 265 // Transmit FIFO Overrun Interrupt Enable 266 volatile uint32_t TFORIEN: 1; 267 // Slave Selected Interrupt Enable 268 volatile uint32_t SLVSELIEN: 1; 269 // Mode Fault Interrupt Enable 270 volatile uint32_t MDFIEN: 1; 271 // Underrun Interrupt Enable 272 volatile uint32_t URIEN: 1; 273 // Shift Register Empty Interrupt Enable 274 volatile uint32_t SREIEN: 1; 275 // SPI Enable 276 volatile uint32_t SPIEN: 1; 277 // Master Mode Enable 278 volatile uint32_t MSTEN: 1; 279 // SPI Clock Polarity 280 volatile uint32_t CLKPOL: 1; 281 // SPI Clock Phase 282 volatile uint32_t CLKPHA: 1; 283 // Slave Select Polarity Select 284 volatile uint32_t NSSPOL: 1; 285 // Data Direction Select 286 volatile uint32_t DDIRSEL: 1; 287 // Slave Select Mode 288 volatile uint32_t NSSMD: 2; 289 // Receive FIFO Threshold 290 volatile uint32_t RFTH: 2; 291 // Transmit FIFO Threshold 292 volatile uint32_t TFTH: 2; 293 // Data Size 294 volatile uint32_t DSIZE: 4; 295 // DMA Enable 296 volatile uint32_t DMAEN: 1; 297 uint32_t reserved0: 4; 298 // Receive FIFO Flush 299 volatile uint32_t RFIFOFL: 1; 300 // Transmit FIFO Flush 301 volatile uint32_t TFIFOFL: 1; 302 // Module Soft Reset 303 volatile uint32_t RESET: 1; 304 }; 305 volatile uint32_t U32; 306 }; 307 }; 308 309 #define SI32_SPI_A_CONFIG_RFRQIEN_MASK 0x00000001 310 #define SI32_SPI_A_CONFIG_RFRQIEN_SHIFT 0 311 // Disable the receive FIFO request interrupt. 312 #define SI32_SPI_A_CONFIG_RFRQIEN_DISABLED_VALUE 0 313 #define SI32_SPI_A_CONFIG_RFRQIEN_DISABLED_U32 \ 314 (SI32_SPI_A_CONFIG_RFRQIEN_DISABLED_VALUE << SI32_SPI_A_CONFIG_RFRQIEN_SHIFT) 315 // Enable the receive FIFO request interrupt. 316 #define SI32_SPI_A_CONFIG_RFRQIEN_ENABLED_VALUE 1 317 #define SI32_SPI_A_CONFIG_RFRQIEN_ENABLED_U32 \ 318 (SI32_SPI_A_CONFIG_RFRQIEN_ENABLED_VALUE << SI32_SPI_A_CONFIG_RFRQIEN_SHIFT) 319 320 #define SI32_SPI_A_CONFIG_RFORIEN_MASK 0x00000002 321 #define SI32_SPI_A_CONFIG_RFORIEN_SHIFT 1 322 // Disable the receive FIFO overrun interrupt. 323 #define SI32_SPI_A_CONFIG_RFORIEN_DISABLED_VALUE 0 324 #define SI32_SPI_A_CONFIG_RFORIEN_DISABLED_U32 \ 325 (SI32_SPI_A_CONFIG_RFORIEN_DISABLED_VALUE << SI32_SPI_A_CONFIG_RFORIEN_SHIFT) 326 // Enable the receive FIFO overrun interrupt. 327 #define SI32_SPI_A_CONFIG_RFORIEN_ENABLED_VALUE 1 328 #define SI32_SPI_A_CONFIG_RFORIEN_ENABLED_U32 \ 329 (SI32_SPI_A_CONFIG_RFORIEN_ENABLED_VALUE << SI32_SPI_A_CONFIG_RFORIEN_SHIFT) 330 331 #define SI32_SPI_A_CONFIG_TFRQIEN_MASK 0x00000004 332 #define SI32_SPI_A_CONFIG_TFRQIEN_SHIFT 2 333 // Disable the transmit FIFO data request interrupt. 334 #define SI32_SPI_A_CONFIG_TFRQIEN_DISABLED_VALUE 0 335 #define SI32_SPI_A_CONFIG_TFRQIEN_DISABLED_U32 \ 336 (SI32_SPI_A_CONFIG_TFRQIEN_DISABLED_VALUE << SI32_SPI_A_CONFIG_TFRQIEN_SHIFT) 337 // Enable the transmit FIFO data request interrupt. 338 #define SI32_SPI_A_CONFIG_TFRQIEN_ENABLED_VALUE 1 339 #define SI32_SPI_A_CONFIG_TFRQIEN_ENABLED_U32 \ 340 (SI32_SPI_A_CONFIG_TFRQIEN_ENABLED_VALUE << SI32_SPI_A_CONFIG_TFRQIEN_SHIFT) 341 342 #define SI32_SPI_A_CONFIG_TFORIEN_MASK 0x00000008 343 #define SI32_SPI_A_CONFIG_TFORIEN_SHIFT 3 344 // Disable the transmit FIFO overrun interrupt. 345 #define SI32_SPI_A_CONFIG_TFORIEN_DISABLED_VALUE 0 346 #define SI32_SPI_A_CONFIG_TFORIEN_DISABLED_U32 \ 347 (SI32_SPI_A_CONFIG_TFORIEN_DISABLED_VALUE << SI32_SPI_A_CONFIG_TFORIEN_SHIFT) 348 // Enable the transmit FIFO overrun interrupt. 349 #define SI32_SPI_A_CONFIG_TFORIEN_ENABLED_VALUE 1 350 #define SI32_SPI_A_CONFIG_TFORIEN_ENABLED_U32 \ 351 (SI32_SPI_A_CONFIG_TFORIEN_ENABLED_VALUE << SI32_SPI_A_CONFIG_TFORIEN_SHIFT) 352 353 #define SI32_SPI_A_CONFIG_SLVSELIEN_MASK 0x00000010 354 #define SI32_SPI_A_CONFIG_SLVSELIEN_SHIFT 4 355 // Disable the slave select interrupt. 356 #define SI32_SPI_A_CONFIG_SLVSELIEN_DISABLED_VALUE 0 357 #define SI32_SPI_A_CONFIG_SLVSELIEN_DISABLED_U32 \ 358 (SI32_SPI_A_CONFIG_SLVSELIEN_DISABLED_VALUE << SI32_SPI_A_CONFIG_SLVSELIEN_SHIFT) 359 // Enable the slave select interrupt. 360 #define SI32_SPI_A_CONFIG_SLVSELIEN_ENABLED_VALUE 1 361 #define SI32_SPI_A_CONFIG_SLVSELIEN_ENABLED_U32 \ 362 (SI32_SPI_A_CONFIG_SLVSELIEN_ENABLED_VALUE << SI32_SPI_A_CONFIG_SLVSELIEN_SHIFT) 363 364 #define SI32_SPI_A_CONFIG_MDFIEN_MASK 0x00000020 365 #define SI32_SPI_A_CONFIG_MDFIEN_SHIFT 5 366 // Disable the mode fault interrupt. 367 #define SI32_SPI_A_CONFIG_MDFIEN_DISABLED_VALUE 0 368 #define SI32_SPI_A_CONFIG_MDFIEN_DISABLED_U32 \ 369 (SI32_SPI_A_CONFIG_MDFIEN_DISABLED_VALUE << SI32_SPI_A_CONFIG_MDFIEN_SHIFT) 370 // Enable the mode fault interrupt. 371 #define SI32_SPI_A_CONFIG_MDFIEN_ENABLED_VALUE 1 372 #define SI32_SPI_A_CONFIG_MDFIEN_ENABLED_U32 \ 373 (SI32_SPI_A_CONFIG_MDFIEN_ENABLED_VALUE << SI32_SPI_A_CONFIG_MDFIEN_SHIFT) 374 375 #define SI32_SPI_A_CONFIG_URIEN_MASK 0x00000040 376 #define SI32_SPI_A_CONFIG_URIEN_SHIFT 6 377 // Disable the underrun interrupt. 378 #define SI32_SPI_A_CONFIG_URIEN_DISABLED_VALUE 0 379 #define SI32_SPI_A_CONFIG_URIEN_DISABLED_U32 \ 380 (SI32_SPI_A_CONFIG_URIEN_DISABLED_VALUE << SI32_SPI_A_CONFIG_URIEN_SHIFT) 381 // Enable the underrun interrupt. 382 #define SI32_SPI_A_CONFIG_URIEN_ENABLED_VALUE 1 383 #define SI32_SPI_A_CONFIG_URIEN_ENABLED_U32 \ 384 (SI32_SPI_A_CONFIG_URIEN_ENABLED_VALUE << SI32_SPI_A_CONFIG_URIEN_SHIFT) 385 386 #define SI32_SPI_A_CONFIG_SREIEN_MASK 0x00000080 387 #define SI32_SPI_A_CONFIG_SREIEN_SHIFT 7 388 // Disable the shift register empty interrupt. 389 #define SI32_SPI_A_CONFIG_SREIEN_DISABLED_VALUE 0 390 #define SI32_SPI_A_CONFIG_SREIEN_DISABLED_U32 \ 391 (SI32_SPI_A_CONFIG_SREIEN_DISABLED_VALUE << SI32_SPI_A_CONFIG_SREIEN_SHIFT) 392 // Enable the shift register empty interrupt. 393 #define SI32_SPI_A_CONFIG_SREIEN_ENABLED_VALUE 1 394 #define SI32_SPI_A_CONFIG_SREIEN_ENABLED_U32 \ 395 (SI32_SPI_A_CONFIG_SREIEN_ENABLED_VALUE << SI32_SPI_A_CONFIG_SREIEN_SHIFT) 396 397 #define SI32_SPI_A_CONFIG_SPIEN_MASK 0x00000100 398 #define SI32_SPI_A_CONFIG_SPIEN_SHIFT 8 399 // Disable the SPI. 400 #define SI32_SPI_A_CONFIG_SPIEN_DISABLED_VALUE 0 401 #define SI32_SPI_A_CONFIG_SPIEN_DISABLED_U32 \ 402 (SI32_SPI_A_CONFIG_SPIEN_DISABLED_VALUE << SI32_SPI_A_CONFIG_SPIEN_SHIFT) 403 // Enable the SPI. 404 #define SI32_SPI_A_CONFIG_SPIEN_ENABLED_VALUE 1 405 #define SI32_SPI_A_CONFIG_SPIEN_ENABLED_U32 \ 406 (SI32_SPI_A_CONFIG_SPIEN_ENABLED_VALUE << SI32_SPI_A_CONFIG_SPIEN_SHIFT) 407 408 #define SI32_SPI_A_CONFIG_MSTEN_MASK 0x00000200 409 #define SI32_SPI_A_CONFIG_MSTEN_SHIFT 9 410 // Operate in slave mode. 411 #define SI32_SPI_A_CONFIG_MSTEN_DISABLED_VALUE 0 412 #define SI32_SPI_A_CONFIG_MSTEN_DISABLED_U32 \ 413 (SI32_SPI_A_CONFIG_MSTEN_DISABLED_VALUE << SI32_SPI_A_CONFIG_MSTEN_SHIFT) 414 // Operate in master mode. 415 #define SI32_SPI_A_CONFIG_MSTEN_ENABLED_VALUE 1 416 #define SI32_SPI_A_CONFIG_MSTEN_ENABLED_U32 \ 417 (SI32_SPI_A_CONFIG_MSTEN_ENABLED_VALUE << SI32_SPI_A_CONFIG_MSTEN_SHIFT) 418 419 #define SI32_SPI_A_CONFIG_CLKPOL_MASK 0x00000400 420 #define SI32_SPI_A_CONFIG_CLKPOL_SHIFT 10 421 // The SCK line is low in the idle state. 422 #define SI32_SPI_A_CONFIG_CLKPOL_LOW_VALUE 0 423 #define SI32_SPI_A_CONFIG_CLKPOL_LOW_U32 \ 424 (SI32_SPI_A_CONFIG_CLKPOL_LOW_VALUE << SI32_SPI_A_CONFIG_CLKPOL_SHIFT) 425 // The SCK line is high in the idle state. 426 #define SI32_SPI_A_CONFIG_CLKPOL_HIGH_VALUE 1 427 #define SI32_SPI_A_CONFIG_CLKPOL_HIGH_U32 \ 428 (SI32_SPI_A_CONFIG_CLKPOL_HIGH_VALUE << SI32_SPI_A_CONFIG_CLKPOL_SHIFT) 429 430 #define SI32_SPI_A_CONFIG_CLKPHA_MASK 0x00000800 431 #define SI32_SPI_A_CONFIG_CLKPHA_SHIFT 11 432 // The first edge of SCK is the sample edge (center of data bit). 433 #define SI32_SPI_A_CONFIG_CLKPHA_CENTER_VALUE 0 434 #define SI32_SPI_A_CONFIG_CLKPHA_CENTER_U32 \ 435 (SI32_SPI_A_CONFIG_CLKPHA_CENTER_VALUE << SI32_SPI_A_CONFIG_CLKPHA_SHIFT) 436 // The first edge of SCK is the shift edge (edge of data bit). 437 #define SI32_SPI_A_CONFIG_CLKPHA_EDGE_VALUE 1 438 #define SI32_SPI_A_CONFIG_CLKPHA_EDGE_U32 \ 439 (SI32_SPI_A_CONFIG_CLKPHA_EDGE_VALUE << SI32_SPI_A_CONFIG_CLKPHA_SHIFT) 440 441 #define SI32_SPI_A_CONFIG_NSSPOL_MASK 0x00001000 442 #define SI32_SPI_A_CONFIG_NSSPOL_SHIFT 12 443 // NSS is active low. 444 #define SI32_SPI_A_CONFIG_NSSPOL_LOW_VALUE 0 445 #define SI32_SPI_A_CONFIG_NSSPOL_LOW_U32 \ 446 (SI32_SPI_A_CONFIG_NSSPOL_LOW_VALUE << SI32_SPI_A_CONFIG_NSSPOL_SHIFT) 447 // NSS is active high. 448 #define SI32_SPI_A_CONFIG_NSSPOL_HIGH_VALUE 1 449 #define SI32_SPI_A_CONFIG_NSSPOL_HIGH_U32 \ 450 (SI32_SPI_A_CONFIG_NSSPOL_HIGH_VALUE << SI32_SPI_A_CONFIG_NSSPOL_SHIFT) 451 452 #define SI32_SPI_A_CONFIG_DDIRSEL_MASK 0x00002000 453 #define SI32_SPI_A_CONFIG_DDIRSEL_SHIFT 13 454 // Data will be shifted MSB first. 455 #define SI32_SPI_A_CONFIG_DDIRSEL_MSB_FIRST_VALUE 0 456 #define SI32_SPI_A_CONFIG_DDIRSEL_MSB_FIRST_U32 \ 457 (SI32_SPI_A_CONFIG_DDIRSEL_MSB_FIRST_VALUE << SI32_SPI_A_CONFIG_DDIRSEL_SHIFT) 458 // Data will be shifted LSB first. 459 #define SI32_SPI_A_CONFIG_DDIRSEL_LSB_FIRST_VALUE 1 460 #define SI32_SPI_A_CONFIG_DDIRSEL_LSB_FIRST_U32 \ 461 (SI32_SPI_A_CONFIG_DDIRSEL_LSB_FIRST_VALUE << SI32_SPI_A_CONFIG_DDIRSEL_SHIFT) 462 463 #define SI32_SPI_A_CONFIG_NSSMD_MASK 0x0000C000 464 #define SI32_SPI_A_CONFIG_NSSMD_SHIFT 14 465 // 3-wire Slave or 3-wire Master. 466 #define SI32_SPI_A_CONFIG_NSSMD_3_WIRE_MASTER_SLAVE_VALUE 0 467 #define SI32_SPI_A_CONFIG_NSSMD_3_WIRE_MASTER_SLAVE_U32 \ 468 (SI32_SPI_A_CONFIG_NSSMD_3_WIRE_MASTER_SLAVE_VALUE << SI32_SPI_A_CONFIG_NSSMD_SHIFT) 469 // 4-wire slave (NSS input). This setting can also be used for multi-master 470 // configurations. 471 #define SI32_SPI_A_CONFIG_NSSMD_4_WIRE_SLAVE_VALUE 1 472 #define SI32_SPI_A_CONFIG_NSSMD_4_WIRE_SLAVE_U32 \ 473 (SI32_SPI_A_CONFIG_NSSMD_4_WIRE_SLAVE_VALUE << SI32_SPI_A_CONFIG_NSSMD_SHIFT) 474 // 4-wire master with NSS low (NSS output). 475 #define SI32_SPI_A_CONFIG_NSSMD_4_WIRE_MASTER_NSS_LOW_VALUE 2 476 #define SI32_SPI_A_CONFIG_NSSMD_4_WIRE_MASTER_NSS_LOW_U32 \ 477 (SI32_SPI_A_CONFIG_NSSMD_4_WIRE_MASTER_NSS_LOW_VALUE << SI32_SPI_A_CONFIG_NSSMD_SHIFT) 478 // 4-wire master with NSS high (NSS output). 479 #define SI32_SPI_A_CONFIG_NSSMD_4_WIRE_MASTER_NSS_HIGH_VALUE 3 480 #define SI32_SPI_A_CONFIG_NSSMD_4_WIRE_MASTER_NSS_HIGH_U32 \ 481 (SI32_SPI_A_CONFIG_NSSMD_4_WIRE_MASTER_NSS_HIGH_VALUE << SI32_SPI_A_CONFIG_NSSMD_SHIFT) 482 483 #define SI32_SPI_A_CONFIG_RFTH_MASK 0x00030000 484 #define SI32_SPI_A_CONFIG_RFTH_SHIFT 16 485 // A DMA / RFRQ request asserts when >= 1 FIFO slot is filled. 486 #define SI32_SPI_A_CONFIG_RFTH_ONE_VALUE 0 487 #define SI32_SPI_A_CONFIG_RFTH_ONE_U32 \ 488 (SI32_SPI_A_CONFIG_RFTH_ONE_VALUE << SI32_SPI_A_CONFIG_RFTH_SHIFT) 489 // A DMA / RFRQ request asserts when >= 2 FIFO slots are filled. 490 #define SI32_SPI_A_CONFIG_RFTH_TWO_VALUE 1 491 #define SI32_SPI_A_CONFIG_RFTH_TWO_U32 \ 492 (SI32_SPI_A_CONFIG_RFTH_TWO_VALUE << SI32_SPI_A_CONFIG_RFTH_SHIFT) 493 // A DMA / RFRQ request asserts when >= 4 FIFO slots are filled. 494 #define SI32_SPI_A_CONFIG_RFTH_FOUR_VALUE 2 495 #define SI32_SPI_A_CONFIG_RFTH_FOUR_U32 \ 496 (SI32_SPI_A_CONFIG_RFTH_FOUR_VALUE << SI32_SPI_A_CONFIG_RFTH_SHIFT) 497 // A DMA / RFRQ request asserts when all FIFO slots are filled. 498 #define SI32_SPI_A_CONFIG_RFTH_FULL_VALUE 3 499 #define SI32_SPI_A_CONFIG_RFTH_FULL_U32 \ 500 (SI32_SPI_A_CONFIG_RFTH_FULL_VALUE << SI32_SPI_A_CONFIG_RFTH_SHIFT) 501 502 #define SI32_SPI_A_CONFIG_TFTH_MASK 0x000C0000 503 #define SI32_SPI_A_CONFIG_TFTH_SHIFT 18 504 // A DMA / TFRQ request asserts when >= 1 FIFO slot is empty. 505 #define SI32_SPI_A_CONFIG_TFTH_ONE_VALUE 0 506 #define SI32_SPI_A_CONFIG_TFTH_ONE_U32 \ 507 (SI32_SPI_A_CONFIG_TFTH_ONE_VALUE << SI32_SPI_A_CONFIG_TFTH_SHIFT) 508 // A DMA / TFRQ request asserts when >= 2 FIFO slots are empty. 509 #define SI32_SPI_A_CONFIG_TFTH_TWO_VALUE 1 510 #define SI32_SPI_A_CONFIG_TFTH_TWO_U32 \ 511 (SI32_SPI_A_CONFIG_TFTH_TWO_VALUE << SI32_SPI_A_CONFIG_TFTH_SHIFT) 512 // A DMA / TFRQ request asserts when >= 4 FIFO slots are empty. 513 #define SI32_SPI_A_CONFIG_TFTH_FOUR_VALUE 2 514 #define SI32_SPI_A_CONFIG_TFTH_FOUR_U32 \ 515 (SI32_SPI_A_CONFIG_TFTH_FOUR_VALUE << SI32_SPI_A_CONFIG_TFTH_SHIFT) 516 // A DMA / TFRQ request asserts when all FIFO slots are empty. 517 #define SI32_SPI_A_CONFIG_TFTH_EMPTY_VALUE 3 518 #define SI32_SPI_A_CONFIG_TFTH_EMPTY_U32 \ 519 (SI32_SPI_A_CONFIG_TFTH_EMPTY_VALUE << SI32_SPI_A_CONFIG_TFTH_SHIFT) 520 521 #define SI32_SPI_A_CONFIG_DSIZE_MASK 0x00F00000 522 #define SI32_SPI_A_CONFIG_DSIZE_SHIFT 20 523 524 #define SI32_SPI_A_CONFIG_DMAEN_MASK 0x01000000 525 #define SI32_SPI_A_CONFIG_DMAEN_SHIFT 24 526 // Disable DMA requests. 527 #define SI32_SPI_A_CONFIG_DMAEN_DISABLED_VALUE 0 528 #define SI32_SPI_A_CONFIG_DMAEN_DISABLED_U32 \ 529 (SI32_SPI_A_CONFIG_DMAEN_DISABLED_VALUE << SI32_SPI_A_CONFIG_DMAEN_SHIFT) 530 // Enable DMA requests when the transmit buffer is empty or the receive buffer is 531 // full. 532 #define SI32_SPI_A_CONFIG_DMAEN_ENABLED_VALUE 1 533 #define SI32_SPI_A_CONFIG_DMAEN_ENABLED_U32 \ 534 (SI32_SPI_A_CONFIG_DMAEN_ENABLED_VALUE << SI32_SPI_A_CONFIG_DMAEN_SHIFT) 535 536 #define SI32_SPI_A_CONFIG_RFIFOFL_MASK 0x20000000 537 #define SI32_SPI_A_CONFIG_RFIFOFL_SHIFT 29 538 // Flush the receive FIFO. 539 #define SI32_SPI_A_CONFIG_RFIFOFL_SET_VALUE 1 540 #define SI32_SPI_A_CONFIG_RFIFOFL_SET_U32 \ 541 (SI32_SPI_A_CONFIG_RFIFOFL_SET_VALUE << SI32_SPI_A_CONFIG_RFIFOFL_SHIFT) 542 543 #define SI32_SPI_A_CONFIG_TFIFOFL_MASK 0x40000000 544 #define SI32_SPI_A_CONFIG_TFIFOFL_SHIFT 30 545 // Flush the transmit FIFO. 546 #define SI32_SPI_A_CONFIG_TFIFOFL_SET_VALUE 1 547 #define SI32_SPI_A_CONFIG_TFIFOFL_SET_U32 \ 548 (SI32_SPI_A_CONFIG_TFIFOFL_SET_VALUE << SI32_SPI_A_CONFIG_TFIFOFL_SHIFT) 549 550 #define SI32_SPI_A_CONFIG_RESET_MASK 0x80000000 551 #define SI32_SPI_A_CONFIG_RESET_SHIFT 31 552 // SPI module is not in soft reset. 553 #define SI32_SPI_A_CONFIG_RESET_INACTIVE_VALUE 0U 554 #define SI32_SPI_A_CONFIG_RESET_INACTIVE_U32 \ 555 (SI32_SPI_A_CONFIG_RESET_INACTIVE_VALUE << SI32_SPI_A_CONFIG_RESET_SHIFT) 556 // SPI module is in soft reset and some of the module bits cannot be accessed until 557 // this bit is cleared to 0 by hardware. 558 #define SI32_SPI_A_CONFIG_RESET_ACTIVE_VALUE 1U 559 #define SI32_SPI_A_CONFIG_RESET_ACTIVE_U32 \ 560 (SI32_SPI_A_CONFIG_RESET_ACTIVE_VALUE << SI32_SPI_A_CONFIG_RESET_SHIFT) 561 562 563 564 struct SI32_SPI_A_CLKRATE_Struct 565 { 566 union 567 { 568 struct 569 { 570 // Clock Divider 571 volatile uint16_t CLKDIV; 572 uint32_t reserved0: 16; 573 }; 574 volatile uint32_t U32; 575 }; 576 }; 577 578 #define SI32_SPI_A_CLKRATE_CLKDIV_MASK 0x0000FFFF 579 #define SI32_SPI_A_CLKRATE_CLKDIV_SHIFT 0 580 581 582 583 struct SI32_SPI_A_FSTATUS_Struct 584 { 585 union 586 { 587 struct 588 { 589 // Receive FIFO Read Pointer 590 volatile uint32_t RFRPTR: 4; 591 // Receive FIFO Write Pointer 592 volatile uint32_t RFWPTR: 4; 593 // Transmit FIFO Read Pointer 594 volatile uint32_t TFRPTR: 4; 595 // Transmit FIFO Write Pointer 596 volatile uint32_t TFWPTR: 4; 597 uint32_t reserved0: 16; 598 }; 599 volatile uint32_t U32; 600 }; 601 }; 602 603 #define SI32_SPI_A_FSTATUS_RFRPTR_MASK 0x0000000F 604 #define SI32_SPI_A_FSTATUS_RFRPTR_SHIFT 0 605 606 #define SI32_SPI_A_FSTATUS_RFWPTR_MASK 0x000000F0 607 #define SI32_SPI_A_FSTATUS_RFWPTR_SHIFT 4 608 609 #define SI32_SPI_A_FSTATUS_TFRPTR_MASK 0x00000F00 610 #define SI32_SPI_A_FSTATUS_TFRPTR_SHIFT 8 611 612 #define SI32_SPI_A_FSTATUS_TFWPTR_MASK 0x0000F000 613 #define SI32_SPI_A_FSTATUS_TFWPTR_SHIFT 12 614 615 616 617 typedef struct SI32_SPI_A_Struct 618 { 619 struct SI32_SPI_A_DATA_Struct DATA ; // Base Address + 0x0 620 uint32_t reserved0; 621 uint32_t reserved1; 622 uint32_t reserved2; 623 struct SI32_SPI_A_CONTROL_Struct CONTROL ; // Base Address + 0x10 624 volatile uint32_t CONTROL_SET; 625 volatile uint32_t CONTROL_CLR; 626 uint32_t reserved3; 627 struct SI32_SPI_A_CONFIG_Struct CONFIG ; // Base Address + 0x20 628 volatile uint32_t CONFIG_SET; 629 volatile uint32_t CONFIG_CLR; 630 uint32_t reserved4; 631 struct SI32_SPI_A_CLKRATE_Struct CLKRATE ; // Base Address + 0x30 632 uint32_t reserved5; 633 uint32_t reserved6; 634 uint32_t reserved7; 635 struct SI32_SPI_A_FSTATUS_Struct FSTATUS ; // Base Address + 0x40 636 uint32_t reserved8; 637 uint32_t reserved9; 638 uint32_t reserved10; 639 } SI32_SPI_A_Type; 640 641 #ifdef __cplusplus 642 } 643 #endif 644 645 #endif // __SI32_SPI_A_REGISTERS_H__ 646 647 //-eof-------------------------------------------------------------------------- 648 649
