1 //----------------------------------------------------------------------------- 2 // Copyright 2012 (c) Silicon Laboratories Inc. 3 // 4 // SPDX-License-Identifier: Zlib 5 // 6 // This siHAL software is provided 'as-is', without any express or implied 7 // warranty. In no event will the authors be held liable for any damages 8 // arising from the use of this software. 9 // 10 // Permission is granted to anyone to use this software for any purpose, 11 // including commercial applications, and to alter it and redistribute it 12 // freely, subject to the following restrictions: 13 // 14 // 1. The origin of this software must not be misrepresented; you must not 15 // claim that you wrote the original software. If you use this software 16 // in a product, an acknowledgment in the product documentation would be 17 // appreciated but is not required. 18 // 2. Altered source versions must be plainly marked as such, and must not be 19 // misrepresented as being the original software. 20 // 3. This notice may not be removed or altered from any source distribution. 21 //----------------------------------------------------------------------------- 22 // 23 // Script: 0.61 24 // Version: 1 25 26 #ifndef __SI32_RTC_B_REGISTERS_H__ 27 #define __SI32_RTC_B_REGISTERS_H__ 28 29 #include <stdint.h> 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 struct SI32_RTC_B_CONFIG_Struct 36 { 37 union 38 { 39 struct 40 { 41 // Alarm 0 Automatic Reset Enable 42 volatile uint32_t ALM0AREN: 1; 43 // RTC Timer Run Control 44 volatile uint32_t RUN: 1; 45 // Missing Clock Detector Enable 46 volatile uint32_t MCLKEN: 1; 47 // Automatic Crystal Load Capacitance Stepping Enable 48 volatile uint32_t ASEN: 1; 49 // Load Capacitance Value 50 volatile uint32_t RTCLC: 4; 51 uint32_t reserved0: 8; 52 // Bias Doubler Enable 53 volatile uint32_t BDEN: 1; 54 // Crystal Oscillator Enable 55 volatile uint32_t CRYSEN: 1; 56 // Automatic Gain Control Enable 57 volatile uint32_t AGCEN: 1; 58 uint32_t reserved1: 5; 59 // Alarm 0 Enable 60 volatile uint32_t ALM0EN: 1; 61 // Alarm 1 Enable 62 volatile uint32_t ALM1EN: 1; 63 // Alarm 2 Enable 64 volatile uint32_t ALM2EN: 1; 65 uint32_t reserved2: 1; 66 // RTC Clock Output Enable 67 volatile uint32_t CLKOEN: 1; 68 // RTC External Output Enable 69 volatile uint32_t RTCOEN: 1; 70 // RTC Timer Clock Select 71 volatile uint32_t CLKSEL: 1; 72 // RTC Timer Enable 73 volatile uint32_t RTCEN: 1; 74 }; 75 volatile uint32_t U32; 76 }; 77 }; 78 79 #define SI32_RTC_B_CONFIG_ALM0AREN_MASK 0x00000001 80 #define SI32_RTC_B_CONFIG_ALM0AREN_SHIFT 0 81 // Disable the Alarm 0 automatic reset. 82 #define SI32_RTC_B_CONFIG_ALM0AREN_DISABLED_VALUE 0 83 #define SI32_RTC_B_CONFIG_ALM0AREN_DISABLED_U32 \ 84 (SI32_RTC_B_CONFIG_ALM0AREN_DISABLED_VALUE << SI32_RTC_B_CONFIG_ALM0AREN_SHIFT) 85 // Enable the Alarm 0 automatic reset. 86 #define SI32_RTC_B_CONFIG_ALM0AREN_ENABLED_VALUE 1 87 #define SI32_RTC_B_CONFIG_ALM0AREN_ENABLED_U32 \ 88 (SI32_RTC_B_CONFIG_ALM0AREN_ENABLED_VALUE << SI32_RTC_B_CONFIG_ALM0AREN_SHIFT) 89 90 #define SI32_RTC_B_CONFIG_RUN_MASK 0x00000002 91 #define SI32_RTC_B_CONFIG_RUN_SHIFT 1 92 // Stop the RTC timer. 93 #define SI32_RTC_B_CONFIG_RUN_STOP_VALUE 0 94 #define SI32_RTC_B_CONFIG_RUN_STOP_U32 \ 95 (SI32_RTC_B_CONFIG_RUN_STOP_VALUE << SI32_RTC_B_CONFIG_RUN_SHIFT) 96 // Run the RTC timer. 97 #define SI32_RTC_B_CONFIG_RUN_START_VALUE 1 98 #define SI32_RTC_B_CONFIG_RUN_START_U32 \ 99 (SI32_RTC_B_CONFIG_RUN_START_VALUE << SI32_RTC_B_CONFIG_RUN_SHIFT) 100 101 #define SI32_RTC_B_CONFIG_MCLKEN_MASK 0x00000004 102 #define SI32_RTC_B_CONFIG_MCLKEN_SHIFT 2 103 // Disable the missing clock detector. 104 #define SI32_RTC_B_CONFIG_MCLKEN_DISABLED_VALUE 0 105 #define SI32_RTC_B_CONFIG_MCLKEN_DISABLED_U32 \ 106 (SI32_RTC_B_CONFIG_MCLKEN_DISABLED_VALUE << SI32_RTC_B_CONFIG_MCLKEN_SHIFT) 107 // Enable the missing clock detector. If the missing clock detector triggers, it 108 // will generate an RTC Fail event. 109 #define SI32_RTC_B_CONFIG_MCLKEN_ENABLED_VALUE 1 110 #define SI32_RTC_B_CONFIG_MCLKEN_ENABLED_U32 \ 111 (SI32_RTC_B_CONFIG_MCLKEN_ENABLED_VALUE << SI32_RTC_B_CONFIG_MCLKEN_SHIFT) 112 113 #define SI32_RTC_B_CONFIG_ASEN_MASK 0x00000008 114 #define SI32_RTC_B_CONFIG_ASEN_SHIFT 3 115 // Disable automatic load capacitance stepping. 116 #define SI32_RTC_B_CONFIG_ASEN_DISABLED_VALUE 0 117 #define SI32_RTC_B_CONFIG_ASEN_DISABLED_U32 \ 118 (SI32_RTC_B_CONFIG_ASEN_DISABLED_VALUE << SI32_RTC_B_CONFIG_ASEN_SHIFT) 119 // Enable automatic load capacitance stepping. 120 #define SI32_RTC_B_CONFIG_ASEN_ENABLED_VALUE 1 121 #define SI32_RTC_B_CONFIG_ASEN_ENABLED_U32 \ 122 (SI32_RTC_B_CONFIG_ASEN_ENABLED_VALUE << SI32_RTC_B_CONFIG_ASEN_SHIFT) 123 124 #define SI32_RTC_B_CONFIG_RTCLC_MASK 0x000000F0 125 #define SI32_RTC_B_CONFIG_RTCLC_SHIFT 4 126 127 #define SI32_RTC_B_CONFIG_BDEN_MASK 0x00010000 128 #define SI32_RTC_B_CONFIG_BDEN_SHIFT 16 129 // Disable the bias doubler, saving power. 130 #define SI32_RTC_B_CONFIG_BDEN_DISABLED_VALUE 0 131 #define SI32_RTC_B_CONFIG_BDEN_DISABLED_U32 \ 132 (SI32_RTC_B_CONFIG_BDEN_DISABLED_VALUE << SI32_RTC_B_CONFIG_BDEN_SHIFT) 133 // Enable the bias doubler. 134 #define SI32_RTC_B_CONFIG_BDEN_ENABLED_VALUE 1 135 #define SI32_RTC_B_CONFIG_BDEN_ENABLED_U32 \ 136 (SI32_RTC_B_CONFIG_BDEN_ENABLED_VALUE << SI32_RTC_B_CONFIG_BDEN_SHIFT) 137 138 #define SI32_RTC_B_CONFIG_CRYSEN_MASK 0x00020000 139 #define SI32_RTC_B_CONFIG_CRYSEN_SHIFT 17 140 // Disable the crystal oscillator circuitry. 141 #define SI32_RTC_B_CONFIG_CRYSEN_DISABLED_VALUE 0 142 #define SI32_RTC_B_CONFIG_CRYSEN_DISABLED_U32 \ 143 (SI32_RTC_B_CONFIG_CRYSEN_DISABLED_VALUE << SI32_RTC_B_CONFIG_CRYSEN_SHIFT) 144 // Enable the crystal oscillator circuitry. 145 #define SI32_RTC_B_CONFIG_CRYSEN_ENABLED_VALUE 1 146 #define SI32_RTC_B_CONFIG_CRYSEN_ENABLED_U32 \ 147 (SI32_RTC_B_CONFIG_CRYSEN_ENABLED_VALUE << SI32_RTC_B_CONFIG_CRYSEN_SHIFT) 148 149 #define SI32_RTC_B_CONFIG_AGCEN_MASK 0x00040000 150 #define SI32_RTC_B_CONFIG_AGCEN_SHIFT 18 151 // Disable automatic gain control. 152 #define SI32_RTC_B_CONFIG_AGCEN_DISABLED_VALUE 0 153 #define SI32_RTC_B_CONFIG_AGCEN_DISABLED_U32 \ 154 (SI32_RTC_B_CONFIG_AGCEN_DISABLED_VALUE << SI32_RTC_B_CONFIG_AGCEN_SHIFT) 155 // Enable automatic gain control, saving power. 156 #define SI32_RTC_B_CONFIG_AGCEN_ENABLED_VALUE 1 157 #define SI32_RTC_B_CONFIG_AGCEN_ENABLED_U32 \ 158 (SI32_RTC_B_CONFIG_AGCEN_ENABLED_VALUE << SI32_RTC_B_CONFIG_AGCEN_SHIFT) 159 160 #define SI32_RTC_B_CONFIG_ALM0EN_MASK 0x01000000 161 #define SI32_RTC_B_CONFIG_ALM0EN_SHIFT 24 162 // Disable RTC Alarm 0. 163 #define SI32_RTC_B_CONFIG_ALM0EN_DISABLED_VALUE 0 164 #define SI32_RTC_B_CONFIG_ALM0EN_DISABLED_U32 \ 165 (SI32_RTC_B_CONFIG_ALM0EN_DISABLED_VALUE << SI32_RTC_B_CONFIG_ALM0EN_SHIFT) 166 // Enable RTC Alarm 0. 167 #define SI32_RTC_B_CONFIG_ALM0EN_ENABLED_VALUE 1 168 #define SI32_RTC_B_CONFIG_ALM0EN_ENABLED_U32 \ 169 (SI32_RTC_B_CONFIG_ALM0EN_ENABLED_VALUE << SI32_RTC_B_CONFIG_ALM0EN_SHIFT) 170 171 #define SI32_RTC_B_CONFIG_ALM1EN_MASK 0x02000000 172 #define SI32_RTC_B_CONFIG_ALM1EN_SHIFT 25 173 // Disable RTC Alarm 1. 174 #define SI32_RTC_B_CONFIG_ALM1EN_DISABLED_VALUE 0 175 #define SI32_RTC_B_CONFIG_ALM1EN_DISABLED_U32 \ 176 (SI32_RTC_B_CONFIG_ALM1EN_DISABLED_VALUE << SI32_RTC_B_CONFIG_ALM1EN_SHIFT) 177 // Enable RTC Alarm 1. 178 #define SI32_RTC_B_CONFIG_ALM1EN_ENABLED_VALUE 1 179 #define SI32_RTC_B_CONFIG_ALM1EN_ENABLED_U32 \ 180 (SI32_RTC_B_CONFIG_ALM1EN_ENABLED_VALUE << SI32_RTC_B_CONFIG_ALM1EN_SHIFT) 181 182 #define SI32_RTC_B_CONFIG_ALM2EN_MASK 0x04000000 183 #define SI32_RTC_B_CONFIG_ALM2EN_SHIFT 26 184 // Disable RTC Alarm 2. 185 #define SI32_RTC_B_CONFIG_ALM2EN_DISABLED_VALUE 0 186 #define SI32_RTC_B_CONFIG_ALM2EN_DISABLED_U32 \ 187 (SI32_RTC_B_CONFIG_ALM2EN_DISABLED_VALUE << SI32_RTC_B_CONFIG_ALM2EN_SHIFT) 188 // Enable RTC Alarm 2. 189 #define SI32_RTC_B_CONFIG_ALM2EN_ENABLED_VALUE 1 190 #define SI32_RTC_B_CONFIG_ALM2EN_ENABLED_U32 \ 191 (SI32_RTC_B_CONFIG_ALM2EN_ENABLED_VALUE << SI32_RTC_B_CONFIG_ALM2EN_SHIFT) 192 193 #define SI32_RTC_B_CONFIG_CLKOEN_MASK 0x10000000 194 #define SI32_RTC_B_CONFIG_CLKOEN_SHIFT 28 195 // Disable the RTCnTCLK output to the timer and other internal modules. 196 #define SI32_RTC_B_CONFIG_CLKOEN_DISABLED_VALUE 0 197 #define SI32_RTC_B_CONFIG_CLKOEN_DISABLED_U32 \ 198 (SI32_RTC_B_CONFIG_CLKOEN_DISABLED_VALUE << SI32_RTC_B_CONFIG_CLKOEN_SHIFT) 199 // Enable the RTCnTCLK output to the timer and other internal modules. 200 #define SI32_RTC_B_CONFIG_CLKOEN_ENABLED_VALUE 1 201 #define SI32_RTC_B_CONFIG_CLKOEN_ENABLED_U32 \ 202 (SI32_RTC_B_CONFIG_CLKOEN_ENABLED_VALUE << SI32_RTC_B_CONFIG_CLKOEN_SHIFT) 203 204 #define SI32_RTC_B_CONFIG_RTCOEN_MASK 0x20000000 205 #define SI32_RTC_B_CONFIG_RTCOEN_SHIFT 29 206 // Disable the external RTCnTCLK_OUT output. 207 #define SI32_RTC_B_CONFIG_RTCOEN_DISABLED_VALUE 0 208 #define SI32_RTC_B_CONFIG_RTCOEN_DISABLED_U32 \ 209 (SI32_RTC_B_CONFIG_RTCOEN_DISABLED_VALUE << SI32_RTC_B_CONFIG_RTCOEN_SHIFT) 210 // Enable the external RTCnTCLK_OUT output. 211 #define SI32_RTC_B_CONFIG_RTCOEN_ENABLED_VALUE 1 212 #define SI32_RTC_B_CONFIG_RTCOEN_ENABLED_U32 \ 213 (SI32_RTC_B_CONFIG_RTCOEN_ENABLED_VALUE << SI32_RTC_B_CONFIG_RTCOEN_SHIFT) 214 215 #define SI32_RTC_B_CONFIG_CLKSEL_MASK 0x40000000 216 #define SI32_RTC_B_CONFIG_CLKSEL_SHIFT 30 217 // Select the External Crystal or External CMOS Clock as the RTC Timer clock 218 // (RTCnTCLK) source. 219 #define SI32_RTC_B_CONFIG_CLKSEL_RTCNOSC_VALUE 0 220 #define SI32_RTC_B_CONFIG_CLKSEL_RTCNOSC_U32 \ 221 (SI32_RTC_B_CONFIG_CLKSEL_RTCNOSC_VALUE << SI32_RTC_B_CONFIG_CLKSEL_SHIFT) 222 // Select the Low Frequency Oscillator as the RTC Timer clock (RTCnTCLK) source. 223 #define SI32_RTC_B_CONFIG_CLKSEL_LFOSCN_VALUE 1 224 #define SI32_RTC_B_CONFIG_CLKSEL_LFOSCN_U32 \ 225 (SI32_RTC_B_CONFIG_CLKSEL_LFOSCN_VALUE << SI32_RTC_B_CONFIG_CLKSEL_SHIFT) 226 227 #define SI32_RTC_B_CONFIG_RTCEN_MASK 0x80000000 228 #define SI32_RTC_B_CONFIG_RTCEN_SHIFT 31 229 // Disable the RTC timer. 230 #define SI32_RTC_B_CONFIG_RTCEN_DISABLED_VALUE 0U 231 #define SI32_RTC_B_CONFIG_RTCEN_DISABLED_U32 \ 232 (SI32_RTC_B_CONFIG_RTCEN_DISABLED_VALUE << SI32_RTC_B_CONFIG_RTCEN_SHIFT) 233 // Enable the RTC timer. 234 #define SI32_RTC_B_CONFIG_RTCEN_ENABLED_VALUE 1U 235 #define SI32_RTC_B_CONFIG_RTCEN_ENABLED_U32 \ 236 (SI32_RTC_B_CONFIG_RTCEN_ENABLED_VALUE << SI32_RTC_B_CONFIG_RTCEN_SHIFT) 237 238 239 240 struct SI32_RTC_B_CONTROL_Struct 241 { 242 union 243 { 244 struct 245 { 246 // Alarm 0 Interrupt Flag 247 volatile uint32_t ALM0I: 1; 248 // Alarm 1 Interrupt Flag 249 volatile uint32_t ALM1I: 1; 250 // Alarm 2 Interrupt Flag 251 volatile uint32_t ALM2I: 1; 252 // RTC Timer Capture 253 volatile uint32_t TMRCAP: 1; 254 // RTC Timer Set 255 volatile uint32_t TMRSET: 1; 256 // RTC External Oscillator Valid Flag 257 volatile uint32_t CLKVF: 1; 258 // RTC Oscillator Fail Interrupt Flag 259 volatile uint32_t OSCFI: 1; 260 // RTC High Speed Mode Enable 261 volatile uint32_t HSMDEN: 1; 262 // RTC Load Capacitance Ready Flag 263 volatile uint32_t LRDYF: 1; 264 uint32_t reserved0: 23; 265 }; 266 volatile uint32_t U32; 267 }; 268 }; 269 270 #define SI32_RTC_B_CONTROL_ALM0I_MASK 0x00000001 271 #define SI32_RTC_B_CONTROL_ALM0I_SHIFT 0 272 // Alarm 0 event has not occurred. 273 #define SI32_RTC_B_CONTROL_ALM0I_NOT_SET_VALUE 0 274 #define SI32_RTC_B_CONTROL_ALM0I_NOT_SET_U32 \ 275 (SI32_RTC_B_CONTROL_ALM0I_NOT_SET_VALUE << SI32_RTC_B_CONTROL_ALM0I_SHIFT) 276 // Alarm 0 event occurred. 277 #define SI32_RTC_B_CONTROL_ALM0I_SET_VALUE 1 278 #define SI32_RTC_B_CONTROL_ALM0I_SET_U32 \ 279 (SI32_RTC_B_CONTROL_ALM0I_SET_VALUE << SI32_RTC_B_CONTROL_ALM0I_SHIFT) 280 281 #define SI32_RTC_B_CONTROL_ALM1I_MASK 0x00000002 282 #define SI32_RTC_B_CONTROL_ALM1I_SHIFT 1 283 // Alarm 1 event has not occurred. 284 #define SI32_RTC_B_CONTROL_ALM1I_NOT_SET_VALUE 0 285 #define SI32_RTC_B_CONTROL_ALM1I_NOT_SET_U32 \ 286 (SI32_RTC_B_CONTROL_ALM1I_NOT_SET_VALUE << SI32_RTC_B_CONTROL_ALM1I_SHIFT) 287 // Alarm 1 event occurred. 288 #define SI32_RTC_B_CONTROL_ALM1I_SET_VALUE 1 289 #define SI32_RTC_B_CONTROL_ALM1I_SET_U32 \ 290 (SI32_RTC_B_CONTROL_ALM1I_SET_VALUE << SI32_RTC_B_CONTROL_ALM1I_SHIFT) 291 292 #define SI32_RTC_B_CONTROL_ALM2I_MASK 0x00000004 293 #define SI32_RTC_B_CONTROL_ALM2I_SHIFT 2 294 // Alarm 2 event has not occurred. 295 #define SI32_RTC_B_CONTROL_ALM2I_NOT_SET_VALUE 0 296 #define SI32_RTC_B_CONTROL_ALM2I_NOT_SET_U32 \ 297 (SI32_RTC_B_CONTROL_ALM2I_NOT_SET_VALUE << SI32_RTC_B_CONTROL_ALM2I_SHIFT) 298 // Alarm 2 event occurred. 299 #define SI32_RTC_B_CONTROL_ALM2I_SET_VALUE 1 300 #define SI32_RTC_B_CONTROL_ALM2I_SET_U32 \ 301 (SI32_RTC_B_CONTROL_ALM2I_SET_VALUE << SI32_RTC_B_CONTROL_ALM2I_SHIFT) 302 303 #define SI32_RTC_B_CONTROL_TMRCAP_MASK 0x00000008 304 #define SI32_RTC_B_CONTROL_TMRCAP_SHIFT 3 305 // RTC timer capture operation is complete. 306 #define SI32_RTC_B_CONTROL_TMRCAP_NOT_SET_VALUE 0 307 #define SI32_RTC_B_CONTROL_TMRCAP_NOT_SET_U32 \ 308 (SI32_RTC_B_CONTROL_TMRCAP_NOT_SET_VALUE << SI32_RTC_B_CONTROL_TMRCAP_SHIFT) 309 // Start the RTC timer capture. 310 #define SI32_RTC_B_CONTROL_TMRCAP_SET_VALUE 1 311 #define SI32_RTC_B_CONTROL_TMRCAP_SET_U32 \ 312 (SI32_RTC_B_CONTROL_TMRCAP_SET_VALUE << SI32_RTC_B_CONTROL_TMRCAP_SHIFT) 313 314 #define SI32_RTC_B_CONTROL_TMRSET_MASK 0x00000010 315 #define SI32_RTC_B_CONTROL_TMRSET_SHIFT 4 316 // RTC timer set operation is complete. 317 #define SI32_RTC_B_CONTROL_TMRSET_NOT_SET_VALUE 0 318 #define SI32_RTC_B_CONTROL_TMRSET_NOT_SET_U32 \ 319 (SI32_RTC_B_CONTROL_TMRSET_NOT_SET_VALUE << SI32_RTC_B_CONTROL_TMRSET_SHIFT) 320 // Start the RTC timer set. 321 #define SI32_RTC_B_CONTROL_TMRSET_SET_VALUE 1 322 #define SI32_RTC_B_CONTROL_TMRSET_SET_U32 \ 323 (SI32_RTC_B_CONTROL_TMRSET_SET_VALUE << SI32_RTC_B_CONTROL_TMRSET_SHIFT) 324 325 #define SI32_RTC_B_CONTROL_CLKVF_MASK 0x00000020 326 #define SI32_RTC_B_CONTROL_CLKVF_SHIFT 5 327 // External oscillator is not valid. 328 #define SI32_RTC_B_CONTROL_CLKVF_NOT_SET_VALUE 0 329 #define SI32_RTC_B_CONTROL_CLKVF_NOT_SET_U32 \ 330 (SI32_RTC_B_CONTROL_CLKVF_NOT_SET_VALUE << SI32_RTC_B_CONTROL_CLKVF_SHIFT) 331 // External oscillator is valid. 332 #define SI32_RTC_B_CONTROL_CLKVF_SET_VALUE 1 333 #define SI32_RTC_B_CONTROL_CLKVF_SET_U32 \ 334 (SI32_RTC_B_CONTROL_CLKVF_SET_VALUE << SI32_RTC_B_CONTROL_CLKVF_SHIFT) 335 336 #define SI32_RTC_B_CONTROL_OSCFI_MASK 0x00000040 337 #define SI32_RTC_B_CONTROL_OSCFI_SHIFT 6 338 // Oscillator is running. 339 #define SI32_RTC_B_CONTROL_OSCFI_NOT_SET_VALUE 0 340 #define SI32_RTC_B_CONTROL_OSCFI_NOT_SET_U32 \ 341 (SI32_RTC_B_CONTROL_OSCFI_NOT_SET_VALUE << SI32_RTC_B_CONTROL_OSCFI_SHIFT) 342 // Oscillator has failed. 343 #define SI32_RTC_B_CONTROL_OSCFI_SET_VALUE 1 344 #define SI32_RTC_B_CONTROL_OSCFI_SET_U32 \ 345 (SI32_RTC_B_CONTROL_OSCFI_SET_VALUE << SI32_RTC_B_CONTROL_OSCFI_SHIFT) 346 347 #define SI32_RTC_B_CONTROL_HSMDEN_MASK 0x00000080 348 #define SI32_RTC_B_CONTROL_HSMDEN_SHIFT 7 349 // Disable high speed mode. (AHBCLK < 4x RTCnTCLK) 350 #define SI32_RTC_B_CONTROL_HSMDEN_DISABLED_VALUE 0 351 #define SI32_RTC_B_CONTROL_HSMDEN_DISABLED_U32 \ 352 (SI32_RTC_B_CONTROL_HSMDEN_DISABLED_VALUE << SI32_RTC_B_CONTROL_HSMDEN_SHIFT) 353 // Enable high speed mode. (AHBCLK >= 4x RTCnTCLK) 354 #define SI32_RTC_B_CONTROL_HSMDEN_ENABLED_VALUE 1 355 #define SI32_RTC_B_CONTROL_HSMDEN_ENABLED_U32 \ 356 (SI32_RTC_B_CONTROL_HSMDEN_ENABLED_VALUE << SI32_RTC_B_CONTROL_HSMDEN_SHIFT) 357 358 #define SI32_RTC_B_CONTROL_LRDYF_MASK 0x00000100 359 #define SI32_RTC_B_CONTROL_LRDYF_SHIFT 8 360 // The load capacitance is currently stepping. 361 #define SI32_RTC_B_CONTROL_LRDYF_NOT_SET_VALUE 0 362 #define SI32_RTC_B_CONTROL_LRDYF_NOT_SET_U32 \ 363 (SI32_RTC_B_CONTROL_LRDYF_NOT_SET_VALUE << SI32_RTC_B_CONTROL_LRDYF_SHIFT) 364 // The load capacitance has reached its programmed value. 365 #define SI32_RTC_B_CONTROL_LRDYF_SET_VALUE 1 366 #define SI32_RTC_B_CONTROL_LRDYF_SET_U32 \ 367 (SI32_RTC_B_CONTROL_LRDYF_SET_VALUE << SI32_RTC_B_CONTROL_LRDYF_SHIFT) 368 369 370 371 struct SI32_RTC_B_ALARM0_Struct 372 { 373 union 374 { 375 struct 376 { 377 // RTC Alarm 0 378 volatile uint32_t ALARM0_BITS; 379 }; 380 volatile uint32_t U32; 381 }; 382 }; 383 384 #define SI32_RTC_B_ALARM0_ALARM0_MASK 0xFFFFFFFF 385 #define SI32_RTC_B_ALARM0_ALARM0_SHIFT 0 386 387 388 389 struct SI32_RTC_B_ALARM1_Struct 390 { 391 union 392 { 393 struct 394 { 395 // RTC Alarm 1 396 volatile uint32_t ALARM1_BITS; 397 }; 398 volatile uint32_t U32; 399 }; 400 }; 401 402 #define SI32_RTC_B_ALARM1_ALARM1_MASK 0xFFFFFFFF 403 #define SI32_RTC_B_ALARM1_ALARM1_SHIFT 0 404 405 406 407 struct SI32_RTC_B_ALARM2_Struct 408 { 409 union 410 { 411 struct 412 { 413 // RTC Alarm 2 414 volatile uint32_t ALARM2_BITS; 415 }; 416 volatile uint32_t U32; 417 }; 418 }; 419 420 #define SI32_RTC_B_ALARM2_ALARM2_MASK 0xFFFFFFFF 421 #define SI32_RTC_B_ALARM2_ALARM2_SHIFT 0 422 423 424 425 struct SI32_RTC_B_SETCAP_Struct 426 { 427 union 428 { 429 struct 430 { 431 // RTC Timer Set/Capture Value 432 volatile uint32_t SETCAP_BITS; 433 }; 434 volatile uint32_t U32; 435 }; 436 }; 437 438 #define SI32_RTC_B_SETCAP_SETCAP_MASK 0xFFFFFFFF 439 #define SI32_RTC_B_SETCAP_SETCAP_SHIFT 0 440 441 442 443 struct SI32_RTC_B_LFOCONTROL_Struct 444 { 445 union 446 { 447 struct 448 { 449 uint32_t reserved0: 30; 450 // Low Frequency Oscillator Output Enable 451 volatile uint32_t LFOOEN: 1; 452 // Low Frequency Oscillator Enable 453 volatile uint32_t LFOSCEN: 1; 454 }; 455 volatile uint32_t U32; 456 }; 457 }; 458 459 #define SI32_RTC_B_LFOCONTROL_LFOOEN_MASK 0x40000000 460 #define SI32_RTC_B_LFOCONTROL_LFOOEN_SHIFT 30 461 // Disable the Low Frequency Oscillator output to internal modules. 462 #define SI32_RTC_B_LFOCONTROL_LFOOEN_DISABLED_VALUE 0 463 #define SI32_RTC_B_LFOCONTROL_LFOOEN_DISABLED_U32 \ 464 (SI32_RTC_B_LFOCONTROL_LFOOEN_DISABLED_VALUE << SI32_RTC_B_LFOCONTROL_LFOOEN_SHIFT) 465 // Enable the Low Frequency Oscillator output to internal module. 466 #define SI32_RTC_B_LFOCONTROL_LFOOEN_ENABLED_VALUE 1 467 #define SI32_RTC_B_LFOCONTROL_LFOOEN_ENABLED_U32 \ 468 (SI32_RTC_B_LFOCONTROL_LFOOEN_ENABLED_VALUE << SI32_RTC_B_LFOCONTROL_LFOOEN_SHIFT) 469 470 #define SI32_RTC_B_LFOCONTROL_LFOSCEN_MASK 0x80000000 471 #define SI32_RTC_B_LFOCONTROL_LFOSCEN_SHIFT 31 472 // Disable the Low Frequency Oscillator (LFOSCn). 473 #define SI32_RTC_B_LFOCONTROL_LFOSCEN_DISABLED_VALUE 0U 474 #define SI32_RTC_B_LFOCONTROL_LFOSCEN_DISABLED_U32 \ 475 (SI32_RTC_B_LFOCONTROL_LFOSCEN_DISABLED_VALUE << SI32_RTC_B_LFOCONTROL_LFOSCEN_SHIFT) 476 // Enable the Low Frequency Oscillator (LFOSCn). 477 #define SI32_RTC_B_LFOCONTROL_LFOSCEN_ENABLED_VALUE 1U 478 #define SI32_RTC_B_LFOCONTROL_LFOSCEN_ENABLED_U32 \ 479 (SI32_RTC_B_LFOCONTROL_LFOSCEN_ENABLED_VALUE << SI32_RTC_B_LFOCONTROL_LFOSCEN_SHIFT) 480 481 482 483 typedef struct SI32_RTC_B_Struct 484 { 485 struct SI32_RTC_B_CONFIG_Struct CONFIG ; // Base Address + 0x0 486 volatile uint32_t CONFIG_SET; 487 volatile uint32_t CONFIG_CLR; 488 uint32_t reserved0; 489 struct SI32_RTC_B_CONTROL_Struct CONTROL ; // Base Address + 0x10 490 volatile uint32_t CONTROL_SET; 491 volatile uint32_t CONTROL_CLR; 492 uint32_t reserved1; 493 struct SI32_RTC_B_ALARM0_Struct ALARM0 ; // Base Address + 0x20 494 uint32_t reserved2; 495 uint32_t reserved3; 496 uint32_t reserved4; 497 struct SI32_RTC_B_ALARM1_Struct ALARM1 ; // Base Address + 0x30 498 uint32_t reserved5; 499 uint32_t reserved6; 500 uint32_t reserved7; 501 struct SI32_RTC_B_ALARM2_Struct ALARM2 ; // Base Address + 0x40 502 uint32_t reserved8; 503 uint32_t reserved9; 504 uint32_t reserved10; 505 struct SI32_RTC_B_SETCAP_Struct SETCAP ; // Base Address + 0x50 506 uint32_t reserved11; 507 uint32_t reserved12; 508 uint32_t reserved13; 509 struct SI32_RTC_B_LFOCONTROL_Struct LFOCONTROL ; // Base Address + 0x60 510 uint32_t reserved14; 511 uint32_t reserved15; 512 uint32_t reserved16; 513 uint32_t reserved17[4]; 514 uint32_t reserved18[4]; 515 } SI32_RTC_B_Type; 516 517 #ifdef __cplusplus 518 } 519 #endif 520 521 #endif // __SI32_RTC_B_REGISTERS_H__ 522 523 //-eof-------------------------------------------------------------------------- 524 525
