1 //----------------------------------------------------------------------------- 2 // Copyright 2012 (c) Silicon Laboratories Inc. 3 // 4 // SPDX-License-Identifier: Zlib 5 // 6 // This siHAL software is provided 'as-is', without any express or implied 7 // warranty. In no event will the authors be held liable for any damages 8 // arising from the use of this software. 9 // 10 // Permission is granted to anyone to use this software for any purpose, 11 // including commercial applications, and to alter it and redistribute it 12 // freely, subject to the following restrictions: 13 // 14 // 1. The origin of this software must not be misrepresented; you must not 15 // claim that you wrote the original software. If you use this software 16 // in a product, an acknowledgment in the product documentation would be 17 // appreciated but is not required. 18 // 2. Altered source versions must be plainly marked as such, and must not be 19 // misrepresented as being the original software. 20 // 3. This notice may not be removed or altered from any source distribution. 21 //----------------------------------------------------------------------------- 22 // 23 // Script: 0.61 24 // Version: 1 25 26 #ifndef __SI32_RTC_A_REGISTERS_H__ 27 #define __SI32_RTC_A_REGISTERS_H__ 28 29 #include <stdint.h> 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 struct SI32_RTC_A_CONFIG_Struct 36 { 37 union 38 { 39 struct 40 { 41 // Alarm 0 Automatic Reset Enable 42 volatile uint32_t ALM0AREN: 1; 43 // RTC Timer Run Control 44 volatile uint32_t RUN: 1; 45 // Missing Clock Detector Enable 46 volatile uint32_t MCLKEN: 1; 47 // Automatic Crystal Load Capacitance Stepping Enable 48 volatile uint32_t ASEN: 1; 49 // Load Capacitance Value 50 volatile uint32_t RTCLC: 4; 51 uint32_t reserved0: 8; 52 // Bias Doubler Enable 53 volatile uint32_t BDEN: 1; 54 // Crystal Oscillator Enable 55 volatile uint32_t CRYSEN: 1; 56 // Automatic Gain Control Enable 57 volatile uint32_t AGCEN: 1; 58 uint32_t reserved1: 5; 59 // Alarm 0 Enable 60 volatile uint32_t ALM0EN: 1; 61 // Alarm 1 Enable 62 volatile uint32_t ALM1EN: 1; 63 // Alarm 2 Enable 64 volatile uint32_t ALM2EN: 1; 65 uint32_t reserved2: 2; 66 // RTC0 External Output Enable 67 volatile uint32_t RTCOEN: 1; 68 // RTC Timer Clock Select 69 volatile uint32_t CLKSEL: 1; 70 // RTC Timer Enable 71 volatile uint32_t RTCEN: 1; 72 }; 73 volatile uint32_t U32; 74 }; 75 }; 76 77 #define SI32_RTC_A_CONFIG_ALM0AREN_MASK 0x00000001 78 #define SI32_RTC_A_CONFIG_ALM0AREN_SHIFT 0 79 // Disable the Alarm 0 automatic reset. 80 #define SI32_RTC_A_CONFIG_ALM0AREN_DISABLED_VALUE 0 81 #define SI32_RTC_A_CONFIG_ALM0AREN_DISABLED_U32 \ 82 (SI32_RTC_A_CONFIG_ALM0AREN_DISABLED_VALUE << SI32_RTC_A_CONFIG_ALM0AREN_SHIFT) 83 // Enable the Alarm 0 automatic reset. 84 #define SI32_RTC_A_CONFIG_ALM0AREN_ENABLED_VALUE 1 85 #define SI32_RTC_A_CONFIG_ALM0AREN_ENABLED_U32 \ 86 (SI32_RTC_A_CONFIG_ALM0AREN_ENABLED_VALUE << SI32_RTC_A_CONFIG_ALM0AREN_SHIFT) 87 88 #define SI32_RTC_A_CONFIG_RUN_MASK 0x00000002 89 #define SI32_RTC_A_CONFIG_RUN_SHIFT 1 90 // Stop the RTC timer. 91 #define SI32_RTC_A_CONFIG_RUN_STOP_VALUE 0 92 #define SI32_RTC_A_CONFIG_RUN_STOP_U32 \ 93 (SI32_RTC_A_CONFIG_RUN_STOP_VALUE << SI32_RTC_A_CONFIG_RUN_SHIFT) 94 // Start the RTC timer running. 95 #define SI32_RTC_A_CONFIG_RUN_START_VALUE 1 96 #define SI32_RTC_A_CONFIG_RUN_START_U32 \ 97 (SI32_RTC_A_CONFIG_RUN_START_VALUE << SI32_RTC_A_CONFIG_RUN_SHIFT) 98 99 #define SI32_RTC_A_CONFIG_MCLKEN_MASK 0x00000004 100 #define SI32_RTC_A_CONFIG_MCLKEN_SHIFT 2 101 // Disable the missing clock detector. 102 #define SI32_RTC_A_CONFIG_MCLKEN_DISABLED_VALUE 0 103 #define SI32_RTC_A_CONFIG_MCLKEN_DISABLED_U32 \ 104 (SI32_RTC_A_CONFIG_MCLKEN_DISABLED_VALUE << SI32_RTC_A_CONFIG_MCLKEN_SHIFT) 105 // Enable the missing clock detector. If the missing clock detector triggers, it 106 // will generate an RTC Fail event. 107 #define SI32_RTC_A_CONFIG_MCLKEN_ENABLED_VALUE 1 108 #define SI32_RTC_A_CONFIG_MCLKEN_ENABLED_U32 \ 109 (SI32_RTC_A_CONFIG_MCLKEN_ENABLED_VALUE << SI32_RTC_A_CONFIG_MCLKEN_SHIFT) 110 111 #define SI32_RTC_A_CONFIG_ASEN_MASK 0x00000008 112 #define SI32_RTC_A_CONFIG_ASEN_SHIFT 3 113 // Disable automatic load capacitance stepping. 114 #define SI32_RTC_A_CONFIG_ASEN_DISABLED_VALUE 0 115 #define SI32_RTC_A_CONFIG_ASEN_DISABLED_U32 \ 116 (SI32_RTC_A_CONFIG_ASEN_DISABLED_VALUE << SI32_RTC_A_CONFIG_ASEN_SHIFT) 117 // Enable automatic load capacitance stepping. 118 #define SI32_RTC_A_CONFIG_ASEN_ENABLED_VALUE 1 119 #define SI32_RTC_A_CONFIG_ASEN_ENABLED_U32 \ 120 (SI32_RTC_A_CONFIG_ASEN_ENABLED_VALUE << SI32_RTC_A_CONFIG_ASEN_SHIFT) 121 122 #define SI32_RTC_A_CONFIG_RTCLC_MASK 0x000000F0 123 #define SI32_RTC_A_CONFIG_RTCLC_SHIFT 4 124 125 #define SI32_RTC_A_CONFIG_BDEN_MASK 0x00010000 126 #define SI32_RTC_A_CONFIG_BDEN_SHIFT 16 127 // Disable the bias doubler, saving power. 128 #define SI32_RTC_A_CONFIG_BDEN_DISABLED_VALUE 0 129 #define SI32_RTC_A_CONFIG_BDEN_DISABLED_U32 \ 130 (SI32_RTC_A_CONFIG_BDEN_DISABLED_VALUE << SI32_RTC_A_CONFIG_BDEN_SHIFT) 131 // Enable the bias doubler. 132 #define SI32_RTC_A_CONFIG_BDEN_ENABLED_VALUE 1 133 #define SI32_RTC_A_CONFIG_BDEN_ENABLED_U32 \ 134 (SI32_RTC_A_CONFIG_BDEN_ENABLED_VALUE << SI32_RTC_A_CONFIG_BDEN_SHIFT) 135 136 #define SI32_RTC_A_CONFIG_CRYSEN_MASK 0x00020000 137 #define SI32_RTC_A_CONFIG_CRYSEN_SHIFT 17 138 // Disable the crystal oscillator circuitry. 139 #define SI32_RTC_A_CONFIG_CRYSEN_DISABLED_VALUE 0 140 #define SI32_RTC_A_CONFIG_CRYSEN_DISABLED_U32 \ 141 (SI32_RTC_A_CONFIG_CRYSEN_DISABLED_VALUE << SI32_RTC_A_CONFIG_CRYSEN_SHIFT) 142 // Enable the crystal oscillator circuitry. 143 #define SI32_RTC_A_CONFIG_CRYSEN_ENABLED_VALUE 1 144 #define SI32_RTC_A_CONFIG_CRYSEN_ENABLED_U32 \ 145 (SI32_RTC_A_CONFIG_CRYSEN_ENABLED_VALUE << SI32_RTC_A_CONFIG_CRYSEN_SHIFT) 146 147 #define SI32_RTC_A_CONFIG_AGCEN_MASK 0x00040000 148 #define SI32_RTC_A_CONFIG_AGCEN_SHIFT 18 149 // Disable automatic gain control. 150 #define SI32_RTC_A_CONFIG_AGCEN_DISABLED_VALUE 0 151 #define SI32_RTC_A_CONFIG_AGCEN_DISABLED_U32 \ 152 (SI32_RTC_A_CONFIG_AGCEN_DISABLED_VALUE << SI32_RTC_A_CONFIG_AGCEN_SHIFT) 153 // Enable automatic gain control, saving power. 154 #define SI32_RTC_A_CONFIG_AGCEN_ENABLED_VALUE 1 155 #define SI32_RTC_A_CONFIG_AGCEN_ENABLED_U32 \ 156 (SI32_RTC_A_CONFIG_AGCEN_ENABLED_VALUE << SI32_RTC_A_CONFIG_AGCEN_SHIFT) 157 158 #define SI32_RTC_A_CONFIG_ALM0EN_MASK 0x01000000 159 #define SI32_RTC_A_CONFIG_ALM0EN_SHIFT 24 160 // Disable RTC Alarm 0. 161 #define SI32_RTC_A_CONFIG_ALM0EN_DISABLED_VALUE 0 162 #define SI32_RTC_A_CONFIG_ALM0EN_DISABLED_U32 \ 163 (SI32_RTC_A_CONFIG_ALM0EN_DISABLED_VALUE << SI32_RTC_A_CONFIG_ALM0EN_SHIFT) 164 // Enable RTC Alarm 0 and Alarm 0 Interrupt. 165 #define SI32_RTC_A_CONFIG_ALM0EN_ENABLED_VALUE 1 166 #define SI32_RTC_A_CONFIG_ALM0EN_ENABLED_U32 \ 167 (SI32_RTC_A_CONFIG_ALM0EN_ENABLED_VALUE << SI32_RTC_A_CONFIG_ALM0EN_SHIFT) 168 169 #define SI32_RTC_A_CONFIG_ALM1EN_MASK 0x02000000 170 #define SI32_RTC_A_CONFIG_ALM1EN_SHIFT 25 171 // Disable RTC Alarm 1. 172 #define SI32_RTC_A_CONFIG_ALM1EN_DISABLED_VALUE 0 173 #define SI32_RTC_A_CONFIG_ALM1EN_DISABLED_U32 \ 174 (SI32_RTC_A_CONFIG_ALM1EN_DISABLED_VALUE << SI32_RTC_A_CONFIG_ALM1EN_SHIFT) 175 // Enable RTC Alarm 1 and Alarm 1 Interrupt. 176 #define SI32_RTC_A_CONFIG_ALM1EN_ENABLED_VALUE 1 177 #define SI32_RTC_A_CONFIG_ALM1EN_ENABLED_U32 \ 178 (SI32_RTC_A_CONFIG_ALM1EN_ENABLED_VALUE << SI32_RTC_A_CONFIG_ALM1EN_SHIFT) 179 180 #define SI32_RTC_A_CONFIG_ALM2EN_MASK 0x04000000 181 #define SI32_RTC_A_CONFIG_ALM2EN_SHIFT 26 182 // Disable RTC Alarm 2. 183 #define SI32_RTC_A_CONFIG_ALM2EN_DISABLED_VALUE 0 184 #define SI32_RTC_A_CONFIG_ALM2EN_DISABLED_U32 \ 185 (SI32_RTC_A_CONFIG_ALM2EN_DISABLED_VALUE << SI32_RTC_A_CONFIG_ALM2EN_SHIFT) 186 // Enable RTC Alarm 2 and Alarm 2 Interrupt. 187 #define SI32_RTC_A_CONFIG_ALM2EN_ENABLED_VALUE 1 188 #define SI32_RTC_A_CONFIG_ALM2EN_ENABLED_U32 \ 189 (SI32_RTC_A_CONFIG_ALM2EN_ENABLED_VALUE << SI32_RTC_A_CONFIG_ALM2EN_SHIFT) 190 191 #define SI32_RTC_A_CONFIG_RTCOEN_MASK 0x20000000 192 #define SI32_RTC_A_CONFIG_RTCOEN_SHIFT 29 193 // Disable the external RTCnOSC output. 194 #define SI32_RTC_A_CONFIG_RTCOEN_DISABLED_VALUE 0 195 #define SI32_RTC_A_CONFIG_RTCOEN_DISABLED_U32 \ 196 (SI32_RTC_A_CONFIG_RTCOEN_DISABLED_VALUE << SI32_RTC_A_CONFIG_RTCOEN_SHIFT) 197 // Enable the external RTCnOSC output. 198 #define SI32_RTC_A_CONFIG_RTCOEN_ENABLED_VALUE 1 199 #define SI32_RTC_A_CONFIG_RTCOEN_ENABLED_U32 \ 200 (SI32_RTC_A_CONFIG_RTCOEN_ENABLED_VALUE << SI32_RTC_A_CONFIG_RTCOEN_SHIFT) 201 202 #define SI32_RTC_A_CONFIG_CLKSEL_MASK 0x40000000 203 #define SI32_RTC_A_CONFIG_CLKSEL_SHIFT 30 204 // Select the External Crystal or External CMOS Clock as the RTC Timer clock 205 // (RTCnTCLK) source. 206 #define SI32_RTC_A_CONFIG_CLKSEL_RTCNOSC_VALUE 0 207 #define SI32_RTC_A_CONFIG_CLKSEL_RTCNOSC_U32 \ 208 (SI32_RTC_A_CONFIG_CLKSEL_RTCNOSC_VALUE << SI32_RTC_A_CONFIG_CLKSEL_SHIFT) 209 // Select the Low Frequency Oscillator as the RTC Timer clock (RTCnTCLK) source. 210 #define SI32_RTC_A_CONFIG_CLKSEL_LFOSCN_VALUE 1 211 #define SI32_RTC_A_CONFIG_CLKSEL_LFOSCN_U32 \ 212 (SI32_RTC_A_CONFIG_CLKSEL_LFOSCN_VALUE << SI32_RTC_A_CONFIG_CLKSEL_SHIFT) 213 214 #define SI32_RTC_A_CONFIG_RTCEN_MASK 0x80000000 215 #define SI32_RTC_A_CONFIG_RTCEN_SHIFT 31 216 // Disable the RTC timer. 217 #define SI32_RTC_A_CONFIG_RTCEN_DISABLED_VALUE 0U 218 #define SI32_RTC_A_CONFIG_RTCEN_DISABLED_U32 \ 219 (SI32_RTC_A_CONFIG_RTCEN_DISABLED_VALUE << SI32_RTC_A_CONFIG_RTCEN_SHIFT) 220 // Enable the RTC timer. 221 #define SI32_RTC_A_CONFIG_RTCEN_ENABLED_VALUE 1U 222 #define SI32_RTC_A_CONFIG_RTCEN_ENABLED_U32 \ 223 (SI32_RTC_A_CONFIG_RTCEN_ENABLED_VALUE << SI32_RTC_A_CONFIG_RTCEN_SHIFT) 224 225 226 227 struct SI32_RTC_A_CONTROL_Struct 228 { 229 union 230 { 231 struct 232 { 233 // Alarm 0 Interrupt Flag 234 volatile uint32_t ALM0I: 1; 235 // Alarm 1 Interrupt Flag 236 volatile uint32_t ALM1I: 1; 237 // Alarm 2 Interrupt Flag 238 volatile uint32_t ALM2I: 1; 239 // RTC Timer Capture 240 volatile uint32_t TMRCAP: 1; 241 // RTC Timer Set 242 volatile uint32_t TMRSET: 1; 243 // RTC External Oscillator Valid Flag 244 volatile uint32_t CLKVF: 1; 245 // RTC Oscillator Fail Interrupt Flag 246 volatile uint32_t OSCFI: 1; 247 // RTC High Speed Mode Enable 248 volatile uint32_t HSMDEN: 1; 249 // RTC Load Capacitance Ready Flag 250 volatile uint32_t LRDYF: 1; 251 uint32_t reserved0: 23; 252 }; 253 volatile uint32_t U32; 254 }; 255 }; 256 257 #define SI32_RTC_A_CONTROL_ALM0I_MASK 0x00000001 258 #define SI32_RTC_A_CONTROL_ALM0I_SHIFT 0 259 // Alarm 0 event has not occurred. 260 #define SI32_RTC_A_CONTROL_ALM0I_NOT_SET_VALUE 0 261 #define SI32_RTC_A_CONTROL_ALM0I_NOT_SET_U32 \ 262 (SI32_RTC_A_CONTROL_ALM0I_NOT_SET_VALUE << SI32_RTC_A_CONTROL_ALM0I_SHIFT) 263 // Alarm 0 event occurred. 264 #define SI32_RTC_A_CONTROL_ALM0I_SET_VALUE 1 265 #define SI32_RTC_A_CONTROL_ALM0I_SET_U32 \ 266 (SI32_RTC_A_CONTROL_ALM0I_SET_VALUE << SI32_RTC_A_CONTROL_ALM0I_SHIFT) 267 268 #define SI32_RTC_A_CONTROL_ALM1I_MASK 0x00000002 269 #define SI32_RTC_A_CONTROL_ALM1I_SHIFT 1 270 // Alarm 1 event has not occurred. 271 #define SI32_RTC_A_CONTROL_ALM1I_NOT_SET_VALUE 0 272 #define SI32_RTC_A_CONTROL_ALM1I_NOT_SET_U32 \ 273 (SI32_RTC_A_CONTROL_ALM1I_NOT_SET_VALUE << SI32_RTC_A_CONTROL_ALM1I_SHIFT) 274 // Alarm 1 event occurred. 275 #define SI32_RTC_A_CONTROL_ALM1I_SET_VALUE 1 276 #define SI32_RTC_A_CONTROL_ALM1I_SET_U32 \ 277 (SI32_RTC_A_CONTROL_ALM1I_SET_VALUE << SI32_RTC_A_CONTROL_ALM1I_SHIFT) 278 279 #define SI32_RTC_A_CONTROL_ALM2I_MASK 0x00000004 280 #define SI32_RTC_A_CONTROL_ALM2I_SHIFT 2 281 // Alarm 2 event has not occurred. 282 #define SI32_RTC_A_CONTROL_ALM2I_NOT_SET_VALUE 0 283 #define SI32_RTC_A_CONTROL_ALM2I_NOT_SET_U32 \ 284 (SI32_RTC_A_CONTROL_ALM2I_NOT_SET_VALUE << SI32_RTC_A_CONTROL_ALM2I_SHIFT) 285 // Alarm 2 event occurred. 286 #define SI32_RTC_A_CONTROL_ALM2I_SET_VALUE 1 287 #define SI32_RTC_A_CONTROL_ALM2I_SET_U32 \ 288 (SI32_RTC_A_CONTROL_ALM2I_SET_VALUE << SI32_RTC_A_CONTROL_ALM2I_SHIFT) 289 290 #define SI32_RTC_A_CONTROL_TMRCAP_MASK 0x00000008 291 #define SI32_RTC_A_CONTROL_TMRCAP_SHIFT 3 292 // RTC timer capture operation is complete. 293 #define SI32_RTC_A_CONTROL_TMRCAP_NOT_SET_VALUE 0 294 #define SI32_RTC_A_CONTROL_TMRCAP_NOT_SET_U32 \ 295 (SI32_RTC_A_CONTROL_TMRCAP_NOT_SET_VALUE << SI32_RTC_A_CONTROL_TMRCAP_SHIFT) 296 // Start the RTC timer capture. 297 #define SI32_RTC_A_CONTROL_TMRCAP_SET_VALUE 1 298 #define SI32_RTC_A_CONTROL_TMRCAP_SET_U32 \ 299 (SI32_RTC_A_CONTROL_TMRCAP_SET_VALUE << SI32_RTC_A_CONTROL_TMRCAP_SHIFT) 300 301 #define SI32_RTC_A_CONTROL_TMRSET_MASK 0x00000010 302 #define SI32_RTC_A_CONTROL_TMRSET_SHIFT 4 303 // RTC timer set operation is complete. 304 #define SI32_RTC_A_CONTROL_TMRSET_NOT_SET_VALUE 0 305 #define SI32_RTC_A_CONTROL_TMRSET_NOT_SET_U32 \ 306 (SI32_RTC_A_CONTROL_TMRSET_NOT_SET_VALUE << SI32_RTC_A_CONTROL_TMRSET_SHIFT) 307 // Start the RTC timer set. 308 #define SI32_RTC_A_CONTROL_TMRSET_SET_VALUE 1 309 #define SI32_RTC_A_CONTROL_TMRSET_SET_U32 \ 310 (SI32_RTC_A_CONTROL_TMRSET_SET_VALUE << SI32_RTC_A_CONTROL_TMRSET_SHIFT) 311 312 #define SI32_RTC_A_CONTROL_CLKVF_MASK 0x00000020 313 #define SI32_RTC_A_CONTROL_CLKVF_SHIFT 5 314 // External oscillator is not valid. 315 #define SI32_RTC_A_CONTROL_CLKVF_NOT_SET_VALUE 0 316 #define SI32_RTC_A_CONTROL_CLKVF_NOT_SET_U32 \ 317 (SI32_RTC_A_CONTROL_CLKVF_NOT_SET_VALUE << SI32_RTC_A_CONTROL_CLKVF_SHIFT) 318 // External oscillator is valid. 319 #define SI32_RTC_A_CONTROL_CLKVF_SET_VALUE 1 320 #define SI32_RTC_A_CONTROL_CLKVF_SET_U32 \ 321 (SI32_RTC_A_CONTROL_CLKVF_SET_VALUE << SI32_RTC_A_CONTROL_CLKVF_SHIFT) 322 323 #define SI32_RTC_A_CONTROL_OSCFI_MASK 0x00000040 324 #define SI32_RTC_A_CONTROL_OSCFI_SHIFT 6 325 // Oscillator is running. 326 #define SI32_RTC_A_CONTROL_OSCFI_NOT_SET_VALUE 0 327 #define SI32_RTC_A_CONTROL_OSCFI_NOT_SET_U32 \ 328 (SI32_RTC_A_CONTROL_OSCFI_NOT_SET_VALUE << SI32_RTC_A_CONTROL_OSCFI_SHIFT) 329 // Oscillator has failed. 330 #define SI32_RTC_A_CONTROL_OSCFI_SET_VALUE 1 331 #define SI32_RTC_A_CONTROL_OSCFI_SET_U32 \ 332 (SI32_RTC_A_CONTROL_OSCFI_SET_VALUE << SI32_RTC_A_CONTROL_OSCFI_SHIFT) 333 334 #define SI32_RTC_A_CONTROL_HSMDEN_MASK 0x00000080 335 #define SI32_RTC_A_CONTROL_HSMDEN_SHIFT 7 336 // Disable high speed mode. (AHBCLK < 4x RTCnTCLK) 337 #define SI32_RTC_A_CONTROL_HSMDEN_DISABLED_VALUE 0 338 #define SI32_RTC_A_CONTROL_HSMDEN_DISABLED_U32 \ 339 (SI32_RTC_A_CONTROL_HSMDEN_DISABLED_VALUE << SI32_RTC_A_CONTROL_HSMDEN_SHIFT) 340 // Enable high speed mode. (AHBCLK >= 4x RTCnTCLK) 341 #define SI32_RTC_A_CONTROL_HSMDEN_ENABLED_VALUE 1 342 #define SI32_RTC_A_CONTROL_HSMDEN_ENABLED_U32 \ 343 (SI32_RTC_A_CONTROL_HSMDEN_ENABLED_VALUE << SI32_RTC_A_CONTROL_HSMDEN_SHIFT) 344 345 #define SI32_RTC_A_CONTROL_LRDYF_MASK 0x00000100 346 #define SI32_RTC_A_CONTROL_LRDYF_SHIFT 8 347 // The load capacitance is currently stepping. 348 #define SI32_RTC_A_CONTROL_LRDYF_NOT_SET_VALUE 0 349 #define SI32_RTC_A_CONTROL_LRDYF_NOT_SET_U32 \ 350 (SI32_RTC_A_CONTROL_LRDYF_NOT_SET_VALUE << SI32_RTC_A_CONTROL_LRDYF_SHIFT) 351 // The load capacitance has reached its programmed value. 352 #define SI32_RTC_A_CONTROL_LRDYF_SET_VALUE 1 353 #define SI32_RTC_A_CONTROL_LRDYF_SET_U32 \ 354 (SI32_RTC_A_CONTROL_LRDYF_SET_VALUE << SI32_RTC_A_CONTROL_LRDYF_SHIFT) 355 356 357 358 struct SI32_RTC_A_ALARM0_Struct 359 { 360 union 361 { 362 struct 363 { 364 // RTC Alarm 0 365 volatile uint32_t ALARM0_BITS; 366 }; 367 volatile uint32_t U32; 368 }; 369 }; 370 371 #define SI32_RTC_A_ALARM0_ALARM0_MASK 0xFFFFFFFF 372 #define SI32_RTC_A_ALARM0_ALARM0_SHIFT 0 373 374 375 376 struct SI32_RTC_A_ALARM1_Struct 377 { 378 union 379 { 380 struct 381 { 382 // RTC Alarm 1 383 volatile uint32_t ALARM1_BITS; 384 }; 385 volatile uint32_t U32; 386 }; 387 }; 388 389 #define SI32_RTC_A_ALARM1_ALARM1_MASK 0xFFFFFFFF 390 #define SI32_RTC_A_ALARM1_ALARM1_SHIFT 0 391 392 393 394 struct SI32_RTC_A_ALARM2_Struct 395 { 396 union 397 { 398 struct 399 { 400 // RTC Alarm 2 401 volatile uint32_t ALARM2_BITS; 402 }; 403 volatile uint32_t U32; 404 }; 405 }; 406 407 #define SI32_RTC_A_ALARM2_ALARM2_MASK 0xFFFFFFFF 408 #define SI32_RTC_A_ALARM2_ALARM2_SHIFT 0 409 410 411 412 struct SI32_RTC_A_SETCAP_Struct 413 { 414 union 415 { 416 struct 417 { 418 // RTC Timer Set/Capture Value 419 volatile uint32_t SETCAP_BITS; 420 }; 421 volatile uint32_t U32; 422 }; 423 }; 424 425 #define SI32_RTC_A_SETCAP_SETCAP_MASK 0xFFFFFFFF 426 #define SI32_RTC_A_SETCAP_SETCAP_SHIFT 0 427 428 429 430 struct SI32_RTC_A_LFOCONTROL_Struct 431 { 432 union 433 { 434 struct 435 { 436 uint32_t reserved0: 31; 437 // Low Frequency Oscillator Enable 438 volatile uint32_t LFOSCEN: 1; 439 }; 440 volatile uint32_t U32; 441 }; 442 }; 443 444 #define SI32_RTC_A_LFOCONTROL_LFOSCEN_MASK 0x80000000 445 #define SI32_RTC_A_LFOCONTROL_LFOSCEN_SHIFT 31 446 // Disable the Low Frequency Oscillator (LFOSCn). 447 #define SI32_RTC_A_LFOCONTROL_LFOSCEN_DISABLED_VALUE 0U 448 #define SI32_RTC_A_LFOCONTROL_LFOSCEN_DISABLED_U32 \ 449 (SI32_RTC_A_LFOCONTROL_LFOSCEN_DISABLED_VALUE << SI32_RTC_A_LFOCONTROL_LFOSCEN_SHIFT) 450 // Enable the Low Frequency Oscillator (LFOSCn). 451 #define SI32_RTC_A_LFOCONTROL_LFOSCEN_ENABLED_VALUE 1U 452 #define SI32_RTC_A_LFOCONTROL_LFOSCEN_ENABLED_U32 \ 453 (SI32_RTC_A_LFOCONTROL_LFOSCEN_ENABLED_VALUE << SI32_RTC_A_LFOCONTROL_LFOSCEN_SHIFT) 454 455 456 457 typedef struct SI32_RTC_A_Struct 458 { 459 struct SI32_RTC_A_CONFIG_Struct CONFIG ; // Base Address + 0x0 460 volatile uint32_t CONFIG_SET; 461 volatile uint32_t CONFIG_CLR; 462 uint32_t reserved0; 463 struct SI32_RTC_A_CONTROL_Struct CONTROL ; // Base Address + 0x10 464 volatile uint32_t CONTROL_SET; 465 volatile uint32_t CONTROL_CLR; 466 uint32_t reserved1; 467 struct SI32_RTC_A_ALARM0_Struct ALARM0 ; // Base Address + 0x20 468 uint32_t reserved2; 469 uint32_t reserved3; 470 uint32_t reserved4; 471 struct SI32_RTC_A_ALARM1_Struct ALARM1 ; // Base Address + 0x30 472 uint32_t reserved5; 473 uint32_t reserved6; 474 uint32_t reserved7; 475 struct SI32_RTC_A_ALARM2_Struct ALARM2 ; // Base Address + 0x40 476 uint32_t reserved8; 477 uint32_t reserved9; 478 uint32_t reserved10; 479 struct SI32_RTC_A_SETCAP_Struct SETCAP ; // Base Address + 0x50 480 uint32_t reserved11; 481 uint32_t reserved12; 482 uint32_t reserved13; 483 struct SI32_RTC_A_LFOCONTROL_Struct LFOCONTROL ; // Base Address + 0x60 484 uint32_t reserved14; 485 uint32_t reserved15; 486 uint32_t reserved16; 487 uint32_t reserved17[4]; 488 uint32_t reserved18[4]; 489 } SI32_RTC_A_Type; 490 491 #ifdef __cplusplus 492 } 493 #endif 494 495 #endif // __SI32_RTC_A_REGISTERS_H__ 496 497 //-eof-------------------------------------------------------------------------- 498 499
