1 //----------------------------------------------------------------------------- 2 // Copyright 2013 (c) Silicon Laboratories Inc. 3 // 4 // SPDX-License-Identifier: Zlib 5 // 6 // This siHAL software is provided 'as-is', without any express or implied 7 // warranty. In no event will the authors be held liable for any damages 8 // arising from the use of this software. 9 // 10 // Permission is granted to anyone to use this software for any purpose, 11 // including commercial applications, and to alter it and redistribute it 12 // freely, subject to the following restrictions: 13 // 14 // 1. The origin of this software must not be misrepresented; you must not 15 // claim that you wrote the original software. If you use this software 16 // in a product, an acknowledgment in the product documentation would be 17 // appreciated but is not required. 18 // 2. Altered source versions must be plainly marked as such, and must not be 19 // misrepresented as being the original software. 20 // 3. This notice may not be removed or altered from any source distribution. 21 //----------------------------------------------------------------------------- 22 // 23 // Script: 0.62 24 // Version: 1 25 26 #ifndef __SI32_PLL_A_REGISTERS_H__ 27 #define __SI32_PLL_A_REGISTERS_H__ 28 29 #include <stdint.h> 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 struct SI32_PLL_A_DIVIDER_Struct 36 { 37 union 38 { 39 struct 40 { 41 // M Divider Value 42 volatile uint32_t M: 12; 43 uint32_t reserved0: 4; 44 // N Divider Value 45 volatile uint32_t N: 12; 46 uint32_t reserved1: 4; 47 }; 48 volatile uint32_t U32; 49 }; 50 }; 51 52 #define SI32_PLL_A_DIVIDER_M_MASK 0x00000FFF 53 #define SI32_PLL_A_DIVIDER_M_SHIFT 0 54 55 #define SI32_PLL_A_DIVIDER_N_MASK 0x0FFF0000 56 #define SI32_PLL_A_DIVIDER_N_SHIFT 16 57 58 59 60 struct SI32_PLL_A_CONTROL_Struct 61 { 62 union 63 { 64 struct 65 { 66 // CAL Saturation (Low) Flag 67 volatile uint32_t LLMTF: 1; 68 // CAL Saturation (High) Flag 69 volatile uint32_t HLMTF: 1; 70 // Phase-Lock and Frequency-Lock Locked Interrupt Flag 71 volatile uint32_t LCKI: 1; 72 uint32_t reserved0: 6; 73 // Limit Interrupt Enable 74 volatile uint32_t LMTIEN: 1; 75 // Locked Interrupt Enable 76 volatile uint32_t LCKIEN: 1; 77 // Lock Interrupt Polarity 78 volatile uint32_t LCKPOL: 1; 79 uint32_t reserved1: 4; 80 // Reference Clock Selection Control 81 volatile uint32_t REFSEL: 3; 82 uint32_t reserved2: 1; 83 // Lock Threshold Control 84 volatile uint32_t LOCKTH: 2; 85 uint32_t reserved3: 4; 86 // DCO Output Updates Stall 87 volatile uint32_t STALL: 1; 88 uint32_t reserved4: 1; 89 // Dithering Enable 90 volatile uint32_t DITHEN: 1; 91 // Edge Lock Select 92 volatile uint32_t EDGSEL: 1; 93 // PLL Output Mode 94 volatile uint32_t OUTMD: 2; 95 }; 96 volatile uint32_t U32; 97 }; 98 }; 99 100 #define SI32_PLL_A_CONTROL_LLMTF_MASK 0x00000001 101 #define SI32_PLL_A_CONTROL_LLMTF_SHIFT 0 102 // DCO period is not saturated low. 103 #define SI32_PLL_A_CONTROL_LLMTF_NOT_SET_VALUE 0 104 #define SI32_PLL_A_CONTROL_LLMTF_NOT_SET_U32 \ 105 (SI32_PLL_A_CONTROL_LLMTF_NOT_SET_VALUE << SI32_PLL_A_CONTROL_LLMTF_SHIFT) 106 // DCO period is saturated low. 107 #define SI32_PLL_A_CONTROL_LLMTF_SET_VALUE 1 108 #define SI32_PLL_A_CONTROL_LLMTF_SET_U32 \ 109 (SI32_PLL_A_CONTROL_LLMTF_SET_VALUE << SI32_PLL_A_CONTROL_LLMTF_SHIFT) 110 111 #define SI32_PLL_A_CONTROL_HLMTF_MASK 0x00000002 112 #define SI32_PLL_A_CONTROL_HLMTF_SHIFT 1 113 // DCO period is not saturated high. 114 #define SI32_PLL_A_CONTROL_HLMTF_NOT_SET_VALUE 0 115 #define SI32_PLL_A_CONTROL_HLMTF_NOT_SET_U32 \ 116 (SI32_PLL_A_CONTROL_HLMTF_NOT_SET_VALUE << SI32_PLL_A_CONTROL_HLMTF_SHIFT) 117 // DCO period is saturated high. 118 #define SI32_PLL_A_CONTROL_HLMTF_SET_VALUE 1 119 #define SI32_PLL_A_CONTROL_HLMTF_SET_U32 \ 120 (SI32_PLL_A_CONTROL_HLMTF_SET_VALUE << SI32_PLL_A_CONTROL_HLMTF_SHIFT) 121 122 #define SI32_PLL_A_CONTROL_LCKI_MASK 0x00000004 123 #define SI32_PLL_A_CONTROL_LCKI_SHIFT 2 124 // DCO is disabled or not locked. 125 #define SI32_PLL_A_CONTROL_LCKI_NOT_SET_VALUE 0 126 #define SI32_PLL_A_CONTROL_LCKI_NOT_SET_U32 \ 127 (SI32_PLL_A_CONTROL_LCKI_NOT_SET_VALUE << SI32_PLL_A_CONTROL_LCKI_SHIFT) 128 // DCO is enabled and locked. 129 #define SI32_PLL_A_CONTROL_LCKI_SET_VALUE 1 130 #define SI32_PLL_A_CONTROL_LCKI_SET_U32 \ 131 (SI32_PLL_A_CONTROL_LCKI_SET_VALUE << SI32_PLL_A_CONTROL_LCKI_SHIFT) 132 133 #define SI32_PLL_A_CONTROL_LMTIEN_MASK 0x00000200 134 #define SI32_PLL_A_CONTROL_LMTIEN_SHIFT 9 135 // Saturation (high and low) interrupt disabled. 136 #define SI32_PLL_A_CONTROL_LMTIEN_DISABLED_VALUE 0 137 #define SI32_PLL_A_CONTROL_LMTIEN_DISABLED_U32 \ 138 (SI32_PLL_A_CONTROL_LMTIEN_DISABLED_VALUE << SI32_PLL_A_CONTROL_LMTIEN_SHIFT) 139 // Saturation (high and low) interrupt enabled. 140 #define SI32_PLL_A_CONTROL_LMTIEN_ENABLED_VALUE 1 141 #define SI32_PLL_A_CONTROL_LMTIEN_ENABLED_U32 \ 142 (SI32_PLL_A_CONTROL_LMTIEN_ENABLED_VALUE << SI32_PLL_A_CONTROL_LMTIEN_SHIFT) 143 144 #define SI32_PLL_A_CONTROL_LCKIEN_MASK 0x00000400 145 #define SI32_PLL_A_CONTROL_LCKIEN_SHIFT 10 146 // The PLL locking does not cause an interrupt 147 #define SI32_PLL_A_CONTROL_LCKIEN_DISABLED_VALUE 0 148 #define SI32_PLL_A_CONTROL_LCKIEN_DISABLED_U32 \ 149 (SI32_PLL_A_CONTROL_LCKIEN_DISABLED_VALUE << SI32_PLL_A_CONTROL_LCKIEN_SHIFT) 150 // An interrupt is generated if LCKI matches the state selected by LCKPOL. 151 #define SI32_PLL_A_CONTROL_LCKIEN_ENABLED_VALUE 1 152 #define SI32_PLL_A_CONTROL_LCKIEN_ENABLED_U32 \ 153 (SI32_PLL_A_CONTROL_LCKIEN_ENABLED_VALUE << SI32_PLL_A_CONTROL_LCKIEN_SHIFT) 154 155 #define SI32_PLL_A_CONTROL_LCKPOL_MASK 0x00000800 156 #define SI32_PLL_A_CONTROL_LCKPOL_SHIFT 11 157 // The lock state PLL interrupt will occur when LCKI is 0. 158 #define SI32_PLL_A_CONTROL_LCKPOL_ACTIVE_LOW_VALUE 0 159 #define SI32_PLL_A_CONTROL_LCKPOL_ACTIVE_LOW_U32 \ 160 (SI32_PLL_A_CONTROL_LCKPOL_ACTIVE_LOW_VALUE << SI32_PLL_A_CONTROL_LCKPOL_SHIFT) 161 // The lock state PLL interrupt will occur when LCKI is 1. 162 #define SI32_PLL_A_CONTROL_LCKPOL_ACTIVE_HIGH_VALUE 1 163 #define SI32_PLL_A_CONTROL_LCKPOL_ACTIVE_HIGH_U32 \ 164 (SI32_PLL_A_CONTROL_LCKPOL_ACTIVE_HIGH_VALUE << SI32_PLL_A_CONTROL_LCKPOL_SHIFT) 165 166 #define SI32_PLL_A_CONTROL_REFSEL_MASK 0x00070000 167 #define SI32_PLL_A_CONTROL_REFSEL_SHIFT 16 168 // PLL reference clock (FREF) is the RTC0TCLK. 169 #define SI32_PLL_A_CONTROL_REFSEL_RTC0OSC_VALUE 0 170 #define SI32_PLL_A_CONTROL_REFSEL_RTC0OSC_U32 \ 171 (SI32_PLL_A_CONTROL_REFSEL_RTC0OSC_VALUE << SI32_PLL_A_CONTROL_REFSEL_SHIFT) 172 // PLL reference clock (FREF) is the divided Low Power Oscillator (LPOSC0). 173 #define SI32_PLL_A_CONTROL_REFSEL_LPOSC0DIV_VALUE 1 174 #define SI32_PLL_A_CONTROL_REFSEL_LPOSC0DIV_U32 \ 175 (SI32_PLL_A_CONTROL_REFSEL_LPOSC0DIV_VALUE << SI32_PLL_A_CONTROL_REFSEL_SHIFT) 176 // PLL reference clock (FREF) is the external oscillator output (EXTOSC0). 177 #define SI32_PLL_A_CONTROL_REFSEL_EXTOSC0_VALUE 2 178 #define SI32_PLL_A_CONTROL_REFSEL_EXTOSC0_U32 \ 179 (SI32_PLL_A_CONTROL_REFSEL_EXTOSC0_VALUE << SI32_PLL_A_CONTROL_REFSEL_SHIFT) 180 // PLL reference clock (FREF) is the USB0 oscillator (USB0OSC). 181 #define SI32_PLL_A_CONTROL_REFSEL_USBOSC0_VALUE 3 182 #define SI32_PLL_A_CONTROL_REFSEL_USBOSC0_U32 \ 183 (SI32_PLL_A_CONTROL_REFSEL_USBOSC0_VALUE << SI32_PLL_A_CONTROL_REFSEL_SHIFT) 184 // PLL reference clock (FREF) is the Low Power Oscillator (LPOSC0). 185 #define SI32_PLL_A_CONTROL_REFSEL_LPOSC0_VALUE 4 186 #define SI32_PLL_A_CONTROL_REFSEL_LPOSC0_U32 \ 187 (SI32_PLL_A_CONTROL_REFSEL_LPOSC0_VALUE << SI32_PLL_A_CONTROL_REFSEL_SHIFT) 188 189 #define SI32_PLL_A_CONTROL_LOCKTH_MASK 0x00300000 190 #define SI32_PLL_A_CONTROL_LOCKTH_SHIFT 20 191 192 #define SI32_PLL_A_CONTROL_STALL_MASK 0x04000000 193 #define SI32_PLL_A_CONTROL_STALL_SHIFT 26 194 // In phase-lock and frequency-lock modes, spectrum spreading, and dithering 195 // operate normally, if enabled. 196 #define SI32_PLL_A_CONTROL_STALL_DISABLED_VALUE 0 197 #define SI32_PLL_A_CONTROL_STALL_DISABLED_U32 \ 198 (SI32_PLL_A_CONTROL_STALL_DISABLED_VALUE << SI32_PLL_A_CONTROL_STALL_SHIFT) 199 // In phase-lock and frequency-lock modes, spectrum spreading, and dithering are 200 // prevented from updating the output of the DCO. 201 #define SI32_PLL_A_CONTROL_STALL_ENABLED_VALUE 1 202 #define SI32_PLL_A_CONTROL_STALL_ENABLED_U32 \ 203 (SI32_PLL_A_CONTROL_STALL_ENABLED_VALUE << SI32_PLL_A_CONTROL_STALL_SHIFT) 204 205 #define SI32_PLL_A_CONTROL_DITHEN_MASK 0x10000000 206 #define SI32_PLL_A_CONTROL_DITHEN_SHIFT 28 207 // Automatic DCO output dithering disabled. 208 #define SI32_PLL_A_CONTROL_DITHEN_DISABLED_VALUE 0 209 #define SI32_PLL_A_CONTROL_DITHEN_DISABLED_U32 \ 210 (SI32_PLL_A_CONTROL_DITHEN_DISABLED_VALUE << SI32_PLL_A_CONTROL_DITHEN_SHIFT) 211 // Automatic DCO output dithering enabled. 212 #define SI32_PLL_A_CONTROL_DITHEN_ENABLED_VALUE 1 213 #define SI32_PLL_A_CONTROL_DITHEN_ENABLED_U32 \ 214 (SI32_PLL_A_CONTROL_DITHEN_ENABLED_VALUE << SI32_PLL_A_CONTROL_DITHEN_SHIFT) 215 216 #define SI32_PLL_A_CONTROL_EDGSEL_MASK 0x20000000 217 #define SI32_PLL_A_CONTROL_EDGSEL_SHIFT 29 218 // Lock DCO output frequency to the falling edge of the reference frequency. 219 #define SI32_PLL_A_CONTROL_EDGSEL_FALLING_EDGE_VALUE 0 220 #define SI32_PLL_A_CONTROL_EDGSEL_FALLING_EDGE_U32 \ 221 (SI32_PLL_A_CONTROL_EDGSEL_FALLING_EDGE_VALUE << SI32_PLL_A_CONTROL_EDGSEL_SHIFT) 222 // Lock DCO output frequency to the rising edge of the reference frequency. 223 #define SI32_PLL_A_CONTROL_EDGSEL_RISING_EDGE_VALUE 1 224 #define SI32_PLL_A_CONTROL_EDGSEL_RISING_EDGE_U32 \ 225 (SI32_PLL_A_CONTROL_EDGSEL_RISING_EDGE_VALUE << SI32_PLL_A_CONTROL_EDGSEL_SHIFT) 226 227 #define SI32_PLL_A_CONTROL_OUTMD_MASK 0xC0000000 228 #define SI32_PLL_A_CONTROL_OUTMD_SHIFT 30 229 // DCO output is off. 230 #define SI32_PLL_A_CONTROL_OUTMD_OFF_VALUE 0U 231 #define SI32_PLL_A_CONTROL_OUTMD_OFF_U32 \ 232 (SI32_PLL_A_CONTROL_OUTMD_OFF_VALUE << SI32_PLL_A_CONTROL_OUTMD_SHIFT) 233 // DCO output is in Free-Running DCO mode. 234 #define SI32_PLL_A_CONTROL_OUTMD_DCO_VALUE 1U 235 #define SI32_PLL_A_CONTROL_OUTMD_DCO_U32 \ 236 (SI32_PLL_A_CONTROL_OUTMD_DCO_VALUE << SI32_PLL_A_CONTROL_OUTMD_SHIFT) 237 // DCO output is in frequency-lock mode (reference source required). 238 #define SI32_PLL_A_CONTROL_OUTMD_FLL_VALUE 2U 239 #define SI32_PLL_A_CONTROL_OUTMD_FLL_U32 \ 240 (SI32_PLL_A_CONTROL_OUTMD_FLL_VALUE << SI32_PLL_A_CONTROL_OUTMD_SHIFT) 241 // DCO output is in phase-lock mode (reference source required). 242 #define SI32_PLL_A_CONTROL_OUTMD_PLL_VALUE 3U 243 #define SI32_PLL_A_CONTROL_OUTMD_PLL_U32 \ 244 (SI32_PLL_A_CONTROL_OUTMD_PLL_VALUE << SI32_PLL_A_CONTROL_OUTMD_SHIFT) 245 246 247 248 struct SI32_PLL_A_SSPR_Struct 249 { 250 union 251 { 252 struct 253 { 254 // Spectrum Spreading Amplitude 255 volatile uint32_t SSAMP: 3; 256 uint32_t reserved0: 5; 257 // Spectrum Spreading Update Interval 258 volatile uint32_t SSUINV: 5; 259 uint32_t reserved1: 19; 260 }; 261 volatile uint32_t U32; 262 }; 263 }; 264 265 #define SI32_PLL_A_SSPR_SSAMP_MASK 0x00000007 266 #define SI32_PLL_A_SSPR_SSAMP_SHIFT 0 267 // Disable Spectrum Spreading. 268 #define SI32_PLL_A_SSPR_SSAMP_DISABLED_VALUE 0 269 #define SI32_PLL_A_SSPR_SSAMP_DISABLED_U32 \ 270 (SI32_PLL_A_SSPR_SSAMP_DISABLED_VALUE << SI32_PLL_A_SSPR_SSAMP_SHIFT) 271 // Spectrum Spreading set to approximately +/- 0.1% of TDCO. 272 #define SI32_PLL_A_SSPR_SSAMP_SETTING1_VALUE 1 273 #define SI32_PLL_A_SSPR_SSAMP_SETTING1_U32 \ 274 (SI32_PLL_A_SSPR_SSAMP_SETTING1_VALUE << SI32_PLL_A_SSPR_SSAMP_SHIFT) 275 // Spectrum Spreading set to approximately +/- 0.2% of TDCO. 276 #define SI32_PLL_A_SSPR_SSAMP_SETTING2_VALUE 2 277 #define SI32_PLL_A_SSPR_SSAMP_SETTING2_U32 \ 278 (SI32_PLL_A_SSPR_SSAMP_SETTING2_VALUE << SI32_PLL_A_SSPR_SSAMP_SHIFT) 279 // Spectrum Spreading set to approximately +/- 0.4% of TDCO. 280 #define SI32_PLL_A_SSPR_SSAMP_SETTING3_VALUE 3 281 #define SI32_PLL_A_SSPR_SSAMP_SETTING3_U32 \ 282 (SI32_PLL_A_SSPR_SSAMP_SETTING3_VALUE << SI32_PLL_A_SSPR_SSAMP_SHIFT) 283 // Spectrum Spreading set to approximately +/- 0.8% of TDCO. 284 #define SI32_PLL_A_SSPR_SSAMP_SETTING4_VALUE 4 285 #define SI32_PLL_A_SSPR_SSAMP_SETTING4_U32 \ 286 (SI32_PLL_A_SSPR_SSAMP_SETTING4_VALUE << SI32_PLL_A_SSPR_SSAMP_SHIFT) 287 // Spectrum Spreading set to approximately +/- 1.6% of TDCO. 288 #define SI32_PLL_A_SSPR_SSAMP_SETTING5_VALUE 5 289 #define SI32_PLL_A_SSPR_SSAMP_SETTING5_U32 \ 290 (SI32_PLL_A_SSPR_SSAMP_SETTING5_VALUE << SI32_PLL_A_SSPR_SSAMP_SHIFT) 291 292 #define SI32_PLL_A_SSPR_SSUINV_MASK 0x00001F00 293 #define SI32_PLL_A_SSPR_SSUINV_SHIFT 8 294 295 296 297 struct SI32_PLL_A_CALCONFIG_Struct 298 { 299 union 300 { 301 struct 302 { 303 // DCO Dither Setting 304 volatile uint32_t DITHER: 4; 305 // DCO Calibration Value 306 volatile uint32_t CAL: 12; 307 // DCO Range 308 volatile uint32_t RANGE: 3; 309 uint32_t reserved0: 13; 310 }; 311 volatile uint32_t U32; 312 }; 313 }; 314 315 #define SI32_PLL_A_CALCONFIG_DITHER_MASK 0x0000000F 316 #define SI32_PLL_A_CALCONFIG_DITHER_SHIFT 0 317 318 #define SI32_PLL_A_CALCONFIG_CAL_MASK 0x0000FFF0 319 #define SI32_PLL_A_CALCONFIG_CAL_SHIFT 4 320 321 #define SI32_PLL_A_CALCONFIG_RANGE_MASK 0x00070000 322 #define SI32_PLL_A_CALCONFIG_RANGE_SHIFT 16 323 // DCO operates from 23 to 37 MHz. 324 #define SI32_PLL_A_CALCONFIG_RANGE_RANGE0_VALUE 0 325 #define SI32_PLL_A_CALCONFIG_RANGE_RANGE0_U32 \ 326 (SI32_PLL_A_CALCONFIG_RANGE_RANGE0_VALUE << SI32_PLL_A_CALCONFIG_RANGE_SHIFT) 327 // DCO operates from 33 to 54 MHz. 328 #define SI32_PLL_A_CALCONFIG_RANGE_RANGE1_VALUE 1 329 #define SI32_PLL_A_CALCONFIG_RANGE_RANGE1_U32 \ 330 (SI32_PLL_A_CALCONFIG_RANGE_RANGE1_VALUE << SI32_PLL_A_CALCONFIG_RANGE_SHIFT) 331 // DCO operates from 45 to 71 MHz. 332 #define SI32_PLL_A_CALCONFIG_RANGE_RANGE2_VALUE 2 333 #define SI32_PLL_A_CALCONFIG_RANGE_RANGE2_U32 \ 334 (SI32_PLL_A_CALCONFIG_RANGE_RANGE2_VALUE << SI32_PLL_A_CALCONFIG_RANGE_SHIFT) 335 // DCO operates from 53 to 80 MHz. 336 #define SI32_PLL_A_CALCONFIG_RANGE_RANGE3_VALUE 3 337 #define SI32_PLL_A_CALCONFIG_RANGE_RANGE3_U32 \ 338 (SI32_PLL_A_CALCONFIG_RANGE_RANGE3_VALUE << SI32_PLL_A_CALCONFIG_RANGE_SHIFT) 339 // DCO operates from 73 to 80 MHz. 340 #define SI32_PLL_A_CALCONFIG_RANGE_RANGE4_VALUE 4 341 #define SI32_PLL_A_CALCONFIG_RANGE_RANGE4_U32 \ 342 (SI32_PLL_A_CALCONFIG_RANGE_RANGE4_VALUE << SI32_PLL_A_CALCONFIG_RANGE_SHIFT) 343 344 345 346 typedef struct SI32_PLL_A_Struct 347 { 348 struct SI32_PLL_A_DIVIDER_Struct DIVIDER ; // Base Address + 0x0 349 uint32_t reserved0; 350 uint32_t reserved1; 351 uint32_t reserved2; 352 struct SI32_PLL_A_CONTROL_Struct CONTROL ; // Base Address + 0x10 353 volatile uint32_t CONTROL_SET; 354 volatile uint32_t CONTROL_CLR; 355 uint32_t reserved3; 356 struct SI32_PLL_A_SSPR_Struct SSPR ; // Base Address + 0x20 357 uint32_t reserved4; 358 uint32_t reserved5; 359 uint32_t reserved6; 360 struct SI32_PLL_A_CALCONFIG_Struct CALCONFIG ; // Base Address + 0x30 361 uint32_t reserved7; 362 uint32_t reserved8; 363 uint32_t reserved9; 364 uint32_t reserved10[4]; 365 uint32_t reserved11[4]; 366 uint32_t reserved12[4]; 367 } SI32_PLL_A_Type; 368 369 #ifdef __cplusplus 370 } 371 #endif 372 373 #endif // __SI32_PLL_A_REGISTERS_H__ 374 375 //-eof-------------------------------------------------------------------------- 376 377
