1 //----------------------------------------------------------------------------- 2 // Copyright 2012 (c) Silicon Laboratories Inc. 3 // 4 // SPDX-License-Identifier: Zlib 5 // 6 // This siHAL software is provided 'as-is', without any express or implied 7 // warranty. In no event will the authors be held liable for any damages 8 // arising from the use of this software. 9 // 10 // Permission is granted to anyone to use this software for any purpose, 11 // including commercial applications, and to alter it and redistribute it 12 // freely, subject to the following restrictions: 13 // 14 // 1. The origin of this software must not be misrepresented; you must not 15 // claim that you wrote the original software. If you use this software 16 // in a product, an acknowledgment in the product documentation would be 17 // appreciated but is not required. 18 // 2. Altered source versions must be plainly marked as such, and must not be 19 // misrepresented as being the original software. 20 // 3. This notice may not be removed or altered from any source distribution. 21 //----------------------------------------------------------------------------- 22 // 23 // Script: 0.61 24 // Version: 1 25 26 #ifndef __SI32_PCA_A_REGISTERS_H__ 27 #define __SI32_PCA_A_REGISTERS_H__ 28 29 #include <stdint.h> 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 struct SI32_PCA_A_MODE_Struct 36 { 37 union 38 { 39 struct 40 { 41 // Input Clock Divisor 42 volatile uint32_t CLKDIV: 10; 43 // Input Clock (F<subscript>CLKIN</subscript>) Select 44 volatile uint32_t CLKSEL: 3; 45 uint32_t reserved0: 19; 46 }; 47 volatile uint32_t U32; 48 }; 49 }; 50 51 #define SI32_PCA_A_MODE_CLKDIV_MASK 0x000003FF 52 #define SI32_PCA_A_MODE_CLKDIV_SHIFT 0 53 54 #define SI32_PCA_A_MODE_CLKSEL_MASK 0x00001C00 55 #define SI32_PCA_A_MODE_CLKSEL_SHIFT 10 56 // Set the APB as the input clock (FCLKIN). 57 #define SI32_PCA_A_MODE_CLKSEL_APB_VALUE 0 58 #define SI32_PCA_A_MODE_CLKSEL_APB_U32 \ 59 (SI32_PCA_A_MODE_CLKSEL_APB_VALUE << SI32_PCA_A_MODE_CLKSEL_SHIFT) 60 // Set Timer 0 low overflows divided by 2 as the input clock (FCLKIN). 61 #define SI32_PCA_A_MODE_CLKSEL_TIMER0_VALUE 1 62 #define SI32_PCA_A_MODE_CLKSEL_TIMER0_U32 \ 63 (SI32_PCA_A_MODE_CLKSEL_TIMER0_VALUE << SI32_PCA_A_MODE_CLKSEL_SHIFT) 64 // Set high-to-low transitions on ECI divided by 2 as the input clock (FCLKIN). 65 #define SI32_PCA_A_MODE_CLKSEL_HL_ECI_VALUE 2 66 #define SI32_PCA_A_MODE_CLKSEL_HL_ECI_U32 \ 67 (SI32_PCA_A_MODE_CLKSEL_HL_ECI_VALUE << SI32_PCA_A_MODE_CLKSEL_SHIFT) 68 // Set the external oscillator module output (EXTOSCn) divided by 2 as the input 69 // clock (FCLKIN). 70 #define SI32_PCA_A_MODE_CLKSEL_EXTOSCN_VALUE 3 71 #define SI32_PCA_A_MODE_CLKSEL_EXTOSCN_U32 \ 72 (SI32_PCA_A_MODE_CLKSEL_EXTOSCN_VALUE << SI32_PCA_A_MODE_CLKSEL_SHIFT) 73 // Set ECI transitions divided by 2 as the input clock (FCLKIN). 74 #define SI32_PCA_A_MODE_CLKSEL_ECI_VALUE 4 75 #define SI32_PCA_A_MODE_CLKSEL_ECI_U32 \ 76 (SI32_PCA_A_MODE_CLKSEL_ECI_VALUE << SI32_PCA_A_MODE_CLKSEL_SHIFT) 77 78 79 80 struct SI32_PCA_A_CONTROL_Struct 81 { 82 union 83 { 84 struct 85 { 86 // PCA Counter Overflow/Limit Interrupt Enable 87 volatile uint32_t OVFIEN: 1; 88 uint32_t reserved0: 5; 89 // PCA Debug Mode 90 volatile uint32_t DBGMD: 1; 91 uint32_t reserved1: 14; 92 // Clock Divider Output State 93 volatile uint32_t DIVST: 1; 94 // Current Clock Divider Count 95 volatile uint32_t DIV: 10; 96 }; 97 volatile uint32_t U32; 98 }; 99 }; 100 101 #define SI32_PCA_A_CONTROL_OVFIEN_MASK 0x00000001 102 #define SI32_PCA_A_CONTROL_OVFIEN_SHIFT 0 103 // Disable the PCA counter overflow/limit event interrupt. 104 #define SI32_PCA_A_CONTROL_OVFIEN_DISABLED_VALUE 0 105 #define SI32_PCA_A_CONTROL_OVFIEN_DISABLED_U32 \ 106 (SI32_PCA_A_CONTROL_OVFIEN_DISABLED_VALUE << SI32_PCA_A_CONTROL_OVFIEN_SHIFT) 107 // Enable the PCA counter overflow/limit event interrupt. 108 #define SI32_PCA_A_CONTROL_OVFIEN_ENABLED_VALUE 1 109 #define SI32_PCA_A_CONTROL_OVFIEN_ENABLED_U32 \ 110 (SI32_PCA_A_CONTROL_OVFIEN_ENABLED_VALUE << SI32_PCA_A_CONTROL_OVFIEN_SHIFT) 111 112 #define SI32_PCA_A_CONTROL_DBGMD_MASK 0x00000040 113 #define SI32_PCA_A_CONTROL_DBGMD_SHIFT 6 114 // A debug breakpoint will cause the PCA to halt. 115 #define SI32_PCA_A_CONTROL_DBGMD_HALT_VALUE 0 116 #define SI32_PCA_A_CONTROL_DBGMD_HALT_U32 \ 117 (SI32_PCA_A_CONTROL_DBGMD_HALT_VALUE << SI32_PCA_A_CONTROL_DBGMD_SHIFT) 118 // The PCA will continue to operate while the core is halted in debug mode. 119 #define SI32_PCA_A_CONTROL_DBGMD_RUN_VALUE 1 120 #define SI32_PCA_A_CONTROL_DBGMD_RUN_U32 \ 121 (SI32_PCA_A_CONTROL_DBGMD_RUN_VALUE << SI32_PCA_A_CONTROL_DBGMD_SHIFT) 122 123 #define SI32_PCA_A_CONTROL_DIVST_MASK 0x00200000 124 #define SI32_PCA_A_CONTROL_DIVST_SHIFT 21 125 // The clock divider is currently in the first half-cycle. 126 #define SI32_PCA_A_CONTROL_DIVST_OUTPUT_HIGH_VALUE 0 127 #define SI32_PCA_A_CONTROL_DIVST_OUTPUT_HIGH_U32 \ 128 (SI32_PCA_A_CONTROL_DIVST_OUTPUT_HIGH_VALUE << SI32_PCA_A_CONTROL_DIVST_SHIFT) 129 // The clock divider is currently in the second half-cycle. 130 #define SI32_PCA_A_CONTROL_DIVST_OUTPUT_LOW_VALUE 1 131 #define SI32_PCA_A_CONTROL_DIVST_OUTPUT_LOW_U32 \ 132 (SI32_PCA_A_CONTROL_DIVST_OUTPUT_LOW_VALUE << SI32_PCA_A_CONTROL_DIVST_SHIFT) 133 134 #define SI32_PCA_A_CONTROL_DIV_MASK 0xFFC00000 135 #define SI32_PCA_A_CONTROL_DIV_SHIFT 22 136 137 138 139 struct SI32_PCA_A_STATUS_Struct 140 { 141 union 142 { 143 struct 144 { 145 // Channel 0 Capture/Compare Interrupt Flag 146 volatile uint32_t C0CCI: 1; 147 // Channel 1 Capture/Compare Interrupt Flag 148 volatile uint32_t C1CCI: 1; 149 uint32_t reserved0: 4; 150 // Counter/Timer Run 151 volatile uint32_t RUN: 1; 152 // Counter/Timer Overflow/Limit Interrupt Flag 153 volatile uint32_t OVFI: 1; 154 uint32_t reserved1: 2; 155 // Channel 0 Intermediate Overflow Interrupt Flag 156 volatile uint32_t C0IOVFI: 1; 157 // Channel 1 Intermediate Overflow Interrupt Flag 158 volatile uint32_t C1IOVFI: 1; 159 uint32_t reserved2: 20; 160 }; 161 volatile uint32_t U32; 162 }; 163 }; 164 165 #define SI32_PCA_A_STATUS_C0CCI_MASK 0x00000001 166 #define SI32_PCA_A_STATUS_C0CCI_SHIFT 0 167 // A Channel 0 match or capture event did not occur. 168 #define SI32_PCA_A_STATUS_C0CCI_NOT_SET_VALUE 0 169 #define SI32_PCA_A_STATUS_C0CCI_NOT_SET_U32 \ 170 (SI32_PCA_A_STATUS_C0CCI_NOT_SET_VALUE << SI32_PCA_A_STATUS_C0CCI_SHIFT) 171 // A Channel 0 match or capture event occurred. 172 #define SI32_PCA_A_STATUS_C0CCI_SET_VALUE 1 173 #define SI32_PCA_A_STATUS_C0CCI_SET_U32 \ 174 (SI32_PCA_A_STATUS_C0CCI_SET_VALUE << SI32_PCA_A_STATUS_C0CCI_SHIFT) 175 176 #define SI32_PCA_A_STATUS_C1CCI_MASK 0x00000002 177 #define SI32_PCA_A_STATUS_C1CCI_SHIFT 1 178 // A Channel 1 match or capture event did not occur. 179 #define SI32_PCA_A_STATUS_C1CCI_NOT_SET_VALUE 0 180 #define SI32_PCA_A_STATUS_C1CCI_NOT_SET_U32 \ 181 (SI32_PCA_A_STATUS_C1CCI_NOT_SET_VALUE << SI32_PCA_A_STATUS_C1CCI_SHIFT) 182 // A Channel 1 match or capture event occurred. 183 #define SI32_PCA_A_STATUS_C1CCI_SET_VALUE 1 184 #define SI32_PCA_A_STATUS_C1CCI_SET_U32 \ 185 (SI32_PCA_A_STATUS_C1CCI_SET_VALUE << SI32_PCA_A_STATUS_C1CCI_SHIFT) 186 187 #define SI32_PCA_A_STATUS_RUN_MASK 0x00000040 188 #define SI32_PCA_A_STATUS_RUN_SHIFT 6 189 // Stop the PCA Counter/Timer. 190 #define SI32_PCA_A_STATUS_RUN_STOP_VALUE 0 191 #define SI32_PCA_A_STATUS_RUN_STOP_U32 \ 192 (SI32_PCA_A_STATUS_RUN_STOP_VALUE << SI32_PCA_A_STATUS_RUN_SHIFT) 193 // Start the PCA Counter/Timer. 194 #define SI32_PCA_A_STATUS_RUN_START_VALUE 1 195 #define SI32_PCA_A_STATUS_RUN_START_U32 \ 196 (SI32_PCA_A_STATUS_RUN_START_VALUE << SI32_PCA_A_STATUS_RUN_SHIFT) 197 198 #define SI32_PCA_A_STATUS_OVFI_MASK 0x00000080 199 #define SI32_PCA_A_STATUS_OVFI_SHIFT 7 200 // A PCA Counter/Timer overflow/limit event did not occur. 201 #define SI32_PCA_A_STATUS_OVFI_NOT_SET_VALUE 0 202 #define SI32_PCA_A_STATUS_OVFI_NOT_SET_U32 \ 203 (SI32_PCA_A_STATUS_OVFI_NOT_SET_VALUE << SI32_PCA_A_STATUS_OVFI_SHIFT) 204 // A PCA Counter/Timer overflow/limit event occurred. 205 #define SI32_PCA_A_STATUS_OVFI_SET_VALUE 1 206 #define SI32_PCA_A_STATUS_OVFI_SET_U32 \ 207 (SI32_PCA_A_STATUS_OVFI_SET_VALUE << SI32_PCA_A_STATUS_OVFI_SHIFT) 208 209 #define SI32_PCA_A_STATUS_C0IOVFI_MASK 0x00000400 210 #define SI32_PCA_A_STATUS_C0IOVFI_SHIFT 10 211 // Channel 0 did not count past the channel n-bit mode limit. 212 #define SI32_PCA_A_STATUS_C0IOVFI_NOT_SET_VALUE 0 213 #define SI32_PCA_A_STATUS_C0IOVFI_NOT_SET_U32 \ 214 (SI32_PCA_A_STATUS_C0IOVFI_NOT_SET_VALUE << SI32_PCA_A_STATUS_C0IOVFI_SHIFT) 215 // Channel 0 counted past the channel n-bit mode limit. 216 #define SI32_PCA_A_STATUS_C0IOVFI_SET_VALUE 1 217 #define SI32_PCA_A_STATUS_C0IOVFI_SET_U32 \ 218 (SI32_PCA_A_STATUS_C0IOVFI_SET_VALUE << SI32_PCA_A_STATUS_C0IOVFI_SHIFT) 219 220 #define SI32_PCA_A_STATUS_C1IOVFI_MASK 0x00000800 221 #define SI32_PCA_A_STATUS_C1IOVFI_SHIFT 11 222 // Channel 1 did not count past the channel n-bit mode limit. 223 #define SI32_PCA_A_STATUS_C1IOVFI_NOT_SET_VALUE 0 224 #define SI32_PCA_A_STATUS_C1IOVFI_NOT_SET_U32 \ 225 (SI32_PCA_A_STATUS_C1IOVFI_NOT_SET_VALUE << SI32_PCA_A_STATUS_C1IOVFI_SHIFT) 226 // Channel 1 counted past the channel n-bit mode limit. 227 #define SI32_PCA_A_STATUS_C1IOVFI_SET_VALUE 1 228 #define SI32_PCA_A_STATUS_C1IOVFI_SET_U32 \ 229 (SI32_PCA_A_STATUS_C1IOVFI_SET_VALUE << SI32_PCA_A_STATUS_C1IOVFI_SHIFT) 230 231 232 233 struct SI32_PCA_A_COUNTER_Struct 234 { 235 union 236 { 237 struct 238 { 239 // Counter/Timer 240 volatile uint16_t COUNTER_BITS; 241 uint32_t reserved0: 16; 242 }; 243 volatile uint32_t U32; 244 }; 245 }; 246 247 #define SI32_PCA_A_COUNTER_COUNTER_MASK 0x0000FFFF 248 #define SI32_PCA_A_COUNTER_COUNTER_SHIFT 0 249 250 251 252 struct SI32_PCA_A_LIMIT_Struct 253 { 254 union 255 { 256 struct 257 { 258 // Upper Limit 259 volatile uint16_t LIMIT_BITS; 260 uint32_t reserved0: 16; 261 }; 262 volatile uint32_t U32; 263 }; 264 }; 265 266 #define SI32_PCA_A_LIMIT_LIMIT_MASK 0x0000FFFF 267 #define SI32_PCA_A_LIMIT_LIMIT_SHIFT 0 268 269 270 271 typedef struct SI32_PCA_A_Struct 272 { 273 struct SI32_PCA_A_MODE_Struct MODE ; // Base Address + 0x0 274 uint32_t reserved0; 275 uint32_t reserved1; 276 uint32_t reserved2; 277 struct SI32_PCA_A_CONTROL_Struct CONTROL ; // Base Address + 0x10 278 volatile uint32_t CONTROL_SET; 279 volatile uint32_t CONTROL_CLR; 280 uint32_t reserved3; 281 struct SI32_PCA_A_STATUS_Struct STATUS ; // Base Address + 0x20 282 volatile uint32_t STATUS_SET; 283 volatile uint32_t STATUS_CLR; 284 uint32_t reserved4; 285 struct SI32_PCA_A_COUNTER_Struct COUNTER ; // Base Address + 0x30 286 uint32_t reserved5; 287 uint32_t reserved6; 288 uint32_t reserved7; 289 struct SI32_PCA_A_LIMIT_Struct LIMIT ; // Base Address + 0x40 290 uint32_t reserved8; 291 uint32_t reserved9; 292 uint32_t reserved10; 293 } SI32_PCA_A_Type; 294 295 #ifdef __cplusplus 296 } 297 #endif 298 299 #endif // __SI32_PCA_A_REGISTERS_H__ 300 301 //-eof-------------------------------------------------------------------------- 302 303
