1 //----------------------------------------------------------------------------- 2 // Copyright 2013 (c) Silicon Laboratories Inc. 3 // 4 // SPDX-License-Identifier: Zlib 5 // 6 // This siHAL software is provided 'as-is', without any express or implied 7 // warranty. In no event will the authors be held liable for any damages 8 // arising from the use of this software. 9 // 10 // Permission is granted to anyone to use this software for any purpose, 11 // including commercial applications, and to alter it and redistribute it 12 // freely, subject to the following restrictions: 13 // 14 // 1. The origin of this software must not be misrepresented; you must not 15 // claim that you wrote the original software. If you use this software 16 // in a product, an acknowledgment in the product documentation would be 17 // appreciated but is not required. 18 // 2. Altered source versions must be plainly marked as such, and must not be 19 // misrepresented as being the original software. 20 // 3. This notice may not be removed or altered from any source distribution. 21 //----------------------------------------------------------------------------- 22 // 23 // Script: 0.62 24 // Version: 1 25 26 #ifndef __SI32_LPTIMER_B_REGISTERS_H__ 27 #define __SI32_LPTIMER_B_REGISTERS_H__ 28 29 #include <stdint.h> 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 struct SI32_LPTIMER_B_CONTROL_Struct 36 { 37 union 38 { 39 struct 40 { 41 // Count Mode 42 volatile uint32_t CMD: 2; 43 uint32_t reserved0: 2; 44 // External Trigger Source Select 45 volatile uint32_t EXTSEL: 4; 46 // Timer Set 47 volatile uint32_t TMRSET: 1; 48 // Timer Capture 49 volatile uint32_t TMRCAP: 1; 50 // High Speed Timer Access Mode Enable 51 volatile uint32_t HSMDEN: 1; 52 // Timer Compare 0 Threshold Enable 53 volatile uint32_t CMP0EN: 1; 54 // Timer Compare 1 Threshold Enable 55 volatile uint32_t CMP1EN: 1; 56 // Output Enable 57 volatile uint32_t OUTEN: 1; 58 uint32_t reserved1: 2; 59 // Timer Overflow Interrupt Enable 60 volatile uint32_t OVFIEN: 1; 61 // Timer Compare 0 Event Interrupt Enable 62 volatile uint32_t CMP0IEN: 1; 63 // Timer Overflow Output Enable 64 volatile uint32_t OVFOEN: 1; 65 // Timer Compare 0 Event Output Enable 66 volatile uint32_t CMP0OEN: 1; 67 // Timer Compare 1 Event Interrupt Enable 68 volatile uint32_t CMP1IEN: 1; 69 // Timer Compare 1 Event Output Enable 70 volatile uint32_t CMP1OEN: 1; 71 // Output Inversion Enable 72 volatile uint32_t OUTINVEN: 1; 73 uint32_t reserved2: 1; 74 // Timer Compare 0 Event Reset Enable 75 volatile uint32_t CMP0RSTEN: 1; 76 // Timer Compare 1 Event Reset Enable 77 volatile uint32_t CMP1RSTEN: 1; 78 uint32_t reserved3: 3; 79 // Low Power Timer Module Clock Enable 80 volatile uint32_t MCLKEN: 1; 81 // Low Power Timer Debug Mode 82 volatile uint32_t DBGMD: 1; 83 // Timer Run Control and Compare Threshold Enable 84 volatile uint32_t RUN: 1; 85 }; 86 volatile uint32_t U32; 87 }; 88 }; 89 90 #define SI32_LPTIMER_B_CONTROL_CMD_MASK 0x00000003 91 #define SI32_LPTIMER_B_CONTROL_CMD_SHIFT 0 92 // The timer is free running mode on the RTC timer clock (RTC0TCLK). 93 #define SI32_LPTIMER_B_CONTROL_CMD_FREE_VALUE 0 94 #define SI32_LPTIMER_B_CONTROL_CMD_FREE_U32 \ 95 (SI32_LPTIMER_B_CONTROL_CMD_FREE_VALUE << SI32_LPTIMER_B_CONTROL_CMD_SHIFT) 96 // The timer is incremented on the rising edges of the selected external trigger 97 // (LPTnTx). 98 #define SI32_LPTIMER_B_CONTROL_CMD_RISING_EDGE_VALUE 1 99 #define SI32_LPTIMER_B_CONTROL_CMD_RISING_EDGE_U32 \ 100 (SI32_LPTIMER_B_CONTROL_CMD_RISING_EDGE_VALUE << SI32_LPTIMER_B_CONTROL_CMD_SHIFT) 101 // The timer is incremented on the falling edges of the selected external trigger 102 // (LPTnTx). 103 #define SI32_LPTIMER_B_CONTROL_CMD_FALLING_EDGE_VALUE 2 104 #define SI32_LPTIMER_B_CONTROL_CMD_FALLING_EDGE_U32 \ 105 (SI32_LPTIMER_B_CONTROL_CMD_FALLING_EDGE_VALUE << SI32_LPTIMER_B_CONTROL_CMD_SHIFT) 106 // The timer is incremented on both edges of the selected external trigger 107 // (LPTnTx). 108 #define SI32_LPTIMER_B_CONTROL_CMD_ANY_EDGE_VALUE 3 109 #define SI32_LPTIMER_B_CONTROL_CMD_ANY_EDGE_U32 \ 110 (SI32_LPTIMER_B_CONTROL_CMD_ANY_EDGE_VALUE << SI32_LPTIMER_B_CONTROL_CMD_SHIFT) 111 112 #define SI32_LPTIMER_B_CONTROL_EXTSEL_MASK 0x000000F0 113 #define SI32_LPTIMER_B_CONTROL_EXTSEL_SHIFT 4 114 // Select external trigger LPTnT0. 115 #define SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT0_VALUE 0 116 #define SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT0_U32 \ 117 (SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT0_VALUE << SI32_LPTIMER_B_CONTROL_EXTSEL_SHIFT) 118 // Select external trigger LPTnT1. 119 #define SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT1_VALUE 1 120 #define SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT1_U32 \ 121 (SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT1_VALUE << SI32_LPTIMER_B_CONTROL_EXTSEL_SHIFT) 122 // Select external trigger LPTnT2. 123 #define SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT2_VALUE 2 124 #define SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT2_U32 \ 125 (SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT2_VALUE << SI32_LPTIMER_B_CONTROL_EXTSEL_SHIFT) 126 // Select external trigger LPTnT3. 127 #define SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT3_VALUE 3 128 #define SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT3_U32 \ 129 (SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT3_VALUE << SI32_LPTIMER_B_CONTROL_EXTSEL_SHIFT) 130 // Select external trigger LPTnT4. 131 #define SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT4_VALUE 4 132 #define SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT4_U32 \ 133 (SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT4_VALUE << SI32_LPTIMER_B_CONTROL_EXTSEL_SHIFT) 134 // Select external trigger LPTnT5. 135 #define SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT5_VALUE 5 136 #define SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT5_U32 \ 137 (SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT5_VALUE << SI32_LPTIMER_B_CONTROL_EXTSEL_SHIFT) 138 // Select external trigger LPTnT6. 139 #define SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT6_VALUE 6 140 #define SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT6_U32 \ 141 (SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT6_VALUE << SI32_LPTIMER_B_CONTROL_EXTSEL_SHIFT) 142 // Select external trigger LPTnT7. 143 #define SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT7_VALUE 7 144 #define SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT7_U32 \ 145 (SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT7_VALUE << SI32_LPTIMER_B_CONTROL_EXTSEL_SHIFT) 146 // Select external trigger LPTnT8. 147 #define SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT8_VALUE 8 148 #define SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT8_U32 \ 149 (SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT8_VALUE << SI32_LPTIMER_B_CONTROL_EXTSEL_SHIFT) 150 // Select external trigger LPTnT9. 151 #define SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT9_VALUE 9 152 #define SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT9_U32 \ 153 (SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT9_VALUE << SI32_LPTIMER_B_CONTROL_EXTSEL_SHIFT) 154 // Select external trigger LPTnT10. 155 #define SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT10_VALUE 10 156 #define SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT10_U32 \ 157 (SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT10_VALUE << SI32_LPTIMER_B_CONTROL_EXTSEL_SHIFT) 158 // Select external trigger LPTnT11. 159 #define SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT11_VALUE 11 160 #define SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT11_U32 \ 161 (SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT11_VALUE << SI32_LPTIMER_B_CONTROL_EXTSEL_SHIFT) 162 // Select external trigger LPTnT12. 163 #define SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT12_VALUE 12 164 #define SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT12_U32 \ 165 (SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT12_VALUE << SI32_LPTIMER_B_CONTROL_EXTSEL_SHIFT) 166 // Select external trigger LPTnT13. 167 #define SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT13_VALUE 13 168 #define SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT13_U32 \ 169 (SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT13_VALUE << SI32_LPTIMER_B_CONTROL_EXTSEL_SHIFT) 170 // Select external trigger LPTnT14. 171 #define SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT14_VALUE 14 172 #define SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT14_U32 \ 173 (SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT14_VALUE << SI32_LPTIMER_B_CONTROL_EXTSEL_SHIFT) 174 // Select external trigger LPTnT15. 175 #define SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT15_VALUE 15 176 #define SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT15_U32 \ 177 (SI32_LPTIMER_B_CONTROL_EXTSEL_LPTNT15_VALUE << SI32_LPTIMER_B_CONTROL_EXTSEL_SHIFT) 178 179 #define SI32_LPTIMER_B_CONTROL_TMRSET_MASK 0x00000100 180 #define SI32_LPTIMER_B_CONTROL_TMRSET_SHIFT 8 181 // Writing a 1 to TMRSET initiates a copy of the value from the COUNT register into 182 // the internal timer register. This field is automatically cleared by hardware 183 // when the copy is complete and does not need to be cleared by software. 184 #define SI32_LPTIMER_B_CONTROL_TMRSET_SET_VALUE 1 185 #define SI32_LPTIMER_B_CONTROL_TMRSET_SET_U32 \ 186 (SI32_LPTIMER_B_CONTROL_TMRSET_SET_VALUE << SI32_LPTIMER_B_CONTROL_TMRSET_SHIFT) 187 188 #define SI32_LPTIMER_B_CONTROL_TMRCAP_MASK 0x00000200 189 #define SI32_LPTIMER_B_CONTROL_TMRCAP_SHIFT 9 190 // Writing a 1 to TMRCAP initiates a read of internal timer register into the COUNT 191 // register. This field is automatically cleared by hardware when the operation 192 // completes and does not need to be cleared by software. 193 #define SI32_LPTIMER_B_CONTROL_TMRCAP_SET_VALUE 1 194 #define SI32_LPTIMER_B_CONTROL_TMRCAP_SET_U32 \ 195 (SI32_LPTIMER_B_CONTROL_TMRCAP_SET_VALUE << SI32_LPTIMER_B_CONTROL_TMRCAP_SHIFT) 196 197 #define SI32_LPTIMER_B_CONTROL_HSMDEN_MASK 0x00000400 198 #define SI32_LPTIMER_B_CONTROL_HSMDEN_SHIFT 10 199 // Disable high speed timer access mode. 200 #define SI32_LPTIMER_B_CONTROL_HSMDEN_DISABLED_VALUE 0 201 #define SI32_LPTIMER_B_CONTROL_HSMDEN_DISABLED_U32 \ 202 (SI32_LPTIMER_B_CONTROL_HSMDEN_DISABLED_VALUE << SI32_LPTIMER_B_CONTROL_HSMDEN_SHIFT) 203 // Enable high speed timer access mode. 204 #define SI32_LPTIMER_B_CONTROL_HSMDEN_ENABLED_VALUE 1 205 #define SI32_LPTIMER_B_CONTROL_HSMDEN_ENABLED_U32 \ 206 (SI32_LPTIMER_B_CONTROL_HSMDEN_ENABLED_VALUE << SI32_LPTIMER_B_CONTROL_HSMDEN_SHIFT) 207 208 #define SI32_LPTIMER_B_CONTROL_CMP0EN_MASK 0x00000800 209 #define SI32_LPTIMER_B_CONTROL_CMP0EN_SHIFT 11 210 #define SI32_LPTIMER_B_CONTROL_CMP0EN_DISABLED_VALUE 0 211 #define SI32_LPTIMER_B_CONTROL_CMP0EN_DISABLED_U32 \ 212 (SI32_LPTIMER_B_CONTROL_CMP0EN_DISABLED_VALUE << SI32_LPTIMER_B_CONTROL_CMP0EN_SHIFT) 213 #define SI32_LPTIMER_B_CONTROL_CMP0EN_ENABLED_VALUE 1 214 #define SI32_LPTIMER_B_CONTROL_CMP0EN_ENABLED_U32 \ 215 (SI32_LPTIMER_B_CONTROL_CMP0EN_ENABLED_VALUE << SI32_LPTIMER_B_CONTROL_CMP0EN_SHIFT) 216 217 #define SI32_LPTIMER_B_CONTROL_CMP1EN_MASK 0x00001000 218 #define SI32_LPTIMER_B_CONTROL_CMP1EN_SHIFT 12 219 #define SI32_LPTIMER_B_CONTROL_CMP1EN_DISABLED_VALUE 0 220 #define SI32_LPTIMER_B_CONTROL_CMP1EN_DISABLED_U32 \ 221 (SI32_LPTIMER_B_CONTROL_CMP1EN_DISABLED_VALUE << SI32_LPTIMER_B_CONTROL_CMP1EN_SHIFT) 222 #define SI32_LPTIMER_B_CONTROL_CMP1EN_ENABLED_VALUE 1 223 #define SI32_LPTIMER_B_CONTROL_CMP1EN_ENABLED_U32 \ 224 (SI32_LPTIMER_B_CONTROL_CMP1EN_ENABLED_VALUE << SI32_LPTIMER_B_CONTROL_CMP1EN_SHIFT) 225 226 #define SI32_LPTIMER_B_CONTROL_OUTEN_MASK 0x00002000 227 #define SI32_LPTIMER_B_CONTROL_OUTEN_SHIFT 13 228 // Disable the LPTIMER0 output. 229 #define SI32_LPTIMER_B_CONTROL_OUTEN_DISABLED_VALUE 0 230 #define SI32_LPTIMER_B_CONTROL_OUTEN_DISABLED_U32 \ 231 (SI32_LPTIMER_B_CONTROL_OUTEN_DISABLED_VALUE << SI32_LPTIMER_B_CONTROL_OUTEN_SHIFT) 232 // Enable the LPTIMER0 output. 233 #define SI32_LPTIMER_B_CONTROL_OUTEN_ENABLED_VALUE 1 234 #define SI32_LPTIMER_B_CONTROL_OUTEN_ENABLED_U32 \ 235 (SI32_LPTIMER_B_CONTROL_OUTEN_ENABLED_VALUE << SI32_LPTIMER_B_CONTROL_OUTEN_SHIFT) 236 237 #define SI32_LPTIMER_B_CONTROL_OVFIEN_MASK 0x00010000 238 #define SI32_LPTIMER_B_CONTROL_OVFIEN_SHIFT 16 239 // Disable the timer overflow interrupt. 240 #define SI32_LPTIMER_B_CONTROL_OVFIEN_DISABLED_VALUE 0 241 #define SI32_LPTIMER_B_CONTROL_OVFIEN_DISABLED_U32 \ 242 (SI32_LPTIMER_B_CONTROL_OVFIEN_DISABLED_VALUE << SI32_LPTIMER_B_CONTROL_OVFIEN_SHIFT) 243 // Enable the timer overflow interrupt. 244 #define SI32_LPTIMER_B_CONTROL_OVFIEN_ENABLED_VALUE 1 245 #define SI32_LPTIMER_B_CONTROL_OVFIEN_ENABLED_U32 \ 246 (SI32_LPTIMER_B_CONTROL_OVFIEN_ENABLED_VALUE << SI32_LPTIMER_B_CONTROL_OVFIEN_SHIFT) 247 248 #define SI32_LPTIMER_B_CONTROL_CMP0IEN_MASK 0x00020000 249 #define SI32_LPTIMER_B_CONTROL_CMP0IEN_SHIFT 17 250 // Disable the timer compare 0 event interrupt. 251 #define SI32_LPTIMER_B_CONTROL_CMP0IEN_DISABLED_VALUE 0 252 #define SI32_LPTIMER_B_CONTROL_CMP0IEN_DISABLED_U32 \ 253 (SI32_LPTIMER_B_CONTROL_CMP0IEN_DISABLED_VALUE << SI32_LPTIMER_B_CONTROL_CMP0IEN_SHIFT) 254 // Enable the timer compare 0 event interrupt. 255 #define SI32_LPTIMER_B_CONTROL_CMP0IEN_ENABLED_VALUE 1 256 #define SI32_LPTIMER_B_CONTROL_CMP0IEN_ENABLED_U32 \ 257 (SI32_LPTIMER_B_CONTROL_CMP0IEN_ENABLED_VALUE << SI32_LPTIMER_B_CONTROL_CMP0IEN_SHIFT) 258 259 #define SI32_LPTIMER_B_CONTROL_OVFOEN_MASK 0x00040000 260 #define SI32_LPTIMER_B_CONTROL_OVFOEN_SHIFT 18 261 // Timer overflows do not modify the Low Power Timer output. 262 #define SI32_LPTIMER_B_CONTROL_OVFOEN_DISABLED_VALUE 0 263 #define SI32_LPTIMER_B_CONTROL_OVFOEN_DISABLED_U32 \ 264 (SI32_LPTIMER_B_CONTROL_OVFOEN_DISABLED_VALUE << SI32_LPTIMER_B_CONTROL_OVFOEN_SHIFT) 265 // Timer overflows set the Low Power Timer output to 1. 266 #define SI32_LPTIMER_B_CONTROL_OVFOEN_ENABLED_VALUE 1 267 #define SI32_LPTIMER_B_CONTROL_OVFOEN_ENABLED_U32 \ 268 (SI32_LPTIMER_B_CONTROL_OVFOEN_ENABLED_VALUE << SI32_LPTIMER_B_CONTROL_OVFOEN_SHIFT) 269 270 #define SI32_LPTIMER_B_CONTROL_CMP0OEN_MASK 0x00080000 271 #define SI32_LPTIMER_B_CONTROL_CMP0OEN_SHIFT 19 272 // Timer compare 0 events do not modify the Low Power Timer output. 273 #define SI32_LPTIMER_B_CONTROL_CMP0OEN_DISABLED_VALUE 0 274 #define SI32_LPTIMER_B_CONTROL_CMP0OEN_DISABLED_U32 \ 275 (SI32_LPTIMER_B_CONTROL_CMP0OEN_DISABLED_VALUE << SI32_LPTIMER_B_CONTROL_CMP0OEN_SHIFT) 276 // Timer compare 0 events clear the Low Power Timer output to 0. 277 #define SI32_LPTIMER_B_CONTROL_CMP0OEN_ENABLED_VALUE 1 278 #define SI32_LPTIMER_B_CONTROL_CMP0OEN_ENABLED_U32 \ 279 (SI32_LPTIMER_B_CONTROL_CMP0OEN_ENABLED_VALUE << SI32_LPTIMER_B_CONTROL_CMP0OEN_SHIFT) 280 281 #define SI32_LPTIMER_B_CONTROL_CMP1IEN_MASK 0x00100000 282 #define SI32_LPTIMER_B_CONTROL_CMP1IEN_SHIFT 20 283 // Disable the timer compare 1 event interrupt. 284 #define SI32_LPTIMER_B_CONTROL_CMP1IEN_DISABLED_VALUE 0 285 #define SI32_LPTIMER_B_CONTROL_CMP1IEN_DISABLED_U32 \ 286 (SI32_LPTIMER_B_CONTROL_CMP1IEN_DISABLED_VALUE << SI32_LPTIMER_B_CONTROL_CMP1IEN_SHIFT) 287 // Enable the timer compare 1 event interrupt. 288 #define SI32_LPTIMER_B_CONTROL_CMP1IEN_ENABLED_VALUE 1 289 #define SI32_LPTIMER_B_CONTROL_CMP1IEN_ENABLED_U32 \ 290 (SI32_LPTIMER_B_CONTROL_CMP1IEN_ENABLED_VALUE << SI32_LPTIMER_B_CONTROL_CMP1IEN_SHIFT) 291 292 #define SI32_LPTIMER_B_CONTROL_CMP1OEN_MASK 0x00200000 293 #define SI32_LPTIMER_B_CONTROL_CMP1OEN_SHIFT 21 294 // Timer compare 1 events do not modify the Low Power Timer output. 295 #define SI32_LPTIMER_B_CONTROL_CMP1OEN_DISABLED_VALUE 0 296 #define SI32_LPTIMER_B_CONTROL_CMP1OEN_DISABLED_U32 \ 297 (SI32_LPTIMER_B_CONTROL_CMP1OEN_DISABLED_VALUE << SI32_LPTIMER_B_CONTROL_CMP1OEN_SHIFT) 298 // Timer compare 1 events set the Low Power Timer output to 1. 299 #define SI32_LPTIMER_B_CONTROL_CMP1OEN_ENABLED_VALUE 1 300 #define SI32_LPTIMER_B_CONTROL_CMP1OEN_ENABLED_U32 \ 301 (SI32_LPTIMER_B_CONTROL_CMP1OEN_ENABLED_VALUE << SI32_LPTIMER_B_CONTROL_CMP1OEN_SHIFT) 302 303 #define SI32_LPTIMER_B_CONTROL_OUTINVEN_MASK 0x00400000 304 #define SI32_LPTIMER_B_CONTROL_OUTINVEN_SHIFT 22 305 // Do not invert the LPTIMER0 output. 306 #define SI32_LPTIMER_B_CONTROL_OUTINVEN_DISABLED_VALUE 0 307 #define SI32_LPTIMER_B_CONTROL_OUTINVEN_DISABLED_U32 \ 308 (SI32_LPTIMER_B_CONTROL_OUTINVEN_DISABLED_VALUE << SI32_LPTIMER_B_CONTROL_OUTINVEN_SHIFT) 309 // Invert the LPTIMER0 output. 310 #define SI32_LPTIMER_B_CONTROL_OUTINVEN_ENABLED_VALUE 1 311 #define SI32_LPTIMER_B_CONTROL_OUTINVEN_ENABLED_U32 \ 312 (SI32_LPTIMER_B_CONTROL_OUTINVEN_ENABLED_VALUE << SI32_LPTIMER_B_CONTROL_OUTINVEN_SHIFT) 313 314 #define SI32_LPTIMER_B_CONTROL_CMP0RSTEN_MASK 0x01000000 315 #define SI32_LPTIMER_B_CONTROL_CMP0RSTEN_SHIFT 24 316 // Timer compare 0 events do not reset the timer. 317 #define SI32_LPTIMER_B_CONTROL_CMP0RSTEN_DISABLED_VALUE 0 318 #define SI32_LPTIMER_B_CONTROL_CMP0RSTEN_DISABLED_U32 \ 319 (SI32_LPTIMER_B_CONTROL_CMP0RSTEN_DISABLED_VALUE << SI32_LPTIMER_B_CONTROL_CMP0RSTEN_SHIFT) 320 // Timer compare 0 events reset the timer. 321 #define SI32_LPTIMER_B_CONTROL_CMP0RSTEN_ENABLED_VALUE 1 322 #define SI32_LPTIMER_B_CONTROL_CMP0RSTEN_ENABLED_U32 \ 323 (SI32_LPTIMER_B_CONTROL_CMP0RSTEN_ENABLED_VALUE << SI32_LPTIMER_B_CONTROL_CMP0RSTEN_SHIFT) 324 325 #define SI32_LPTIMER_B_CONTROL_CMP1RSTEN_MASK 0x02000000 326 #define SI32_LPTIMER_B_CONTROL_CMP1RSTEN_SHIFT 25 327 // Timer compare 1 events do not reset the timer. 328 #define SI32_LPTIMER_B_CONTROL_CMP1RSTEN_DISABLED_VALUE 0 329 #define SI32_LPTIMER_B_CONTROL_CMP1RSTEN_DISABLED_U32 \ 330 (SI32_LPTIMER_B_CONTROL_CMP1RSTEN_DISABLED_VALUE << SI32_LPTIMER_B_CONTROL_CMP1RSTEN_SHIFT) 331 // Timer compare 1 events reset the timer. 332 #define SI32_LPTIMER_B_CONTROL_CMP1RSTEN_ENABLED_VALUE 1 333 #define SI32_LPTIMER_B_CONTROL_CMP1RSTEN_ENABLED_U32 \ 334 (SI32_LPTIMER_B_CONTROL_CMP1RSTEN_ENABLED_VALUE << SI32_LPTIMER_B_CONTROL_CMP1RSTEN_SHIFT) 335 336 #define SI32_LPTIMER_B_CONTROL_MCLKEN_MASK 0x20000000 337 #define SI32_LPTIMER_B_CONTROL_MCLKEN_SHIFT 29 338 // Disable the clock to the Low Power Timer module. 339 #define SI32_LPTIMER_B_CONTROL_MCLKEN_DISABLED_VALUE 0 340 #define SI32_LPTIMER_B_CONTROL_MCLKEN_DISABLED_U32 \ 341 (SI32_LPTIMER_B_CONTROL_MCLKEN_DISABLED_VALUE << SI32_LPTIMER_B_CONTROL_MCLKEN_SHIFT) 342 // Enable the clock to the Low Power Timer module. 343 #define SI32_LPTIMER_B_CONTROL_MCLKEN_ENABLED_VALUE 1 344 #define SI32_LPTIMER_B_CONTROL_MCLKEN_ENABLED_U32 \ 345 (SI32_LPTIMER_B_CONTROL_MCLKEN_ENABLED_VALUE << SI32_LPTIMER_B_CONTROL_MCLKEN_SHIFT) 346 347 #define SI32_LPTIMER_B_CONTROL_DBGMD_MASK 0x40000000 348 #define SI32_LPTIMER_B_CONTROL_DBGMD_SHIFT 30 349 // The Low Power Timer module will continue to operate while the core is halted in 350 // debug mode. 351 #define SI32_LPTIMER_B_CONTROL_DBGMD_RUN_VALUE 0 352 #define SI32_LPTIMER_B_CONTROL_DBGMD_RUN_U32 \ 353 (SI32_LPTIMER_B_CONTROL_DBGMD_RUN_VALUE << SI32_LPTIMER_B_CONTROL_DBGMD_SHIFT) 354 // A debug breakpoint will cause the Low Power Timer module to halt. 355 #define SI32_LPTIMER_B_CONTROL_DBGMD_HALT_VALUE 1 356 #define SI32_LPTIMER_B_CONTROL_DBGMD_HALT_U32 \ 357 (SI32_LPTIMER_B_CONTROL_DBGMD_HALT_VALUE << SI32_LPTIMER_B_CONTROL_DBGMD_SHIFT) 358 359 #define SI32_LPTIMER_B_CONTROL_RUN_MASK 0x80000000 360 #define SI32_LPTIMER_B_CONTROL_RUN_SHIFT 31 361 // Stop the timer and disable the compare threshold. 362 #define SI32_LPTIMER_B_CONTROL_RUN_STOP_VALUE 0U 363 #define SI32_LPTIMER_B_CONTROL_RUN_STOP_U32 \ 364 (SI32_LPTIMER_B_CONTROL_RUN_STOP_VALUE << SI32_LPTIMER_B_CONTROL_RUN_SHIFT) 365 // Start the timer running and enable the compare threshold. 366 #define SI32_LPTIMER_B_CONTROL_RUN_START_VALUE 1U 367 #define SI32_LPTIMER_B_CONTROL_RUN_START_U32 \ 368 (SI32_LPTIMER_B_CONTROL_RUN_START_VALUE << SI32_LPTIMER_B_CONTROL_RUN_SHIFT) 369 370 371 372 struct SI32_LPTIMER_B_COUNT_Struct 373 { 374 union 375 { 376 struct 377 { 378 // Timer Value 379 volatile uint16_t TIMER; 380 uint32_t reserved0: 16; 381 }; 382 volatile uint32_t U32; 383 }; 384 }; 385 386 #define SI32_LPTIMER_B_COUNT_TIMER_MASK 0x0000FFFF 387 #define SI32_LPTIMER_B_COUNT_TIMER_SHIFT 0 388 389 390 391 struct SI32_LPTIMER_B_THRESHOLD_Struct 392 { 393 union 394 { 395 struct 396 { 397 // Timer Compare 0 Threshold Value 398 volatile uint16_t COMPARE0; 399 // Timer Compare 1 Threshold Value 400 volatile uint16_t COMPARE1; 401 }; 402 volatile uint32_t U32; 403 }; 404 }; 405 406 #define SI32_LPTIMER_B_THRESHOLD_COMPARE0_MASK 0x0000FFFF 407 #define SI32_LPTIMER_B_THRESHOLD_COMPARE0_SHIFT 0 408 409 #define SI32_LPTIMER_B_THRESHOLD_COMPARE1_MASK 0xFFFF0000 410 #define SI32_LPTIMER_B_THRESHOLD_COMPARE1_SHIFT 16 411 412 413 414 struct SI32_LPTIMER_B_STATUS_Struct 415 { 416 union 417 { 418 struct 419 { 420 // Timer Overflow Interrupt Flag 421 volatile uint32_t OVFI: 1; 422 // Timer Compare 0 Event Interrupt Flag 423 volatile uint32_t CMP0I: 1; 424 // Timer Compare 1 Event Interrupt Flag 425 volatile uint32_t CMP1I: 1; 426 uint32_t reserved0: 29; 427 }; 428 volatile uint32_t U32; 429 }; 430 }; 431 432 #define SI32_LPTIMER_B_STATUS_OVFI_MASK 0x00000001 433 #define SI32_LPTIMER_B_STATUS_OVFI_SHIFT 0 434 // A timer overflow has not occurred. 435 #define SI32_LPTIMER_B_STATUS_OVFI_NOT_SET_VALUE 0 436 #define SI32_LPTIMER_B_STATUS_OVFI_NOT_SET_U32 \ 437 (SI32_LPTIMER_B_STATUS_OVFI_NOT_SET_VALUE << SI32_LPTIMER_B_STATUS_OVFI_SHIFT) 438 // A timer overflow occurred. 439 #define SI32_LPTIMER_B_STATUS_OVFI_SET_VALUE 1 440 #define SI32_LPTIMER_B_STATUS_OVFI_SET_U32 \ 441 (SI32_LPTIMER_B_STATUS_OVFI_SET_VALUE << SI32_LPTIMER_B_STATUS_OVFI_SHIFT) 442 443 #define SI32_LPTIMER_B_STATUS_CMP0I_MASK 0x00000002 444 #define SI32_LPTIMER_B_STATUS_CMP0I_SHIFT 1 445 // A timer compare 0 event has not occurred. 446 #define SI32_LPTIMER_B_STATUS_CMP0I_NOT_SET_VALUE 0 447 #define SI32_LPTIMER_B_STATUS_CMP0I_NOT_SET_U32 \ 448 (SI32_LPTIMER_B_STATUS_CMP0I_NOT_SET_VALUE << SI32_LPTIMER_B_STATUS_CMP0I_SHIFT) 449 // A timer compare 0 event occurred. 450 #define SI32_LPTIMER_B_STATUS_CMP0I_SET_VALUE 1 451 #define SI32_LPTIMER_B_STATUS_CMP0I_SET_U32 \ 452 (SI32_LPTIMER_B_STATUS_CMP0I_SET_VALUE << SI32_LPTIMER_B_STATUS_CMP0I_SHIFT) 453 454 #define SI32_LPTIMER_B_STATUS_CMP1I_MASK 0x00000004 455 #define SI32_LPTIMER_B_STATUS_CMP1I_SHIFT 2 456 // A timer compare 1 event has not occurred. 457 #define SI32_LPTIMER_B_STATUS_CMP1I_NOT_SET_VALUE 0 458 #define SI32_LPTIMER_B_STATUS_CMP1I_NOT_SET_U32 \ 459 (SI32_LPTIMER_B_STATUS_CMP1I_NOT_SET_VALUE << SI32_LPTIMER_B_STATUS_CMP1I_SHIFT) 460 // A timer compare 1 event occurred. 461 #define SI32_LPTIMER_B_STATUS_CMP1I_SET_VALUE 1 462 #define SI32_LPTIMER_B_STATUS_CMP1I_SET_U32 \ 463 (SI32_LPTIMER_B_STATUS_CMP1I_SET_VALUE << SI32_LPTIMER_B_STATUS_CMP1I_SHIFT) 464 465 466 467 typedef struct SI32_LPTIMER_B_Struct 468 { 469 struct SI32_LPTIMER_B_CONTROL_Struct CONTROL ; // Base Address + 0x0 470 volatile uint32_t CONTROL_SET; 471 volatile uint32_t CONTROL_CLR; 472 uint32_t reserved0; 473 struct SI32_LPTIMER_B_COUNT_Struct COUNT ; // Base Address + 0x10 474 uint32_t reserved1; 475 uint32_t reserved2; 476 uint32_t reserved3; 477 struct SI32_LPTIMER_B_THRESHOLD_Struct THRESHOLD ; // Base Address + 0x20 478 uint32_t reserved4; 479 uint32_t reserved5; 480 uint32_t reserved6; 481 struct SI32_LPTIMER_B_STATUS_Struct STATUS ; // Base Address + 0x30 482 volatile uint32_t STATUS_SET; 483 volatile uint32_t STATUS_CLR; 484 uint32_t reserved7; 485 } SI32_LPTIMER_B_Type; 486 487 #ifdef __cplusplus 488 } 489 #endif 490 491 #endif // __SI32_LPTIMER_B_REGISTERS_H__ 492 493 //-eof-------------------------------------------------------------------------- 494 495
