1 //----------------------------------------------------------------------------- 2 // Copyright 2012 (c) Silicon Laboratories Inc. 3 // 4 // SPDX-License-Identifier: Zlib 5 // 6 // This siHAL software is provided 'as-is', without any express or implied 7 // warranty. In no event will the authors be held liable for any damages 8 // arising from the use of this software. 9 // 10 // Permission is granted to anyone to use this software for any purpose, 11 // including commercial applications, and to alter it and redistribute it 12 // freely, subject to the following restrictions: 13 // 14 // 1. The origin of this software must not be misrepresented; you must not 15 // claim that you wrote the original software. If you use this software 16 // in a product, an acknowledgment in the product documentation would be 17 // appreciated but is not required. 18 // 2. Altered source versions must be plainly marked as such, and must not be 19 // misrepresented as being the original software. 20 // 3. This notice may not be removed or altered from any source distribution. 21 //----------------------------------------------------------------------------- 22 // 23 // Script: 0.61 24 // Version: 1 25 26 #ifndef __SI32_LCD_A_REGISTERS_H__ 27 #define __SI32_LCD_A_REGISTERS_H__ 28 29 #include <stdint.h> 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 struct SI32_LCD_A_CONFIG_Struct 36 { 37 union 38 { 39 struct 40 { 41 // Module Enable 42 volatile uint32_t LCDEN: 1; 43 uint32_t reserved0: 1; 44 // Charge Pump Full Power Drive Mode Enable 45 volatile uint32_t CPFPDEN: 1; 46 // LCD Missing Clock Detector Enable 47 volatile uint32_t MCDEN: 1; 48 // RTC Clock Request Enable 49 volatile uint32_t RTCCEN: 1; 50 // Bias Enable 51 volatile uint32_t BIASEN: 1; 52 // DCDC Bias Output Enable 53 volatile uint32_t DCDCBIASEN: 1; 54 // DCDC Bias Standby Enable 55 volatile uint32_t DCDCSTDBYEN: 1; 56 // Charge Pump Bypass Enable 57 volatile uint32_t CPBEN: 1; 58 // High-Contrast-Voltage Low-Power Mode Enable 59 volatile uint32_t HCVLPMEN: 1; 60 // VBAT Monitor Low Power Enable 61 volatile uint32_t VBMLPEN: 1; 62 // Charge-Pump Oscillator Low-Power Enable 63 volatile uint32_t CPOLPEN: 1; 64 // Comparator Buffer Low-Power Enable 65 volatile uint32_t CMPBLPEN: 1; 66 // Bias Switching Enable 67 volatile uint32_t BIASSEN: 1; 68 // Reference Band Gap Switching Enable 69 volatile uint32_t RBGSEN: 1; 70 uint32_t reserved1: 1; 71 // Charge-Pump Auto-Contrast Enable 72 volatile uint32_t CPACEN: 1; 73 // Force Bias Continuous Mode Enable 74 volatile uint32_t FBIASCEN: 1; 75 uint32_t reserved2: 6; 76 // High-Contrast-Voltage Comparator Bypass Enable 77 volatile uint32_t HCVCBYPEN: 1; 78 // High-Contrast-Voltage Comparator Force On Enable 79 volatile uint32_t HCVCFOEN: 1; 80 // High-Contrast-Voltage Comparator Hysteresis 81 volatile uint32_t HCVCHMD: 1; 82 // High-Contrast-Voltage Comparator Bias 83 volatile uint32_t HCVCBMD: 1; 84 uint32_t reserved3: 2; 85 // High-Contrast-Voltage Comparator Status 86 volatile uint32_t CPCS: 1; 87 uint32_t reserved4: 1; 88 }; 89 volatile uint32_t U32; 90 }; 91 }; 92 93 #define SI32_LCD_A_CONFIG_LCDEN_MASK 0x00000001 94 #define SI32_LCD_A_CONFIG_LCDEN_SHIFT 0 95 // Disable the LCD module. 96 #define SI32_LCD_A_CONFIG_LCDEN_DISABLED_VALUE 0 97 #define SI32_LCD_A_CONFIG_LCDEN_DISABLED_U32 \ 98 (SI32_LCD_A_CONFIG_LCDEN_DISABLED_VALUE << SI32_LCD_A_CONFIG_LCDEN_SHIFT) 99 // Enable the LCD module. 100 #define SI32_LCD_A_CONFIG_LCDEN_ENABLED_VALUE 1 101 #define SI32_LCD_A_CONFIG_LCDEN_ENABLED_U32 \ 102 (SI32_LCD_A_CONFIG_LCDEN_ENABLED_VALUE << SI32_LCD_A_CONFIG_LCDEN_SHIFT) 103 104 #define SI32_LCD_A_CONFIG_CPFPDEN_MASK 0x00000004 105 #define SI32_LCD_A_CONFIG_CPFPDEN_SHIFT 2 106 // Disable the LCD charge pump's full power drive mode. The charge pump draws less 107 // power but operates with reduced output current capabilities. 108 #define SI32_LCD_A_CONFIG_CPFPDEN_DISABLED_VALUE 0 109 #define SI32_LCD_A_CONFIG_CPFPDEN_DISABLED_U32 \ 110 (SI32_LCD_A_CONFIG_CPFPDEN_DISABLED_VALUE << SI32_LCD_A_CONFIG_CPFPDEN_SHIFT) 111 // Enable the LCD charge pump's full output drive mode. The charge pump operates at 112 // full power. 113 #define SI32_LCD_A_CONFIG_CPFPDEN_ENABLED_VALUE 1 114 #define SI32_LCD_A_CONFIG_CPFPDEN_ENABLED_U32 \ 115 (SI32_LCD_A_CONFIG_CPFPDEN_ENABLED_VALUE << SI32_LCD_A_CONFIG_CPFPDEN_SHIFT) 116 117 #define SI32_LCD_A_CONFIG_MCDEN_MASK 0x00000008 118 #define SI32_LCD_A_CONFIG_MCDEN_SHIFT 3 119 // Disable the dedicated LCD missing clock detector. 120 #define SI32_LCD_A_CONFIG_MCDEN_DISABLED_VALUE 0 121 #define SI32_LCD_A_CONFIG_MCDEN_DISABLED_U32 \ 122 (SI32_LCD_A_CONFIG_MCDEN_DISABLED_VALUE << SI32_LCD_A_CONFIG_MCDEN_SHIFT) 123 // Enable the dedicated LCD missing clock detector. 124 #define SI32_LCD_A_CONFIG_MCDEN_ENABLED_VALUE 1 125 #define SI32_LCD_A_CONFIG_MCDEN_ENABLED_U32 \ 126 (SI32_LCD_A_CONFIG_MCDEN_ENABLED_VALUE << SI32_LCD_A_CONFIG_MCDEN_SHIFT) 127 128 #define SI32_LCD_A_CONFIG_RTCCEN_MASK 0x00000010 129 #define SI32_LCD_A_CONFIG_RTCCEN_SHIFT 4 130 // The LCD module does not require the RTC clock. 131 #define SI32_LCD_A_CONFIG_RTCCEN_DISABLED_VALUE 0 132 #define SI32_LCD_A_CONFIG_RTCCEN_DISABLED_U32 \ 133 (SI32_LCD_A_CONFIG_RTCCEN_DISABLED_VALUE << SI32_LCD_A_CONFIG_RTCCEN_SHIFT) 134 // The LCD module requires an active and valid RTC clock (RTC0TCLK). 135 #define SI32_LCD_A_CONFIG_RTCCEN_ENABLED_VALUE 1 136 #define SI32_LCD_A_CONFIG_RTCCEN_ENABLED_U32 \ 137 (SI32_LCD_A_CONFIG_RTCCEN_ENABLED_VALUE << SI32_LCD_A_CONFIG_RTCCEN_SHIFT) 138 139 #define SI32_LCD_A_CONFIG_BIASEN_MASK 0x00000020 140 #define SI32_LCD_A_CONFIG_BIASEN_SHIFT 5 141 // Disable the LCD bias current. 142 #define SI32_LCD_A_CONFIG_BIASEN_DISABLED_VALUE 0 143 #define SI32_LCD_A_CONFIG_BIASEN_DISABLED_U32 \ 144 (SI32_LCD_A_CONFIG_BIASEN_DISABLED_VALUE << SI32_LCD_A_CONFIG_BIASEN_SHIFT) 145 // Enable the LCD bias current. 146 #define SI32_LCD_A_CONFIG_BIASEN_ENABLED_VALUE 1 147 #define SI32_LCD_A_CONFIG_BIASEN_ENABLED_U32 \ 148 (SI32_LCD_A_CONFIG_BIASEN_ENABLED_VALUE << SI32_LCD_A_CONFIG_BIASEN_SHIFT) 149 150 #define SI32_LCD_A_CONFIG_DCDCBIASEN_MASK 0x00000040 151 #define SI32_LCD_A_CONFIG_DCDCBIASEN_SHIFT 6 152 // Disable the secondary bias current output. 153 #define SI32_LCD_A_CONFIG_DCDCBIASEN_DISABLED_VALUE 0 154 #define SI32_LCD_A_CONFIG_DCDCBIASEN_DISABLED_U32 \ 155 (SI32_LCD_A_CONFIG_DCDCBIASEN_DISABLED_VALUE << SI32_LCD_A_CONFIG_DCDCBIASEN_SHIFT) 156 // Enable the secondary bias current output. 157 #define SI32_LCD_A_CONFIG_DCDCBIASEN_ENABLED_VALUE 1 158 #define SI32_LCD_A_CONFIG_DCDCBIASEN_ENABLED_U32 \ 159 (SI32_LCD_A_CONFIG_DCDCBIASEN_ENABLED_VALUE << SI32_LCD_A_CONFIG_DCDCBIASEN_SHIFT) 160 161 #define SI32_LCD_A_CONFIG_DCDCSTDBYEN_MASK 0x00000080 162 #define SI32_LCD_A_CONFIG_DCDCSTDBYEN_SHIFT 7 163 // The DCDC bias is enabled in Power Mode 8. 164 #define SI32_LCD_A_CONFIG_DCDCSTDBYEN_DISABLED_VALUE 0 165 #define SI32_LCD_A_CONFIG_DCDCSTDBYEN_DISABLED_U32 \ 166 (SI32_LCD_A_CONFIG_DCDCSTDBYEN_DISABLED_VALUE << SI32_LCD_A_CONFIG_DCDCSTDBYEN_SHIFT) 167 // The DCDC bias is disabled in Power Mode 8. 168 #define SI32_LCD_A_CONFIG_DCDCSTDBYEN_ENABLED_VALUE 1 169 #define SI32_LCD_A_CONFIG_DCDCSTDBYEN_ENABLED_U32 \ 170 (SI32_LCD_A_CONFIG_DCDCSTDBYEN_ENABLED_VALUE << SI32_LCD_A_CONFIG_DCDCSTDBYEN_SHIFT) 171 172 #define SI32_LCD_A_CONFIG_CPBEN_MASK 0x00000100 173 #define SI32_LCD_A_CONFIG_CPBEN_SHIFT 8 174 // The LCD charge pump generates the VLCD voltage. 175 #define SI32_LCD_A_CONFIG_CPBEN_DISABLED_VALUE 0 176 #define SI32_LCD_A_CONFIG_CPBEN_DISABLED_U32 \ 177 (SI32_LCD_A_CONFIG_CPBEN_DISABLED_VALUE << SI32_LCD_A_CONFIG_CPBEN_SHIFT) 178 // Bypass the LCD charge pump and connect VLCD directly to VBAT. 179 #define SI32_LCD_A_CONFIG_CPBEN_ENABLED_VALUE 1 180 #define SI32_LCD_A_CONFIG_CPBEN_ENABLED_U32 \ 181 (SI32_LCD_A_CONFIG_CPBEN_ENABLED_VALUE << SI32_LCD_A_CONFIG_CPBEN_SHIFT) 182 183 #define SI32_LCD_A_CONFIG_HCVLPMEN_MASK 0x00000200 184 #define SI32_LCD_A_CONFIG_HCVLPMEN_SHIFT 9 185 // Disable the high-contrast-voltage low-power mode. 186 #define SI32_LCD_A_CONFIG_HCVLPMEN_DISABLED_VALUE 0 187 #define SI32_LCD_A_CONFIG_HCVLPMEN_DISABLED_U32 \ 188 (SI32_LCD_A_CONFIG_HCVLPMEN_DISABLED_VALUE << SI32_LCD_A_CONFIG_HCVLPMEN_SHIFT) 189 // Enable the high-contrast-voltage low-power mode. This mode reduces power 190 // consumption when VLCD is higher than VBAT. 191 #define SI32_LCD_A_CONFIG_HCVLPMEN_ENABLED_VALUE 1 192 #define SI32_LCD_A_CONFIG_HCVLPMEN_ENABLED_U32 \ 193 (SI32_LCD_A_CONFIG_HCVLPMEN_ENABLED_VALUE << SI32_LCD_A_CONFIG_HCVLPMEN_SHIFT) 194 195 #define SI32_LCD_A_CONFIG_VBMLPEN_MASK 0x00000400 196 #define SI32_LCD_A_CONFIG_VBMLPEN_SHIFT 10 197 // Disable the LCD VBAT Monitor low power mode. 198 #define SI32_LCD_A_CONFIG_VBMLPEN_DISABLED_VALUE 0 199 #define SI32_LCD_A_CONFIG_VBMLPEN_DISABLED_U32 \ 200 (SI32_LCD_A_CONFIG_VBMLPEN_DISABLED_VALUE << SI32_LCD_A_CONFIG_VBMLPEN_SHIFT) 201 // Enable the LCD VBAT Monitor low power mode. 202 #define SI32_LCD_A_CONFIG_VBMLPEN_ENABLED_VALUE 1 203 #define SI32_LCD_A_CONFIG_VBMLPEN_ENABLED_U32 \ 204 (SI32_LCD_A_CONFIG_VBMLPEN_ENABLED_VALUE << SI32_LCD_A_CONFIG_VBMLPEN_SHIFT) 205 206 #define SI32_LCD_A_CONFIG_CPOLPEN_MASK 0x00000800 207 #define SI32_LCD_A_CONFIG_CPOLPEN_SHIFT 11 208 // Disable the charge-pump oscillator low-power mode. 209 #define SI32_LCD_A_CONFIG_CPOLPEN_DISABLED_VALUE 0 210 #define SI32_LCD_A_CONFIG_CPOLPEN_DISABLED_U32 \ 211 (SI32_LCD_A_CONFIG_CPOLPEN_DISABLED_VALUE << SI32_LCD_A_CONFIG_CPOLPEN_SHIFT) 212 // Enable the charge-pump oscillator low-power mode. 213 #define SI32_LCD_A_CONFIG_CPOLPEN_ENABLED_VALUE 1 214 #define SI32_LCD_A_CONFIG_CPOLPEN_ENABLED_U32 \ 215 (SI32_LCD_A_CONFIG_CPOLPEN_ENABLED_VALUE << SI32_LCD_A_CONFIG_CPOLPEN_SHIFT) 216 217 #define SI32_LCD_A_CONFIG_CMPBLPEN_MASK 0x00001000 218 #define SI32_LCD_A_CONFIG_CMPBLPEN_SHIFT 12 219 // Disable the comparator buffer low-power mode. 220 #define SI32_LCD_A_CONFIG_CMPBLPEN_DISABLED_VALUE 0 221 #define SI32_LCD_A_CONFIG_CMPBLPEN_DISABLED_U32 \ 222 (SI32_LCD_A_CONFIG_CMPBLPEN_DISABLED_VALUE << SI32_LCD_A_CONFIG_CMPBLPEN_SHIFT) 223 // Enable the comparator buffer low-power mode. 224 #define SI32_LCD_A_CONFIG_CMPBLPEN_ENABLED_VALUE 1 225 #define SI32_LCD_A_CONFIG_CMPBLPEN_ENABLED_U32 \ 226 (SI32_LCD_A_CONFIG_CMPBLPEN_ENABLED_VALUE << SI32_LCD_A_CONFIG_CMPBLPEN_SHIFT) 227 228 #define SI32_LCD_A_CONFIG_BIASSEN_MASK 0x00002000 229 #define SI32_LCD_A_CONFIG_BIASSEN_SHIFT 13 230 // Disable bias switching. 231 #define SI32_LCD_A_CONFIG_BIASSEN_DISABLED_VALUE 0 232 #define SI32_LCD_A_CONFIG_BIASSEN_DISABLED_U32 \ 233 (SI32_LCD_A_CONFIG_BIASSEN_DISABLED_VALUE << SI32_LCD_A_CONFIG_BIASSEN_SHIFT) 234 // Enable bias switching. 235 #define SI32_LCD_A_CONFIG_BIASSEN_ENABLED_VALUE 1 236 #define SI32_LCD_A_CONFIG_BIASSEN_ENABLED_U32 \ 237 (SI32_LCD_A_CONFIG_BIASSEN_ENABLED_VALUE << SI32_LCD_A_CONFIG_BIASSEN_SHIFT) 238 239 #define SI32_LCD_A_CONFIG_RBGSEN_MASK 0x00004000 240 #define SI32_LCD_A_CONFIG_RBGSEN_SHIFT 14 241 // Disable reference band gap switching mode. 242 #define SI32_LCD_A_CONFIG_RBGSEN_DISABLED_VALUE 0 243 #define SI32_LCD_A_CONFIG_RBGSEN_DISABLED_U32 \ 244 (SI32_LCD_A_CONFIG_RBGSEN_DISABLED_VALUE << SI32_LCD_A_CONFIG_RBGSEN_SHIFT) 245 // Enable reference band gap switching mode. 246 #define SI32_LCD_A_CONFIG_RBGSEN_ENABLED_VALUE 1 247 #define SI32_LCD_A_CONFIG_RBGSEN_ENABLED_U32 \ 248 (SI32_LCD_A_CONFIG_RBGSEN_ENABLED_VALUE << SI32_LCD_A_CONFIG_RBGSEN_SHIFT) 249 250 #define SI32_LCD_A_CONFIG_CPACEN_MASK 0x00010000 251 #define SI32_LCD_A_CONFIG_CPACEN_SHIFT 16 252 // VLCD continues to track VBAT when VBAT drops below the programmed VLCD value. 253 #define SI32_LCD_A_CONFIG_CPACEN_DISABLED_VALUE 0 254 #define SI32_LCD_A_CONFIG_CPACEN_DISABLED_U32 \ 255 (SI32_LCD_A_CONFIG_CPACEN_DISABLED_VALUE << SI32_LCD_A_CONFIG_CPACEN_SHIFT) 256 // The module automatically enables the charge pump and maintains the VLCD voltage 257 // when VBAT drops below the programmed VBAT monitor level. 258 #define SI32_LCD_A_CONFIG_CPACEN_ENABLED_VALUE 1 259 #define SI32_LCD_A_CONFIG_CPACEN_ENABLED_U32 \ 260 (SI32_LCD_A_CONFIG_CPACEN_ENABLED_VALUE << SI32_LCD_A_CONFIG_CPACEN_SHIFT) 261 262 #define SI32_LCD_A_CONFIG_FBIASCEN_MASK 0x00020000 263 #define SI32_LCD_A_CONFIG_FBIASCEN_SHIFT 17 264 // The bias operates as configured. 265 #define SI32_LCD_A_CONFIG_FBIASCEN_DISABLED_VALUE 0 266 #define SI32_LCD_A_CONFIG_FBIASCEN_DISABLED_U32 \ 267 (SI32_LCD_A_CONFIG_FBIASCEN_DISABLED_VALUE << SI32_LCD_A_CONFIG_FBIASCEN_SHIFT) 268 // Force the bias to operate in continuous mode. The bias will cleanly transition 269 // from its configuration settings to continuous mode. 270 #define SI32_LCD_A_CONFIG_FBIASCEN_ENABLED_VALUE 1 271 #define SI32_LCD_A_CONFIG_FBIASCEN_ENABLED_U32 \ 272 (SI32_LCD_A_CONFIG_FBIASCEN_ENABLED_VALUE << SI32_LCD_A_CONFIG_FBIASCEN_SHIFT) 273 274 #define SI32_LCD_A_CONFIG_HCVCBYPEN_MASK 0x01000000 275 #define SI32_LCD_A_CONFIG_HCVCBYPEN_SHIFT 24 276 // Hardware enables the high-contrast-voltage comparator as needed. 277 #define SI32_LCD_A_CONFIG_HCVCBYPEN_DISABLED_VALUE 0 278 #define SI32_LCD_A_CONFIG_HCVCBYPEN_DISABLED_U32 \ 279 (SI32_LCD_A_CONFIG_HCVCBYPEN_DISABLED_VALUE << SI32_LCD_A_CONFIG_HCVCBYPEN_SHIFT) 280 // High-contrast-voltage comparator in bypass mode. 281 #define SI32_LCD_A_CONFIG_HCVCBYPEN_ENABLED_VALUE 1 282 #define SI32_LCD_A_CONFIG_HCVCBYPEN_ENABLED_U32 \ 283 (SI32_LCD_A_CONFIG_HCVCBYPEN_ENABLED_VALUE << SI32_LCD_A_CONFIG_HCVCBYPEN_SHIFT) 284 285 #define SI32_LCD_A_CONFIG_HCVCFOEN_MASK 0x02000000 286 #define SI32_LCD_A_CONFIG_HCVCFOEN_SHIFT 25 287 // Hardware enables the high-contrast-voltage comparator as needed. 288 #define SI32_LCD_A_CONFIG_HCVCFOEN_DISABLED_VALUE 0 289 #define SI32_LCD_A_CONFIG_HCVCFOEN_DISABLED_U32 \ 290 (SI32_LCD_A_CONFIG_HCVCFOEN_DISABLED_VALUE << SI32_LCD_A_CONFIG_HCVCFOEN_SHIFT) 291 // High-contrast-voltage comparator force on enabled. 292 #define SI32_LCD_A_CONFIG_HCVCFOEN_ENABLED_VALUE 1 293 #define SI32_LCD_A_CONFIG_HCVCFOEN_ENABLED_U32 \ 294 (SI32_LCD_A_CONFIG_HCVCFOEN_ENABLED_VALUE << SI32_LCD_A_CONFIG_HCVCFOEN_SHIFT) 295 296 #define SI32_LCD_A_CONFIG_HCVCHMD_MASK 0x04000000 297 #define SI32_LCD_A_CONFIG_HCVCHMD_SHIFT 26 298 // Set the high-contrast-voltage comparator to high-hysteresis mode. This is the 299 // recommended setting. 300 #define SI32_LCD_A_CONFIG_HCVCHMD_HIGH_VALUE 0 301 #define SI32_LCD_A_CONFIG_HCVCHMD_HIGH_U32 \ 302 (SI32_LCD_A_CONFIG_HCVCHMD_HIGH_VALUE << SI32_LCD_A_CONFIG_HCVCHMD_SHIFT) 303 // Set the high-contrast-voltage comparator to low-hysteresis mode. 304 #define SI32_LCD_A_CONFIG_HCVCHMD_LOW_VALUE 1 305 #define SI32_LCD_A_CONFIG_HCVCHMD_LOW_U32 \ 306 (SI32_LCD_A_CONFIG_HCVCHMD_LOW_VALUE << SI32_LCD_A_CONFIG_HCVCHMD_SHIFT) 307 308 #define SI32_LCD_A_CONFIG_HCVCBMD_MASK 0x08000000 309 #define SI32_LCD_A_CONFIG_HCVCBMD_SHIFT 27 310 // Set the high-contrast-voltage comparator to high bias mode. 311 #define SI32_LCD_A_CONFIG_HCVCBMD_HIGH_VALUE 0 312 #define SI32_LCD_A_CONFIG_HCVCBMD_HIGH_U32 \ 313 (SI32_LCD_A_CONFIG_HCVCBMD_HIGH_VALUE << SI32_LCD_A_CONFIG_HCVCBMD_SHIFT) 314 // Set the high-contrast-voltage comparator to low-bias mode. This is the 315 // recommended setting. 316 #define SI32_LCD_A_CONFIG_HCVCBMD_LOW_VALUE 1 317 #define SI32_LCD_A_CONFIG_HCVCBMD_LOW_U32 \ 318 (SI32_LCD_A_CONFIG_HCVCBMD_LOW_VALUE << SI32_LCD_A_CONFIG_HCVCBMD_SHIFT) 319 320 #define SI32_LCD_A_CONFIG_CPCS_MASK 0x40000000 321 #define SI32_LCD_A_CONFIG_CPCS_SHIFT 30 322 // VBAT is greater than VLCD. 323 #define SI32_LCD_A_CONFIG_CPCS_VBAT_VALUE 0 324 #define SI32_LCD_A_CONFIG_CPCS_VBAT_U32 \ 325 (SI32_LCD_A_CONFIG_CPCS_VBAT_VALUE << SI32_LCD_A_CONFIG_CPCS_SHIFT) 326 // VLCD is greater than VBAT. 327 #define SI32_LCD_A_CONFIG_CPCS_VLCD_VALUE 1 328 #define SI32_LCD_A_CONFIG_CPCS_VLCD_U32 \ 329 (SI32_LCD_A_CONFIG_CPCS_VLCD_VALUE << SI32_LCD_A_CONFIG_CPCS_SHIFT) 330 331 332 333 struct SI32_LCD_A_CLKCONTROL_Struct 334 { 335 union 336 { 337 struct 338 { 339 // Clock Divider 340 volatile uint32_t CLKDIV: 10; 341 uint32_t reserved0: 18; 342 // RTC Input Clock Divider 343 volatile uint32_t RTCCLKDIV: 2; 344 uint32_t reserved1: 2; 345 }; 346 volatile uint32_t U32; 347 }; 348 }; 349 350 #define SI32_LCD_A_CLKCONTROL_CLKDIV_MASK 0x000003FF 351 #define SI32_LCD_A_CLKCONTROL_CLKDIV_SHIFT 0 352 353 #define SI32_LCD_A_CLKCONTROL_RTCCLKDIV_MASK 0x30000000 354 #define SI32_LCD_A_CLKCONTROL_RTCCLKDIV_SHIFT 28 355 #define SI32_LCD_A_CLKCONTROL_RTCCLKDIV_DIVIDE_BY_1_VALUE 0 356 #define SI32_LCD_A_CLKCONTROL_RTCCLKDIV_DIVIDE_BY_1_U32 \ 357 (SI32_LCD_A_CLKCONTROL_RTCCLKDIV_DIVIDE_BY_1_VALUE << SI32_LCD_A_CLKCONTROL_RTCCLKDIV_SHIFT) 358 #define SI32_LCD_A_CLKCONTROL_RTCCLKDIV_DIVIDE_BY_2_VALUE 1 359 #define SI32_LCD_A_CLKCONTROL_RTCCLKDIV_DIVIDE_BY_2_U32 \ 360 (SI32_LCD_A_CLKCONTROL_RTCCLKDIV_DIVIDE_BY_2_VALUE << SI32_LCD_A_CLKCONTROL_RTCCLKDIV_SHIFT) 361 #define SI32_LCD_A_CLKCONTROL_RTCCLKDIV_DIVIDE_BY_4_VALUE 2 362 #define SI32_LCD_A_CLKCONTROL_RTCCLKDIV_DIVIDE_BY_4_U32 \ 363 (SI32_LCD_A_CLKCONTROL_RTCCLKDIV_DIVIDE_BY_4_VALUE << SI32_LCD_A_CLKCONTROL_RTCCLKDIV_SHIFT) 364 #define SI32_LCD_A_CLKCONTROL_RTCCLKDIV_DIVIDE_BY_8_VALUE 3 365 #define SI32_LCD_A_CLKCONTROL_RTCCLKDIV_DIVIDE_BY_8_U32 \ 366 (SI32_LCD_A_CLKCONTROL_RTCCLKDIV_DIVIDE_BY_8_VALUE << SI32_LCD_A_CLKCONTROL_RTCCLKDIV_SHIFT) 367 368 369 370 struct SI32_LCD_A_BLKCONTROL_Struct 371 { 372 union 373 { 374 struct 375 { 376 // Hardware Blinking Enable 377 volatile uint8_t BLKMASK; 378 // Hardware Blinking Rate Divider Exponent 379 volatile uint32_t BLKREXP: 4; 380 uint32_t reserved0: 20; 381 }; 382 volatile uint32_t U32; 383 }; 384 }; 385 386 #define SI32_LCD_A_BLKCONTROL_BLKMASK_MASK 0x000000FF 387 #define SI32_LCD_A_BLKCONTROL_BLKMASK_SHIFT 0 388 389 #define SI32_LCD_A_BLKCONTROL_BLKREXP_MASK 0x00000F00 390 #define SI32_LCD_A_BLKCONTROL_BLKREXP_SHIFT 8 391 // Set blink rate divider to divide by 2. 392 #define SI32_LCD_A_BLKCONTROL_BLKREXP_DIVIDE_BY_2_VALUE 2 393 #define SI32_LCD_A_BLKCONTROL_BLKREXP_DIVIDE_BY_2_U32 \ 394 (SI32_LCD_A_BLKCONTROL_BLKREXP_DIVIDE_BY_2_VALUE << SI32_LCD_A_BLKCONTROL_BLKREXP_SHIFT) 395 // Set blink rate divider to divide by 4. 396 #define SI32_LCD_A_BLKCONTROL_BLKREXP_DIVIDE_BY_4_VALUE 3 397 #define SI32_LCD_A_BLKCONTROL_BLKREXP_DIVIDE_BY_4_U32 \ 398 (SI32_LCD_A_BLKCONTROL_BLKREXP_DIVIDE_BY_4_VALUE << SI32_LCD_A_BLKCONTROL_BLKREXP_SHIFT) 399 // Set blink rate divider to divide by 8. 400 #define SI32_LCD_A_BLKCONTROL_BLKREXP_DIVIDE_BY_8_VALUE 4 401 #define SI32_LCD_A_BLKCONTROL_BLKREXP_DIVIDE_BY_8_U32 \ 402 (SI32_LCD_A_BLKCONTROL_BLKREXP_DIVIDE_BY_8_VALUE << SI32_LCD_A_BLKCONTROL_BLKREXP_SHIFT) 403 // Set blink rate divider to divide by 16. 404 #define SI32_LCD_A_BLKCONTROL_BLKREXP_DIVIDE_BY_16_VALUE 5 405 #define SI32_LCD_A_BLKCONTROL_BLKREXP_DIVIDE_BY_16_U32 \ 406 (SI32_LCD_A_BLKCONTROL_BLKREXP_DIVIDE_BY_16_VALUE << SI32_LCD_A_BLKCONTROL_BLKREXP_SHIFT) 407 // Set blink rate divider to divide by 32. 408 #define SI32_LCD_A_BLKCONTROL_BLKREXP_DIVIDE_BY_32_VALUE 6 409 #define SI32_LCD_A_BLKCONTROL_BLKREXP_DIVIDE_BY_32_U32 \ 410 (SI32_LCD_A_BLKCONTROL_BLKREXP_DIVIDE_BY_32_VALUE << SI32_LCD_A_BLKCONTROL_BLKREXP_SHIFT) 411 // Set blink rate divider to divide by 64. 412 #define SI32_LCD_A_BLKCONTROL_BLKREXP_DIVIDE_BY_64_VALUE 7 413 #define SI32_LCD_A_BLKCONTROL_BLKREXP_DIVIDE_BY_64_U32 \ 414 (SI32_LCD_A_BLKCONTROL_BLKREXP_DIVIDE_BY_64_VALUE << SI32_LCD_A_BLKCONTROL_BLKREXP_SHIFT) 415 // Set blink rate divider to divide by 128. 416 #define SI32_LCD_A_BLKCONTROL_BLKREXP_DIVIDE_BY_128_VALUE 8 417 #define SI32_LCD_A_BLKCONTROL_BLKREXP_DIVIDE_BY_128_U32 \ 418 (SI32_LCD_A_BLKCONTROL_BLKREXP_DIVIDE_BY_128_VALUE << SI32_LCD_A_BLKCONTROL_BLKREXP_SHIFT) 419 // Set blink rate divider to divide by 256. 420 #define SI32_LCD_A_BLKCONTROL_BLKREXP_DIVIDE_BY_256_VALUE 9 421 #define SI32_LCD_A_BLKCONTROL_BLKREXP_DIVIDE_BY_256_U32 \ 422 (SI32_LCD_A_BLKCONTROL_BLKREXP_DIVIDE_BY_256_VALUE << SI32_LCD_A_BLKCONTROL_BLKREXP_SHIFT) 423 // Set blink rate divider to divide by 512. 424 #define SI32_LCD_A_BLKCONTROL_BLKREXP_DIVIDE_BY_512_VALUE 10 425 #define SI32_LCD_A_BLKCONTROL_BLKREXP_DIVIDE_BY_512_U32 \ 426 (SI32_LCD_A_BLKCONTROL_BLKREXP_DIVIDE_BY_512_VALUE << SI32_LCD_A_BLKCONTROL_BLKREXP_SHIFT) 427 // Set blink rate divider to divide by 1024. 428 #define SI32_LCD_A_BLKCONTROL_BLKREXP_DIVIDE_BY_1024_VALUE 11 429 #define SI32_LCD_A_BLKCONTROL_BLKREXP_DIVIDE_BY_1024_U32 \ 430 (SI32_LCD_A_BLKCONTROL_BLKREXP_DIVIDE_BY_1024_VALUE << SI32_LCD_A_BLKCONTROL_BLKREXP_SHIFT) 431 // Set blink rate divider to divide by 2048. 432 #define SI32_LCD_A_BLKCONTROL_BLKREXP_DIVIDE_BY_2048_VALUE 12 433 #define SI32_LCD_A_BLKCONTROL_BLKREXP_DIVIDE_BY_2048_U32 \ 434 (SI32_LCD_A_BLKCONTROL_BLKREXP_DIVIDE_BY_2048_VALUE << SI32_LCD_A_BLKCONTROL_BLKREXP_SHIFT) 435 // Set blink rate divider to divide by 4096. 436 #define SI32_LCD_A_BLKCONTROL_BLKREXP_DIVIDE_BY_4096_VALUE 13 437 #define SI32_LCD_A_BLKCONTROL_BLKREXP_DIVIDE_BY_4096_U32 \ 438 (SI32_LCD_A_BLKCONTROL_BLKREXP_DIVIDE_BY_4096_VALUE << SI32_LCD_A_BLKCONTROL_BLKREXP_SHIFT) 439 440 441 442 struct SI32_LCD_A_SEGCONTROL_Struct 443 { 444 union 445 { 446 struct 447 { 448 // Hardware Bias Mode 449 volatile uint32_t BIASMD: 1; 450 // Segment Mode 451 volatile uint32_t SEGMD: 2; 452 uint32_t reserved0: 1; 453 // Segment Blank Enable 454 volatile uint32_t BLANKEN: 1; 455 // Reset Phase Enable 456 volatile uint32_t RPHEN: 1; 457 // Reset Phase Mode 458 volatile uint32_t RPHMD: 3; 459 uint32_t reserved1: 23; 460 }; 461 volatile uint32_t U32; 462 }; 463 }; 464 465 #define SI32_LCD_A_SEGCONTROL_BIASMD_MASK 0x00000001 466 #define SI32_LCD_A_SEGCONTROL_BIASMD_SHIFT 0 467 // Select 1/3 bias. Use for three-mux segment mode and four-mux segment mode. 468 #define SI32_LCD_A_SEGCONTROL_BIASMD_ONE_THIRD_VALUE 0 469 #define SI32_LCD_A_SEGCONTROL_BIASMD_ONE_THIRD_U32 \ 470 (SI32_LCD_A_SEGCONTROL_BIASMD_ONE_THIRD_VALUE << SI32_LCD_A_SEGCONTROL_BIASMD_SHIFT) 471 // Select 1/2 bias. Use for two-mux segment mode. 472 #define SI32_LCD_A_SEGCONTROL_BIASMD_ONE_HALF_VALUE 1 473 #define SI32_LCD_A_SEGCONTROL_BIASMD_ONE_HALF_U32 \ 474 (SI32_LCD_A_SEGCONTROL_BIASMD_ONE_HALF_VALUE << SI32_LCD_A_SEGCONTROL_BIASMD_SHIFT) 475 476 #define SI32_LCD_A_SEGCONTROL_SEGMD_MASK 0x00000006 477 #define SI32_LCD_A_SEGCONTROL_SEGMD_SHIFT 1 478 // Select static segment mode with one common COMn.0 used. 479 #define SI32_LCD_A_SEGCONTROL_SEGMD_STATIC_VALUE 0 480 #define SI32_LCD_A_SEGCONTROL_SEGMD_STATIC_U32 \ 481 (SI32_LCD_A_SEGCONTROL_SEGMD_STATIC_VALUE << SI32_LCD_A_SEGCONTROL_SEGMD_SHIFT) 482 // Select two-mux segment mode with two commons (COMn.0 and COMn.1) used. 483 #define SI32_LCD_A_SEGCONTROL_SEGMD_2_MUX_VALUE 1 484 #define SI32_LCD_A_SEGCONTROL_SEGMD_2_MUX_U32 \ 485 (SI32_LCD_A_SEGCONTROL_SEGMD_2_MUX_VALUE << SI32_LCD_A_SEGCONTROL_SEGMD_SHIFT) 486 // Select three-mux segment mode with three commons (COMn.0, COMn.1, COMn.2) used. 487 #define SI32_LCD_A_SEGCONTROL_SEGMD_3_MUX_VALUE 2 488 #define SI32_LCD_A_SEGCONTROL_SEGMD_3_MUX_U32 \ 489 (SI32_LCD_A_SEGCONTROL_SEGMD_3_MUX_VALUE << SI32_LCD_A_SEGCONTROL_SEGMD_SHIFT) 490 // Select four-mux segment mode with four commons (COMn.0, COMn.1, COMn.2 and 491 // COMn.3) used. 492 #define SI32_LCD_A_SEGCONTROL_SEGMD_4_MUX_VALUE 3 493 #define SI32_LCD_A_SEGCONTROL_SEGMD_4_MUX_U32 \ 494 (SI32_LCD_A_SEGCONTROL_SEGMD_4_MUX_VALUE << SI32_LCD_A_SEGCONTROL_SEGMD_SHIFT) 495 496 #define SI32_LCD_A_SEGCONTROL_BLANKEN_MASK 0x00000010 497 #define SI32_LCD_A_SEGCONTROL_BLANKEN_SHIFT 4 498 // Operate segments normally. 499 #define SI32_LCD_A_SEGCONTROL_BLANKEN_DISABLED_VALUE 0 500 #define SI32_LCD_A_SEGCONTROL_BLANKEN_DISABLED_U32 \ 501 (SI32_LCD_A_SEGCONTROL_BLANKEN_DISABLED_VALUE << SI32_LCD_A_SEGCONTROL_BLANKEN_SHIFT) 502 // Blank the LCD by disabling all LCD segment and common pins. 503 #define SI32_LCD_A_SEGCONTROL_BLANKEN_ENABLED_VALUE 1 504 #define SI32_LCD_A_SEGCONTROL_BLANKEN_ENABLED_U32 \ 505 (SI32_LCD_A_SEGCONTROL_BLANKEN_ENABLED_VALUE << SI32_LCD_A_SEGCONTROL_BLANKEN_SHIFT) 506 507 #define SI32_LCD_A_SEGCONTROL_RPHEN_MASK 0x00000020 508 #define SI32_LCD_A_SEGCONTROL_RPHEN_SHIFT 5 509 // Hardware switches the LCD segment and common pin controls directly from one 510 // state to another. 511 #define SI32_LCD_A_SEGCONTROL_RPHEN_DISABLED_VALUE 0 512 #define SI32_LCD_A_SEGCONTROL_RPHEN_DISABLED_U32 \ 513 (SI32_LCD_A_SEGCONTROL_RPHEN_DISABLED_VALUE << SI32_LCD_A_SEGCONTROL_RPHEN_SHIFT) 514 // Hardware switches the LCD segment and common pin controls to intermediate states 515 // for several RTC clock cycles before switching to the next state. 516 #define SI32_LCD_A_SEGCONTROL_RPHEN_ENABLED_VALUE 1 517 #define SI32_LCD_A_SEGCONTROL_RPHEN_ENABLED_U32 \ 518 (SI32_LCD_A_SEGCONTROL_RPHEN_ENABLED_VALUE << SI32_LCD_A_SEGCONTROL_RPHEN_SHIFT) 519 520 #define SI32_LCD_A_SEGCONTROL_RPHMD_MASK 0x000001C0 521 #define SI32_LCD_A_SEGCONTROL_RPHMD_SHIFT 6 522 523 524 525 struct SI32_LCD_A_CTRSTCONTROL_Struct 526 { 527 union 528 { 529 struct 530 { 531 // Contrast Voltage 532 volatile uint32_t CTRST: 5; 533 uint32_t reserved0: 11; 534 // Contrast Busy Flag 535 volatile uint32_t CTRSTBF: 1; 536 uint32_t reserved1: 12; 537 // Charge Pump Capacitor Divider Enable 538 volatile uint32_t CPCDEN: 1; 539 uint32_t reserved2: 2; 540 }; 541 volatile uint32_t U32; 542 }; 543 }; 544 545 #define SI32_LCD_A_CTRSTCONTROL_CTRST_MASK 0x0000001F 546 #define SI32_LCD_A_CTRSTCONTROL_CTRST_SHIFT 0 547 548 #define SI32_LCD_A_CTRSTCONTROL_CTRSTBF_MASK 0x00010000 549 #define SI32_LCD_A_CTRSTCONTROL_CTRSTBF_SHIFT 16 550 // An update of the internal contrast registers is not in progress. 551 #define SI32_LCD_A_CTRSTCONTROL_CTRSTBF_NOT_SET_VALUE 0 552 #define SI32_LCD_A_CTRSTCONTROL_CTRSTBF_NOT_SET_U32 \ 553 (SI32_LCD_A_CTRSTCONTROL_CTRSTBF_NOT_SET_VALUE << SI32_LCD_A_CTRSTCONTROL_CTRSTBF_SHIFT) 554 // The internal contrast registers are busy updating. 555 #define SI32_LCD_A_CTRSTCONTROL_CTRSTBF_SET_VALUE 1 556 #define SI32_LCD_A_CTRSTCONTROL_CTRSTBF_SET_U32 \ 557 (SI32_LCD_A_CTRSTCONTROL_CTRSTBF_SET_VALUE << SI32_LCD_A_CTRSTCONTROL_CTRSTBF_SHIFT) 558 559 #define SI32_LCD_A_CTRSTCONTROL_CPCDEN_MASK 0x20000000 560 #define SI32_LCD_A_CTRSTCONTROL_CPCDEN_SHIFT 29 561 // Disable the charge pump capacitor divider. 562 #define SI32_LCD_A_CTRSTCONTROL_CPCDEN_DISABLED_VALUE 0 563 #define SI32_LCD_A_CTRSTCONTROL_CPCDEN_DISABLED_U32 \ 564 (SI32_LCD_A_CTRSTCONTROL_CPCDEN_DISABLED_VALUE << SI32_LCD_A_CTRSTCONTROL_CPCDEN_SHIFT) 565 // Enable the charge pump capacitor divider. 566 #define SI32_LCD_A_CTRSTCONTROL_CPCDEN_ENABLED_VALUE 1 567 #define SI32_LCD_A_CTRSTCONTROL_CPCDEN_ENABLED_U32 \ 568 (SI32_LCD_A_CTRSTCONTROL_CPCDEN_ENABLED_VALUE << SI32_LCD_A_CTRSTCONTROL_CPCDEN_SHIFT) 569 570 571 572 struct SI32_LCD_A_VBMCONTROL_Struct 573 { 574 union 575 { 576 struct 577 { 578 // VBAT Monitor Threshold 579 volatile uint32_t VBMTH: 5; 580 uint32_t reserved0: 11; 581 // VBAT Monitor Busy Flag 582 volatile uint32_t VBMBF: 1; 583 uint32_t reserved1: 5; 584 // VBAT Monitor Clock Divider 585 volatile uint32_t VBMCLKDIV: 3; 586 uint32_t reserved2: 4; 587 // VBAT Monitor Capacitor Divider Enable 588 volatile uint32_t VBMCDEN: 1; 589 // VBAT Monitor Offset Enable 590 volatile uint32_t VBMOEN: 1; 591 // VBAT Monitor Enable 592 volatile uint32_t VBMEN: 1; 593 }; 594 volatile uint32_t U32; 595 }; 596 }; 597 598 #define SI32_LCD_A_VBMCONTROL_VBMTH_MASK 0x0000001F 599 #define SI32_LCD_A_VBMCONTROL_VBMTH_SHIFT 0 600 601 #define SI32_LCD_A_VBMCONTROL_VBMBF_MASK 0x00010000 602 #define SI32_LCD_A_VBMCONTROL_VBMBF_SHIFT 16 603 // An update of the internal VBAT monitor registers is not in progress. 604 #define SI32_LCD_A_VBMCONTROL_VBMBF_NOT_SET_VALUE 0 605 #define SI32_LCD_A_VBMCONTROL_VBMBF_NOT_SET_U32 \ 606 (SI32_LCD_A_VBMCONTROL_VBMBF_NOT_SET_VALUE << SI32_LCD_A_VBMCONTROL_VBMBF_SHIFT) 607 // The internal VBAT monitor registers are busy updating. 608 #define SI32_LCD_A_VBMCONTROL_VBMBF_SET_VALUE 1 609 #define SI32_LCD_A_VBMCONTROL_VBMBF_SET_U32 \ 610 (SI32_LCD_A_VBMCONTROL_VBMBF_SET_VALUE << SI32_LCD_A_VBMCONTROL_VBMBF_SHIFT) 611 612 #define SI32_LCD_A_VBMCONTROL_VBMCLKDIV_MASK 0x01C00000 613 #define SI32_LCD_A_VBMCONTROL_VBMCLKDIV_SHIFT 22 614 615 #define SI32_LCD_A_VBMCONTROL_VBMCDEN_MASK 0x20000000 616 #define SI32_LCD_A_VBMCONTROL_VBMCDEN_SHIFT 29 617 // Disable the VBAT monitor capacitor divider. 618 #define SI32_LCD_A_VBMCONTROL_VBMCDEN_DISABLED_VALUE 0 619 #define SI32_LCD_A_VBMCONTROL_VBMCDEN_DISABLED_U32 \ 620 (SI32_LCD_A_VBMCONTROL_VBMCDEN_DISABLED_VALUE << SI32_LCD_A_VBMCONTROL_VBMCDEN_SHIFT) 621 // Enable the VBAT monitor capacitor divider. 622 #define SI32_LCD_A_VBMCONTROL_VBMCDEN_ENABLED_VALUE 1 623 #define SI32_LCD_A_VBMCONTROL_VBMCDEN_ENABLED_U32 \ 624 (SI32_LCD_A_VBMCONTROL_VBMCDEN_ENABLED_VALUE << SI32_LCD_A_VBMCONTROL_VBMCDEN_SHIFT) 625 626 #define SI32_LCD_A_VBMCONTROL_VBMOEN_MASK 0x40000000 627 #define SI32_LCD_A_VBMCONTROL_VBMOEN_SHIFT 30 628 // The VBAT monitor threshold set by the VBMTH field functions as an absolute 629 // threshold value for the VBAT monitor. 630 #define SI32_LCD_A_VBMCONTROL_VBMOEN_DISABLED_VALUE 0 631 #define SI32_LCD_A_VBMCONTROL_VBMOEN_DISABLED_U32 \ 632 (SI32_LCD_A_VBMCONTROL_VBMOEN_DISABLED_VALUE << SI32_LCD_A_VBMCONTROL_VBMOEN_SHIFT) 633 // The VBAT monitor threshold set by the VBMTH field functions as an offset to the 634 // LCD contrast value set by CTRSTMD. 635 #define SI32_LCD_A_VBMCONTROL_VBMOEN_ENABLED_VALUE 1 636 #define SI32_LCD_A_VBMCONTROL_VBMOEN_ENABLED_U32 \ 637 (SI32_LCD_A_VBMCONTROL_VBMOEN_ENABLED_VALUE << SI32_LCD_A_VBMCONTROL_VBMOEN_SHIFT) 638 639 #define SI32_LCD_A_VBMCONTROL_VBMEN_MASK 0x80000000 640 #define SI32_LCD_A_VBMCONTROL_VBMEN_SHIFT 31 641 // Disable the VBAT monitor. 642 #define SI32_LCD_A_VBMCONTROL_VBMEN_DISABLED_VALUE 0U 643 #define SI32_LCD_A_VBMCONTROL_VBMEN_DISABLED_U32 \ 644 (SI32_LCD_A_VBMCONTROL_VBMEN_DISABLED_VALUE << SI32_LCD_A_VBMCONTROL_VBMEN_SHIFT) 645 // Enable the VBAT monitor. 646 #define SI32_LCD_A_VBMCONTROL_VBMEN_ENABLED_VALUE 1U 647 #define SI32_LCD_A_VBMCONTROL_VBMEN_ENABLED_U32 \ 648 (SI32_LCD_A_VBMCONTROL_VBMEN_ENABLED_VALUE << SI32_LCD_A_VBMCONTROL_VBMEN_SHIFT) 649 650 651 652 struct SI32_LCD_A_SEGMASK0_Struct 653 { 654 union 655 { 656 struct 657 { 658 // Segment Enable 659 volatile uint32_t SEGEN; 660 }; 661 volatile uint32_t U32; 662 }; 663 }; 664 665 #define SI32_LCD_A_SEGMASK0_SEGEN_MASK 0xFFFFFFFF 666 #define SI32_LCD_A_SEGMASK0_SEGEN_SHIFT 0 667 668 669 670 struct SI32_LCD_A_SEGMASK1_Struct 671 { 672 union 673 { 674 struct 675 { 676 // Segment Enable 677 volatile uint8_t SEGEN; 678 uint32_t reserved0: 24; 679 }; 680 volatile uint32_t U32; 681 }; 682 }; 683 684 #define SI32_LCD_A_SEGMASK1_SEGEN_MASK 0x000000FF 685 #define SI32_LCD_A_SEGMASK1_SEGEN_SHIFT 0 686 687 688 689 struct SI32_LCD_A_SEGDATA0_Struct 690 { 691 union 692 { 693 // This is a Union register 694 volatile uint8_t U8[4]; 695 volatile uint16_t U16[2]; 696 volatile uint32_t U32; 697 }; 698 }; 699 700 #define SI32_LCD_A_SEGDATA0_SEGPIN0_MASK 0x0000000F 701 #define SI32_LCD_A_SEGDATA0_SEGPIN0_SHIFT 0 702 703 #define SI32_LCD_A_SEGDATA0_SEGPIN1_MASK 0x000000F0 704 #define SI32_LCD_A_SEGDATA0_SEGPIN1_SHIFT 4 705 706 #define SI32_LCD_A_SEGDATA0_SEGPIN2_MASK 0x00000F00 707 #define SI32_LCD_A_SEGDATA0_SEGPIN2_SHIFT 8 708 709 #define SI32_LCD_A_SEGDATA0_SEGPIN3_MASK 0x0000F000 710 #define SI32_LCD_A_SEGDATA0_SEGPIN3_SHIFT 12 711 712 #define SI32_LCD_A_SEGDATA0_SEGPIN4_MASK 0x000F0000 713 #define SI32_LCD_A_SEGDATA0_SEGPIN4_SHIFT 16 714 715 #define SI32_LCD_A_SEGDATA0_SEGPIN5_MASK 0x00F00000 716 #define SI32_LCD_A_SEGDATA0_SEGPIN5_SHIFT 20 717 718 #define SI32_LCD_A_SEGDATA0_SEGPIN6_MASK 0x0F000000 719 #define SI32_LCD_A_SEGDATA0_SEGPIN6_SHIFT 24 720 721 #define SI32_LCD_A_SEGDATA0_SEGPIN7_MASK 0xF0000000 722 #define SI32_LCD_A_SEGDATA0_SEGPIN7_SHIFT 28 723 724 725 726 struct SI32_LCD_A_SEGDATA1_Struct 727 { 728 union 729 { 730 // This is a Union register 731 volatile uint8_t U8[4]; 732 volatile uint16_t U16[2]; 733 volatile uint32_t U32; 734 }; 735 }; 736 737 #define SI32_LCD_A_SEGDATA1_SEGPIN8_MASK 0x0000000F 738 #define SI32_LCD_A_SEGDATA1_SEGPIN8_SHIFT 0 739 740 #define SI32_LCD_A_SEGDATA1_SEGPIN9_MASK 0x000000F0 741 #define SI32_LCD_A_SEGDATA1_SEGPIN9_SHIFT 4 742 743 #define SI32_LCD_A_SEGDATA1_SEGPIN10_MASK 0x00000F00 744 #define SI32_LCD_A_SEGDATA1_SEGPIN10_SHIFT 8 745 746 #define SI32_LCD_A_SEGDATA1_SEGPIN11_MASK 0x0000F000 747 #define SI32_LCD_A_SEGDATA1_SEGPIN11_SHIFT 12 748 749 #define SI32_LCD_A_SEGDATA1_SEGPIN12_MASK 0x000F0000 750 #define SI32_LCD_A_SEGDATA1_SEGPIN12_SHIFT 16 751 752 #define SI32_LCD_A_SEGDATA1_SEGPIN13_MASK 0x00F00000 753 #define SI32_LCD_A_SEGDATA1_SEGPIN13_SHIFT 20 754 755 #define SI32_LCD_A_SEGDATA1_SEGPIN14_MASK 0x0F000000 756 #define SI32_LCD_A_SEGDATA1_SEGPIN14_SHIFT 24 757 758 #define SI32_LCD_A_SEGDATA1_SEGPIN15_MASK 0xF0000000 759 #define SI32_LCD_A_SEGDATA1_SEGPIN15_SHIFT 28 760 761 762 763 struct SI32_LCD_A_SEGDATA2_Struct 764 { 765 union 766 { 767 // This is a Union register 768 volatile uint8_t U8[4]; 769 volatile uint16_t U16[2]; 770 volatile uint32_t U32; 771 }; 772 }; 773 774 #define SI32_LCD_A_SEGDATA2_SEGPIN16_MASK 0x0000000F 775 #define SI32_LCD_A_SEGDATA2_SEGPIN16_SHIFT 0 776 777 #define SI32_LCD_A_SEGDATA2_SEGPIN17_MASK 0x000000F0 778 #define SI32_LCD_A_SEGDATA2_SEGPIN17_SHIFT 4 779 780 #define SI32_LCD_A_SEGDATA2_SEGPIN18_MASK 0x00000F00 781 #define SI32_LCD_A_SEGDATA2_SEGPIN18_SHIFT 8 782 783 #define SI32_LCD_A_SEGDATA2_SEGPIN19_MASK 0x0000F000 784 #define SI32_LCD_A_SEGDATA2_SEGPIN19_SHIFT 12 785 786 #define SI32_LCD_A_SEGDATA2_SEGPIN20_MASK 0x000F0000 787 #define SI32_LCD_A_SEGDATA2_SEGPIN20_SHIFT 16 788 789 #define SI32_LCD_A_SEGDATA2_SEGPIN21_MASK 0x00F00000 790 #define SI32_LCD_A_SEGDATA2_SEGPIN21_SHIFT 20 791 792 #define SI32_LCD_A_SEGDATA2_SEGPIN22_MASK 0x0F000000 793 #define SI32_LCD_A_SEGDATA2_SEGPIN22_SHIFT 24 794 795 #define SI32_LCD_A_SEGDATA2_SEGPIN23_MASK 0xF0000000 796 #define SI32_LCD_A_SEGDATA2_SEGPIN23_SHIFT 28 797 798 799 800 struct SI32_LCD_A_SEGDATA3_Struct 801 { 802 union 803 { 804 // This is a Union register 805 volatile uint8_t U8[4]; 806 volatile uint16_t U16[2]; 807 volatile uint32_t U32; 808 }; 809 }; 810 811 #define SI32_LCD_A_SEGDATA3_SEGPIN24_MASK 0x0000000F 812 #define SI32_LCD_A_SEGDATA3_SEGPIN24_SHIFT 0 813 814 #define SI32_LCD_A_SEGDATA3_SEGPIN25_MASK 0x000000F0 815 #define SI32_LCD_A_SEGDATA3_SEGPIN25_SHIFT 4 816 817 #define SI32_LCD_A_SEGDATA3_SEGPIN26_MASK 0x00000F00 818 #define SI32_LCD_A_SEGDATA3_SEGPIN26_SHIFT 8 819 820 #define SI32_LCD_A_SEGDATA3_SEGPIN27_MASK 0x0000F000 821 #define SI32_LCD_A_SEGDATA3_SEGPIN27_SHIFT 12 822 823 #define SI32_LCD_A_SEGDATA3_SEGPIN28_MASK 0x000F0000 824 #define SI32_LCD_A_SEGDATA3_SEGPIN28_SHIFT 16 825 826 #define SI32_LCD_A_SEGDATA3_SEGPIN29_MASK 0x00F00000 827 #define SI32_LCD_A_SEGDATA3_SEGPIN29_SHIFT 20 828 829 #define SI32_LCD_A_SEGDATA3_SEGPIN30_MASK 0x0F000000 830 #define SI32_LCD_A_SEGDATA3_SEGPIN30_SHIFT 24 831 832 #define SI32_LCD_A_SEGDATA3_SEGPIN31_MASK 0xF0000000 833 #define SI32_LCD_A_SEGDATA3_SEGPIN31_SHIFT 28 834 835 836 837 struct SI32_LCD_A_SEGDATA4_Struct 838 { 839 union 840 { 841 // This is a Union register 842 volatile uint8_t U8[4]; 843 volatile uint16_t U16[2]; 844 volatile uint32_t U32; 845 }; 846 }; 847 848 #define SI32_LCD_A_SEGDATA4_SEGPIN32_MASK 0x0000000F 849 #define SI32_LCD_A_SEGDATA4_SEGPIN32_SHIFT 0 850 851 #define SI32_LCD_A_SEGDATA4_SEGPIN33_MASK 0x000000F0 852 #define SI32_LCD_A_SEGDATA4_SEGPIN33_SHIFT 4 853 854 #define SI32_LCD_A_SEGDATA4_SEGPIN34_MASK 0x00000F00 855 #define SI32_LCD_A_SEGDATA4_SEGPIN34_SHIFT 8 856 857 #define SI32_LCD_A_SEGDATA4_SEGPIN35_MASK 0x0000F000 858 #define SI32_LCD_A_SEGDATA4_SEGPIN35_SHIFT 12 859 860 #define SI32_LCD_A_SEGDATA4_SEGPIN36_MASK 0x000F0000 861 #define SI32_LCD_A_SEGDATA4_SEGPIN36_SHIFT 16 862 863 #define SI32_LCD_A_SEGDATA4_SEGPIN37_MASK 0x00F00000 864 #define SI32_LCD_A_SEGDATA4_SEGPIN37_SHIFT 20 865 866 #define SI32_LCD_A_SEGDATA4_SEGPIN38_MASK 0x0F000000 867 #define SI32_LCD_A_SEGDATA4_SEGPIN38_SHIFT 24 868 869 #define SI32_LCD_A_SEGDATA4_SEGPIN39_MASK 0xF0000000 870 #define SI32_LCD_A_SEGDATA4_SEGPIN39_SHIFT 28 871 872 873 874 typedef struct SI32_LCD_A_Struct 875 { 876 struct SI32_LCD_A_CONFIG_Struct CONFIG ; // Base Address + 0x0 877 volatile uint32_t CONFIG_SET; 878 volatile uint32_t CONFIG_CLR; 879 uint32_t reserved0; 880 uint32_t reserved1[4]; 881 struct SI32_LCD_A_CLKCONTROL_Struct CLKCONTROL ; // Base Address + 0x20 882 uint32_t reserved2; 883 uint32_t reserved3; 884 uint32_t reserved4; 885 struct SI32_LCD_A_BLKCONTROL_Struct BLKCONTROL ; // Base Address + 0x30 886 uint32_t reserved5; 887 uint32_t reserved6; 888 uint32_t reserved7; 889 struct SI32_LCD_A_SEGCONTROL_Struct SEGCONTROL ; // Base Address + 0x40 890 uint32_t reserved8; 891 uint32_t reserved9; 892 uint32_t reserved10; 893 uint32_t reserved11[4]; 894 struct SI32_LCD_A_CTRSTCONTROL_Struct CTRSTCONTROL ; // Base Address + 0x60 895 uint32_t reserved12; 896 uint32_t reserved13; 897 uint32_t reserved14; 898 struct SI32_LCD_A_VBMCONTROL_Struct VBMCONTROL ; // Base Address + 0x70 899 uint32_t reserved15; 900 uint32_t reserved16; 901 uint32_t reserved17; 902 struct SI32_LCD_A_SEGMASK0_Struct SEGMASK0 ; // Base Address + 0x80 903 volatile uint32_t SEGMASK0_SET; 904 volatile uint32_t SEGMASK0_CLR; 905 uint32_t reserved18; 906 struct SI32_LCD_A_SEGMASK1_Struct SEGMASK1 ; // Base Address + 0x90 907 volatile uint32_t SEGMASK1_SET; 908 volatile uint32_t SEGMASK1_CLR; 909 uint32_t reserved19; 910 struct SI32_LCD_A_SEGDATA0_Struct SEGDATA0 ; // Base Address + 0xa0 911 uint32_t reserved20; 912 uint32_t reserved21; 913 uint32_t reserved22; 914 struct SI32_LCD_A_SEGDATA1_Struct SEGDATA1 ; // Base Address + 0xb0 915 uint32_t reserved23; 916 uint32_t reserved24; 917 uint32_t reserved25; 918 struct SI32_LCD_A_SEGDATA2_Struct SEGDATA2 ; // Base Address + 0xc0 919 uint32_t reserved26; 920 uint32_t reserved27; 921 uint32_t reserved28; 922 struct SI32_LCD_A_SEGDATA3_Struct SEGDATA3 ; // Base Address + 0xd0 923 uint32_t reserved29; 924 uint32_t reserved30; 925 uint32_t reserved31; 926 struct SI32_LCD_A_SEGDATA4_Struct SEGDATA4 ; // Base Address + 0xe0 927 uint32_t reserved32; 928 uint32_t reserved33; 929 uint32_t reserved34; 930 uint32_t reserved35[4]; 931 uint32_t reserved36[4]; 932 } SI32_LCD_A_Type; 933 934 #ifdef __cplusplus 935 } 936 #endif 937 938 #endif // __SI32_LCD_A_REGISTERS_H__ 939 940 //-eof-------------------------------------------------------------------------- 941 942
