1 //------------------------------------------------------------------------------ 2 // Copyright 2012 (c) Silicon Laboratories Inc. 3 // 4 // SPDX-License-Identifier: Zlib 5 // 6 // This siHAL software is provided 'as-is', without any express or implied 7 // warranty. In no event will the authors be held liable for any damages 8 // arising from the use of this software. 9 // 10 // Permission is granted to anyone to use this software for any purpose, 11 // including commercial applications, and to alter it and redistribute it 12 // freely, subject to the following restrictions: 13 // 14 // 1. The origin of this software must not be misrepresented; you must not 15 // claim that you wrote the original software. If you use this software 16 // in a product, an acknowledgment in the product documentation would be 17 // appreciated but is not required. 18 // 2. Altered source versions must be plainly marked as such, and must not be 19 // misrepresented as being the original software. 20 // 3. This notice may not be removed or altered from any source distribution. 21 //------------------------------------------------------------------------------ 22 // 23 // Script: 0.57 24 // Version: 1 25 26 #ifndef __SI32_IVC_A_REGISTERS_H__ 27 #define __SI32_IVC_A_REGISTERS_H__ 28 29 #include <stdint.h> 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 struct SI32_IVC_A_CONTROL_Struct 36 { 37 union 38 { 39 struct 40 { 41 // Input 0 Range 42 volatile uint32_t IN0RANGE: 3; 43 uint32_t reserved0: 1; 44 // Input 1 Range 45 volatile uint32_t IN1RANGE: 3; 46 uint32_t reserved1: 23; 47 // Converter 0 Enable 48 volatile uint32_t C0EN: 1; 49 // Converter 1 Enable 50 volatile uint32_t C1EN: 1; 51 }; 52 volatile uint32_t U32; 53 }; 54 }; 55 56 #define SI32_IVC_A_CONTROL_IN0RANGE_MASK 0x00000007 57 #define SI32_IVC_A_CONTROL_IN0RANGE_SHIFT 0 58 // Input range is 0-6 mA. 59 #define SI32_IVC_A_CONTROL_IN0RANGE_6_MA_VALUE 0 60 #define SI32_IVC_A_CONTROL_IN0RANGE_6_MA_U32 \ 61 (SI32_IVC_A_CONTROL_IN0RANGE_6_MA_VALUE << SI32_IVC_A_CONTROL_IN0RANGE_SHIFT) 62 // Input range is 0-5 mA. 63 #define SI32_IVC_A_CONTROL_IN0RANGE_5_MA_VALUE 1 64 #define SI32_IVC_A_CONTROL_IN0RANGE_5_MA_U32 \ 65 (SI32_IVC_A_CONTROL_IN0RANGE_5_MA_VALUE << SI32_IVC_A_CONTROL_IN0RANGE_SHIFT) 66 // Input range is 0-4 mA. 67 #define SI32_IVC_A_CONTROL_IN0RANGE_4_MA_VALUE 2 68 #define SI32_IVC_A_CONTROL_IN0RANGE_4_MA_U32 \ 69 (SI32_IVC_A_CONTROL_IN0RANGE_4_MA_VALUE << SI32_IVC_A_CONTROL_IN0RANGE_SHIFT) 70 // Input range is 0-3 mA. 71 #define SI32_IVC_A_CONTROL_IN0RANGE_3_MA_VALUE 3 72 #define SI32_IVC_A_CONTROL_IN0RANGE_3_MA_U32 \ 73 (SI32_IVC_A_CONTROL_IN0RANGE_3_MA_VALUE << SI32_IVC_A_CONTROL_IN0RANGE_SHIFT) 74 // Input range is 0-2 mA. 75 #define SI32_IVC_A_CONTROL_IN0RANGE_2_MA_VALUE 4 76 #define SI32_IVC_A_CONTROL_IN0RANGE_2_MA_U32 \ 77 (SI32_IVC_A_CONTROL_IN0RANGE_2_MA_VALUE << SI32_IVC_A_CONTROL_IN0RANGE_SHIFT) 78 // Input range is 0-1 mA. 79 #define SI32_IVC_A_CONTROL_IN0RANGE_1_MA_VALUE 5 80 #define SI32_IVC_A_CONTROL_IN0RANGE_1_MA_U32 \ 81 (SI32_IVC_A_CONTROL_IN0RANGE_1_MA_VALUE << SI32_IVC_A_CONTROL_IN0RANGE_SHIFT) 82 83 #define SI32_IVC_A_CONTROL_IN1RANGE_MASK 0x00000070 84 #define SI32_IVC_A_CONTROL_IN1RANGE_SHIFT 4 85 // Input range is 0-6 mA. 86 #define SI32_IVC_A_CONTROL_IN1RANGE_6_MA_VALUE 0 87 #define SI32_IVC_A_CONTROL_IN1RANGE_6_MA_U32 \ 88 (SI32_IVC_A_CONTROL_IN1RANGE_6_MA_VALUE << SI32_IVC_A_CONTROL_IN1RANGE_SHIFT) 89 // Input range is 0-5 mA. 90 #define SI32_IVC_A_CONTROL_IN1RANGE_5_MA_VALUE 1 91 #define SI32_IVC_A_CONTROL_IN1RANGE_5_MA_U32 \ 92 (SI32_IVC_A_CONTROL_IN1RANGE_5_MA_VALUE << SI32_IVC_A_CONTROL_IN1RANGE_SHIFT) 93 // Input range is 0-4 mA. 94 #define SI32_IVC_A_CONTROL_IN1RANGE_4_MA_VALUE 2 95 #define SI32_IVC_A_CONTROL_IN1RANGE_4_MA_U32 \ 96 (SI32_IVC_A_CONTROL_IN1RANGE_4_MA_VALUE << SI32_IVC_A_CONTROL_IN1RANGE_SHIFT) 97 // Input range is 0-3 mA. 98 #define SI32_IVC_A_CONTROL_IN1RANGE_3_MA_VALUE 3 99 #define SI32_IVC_A_CONTROL_IN1RANGE_3_MA_U32 \ 100 (SI32_IVC_A_CONTROL_IN1RANGE_3_MA_VALUE << SI32_IVC_A_CONTROL_IN1RANGE_SHIFT) 101 // Input range is 0-2 mA. 102 #define SI32_IVC_A_CONTROL_IN1RANGE_2_MA_VALUE 4 103 #define SI32_IVC_A_CONTROL_IN1RANGE_2_MA_U32 \ 104 (SI32_IVC_A_CONTROL_IN1RANGE_2_MA_VALUE << SI32_IVC_A_CONTROL_IN1RANGE_SHIFT) 105 // Input range is 0-1 mA. 106 #define SI32_IVC_A_CONTROL_IN1RANGE_1_MA_VALUE 5 107 #define SI32_IVC_A_CONTROL_IN1RANGE_1_MA_U32 \ 108 (SI32_IVC_A_CONTROL_IN1RANGE_1_MA_VALUE << SI32_IVC_A_CONTROL_IN1RANGE_SHIFT) 109 110 #define SI32_IVC_A_CONTROL_C0EN_MASK 0x40000000 111 #define SI32_IVC_A_CONTROL_C0EN_SHIFT 30 112 // Disable IVC channel 0. 113 #define SI32_IVC_A_CONTROL_C0EN_DISABLED_VALUE 0 114 #define SI32_IVC_A_CONTROL_C0EN_DISABLED_U32 \ 115 (SI32_IVC_A_CONTROL_C0EN_DISABLED_VALUE << SI32_IVC_A_CONTROL_C0EN_SHIFT) 116 // Enable IVC channel 0. 117 #define SI32_IVC_A_CONTROL_C0EN_ENABLED_VALUE 1 118 #define SI32_IVC_A_CONTROL_C0EN_ENABLED_U32 \ 119 (SI32_IVC_A_CONTROL_C0EN_ENABLED_VALUE << SI32_IVC_A_CONTROL_C0EN_SHIFT) 120 121 #define SI32_IVC_A_CONTROL_C1EN_MASK 0x80000000 122 #define SI32_IVC_A_CONTROL_C1EN_SHIFT 31 123 // Disable IVC channel 1. 124 #define SI32_IVC_A_CONTROL_C1EN_DISABLED_VALUE 0U 125 #define SI32_IVC_A_CONTROL_C1EN_DISABLED_U32 \ 126 (SI32_IVC_A_CONTROL_C1EN_DISABLED_VALUE << SI32_IVC_A_CONTROL_C1EN_SHIFT) 127 // Enable IVC channel 1. 128 #define SI32_IVC_A_CONTROL_C1EN_ENABLED_VALUE 1U 129 #define SI32_IVC_A_CONTROL_C1EN_ENABLED_U32 \ 130 (SI32_IVC_A_CONTROL_C1EN_ENABLED_VALUE << SI32_IVC_A_CONTROL_C1EN_SHIFT) 131 132 133 134 typedef struct SI32_IVC_A_Struct 135 { 136 struct SI32_IVC_A_CONTROL_Struct CONTROL ; // Base Address + 0x0 137 volatile uint32_t CONTROL_SET; 138 volatile uint32_t CONTROL_CLR; 139 uint32_t reserved0; 140 uint32_t reserved1[4]; 141 } SI32_IVC_A_Type; 142 143 #ifdef __cplusplus 144 } 145 #endif 146 147 #endif // __SI32_IVC_A_REGISTERS_H__ 148 149 //-eof-------------------------------------------------------------------------- 150 151
