1 //----------------------------------------------------------------------------- 2 // Copyright 2012 (c) Silicon Laboratories Inc. 3 // 4 // SPDX-License-Identifier: Zlib 5 // 6 // This siHAL software is provided 'as-is', without any express or implied 7 // warranty. In no event will the authors be held liable for any damages 8 // arising from the use of this software. 9 // 10 // Permission is granted to anyone to use this software for any purpose, 11 // including commercial applications, and to alter it and redistribute it 12 // freely, subject to the following restrictions: 13 // 14 // 1. The origin of this software must not be misrepresented; you must not 15 // claim that you wrote the original software. If you use this software 16 // in a product, an acknowledgment in the product documentation would be 17 // appreciated but is not required. 18 // 2. Altered source versions must be plainly marked as such, and must not be 19 // misrepresented as being the original software. 20 // 3. This notice may not be removed or altered from any source distribution. 21 //----------------------------------------------------------------------------- 22 // 23 // Script: 0.61 24 // Version: 1 25 26 #ifndef __SI32_IDAC_A_REGISTERS_H__ 27 #define __SI32_IDAC_A_REGISTERS_H__ 28 29 #include <stdint.h> 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 struct SI32_IDAC_A_CONTROL_Struct 36 { 37 union 38 { 39 struct 40 { 41 // Output Update Trigger 42 volatile uint32_t OUPDT: 3; 43 // Edge Trigger Source Select 44 volatile uint32_t ETRIG: 3; 45 // Output Mode 46 volatile uint32_t OUTMD: 2; 47 // Data Input Format 48 volatile uint32_t INFMT: 2; 49 // DMA Run 50 volatile uint32_t DMARUN: 1; 51 // Data Justification Select 52 volatile uint32_t JSEL: 1; 53 // Data Buffer Reset 54 volatile uint32_t BUFRESET: 1; 55 // Trigger Source Inhibit 56 volatile uint32_t TRIGINH: 1; 57 uint32_t reserved0: 2; 58 // Wrap Mode Enable 59 volatile uint32_t WRAPEN: 1; 60 uint32_t reserved1: 3; 61 // FIFO Overrun Interrupt Enable 62 volatile uint32_t ORIEN: 1; 63 // FIFO Underrun Interrupt Enable 64 volatile uint32_t URIEN: 1; 65 // FIFO Went Empty Interrupt Enable 66 volatile uint32_t WEIEN: 1; 67 uint32_t reserved2: 6; 68 // IDAC Debug Mode 69 volatile uint32_t DBGMD: 1; 70 // Load Resistor Enable 71 volatile uint32_t LOADEN: 1; 72 // IDAC Enable 73 volatile uint32_t IDACEN: 1; 74 }; 75 volatile uint32_t U32; 76 }; 77 }; 78 79 #define SI32_IDAC_A_CONTROL_OUPDT_MASK 0x00000007 80 #define SI32_IDAC_A_CONTROL_OUPDT_SHIFT 0 81 // The IDAC output updates using the DACnT8 trigger source. 82 #define SI32_IDAC_A_CONTROL_OUPDT_DACNT8_VALUE 0 83 #define SI32_IDAC_A_CONTROL_OUPDT_DACNT8_U32 \ 84 (SI32_IDAC_A_CONTROL_OUPDT_DACNT8_VALUE << SI32_IDAC_A_CONTROL_OUPDT_SHIFT) 85 // The IDAC output updates using the DACnT9 trigger source. 86 #define SI32_IDAC_A_CONTROL_OUPDT_DACNT9_VALUE 1 87 #define SI32_IDAC_A_CONTROL_OUPDT_DACNT9_U32 \ 88 (SI32_IDAC_A_CONTROL_OUPDT_DACNT9_VALUE << SI32_IDAC_A_CONTROL_OUPDT_SHIFT) 89 // The IDAC output updates using the DACnT10 trigger source. 90 #define SI32_IDAC_A_CONTROL_OUPDT_DACNT10_VALUE 2 91 #define SI32_IDAC_A_CONTROL_OUPDT_DACNT10_U32 \ 92 (SI32_IDAC_A_CONTROL_OUPDT_DACNT10_VALUE << SI32_IDAC_A_CONTROL_OUPDT_SHIFT) 93 // The IDAC output updates using the DACnT11 trigger source. 94 #define SI32_IDAC_A_CONTROL_OUPDT_DACNT11_VALUE 3 95 #define SI32_IDAC_A_CONTROL_OUPDT_DACNT11_U32 \ 96 (SI32_IDAC_A_CONTROL_OUPDT_DACNT11_VALUE << SI32_IDAC_A_CONTROL_OUPDT_SHIFT) 97 // The IDAC output updates on the rising edge of the trigger source selected by 98 // ETRIG. 99 #define SI32_IDAC_A_CONTROL_OUPDT_DACNT12_VALUE 4 100 #define SI32_IDAC_A_CONTROL_OUPDT_DACNT12_U32 \ 101 (SI32_IDAC_A_CONTROL_OUPDT_DACNT12_VALUE << SI32_IDAC_A_CONTROL_OUPDT_SHIFT) 102 // The IDAC output updates on the falling edge of the trigger source selected by 103 // ETRIG. 104 #define SI32_IDAC_A_CONTROL_OUPDT_DACNT13_VALUE 5 105 #define SI32_IDAC_A_CONTROL_OUPDT_DACNT13_U32 \ 106 (SI32_IDAC_A_CONTROL_OUPDT_DACNT13_VALUE << SI32_IDAC_A_CONTROL_OUPDT_SHIFT) 107 // The IDAC output updates on any edge of the trigger source selected by ETRIG. 108 #define SI32_IDAC_A_CONTROL_OUPDT_DACNT14_VALUE 6 109 #define SI32_IDAC_A_CONTROL_OUPDT_DACNT14_U32 \ 110 (SI32_IDAC_A_CONTROL_OUPDT_DACNT14_VALUE << SI32_IDAC_A_CONTROL_OUPDT_SHIFT) 111 // The IDAC output updates on write to DATA register (On Demand). 112 #define SI32_IDAC_A_CONTROL_OUPDT_DACNT15_VALUE 7 113 #define SI32_IDAC_A_CONTROL_OUPDT_DACNT15_U32 \ 114 (SI32_IDAC_A_CONTROL_OUPDT_DACNT15_VALUE << SI32_IDAC_A_CONTROL_OUPDT_SHIFT) 115 116 #define SI32_IDAC_A_CONTROL_ETRIG_MASK 0x00000038 117 #define SI32_IDAC_A_CONTROL_ETRIG_SHIFT 3 118 // Select DACnT0 as the IDAC external trigger source. 119 #define SI32_IDAC_A_CONTROL_ETRIG_DACNT0_VALUE 0 120 #define SI32_IDAC_A_CONTROL_ETRIG_DACNT0_U32 \ 121 (SI32_IDAC_A_CONTROL_ETRIG_DACNT0_VALUE << SI32_IDAC_A_CONTROL_ETRIG_SHIFT) 122 // Select DACnT1 as the IDAC external trigger source. 123 #define SI32_IDAC_A_CONTROL_ETRIG_DACNT1_VALUE 1 124 #define SI32_IDAC_A_CONTROL_ETRIG_DACNT1_U32 \ 125 (SI32_IDAC_A_CONTROL_ETRIG_DACNT1_VALUE << SI32_IDAC_A_CONTROL_ETRIG_SHIFT) 126 // Select DACnT2 as the IDAC external trigger source. 127 #define SI32_IDAC_A_CONTROL_ETRIG_DACNT2_VALUE 2 128 #define SI32_IDAC_A_CONTROL_ETRIG_DACNT2_U32 \ 129 (SI32_IDAC_A_CONTROL_ETRIG_DACNT2_VALUE << SI32_IDAC_A_CONTROL_ETRIG_SHIFT) 130 // Select DACnT3 as the IDAC external trigger source. 131 #define SI32_IDAC_A_CONTROL_ETRIG_DACNT3_VALUE 3 132 #define SI32_IDAC_A_CONTROL_ETRIG_DACNT3_U32 \ 133 (SI32_IDAC_A_CONTROL_ETRIG_DACNT3_VALUE << SI32_IDAC_A_CONTROL_ETRIG_SHIFT) 134 // Select DACnT4 as the IDAC external trigger source. 135 #define SI32_IDAC_A_CONTROL_ETRIG_DACNT4_VALUE 4 136 #define SI32_IDAC_A_CONTROL_ETRIG_DACNT4_U32 \ 137 (SI32_IDAC_A_CONTROL_ETRIG_DACNT4_VALUE << SI32_IDAC_A_CONTROL_ETRIG_SHIFT) 138 // Select DACnT5 as the IDAC external trigger source. 139 #define SI32_IDAC_A_CONTROL_ETRIG_DACNT5_VALUE 5 140 #define SI32_IDAC_A_CONTROL_ETRIG_DACNT5_U32 \ 141 (SI32_IDAC_A_CONTROL_ETRIG_DACNT5_VALUE << SI32_IDAC_A_CONTROL_ETRIG_SHIFT) 142 // Select DACnT6 as the IDAC external trigger source. 143 #define SI32_IDAC_A_CONTROL_ETRIG_DACNT6_VALUE 6 144 #define SI32_IDAC_A_CONTROL_ETRIG_DACNT6_U32 \ 145 (SI32_IDAC_A_CONTROL_ETRIG_DACNT6_VALUE << SI32_IDAC_A_CONTROL_ETRIG_SHIFT) 146 // Select DACnT7 as the IDAC external trigger source. 147 #define SI32_IDAC_A_CONTROL_ETRIG_DACNT7_VALUE 7 148 #define SI32_IDAC_A_CONTROL_ETRIG_DACNT7_U32 \ 149 (SI32_IDAC_A_CONTROL_ETRIG_DACNT7_VALUE << SI32_IDAC_A_CONTROL_ETRIG_SHIFT) 150 151 #define SI32_IDAC_A_CONTROL_OUTMD_MASK 0x000000C0 152 #define SI32_IDAC_A_CONTROL_OUTMD_SHIFT 6 153 // The full-scale output current is 0.5 mA. 154 #define SI32_IDAC_A_CONTROL_OUTMD_0P5_MA_VALUE 0 155 #define SI32_IDAC_A_CONTROL_OUTMD_0P5_MA_U32 \ 156 (SI32_IDAC_A_CONTROL_OUTMD_0P5_MA_VALUE << SI32_IDAC_A_CONTROL_OUTMD_SHIFT) 157 // The full-scale output current is 1 mA. 158 #define SI32_IDAC_A_CONTROL_OUTMD_1_MA_VALUE 1 159 #define SI32_IDAC_A_CONTROL_OUTMD_1_MA_U32 \ 160 (SI32_IDAC_A_CONTROL_OUTMD_1_MA_VALUE << SI32_IDAC_A_CONTROL_OUTMD_SHIFT) 161 // The full-scale output current is 2 mA. 162 #define SI32_IDAC_A_CONTROL_OUTMD_2_MA_VALUE 2 163 #define SI32_IDAC_A_CONTROL_OUTMD_2_MA_U32 \ 164 (SI32_IDAC_A_CONTROL_OUTMD_2_MA_VALUE << SI32_IDAC_A_CONTROL_OUTMD_SHIFT) 165 166 #define SI32_IDAC_A_CONTROL_INFMT_MASK 0x00000300 167 #define SI32_IDAC_A_CONTROL_INFMT_SHIFT 8 168 // Writes are interpreted as one 10-bit sample. 169 #define SI32_IDAC_A_CONTROL_INFMT_1_10_BIT_VALUE 0 170 #define SI32_IDAC_A_CONTROL_INFMT_1_10_BIT_U32 \ 171 (SI32_IDAC_A_CONTROL_INFMT_1_10_BIT_VALUE << SI32_IDAC_A_CONTROL_INFMT_SHIFT) 172 // Writes are interpreted as two 10-bit samples. 173 #define SI32_IDAC_A_CONTROL_INFMT_2_10_BIT_VALUE 1 174 #define SI32_IDAC_A_CONTROL_INFMT_2_10_BIT_U32 \ 175 (SI32_IDAC_A_CONTROL_INFMT_2_10_BIT_VALUE << SI32_IDAC_A_CONTROL_INFMT_SHIFT) 176 // Writes are interpreted as four 8-bit samples. 177 #define SI32_IDAC_A_CONTROL_INFMT_4_8_BIT_VALUE 2 178 #define SI32_IDAC_A_CONTROL_INFMT_4_8_BIT_U32 \ 179 (SI32_IDAC_A_CONTROL_INFMT_4_8_BIT_VALUE << SI32_IDAC_A_CONTROL_INFMT_SHIFT) 180 181 #define SI32_IDAC_A_CONTROL_DMARUN_MASK 0x00000400 182 #define SI32_IDAC_A_CONTROL_DMARUN_SHIFT 10 183 // Read: No DMA operations are occurring or the DMA is done. Write: No effect. 184 #define SI32_IDAC_A_CONTROL_DMARUN_DISABLED_VALUE 0 185 #define SI32_IDAC_A_CONTROL_DMARUN_DISABLED_U32 \ 186 (SI32_IDAC_A_CONTROL_DMARUN_DISABLED_VALUE << SI32_IDAC_A_CONTROL_DMARUN_SHIFT) 187 // Read: A DMA operation is currently in progress. Write: Start a DMA operation. 188 #define SI32_IDAC_A_CONTROL_DMARUN_ENABLED_VALUE 1 189 #define SI32_IDAC_A_CONTROL_DMARUN_ENABLED_U32 \ 190 (SI32_IDAC_A_CONTROL_DMARUN_ENABLED_VALUE << SI32_IDAC_A_CONTROL_DMARUN_SHIFT) 191 192 #define SI32_IDAC_A_CONTROL_JSEL_MASK 0x00000800 193 #define SI32_IDAC_A_CONTROL_JSEL_SHIFT 11 194 // Data is right-justified. 195 #define SI32_IDAC_A_CONTROL_JSEL_RIGHT_VALUE 0 196 #define SI32_IDAC_A_CONTROL_JSEL_RIGHT_U32 \ 197 (SI32_IDAC_A_CONTROL_JSEL_RIGHT_VALUE << SI32_IDAC_A_CONTROL_JSEL_SHIFT) 198 // Data is left-justified. 199 #define SI32_IDAC_A_CONTROL_JSEL_LEFT_VALUE 1 200 #define SI32_IDAC_A_CONTROL_JSEL_LEFT_U32 \ 201 (SI32_IDAC_A_CONTROL_JSEL_LEFT_VALUE << SI32_IDAC_A_CONTROL_JSEL_SHIFT) 202 203 #define SI32_IDAC_A_CONTROL_BUFRESET_MASK 0x00001000 204 #define SI32_IDAC_A_CONTROL_BUFRESET_SHIFT 12 205 // Initiate a data buffer reset. 206 #define SI32_IDAC_A_CONTROL_BUFRESET_RESET_VALUE 1 207 #define SI32_IDAC_A_CONTROL_BUFRESET_RESET_U32 \ 208 (SI32_IDAC_A_CONTROL_BUFRESET_RESET_VALUE << SI32_IDAC_A_CONTROL_BUFRESET_SHIFT) 209 210 #define SI32_IDAC_A_CONTROL_TRIGINH_MASK 0x00002000 211 #define SI32_IDAC_A_CONTROL_TRIGINH_SHIFT 13 212 // The selected trigger source will cause the IDAC output to update. 213 #define SI32_IDAC_A_CONTROL_TRIGINH_INACTIVE_VALUE 0 214 #define SI32_IDAC_A_CONTROL_TRIGINH_INACTIVE_U32 \ 215 (SI32_IDAC_A_CONTROL_TRIGINH_INACTIVE_VALUE << SI32_IDAC_A_CONTROL_TRIGINH_SHIFT) 216 // The selected trigger source will not update the IDAC output, except for On- 217 // Demand DATA writes. 218 #define SI32_IDAC_A_CONTROL_TRIGINH_ACTIVE_VALUE 1 219 #define SI32_IDAC_A_CONTROL_TRIGINH_ACTIVE_U32 \ 220 (SI32_IDAC_A_CONTROL_TRIGINH_ACTIVE_VALUE << SI32_IDAC_A_CONTROL_TRIGINH_SHIFT) 221 222 #define SI32_IDAC_A_CONTROL_WRAPEN_MASK 0x00010000 223 #define SI32_IDAC_A_CONTROL_WRAPEN_SHIFT 16 224 // The IDAC will not wrap when it reaches the end of the data buffer. 225 #define SI32_IDAC_A_CONTROL_WRAPEN_DISABLED_VALUE 0 226 #define SI32_IDAC_A_CONTROL_WRAPEN_DISABLED_U32 \ 227 (SI32_IDAC_A_CONTROL_WRAPEN_DISABLED_VALUE << SI32_IDAC_A_CONTROL_WRAPEN_SHIFT) 228 // The IDAC will cycle through the data buffer contents. 229 #define SI32_IDAC_A_CONTROL_WRAPEN_ENABLED_VALUE 1 230 #define SI32_IDAC_A_CONTROL_WRAPEN_ENABLED_U32 \ 231 (SI32_IDAC_A_CONTROL_WRAPEN_ENABLED_VALUE << SI32_IDAC_A_CONTROL_WRAPEN_SHIFT) 232 233 #define SI32_IDAC_A_CONTROL_ORIEN_MASK 0x00100000 234 #define SI32_IDAC_A_CONTROL_ORIEN_SHIFT 20 235 // Disable the FIFO overrun interrupt (ORI). 236 #define SI32_IDAC_A_CONTROL_ORIEN_DISABLED_VALUE 0 237 #define SI32_IDAC_A_CONTROL_ORIEN_DISABLED_U32 \ 238 (SI32_IDAC_A_CONTROL_ORIEN_DISABLED_VALUE << SI32_IDAC_A_CONTROL_ORIEN_SHIFT) 239 // Enable the FIFO overrun interrupt (ORI). 240 #define SI32_IDAC_A_CONTROL_ORIEN_ENABLED_VALUE 1 241 #define SI32_IDAC_A_CONTROL_ORIEN_ENABLED_U32 \ 242 (SI32_IDAC_A_CONTROL_ORIEN_ENABLED_VALUE << SI32_IDAC_A_CONTROL_ORIEN_SHIFT) 243 244 #define SI32_IDAC_A_CONTROL_URIEN_MASK 0x00200000 245 #define SI32_IDAC_A_CONTROL_URIEN_SHIFT 21 246 // Disable the FIFO underrun interrupt (URI). 247 #define SI32_IDAC_A_CONTROL_URIEN_DISABLED_VALUE 0 248 #define SI32_IDAC_A_CONTROL_URIEN_DISABLED_U32 \ 249 (SI32_IDAC_A_CONTROL_URIEN_DISABLED_VALUE << SI32_IDAC_A_CONTROL_URIEN_SHIFT) 250 // Enable the FIFO underrun interrupt (URI). 251 #define SI32_IDAC_A_CONTROL_URIEN_ENABLED_VALUE 1 252 #define SI32_IDAC_A_CONTROL_URIEN_ENABLED_U32 \ 253 (SI32_IDAC_A_CONTROL_URIEN_ENABLED_VALUE << SI32_IDAC_A_CONTROL_URIEN_SHIFT) 254 255 #define SI32_IDAC_A_CONTROL_WEIEN_MASK 0x00400000 256 #define SI32_IDAC_A_CONTROL_WEIEN_SHIFT 22 257 // Disable the FIFO went empty interrupt (WEI). 258 #define SI32_IDAC_A_CONTROL_WEIEN_DISABLED_VALUE 0 259 #define SI32_IDAC_A_CONTROL_WEIEN_DISABLED_U32 \ 260 (SI32_IDAC_A_CONTROL_WEIEN_DISABLED_VALUE << SI32_IDAC_A_CONTROL_WEIEN_SHIFT) 261 // Enable the FIFO went empty interrupt (WEI). 262 #define SI32_IDAC_A_CONTROL_WEIEN_ENABLED_VALUE 1 263 #define SI32_IDAC_A_CONTROL_WEIEN_ENABLED_U32 \ 264 (SI32_IDAC_A_CONTROL_WEIEN_ENABLED_VALUE << SI32_IDAC_A_CONTROL_WEIEN_SHIFT) 265 266 #define SI32_IDAC_A_CONTROL_DBGMD_MASK 0x20000000 267 #define SI32_IDAC_A_CONTROL_DBGMD_SHIFT 29 268 // The IDAC module will continue to operate while the core is halted in debug mode. 269 #define SI32_IDAC_A_CONTROL_DBGMD_RUN_VALUE 0 270 #define SI32_IDAC_A_CONTROL_DBGMD_RUN_U32 \ 271 (SI32_IDAC_A_CONTROL_DBGMD_RUN_VALUE << SI32_IDAC_A_CONTROL_DBGMD_SHIFT) 272 // A debug breakpoint will cause the IDAC module to halt (ignore update triggers). 273 #define SI32_IDAC_A_CONTROL_DBGMD_HALT_VALUE 1 274 #define SI32_IDAC_A_CONTROL_DBGMD_HALT_U32 \ 275 (SI32_IDAC_A_CONTROL_DBGMD_HALT_VALUE << SI32_IDAC_A_CONTROL_DBGMD_SHIFT) 276 277 #define SI32_IDAC_A_CONTROL_LOADEN_MASK 0x40000000 278 #define SI32_IDAC_A_CONTROL_LOADEN_SHIFT 30 279 // Disable the internal load resistor. 280 #define SI32_IDAC_A_CONTROL_LOADEN_DISABLED_VALUE 0 281 #define SI32_IDAC_A_CONTROL_LOADEN_DISABLED_U32 \ 282 (SI32_IDAC_A_CONTROL_LOADEN_DISABLED_VALUE << SI32_IDAC_A_CONTROL_LOADEN_SHIFT) 283 // Enable the internal load resistor. 284 #define SI32_IDAC_A_CONTROL_LOADEN_ENABLED_VALUE 1 285 #define SI32_IDAC_A_CONTROL_LOADEN_ENABLED_U32 \ 286 (SI32_IDAC_A_CONTROL_LOADEN_ENABLED_VALUE << SI32_IDAC_A_CONTROL_LOADEN_SHIFT) 287 288 #define SI32_IDAC_A_CONTROL_IDACEN_MASK 0x80000000 289 #define SI32_IDAC_A_CONTROL_IDACEN_SHIFT 31 290 // Disable the IDAC. 291 #define SI32_IDAC_A_CONTROL_IDACEN_DISABLED_VALUE 0U 292 #define SI32_IDAC_A_CONTROL_IDACEN_DISABLED_U32 \ 293 (SI32_IDAC_A_CONTROL_IDACEN_DISABLED_VALUE << SI32_IDAC_A_CONTROL_IDACEN_SHIFT) 294 // Enable the IDAC. 295 #define SI32_IDAC_A_CONTROL_IDACEN_ENABLED_VALUE 1U 296 #define SI32_IDAC_A_CONTROL_IDACEN_ENABLED_U32 \ 297 (SI32_IDAC_A_CONTROL_IDACEN_ENABLED_VALUE << SI32_IDAC_A_CONTROL_IDACEN_SHIFT) 298 299 300 301 struct SI32_IDAC_A_DATA_Struct 302 { 303 union 304 { 305 struct 306 { 307 // Output Data 308 volatile uint32_t DATA_BITS; 309 }; 310 volatile uint32_t U32; 311 }; 312 }; 313 314 #define SI32_IDAC_A_DATA_DATA_MASK 0xFFFFFFFF 315 #define SI32_IDAC_A_DATA_DATA_SHIFT 0 316 317 318 319 struct SI32_IDAC_A_BUFSTATUS_Struct 320 { 321 union 322 { 323 struct 324 { 325 // FIFO Level 326 volatile uint32_t LEVEL: 3; 327 uint32_t reserved0: 1; 328 // FIFO Overrun Interrupt Flag 329 volatile uint32_t ORI: 1; 330 // FIFO Underrun Interrupt Flag 331 volatile uint32_t URI: 1; 332 // FIFO Went Empty Interrupt Flag 333 volatile uint32_t WEI: 1; 334 uint32_t reserved1: 25; 335 }; 336 volatile uint32_t U32; 337 }; 338 }; 339 340 #define SI32_IDAC_A_BUFSTATUS_LEVEL_MASK 0x00000007 341 #define SI32_IDAC_A_BUFSTATUS_LEVEL_SHIFT 0 342 // The data FIFO is empty. 343 #define SI32_IDAC_A_BUFSTATUS_LEVEL_EMPTY_VALUE 0 344 #define SI32_IDAC_A_BUFSTATUS_LEVEL_EMPTY_U32 \ 345 (SI32_IDAC_A_BUFSTATUS_LEVEL_EMPTY_VALUE << SI32_IDAC_A_BUFSTATUS_LEVEL_SHIFT) 346 // The data FIFO contains one word. 347 #define SI32_IDAC_A_BUFSTATUS_LEVEL_1WORD_VALUE 1 348 #define SI32_IDAC_A_BUFSTATUS_LEVEL_1WORD_U32 \ 349 (SI32_IDAC_A_BUFSTATUS_LEVEL_1WORD_VALUE << SI32_IDAC_A_BUFSTATUS_LEVEL_SHIFT) 350 // The data FIFO contains two words. 351 #define SI32_IDAC_A_BUFSTATUS_LEVEL_2WORDS_VALUE 2 352 #define SI32_IDAC_A_BUFSTATUS_LEVEL_2WORDS_U32 \ 353 (SI32_IDAC_A_BUFSTATUS_LEVEL_2WORDS_VALUE << SI32_IDAC_A_BUFSTATUS_LEVEL_SHIFT) 354 // The data FIFO contains three words. 355 #define SI32_IDAC_A_BUFSTATUS_LEVEL_3WORDS_VALUE 3 356 #define SI32_IDAC_A_BUFSTATUS_LEVEL_3WORDS_U32 \ 357 (SI32_IDAC_A_BUFSTATUS_LEVEL_3WORDS_VALUE << SI32_IDAC_A_BUFSTATUS_LEVEL_SHIFT) 358 // The data FIFO is full and contains four words. 359 #define SI32_IDAC_A_BUFSTATUS_LEVEL_4WORDS_VALUE 4 360 #define SI32_IDAC_A_BUFSTATUS_LEVEL_4WORDS_U32 \ 361 (SI32_IDAC_A_BUFSTATUS_LEVEL_4WORDS_VALUE << SI32_IDAC_A_BUFSTATUS_LEVEL_SHIFT) 362 363 #define SI32_IDAC_A_BUFSTATUS_ORI_MASK 0x00000010 364 #define SI32_IDAC_A_BUFSTATUS_ORI_SHIFT 4 365 // Read: A FIFO overrun has not occurred. Write: Clear the interrupt. 366 #define SI32_IDAC_A_BUFSTATUS_ORI_NOT_SET_VALUE 0 367 #define SI32_IDAC_A_BUFSTATUS_ORI_NOT_SET_U32 \ 368 (SI32_IDAC_A_BUFSTATUS_ORI_NOT_SET_VALUE << SI32_IDAC_A_BUFSTATUS_ORI_SHIFT) 369 // Read: A FIFO overrun occurred. Write: Force a FIFO overrun interrupt. 370 #define SI32_IDAC_A_BUFSTATUS_ORI_SET_VALUE 1 371 #define SI32_IDAC_A_BUFSTATUS_ORI_SET_U32 \ 372 (SI32_IDAC_A_BUFSTATUS_ORI_SET_VALUE << SI32_IDAC_A_BUFSTATUS_ORI_SHIFT) 373 374 #define SI32_IDAC_A_BUFSTATUS_URI_MASK 0x00000020 375 #define SI32_IDAC_A_BUFSTATUS_URI_SHIFT 5 376 // Read: A FIFO underrun has not occurred. Write: Clear the interrupt. 377 #define SI32_IDAC_A_BUFSTATUS_URI_NOT_SET_VALUE 0 378 #define SI32_IDAC_A_BUFSTATUS_URI_NOT_SET_U32 \ 379 (SI32_IDAC_A_BUFSTATUS_URI_NOT_SET_VALUE << SI32_IDAC_A_BUFSTATUS_URI_SHIFT) 380 // Read: A FIFO underrun occurred. Write: Force a FIFO underrun interrupt. 381 #define SI32_IDAC_A_BUFSTATUS_URI_SET_VALUE 1 382 #define SI32_IDAC_A_BUFSTATUS_URI_SET_U32 \ 383 (SI32_IDAC_A_BUFSTATUS_URI_SET_VALUE << SI32_IDAC_A_BUFSTATUS_URI_SHIFT) 384 385 #define SI32_IDAC_A_BUFSTATUS_WEI_MASK 0x00000040 386 #define SI32_IDAC_A_BUFSTATUS_WEI_SHIFT 6 387 // Read: A FIFO went empty condition has not occurred. Write: Clear the interrupt. 388 #define SI32_IDAC_A_BUFSTATUS_WEI_NOT_SET_VALUE 0 389 #define SI32_IDAC_A_BUFSTATUS_WEI_NOT_SET_U32 \ 390 (SI32_IDAC_A_BUFSTATUS_WEI_NOT_SET_VALUE << SI32_IDAC_A_BUFSTATUS_WEI_SHIFT) 391 // Read: The FIFO is empty. Write: Force a FIFO went empty interrupt. 392 #define SI32_IDAC_A_BUFSTATUS_WEI_SET_VALUE 1 393 #define SI32_IDAC_A_BUFSTATUS_WEI_SET_U32 \ 394 (SI32_IDAC_A_BUFSTATUS_WEI_SET_VALUE << SI32_IDAC_A_BUFSTATUS_WEI_SHIFT) 395 396 397 398 struct SI32_IDAC_A_BUFFER10_Struct 399 { 400 union 401 { 402 struct 403 { 404 // FIFO Buffer Entry 0 405 volatile uint16_t BUFFER0; 406 // FIFO Buffer Entry 1 407 volatile uint16_t BUFFER1; 408 }; 409 volatile uint32_t U32; 410 }; 411 }; 412 413 #define SI32_IDAC_A_BUFFER10_BUFFER0_MASK 0x0000FFFF 414 #define SI32_IDAC_A_BUFFER10_BUFFER0_SHIFT 0 415 416 #define SI32_IDAC_A_BUFFER10_BUFFER1_MASK 0xFFFF0000 417 #define SI32_IDAC_A_BUFFER10_BUFFER1_SHIFT 16 418 419 420 421 struct SI32_IDAC_A_BUFFER32_Struct 422 { 423 union 424 { 425 struct 426 { 427 // FIFO Buffer Entry 2 428 volatile uint16_t BUFFER2; 429 // FIFO Buffer Entry 3 430 volatile uint16_t BUFFER3; 431 }; 432 volatile uint32_t U32; 433 }; 434 }; 435 436 #define SI32_IDAC_A_BUFFER32_BUFFER2_MASK 0x0000FFFF 437 #define SI32_IDAC_A_BUFFER32_BUFFER2_SHIFT 0 438 439 #define SI32_IDAC_A_BUFFER32_BUFFER3_MASK 0xFFFF0000 440 #define SI32_IDAC_A_BUFFER32_BUFFER3_SHIFT 16 441 442 443 444 struct SI32_IDAC_A_GAINADJ_Struct 445 { 446 union 447 { 448 struct 449 { 450 // Output Current Gain Adjust 451 volatile uint32_t GAINADJ_BITS: 5; 452 uint32_t reserved0: 27; 453 }; 454 volatile uint32_t U32; 455 }; 456 }; 457 458 #define SI32_IDAC_A_GAINADJ_GAINADJ_MASK 0x0000001F 459 #define SI32_IDAC_A_GAINADJ_GAINADJ_SHIFT 0 460 461 462 463 typedef struct SI32_IDAC_A_Struct 464 { 465 struct SI32_IDAC_A_CONTROL_Struct CONTROL ; // Base Address + 0x0 466 volatile uint32_t CONTROL_SET; 467 volatile uint32_t CONTROL_CLR; 468 uint32_t reserved0; 469 struct SI32_IDAC_A_DATA_Struct DATA ; // Base Address + 0x10 470 uint32_t reserved1; 471 uint32_t reserved2; 472 uint32_t reserved3; 473 struct SI32_IDAC_A_BUFSTATUS_Struct BUFSTATUS ; // Base Address + 0x20 474 volatile uint32_t BUFSTATUS_SET; 475 volatile uint32_t BUFSTATUS_CLR; 476 uint32_t reserved4; 477 struct SI32_IDAC_A_BUFFER10_Struct BUFFER10 ; // Base Address + 0x30 478 uint32_t reserved5; 479 uint32_t reserved6; 480 uint32_t reserved7; 481 struct SI32_IDAC_A_BUFFER32_Struct BUFFER32 ; // Base Address + 0x40 482 uint32_t reserved8; 483 uint32_t reserved9; 484 uint32_t reserved10; 485 struct SI32_IDAC_A_GAINADJ_Struct GAINADJ ; // Base Address + 0x50 486 uint32_t reserved11; 487 uint32_t reserved12; 488 uint32_t reserved13; 489 } SI32_IDAC_A_Type; 490 491 #ifdef __cplusplus 492 } 493 #endif 494 495 #endif // __SI32_IDAC_A_REGISTERS_H__ 496 497 //-eof-------------------------------------------------------------------------- 498 499
